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1.1 root 1: % 0: bit 0
2: % 1: bit 1
3: % c: condition code
4: % C: condition codes, except F
5: % f: direction
6: % i: immediate
7: % I: immediate, except 00 and ff
8: % j: immediate 1..8
9: % J: immediate 0..15
10: % k: immediate 0..7
11: % K: immediate 0..63
12: % p: immediate 0..3 (CINV and CPUSH: cache field)
13: % s: source mode
14: % S: source reg
15: % d: dest mode
16: % D: dest reg
17: % r: reg
18: % z: size
19: %
20: % Actually, a sssSSS may appear as a destination, and
21: % vice versa. The only difference between sssSSS and
22: % dddDDD are the valid addressing modes. There is
23: % no match for immediate and pc-rel. addressing modes
24: % in case of dddDDD.
25: %
26: % Arp: --> -(Ar)
27: % ArP: --> (Ar)+
28: % Ara: --> (Ar)
29: % L: (xxx.L)
30: %
31: % Fields on a line:
32: % 16 chars bitpattern :
33: % CPU level / privilege level :
34: % CPU level 0: 68000
35: % 1: 68010
36: % 2: 68020
37: % 3: 68030
38: % 4: 68040
39: % 5: 68060 (not used to produce a cputbl)
40: % [Everything from 68020 possibly allows for FPU emulation]
41: % privilege level 0: not privileged
42: % 1: unprivileged only on 68000 (check regs.s)
43: % 2: privileged (check regs.s)
44: % 3: privileged if size == word (check regs.s)
45: % Flags set by instruction: XNZVC :
46: % Flags used by instruction: XNZVC :
47: % - means flag unaffected / unused
48: % 0 means flag reset
49: % 1 means flag set
50: % ? means programmer was too lazy to check or instruction may trap
51: % + means instruction is conditional branch
52: % everything else means flag set/used
53: % / means instruction is unconditional branch/call
54: % x means flag is unknown and well-behaved programs shouldn't check it
55: % srcaddr status destaddr status :
56: % bitmasks of
57: % 1 means fetched
58: % 2 means stored
59: % 4 means jump offset
60: % 8 means jump address
61: % instruction
62: %
63:
64: 0000 0000 0011 1100:00:XNZVC:XNZVC:10: ORSR.B #1
65: 0000 0000 0111 1100:02:?????:?????:10: ORSR.W #1
66: 0000 0zz0 11ss sSSS:20:?????:?????:11: CHK2.z #1,s[!Dreg,Areg,Aipi,Apdi,Immd]
67: 0000 0000 zzdd dDDD:00:-NZ00:-----:13: OR.z #z,d[!Areg]
68: 0000 0010 0011 1100:00:XNZVC:XNZVC:10: ANDSR.B #1
69: 0000 0010 0111 1100:02:?????:?????:10: ANDSR.W #1
70: 0000 0010 zzdd dDDD:00:-NZ00:-----:13: AND.z #z,d[!Areg]
71: 0000 0100 zzdd dDDD:00:XNZVC:-----:13: SUB.z #z,d[!Areg]
72: 0000 0110 zzdd dDDD:00:XNZVC:-----:13: ADD.z #z,d[!Areg]
73: 0000 0110 11ss sSSS:20:?????:?????:10: CALLM s[!Dreg,Areg,Aipi,Apdi,Immd]
74: 0000 0110 11ss sSSS:20:?????:?????:10: RTM s[Dreg,Areg]
75: 0000 1000 00ss sSSS:00:--Z--:-----:11: BTST #1,s[!Areg]
1.1.1.3 ! root 76: 0000 1000 01ss sSSS:00:--Z--:-----:13: BCHG #1,s[!Areg,Immd,PC8r,PC16]
! 77: 0000 1000 10ss sSSS:00:--Z--:-----:13: BCLR #1,s[!Areg,Immd,PC8r,PC16]
! 78: 0000 1000 11ss sSSS:00:--Z--:-----:13: BSET #1,s[!Areg,Immd,PC8r,PC16]
1.1 root 79: 0000 1010 0011 1100:00:XNZVC:XNZVC:10: EORSR.B #1
80: 0000 1010 0111 1100:02:?????:?????:10: EORSR.W #1
81: 0000 1010 zzdd dDDD:00:-NZ00:-----:13: EOR.z #z,d[!Areg]
82: 0000 1100 zzss sSSS:00:-NZVC:-----:11: CMP.z #z,s[!Areg,Immd]
83:
84: 0000 1010 11ss sSSS:20:?????:?????:13: CAS.B #1,s[!Dreg,Areg,Immd,PC8r,PC16]
85: 0000 1100 11ss sSSS:20:?????:?????:13: CAS.W #1,s[!Dreg,Areg,Immd,PC8r,PC16]
86: 0000 1100 1111 1100:20:?????:?????:10: CAS2.W #2
87: 0000 1110 zzss sSSS:22:?????:?????:13: MOVES.z #1,s[!Dreg,Areg,Immd,PC8r,PC16]
88: 0000 1110 11ss sSSS:20:?????:?????:13: CAS.L #1,s[!Dreg,Areg,Immd,PC8r,PC16]
89: 0000 1110 1111 1100:20:?????:?????:10: CAS2.L #2
90:
91: 0000 rrr1 00dd dDDD:00:-----:-----:12: MVPMR.W d[Areg-Ad16],Dr
92: 0000 rrr1 01dd dDDD:00:-----:-----:12: MVPMR.L d[Areg-Ad16],Dr
93: 0000 rrr1 10dd dDDD:00:-----:-----:12: MVPRM.W Dr,d[Areg-Ad16]
94: 0000 rrr1 11dd dDDD:00:-----:-----:12: MVPRM.L Dr,d[Areg-Ad16]
95: 0000 rrr1 00ss sSSS:00:--Z--:-----:11: BTST Dr,s[!Areg]
1.1.1.3 ! root 96: 0000 rrr1 01ss sSSS:00:--Z--:-----:13: BCHG Dr,s[!Areg,Immd,PC8r,PC16]
! 97: 0000 rrr1 10ss sSSS:00:--Z--:-----:13: BCLR Dr,s[!Areg,Immd,PC8r,PC16]
! 98: 0000 rrr1 11ss sSSS:00:--Z--:-----:13: BSET Dr,s[!Areg,Immd,PC8r,PC16]
1.1 root 99:
100: 0001 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.B s,d[!Areg]
101: 0010 DDDd ddss sSSS:00:-----:-----:12: MOVEA.L s,d[Areg]
102: 0010 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.L s,d[!Areg]
103: 0011 DDDd ddss sSSS:00:-----:-----:12: MOVEA.W s,d[Areg]
104: 0011 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.W s,d[!Areg]
105:
106: 0100 0000 zzdd dDDD:00:XxZxC:X-Z--:30: NEGX.z d[!Areg]
107: 0100 0000 11dd dDDD:01:?????:?????:10: MVSR2.W d[!Areg]
108: 0100 0010 zzdd dDDD:00:-0100:-----:20: CLR.z d[!Areg]
109: 0100 0010 11dd dDDD:10:?????:?????:10: MVSR2.B d[!Areg]
110: 0100 0100 zzdd dDDD:00:XNZVC:-----:30: NEG.z d[!Areg]
111: 0100 0100 11ss sSSS:00:XNZVC:-----:10: MV2SR.B s[!Areg]
112: 0100 0110 zzdd dDDD:00:-NZ00:-----:30: NOT.z d[!Areg]
113: 0100 0110 11ss sSSS:02:?????:?????:10: MV2SR.W s[!Areg]
114: 0100 1000 0000 1rrr:20:-----:-----:31: LINK.L Ar,#2
115: 0100 1000 00dd dDDD:00:X?Z?C:X-Z--:30: NBCD.B d[!Areg]
116: 0100 1000 0100 1kkk:20:?????:?????:10: BKPT #k
117: 0100 1000 01ss sSSS:00:-NZ00:-----:30: SWAP.W s[Dreg]
118: 0100 1000 01ss sSSS:00:-----:-----:00: PEA.L s[!Dreg,Areg,Aipi,Apdi,Immd]
119: 0100 1000 10dd dDDD:00:-NZ00:-----:30: EXT.W d[Dreg]
120: 0100 1000 10dd dDDD:00:-----:-----:02: MVMLE.W #1,d[!Dreg,Areg,Aipi]
121: 0100 1000 11dd dDDD:00:-NZ00:-----:30: EXT.L d[Dreg]
122: 0100 1000 11dd dDDD:00:-----:-----:02: MVMLE.L #1,d[!Dreg,Areg,Aipi]
123: 0100 1001 11dd dDDD:20:-NZ00:-----:30: EXT.B d[Dreg]
124: 0100 1010 zzss sSSS:00:-NZ00:-----:10: TST.z s
125: 0100 1010 11dd dDDD:00:?????:?????:30: TAS.B d[!Areg]
126: 0100 1010 1111 1100:00:?????:?????:00: ILLEGAL
127: 0100 1100 00ss sSSS:20:-NZVC:-----:13: MULL.L #1,s[!Areg]
128: 0100 1100 01ss sSSS:20:?????:?????:13: DIVL.L #1,s[!Areg]
129: 0100 1100 10ss sSSS:00:-----:-----:01: MVMEL.W #1,s[!Dreg,Areg,Apdi,Immd]
130: 0100 1100 11ss sSSS:00:-----:-----:01: MVMEL.L #1,s[!Dreg,Areg,Apdi,Immd]
131: 0100 1110 0100 JJJJ:00:-----:XNZVC:10: TRAP #J
132: 0100 1110 0101 0rrr:00:-----:-----:31: LINK.W Ar,#1
133: 0100 1110 0101 1rrr:00:-----:-----:30: UNLK.L Ar
134: 0100 1110 0110 0rrr:02:-----:-----:10: MVR2USP.L Ar
135: 0100 1110 0110 1rrr:02:-----:-----:20: MVUSP2R.L Ar
136: 0100 1110 0111 0000:02:-----:-----:00: RESET
137: 0100 1110 0111 0001:00:-----:-----:00: NOP
138: 0100 1110 0111 0010:02:XNZVC:-----:10: STOP #1
139: 0100 1110 0111 0011:02:XNZVC:-----:00: RTE
140: 0100 1110 0111 0100:00:?????:?????:10: RTD #1
141: 0100 1110 0111 0101:00:-----:-----:00: RTS
142: 0100 1110 0111 0110:00:-----:XNZVC:00: TRAPV
143: 0100 1110 0111 0111:00:XNZVC:-----:00: RTR
144: 0100 1110 0111 1010:12:?????:?????:10: MOVEC2 #1
145: 0100 1110 0111 1011:12:?????:?????:10: MOVE2C #1
146: 0100 1110 10ss sSSS:00://///://///:80: JSR.L s[!Dreg,Areg,Aipi,Apdi,Immd]
147: 0100 rrr1 00ss sSSS:20:?????:?????:11: CHK.L s[!Areg],Dr
148: 0100 rrr1 10ss sSSS:00:?????:?????:11: CHK.W s[!Areg],Dr
149: 0100 1110 11ss sSSS:00://///://///:80: JMP.L s[!Dreg,Areg,Aipi,Apdi,Immd]
150: 0100 rrr1 11ss sSSS:00:-----:-----:02: LEA.L s[!Dreg,Areg,Aipi,Apdi,Immd],Ar
151:
152: 0101 jjj0 01dd dDDD:00:-----:-----:13: ADDA.W #j,d[Areg]
153: 0101 jjj0 10dd dDDD:00:-----:-----:13: ADDA.L #j,d[Areg]
154: 0101 jjj0 zzdd dDDD:00:XNZVC:-----:13: ADD.z #j,d[!Areg]
155: 0101 jjj1 01dd dDDD:00:-----:-----:13: SUBA.W #j,d[Areg]
156: 0101 jjj1 10dd dDDD:00:-----:-----:13: SUBA.L #j,d[Areg]
157: 0101 jjj1 zzdd dDDD:00:XNZVC:-----:13: SUB.z #j,d[!Areg]
158: 0101 cccc 1100 1rrr:00:-----:-++++:31: DBcc.W Dr,#1
159: 0101 cccc 11dd dDDD:00:-----:-++++:20: Scc.B d[!Areg]
160: 0101 cccc 1111 1010:20:?????:?????:10: TRAPcc #1
161: 0101 cccc 1111 1011:20:?????:?????:10: TRAPcc #2
162: 0101 cccc 1111 1100:20:?????:?????:00: TRAPcc
163:
164: % Bxx.L is 68020 only, but setting the CPU level to 2 would give illegal
165: % instruction exceptions when compiling a 68000 only emulation, which isn't
166: % what we want either.
167: 0110 0001 0000 0000:00://///://///:40: BSR.W #1
168: 0110 0001 IIII IIII:00://///://///:40: BSR.B #i
169: 0110 0001 1111 1111:00://///://///:40: BSR.L #2
170: 0110 CCCC 0000 0000:00:-----:-++++:40: Bcc.W #1
171: 0110 CCCC IIII IIII:00:-----:-++++:40: Bcc.B #i
172: 0110 CCCC 1111 1111:00:-----:-++++:40: Bcc.L #2
173:
174: 0111 rrr0 iiii iiii:00:-NZ00:-----:12: MOVE.L #i,Dr
175:
176: 1000 rrr0 zzss sSSS:00:-NZ00:-----:13: OR.z s[!Areg],Dr
177: 1000 rrr0 11ss sSSS:00:?????:?????:13: DIVU.W s[!Areg],Dr
178: 1000 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: SBCD.B d[Dreg],Dr
179: 1000 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: SBCD.B d[Areg-Apdi],Arp
180: 1000 rrr1 zzdd dDDD:00:-NZ00:-----:13: OR.z Dr,d[!Areg,Dreg]
181: 1000 rrr1 01dd dDDD:20:?????:?????:12: PACK d[Dreg],Dr
182: 1000 rrr1 01dd dDDD:20:?????:?????:12: PACK d[Areg-Apdi],Arp
183: 1000 rrr1 10dd dDDD:20:?????:?????:12: UNPK d[Dreg],Dr
184: 1000 rrr1 10dd dDDD:20:?????:?????:12: UNPK d[Areg-Apdi],Arp
185: 1000 rrr1 11ss sSSS:00:?????:?????:13: DIVS.W s[!Areg],Dr
186:
187: 1001 rrr0 zzss sSSS:00:XNZVC:-----:13: SUB.z s,Dr
188: 1001 rrr0 11ss sSSS:00:-----:-----:13: SUBA.W s,Ar
189: 1001 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: SUBX.z d[Dreg],Dr
190: 1001 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: SUBX.z d[Areg-Apdi],Arp
191: 1001 rrr1 zzdd dDDD:00:XNZVC:-----:13: SUB.z Dr,d[!Areg,Dreg]
192: 1001 rrr1 11ss sSSS:00:-----:-----:13: SUBA.L s,Ar
193:
194: 1011 rrr0 zzss sSSS:00:-NZVC:-----:11: CMP.z s,Dr
195: 1011 rrr0 11ss sSSS:00:-NZVC:-----:11: CMPA.W s,Ar
196: 1011 rrr1 11ss sSSS:00:-NZVC:-----:11: CMPA.L s,Ar
197: 1011 rrr1 zzdd dDDD:00:-NZVC:-----:11: CMPM.z d[Areg-Aipi],ArP
198: 1011 rrr1 zzdd dDDD:00:-NZ00:-----:13: EOR.z Dr,d[!Areg]
199:
200: 1100 rrr0 zzss sSSS:00:-NZ00:-----:13: AND.z s[!Areg],Dr
201: 1100 rrr0 11ss sSSS:00:-NZ00:-----:13: MULU.W s[!Areg],Dr
202: 1100 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: ABCD.B d[Dreg],Dr
203: 1100 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: ABCD.B d[Areg-Apdi],Arp
204: 1100 rrr1 zzdd dDDD:00:-NZ00:-----:13: AND.z Dr,d[!Areg,Dreg]
205: 1100 rrr1 01dd dDDD:00:-----:-----:33: EXG.L Dr,d[Dreg]
206: 1100 rrr1 01dd dDDD:00:-----:-----:33: EXG.L Ar,d[Areg]
207: 1100 rrr1 10dd dDDD:00:-----:-----:33: EXG.L Dr,d[Areg]
208: 1100 rrr1 11ss sSSS:00:-NZ00:-----:13: MULS.W s[!Areg],Dr
209:
210: 1101 rrr0 zzss sSSS:00:XNZVC:-----:13: ADD.z s,Dr
211: 1101 rrr0 11ss sSSS:00:-----:-----:13: ADDA.W s,Ar
212: 1101 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: ADDX.z d[Dreg],Dr
213: 1101 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: ADDX.z d[Areg-Apdi],Arp
214: 1101 rrr1 zzdd dDDD:00:XNZVC:-----:13: ADD.z Dr,d[!Areg,Dreg]
215: 1101 rrr1 11ss sSSS:00:-----:-----:13: ADDA.L s,Ar
216:
217: 1110 jjjf zz00 0RRR:00:XNZVC:-----:13: ASf.z #j,DR
218: 1110 jjjf zz00 1RRR:00:XNZ0C:-----:13: LSf.z #j,DR
219: 1110 jjjf zz01 0RRR:00:XNZ0C:X----:13: ROXf.z #j,DR
220: 1110 jjjf zz01 1RRR:00:-NZ0C:-----:13: ROf.z #j,DR
221: 1110 rrrf zz10 0RRR:00:XNZVC:X----:13: ASf.z Dr,DR
222: 1110 rrrf zz10 1RRR:00:XNZ0C:X----:13: LSf.z Dr,DR
223: 1110 rrrf zz11 0RRR:00:XNZ0C:X----:13: ROXf.z Dr,DR
224: 1110 rrrf zz11 1RRR:00:-NZ0C:-----:13: ROf.z Dr,DR
225: 1110 000f 11dd dDDD:00:XNZVC:-----:13: ASfW.W d[!Dreg,Areg]
226: 1110 001f 11dd dDDD:00:XNZ0C:-----:13: LSfW.W d[!Dreg,Areg]
227: 1110 010f 11dd dDDD:00:XNZ0C:X----:13: ROXfW.W d[!Dreg,Areg]
228: 1110 011f 11dd dDDD:00:-NZ0C:-----:13: ROfW.W d[!Dreg,Areg]
229:
230: 1110 1000 11ss sSSS:20:?????:?????:11: BFTST #1,s[!Areg,Apdi,Aipi,Immd]
231: 1110 1001 11ss sSSS:20:?????:?????:11: BFEXTU #1,s[!Areg,Apdi,Aipi,Immd]
232: 1110 1010 11ss sSSS:20:?????:?????:13: BFCHG #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
233: 1110 1011 11ss sSSS:20:?????:?????:11: BFEXTS #1,s[!Areg,Apdi,Aipi,Immd]
234: 1110 1100 11ss sSSS:20:?????:?????:13: BFCLR #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
235: 1110 1101 11ss sSSS:20:?????:?????:11: BFFFO #1,s[!Areg,Apdi,Aipi,Immd]
236: 1110 1110 11ss sSSS:20:?????:?????:13: BFSET #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
237: 1110 1111 11ss sSSS:20:?????:?????:13: BFINS #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
238:
239: % floating point co processor
240: 1111 0010 00ss sSSS:20:?????:?????:11: FPP #1,s
241: 1111 0010 01ss sSSS:20:?????:?????:11: FDBcc #1,s[Areg-Dreg]
242: 1111 0010 01ss sSSS:20:?????:?????:11: FScc #1,s[!Areg,Immd,PC8r,PC16]
243: 1111 0010 0111 1010:20:?????:?????:10: FTRAPcc #1
244: 1111 0010 0111 1011:20:?????:?????:10: FTRAPcc #2
245: 1111 0010 0111 1100:20:?????:?????:00: FTRAPcc
246: 1111 0010 10KK KKKK:20:?????:?????:11: FBcc #K,#1
247: 1111 0010 11KK KKKK:20:?????:?????:11: FBcc #K,#2
248: 1111 0011 00ss sSSS:22:?????:?????:20: FSAVE s[!Dreg,Areg,Aipi,Immd,PC8r,PC16]
249: 1111 0011 01ss sSSS:22:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd]
250:
251: % 68030 MMU (allowed addressing modes not checked!)
1.1.1.2 root 252: 1111 0000 00ss sSSS:32:?????:?????:11: MMUOP030 s[Dreg,Areg,Aind,Ad16,Ad8r,absl,absw],#1
1.1 root 253:
254: % 68040/68060 instructions
255: 1111 0100 pp00 1rrr:42:-----:-----:02: CINVL #p,Ar
256: 1111 0100 pp01 0rrr:42:-----:-----:02: CINVP #p,Ar
257: 1111 0100 pp01 1rrr:42:-----:-----:00: CINVA #p
258: 1111 0100 pp10 1rrr:42:-----:-----:02: CPUSHL #p,Ar
259: 1111 0100 pp11 0rrr:42:-----:-----:02: CPUSHP #p,Ar
260: 1111 0100 pp11 1rrr:42:-----:-----:00: CPUSHA #p
261: 1111 0101 0000 0rrr:42:-----:-----:00: PFLUSHN Ara
262: 1111 0101 0000 1rrr:42:-----:-----:00: PFLUSH Ara
263: 1111 0101 0001 0rrr:42:-----:-----:00: PFLUSHAN Ara
264: 1111 0101 0001 1rrr:42:-----:-----:00: PFLUSHA Ara
265: 1111 0101 0100 1rrr:42:-----:-----:00: PTESTR Ara
266: 1111 0101 0110 1rrr:42:-----:-----:00: PTESTW Ara
267:
268: % destination register number is encoded in the following word
269: 1111 0110 0010 0rrr:40:-----:-----:12: MOVE16 ArP,AxP
270: 1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Dreg-Aipi],L
271: 1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 L,d[Areg-Aipi]
272: 1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Aind],L
273: 1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 L,d[Aipi-Aind]
274:
275: % 68060
276: 1111 1000 0000 0000:52:?????:?????:10: LPSTOP #1
277: 1111 0101 1000 1rrr:52:-----:-----:00: PLPAR Ara
278: 1111 0101 1100 1rrr:52:-----:-----:00: PLPAW Ara
279:
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