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1.1 root 1: /***
2: * 68k disassembler, written 2010 by Markus Fritze, www.sarnau.com
3: *
4: * This file is distributed under the GNU Public License, version 2 or at
5: * your option any later version. Read the file gpl.txt for details.
6: ***/
7:
8: #include <stdio.h>
9: #include <ctype.h>
10: #include <strings.h>
11: #include <stdlib.h>
12:
13: #include "config.h"
14: #include "sysdeps.h"
15: #include "main.h"
16: #include "newcpu.h"
17: #include "paths.h"
1.1.1.3 ! root 18: #include "profile.h"
1.1 root 19: #include "tos.h"
20: #include "68kDisass.h"
21:
22: #define ADDRESS_ON_PC 1
23: #define USE_SYMBOLS 1
24:
25: typedef enum {
26: doptNoBrackets = 1, // hide brackets around absolute addressing
27: doptOpcodesSmall = 2, // opcodes are small letters
28: doptRegisterSmall = 4, // register names are small letters
29: doptStackSP = 8, // stack pointer is named "SP" instead of "A7" (except for MOVEM)
30: } Diss68kOptions;
31:
32: static Diss68kOptions options = doptOpcodesSmall | doptRegisterSmall | doptStackSP | doptNoBrackets;
33:
34: // values <0 will hide the group
1.1.1.3 ! root 35: static const int optionPosAddress = 0; // current address
! 36: static const int optionPosHexdump = 10; // 16-bit words at this address
! 37: static const int optionPosLabel = 35; // label, if defined
! 38: static const int optionPosOpcode = 47; // opcode
! 39: static const int optionPosOperand = 57; // operands for the opcode
! 40: static const int optionPosComment = 82; // comment, if defined
1.1 root 41:
42: /***
43: * Motorola 16-/32-Bit Microprocessor and coprocessor types
44: ***/
45: #define MC68000 0x000001 // 16-/32-Bit Microprocessor
46: #define MC68EC000 0x000002 // 16-/32-Bit Embedded Controller
47: #define MC68HC000 0x000004 // Low Power 16-/32-Bit Microprocessor
48: #define MC68008 0x000008 // 16-Bit Microprocessor with 8-Bit Data Bus
49: #define MC68010 0x000010 // 16-/32-Bit Virtual Memory Microprocessor
50: #define MC68020 0x000020 // 32-Bit Virtual Memory Microprocessor
51: #define MC68EC020 0x000040 // 32-Bit Embedded Controller (no PMMU)
52: #define MC68030 0x000080 // Second-Generation 32-Bit Enhanced Microprocessor
53: #define MC68EC030 0x000100 // 32-Bit Embedded Controller (no PMMU)
54: #define MC68040 0x000200 // Third-Generation 32-Bit Microprocessor
55: #define MC68LC040 0x000400 // Third-Generation 32-Bit Microprocessor (no FPU)
56: #define MC68EC040 0x000800 // 32-Bit Embedded Controller (no FPU, no PMMU)
57: #define MC68330 0x001000 // CPU32 Integrated CPU32 Processor
58: #define MC68340 0x002000 // CPU32 Integrated Processor with DMA
59: #define MC68060 0x004000 // Fourth-Generation 32-Bit Microprocessor
60: #define MC68LC060 0x008000 // Fourth-Generation 32-Bit Microprocessor (no FPU)
61: #define MC68EC060 0x010000 // Fourth-Generation 32-Bit Microprocessor (no FPU, no PMMU)
62: #define MC_CPU32 (MC68330|MC68340)
63:
64: #define MC_020 (MC68020|MC68EC020|MC68030|MC68EC030|MC68040|MC68LC040|MC68EC040|MC_CPU32|MC68060|MC68LC060|MC68EC060)
65: #define MC_ALL (MC68000|MC68EC000|MC68HC000|MC68008|MC68010|MC_020)
66:
67: #define MC68851 0x020000 // Paged Memory Management Unit
68:
69: #define MC68881 0x040000 // Floating-PointCoprocessor
70: #define MC68882 0x080000 // Enhanced Floating-Point Coprocessor
71:
72: #define MC_PMMU (MC68881|MC68882)
73: #define MC_FPU (MC68881|MC68882)
74:
75: static int optionCPUTypeMask = ( MC_ALL & ~MC68040 & ~MC_CPU32 & ~MC68060 ) | MC_PMMU | MC_FPU;
76:
77:
78: typedef enum {
79: dtNone,
80: dtByte, // a specific number of bytes, usually 1
81: dtWord, // one 16-bit value
82: dtLong, // one 32-bit value
83: dtOpcode, // an opcode of variable length
84: dtASCString, // a 0-byte terminated ASCII string
85: dtPointer, // a generic 32-bit pointer
86: dtFunctionPointer, // a 32-bit pointer to a function
87: dtStringArray, // a specific number of ASCII bytes
88: } Disass68kDataType;
89:
90: typedef struct {
91: char *name;
92: char *comment;
93: Disass68kDataType type;
94: int size;
95: } disStructElement;
96:
97: typedef struct {
98: char *name; // name of the structure
99: int size; // size of structure
100: int count; // number of lines
101: disStructElement *elements; // array of all elements of the struct
102: } disStructEntry;
103:
104: static int disStructCounts;
105: static disStructEntry *disStructEntries;
106:
107: typedef struct {
108: long addr; // address of the label
109: Disass68kDataType type; // type of the data on the address
110: int size; // size of the label, references inside it are addressed via base address + offset
111: int count; // number of elements at this address with the given size
112: int structIndex; // -1 no struct to describe the element
113: char *name; // name of the label
114: char *comment; // optional comment
115: } disSymbolEntry;
116:
117: static int disSymbolCounts;
118: static disSymbolEntry *disSymbolEntries;
119:
120:
121: static inline unsigned short Disass68kGetWord(long addr)
122: {
123: return get_word(addr);
124: }
125:
126: // Load a text file into memory, count the lines and replace the LF with 0-bytes.
127: static int Disass68kLoadTextFile(const char *filename, char **filebuf)
128: {
129: long index;
130:
131: if(filebuf)
132: *filebuf = NULL;
133: FILE *f = fopen(filename, "r");
134: if(!f) return 0;
135: if(fseek(f, 0, SEEK_END))
136: return 0;
137: long fileLength = ftell(f);
138: if(!fileLength) return 0;
139: if(fseek(f, 0, SEEK_SET))
140: return 0;
141: char *fbuf = malloc(fileLength);
142: if(!fbuf) return 0;
143: if((size_t)fileLength != fread(fbuf, sizeof(char), fileLength, f))
144: return 0;
145: int lineCount = 0;
146: for(index=0; index<fileLength; ++index)
147: {
148: if(fbuf[index] == '\r') // convert potential CR into a space (which we ignore at the end of the line anyway)
149: fbuf[index] = ' ';
150: if(fbuf[index] == '\n') // count LF and terminate line
151: {
152: ++lineCount;
153: fbuf[index] = 0;
154: }
155: }
156: if(filebuf)
157: *filebuf = fbuf;
158: return lineCount;
159: }
160:
161: static void Disass68kLoadStructInfo(const char *filename)
162: {
163: char *fbuf = NULL;
164: int lineCount = Disass68kLoadTextFile(filename, &fbuf);
165: if(!lineCount) { if(fbuf) free(fbuf); return; }
166: disStructEntry *se = NULL;
167: disStructEntries = realloc(disStructEntries, sizeof(disStructEntry) * (disStructCounts + lineCount));
168: if(!disStructEntries) { free(fbuf); return; }
169: char *line = fbuf;
170: char *nextLine;
171: int i,j;
172:
173: for(i=0; i<lineCount; line = nextLine, ++i)
174: {
175: // strip spaces at the end of the line, remember the ptr to the next line
176: char *sp = line;
177: while(*sp++)
178: ;
179: nextLine = sp--;
180: while(isspace(*--sp))
181: *sp = 0;
182:
183: if(line[0] == '{')
184: {
185: se = &disStructEntries[disStructCounts];
186: se->name = strdup(line+1);
187: se->count = 0;
188: se->elements = malloc(sizeof(disStructElement) * lineCount); // lineCount is way too much, but safe
189: } else if(line[0] == '}') {
190: if(se)
191: {
192: se->size = 0;
193: for(j=0; j<se->count; ++j)
194: se->size += se->elements[j].size;
195: // printf("%s : %d bytes\n", se->name, se->size);
196: ++disStructCounts;
197: se = NULL;
198: }
199: } else if(line[0] == '#') {
200: disStructElement dse;
201: int val = 0;
202: int index = 2;
203: if(line[1] == 'A' || line[1] == 'B')
204: {
205: for(; isdigit(line[index]); ++index)
206: {
207: val *= 10;
208: val += line[index] - '0';
209: }
210: }
211: if(val == 0) val = 1;
212: dse.name = NULL;
213: switch(line[1])
214: {
215: case 'A': dse.type = dtStringArray; dse.size = val; dse.name = strdup(line + index + 1); break;
216: case 'B': dse.type = dtByte; dse.size = val; break;
217: case 'W': dse.type = dtWord; dse.size = 2; break;
218: case 'L': dse.type = dtLong; dse.size = 4; break;
219: case 'C': dse.type = dtOpcode; dse.size = 2; break;
220: case 'f': dse.type = dtFunctionPointer; dse.size = 4; break;
221: case 'p': dse.type = dtPointer; dse.size = 4; break;
222: default: dse.type = dtNone; dse.size = 0;
223: printf("Unknown type in \"%s\"\n", line); break;
224: }
225: if(!dse.name)
226: dse.name = strdup(line+3);
227: dse.comment = NULL;
228: if(se)
229: se->elements[se->count++] = dse;
230: }
231: }
232: free(fbuf);
233: }
234:
235: static void Disass68kLoadSymbols(const char *filename)
236: {
237: char *fbuf = NULL;
238: int lineCount = Disass68kLoadTextFile(filename, &fbuf);
239: if(!lineCount) { if(fbuf) free(fbuf); return; }
240: disSymbolEntries = realloc(disSymbolEntries, sizeof(disSymbolEntry) * (disSymbolCounts + lineCount));
241: if(!disSymbolEntries) { free(fbuf); return; }
242: char *line = fbuf;
243: char *nextLine;
244: int i,j;
245:
246: for(i=0; i<lineCount; line = nextLine, ++i)
247: {
248: // strip spaces at the end of the line, remember the ptr to the next line
249: char *sp = line;
250: while(*sp++)
251: ;
252: nextLine = sp--;
253: while(isspace(*--sp))
254: *sp = 0;
255:
256: // ignore empty lines
257: if(line[0] == 0)
258: continue;
259:
260: long addr;
261: sscanf(line, "%lx",&addr);
262: disSymbolEntries[disSymbolCounts].addr = addr;
263: disSymbolEntries[disSymbolCounts].structIndex = -1;
264:
265: char *parameterPtr[10];
266: int parameterCount = 0;
267: char *str = line;
268: do {
269: str = strchr(str, ',');
270: if(str)
271: {
272: char *ep = str;
273: while(isspace(*--ep))
274: *ep = 0;
275: *str++ = 0;
276: while(*str && isspace(*str))
277: ++str;
278: parameterPtr[parameterCount++] = str;
279: }
280: } while(str != NULL && parameterCount < 10);
281:
282: if(parameterCount != 3 && parameterCount != 4)
283: continue; // ignore line
284:
285: long size = 0;
286: int type = 0;
287: if(strlen(parameterPtr[0]) == 1)
288: {
289: switch(parameterPtr[0][0])
290: {
291: case 'A': type = dtASCString; size = 1; break; // ascii NULL
292: case 'B': type = dtByte; size = 1; break; // byte
293: case 'W': type = dtWord; size = 2; break; // word
294: case 'L': type = dtLong; size = 4; break; // long
295: case 'C': type = dtOpcode; size = 2; break; // code
296: case 'f': type = dtFunctionPointer; size = 4; break; // function pointer
297: case 'p': type = dtPointer; size = 4; break; // regular pointer
298: default: printf("ERROR: $%lx : %s\n", addr, parameterPtr[0]); continue;
299: }
300: } else {
301: for(j=0; j<disStructCounts; ++j)
302: {
303: disStructEntry *se = &disStructEntries[j];
304: if(se->name == NULL)
305: break;
306: if(strcmp(parameterPtr[0], se->name))
307: continue;
308: size = se->size;
309: disSymbolEntries[disSymbolCounts].structIndex = j;
310: }
311: }
312: if(!size)
313: continue;
314:
315: disSymbolEntries[disSymbolCounts].type = type;
316: disSymbolEntries[disSymbolCounts].size = size;
317: disSymbolEntries[disSymbolCounts].count = atol(parameterPtr[1]);
318: disSymbolEntries[disSymbolCounts].name = strdup(parameterPtr[2]);
319: disSymbolEntries[disSymbolCounts].comment = NULL;
320: if(parameterCount == 4)
321: disSymbolEntries[disSymbolCounts].comment = strdup(parameterPtr[3]);
322: ++disSymbolCounts;
323: }
324: free(fbuf);
325: }
326:
327: static void Disass68kInit(const char *baseDirectory)
328: {
1.1.1.2 root 329: char filename[FILENAME_MAX];
1.1 root 330:
331: disStructCounts = 0;
332: sprintf(filename, "%s/DisassStructs.txt", baseDirectory);
333: Disass68kLoadStructInfo(filename);
334: sprintf(filename, "%s/DisassStructs_%4.4X.txt", baseDirectory, TosVersion);
335: Disass68kLoadStructInfo(filename);
336:
337: disSymbolCounts = 0;
338: sprintf(filename, "%s/DisassSymbols.txt", baseDirectory);
339: Disass68kLoadSymbols(filename);
340: sprintf(filename, "%s/DisassSymbols_%4.4X.txt", baseDirectory, TosVersion);
341: Disass68kLoadSymbols(filename);
342: }
343:
344:
345:
346: static Disass68kDataType Disass68kType(long addr, char *addressLabel, char *commentBuffer, int *count)
347: {
348: int i,j;
349:
350: addressLabel[0] = 0;
351: commentBuffer[0] = 0;
352: for(i=0; i<disSymbolCounts; ++i)
353: {
354: const disSymbolEntry *dse = &disSymbolEntries[i];
355: int offset = addr - dse->addr;
356: if(offset < 0 || offset >= dse->count * dse->size)
357: continue;
358:
359: // no special struct that devices this value?
360: if(dse->structIndex < 0)
361: {
362: offset = (offset + dse->size - 1) / dse->size;
363: *count = dse->count - offset;
364: if(offset == 0) // only in the first line
365: {
366: strcpy(addressLabel, dse->name);
367: if(dse->comment)
368: strcpy(commentBuffer, dse->comment);
369: }
370: return dse->type;
371: }
372:
373: *count = 1;
374: const disStructEntry *se = &disStructEntries[dse->structIndex];
375: for(j=0; j<se->count; ++j)
376: {
377: const disStructElement *e = &se->elements[j];
378: if(offset < e->size)
379: {
380: if(e->type == dtStringArray)
381: *count = e->size;
382: if(j == 0)
383: strcpy(addressLabel, dse->name);
384:
385: sprintf(commentBuffer, "[%s]", e->name);
386: if(e->comment)
387: strcat(commentBuffer, e->comment);
388: return e->type;
389: }
390: offset -= e->size;
391: }
392: return dse->size;
393: }
394: return dtNone;
395: }
396:
397: /***
398: * Lookup a symbol name
399: ***/
400: static const char *Disass68kSymbolName(long addr, int size)
401: {
402: int i;
403:
404: for(i=0; i<disSymbolCounts; ++i)
405: {
406: const disSymbolEntry *dse = &disSymbolEntries[i];
407: int offset = addr - dse->addr;
408: if(offset < 0 || offset >= dse->count * dse->size)
409: continue;
410:
411: if(dse->name[0] == 0)
412: return NULL;
413:
414: int reminder = offset % dse->size;
415: offset /= dse->size;
416:
417: static char symbolName[128];
418: strcpy(symbolName, dse->name);
419: if(offset)
420: sprintf(symbolName+strlen(symbolName), "+%d*%d", dse->size, offset);
421: if(reminder)
422: sprintf(symbolName+strlen(symbolName), "+%d", reminder);
423: return symbolName;
424: }
425: return NULL;
426: }
427:
428: /***
429: * return a string pointer to display a register name
430: ***/
431: static const char *Disass68kRegname(int reg)
432: {
433: static char regName[3];
434: switch(reg)
435: {
436: case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
437: sprintf(regName, "%c%d", (options & doptRegisterSmall ? 'd' : 'D'), reg);
438: break;
439:
440: case 0x0F:
441: if(options & doptStackSP) // display A7 as SP
442: {
443: if(options & doptRegisterSmall)
444: return "sp";
445: return "SP";
446: }
447: case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: case 0x0D: case 0x0E:
448: sprintf(regName, "%c%d", (options & doptRegisterSmall ? 'a' : 'A'), reg & 7);
449: break;
450: }
451: return regName;
452: }
453:
454: /***
455: * return a string pointer to display a register name
456: ***/
457: static const char *Disass68kNumber(int val)
458: {
459: static char numString[32];
460: if(val >= -9 && val <= 9)
461: {
462: sprintf(numString, "%d", val);
463: } else {
464: // 4 characters/numbers or underscore (e.g. for cookies)
465: char c0 = (val >> 24) & 0xFF;
466: char c1 = (val >> 16) & 0xFF;
467: char c2 = (val >> 8) & 0xFF;
468: char c3 = (val >> 0) & 0xFF;
469: if((isalnum(c0) || c0 == '_') && (isalnum(c1) || c1 == '_') && (isalnum(c2) || c2 == '_') && (isalnum(c3) || c3 == '_'))
470: {
471: sprintf(numString, "'%c%c%c%c'", c0, c1, c2, c3);
472: } else {
473: sprintf(numString, "$%x", val);
474: }
475: }
476: return numString;
477: }
478:
479: /***
480: * Supported registers for e.g. MOVEC
481: ***/
482: #define REG_CCR -1
483: #define REG_SR -2
484: #define REG_PC -3
485: #define REG_ZPC -4
486: #define REG_TT0 -8
487: #define REG_TT1 -9
488: #define REG_MMUSR -10
489: #define REG_USP 0x800
490: #define REG_SFC 0x000
491: #define REG_DFC 0x001
492: #define REG_TC 0x10000
493: #define REG_SRP 0x10002
494: #define REG_CRP 0x10003
495: #define REG_VAL 0x20000
496: #define REG_CACHES_NONE 0x20010
497: #define REG_CACHES_IC 0x20011
498: #define REG_CACHES_DC 0x20012
499: #define REG_CACHES_ICDC 0x20013
500: #define REG_FPU_FPCR 0x30004
501: #define REG_FPU_FPSR 0x30002
502: #define REG_FPU_FPIAR 0x30001
503:
504: static const char *Disass68kSpecialRegister(int reg)
505: {
506: static char buf[8];
507: const char *sp = NULL;
508: switch (reg)
509: {
510: case 0x000: sp = "SFC"; break;
511: case 0x001: sp = "DFC"; break;
512: case 0x002: sp = "CACR"; break;
513: case 0x003: sp = "TC"; break;
514: case 0x004: sp = "ITT0"; break; // IACR0 on an 68EC040 only
515: case 0x005: sp = "ITT1"; break; // IACR1 on an 68EC040 only
516: case 0x006: sp = "DTT0"; break; // DACR0 on an 68EC040 only
517: case 0x007: sp = "DTT1"; break; // DACR1 on an 68EC040 only
518: case 0x008: sp = "BUSCR"; break;
519:
520: case 0x800: sp = "USP"; break;
521: case 0x801: sp = "VBR"; break;
522: case 0x802: sp = "CAAR"; break;
523: case 0x803: sp = "MSP"; break;
524: case 0x804: sp = "ISP"; break;
525: case 0x805: sp = "MMUSR"; break;
526: case 0x806: sp = "URP"; break;
527: case 0x807: sp = "SRP"; break;
528: case 0x808: sp = "PCR"; break;
529:
530: // MMU register
531: case 0x10000: sp = "TC"; break;
532: case 0x10001: sp = "DRP"; break;
533: case 0x10002: sp = "SRP"; break;
534: case 0x10003: sp = "CRP"; break;
535: case 0x10004: sp = "CAL"; break;
536: case 0x10005: sp = "VAL"; break;
537: case 0x10006: sp = "SCCR"; break;
538: case 0x10007: sp = "ACR"; break;
539:
540: case REG_CCR: sp = "CCR"; break;
541: case REG_SR: sp = "SR"; break;
542: case REG_PC: sp = "PC"; break;
543: case REG_ZPC: sp = "ZPC"; break;
544: case REG_TT0: sp = "TT0"; break;
545: case REG_TT1: sp = "TT1"; break;
546: case REG_MMUSR: sp = "MMUSR"; break;
547:
548: case REG_VAL: sp = "VAL"; break;
549:
550: case REG_CACHES_NONE: sp = "NC"; break;
551: case REG_CACHES_IC: sp = "IC"; break;
552: case REG_CACHES_DC: sp = "DC"; break;
553: case REG_CACHES_ICDC: sp = "IC/DC"; break; // GCC lists this as "BC"
554:
555: case REG_FPU_FPCR: sp = "FPCR"; break;
556: case REG_FPU_FPSR: sp = "FPSR"; break;
557: case REG_FPU_FPIAR: sp = "FPIAR"; break;
558:
559: // unknown register => unknown opcode!
560: default: break;
561: }
562: if(options & doptRegisterSmall)
563: {
564: strcpy(buf, sp);
565: char *bp = buf;
566: for(; *bp; ++bp)
567: *bp = tolower(*bp);
568: return buf;
569: }
570: return sp;
571: }
572:
573: /***
574: * 680x0 EA disassembly, supports all address modes
575: *
576: * disassbuf = output buffer for the EA, empty string in case of an illegal EA
577: * addr = pointer to the address, which Disass68kGetWord() will allow to read memory.
578: * Incremented by the function to point behind the opcode, when done
579: * ea = 6-bit ea from the opcode
580: * size = addressed size of the opcode in bytes (e.g. 1,2,4 for MOVE.B, MOVE.W, MOVE.L), only used for immediate addressing
581: ***/
582:
583: #define EA_Dn 0x00001 // Dn
584: #define EA_An 0x00002 // An
585: #define EA_Ani 0x00004 // (An)
586: #define EA_Anip 0x00008 // (An)+
587: #define EA_piAn 0x00010 // -(An)
588: #define EA_dAn 0x00020 // d(An), d(An,Dn), etc.
589: #define EA_PCRel 0x00040 // d(PC), d(PC,Dn), etc.
590: #define EA_Abs 0x00080 // abs.w, abs.l
591: #define EA_Immed 0x00100 // #<val>
592:
593: #define EA_ImmedParameter 0x0200 // an immediate value as a parameter
594: #define EA_ValueParameter 0x0400 // an immediate value as a parameter without the "#"
595: #define EA_SpecialRegister 0x0800 // any special register e.g. SR,CCR,USP,etc
596: #define EA_PCDisplacement 0x1000 // PC relative jump, like for BRA and friends
597:
598: #define EA_All (EA_Dn | EA_An | EA_Ani | EA_Anip | EA_piAn | EA_dAn | EA_Abs | EA_Immed | EA_PCRel)
599: #define EA_Dest (EA_Dn | EA_An | EA_Ani | EA_Anip | EA_piAn | EA_dAn | EA_Abs)
600:
601: static char *Disass68kEA(char *disassbuf, char *commentBuffer, long *addr, long opcodeAddr, int ea, int size, int allowedEAs, int parameterValue, int disassFlag)
602: {
603: unsigned short eWord1;
604: unsigned short eWord2;
605: int xn,c,scale;
606: int reg = ea & 7;
607: const char *sp;
608: long val;
609: val = 0;
610:
611: disassbuf[0] = 0;
612: switch(ea)
613: {
614: // M=000 = 0 Dn
615: // Data Register Direct Mode
616: // Dn
617: // M=001 = 1 An
618: // Address Register Direct Mode
619: // An
620: case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
621: if((allowedEAs & EA_Dn) != EA_Dn)
622: break;
623: sprintf(disassbuf, "%s", Disass68kRegname(ea & 0x0F));
624: break;
625: case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: case 0x0D: case 0x0E: case 0x0F:
626: if((allowedEAs & EA_An) != EA_An)
627: break;
628: sprintf(disassbuf, "%s", Disass68kRegname(ea & 0x0F));
629: break;
630:
631: // M=010 = 2
632: // Address Register Indirect Mode
633: // (An)
634: case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
635: if((allowedEAs & EA_Ani) != EA_Ani)
636: break;
637: sprintf(disassbuf, "(%s)", Disass68kRegname(reg | 8));
638: break;
639:
640: // M=011 = 3
641: // Address Register Indirect with Postincrement Mode
642: // (An) +
643: case 0x18: case 0x19: case 0x1A: case 0x1B: case 0x1C: case 0x1D: case 0x1E: case 0x1F:
644: if((allowedEAs & EA_Anip) != EA_Anip)
645: break;
646: sprintf(disassbuf, "(%s)+", Disass68kRegname(reg | 8));
647: break;
648:
649: // M=100 = 4
650: // Address Register Indirect with Predecrement Mode
651: // – (An)
652: case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
653: if((allowedEAs & EA_piAn) != EA_piAn)
654: break;
655: sprintf(disassbuf, "-(%s)", Disass68kRegname(reg | 8));
656: break;
657:
658: // M=101 = 5
659: // Address Register Indirect with Displacement Mode
660: // (d16,An)
661: case 0x28: case 0x29: case 0x2A: case 0x2B: case 0x2C: case 0x2D: case 0x2E: case 0x2F:
662: if((allowedEAs & EA_dAn) != EA_dAn)
663: break;
664: eWord1 = Disass68kGetWord(*addr); *addr += 2;
665: sprintf(disassbuf, "%s(%s)", Disass68kNumber(eWord1), Disass68kRegname(reg | 8));
666: break;
667:
668: // M=111 = 7, Xn/reg = 011 = 3
669: // Program Counter Indirect with Index (Base Displacement) Mode
670: // (bd, PC, Xn. SIZE*SCALE)
671: // Program Counter Memory Indirect Postindexed Mode
672: // ([bd,PC],Xn.SIZE*SCALE,od)
673: // Program Counter Memory Indirect Preindexed Mode
674: // ([bd,PC,Xn.SIZE*SCALE],od)
675: case 0x3B:
676: // This is equal to the following, except that instead of An, it is PC relative
677:
678: // M=110 = 6
679: // Address Register Indirect with Index (Base Displacement) Mode
680: // (bd,An,Xn.SIZE*SCALE)
681: // Memory Indirect Postindexed Mode
682: // ([bd,An],Xn.SIZE*SCALE,od)
683: // Memory Indirect Preindexed Mode
684: // ([bd, An, Xn.SIZE*SCALE], od)
685: case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
686: eWord1 = Disass68kGetWord(*addr); *addr += 2;
687: xn = (eWord1 >> 12) & 0x0F; // Register D0..D7/A0..A7
688: c = ((eWord1 >> 11) & 1) ? 'l' : 'w'; // Word/Long-Word Index Size 0 = Sign-Extended Word 1 = Long Word
689: scale = (eWord1 >> 9) & 3; // Scale Factor 00 = 1 01 = 2 10 = 4 11 = 8
690: char regName[3];
691: if(ea == 0x3B)
692: {
693: sp = Disass68kSpecialRegister(REG_PC);
694: if(!sp) return NULL;
695: strcpy(regName, sp);
696: } else {
697: sprintf(regName, "%s", Disass68kRegname(reg | 8));
698: }
699:
700: if((eWord1 & 0x0100) == 0)
701: {
702: // BRIEF EXTENSION WORD FORMAT
703: if(ea == 0x3B)
704: {
705: if((allowedEAs & EA_PCRel) != EA_PCRel)
706: break;
707: } else {
708: if((allowedEAs & EA_dAn) != EA_dAn)
709: break;
710: }
711:
712: // Address Register Indirect with Index (8-Bit Displacement) Mode
713: // (d8 ,An, Xn.SIZE*SCALE)
714: const char *numStr = Disass68kNumber(eWord1 & 0xFF);
715: if(numStr[0] == '0' && numStr[1] == 0)
716: numStr = "";
717:
718: // scale is only on 68020 and later supported
719: if(scale != 0 && (optionCPUTypeMask & MC_020) == 0)
720: return NULL;
721:
722: if(scale == 0)
723: {
724: #if ADDRESS_ON_PC
725: if(ea == 0x3B)
726: sprintf(disassbuf, "$%lx(%s,%s.%c)", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2, Disass68kSpecialRegister(REG_PC), Disass68kRegname(xn), c);
727: else
728: #endif
729: sprintf(disassbuf, "%s(%s,%s.%c)", numStr, regName, Disass68kRegname(xn), c);
730: } else
731: {
732: #if ADDRESS_ON_PC
733: if(ea == 0x3B)
734: sprintf(disassbuf, "$%lx(%s,%s.%c*%d)", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2, Disass68kSpecialRegister(REG_PC), Disass68kRegname(xn), c, 1 << scale);
735: else
736: #endif
737: sprintf(disassbuf, "%s(%s,%s.%c*%d)", numStr, regName, Disass68kRegname(xn), c, 1 << scale);
738: }
739: #if USE_SYMBOLS
740: if(ea == 0x3B)
741: {
742: const char *symStr = Disass68kSymbolName((signed char)(eWord1 & 0xFF) + opcodeAddr + 2, size);
743: if(symStr)
744: {
745: commentBuffer += strlen(commentBuffer);
746: sprintf(commentBuffer+strlen(commentBuffer), "%s", symStr);
747: }
748: }
749: #endif
750: #if !ADDRESS_ON_PC
751: if(ea == 0x3B)
752: {
753: commentBuffer += strlen(commentBuffer);
754: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2);
755: }
756: #endif
757: } else {
758: // FULL EXTENSION WORD FORMAT
759:
760: int bs = (eWord1 >> 7) & 1; // Base Register Suppress 0 = Base Register Added 1 = Base Register Suppressed
761: int is = (eWord1 >> 6) & 1; // Index Suppress 0 = Evaluate and Add Index Operand 1 = Suppress Index Operand
762: int bdSize = (eWord1 >> 4) & 3; // Base Displacement Size 00 = Reserved 01 = Null Displacement 10 = Word Displacement 11 = Long Displacement
763: int iis = eWord1 & 7; // Index/Indirect Selection Indirect and Indexing Operand Determined in Conjunction with Bit 6, Index Suppress
764: bool prefixComma;
765:
766: // reserved, has to be 0
767: if((eWord1 & 8) != 0 || bdSize == 0 || (is && iis > 3) || iis == 4)
768: break;
769:
770: // full extension format is only supported on 68020 or later
771: if((optionCPUTypeMask & MC_020) == 0)
772: return NULL;
773:
774: if(ea == 0x3B)
775: {
776: if((allowedEAs & EA_PCRel) != EA_PCRel)
777: break;
778: } else {
779: if((allowedEAs & EA_dAn) != EA_dAn)
780: break;
781: }
782:
783: long bd = 0;
784: switch(bdSize)
785: {
786: case 3:
787: bd = Disass68kGetWord(*addr); *addr += 2;
788: bd <<= 16;
789: case 2:
790: bd |= Disass68kGetWord(*addr); *addr += 2;
791: break;
792: default:
793: break;
794: }
795:
796: prefixComma = false;
797: if(bdSize >= 2 && iis == 0)
798: sprintf(disassbuf, "%s", Disass68kNumber(bd));
799: strcat(disassbuf, "(");
800: if(iis != 0)
801: {
802: // the CPU32 doesn't support the memory indirect mode
803: if(optionCPUTypeMask & MC_CPU32)
804: return NULL;
805:
806: strcat(disassbuf, "[");
807: }
808: if(bdSize >= 2 && iis != 0)
809: {
810: sprintf(disassbuf+strlen(disassbuf), "%s", Disass68kNumber(bd));
811: prefixComma = true;
812: }
813: if(bdSize == 1 && ((bs && is && iis > 0) || (bs && iis >= 5)))
814: {
815: if(ea == 0x3B)
816: {
817: sp = Disass68kSpecialRegister(REG_ZPC);
818: if(!sp) return NULL;
819: strcat(disassbuf, sp);
820: } else {
821: strcat(disassbuf, "0");
822: }
823: }
824: if(!bs)
825: {
826: if(prefixComma)
827: strcat(disassbuf, ",");
828: strcat(disassbuf, regName);
829: prefixComma = true;
830: }
831: if(iis >= 5 && iis <= 7)
832: {
833: strcat(disassbuf, "]");
834: prefixComma = true;
835: }
836: if(!is)
837: {
838: if(prefixComma)
839: strcat(disassbuf, ",");
840: if(scale == 0)
841: {
842: sprintf(disassbuf+strlen(disassbuf), "%s.%c", Disass68kRegname(xn), c);
843: } else
844: {
845: sprintf(disassbuf+strlen(disassbuf), "%s.%c*%d", Disass68kRegname(xn), c, 1 << scale);
846: }
847: }
848: if(iis >= 1 && iis <= 3)
849: {
850: strcat(disassbuf, "]");
851: prefixComma = true;
852: }
853: long od = 0;
854: switch(iis & 3)
855: {
856: case 3:
857: od = Disass68kGetWord(*addr); *addr += 2;
858: od <<= 16;
859: case 2:
860: od |= Disass68kGetWord(*addr); *addr += 2;
861: if(prefixComma)
862: strcat(disassbuf, ",");
863: sprintf(disassbuf+strlen(disassbuf), "%s", Disass68kNumber(od));
864: break;
865: default:
866: break;
867: }
868: strcat(disassbuf, ")");
869: }
870: break;
871:
872: // M=111 = 7, Xn/reg = 000 = 0
873: // Absolute Short Addressing Mode
874: // (xxx).W
875: case 0x38:
876: if((allowedEAs & EA_Abs) != EA_Abs)
877: break;
878: eWord1 = Disass68kGetWord(*addr); *addr += 2;
879: val = eWord1;
880: if(eWord1 & 0x8000)
881: val |= 0xFFFF0000;
882: #if USE_SYMBOLS
883: sp = Disass68kSymbolName(val, size);
884: if(sp)
885: {
886: if(options & doptNoBrackets)
887: sprintf(disassbuf, "%s.w", sp);
888: else
889: sprintf(disassbuf, "(%s).w", sp);
890: break;
891: }
892: #endif
893: if(options & doptNoBrackets)
894: {
895: if(val & 0x80000000)
896: sprintf(disassbuf, "$%8.8lx.w", val);
897: else
898: sprintf(disassbuf, "$%4.4lx.w", val);
899: } else {
900: if(val & 0x80000000)
901: sprintf(disassbuf, "($%8.8lx).w", val);
902: else
903: sprintf(disassbuf, "($%4.4lx).w", val);
904: }
905: break;
906:
907: // M=111 = 7, Xn/reg = 001 = 1
908: // Absolute Long Addressing Mode
909: // (xxx).L
910: case 0x39:
911: if((allowedEAs & EA_Abs) != EA_Abs)
912: break;
913: eWord1 = Disass68kGetWord(*addr); *addr += 2;
914: eWord2 = Disass68kGetWord(*addr); *addr += 2;
915: #if USE_SYMBOLS
916: val = (eWord1 << 16) | eWord2;
917: sp = Disass68kSymbolName(val, size);
918: if(sp)
919: {
920: if(options & doptNoBrackets)
921: sprintf(disassbuf, "%s", sp);
922: else
923: sprintf(disassbuf, "(%s).l", sp);
924: break;
925: }
926: #endif
927: if(options & doptNoBrackets)
928: sprintf(disassbuf, "%s", Disass68kNumber((eWord1 << 16) | eWord2));
929: else
930: sprintf(disassbuf, "(%s).l", Disass68kNumber((eWord1 << 16) | eWord2));
931: break;
932:
933: // M=111 = 7, Xn/reg = 010 = 2
934: // Program Counter Indirect with Displacement Mode
935: // (d16,PC)
936: case 0x3A:
937: if((allowedEAs & EA_PCRel) != EA_PCRel)
938: break;
939: eWord1 = Disass68kGetWord(*addr); *addr += 2;
940: sp = Disass68kSpecialRegister(REG_PC);
941: if(!sp) return NULL;
942: #if ADDRESS_ON_PC
943: #if USE_SYMBOLS
944: sp = Disass68kSymbolName(((signed short)eWord1 + *addr - 2), size);
945: if(sp)
946: {
947: sprintf(disassbuf, "%s(%s)", sp, Disass68kSpecialRegister(REG_PC));
948: } else {
949: sprintf(disassbuf, "$%lx(%s)", (signed short)eWord1 + *addr - 2, Disass68kSpecialRegister(REG_PC));
950: }
951: #else
952: sprintf(disassbuf, "$%lx(%s)", (signed short)eWord1 + *addr - 2, Disass68kSpecialRegister(REG_PC));
953: #endif
954: #else
955: sprintf(disassbuf, "%s(%s)", Disass68kNumber(eWord1),sp);
956: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", (signed short)eWord1 + *addr - 2);
957: #endif
958: break;
959:
960: // M=111 = 7, Xn/reg = 100 = 4
961: // Immediate Data
962: // #<xxx>
963: case 0x3C:
964: if((allowedEAs & EA_Immed) != EA_Immed)
965: break;
966: eWord1 = Disass68kGetWord(*addr); *addr += 2;
967: goto immed;
968:
969: case 0x0100: // Immediate Value as a parameter
970: if((allowedEAs & EA_ImmedParameter) != EA_ImmedParameter)
971: break;
972: eWord1 = parameterValue;
973: immed:
974: switch(size)
975: {
976: case 1: eWord1 &= 0xFF;
977: case 2:
978: #if USE_SYMBOLS
979: if(disassFlag)
980: {
981: val = eWord1;
982: if(eWord1 & 0x8000)
983: val |= 0xFFFF0000;
984: sp = Disass68kSymbolName(val, size);
985: if(sp)
986: {
987: sprintf(disassbuf, "#%s", sp);
988: break;
989: }
990: }
991: #endif
992: sprintf(disassbuf, "#%s", Disass68kNumber(eWord1));
993: break;
994: case 4: eWord2 = Disass68kGetWord(*addr); *addr += 2;
995: #if USE_SYMBOLS
996: if(disassFlag)
997: {
998: val = (eWord1 << 16) | eWord2;
999: sp = Disass68kSymbolName(val, size);
1000: if(sp)
1001: {
1002: sprintf(disassbuf, "#%s", sp);
1003: break;
1004: }
1005: }
1006: #endif
1007: sprintf(disassbuf, "#%s", Disass68kNumber((eWord1 << 16) | eWord2));
1008: break;
1009: }
1010: break;
1011:
1012: case 0x0103:
1013: if((allowedEAs & EA_ValueParameter) != EA_ValueParameter)
1014: break;
1015: sprintf(disassbuf, "%d", parameterValue);
1016: break;
1017:
1018: case 0x0101: // Special Registers as in the parameter
1019: if((allowedEAs & EA_SpecialRegister) != EA_SpecialRegister)
1020: break;
1021: sp = Disass68kSpecialRegister(parameterValue);
1022: if(!sp) return NULL;
1023: strcpy(disassbuf, sp);
1024: break;
1025:
1026: case 0x0102: // PC relative jump, like for BRA and friends
1027: if((allowedEAs & EA_PCDisplacement) != EA_PCDisplacement)
1028: break;
1029: signed long pcoffset = 0;
1030: switch(size)
1031: {
1032: case 1: pcoffset = (signed char)parameterValue;
1033: break;
1034: case 2: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1035: pcoffset = (signed short)eWord1;
1036: pcoffset -= 2;
1037: break;
1038: case 4: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1039: eWord2 = Disass68kGetWord(*addr); *addr += 2;
1040: pcoffset = (signed int)((eWord1 << 16) | eWord2);
1041: pcoffset -= 4;
1042: break;
1043: }
1044: #if ADDRESS_ON_PC
1045: #if USE_SYMBOLS
1046: sp = Disass68kSymbolName((*addr + pcoffset), size);
1047: if(sp)
1048: {
1049: strcat(disassbuf, sp);
1050: } else {
1051: sprintf(disassbuf, "$%lx", *addr + pcoffset);
1052: }
1053: #else
1054: sprintf(disassbuf, "$%lx", *addr + pcoffset);
1055: #endif
1056: #else
1057: if(pcoffset < 0)
1058: {
1059: sprintf(disassbuf, "*-$%lx", -pcoffset - 2);
1060: } else {
1061: sprintf(disassbuf, "*+$%lx", pcoffset + 2);
1062: }
1063: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", *addr + pcoffset);
1064: #endif
1065: break;
1066:
1067: default: // 0x3D..0x3F are reserved
1068: break;
1069:
1070: }
1071: if(disassbuf[0] == 0)
1072: return NULL;
1073: return disassbuf + strlen(disassbuf);
1074: }
1075:
1076: /***
1077: * Create a register list for the MOVEM opcode
1078: ***/
1079: static char *Disass68kReglist(char *buf, unsigned short reglist)
1080: {
1081: int bit;
1082: int lastBit = -99;
1083: int lastBitStart = -99;
1084: char regD = options & doptRegisterSmall ? 'd' : 'D';
1085: char regA = options & doptRegisterSmall ? 'a' : 'A';
1086: for(bit=0; bit<=15; ++bit)
1087: {
1088: // bit clear?
1089: if((reglist & (1 << bit)) == 0)
1090: {
1091: // do we have a run? => close it!
1092: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1093: {
1094: *buf++ = '-';
1095: *buf++ = ((bit-1) >= 8) ? regA : regD;
1096: *buf++ = '0' + ((bit-1) & 7);
1097: }
1098: lastBitStart = -1;
1099: continue;
1100: }
1101: // reset when switching from D to A
1102: if(bit == 8 && lastBitStart >= 0)
1103: {
1104: *buf++ = '-';
1105: *buf++ = regD;
1106: *buf++ = '7';
1107: lastBit = 0;
1108: lastBitStart = -99;
1109: }
1110: // separate bits, skip runs of bits to merge them later
1111: if(lastBit >= 0)
1112: {
1113: if(lastBit == bit - 1)
1114: {
1115: lastBit = bit;
1116: continue;
1117: }
1118: *buf++ = '/';
1119: }
1120: *buf++ = (bit >= 8) ? regA : regD;
1121: *buf++ = '0' + (bit & 7);
1122: lastBit = bit;
1123: lastBitStart = bit;
1124: }
1125: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1126: {
1127: *buf++ = '-';
1128: *buf++ = regA;
1129: *buf++ = '7';
1130: }
1131: if(lastBit < 0)
1132: {
1133: *buf++ = '0';
1134: }
1135: *buf = 0;
1136: return buf;
1137: }
1138:
1139: /***
1140: * Flip the bits in an unsigned short, for MOVEM RegList,-(An)
1141: ***/
1142: static unsigned short Disass68kFlipBits(unsigned short mask)
1143: {
1144: unsigned short retMask = 0;
1145: int i;
1146:
1147: for(i=0; i<=15; ++i)
1148: if(mask & (1 << i))
1149: retMask |= (1 << (15-i));
1150: return retMask;
1151: }
1152:
1153: /***
1154: * Create a register list for the MOVEM opcode
1155: ***/
1156: static char *Disass68kFPUReglist(char *buf, unsigned char reglist)
1157: {
1158: int bit;
1159: int lastBit = -99;
1160: int lastBitStart = -99;
1161: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
1162: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
1163: for(bit=0; bit<=7; ++bit)
1164: {
1165: // bit clear?
1166: if((reglist & (1 << bit)) == 0)
1167: {
1168: // do we have a run? => close it!
1169: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1170: {
1171: *buf++ = '-';
1172: *buf++ = regFP1;
1173: *buf++ = regFP2;
1174: *buf++ = '0' + ((bit-1) & 7);
1175: }
1176: lastBitStart = -1;
1177: continue;
1178: }
1179: // separate bits, skip runs of bits to merge them later
1180: if(lastBit >= 0)
1181: {
1182: if(lastBit == bit - 1)
1183: {
1184: lastBit = bit;
1185: continue;
1186: }
1187: *buf++ = '/';
1188: }
1189: *buf++ = regFP1;
1190: *buf++ = regFP2;
1191: *buf++ = '0' + (bit & 7);
1192: lastBit = bit;
1193: lastBitStart = bit;
1194: }
1195: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1196: {
1197: *buf++ = '-';
1198: *buf++ = regFP1;
1199: *buf++ = regFP2;
1200: *buf++ = '7';
1201: }
1202: if(lastBit < 0)
1203: {
1204: *buf++ = '0';
1205: }
1206: *buf = 0;
1207: return buf;
1208: }
1209:
1210:
1211: /***
1212: * List of special cases for the operands
1213: ***/
1214: typedef enum {
1215: ofNone,
1216: ofEa,
1217: ofDn,
1218: ofAn,
1219: ofAni,
1220: ofI,
1221: ofSpecReg,
1222: ofSpecExtReg,
1223: ofD16An,
1224: ofDestDn,
1225: ofDestAn,
1226: ofExtReg,
1227: ofExtAnip,
1228: ofExtReg0,
1229: ofExtRegA0,
1230: ofExtRegD04,
1231: ofExtRegA05,
1232: ofFPUReglist,
1233: ofFPUSRRegList,
1234: ofDestEa6,
1235: ofDestAbsL,
1236: ofIOpcode,
1237: ofCAS,
1238: ofCAS2,
1239: ofI3,
1240: ofExtIm,
1241: ofExtIm32,
1242: ofExtIm4,
1243: ofExtIm10,
1244: ofDisp,
1245: ofPiAn,
1246: ofDestPiAn,
1247: ofAnip,
1248: ofDestAnip,
1249: ofBFEa,
1250: ofRegList,
1251: ofExt4Dn,
1252: ofFPU,
1253: ofFPUMOVE,
1254: ofFMOVECR,
1255: ofFPU3Reg,
1256: ofLineA,
1257: } Disass68kOpcodeFormat;
1258:
1259:
1260: /***
1261: * The order of the table is not important (with the exception of some FPU opcodes, which are commented further down),
1262: * as each opcode should decline if it doesn't match 100%. The 68k CPU also doesn't do guessing based on the context!
1263: ***/
1264: typedef const struct {
1265: int cpuMask;
1266: unsigned long opcodeMask[2*5];
1267: char operationSize[4];
1268: char op[5];
1269: const char *opcodeName;
1270: int parameter[5];
1271: int disassFlag;
1272: } OpcodeTableStruct;
1273:
1274: static const OpcodeTableStruct OpcodeTable[] = {
1275: { MC_ALL, {0xff00, 0x0000}, {-1,6,2,0}, {ofI,ofEa}, "ORI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1276: { MC_ALL, {0xf1c0, 0x0100}, {4}, {ofDestDn,ofEa}, "BTST",{0,EA_An|EA_Immed} },
1277: { MC_ALL, {0xf1c0, 0x0140}, {4}, {ofDestDn,ofEa}, "BCHG",{0,EA_Immed|EA_PCRel|EA_An}},
1278: { MC_ALL, {0xf1c0, 0x0180}, {4}, {ofDestDn,ofEa}, "BCLR",{0,EA_Immed|EA_PCRel|EA_An}},
1279: { MC_ALL, {0xf1c0, 0x01C0}, {4}, {ofDestDn,ofEa}, "BSET",{0,EA_Immed|EA_PCRel|EA_An}},
1280: { MC_ALL-MC68060, {0xf1f8, 0x0108}, {2}, {ofD16An,ofDestDn}, "MOVEP.W"},
1281: { MC_ALL-MC68060, {0xf1f8, 0x0148}, {4}, {ofD16An,ofDestDn}, "MOVEP.L"},
1282: { MC_ALL-MC68060, {0xf1f8, 0x0188}, {2}, {ofDestDn,ofD16An}, "MOVEP.W"},
1283: { MC_ALL-MC68060, {0xf1f8, 0x01C8}, {4}, {ofDestDn,ofD16An}, "MOVEP.L"},
1284: { MC_ALL, {0xff00, 0x0200}, {-1,6,2,0}, {ofI,ofEa}, "ANDI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1285: { MC_ALL, {0xff00, 0x0400}, {-1,6,2,0}, {ofI,ofEa}, "SUBI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1286: { MC_ALL, {0xff00, 0x0600}, {-1,6,2,0}, {ofI,ofEa}, "ADDI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1287: { MC_ALL, {0xffc0, 0x0800}, {1}, {ofI,ofEa}, "BTST",{0,EA_An|EA_Immed} },
1288: { MC_ALL, {0xffc0, 0x0840}, {1}, {ofI,ofEa}, "BCHG",{0,EA_Immed|EA_PCRel|EA_An}},
1289: { MC_ALL, {0xffc0, 0x0880}, {1}, {ofI,ofEa}, "BCLR",{0,EA_Immed|EA_PCRel|EA_An}},
1290: { MC_ALL, {0xffc0, 0x08C0}, {1}, {ofI,ofEa}, "BSET",{0,EA_Immed|EA_PCRel|EA_An}},
1291: { MC_ALL, {0xff00, 0x0A00}, {-1,6,2,0}, {ofI,ofEa}, "EORI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1292: { MC_ALL, {0xff00, 0x0C00}, {-1,6,2,0}, {ofI,ofEa}, "CMPI.?",{0,EA_Immed|EA_An}},
1293: { MC_ALL, {0xffff, 0x003C}, {1}, {ofEa,ofSpecReg}, "ORI",{0,REG_CCR} },
1294: { MC_ALL, {0xffff, 0x007C}, {2}, {ofEa,ofSpecReg}, "ORI",{0,REG_SR} },
1295: { MC_ALL, {0xffff, 0x023C}, {1}, {ofEa,ofSpecReg}, "ANDI",{0,REG_CCR} },
1296: { MC_ALL, {0xffff, 0x027C}, {2}, {ofEa,ofSpecReg}, "ANDI",{0,REG_SR} },
1297: { MC_ALL, {0xffff, 0x0A3C}, {1}, {ofEa,ofSpecReg}, "EORI",{0,REG_CCR} },
1298: { MC_ALL, {0xffff, 0x0A7C}, {2}, {ofEa,ofSpecReg}, "EORI",{0,REG_SR} },
1299: { MC68020, {0xffc0, 0x06C0}, {1}, {ofEa}, "CALLM",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1300: { MC68020, {0xfff0, 0x06C0}, {1}, {ofEa}, "RTM"},
1301: { MC_020, {0xf9c0, 0x00C0, 0x0fff,0x0000}, {-1,9,2,0}, {ofEa,ofExtReg}, "CMP2.?",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1302: { MC_020, {0xf9c0, 0x00C0, 0x0fff,0x0800}, {-1,9,2,0}, {ofEa,ofExtReg}, "CHK2.?",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1303: { MC_020&~MC_CPU32, {0xffc0, 0x0AC0, 0xFE38,0x0000}, {1}, {ofCAS,ofEa}, "CAS.B",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1304: { MC_020&~MC_CPU32, {0xffc0, 0x0CC0, 0xFE38,0x0000}, {2}, {ofCAS,ofEa}, "CAS.W",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1305: { MC_020&~MC_CPU32, {0xffc0, 0x0EC0, 0xFE38,0x0000}, {4}, {ofCAS,ofEa}, "CAS.L",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1306: { MC_020&~MC_CPU32, {0xffff, 0x0CFC, 0x0E38,0x0000, 0x0E38,0x0000}, {2}, {ofCAS2}, "CAS2.W"},
1307: { MC_020&~MC_CPU32, {0xffff, 0x0EFC, 0x0E38,0x0000, 0x0E38,0x0000}, {4}, {ofCAS2}, "CAS2.L"},
1308: { MC68010|MC_020, {0xff00, 0x0e00, 0x0fff,0x0000}, {-1,6,2,0}, {ofEa,ofExtReg}, "MOVES.?",{EA_Immed|EA_PCRel|EA_An|EA_Dn,0}},
1309: { MC68010|MC_020, {0xff00, 0x0e00, 0x0fff,0x0800}, {-1,6,2,0}, {ofExtReg,ofEa}, "MOVES.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1310:
1311: { MC_ALL, {0xf000, 0x1000}, {1}, {ofEa,ofDestEa6}, "MOVE.B"},
1312:
1313: { MC_ALL, {0xf000, 0x2000}, {4}, {ofEa,ofDestEa6}, "MOVE.L"},
1314: { MC_ALL, {0xf1c0, 0x2040}, {4}, {ofEa,ofDestAn}, "MOVEA.L",{0},1},
1315:
1316: { MC_ALL, {0xf000, 0x3000}, {2}, {ofEa,ofDestEa6}, "MOVE.W"},
1317: { MC_ALL, {0xf1c0, 0x3040}, {2}, {ofEa,ofDestAn}, "MOVEA.W",{0},1},
1318:
1319: { MC_ALL, {0xff00, 0x4000}, {-1,6,2,0}, {ofEa}, "NEGX.?",{EA_Immed|EA_PCRel|EA_An}},
1320: { MC_020, {0xf1c0, 0x4100}, {4}, {ofEa,ofDestDn}, "CHK.L", {EA_An,0}},
1321: { MC_ALL, {0xf1c0, 0x4180}, {2}, {ofEa,ofDestDn}, "CHK.W", {EA_An,0}},
1322: { MC_ALL, {0xf1c0, 0x41c0}, {4}, {ofEa,ofDestAn}, "LEA",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn,0},1 },
1323: { MC_ALL, {0xff00, 0x4200}, {-1,6,2,0}, {ofEa}, "CLR.?",{EA_Immed|EA_PCRel|EA_An}},
1324: { MC_ALL, {0xff00, 0x4400}, {-1,6,2,0}, {ofEa}, "NEG.?",{EA_Immed|EA_PCRel|EA_An}},
1325: { MC_ALL, {0xff00, 0x4600}, {-1,6,2,0}, {ofEa}, "NOT.?",{EA_Immed|EA_PCRel|EA_An}},
1326: { MC_ALL, {0xffc0, 0x40c0}, {2}, {ofSpecReg,ofEa}, "MOVE",{REG_SR,EA_Immed|EA_PCRel|EA_An} },
1327: { MC_ALL, {0xffc0, 0x42c0}, {1}, {ofSpecReg,ofEa}, "MOVE",{REG_CCR,EA_Immed|EA_PCRel|EA_An} },
1328: { MC_ALL, {0xffc0, 0x44c0}, {1}, {ofEa,ofSpecReg}, "MOVE",{EA_An,REG_CCR} },
1329: { MC_ALL, {0xffc0, 0x46c0}, {2}, {ofEa,ofSpecReg}, "MOVE",{EA_An,REG_SR} },
1330: { MC_ALL, {0xffc0, 0x4800}, {1}, {ofEa}, "NBCD",{EA_Immed|EA_PCRel|EA_An}},
1331: { MC_020, {0xfff8, 0x4808}, {4}, {ofEa,ofI}, "LINK.L"},
1332: { MC_ALL, {0xffc0, 0x4840}, {0}, {ofEa}, "PEA",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn},1 },
1333: { MC_ALL, {0xfff8, 0x4840}, {4}, {ofEa}, "SWAP"},
1334: { MC68010|MC_020, {0xfff8, 0x4848}, {0}, {ofIOpcode}, "BKPT",{0x07} },
1335: { MC_ALL, {0xffc0, 0x4880, 0x10000}, {2}, {ofRegList,ofEa}, "MOVEM.W",{0,EA_Dn|EA_An|EA_Immed|EA_Anip|EA_PCRel} },
1336: { MC_ALL, {0xffc0, 0x48c0, 0x10000}, {4}, {ofRegList,ofEa}, "MOVEM.L",{0,EA_Dn|EA_An|EA_Immed|EA_Anip|EA_PCRel} },
1337: { MC_ALL, {0xfff8, 0x4880}, {2}, {ofEa}, "EXT.W"},
1338: { MC_ALL, {0xfff8, 0x48c0}, {4}, {ofEa}, "EXT.L"},
1339: { MC_020, {0xfff8, 0x49c0}, {4}, {ofEa}, "EXTB.L"},
1340: { MC_ALL, {0xff00, 0x4a00}, {-1,6,2,0}, {ofEa}, "TST.?"},
1341: { MC_ALL, {0xffc0, 0x4ac0}, {1}, {ofEa}, "TAS",{EA_Immed|EA_PCRel|EA_An}},
1342: { MC_CPU32, {0xffff, 0x4afa}, {0}, {ofNone}, "BGND"},
1343: { MC_ALL, {0xffff, 0x4afc}, {0}, {ofNone}, "ILLEGAL"},
1344: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0000}, {4}, {ofEa,ofExtReg}, "MULU.L", {EA_An,0}},
1345: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0800}, {4}, {ofEa,ofExtReg}, "MULS.L", {EA_An,0}},
1346: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0000}, {4}, {ofEa,ofExtReg}, "DIVU.L", {EA_An,0}},
1347: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0800}, {4}, {ofEa,ofExtReg}, "DIVS.L", {EA_An,0}},
1348: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0400}, {4}, {ofEa,ofExtReg,ofExtReg0}, "MULU.L", {EA_An,0,0}},
1349: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0c00}, {4}, {ofEa,ofExtReg,ofExtReg0}, "MULS.L", {EA_An,0,0}},
1350: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0400}, {4}, {ofEa,ofExtReg,ofExtReg0}, "DIVU.L", {EA_An,0,0}},
1351: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0c00}, {4}, {ofEa,ofExtReg,ofExtReg0}, "DIVS.L", {EA_An,0,0}},
1352: { MC_ALL, {0xffc0, 0x4c80, 0x10000}, {2}, {ofEa,ofRegList}, "MOVEM.W",{EA_Dn|EA_An|EA_Immed|EA_piAn,0} },
1353: { MC_ALL, {0xffc0, 0x4cc0, 0x10000}, {4}, {ofEa,ofRegList}, "MOVEM.L",{EA_Dn|EA_An|EA_Immed|EA_piAn,0} },
1354: { MC_ALL, {0xfff0, 0x4e40}, {0}, {ofIOpcode}, "TRAP",{0x0f} },
1355: { MC_ALL, {0xfff8, 0x4e50}, {2}, {ofAn,ofI}, "LINK"},
1356: { MC_ALL, {0xfff8, 0x4e58}, {4}, {ofAn}, "UNLK"},
1357: { MC_ALL, {0xfff8, 0x4e60}, {4}, {ofAn,ofSpecReg}, "MOVE",{0,REG_USP} },
1358: { MC_ALL, {0xfff8, 0x4e68}, {4}, {ofSpecReg,ofAn}, "MOVE",{REG_USP,0} },
1359: { MC_ALL, {0xffff, 0x4e70}, {0}, {ofNone}, "RESET"},
1360: { MC_ALL, {0xffff, 0x4e71}, {0}, {ofNone}, "NOP"},
1361: { MC_ALL, {0xffff, 0x4e72}, {2}, {ofI}, "STOP"},
1362: { MC_ALL, {0xffff, 0x4e73}, {0}, {ofNone}, "RTE"},
1363: { MC68010|MC_020, {0xffff, 0x4e74}, {2}, {ofI}, "RTD"},
1364: { MC_ALL, {0xffff, 0x4e75}, {0}, {ofNone}, "RTS"},
1365: { MC_ALL, {0xffff, 0x4e76}, {0}, {ofNone}, "TRAPV"},
1366: { MC_ALL, {0xffff, 0x4e77}, {0}, {ofNone}, "RTR"},
1367: { MC68010|MC_020, {0xffff, 0x4e7a, 0x10000}, {4}, {ofSpecExtReg,ofExtReg}, "MOVEC"},
1368: { MC68010|MC_020, {0xffff, 0x4e7b, 0x10000}, {4}, {ofExtReg,ofSpecExtReg}, "MOVEC"},
1369: { MC_ALL, {0xffc0, 0x4e80}, {0}, {ofEa}, "JSR",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1370: { MC_ALL, {0xffc0, 0x4ec0}, {0}, {ofEa}, "JMP",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1371:
1372: { MC_ALL, {0xf1c0, 0x5000}, {1}, {ofI3,ofEa}, "ADDQ.B",{0,EA_An|EA_Immed|EA_PCRel} },
1373: { MC_ALL, {0xf1c0, 0x5040}, {2}, {ofI3,ofEa}, "ADDQ.W",{0,EA_Immed|EA_PCRel} },
1374: { MC_ALL, {0xf1c0, 0x5080}, {4}, {ofI3,ofEa}, "ADDQ.L",{0,EA_Immed|EA_PCRel} },
1375: { MC_ALL, {0xf0c0, 0x50C0}, {1}, {ofEa}, "Sci",{EA_Immed|EA_PCRel|EA_An}},
1376: { MC_ALL, {0xf0f8, 0x50C8}, {2}, {ofDn,ofDisp}, "DBcd"},
1377: { MC_020, {0xf0ff, 0x50fa}, {2}, {ofI}, "TRAPci.W"},
1378: { MC_020, {0xf0ff, 0x50fb}, {4}, {ofI}, "TRAPci.L"},
1379: { MC_020, {0xf0ff, 0x50fc}, {0}, {ofNone}, "TRAPci"},
1380: { MC_ALL, {0xf1c0, 0x5100}, {1}, {ofI3,ofEa}, "SUBQ.B",{0,EA_An|EA_Immed|EA_PCRel} },
1381: { MC_ALL, {0xf1c0, 0x5140}, {2}, {ofI3,ofEa}, "SUBQ.W",{0,EA_Immed|EA_PCRel} },
1382: { MC_ALL, {0xf1c0, 0x5180}, {4}, {ofI3,ofEa}, "SUBQ.L",{0,EA_Immed|EA_PCRel} },
1383:
1384: { MC_ALL, {0xf0ff, 0x6000}, {2}, {ofDisp}, "Bcb"},
1385: { MC_ALL, {0xf000, 0x6000}, {1}, {ofDisp}, "Bcb.S"},
1386: { MC_020, {0xf0ff, 0x60FF}, {4}, {ofDisp}, "Bcb.L"},
1387:
1388: { MC_ALL, {0xf100, 0x7000}, {0}, {ofIOpcode,ofDestDn}, "MOVEQ", {0xFF,0}},
1389:
1390: { MC_ALL, {0xf100, 0x8000}, {-1,6,2,0}, {ofEa,ofDestDn}, "OR.?", {EA_An,0}},
1391: { MC_ALL, {0xf100, 0x8100}, {-1,6,2,0}, {ofDestDn,ofEa}, "OR.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1392: { MC_ALL, {0xf1f8, 0x8100}, {1}, {ofDn,ofDestDn}, "SBCD"},
1393: { MC_ALL, {0xf1f8, 0x8108}, {1}, {ofPiAn,ofDestPiAn}, "SBCD"},
1394: { MC_020&~MC_CPU32, {0xf1f8, 0x8140, 0x10000}, {0}, {ofDn,ofDestDn,ofExtIm}, "PACK"},
1395: { MC_020&~MC_CPU32, {0xf1f8, 0x8148, 0x10000}, {0}, {ofPiAn,ofDestPiAn,ofExtIm}, "PACK"},
1396: { MC_020&~MC_CPU32, {0xf1f8, 0x8180, 0x10000}, {0}, {ofDn,ofDestDn,ofExtIm}, "UNPK"},
1397: { MC_020&~MC_CPU32, {0xf1f8, 0x8188, 0x10000}, {0}, {ofPiAn,ofDestPiAn,ofExtIm}, "UNPK"},
1398: { MC_ALL, {0xf1c0, 0x80c0}, {2}, {ofEa,ofDestDn}, "DIVU.W", {EA_An,0}},
1399: { MC_ALL, {0xf1c0, 0x81c0}, {2}, {ofEa,ofDestDn}, "DIVS.W", {EA_An,0}},
1400:
1401: { MC_ALL, {0xf1c0, 0x9000}, {1}, {ofEa,ofDestDn}, "SUB.B", {EA_An,0}},
1402: { MC_ALL, {0xf1c0, 0x9040}, {2}, {ofEa,ofDestDn}, "SUB.W"},
1403: { MC_ALL, {0xf1c0, 0x9080}, {4}, {ofEa,ofDestDn}, "SUB.L"},
1404: { MC_ALL, {0xf1c0, 0x90c0}, {2}, {ofEa,ofDestAn}, "SUBA.W"},
1405: { MC_ALL, {0xf1c0, 0x91c0}, {4}, {ofEa,ofDestAn}, "SUBA.L"},
1406: { MC_ALL, {0xf100, 0x9100}, {-1,6,2,0}, {ofDestDn,ofEa}, "SUB.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1407: { MC_ALL, {0xf138, 0x9100}, {-1,6,2,0}, {ofDn,ofDestDn}, "SUBX.?"},
1408: { MC_ALL, {0xf138, 0x9108}, {-1,6,2,0}, {ofPiAn,ofDestPiAn}, "SUBX.?"},
1409:
1410: { MC_ALL, {0xf000, 0xa000}, {0}, {ofLineA}, "LINEA"},
1411:
1412: { MC_ALL, {0xf1c0, 0xb000}, {1}, {ofEa,ofDestDn}, "CMP.B", {EA_An,0}},
1413: { MC_ALL, {0xf1c0, 0xb040}, {2}, {ofEa,ofDestDn}, "CMP.W"},
1414: { MC_ALL, {0xf1c0, 0xb080}, {4}, {ofEa,ofDestDn}, "CMP.L"},
1415: { MC_ALL, {0xf1c0, 0xb0c0}, {2}, {ofEa,ofDestAn}, "CMPA.W"},
1416: { MC_ALL, {0xf1c0, 0xb1c0}, {4}, {ofEa,ofDestAn}, "CMPA.L"},
1417: { MC_ALL, {0xf100, 0xb100}, {-1,6,2,0}, {ofDestDn,ofEa}, "EOR.?",{0,EA_An|EA_Immed|EA_PCRel} },
1418: { MC_ALL, {0xf138, 0xb108}, {-1,6,2,0}, {ofAnip,ofDestAnip}, "CMPM.?"},
1419:
1420: { MC_ALL, {0xf100, 0xc000}, {-1,6,2,0}, {ofEa,ofDestDn}, "AND.?", {EA_An,0}},
1421: { MC_ALL, {0xf100, 0xc100}, {-1,6,2,0}, {ofDestDn,ofEa}, "AND.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1422: { MC_ALL, {0xf1f8, 0xc100}, {1}, {ofDn,ofDestDn}, "ABCD"},
1423: { MC_ALL, {0xf1f8, 0xc108}, {1}, {ofPiAn,ofDestPiAn}, "ABCD"},
1424: { MC_ALL, {0xf1f8, 0xc140}, {1}, {ofDestDn,ofDn}, "EXG"},
1425: { MC_ALL, {0xf1f8, 0xc148}, {1}, {ofDestAn,ofAn}, "EXG"},
1426: { MC_ALL, {0xf1f8, 0xc188}, {1}, {ofDestDn,ofAn}, "EXG"},
1427: { MC_ALL, {0xf1c0, 0xc0c0}, {2}, {ofEa,ofDestDn}, "MULU.W", {EA_An,0}},
1428: { MC_ALL, {0xf1c0, 0xc1c0}, {2}, {ofEa,ofDestDn}, "MULS.W", {EA_An,0}},
1429:
1430: { MC_ALL, {0xf1c0, 0xd000}, {1}, {ofEa,ofDestDn}, "ADD.B", {EA_An,0}},
1431: { MC_ALL, {0xf1c0, 0xd040}, {2}, {ofEa,ofDestDn}, "ADD.W"},
1432: { MC_ALL, {0xf1c0, 0xd080}, {4}, {ofEa,ofDestDn}, "ADD.L"},
1433: { MC_ALL, {0xf1c0, 0xd0c0}, {2}, {ofEa,ofDestAn}, "ADDA.W"},
1434: { MC_ALL, {0xf1c0, 0xd1c0}, {4}, {ofEa,ofDestAn}, "ADDA.L"},
1435: { MC_ALL, {0xf100, 0xd100}, {-1,6,2,0}, {ofDestDn,ofEa}, "ADD.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1436: { MC_ALL, {0xf138, 0xd100}, {-1,6,2,0}, {ofDn,ofDestDn}, "ADDX.?"},
1437: { MC_ALL, {0xf138, 0xd108}, {-1,6,2,0}, {ofPiAn,ofDestPiAn}, "ADDX.?"},
1438:
1439: { MC_ALL, {0xf138, 0xe000}, {-1,6,2,0}, {ofI3,ofDn}, "ASR.?"},
1440: { MC_ALL, {0xf138, 0xe008}, {-1,6,2,0}, {ofI3,ofDn}, "LSR.?"},
1441: { MC_ALL, {0xf138, 0xe010}, {-1,6,2,0}, {ofI3,ofDn}, "ROXR.?"},
1442: { MC_ALL, {0xf138, 0xe018}, {-1,6,2,0}, {ofI3,ofDn}, "ROR.?"},
1443: { MC_ALL, {0xf138, 0xe020}, {-1,6,2,0}, {ofDestDn,ofDn}, "ASR.?"},
1444: { MC_ALL, {0xf138, 0xe028}, {-1,6,2,0}, {ofDestDn,ofDn}, "LSR.?"},
1445: { MC_ALL, {0xf138, 0xe030}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROXR.?"},
1446: { MC_ALL, {0xf138, 0xe038}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROR.?"},
1447: { MC_ALL, {0xf138, 0xe100}, {-1,6,2,0}, {ofI3,ofDn}, "ASL.?"},
1448: { MC_ALL, {0xf138, 0xe108}, {-1,6,2,0}, {ofI3,ofDn}, "LSL.?"},
1449: { MC_ALL, {0xf138, 0xe110}, {-1,6,2,0}, {ofI3,ofDn}, "ROXL.?"},
1450: { MC_ALL, {0xf138, 0xe118}, {-1,6,2,0}, {ofI3,ofDn}, "ROL.?"},
1451: { MC_ALL, {0xf138, 0xe120}, {-1,6,2,0}, {ofDestDn,ofDn}, "ASL.?"},
1452: { MC_ALL, {0xf138, 0xe128}, {-1,6,2,0}, {ofDestDn,ofDn}, "LSL.?"},
1453: { MC_ALL, {0xf138, 0xe130}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROXL.?"},
1454: { MC_ALL, {0xf138, 0xe138}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROL.?"},
1455: { MC_ALL, {0xffc0, 0xe0c0}, {1}, {ofEa}, "ASR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1456: { MC_ALL, {0xffc0, 0xe1c0}, {1}, {ofEa}, "ASL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1457: { MC_ALL, {0xffc0, 0xe2c0}, {1}, {ofEa}, "LSR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1458: { MC_ALL, {0xffc0, 0xe3c0}, {1}, {ofEa}, "LSL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1459: { MC_ALL, {0xffc0, 0xe4c0}, {1}, {ofEa}, "ROXR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1460: { MC_ALL, {0xffc0, 0xe5c0}, {1}, {ofEa}, "ROXL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1461: { MC_ALL, {0xffc0, 0xe6c0}, {1}, {ofEa}, "ROR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1462: { MC_ALL, {0xffc0, 0xe7c0}, {1}, {ofEa}, "ROL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1463: { MC_020&~MC_CPU32, {0xffc0, 0xe8c0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFTST",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1464: { MC_020&~MC_CPU32, {0xffc0, 0xe9c0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFEXTU",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1465: { MC_020&~MC_CPU32, {0xffc0, 0xeac0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFCHG",{EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1466: { MC_020&~MC_CPU32, {0xffc0, 0xebc0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFEXTS",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1467: { MC_020&~MC_CPU32, {0xffc0, 0xecc0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFCLR",{EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1468: { MC_020&~MC_CPU32, {0xffc0, 0xedc0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFFFO",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1469: { MC_020&~MC_CPU32, {0xffc0, 0xeec0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFSET",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1470: { MC_020&~MC_CPU32, {0xffc0, 0xefc0, 0x8000, 0x0000}, {1}, {ofExtReg,ofBFEa}, "BFINS",{0,EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1471:
1472:
1473: #define PMMU_COPROC_ID 0 // 0 is the standard PMMU
1474:
1475: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2000}, {0}, {ofSpecReg,ofEa}, "PLOADW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1476: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2001}, {0}, {ofSpecReg,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1477: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2008}, {0}, {ofExtReg0,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1478: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff0, 0x2010}, {0}, {ofExtIm4,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1479:
1480: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2200}, {0}, {ofSpecReg,ofEa}, "PLOADR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1481: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2201}, {0}, {ofSpecReg,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1482: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2208}, {0}, {ofExtReg0,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1483: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff0, 0x2210}, {0}, {ofExtIm4,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1484:
1485: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0xa000}, {0}, {ofEa}, "PFLUSHR",{EA_Dn|EA_An} },
1486:
1487: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0800}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1488: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0900}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1489: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0B00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1490: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0C00}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1491: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0C00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1492: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0D00}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1493: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0E00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1494: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0F00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1495: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4000}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1496: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4100}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1497: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4200}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1498: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4300}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1499: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4800}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1500: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4900}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1501: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4A00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1502: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4B00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1503: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4C00}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1504: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4D00}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1505: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4e00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1506: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4f00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1507: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x6000}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_MMUSR} },
1508: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x6200}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_MMUSR} },
1509:
1510: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2800}, {0}, {ofSpecReg,ofEa}, "PVALID",{REG_VAL,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1511: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2C00}, {0}, {ofExtRegA0,ofEa}, "PVALID",{0,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1512:
1513: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8000}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1514: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8001}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1515: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f8, 0x8008}, {0}, {ofExtReg0,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1516: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f0, 0x8010}, {0}, {ofExtIm4,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1517:
1518: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8200}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1519: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8201}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1520: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f8, 0x8208}, {0}, {ofExtReg0,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1521: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f0, 0x8210}, {0}, {ofExtIm4,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1522:
1523: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8100}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1524: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8101}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1525: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe318, 0x8108}, {0}, {ofExtReg0,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1526: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe310, 0x8110}, {0}, {ofExtIm4,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1527:
1528: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8300}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1529: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8301}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1530: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe318, 0x8308}, {0}, {ofExtReg0,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1531: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe310, 0x8310}, {0}, {ofExtIm4,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1532:
1533: { MC_PMMU, {0xffc0, 0xf040|(PMMU_COPROC_ID<<9), 0xfff0, 0x8310}, {0}, {ofEa}, "PScp",{EA_An|EA_Immed|EA_PCRel} },
1534: { MC_PMMU, {0xfff8, 0xf048|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000}, {2}, {ofDn,ofDisp}, "PDBcp"},
1535: { MC_PMMU, {0xffff, 0xf07A|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {2}, {ofExtIm32}, "PTRAPcp.W" },
1536: { MC_PMMU, {0xffff, 0xf07B|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {4}, {ofExtIm32}, "PTRAPcp.L" },
1537: { MC_PMMU, {0xffff, 0xf07C|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000}, {0}, {ofNone}, "PTRAPcp" },
1538: { MC_PMMU, {0xfff0, 0xf080|(PMMU_COPROC_ID<<9)}, {2}, {ofDisp}, "PBcp.W"},
1539: { MC_PMMU, {0xfff0, 0xf0C0|(PMMU_COPROC_ID<<9)}, {4}, {ofDisp}, "PBcp.L"},
1540: { MC_PMMU, {0xffc0, 0xf100|(PMMU_COPROC_ID<<9)}, {0}, {ofEa}, "PSAVE",{EA_Dn|EA_An|EA_Anip|EA_Immed} },
1541: { MC_PMMU, {0xffc0, 0xf140|(PMMU_COPROC_ID<<9)}, {0}, {ofEa}, "PRESTORE",{EA_Dn|EA_An|EA_piAn|EA_Immed} },
1542:
1543:
1544: #define MC040_COPROC_ID 3 // 3 is the code for some 68040/68060 opcodes
1545:
1546: { MC68040|MC68060, {0xfff8, 0xf000|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAnip,ofDestAbsL}, "MOVE16"},
1547: { MC68040|MC68060, {0xfff8, 0xf008|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofDestAbsL,ofAnip}, "MOVE16"},
1548: { MC68040|MC68060, {0xfff8, 0xf010|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAni,ofDestAbsL}, "MOVE16"},
1549: { MC68040|MC68060, {0xfff8, 0xf018|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofDestAbsL,ofAni}, "MOVE16"},
1550: { MC68040|MC68060, {0xfff8, 0xf020|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAnip,ofExtAnip}, "MOVE16"},
1551:
1552:
1553: #define CPU32_COPROC_ID 4 // 4 is the code for some CPU32 opcodes
1554:
1555: { MC68040|MC68060, {0xfff8, 0xf008|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_NONE} },
1556: { MC68040|MC68060, {0xfff8, 0xf048|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_DC} },
1557: { MC68040|MC68060, {0xfff8, 0xf088|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_IC} },
1558: { MC68040|MC68060, {0xfff8, 0xf0C8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_ICDC} },
1559:
1560: { MC68040|MC68060, {0xfff8, 0xf010|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_NONE} },
1561: { MC68040|MC68060, {0xfff8, 0xf050|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_DC} },
1562: { MC68040|MC68060, {0xfff8, 0xf090|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_IC} },
1563: { MC68040|MC68060, {0xfff8, 0xf0D0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_ICDC} },
1564:
1565: { MC68040|MC68060, {0xfff8, 0xf018|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_NONE} },
1566: { MC68040|MC68060, {0xfff8, 0xf058|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_DC} },
1567: { MC68040|MC68060, {0xfff8, 0xf098|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_IC} },
1568: { MC68040|MC68060, {0xfff8, 0xf0D8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_ICDC} },
1569:
1570: { MC68040|MC68060, {0xfff8, 0xf028|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_NONE} },
1571: { MC68040|MC68060, {0xfff8, 0xf068|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_DC} },
1572: { MC68040|MC68060, {0xfff8, 0xf0A8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_IC} },
1573: { MC68040|MC68060, {0xfff8, 0xf0E8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_ICDC} },
1574:
1575: { MC68040|MC68060, {0xfff8, 0xf030|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_NONE} },
1576: { MC68040|MC68060, {0xfff8, 0xf070|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_DC} },
1577: { MC68040|MC68060, {0xfff8, 0xf0B0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_IC} },
1578: { MC68040|MC68060, {0xfff8, 0xf0F0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_ICDC} },
1579:
1580: { MC68040|MC68060, {0xfff8, 0xf038|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_NONE} },
1581: { MC68040|MC68060, {0xfff8, 0xf078|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_DC} },
1582: { MC68040|MC68060, {0xfff8, 0xf0B8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_IC} },
1583: { MC68040|MC68060, {0xfff8, 0xf0F8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_ICDC} },
1584:
1585: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f08, 0x0100}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLU.?" },
1586: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0100}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLU.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1587: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f28, 0x0500}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLUN.?" },
1588: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0500}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLUN.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1589:
1590: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f08, 0x0900}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLS.?" },
1591: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0900}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLS.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1592: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f28, 0x0D00}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLSN.?" },
1593: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0D00}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLSN.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1594:
1595: { MC_CPU32, {0xffff, 0xf000|(CPU32_COPROC_ID<<9), 0xffff, 0x01C0}, {2}, {ofI}, "LPSTOP" },
1596:
1597:
1598: #define FPU_COPROC_ID 1 // 1 is the standard FPU, required to be 1 for the 68040 anyway
1599:
1600: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0000}, {-1,16+10,3,1}, {ofFPU}, "FMOVE.?" },
1601: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0001}, {-1,16+10,3,1}, {ofFPU}, "FINT.?" },
1602: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0002}, {-1,16+10,3,1}, {ofFPU}, "FSINH.?" },
1603: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0003}, {-1,16+10,3,1}, {ofFPU}, "FINTRZ.?" },
1604: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0004}, {-1,16+10,3,1}, {ofFPU}, "FSQRT.?" },
1605: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0006}, {-1,16+10,3,1}, {ofFPU}, "FLOGNP1.?" },
1606: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0008}, {-1,16+10,3,1}, {ofFPU}, "FETOXM1.?" },
1607: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0009}, {-1,16+10,3,1}, {ofFPU}, "FTANH.?" },
1608: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000A}, {-1,16+10,3,1}, {ofFPU}, "FATAN.?" },
1609: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000C}, {-1,16+10,3,1}, {ofFPU}, "FASIN.?" },
1610: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000D}, {-1,16+10,3,1}, {ofFPU}, "FATANH.?" },
1611: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000E}, {-1,16+10,3,1}, {ofFPU}, "FSIN.?" },
1612: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000F}, {-1,16+10,3,1}, {ofFPU}, "FTAN.?" },
1613: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0010}, {-1,16+10,3,1}, {ofFPU}, "FETOX.?" },
1614: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0011}, {-1,16+10,3,1}, {ofFPU}, "FTWOTOX.?" },
1615: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0012}, {-1,16+10,3,1}, {ofFPU}, "FTENTOX.?" },
1616: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0014}, {-1,16+10,3,1}, {ofFPU}, "FLOGN.?" },
1617: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0015}, {-1,16+10,3,1}, {ofFPU}, "FLOG10.?" },
1618: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0016}, {-1,16+10,3,1}, {ofFPU}, "FLOG2.?" },
1619: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0018}, {-1,16+10,3,1}, {ofFPU}, "FABS.?" },
1620: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0019}, {-1,16+10,3,1}, {ofFPU}, "FCOSH.?" },
1621: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001A}, {-1,16+10,3,1}, {ofFPU}, "FNEG.?" },
1622: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001C}, {-1,16+10,3,1}, {ofFPU}, "FACOS.?" },
1623: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001D}, {-1,16+10,3,1}, {ofFPU}, "FCOS.?" },
1624: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001E}, {-1,16+10,3,1}, {ofFPU}, "FGETEXP.?" },
1625: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001F}, {-1,16+10,3,1}, {ofFPU}, "FGETMAN.?" },
1626: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0020}, {-1,16+10,3,1}, {ofFPU}, "FDIV.?" },
1627: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0021}, {-1,16+10,3,1}, {ofFPU}, "FMOD.?" },
1628: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0022}, {-1,16+10,3,1}, {ofFPU}, "FADD.?" },
1629: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0023}, {-1,16+10,3,1}, {ofFPU}, "FMUL.?" },
1630: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0024}, {-1,16+10,3,1}, {ofFPU}, "FSGLDIV.?" },
1631: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0025}, {-1,16+10,3,1}, {ofFPU}, "FREM.?" },
1632: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0026}, {-1,16+10,3,1}, {ofFPU}, "FSCALE.?" },
1633: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0027}, {-1,16+10,3,1}, {ofFPU}, "FSGLMUL.?" },
1634: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0028}, {-1,16+10,3,1}, {ofFPU}, "FSUB.?" },
1635: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA078,0x0030}, {-1,16+10,3,1}, {ofFPU3Reg}, "FSINCOS.?" },
1636: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0038}, {-1,16+10,3,1}, {ofFPU}, "FCMP.?" },
1637: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x003A}, {-1,16+10,3,1}, {ofFPU}, "FTST.?" },
1638: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0040}, {-1,16+10,3,1}, {ofFPU}, "FSMOVE.?" },
1639: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0041}, {-1,16+10,3,1}, {ofFPU}, "FSSQRT.?" },
1640: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0042}, {-1,16+10,3,1}, {ofFPU}, "FSADD.?" },
1641: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0044}, {-1,16+10,3,1}, {ofFPU}, "FDMOVE.?" },
1642: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0045}, {-1,16+10,3,1}, {ofFPU}, "FDSQRT.?" },
1643: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0046}, {-1,16+10,3,1}, {ofFPU}, "FDADD.?" },
1644: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0058}, {-1,16+10,3,1}, {ofFPU}, "FSABS.?" },
1645: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005A}, {-1,16+10,3,1}, {ofFPU}, "FSNEG.?" },
1646: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005C}, {-1,16+10,3,1}, {ofFPU}, "FDABS.?" },
1647: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005E}, {-1,16+10,3,1}, {ofFPU}, "FDNEG.?" },
1648: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0060}, {-1,16+10,3,1}, {ofFPU}, "FSDIV.?" },
1649: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0063}, {-1,16+10,3,1}, {ofFPU}, "FSMUL.?" },
1650: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0064}, {-1,16+10,3,1}, {ofFPU}, "FDDIV.?" },
1651: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0067}, {-1,16+10,3,1}, {ofFPU}, "FDMUL.?" },
1652: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0068}, {-1,16+10,3,1}, {ofFPU}, "FSSUB.?" },
1653: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x006C}, {-1,16+10,3,1}, {ofFPU}, "FDSUB.?" },
1654: { MC68040|MC_FPU, {0xffff, 0xf000|(FPU_COPROC_ID<<9),0xFC00,0x5C00}, {0}, {ofFMOVECR}, "FMOVECR" },
1655:
1656: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE000,0x6000}, {-1,16+10,3,1}, {ofFPUMOVE}, "FMOVE.?" },
1657:
1658: // these 3 are special versions of MOVEM with just one register, they have to be before the FMOVEM version
1659: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x8400}, {0}, {ofEa,ofSpecReg}, "FMOVE", {0,REG_FPU_FPIAR} },
1660: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x8800}, {0}, {ofEa,ofSpecReg}, "FMOVE", {EA_An,REG_FPU_FPSR} },
1661: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x9000}, {0}, {ofEa,ofSpecReg}, "FMOVE", {EA_An,REG_FPU_FPCR} },
1662: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE3FF,0x8000}, {0}, {ofEa,ofFPUSRRegList}, "FMOVEM", {EA_Dn|EA_An,0} },
1663: // these 3 are special versions of MOVEM with just one register, they have to be before the FMOVEM version
1664: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xA400}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPIAR,EA_Immed|EA_PCRel} },
1665: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xA800}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPSR,EA_An|EA_Immed|EA_PCRel} },
1666: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xB000}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPCR,EA_An|EA_Immed|EA_PCRel} },
1667: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE3FF,0xA000}, {0}, {ofFPUSRRegList,ofEa}, "FMOVEM", {0,EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1668:
1669: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE00,0xC000}, {0}, {ofFPUReglist,ofEa}, "FMOVEM.X",{0,EA_Dn|EA_An|EA_Anip|EA_Immed} },
1670: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE8F,0xC800}, {0}, {ofExtRegD04,ofEa}, "FMOVEM.X",{0,EA_Dn|EA_An|EA_piAn|EA_Immed} },
1671: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE00,0xE000}, {0}, {ofEa,ofFPUReglist}, "FMOVEM.X",{EA_Dn|EA_An|EA_piAn|EA_Immed,0} },
1672: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE8F,0xE800}, {0}, {ofEa,ofExtRegD04}, "FMOVEM.X",{EA_Dn|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1673:
1674: { MC68040|MC_FPU, {0xffc0, 0xf040|(FPU_COPROC_ID<<9),0xFFC0,0x0000}, {0}, {ofEa}, "FScf.B",{EA_An|EA_Immed|EA_PCRel} },
1675: { MC68040|MC_FPU, {0xfff8, 0xf048|(FPU_COPROC_ID<<9),0xFFC0,0x0000}, {2}, {ofDn,ofDisp}, "FDBcf" },
1676: { MC68040|MC_FPU, {0xffff, 0xf07A|(FPU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {2}, {ofExtIm32}, "FTRAPcf.W" },
1677: { MC68040|MC_FPU, {0xffff, 0xf07B|(FPU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {4}, {ofExtIm32}, "FTRAPcf.L" },
1678: { MC68040|MC_FPU, {0xffff, 0xf07C|(FPU_COPROC_ID<<9), 0xfff0, 0x0000}, {0}, {ofNone}, "FTRAPcf" },
1679:
1680: // FNOP _has_ to be before FBcf.W, not worth to have a special case for that one
1681: { MC68040|MC_FPU, {0xffff, 0xf080|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {0}, {ofNone}, "FNOP" },
1682: { MC68040|MC_FPU, {0xffc0, 0xf080|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {2}, {ofDisp}, "FBcF.W" },
1683: { MC68040|MC_FPU, {0xffc0, 0xf0c0|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {4}, {ofDisp}, "FBcF.L" },
1684: { MC68040|MC68060|MC_FPU, {0xffc0, 0xf100|(FPU_COPROC_ID<<9)}, {0}, {ofEa}, "FSAVE", {EA_Dn|EA_An|EA_piAn|EA_Immed} },
1685: { MC68040|MC68060|MC_FPU, {0xffc0, 0xf140|(FPU_COPROC_ID<<9)}, {0}, {ofEa}, "FRESTORE", {EA_Dn|EA_An|EA_piAn|EA_Immed} },
1686:
1687: { }
1688: };
1689:
1690: static int Disass68k(long addr, char *labelBuffer, char *opcodeBuffer, char *operandBuffer, char *commentBuffer)
1691: {
1692: long baseAddr = addr;
1693: int val;
1694: const char *sp;
1695: labelBuffer[0] = 0;
1696: opcodeBuffer[0] = 0;
1697: operandBuffer[0] = 0;
1698: commentBuffer[0] = 0;
1699: int i;
1700:
1701: int count = 0;
1702: char addressLabel[256];
1703: char cmtBuffer[256];
1704: Disass68kDataType type = Disass68kType(baseAddr, addressLabel, cmtBuffer, &count);
1705: if(addressLabel[0])
1706: sprintf(labelBuffer, "%s:", addressLabel);
1707: sprintf(commentBuffer, "%s", cmtBuffer);
1708: switch(type)
1709: {
1710: case dtByte:if(count > 8)
1711: count = 8;
1712: strcpy(opcodeBuffer,"DC.B");
1713: for(i=0; i<count; ++i)
1714: {
1715: if((i & 7) > 0)
1716: strcat(operandBuffer, ",");
1717: char hbuf[16];
1718: unsigned short val = Disass68kGetWord(addr+(i & ~1));
1719: if(i & 1)
1720: val &= 0xFF;
1721: else
1722: val = val >> 8;
1723: sprintf(hbuf,"$%2.2x", val);
1724: strcat(operandBuffer, hbuf);
1725: }
1726: return count;
1727:
1728: case dtWord:if(count > 4)
1729: count = 4;
1730: strcpy(opcodeBuffer,"DC.W");
1731: for(i=0; i<count; ++i)
1732: {
1733: if((i & 3) > 0)
1734: strcat(operandBuffer, ",");
1735: char hbuf[16];
1736: sprintf(hbuf,"$%4.4x", Disass68kGetWord(addr+i*2));
1737: strcat(operandBuffer, hbuf);
1738: }
1739: return count * 2;
1740:
1741: case dtLong:if(count > 2)
1742: count = 2;
1743: strcpy(opcodeBuffer,"DC.L");
1744: for(i=0; i<count; ++i)
1745: {
1746: if((i & 1) > 0)
1747: strcat(operandBuffer, ",");
1748: char hbuf[16];
1749: sprintf(hbuf,"$%8.8x", (Disass68kGetWord(addr+i*4) << 16) | Disass68kGetWord(addr+i*4+2));
1750: strcat(operandBuffer, hbuf);
1751: }
1752: return count * 4;
1753:
1754: case dtStringArray:
1755: {
1756: strcpy(opcodeBuffer,"DC.B");
1757: strcat(operandBuffer, "'");
1758: char *sp = operandBuffer + strlen(operandBuffer);
1759: for(i=0; i < count; ++i)
1760: {
1761: unsigned short val = Disass68kGetWord(addr+(i & ~1));
1762: if(i & 1)
1763: val &= 0xFF;
1764: else
1765: val = val >> 8;
1766: if(val == 0)
1767: break;
1768: switch(val)
1769: {
1770: case 9: *sp++ = '\\'; *sp++ = 't'; break;
1771: case 10: *sp++ = '\\'; *sp++ = 'n'; break;
1772: case 13: *sp++ = '\\'; *sp++ = 'r'; break;
1773: default:
1774: if(val >= 0x20 && val <= 0x7E)
1775: *sp++ = val;
1776: }
1777: }
1778: *sp = 0;
1779: strcat(sp, "'");
1780: return count;
1781: }
1782:
1783: case dtASCString:
1784: {
1785: int count = 1;
1786: unsigned short val = Disass68kGetWord(addr+0);
1787: strcpy(opcodeBuffer,"DC.B");
1788: if((val >> 8) == 0)
1789: {
1790: strcat(operandBuffer, "0");
1791: } else {
1792: strcat(operandBuffer, "'");
1793: char *sp = operandBuffer + strlen(operandBuffer);
1794: for(i=0; ; ++i)
1795: {
1796: unsigned short val = Disass68kGetWord(addr+(i & ~1));
1797: if(i & 1)
1798: val &= 0xFF;
1799: else
1800: val = val >> 8;
1801: if(val == 0)
1802: break;
1803: switch(val)
1804: {
1805: case 9: *sp++ = '\\'; *sp++ = 't'; break;
1806: case 10: *sp++ = '\\'; *sp++ = 'n'; break;
1807: case 13: *sp++ = '\\'; *sp++ = 'r'; break;
1808: default:
1809: if(val >= 0x20 && val <= 0x7E)
1810: *sp++ = val;
1811: }
1812: ++count;
1813: }
1814: *sp = 0;
1815: strcat(sp, "',0");
1816: }
1817: return (count + 1) & ~1;
1818: }
1819:
1820: case dtPointer:
1821: case dtFunctionPointer:
1822: val = (Disass68kGetWord(addr) << 16) | Disass68kGetWord(addr+2);
1823: sp = Disass68kSymbolName(val, 2);
1824: strcpy(opcodeBuffer,"DC.L");
1825: if(sp)
1826: sprintf(operandBuffer,"%s", sp);
1827: else
1828: sprintf(operandBuffer,"$%6.6x", val);
1829: return 4;
1830:
1831: default: break;
1832: }
1833:
1834: int index = 0;
1835: long opcodeAddr = addr;
1836: more:
1837: addr = opcodeAddr;
1838:
1839: opcodeBuffer[0] = 0;
1840: operandBuffer[0] = 0;
1841:
1842: commentBuffer[0] = 0;
1843: if(cmtBuffer[0])
1844: sprintf(commentBuffer, "%s ", cmtBuffer);
1845:
1846: while(1)
1847: {
1848: OpcodeTableStruct *ots = &OpcodeTable[index++];
1849: if(ots->opcodeName == NULL)
1850: break;
1851: if((ots->cpuMask & optionCPUTypeMask) == 0) // CPU doesn't match?
1852: continue;
1853:
1854: // search for the opcode plus up to 2 extension words
1855: unsigned short opcode[5] = {};
1856: unsigned int i;
1857: for(i=0; i<5; ++i)
1858: {
1859: if(!ots->opcodeMask[i*2])
1860: break;
1861: opcode[i] = Disass68kGetWord(addr);
1862: if(((ots->opcodeMask[i*2] & 0xFFFF) & opcode[i]) != ots->opcodeMask[i*2+1])
1863: goto more;
1864: addr += 2;
1865: }
1866:
1867: // find out the size of the opcode operand
1868: int size = ots->operationSize[0];
1869: char sizeChar = 0;
1870: if(size < 0) // custom size?
1871: {
1872: int opcodeOffset = ots->operationSize[1] >> 4;
1873: int bitShiftOffset = ots->operationSize[1] & 0x0F;
1874: int sizeBitMask = (opcode[opcodeOffset] >> bitShiftOffset) & ((1 << ots->operationSize[2]) - 1);
1875: switch(ots->operationSize[3])
1876: {
1877: case 0: // 2 Bit Size
1878: switch(sizeBitMask)
1879: {
1880: case 0: size = 1; sizeChar = 'B'; break;
1881: case 1: size = 2; sizeChar = 'W'; break;
1882: case 2: size = 4; sizeChar = 'L'; break;
1883: case 3: goto more; // illegal size mask
1884: }
1885: break;
1886: case 1: // 3 Bit FPU Size
1887: if((opcode[1] & 0x4000) == 0x0000) // Register => Register?
1888: sizeBitMask = 2; // => 'X' Format
1889: switch(sizeBitMask)
1890: {
1891: case 0: size = 4; sizeChar = 'L'; break;
1892: case 1: size = 4; sizeChar = 'S'; break;
1893: case 2: size = 12; sizeChar = 'X'; break;
1894: case 7: if((opcode[1] & 0xE000) != 0x6000) // MOVE.P <ea>,FPn{Dn-Factor}
1895: goto more; // illegal size mask
1896: case 3: size = 12; sizeChar = 'P'; break;
1897: case 4: size = 2; sizeChar = 'W'; break;
1898: case 5: size = 8; sizeChar = 'D'; break;
1899: case 6: size = 1; sizeChar = 'B'; break;
1900: }
1901: break;
1902: }
1903: }
1904:
1905: // copy the opcode plus a necessary TAB for the operand
1906: char *dbuf = opcodeBuffer;
1907: for(i=0; ots->opcodeName[i]; ++i)
1908: {
1909: char c = ots->opcodeName[i];
1910: if(c == 'c') // condition code
1911: {
1912: static const char *pmmuCond[16] = { "BS", "BC", "LS", "LC", "SS", "SC", "AS", "AC", "WS", "WC", "IS", "IC", "GS", "GC", "CS", "CC" };
1913: static const char *braCond[16] = { "RA", "SR", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1914: static const char *sccCond[16] = { "T", "F", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1915: static const char *dbCond[16] = { "T", "RA", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1916: static const char *fpuCond[64] = { "F", "EQ", "OGT", "OGE", "OLT", "OLE", "OGL", "OR", "UN", "UEQ", "UGT", "UGE", "ULT", "ULE", "NE", "T", "SF", "SEQ", "GT", "GE", "LT", "LE", "GL", "GLE", "NGLE", "NGL", "NLE", "NLT", "NGE", "NGT", "SNE", "ST" };
1917:
1918: const char *sp = NULL;
1919: switch(ots->opcodeName[++i])
1920: {
1921: case 'p': // PMMU conditions
1922: sp = pmmuCond[opcode[1] & 0xF];
1923: break;
1924: case 'b': // BRA conditions
1925: sp = braCond[(opcode[0] >> 8) & 0xF];
1926: break;
1927: case 'i': // Scc,TRAPcc conditions
1928: sp = sccCond[(opcode[0] >> 8) & 0xF];
1929: break;
1930: case 'd': // DBcc conditions
1931: sp = dbCond[(opcode[0] >> 8) & 0xF];
1932: break;
1933: case 'F': // FPU conditions (first word)
1934: sp = fpuCond[opcode[0] & 0x3F];
1935: break;
1936: case 'f': // FPU conditions (second word)
1937: sp = fpuCond[opcode[1] & 0x3F];
1938: break;
1939: }
1940: if(sp)
1941: {
1942: if(options & doptOpcodesSmall)
1943: {
1944: char buf[8];
1945: strcpy(buf, sp);
1946: sp = buf;
1947: char *bp = buf;
1948: for(; *bp; ++bp)
1949: *bp = tolower(*bp);
1950: }
1951: strcpy(dbuf, sp);
1952: dbuf += strlen(sp);
1953: continue;
1954: }
1955: goto more;
1956: }
1957: if(c == '?') // size mask
1958: c = sizeChar;
1959: if(options & doptOpcodesSmall)
1960: c = tolower(c);
1961: *dbuf++ = c;
1962: }
1963: *dbuf = 0;
1964:
1965: // Parse the EAs for all operands
1966: int ea = opcode[0] & 0x3F;
1967: dbuf = operandBuffer;
1968: for(i=0; i<(sizeof(ots->op)/sizeof(ots->op[0])); ++i)
1969: {
1970: switch(ots->op[i])
1971: {
1972: case ofNone: // nothing
1973: break;
1974:
1975: case ofEa:
1976: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, EA_All & ~(ots->parameter[i]), 0, ots->disassFlag);
1977: break;
1978:
1979: case ofDn:
1980: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x00, size, EA_Dn, 0, ots->disassFlag);
1981: break;
1982: case ofAn:
1983: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x08, size, EA_An, 0, ots->disassFlag);
1984: break;
1985: case ofAni:
1986: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x10, size, EA_Ani, 0, ots->disassFlag);
1987: break;
1988: case ofAnip:
1989: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
1990: break;
1991: case ofPiAn:
1992: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x20, size, EA_piAn, 0, ots->disassFlag);
1993: break;
1994: case ofD16An:
1995: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x28, size, EA_dAn, 0, ots->disassFlag);
1996: break;
1997:
1998: case ofI:
1999: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x3C, size, EA_Immed, 0, ots->disassFlag);
2000: break;
2001:
2002: case ofDestDn:
2003: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2004: break;
2005: case ofDestAn:
2006: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x08, size, EA_An, 0, ots->disassFlag);
2007: break;
2008: case ofDestAnip:
2009: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2010: break;
2011: case ofDestPiAn:
2012: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x20, size, EA_piAn, 0, ots->disassFlag);
2013: break;
2014: case ofDestEa6:
2015: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | (((opcode[0] >> 6) & 0x7) << 3), size, EA_Dest-EA_An, 0, ots->disassFlag);
2016: break;
2017: case ofDestAbsL:
2018: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x39, size, EA_Abs, 0, ots->disassFlag);
2019: break;
2020:
2021: case ofIOpcode:
2022: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, opcode[0] & ots->parameter[i], ots->disassFlag);
2023: break;
2024: case ofI3:
2025: val = ((opcode[0] >> 9) & 7);
2026: if(!val) val = 8;
2027: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, val, ots->disassFlag);
2028: break;
2029: case ofExtIm:
2030: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, opcode[1], ots->disassFlag);
2031: break;
2032: case ofExtIm32:
2033: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, size, EA_ImmedParameter, opcode[2], ots->disassFlag);
2034: break;
2035: case ofExtIm4:
2036: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, opcode[1] & 0x0F, ots->disassFlag);
2037: break;
2038: case ofExtIm10:
2039: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, (opcode[1] >> 10) & 0x07, ots->disassFlag);
2040: break;
2041: case ofSpecReg:
2042: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0101, size, EA_SpecialRegister, ots->parameter[i], ots->disassFlag);
2043: break;
2044: case ofSpecExtReg:
2045: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0101, size, EA_SpecialRegister, opcode[1] & 0xFFF, ots->disassFlag);
2046: break;
2047: case ofExtReg0:
2048: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2049: break;
2050: case ofExtRegA0:
2051: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07) | 0x08, size, EA_An, 0, ots->disassFlag);
2052: break;
2053: case ofExtRegD04:
2054: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 4) & 0x07) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2055: break;
2056: case ofExtRegA05:
2057: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 5) & 0x07) | 0x08, size, EA_An, 0, ots->disassFlag);
2058: break;
2059: case ofExtReg:
2060: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2061: break;
2062: case ofExtAnip:
2063: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2064: break;
2065:
2066: case ofDisp:
2067: // branch treats the displacement 0x00 and 0xFF as an indicator how many words follow
2068: // This test will decline a displacement with the wrong word offset
2069: if((opcode[0] & 0xF000) == 0x6000)
2070: {
2071: val = opcode[0] & 0xFF;
2072: if(val == 0x00 && size != 2) goto more;
2073: if(val == 0xFF && size != 4) goto more;
2074: }
2075: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0102, size, EA_PCDisplacement, opcode[0] & 0xFF, ots->disassFlag);
2076: break;
2077:
2078: case ofRegList:
2079: val = opcode[1];
2080: if((ea & 0x38) == 0x20) // -(An) has a flipped bitmask
2081: val = Disass68kFlipBits(val);
2082: dbuf = Disass68kReglist(dbuf, val);
2083: break;
2084:
2085: case ofFPU:
2086: { // default FPU opcode modes
2087: int src = (opcode[1] >> 10) & 7;
2088: int dest = (opcode[1] >> 7) & 7;
2089: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2090: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2091: if(opcode[1] & 0x4000)
2092: {
2093: // <ea>,FPn
2094: int mask = EA_All - EA_An;
2095: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2096: mask -= EA_Dn;
2097: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2098: if(!dbuf) goto more;
2099: *dbuf++ = ',';
2100: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2101: *dbuf = 0;
2102: } else {
2103: // FPn,FPn or FPn
2104:
2105: // <ea> has to be 0
2106: if((opcode[0] & 0x3F) != 0) goto more;
2107:
2108: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+src;
2109: if(src != dest)
2110: {
2111: *dbuf++ = ',';
2112: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2113: }
2114: *dbuf = 0;
2115: }
2116: }
2117: break;
2118: case ofFPUMOVE:
2119: { // MOVE <ea>,FPn{k-Factor}
2120: int src = (opcode[1] >> 10) & 7;
2121: // <ea>,FPn
2122: int mask = EA_All - EA_An;
2123: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2124: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2125: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2126: mask -= EA_Dn;
2127: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2128: if(!dbuf) goto more;
2129: *dbuf++ = ',';
2130: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+((opcode[1] >> 7) & 7);
2131: if(src == 3)
2132: {
2133: int kFactor = opcode[1] & 0x7F;
2134: if(kFactor & 0x40)
2135: kFactor |= 0x80;
2136: *dbuf++ = '{';
2137: sprintf(dbuf, "%d", (signed char)kFactor);
2138: dbuf += strlen(dbuf);
2139: *dbuf++ = '}';
2140: } else if(src == 7)
2141: {
2142: if((opcode[1] & 0x0F) != 0) goto more;
2143: *dbuf++ = '{';
2144: *dbuf++ = options & doptRegisterSmall ? 'd' : 'D';
2145: *dbuf++ = '0' + ((opcode[1] >> 4) & 7);
2146: *dbuf++ = '}';
2147: } else {
2148: if((opcode[1] & 0x7F) != 0) goto more;
2149: }
2150: *dbuf = 0;
2151: }
2152: break;
2153: case ofFMOVECR:
2154: { // MOVECR #const,FPn
2155: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2156: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2157: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, opcode[1] & 0x7F, ots->disassFlag);
2158: if(!dbuf) goto more;
2159: int reg = (opcode[1] >> 7) & 7;
2160: *dbuf++ = ',';
2161: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+reg;
2162: *dbuf = 0;
2163: switch(opcode[1] & 0x7F) // document the well-known constants
2164: {
2165: case 0x00: strcat(commentBuffer, "PI"); break;
2166: case 0x0B: strcat(commentBuffer, "Log10(2)"); break;
2167: case 0x0C: strcat(commentBuffer, "e"); break;
2168: case 0x0D: strcat(commentBuffer, "Log2(e)"); break;
2169: case 0x0E: strcat(commentBuffer, "Log10(e)"); break;
2170: case 0x0F: strcat(commentBuffer, "0.0"); break;
2171: case 0x30: strcat(commentBuffer, "1n(2)"); break;
2172: case 0x31: strcat(commentBuffer, "1n(10)"); break;
2173: case 0x32: strcat(commentBuffer, "100"); break;
2174: case 0x33: strcat(commentBuffer, "10^1"); break;
2175: case 0x34: strcat(commentBuffer, "10^2"); break;
2176: case 0x35: strcat(commentBuffer, "10^4"); break;
2177: case 0x36: strcat(commentBuffer, "10^8"); break;
2178: case 0x37: strcat(commentBuffer, "10^16"); break;
2179: case 0x38: strcat(commentBuffer, "10^32"); break;
2180: case 0x39: strcat(commentBuffer, "10^64"); break;
2181: case 0x3A: strcat(commentBuffer, "10^128"); break;
2182: case 0x3B: strcat(commentBuffer, "10^256"); break;
2183: case 0x3C: strcat(commentBuffer, "10^512"); break;
2184: case 0x3D: strcat(commentBuffer, "10^1024"); break;
2185: case 0x3E: strcat(commentBuffer, "10^2048"); break;
2186: case 0x3F: strcat(commentBuffer, "10^4096"); break;
2187: }
2188: }
2189: break;
2190: case ofFPUSRRegList:
2191: {
2192: int hasReg = 0;
2193: *dbuf = 0;
2194: if(opcode[1] & 0x0400)
2195: {
2196: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPIAR));
2197: hasReg = 1;
2198: }
2199: if(opcode[1] & 0x0800)
2200: {
2201: if(hasReg) strcat(dbuf, "/");
2202: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPSR));
2203: hasReg = 1;
2204: }
2205: if(opcode[1] & 0x1000)
2206: {
2207: if(hasReg) strcat(dbuf, "/");
2208: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPCR));
2209: hasReg = 1;
2210: }
2211: if(!hasReg)
2212: strcat(dbuf, "0");
2213: dbuf += strlen(dbuf);
2214: }
2215: break;
2216: case ofFPUReglist: // FMOVEM
2217: {
2218: int mask = opcode[1] & 0xFF;
2219: if(opcode[1] & 0x0100)
2220: mask = Disass68kFlipBits(mask) >> 8;
2221: dbuf = Disass68kFPUReglist(dbuf, mask);
2222: }
2223: break;
2224: case ofFPU3Reg:
2225: { // FSINCOS
2226: int src = (opcode[1] >> 10) & 7;
2227: int dest = (opcode[1] >> 7) & 7;
2228: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2229: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2230: if(opcode[1] & 0x4000)
2231: {
2232: // <ea>,FPn
2233: int mask = EA_All - EA_An;
2234: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2235: mask -= EA_Dn;
2236: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2237: if(!dbuf) goto more;
2238: *dbuf++ = ',';
2239: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+(opcode[1] & 7);
2240: *dbuf++ = ',';
2241: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2242: *dbuf = 0;
2243: } else {
2244: // FPn,FPn or FPn
2245:
2246: // <ea> has to be 0
2247: if((opcode[0] & 0x3F) != 0) goto more;
2248:
2249: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+src;
2250: *dbuf++ = ',';
2251: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+(opcode[1] & 7);
2252: *dbuf++ = ',';
2253: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2254: *dbuf = 0;
2255: }
2256: }
2257: break;
2258:
2259: case ofCAS:
2260: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2261: if(!dbuf) goto more;
2262: *dbuf++ = ',';
2263: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2264: break;
2265: case ofCAS2:
2266: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2267: if(!dbuf) goto more;
2268: *dbuf++ = ':';
2269: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[2] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2270: if(!dbuf) goto more;
2271: *dbuf++ = ',';
2272: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2273: if(!dbuf) goto more;
2274: *dbuf++ = ':';
2275: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[2] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2276: if(!dbuf) goto more;
2277: *dbuf++ = ',';
2278: *dbuf++ = '(';
2279: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2280: if(!dbuf) goto more;
2281: *dbuf++ = ')';
2282: *dbuf++ = ':';
2283: *dbuf++ = '(';
2284: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[2] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2285: if(!dbuf) goto more;
2286: *dbuf++ = ')';
2287: *dbuf = 0;
2288: break;
2289: case ofExt4Dn:
2290: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[0] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2291: if(!dbuf) goto more;
2292: *dbuf++ = ':';
2293: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2294: if(!dbuf) goto more;
2295: *dbuf++ = ',';
2296: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2297: if(!dbuf) goto more;
2298: *dbuf = 0;
2299: break;
2300: case ofBFEa:
2301: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, EA_All & ~(ots->parameter[i]), 0, ots->disassFlag);
2302: if(!dbuf) goto more;
2303: *dbuf++ = '{';
2304: val = (opcode[1] >> 6) & 0x1F;
2305: if(opcode[1] & 0x0800)
2306: {
2307: if(val & 0x18) goto more;
2308: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, val & 0x07, 1, EA_Dn, val, ots->disassFlag);
2309: } else {
2310: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0103, 1, EA_ValueParameter, val, ots->disassFlag);
2311: }
2312: *dbuf++ = ':';
2313: val = opcode[1] & 0x1F;
2314: if(opcode[1] & 0x0020)
2315: {
2316: if(val & 0x18) goto more;
2317: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, val & 0x07, 1, EA_Dn, val, ots->disassFlag);
2318: } else {
2319: if(val == 0) val = 32;
2320: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0103, 1, EA_ValueParameter, val, ots->disassFlag);
2321: }
2322: *dbuf++ = '}';
2323: *dbuf = 0;
2324: break;
2325: case ofLineA:
2326: {
2327: int lineAVal = opcode[0] & 0xFFF;
2328: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, lineAVal, ots->disassFlag);
2329: const char *lineAStr[16] = { "Line-A Initialization",
2330: "Put pixel",
2331: "Get pixel",
2332: "Arbitrary line",
2333: "Horizontal line",
2334: "Filled rectangle",
2335: "Filled polygon",
2336: "Bit block transfer",
2337: "Text block transfer",
2338: "Show mouse",
2339: "Hide mouse",
2340: "Transform mouse",
2341: "Undraw sprite",
2342: "Draw sprite",
2343: "Copy raster form",
2344: "Seedfill"
2345: };
2346: if(lineAVal < 16)
2347: strcat(commentBuffer, lineAStr[lineAVal]);
2348: }
2349: break;
2350:
2351: default:
2352: goto more;
2353: }
2354: if(!dbuf) goto more;
2355:
2356: // does another operand follow => add separator
2357: if(ots->op[i+1] != ofNone)
2358: *dbuf++ = ',';
2359: }
2360: return addr-baseAddr;
2361: }
2362:
2363: // unknown opcode
2364: strcpy(opcodeBuffer, "DC.W");
2365: sprintf(operandBuffer,"$%4.4x", Disass68kGetWord(addr));
2366: return 2;
2367: }
2368:
2369: static void Disass68kComposeStr(char *dbuf, const char *str, int position, int maxPos)
2370: {
2371: int i;
2372: int len = strlen(dbuf);
2373: while(len < position) {
2374: dbuf[len++] = ' '; /* Will give harmless warning from GCC */
2375: }
2376: for(i=0; str[i] && (!maxPos || len+i<maxPos); ++i)
2377: dbuf[len+i] = str[i];
2378: if(str[i])
2379: dbuf[len+i-1] = '+';
2380: dbuf[len+i] = 0;
2381: }
2382:
2383: static void Disass68k_loop (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
2384: {
2385: static bool isInit = false;
2386: if(!isInit)
2387: {
2388: Disass68kInit(Paths_GetHatariHome());
2389: isInit = true;
2390: }
2391:
2392: while (cnt-- > 0) {
2393: int addrWidth = 6; // 6 on an ST, 8 on a TT
2394: char lineBuffer[1024];
2395:
2396: char addressBuffer[32];
2397: char hexdumpBuffer[256];
2398: char labelBuffer[256];
2399: char opcodeBuffer[64];
2400: char operandBuffer[256];
2401: char commentBuffer[256];
2402: int len = Disass68k(addr, labelBuffer, opcodeBuffer, operandBuffer, commentBuffer);
2403: if(!len) break;
2404:
2405: sprintf(addressBuffer, "$%*.*x :", addrWidth,addrWidth, addr);
2406:
2407: hexdumpBuffer[0] = 0;
2408: int plen = len;
2409: if(plen > 80 && (!strncmp(opcodeBuffer, "DC.", 3) || !strncmp(opcodeBuffer, "dc.", 3)))
2410: plen = ((optionPosLabel - optionPosHexdump) / 5) * 2;
2411: int j;
2412: for(j=0; j<plen; j += 2)
2413: {
2414: if(j > 0)
2415: strcat(hexdumpBuffer, " ");
2416: if(j + 2 > plen)
2417: {
2418: sprintf(hexdumpBuffer+strlen(hexdumpBuffer), "%2.2x", Disass68kGetWord(addr+j) >> 8);
2419: } else {
2420: sprintf(hexdumpBuffer+strlen(hexdumpBuffer), "%4.4x", Disass68kGetWord(addr+j));
2421: }
2422: }
2423:
2424: lineBuffer[0] = 0;
2425: if(optionPosAddress >= 0)
2426: Disass68kComposeStr(lineBuffer, addressBuffer, optionPosAddress, 0);
2427: if(optionPosHexdump >= 0)
2428: Disass68kComposeStr(lineBuffer, hexdumpBuffer, optionPosHexdump, optionPosLabel);
2429: if(optionPosLabel >= 0)
2430: Disass68kComposeStr(lineBuffer, labelBuffer, optionPosLabel, 0);
2431: if(optionPosOpcode >= 0)
2432: Disass68kComposeStr(lineBuffer, opcodeBuffer, optionPosOpcode, 0);
2433: if(optionPosOperand >= 0)
2434: {
2435: size_t l = strlen(lineBuffer);
2436: if(lineBuffer[l-1] != ' ') // force at least one space between opcode and operand
2437: {
2438: lineBuffer[l++] = ' ';
2439: lineBuffer[l] = 0;
2440: }
2441: Disass68kComposeStr(lineBuffer, operandBuffer, optionPosOperand, 0);
2442: }
2443: if(commentBuffer[0] && optionPosComment >= 0)
2444: {
2445: Disass68kComposeStr(lineBuffer, " ;", optionPosComment, 0);
2446: Disass68kComposeStr(lineBuffer, commentBuffer, optionPosComment+3, 0);
2447: }
1.1.1.3 ! root 2448: else if (optionPosComment >= 0)
! 2449: {
! 2450: /* assume comments are for things which aren't profiled */
! 2451: Uint32 count, cycles;
! 2452: if (Profile_CpuAddressData(addr, &count, &cycles))
! 2453: {
! 2454: sprintf(commentBuffer, "%d/%d times/cycles", count, cycles);
! 2455: Disass68kComposeStr(lineBuffer, commentBuffer, optionPosComment+1, 0);
! 2456: }
! 2457: }
1.1 root 2458: fprintf(f, "%s\n", lineBuffer);
2459: // if(strstr(opcodeBuffer, "RTS") || strstr(opcodeBuffer, "RTE") || strstr(opcodeBuffer, "JMP")
2460: // || strstr(opcodeBuffer, "rts") || strstr(opcodeBuffer, "rte") || strstr(opcodeBuffer, "jmp"))
2461: // fprintf(f, "\n");
2462: addr += len;
2463: }
2464: if (nextpc)
2465: *nextpc = addr;
2466: }
2467:
2468:
2469: /*
2470: * Disasm should be called from Hatari's sources to use either uae's built in
2471: * disassembler (DISASM_ENGINE_UAE) or the stand alone disassembler above (DISASM_ENGINE_EXT)
2472: */
2473:
2474: void Disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt , int DisasmEngine)
2475: {
2476: if ( DisasmEngine == DISASM_ENGINE_UAE )
2477: return m68k_disasm (f, addr, nextpc, cnt);
2478: else if ( DisasmEngine == DISASM_ENGINE_EXT )
2479: return Disass68k_loop (f, addr, nextpc, cnt);
2480: }
2481:
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