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1.1 root 1: /***
2: * 68k disassembler, written 2010 by Markus Fritze, www.sarnau.com
3: *
1.1.1.4 ! root 4: * This file is distributed under the GNU General Public License, version 2
! 5: * or at your option any later version. Read the file gpl.txt for details.
1.1 root 6: ***/
7:
8: #include <stdio.h>
9: #include <ctype.h>
10: #include <strings.h>
11: #include <stdlib.h>
12:
13: #include "config.h"
14: #include "sysdeps.h"
15: #include "main.h"
1.1.1.4 ! root 16: #include "configuration.h"
1.1 root 17: #include "newcpu.h"
18: #include "paths.h"
1.1.1.3 root 19: #include "profile.h"
1.1 root 20: #include "tos.h"
21: #include "68kDisass.h"
22:
23: #define ADDRESS_ON_PC 1
24: #define USE_SYMBOLS 1
25:
26: typedef enum {
27: doptNoBrackets = 1, // hide brackets around absolute addressing
28: doptOpcodesSmall = 2, // opcodes are small letters
29: doptRegisterSmall = 4, // register names are small letters
30: doptStackSP = 8, // stack pointer is named "SP" instead of "A7" (except for MOVEM)
31: } Diss68kOptions;
32:
33: static Diss68kOptions options = doptOpcodesSmall | doptRegisterSmall | doptStackSP | doptNoBrackets;
34:
1.1.1.4 ! root 35: /* all options */
! 36: static const Diss68kOptions optionsMask = doptOpcodesSmall | doptRegisterSmall | doptStackSP | doptNoBrackets;
! 37:
1.1 root 38: // values <0 will hide the group
1.1.1.4 ! root 39: static int optionPosAddress = 0; // current address
! 40: static int optionPosHexdump = 10; // 16-bit words at this address
! 41: static int optionPosLabel = 35; // label, if defined
! 42: static int optionPosOpcode = 47; // opcode
! 43: static int optionPosOperand = 57; // operands for the opcode
! 44: static int optionPosComment = 82; // comment, if defined
1.1 root 45:
46: /***
47: * Motorola 16-/32-Bit Microprocessor and coprocessor types
48: ***/
49: #define MC68000 0x000001 // 16-/32-Bit Microprocessor
50: #define MC68EC000 0x000002 // 16-/32-Bit Embedded Controller
51: #define MC68HC000 0x000004 // Low Power 16-/32-Bit Microprocessor
52: #define MC68008 0x000008 // 16-Bit Microprocessor with 8-Bit Data Bus
53: #define MC68010 0x000010 // 16-/32-Bit Virtual Memory Microprocessor
54: #define MC68020 0x000020 // 32-Bit Virtual Memory Microprocessor
55: #define MC68EC020 0x000040 // 32-Bit Embedded Controller (no PMMU)
56: #define MC68030 0x000080 // Second-Generation 32-Bit Enhanced Microprocessor
57: #define MC68EC030 0x000100 // 32-Bit Embedded Controller (no PMMU)
58: #define MC68040 0x000200 // Third-Generation 32-Bit Microprocessor
59: #define MC68LC040 0x000400 // Third-Generation 32-Bit Microprocessor (no FPU)
60: #define MC68EC040 0x000800 // 32-Bit Embedded Controller (no FPU, no PMMU)
61: #define MC68330 0x001000 // CPU32 Integrated CPU32 Processor
62: #define MC68340 0x002000 // CPU32 Integrated Processor with DMA
63: #define MC68060 0x004000 // Fourth-Generation 32-Bit Microprocessor
64: #define MC68LC060 0x008000 // Fourth-Generation 32-Bit Microprocessor (no FPU)
65: #define MC68EC060 0x010000 // Fourth-Generation 32-Bit Microprocessor (no FPU, no PMMU)
66: #define MC_CPU32 (MC68330|MC68340)
67:
68: #define MC_020 (MC68020|MC68EC020|MC68030|MC68EC030|MC68040|MC68LC040|MC68EC040|MC_CPU32|MC68060|MC68LC060|MC68EC060)
69: #define MC_ALL (MC68000|MC68EC000|MC68HC000|MC68008|MC68010|MC_020)
70:
71: #define MC68851 0x020000 // Paged Memory Management Unit
72:
73: #define MC68881 0x040000 // Floating-PointCoprocessor
74: #define MC68882 0x080000 // Enhanced Floating-Point Coprocessor
75:
76: #define MC_PMMU (MC68881|MC68882)
77: #define MC_FPU (MC68881|MC68882)
78:
79: static int optionCPUTypeMask = ( MC_ALL & ~MC68040 & ~MC_CPU32 & ~MC68060 ) | MC_PMMU | MC_FPU;
80:
81:
82: typedef enum {
83: dtNone,
84: dtByte, // a specific number of bytes, usually 1
85: dtWord, // one 16-bit value
86: dtLong, // one 32-bit value
87: dtOpcode, // an opcode of variable length
88: dtASCString, // a 0-byte terminated ASCII string
89: dtPointer, // a generic 32-bit pointer
90: dtFunctionPointer, // a 32-bit pointer to a function
91: dtStringArray, // a specific number of ASCII bytes
92: } Disass68kDataType;
93:
94: typedef struct {
95: char *name;
96: char *comment;
97: Disass68kDataType type;
98: int size;
99: } disStructElement;
100:
101: typedef struct {
102: char *name; // name of the structure
103: int size; // size of structure
104: int count; // number of lines
105: disStructElement *elements; // array of all elements of the struct
106: } disStructEntry;
107:
108: static int disStructCounts;
109: static disStructEntry *disStructEntries;
110:
111: typedef struct {
112: long addr; // address of the label
113: Disass68kDataType type; // type of the data on the address
114: int size; // size of the label, references inside it are addressed via base address + offset
115: int count; // number of elements at this address with the given size
116: int structIndex; // -1 no struct to describe the element
117: char *name; // name of the label
118: char *comment; // optional comment
119: } disSymbolEntry;
120:
121: static int disSymbolCounts;
122: static disSymbolEntry *disSymbolEntries;
123:
124:
125: static inline unsigned short Disass68kGetWord(long addr)
126: {
127: return get_word(addr);
128: }
129:
130: // Load a text file into memory, count the lines and replace the LF with 0-bytes.
131: static int Disass68kLoadTextFile(const char *filename, char **filebuf)
132: {
133: long index;
1.1.1.4 ! root 134: long fileLength;
! 135: int lineCount;
! 136: char *fbuf;
! 137: FILE *f;
! 138:
1.1 root 139: if(filebuf)
140: *filebuf = NULL;
1.1.1.4 ! root 141: f = fopen(filename, "r");
1.1 root 142: if(!f) return 0;
143: if(fseek(f, 0, SEEK_END))
144: return 0;
1.1.1.4 ! root 145: fileLength = ftell(f);
! 146: if(fileLength <= 0) return 0;
1.1 root 147: if(fseek(f, 0, SEEK_SET))
148: return 0;
1.1.1.4 ! root 149: fbuf = malloc(fileLength);
1.1 root 150: if(!fbuf) return 0;
151: if((size_t)fileLength != fread(fbuf, sizeof(char), fileLength, f))
1.1.1.4 ! root 152: {
! 153: free(fbuf);
1.1 root 154: return 0;
1.1.1.4 ! root 155: }
! 156: lineCount = 0;
1.1 root 157: for(index=0; index<fileLength; ++index)
158: {
159: if(fbuf[index] == '\r') // convert potential CR into a space (which we ignore at the end of the line anyway)
160: fbuf[index] = ' ';
161: if(fbuf[index] == '\n') // count LF and terminate line
162: {
163: ++lineCount;
164: fbuf[index] = 0;
165: }
166: }
167: if(filebuf)
168: *filebuf = fbuf;
169: return lineCount;
170: }
171:
172: static void Disass68kLoadStructInfo(const char *filename)
173: {
1.1.1.4 ! root 174: int i,j;
! 175: char *nextLine;
! 176: char *line;
1.1 root 177: char *fbuf = NULL;
1.1.1.4 ! root 178: int lineCount = Disass68kLoadTextFile(filename, &fbuf);
1.1 root 179: disStructEntry *se = NULL;
1.1.1.4 ! root 180:
! 181: if(!lineCount) return;
! 182:
! 183: disStructEntries = realloc(disStructEntries, sizeof(disStructEntry)
! 184: * (disStructCounts + lineCount));
1.1 root 185: if(!disStructEntries) { free(fbuf); return; }
1.1.1.4 ! root 186:
! 187: line = fbuf;
1.1 root 188:
189: for(i=0; i<lineCount; line = nextLine, ++i)
190: {
191: // strip spaces at the end of the line, remember the ptr to the next line
192: char *sp = line;
193: while(*sp++)
194: ;
195: nextLine = sp--;
196: while(isspace(*--sp))
197: *sp = 0;
198:
199: if(line[0] == '{')
200: {
201: se = &disStructEntries[disStructCounts];
202: se->name = strdup(line+1);
203: se->count = 0;
204: se->elements = malloc(sizeof(disStructElement) * lineCount); // lineCount is way too much, but safe
205: } else if(line[0] == '}') {
206: if(se)
207: {
208: se->size = 0;
209: for(j=0; j<se->count; ++j)
210: se->size += se->elements[j].size;
211: // printf("%s : %d bytes\n", se->name, se->size);
212: ++disStructCounts;
213: se = NULL;
214: }
215: } else if(line[0] == '#') {
216: disStructElement dse;
217: int val = 0;
218: int index = 2;
219: if(line[1] == 'A' || line[1] == 'B')
220: {
221: for(; isdigit(line[index]); ++index)
222: {
223: val *= 10;
224: val += line[index] - '0';
225: }
226: }
227: if(val == 0) val = 1;
228: dse.name = NULL;
229: switch(line[1])
230: {
231: case 'A': dse.type = dtStringArray; dse.size = val; dse.name = strdup(line + index + 1); break;
232: case 'B': dse.type = dtByte; dse.size = val; break;
233: case 'W': dse.type = dtWord; dse.size = 2; break;
234: case 'L': dse.type = dtLong; dse.size = 4; break;
235: case 'C': dse.type = dtOpcode; dse.size = 2; break;
236: case 'f': dse.type = dtFunctionPointer; dse.size = 4; break;
237: case 'p': dse.type = dtPointer; dse.size = 4; break;
238: default: dse.type = dtNone; dse.size = 0;
239: printf("Unknown type in \"%s\"\n", line); break;
240: }
241: if(!dse.name)
242: dse.name = strdup(line+3);
243: dse.comment = NULL;
244: if(se)
245: se->elements[se->count++] = dse;
246: }
247: }
248: free(fbuf);
249: }
250:
251: static void Disass68kLoadSymbols(const char *filename)
252: {
1.1.1.4 ! root 253: int i,j;
! 254: char *nextLine;
! 255: char *line;
1.1 root 256: char *fbuf = NULL;
257: int lineCount = Disass68kLoadTextFile(filename, &fbuf);
1.1.1.4 ! root 258: if(!lineCount) return;
1.1 root 259: disSymbolEntries = realloc(disSymbolEntries, sizeof(disSymbolEntry) * (disSymbolCounts + lineCount));
260: if(!disSymbolEntries) { free(fbuf); return; }
1.1.1.4 ! root 261: line = fbuf;
1.1 root 262:
263: for(i=0; i<lineCount; line = nextLine, ++i)
264: {
1.1.1.4 ! root 265: long addr;
1.1 root 266: char *sp = line;
1.1.1.4 ! root 267: char *parameterPtr[10];
! 268: int parameterCount = 0;
! 269: char *str;
! 270: long size = 0;
! 271: int type = 0;
! 272:
! 273: // strip spaces at the end of the line, remember the ptr to the next line
1.1 root 274: while(*sp++)
275: ;
276: nextLine = sp--;
277: while(isspace(*--sp))
278: *sp = 0;
279:
280: // ignore empty lines
281: if(line[0] == 0)
282: continue;
283:
284: sscanf(line, "%lx",&addr);
285: disSymbolEntries[disSymbolCounts].addr = addr;
286: disSymbolEntries[disSymbolCounts].structIndex = -1;
287:
1.1.1.4 ! root 288: str = line;
1.1 root 289: do {
290: str = strchr(str, ',');
291: if(str)
292: {
293: char *ep = str;
294: while(isspace(*--ep))
295: *ep = 0;
296: *str++ = 0;
297: while(*str && isspace(*str))
298: ++str;
299: parameterPtr[parameterCount++] = str;
300: }
301: } while(str != NULL && parameterCount < 10);
302:
303: if(parameterCount != 3 && parameterCount != 4)
304: continue; // ignore line
305:
306: if(strlen(parameterPtr[0]) == 1)
307: {
308: switch(parameterPtr[0][0])
309: {
310: case 'A': type = dtASCString; size = 1; break; // ascii NULL
311: case 'B': type = dtByte; size = 1; break; // byte
312: case 'W': type = dtWord; size = 2; break; // word
313: case 'L': type = dtLong; size = 4; break; // long
314: case 'C': type = dtOpcode; size = 2; break; // code
315: case 'f': type = dtFunctionPointer; size = 4; break; // function pointer
316: case 'p': type = dtPointer; size = 4; break; // regular pointer
317: default: printf("ERROR: $%lx : %s\n", addr, parameterPtr[0]); continue;
318: }
319: } else {
320: for(j=0; j<disStructCounts; ++j)
321: {
322: disStructEntry *se = &disStructEntries[j];
323: if(se->name == NULL)
324: break;
325: if(strcmp(parameterPtr[0], se->name))
326: continue;
327: size = se->size;
328: disSymbolEntries[disSymbolCounts].structIndex = j;
329: }
330: }
331: if(!size)
332: continue;
333:
334: disSymbolEntries[disSymbolCounts].type = type;
335: disSymbolEntries[disSymbolCounts].size = size;
336: disSymbolEntries[disSymbolCounts].count = atol(parameterPtr[1]);
337: disSymbolEntries[disSymbolCounts].name = strdup(parameterPtr[2]);
338: disSymbolEntries[disSymbolCounts].comment = NULL;
339: if(parameterCount == 4)
340: disSymbolEntries[disSymbolCounts].comment = strdup(parameterPtr[3]);
341: ++disSymbolCounts;
342: }
343: free(fbuf);
344: }
345:
346: static void Disass68kInit(const char *baseDirectory)
347: {
1.1.1.2 root 348: char filename[FILENAME_MAX];
1.1 root 349:
350: disStructCounts = 0;
351: sprintf(filename, "%s/DisassStructs.txt", baseDirectory);
352: Disass68kLoadStructInfo(filename);
353: sprintf(filename, "%s/DisassStructs_%4.4X.txt", baseDirectory, TosVersion);
354: Disass68kLoadStructInfo(filename);
355:
356: disSymbolCounts = 0;
357: sprintf(filename, "%s/DisassSymbols.txt", baseDirectory);
358: Disass68kLoadSymbols(filename);
359: sprintf(filename, "%s/DisassSymbols_%4.4X.txt", baseDirectory, TosVersion);
360: Disass68kLoadSymbols(filename);
361: }
362:
363:
364:
365: static Disass68kDataType Disass68kType(long addr, char *addressLabel, char *commentBuffer, int *count)
366: {
367: int i,j;
368:
369: addressLabel[0] = 0;
370: commentBuffer[0] = 0;
371: for(i=0; i<disSymbolCounts; ++i)
372: {
1.1.1.4 ! root 373: const disStructEntry *se;
1.1 root 374: const disSymbolEntry *dse = &disSymbolEntries[i];
375: int offset = addr - dse->addr;
1.1.1.4 ! root 376:
1.1 root 377: if(offset < 0 || offset >= dse->count * dse->size)
378: continue;
379:
380: // no special struct that devices this value?
381: if(dse->structIndex < 0)
382: {
383: offset = (offset + dse->size - 1) / dse->size;
384: *count = dse->count - offset;
385: if(offset == 0) // only in the first line
386: {
387: strcpy(addressLabel, dse->name);
388: if(dse->comment)
389: strcpy(commentBuffer, dse->comment);
390: }
391: return dse->type;
392: }
393:
394: *count = 1;
1.1.1.4 ! root 395: se = &disStructEntries[dse->structIndex];
1.1 root 396: for(j=0; j<se->count; ++j)
397: {
398: const disStructElement *e = &se->elements[j];
399: if(offset < e->size)
400: {
401: if(e->type == dtStringArray)
402: *count = e->size;
403: if(j == 0)
404: strcpy(addressLabel, dse->name);
405:
406: sprintf(commentBuffer, "[%s]", e->name);
407: if(e->comment)
408: strcat(commentBuffer, e->comment);
409: return e->type;
410: }
411: offset -= e->size;
412: }
413: return dse->size;
414: }
415: return dtNone;
416: }
417:
418: /***
419: * Lookup a symbol name
420: ***/
421: static const char *Disass68kSymbolName(long addr, int size)
422: {
423: int i;
424:
425: for(i=0; i<disSymbolCounts; ++i)
426: {
1.1.1.4 ! root 427: static char symbolName[128];
1.1 root 428: const disSymbolEntry *dse = &disSymbolEntries[i];
1.1.1.4 ! root 429: int offset = addr - dse->addr;
! 430: int reminder;
! 431:
1.1 root 432: if(offset < 0 || offset >= dse->count * dse->size)
433: continue;
434:
435: if(dse->name[0] == 0)
436: return NULL;
437:
1.1.1.4 ! root 438: reminder = offset % dse->size;
1.1 root 439: offset /= dse->size;
440:
441: strcpy(symbolName, dse->name);
442: if(offset)
443: sprintf(symbolName+strlen(symbolName), "+%d*%d", dse->size, offset);
444: if(reminder)
445: sprintf(symbolName+strlen(symbolName), "+%d", reminder);
446: return symbolName;
447: }
448: return NULL;
449: }
450:
451: /***
452: * return a string pointer to display a register name
453: ***/
454: static const char *Disass68kRegname(int reg)
455: {
456: static char regName[3];
457: switch(reg)
458: {
459: case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
460: sprintf(regName, "%c%d", (options & doptRegisterSmall ? 'd' : 'D'), reg);
461: break;
462:
463: case 0x0F:
464: if(options & doptStackSP) // display A7 as SP
465: {
466: if(options & doptRegisterSmall)
467: return "sp";
468: return "SP";
469: }
470: case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: case 0x0D: case 0x0E:
471: sprintf(regName, "%c%d", (options & doptRegisterSmall ? 'a' : 'A'), reg & 7);
472: break;
473: }
474: return regName;
475: }
476:
477: /***
478: * return a string pointer to display a register name
479: ***/
480: static const char *Disass68kNumber(int val)
481: {
482: static char numString[32];
483: if(val >= -9 && val <= 9)
484: {
485: sprintf(numString, "%d", val);
486: } else {
487: // 4 characters/numbers or underscore (e.g. for cookies)
488: char c0 = (val >> 24) & 0xFF;
489: char c1 = (val >> 16) & 0xFF;
490: char c2 = (val >> 8) & 0xFF;
491: char c3 = (val >> 0) & 0xFF;
492: if((isalnum(c0) || c0 == '_') && (isalnum(c1) || c1 == '_') && (isalnum(c2) || c2 == '_') && (isalnum(c3) || c3 == '_'))
493: {
494: sprintf(numString, "'%c%c%c%c'", c0, c1, c2, c3);
495: } else {
496: sprintf(numString, "$%x", val);
497: }
498: }
499: return numString;
500: }
501:
502: /***
503: * Supported registers for e.g. MOVEC
504: ***/
505: #define REG_CCR -1
506: #define REG_SR -2
507: #define REG_PC -3
508: #define REG_ZPC -4
509: #define REG_TT0 -8
510: #define REG_TT1 -9
511: #define REG_MMUSR -10
512: #define REG_USP 0x800
513: #define REG_SFC 0x000
514: #define REG_DFC 0x001
515: #define REG_TC 0x10000
516: #define REG_SRP 0x10002
517: #define REG_CRP 0x10003
518: #define REG_VAL 0x20000
519: #define REG_CACHES_NONE 0x20010
520: #define REG_CACHES_IC 0x20011
521: #define REG_CACHES_DC 0x20012
522: #define REG_CACHES_ICDC 0x20013
523: #define REG_FPU_FPCR 0x30004
524: #define REG_FPU_FPSR 0x30002
525: #define REG_FPU_FPIAR 0x30001
526:
527: static const char *Disass68kSpecialRegister(int reg)
528: {
529: static char buf[8];
530: const char *sp = NULL;
531: switch (reg)
532: {
533: case 0x000: sp = "SFC"; break;
534: case 0x001: sp = "DFC"; break;
535: case 0x002: sp = "CACR"; break;
536: case 0x003: sp = "TC"; break;
537: case 0x004: sp = "ITT0"; break; // IACR0 on an 68EC040 only
538: case 0x005: sp = "ITT1"; break; // IACR1 on an 68EC040 only
539: case 0x006: sp = "DTT0"; break; // DACR0 on an 68EC040 only
540: case 0x007: sp = "DTT1"; break; // DACR1 on an 68EC040 only
541: case 0x008: sp = "BUSCR"; break;
542:
543: case 0x800: sp = "USP"; break;
544: case 0x801: sp = "VBR"; break;
545: case 0x802: sp = "CAAR"; break;
546: case 0x803: sp = "MSP"; break;
547: case 0x804: sp = "ISP"; break;
548: case 0x805: sp = "MMUSR"; break;
549: case 0x806: sp = "URP"; break;
550: case 0x807: sp = "SRP"; break;
551: case 0x808: sp = "PCR"; break;
552:
553: // MMU register
554: case 0x10000: sp = "TC"; break;
555: case 0x10001: sp = "DRP"; break;
556: case 0x10002: sp = "SRP"; break;
557: case 0x10003: sp = "CRP"; break;
558: case 0x10004: sp = "CAL"; break;
559: case 0x10005: sp = "VAL"; break;
560: case 0x10006: sp = "SCCR"; break;
561: case 0x10007: sp = "ACR"; break;
562:
563: case REG_CCR: sp = "CCR"; break;
564: case REG_SR: sp = "SR"; break;
565: case REG_PC: sp = "PC"; break;
566: case REG_ZPC: sp = "ZPC"; break;
567: case REG_TT0: sp = "TT0"; break;
568: case REG_TT1: sp = "TT1"; break;
569: case REG_MMUSR: sp = "MMUSR"; break;
570:
571: case REG_VAL: sp = "VAL"; break;
572:
573: case REG_CACHES_NONE: sp = "NC"; break;
574: case REG_CACHES_IC: sp = "IC"; break;
575: case REG_CACHES_DC: sp = "DC"; break;
576: case REG_CACHES_ICDC: sp = "IC/DC"; break; // GCC lists this as "BC"
577:
578: case REG_FPU_FPCR: sp = "FPCR"; break;
579: case REG_FPU_FPSR: sp = "FPSR"; break;
580: case REG_FPU_FPIAR: sp = "FPIAR"; break;
581:
582: // unknown register => unknown opcode!
1.1.1.4 ! root 583: default: return NULL;
1.1 root 584: }
1.1.1.4 ! root 585:
1.1 root 586: if(options & doptRegisterSmall)
587: {
1.1.1.4 ! root 588: char *bp;
1.1 root 589: strcpy(buf, sp);
1.1.1.4 ! root 590: for (bp = buf; *bp; ++bp)
1.1 root 591: *bp = tolower(*bp);
592: return buf;
593: }
594: return sp;
595: }
596:
597: /***
598: * 680x0 EA disassembly, supports all address modes
599: *
600: * disassbuf = output buffer for the EA, empty string in case of an illegal EA
601: * addr = pointer to the address, which Disass68kGetWord() will allow to read memory.
602: * Incremented by the function to point behind the opcode, when done
603: * ea = 6-bit ea from the opcode
604: * size = addressed size of the opcode in bytes (e.g. 1,2,4 for MOVE.B, MOVE.W, MOVE.L), only used for immediate addressing
605: ***/
606:
607: #define EA_Dn 0x00001 // Dn
608: #define EA_An 0x00002 // An
609: #define EA_Ani 0x00004 // (An)
610: #define EA_Anip 0x00008 // (An)+
611: #define EA_piAn 0x00010 // -(An)
612: #define EA_dAn 0x00020 // d(An), d(An,Dn), etc.
613: #define EA_PCRel 0x00040 // d(PC), d(PC,Dn), etc.
614: #define EA_Abs 0x00080 // abs.w, abs.l
615: #define EA_Immed 0x00100 // #<val>
616:
617: #define EA_ImmedParameter 0x0200 // an immediate value as a parameter
618: #define EA_ValueParameter 0x0400 // an immediate value as a parameter without the "#"
619: #define EA_SpecialRegister 0x0800 // any special register e.g. SR,CCR,USP,etc
620: #define EA_PCDisplacement 0x1000 // PC relative jump, like for BRA and friends
621:
622: #define EA_All (EA_Dn | EA_An | EA_Ani | EA_Anip | EA_piAn | EA_dAn | EA_Abs | EA_Immed | EA_PCRel)
623: #define EA_Dest (EA_Dn | EA_An | EA_Ani | EA_Anip | EA_piAn | EA_dAn | EA_Abs)
624:
625: static char *Disass68kEA(char *disassbuf, char *commentBuffer, long *addr, long opcodeAddr, int ea, int size, int allowedEAs, int parameterValue, int disassFlag)
626: {
627: unsigned short eWord1;
628: unsigned short eWord2;
629: int xn,c,scale;
630: int reg = ea & 7;
631: const char *sp;
632: long val;
1.1.1.4 ! root 633: char regName[3];
! 634: signed long pcoffset;
! 635:
1.1 root 636: val = 0;
637:
638: disassbuf[0] = 0;
639: switch(ea)
640: {
641: // M=000 = 0 Dn
642: // Data Register Direct Mode
643: // Dn
644: // M=001 = 1 An
645: // Address Register Direct Mode
646: // An
647: case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
648: if((allowedEAs & EA_Dn) != EA_Dn)
649: break;
650: sprintf(disassbuf, "%s", Disass68kRegname(ea & 0x0F));
651: break;
652: case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: case 0x0D: case 0x0E: case 0x0F:
653: if((allowedEAs & EA_An) != EA_An)
654: break;
655: sprintf(disassbuf, "%s", Disass68kRegname(ea & 0x0F));
656: break;
657:
658: // M=010 = 2
659: // Address Register Indirect Mode
660: // (An)
661: case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
662: if((allowedEAs & EA_Ani) != EA_Ani)
663: break;
664: sprintf(disassbuf, "(%s)", Disass68kRegname(reg | 8));
665: break;
666:
667: // M=011 = 3
668: // Address Register Indirect with Postincrement Mode
669: // (An) +
670: case 0x18: case 0x19: case 0x1A: case 0x1B: case 0x1C: case 0x1D: case 0x1E: case 0x1F:
671: if((allowedEAs & EA_Anip) != EA_Anip)
672: break;
673: sprintf(disassbuf, "(%s)+", Disass68kRegname(reg | 8));
674: break;
675:
676: // M=100 = 4
677: // Address Register Indirect with Predecrement Mode
678: // – (An)
679: case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
680: if((allowedEAs & EA_piAn) != EA_piAn)
681: break;
682: sprintf(disassbuf, "-(%s)", Disass68kRegname(reg | 8));
683: break;
684:
685: // M=101 = 5
686: // Address Register Indirect with Displacement Mode
687: // (d16,An)
688: case 0x28: case 0x29: case 0x2A: case 0x2B: case 0x2C: case 0x2D: case 0x2E: case 0x2F:
689: if((allowedEAs & EA_dAn) != EA_dAn)
690: break;
691: eWord1 = Disass68kGetWord(*addr); *addr += 2;
692: sprintf(disassbuf, "%s(%s)", Disass68kNumber(eWord1), Disass68kRegname(reg | 8));
693: break;
694:
695: // M=111 = 7, Xn/reg = 011 = 3
696: // Program Counter Indirect with Index (Base Displacement) Mode
697: // (bd, PC, Xn. SIZE*SCALE)
698: // Program Counter Memory Indirect Postindexed Mode
699: // ([bd,PC],Xn.SIZE*SCALE,od)
700: // Program Counter Memory Indirect Preindexed Mode
701: // ([bd,PC,Xn.SIZE*SCALE],od)
702: case 0x3B:
703: // This is equal to the following, except that instead of An, it is PC relative
704:
705: // M=110 = 6
706: // Address Register Indirect with Index (Base Displacement) Mode
707: // (bd,An,Xn.SIZE*SCALE)
708: // Memory Indirect Postindexed Mode
709: // ([bd,An],Xn.SIZE*SCALE,od)
710: // Memory Indirect Preindexed Mode
711: // ([bd, An, Xn.SIZE*SCALE], od)
712: case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
713: eWord1 = Disass68kGetWord(*addr); *addr += 2;
714: xn = (eWord1 >> 12) & 0x0F; // Register D0..D7/A0..A7
715: c = ((eWord1 >> 11) & 1) ? 'l' : 'w'; // Word/Long-Word Index Size 0 = Sign-Extended Word 1 = Long Word
716: scale = (eWord1 >> 9) & 3; // Scale Factor 00 = 1 01 = 2 10 = 4 11 = 8
1.1.1.4 ! root 717:
1.1 root 718: if(ea == 0x3B)
719: {
720: sp = Disass68kSpecialRegister(REG_PC);
721: if(!sp) return NULL;
722: strcpy(regName, sp);
723: } else {
724: sprintf(regName, "%s", Disass68kRegname(reg | 8));
725: }
726:
727: if((eWord1 & 0x0100) == 0)
728: {
1.1.1.4 ! root 729: const char *numStr;
! 730:
1.1 root 731: // BRIEF EXTENSION WORD FORMAT
732: if(ea == 0x3B)
733: {
734: if((allowedEAs & EA_PCRel) != EA_PCRel)
735: break;
736: } else {
737: if((allowedEAs & EA_dAn) != EA_dAn)
738: break;
739: }
740:
741: // Address Register Indirect with Index (8-Bit Displacement) Mode
742: // (d8 ,An, Xn.SIZE*SCALE)
1.1.1.4 ! root 743: numStr = Disass68kNumber(eWord1 & 0xFF);
1.1 root 744: if(numStr[0] == '0' && numStr[1] == 0)
745: numStr = "";
746:
747: // scale is only on 68020 and later supported
748: if(scale != 0 && (optionCPUTypeMask & MC_020) == 0)
749: return NULL;
750:
751: if(scale == 0)
752: {
753: #if ADDRESS_ON_PC
754: if(ea == 0x3B)
755: sprintf(disassbuf, "$%lx(%s,%s.%c)", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2, Disass68kSpecialRegister(REG_PC), Disass68kRegname(xn), c);
756: else
757: #endif
758: sprintf(disassbuf, "%s(%s,%s.%c)", numStr, regName, Disass68kRegname(xn), c);
759: } else
760: {
761: #if ADDRESS_ON_PC
762: if(ea == 0x3B)
763: sprintf(disassbuf, "$%lx(%s,%s.%c*%d)", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2, Disass68kSpecialRegister(REG_PC), Disass68kRegname(xn), c, 1 << scale);
764: else
765: #endif
766: sprintf(disassbuf, "%s(%s,%s.%c*%d)", numStr, regName, Disass68kRegname(xn), c, 1 << scale);
767: }
768: #if USE_SYMBOLS
769: if(ea == 0x3B)
770: {
771: const char *symStr = Disass68kSymbolName((signed char)(eWord1 & 0xFF) + opcodeAddr + 2, size);
772: if(symStr)
773: {
774: commentBuffer += strlen(commentBuffer);
775: sprintf(commentBuffer+strlen(commentBuffer), "%s", symStr);
776: }
777: }
778: #endif
779: #if !ADDRESS_ON_PC
780: if(ea == 0x3B)
781: {
782: commentBuffer += strlen(commentBuffer);
783: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2);
784: }
785: #endif
786: } else {
787: // FULL EXTENSION WORD FORMAT
788:
1.1.1.4 ! root 789: int bs = (eWord1 >> 7) & 1; // Base Register Suppress 0 = Base Register Added 1 = Base Register Suppressed
! 790: int is = (eWord1 >> 6) & 1; // Index Suppress 0 = Evaluate and Add Index Operand 1 = Suppress Index Operand
! 791: int bdSize = (eWord1 >> 4) & 3; // Base Displacement Size 00 = Reserved 01 = Null Displacement 10 = Word Displacement 11 = Long Displacement
! 792: int iis = eWord1 & 7; // Index/Indirect Selection Indirect and Indexing Operand Determined in Conjunction with Bit 6, Index Suppress
1.1 root 793: bool prefixComma;
1.1.1.4 ! root 794: long bd, od;
1.1 root 795:
796: // reserved, has to be 0
797: if((eWord1 & 8) != 0 || bdSize == 0 || (is && iis > 3) || iis == 4)
798: break;
799:
800: // full extension format is only supported on 68020 or later
801: if((optionCPUTypeMask & MC_020) == 0)
802: return NULL;
803:
804: if(ea == 0x3B)
805: {
806: if((allowedEAs & EA_PCRel) != EA_PCRel)
807: break;
808: } else {
809: if((allowedEAs & EA_dAn) != EA_dAn)
810: break;
811: }
812:
1.1.1.4 ! root 813: bd = 0;
1.1 root 814: switch(bdSize)
815: {
816: case 3:
817: bd = Disass68kGetWord(*addr); *addr += 2;
818: bd <<= 16;
819: case 2:
820: bd |= Disass68kGetWord(*addr); *addr += 2;
821: break;
822: default:
823: break;
824: }
825:
826: prefixComma = false;
827: if(bdSize >= 2 && iis == 0)
828: sprintf(disassbuf, "%s", Disass68kNumber(bd));
829: strcat(disassbuf, "(");
830: if(iis != 0)
831: {
832: // the CPU32 doesn't support the memory indirect mode
833: if(optionCPUTypeMask & MC_CPU32)
834: return NULL;
835:
836: strcat(disassbuf, "[");
837: }
838: if(bdSize >= 2 && iis != 0)
839: {
840: sprintf(disassbuf+strlen(disassbuf), "%s", Disass68kNumber(bd));
841: prefixComma = true;
842: }
843: if(bdSize == 1 && ((bs && is && iis > 0) || (bs && iis >= 5)))
844: {
845: if(ea == 0x3B)
846: {
847: sp = Disass68kSpecialRegister(REG_ZPC);
848: if(!sp) return NULL;
849: strcat(disassbuf, sp);
850: } else {
851: strcat(disassbuf, "0");
852: }
853: }
854: if(!bs)
855: {
856: if(prefixComma)
857: strcat(disassbuf, ",");
858: strcat(disassbuf, regName);
859: prefixComma = true;
860: }
861: if(iis >= 5 && iis <= 7)
862: {
863: strcat(disassbuf, "]");
864: prefixComma = true;
865: }
866: if(!is)
867: {
868: if(prefixComma)
869: strcat(disassbuf, ",");
870: if(scale == 0)
871: {
872: sprintf(disassbuf+strlen(disassbuf), "%s.%c", Disass68kRegname(xn), c);
873: } else
874: {
875: sprintf(disassbuf+strlen(disassbuf), "%s.%c*%d", Disass68kRegname(xn), c, 1 << scale);
876: }
877: }
878: if(iis >= 1 && iis <= 3)
879: {
880: strcat(disassbuf, "]");
881: prefixComma = true;
882: }
1.1.1.4 ! root 883: od = 0;
1.1 root 884: switch(iis & 3)
885: {
886: case 3:
887: od = Disass68kGetWord(*addr); *addr += 2;
888: od <<= 16;
889: case 2:
890: od |= Disass68kGetWord(*addr); *addr += 2;
891: if(prefixComma)
892: strcat(disassbuf, ",");
893: sprintf(disassbuf+strlen(disassbuf), "%s", Disass68kNumber(od));
894: break;
895: default:
896: break;
897: }
898: strcat(disassbuf, ")");
899: }
900: break;
901:
902: // M=111 = 7, Xn/reg = 000 = 0
903: // Absolute Short Addressing Mode
904: // (xxx).W
905: case 0x38:
906: if((allowedEAs & EA_Abs) != EA_Abs)
907: break;
908: eWord1 = Disass68kGetWord(*addr); *addr += 2;
909: val = eWord1;
910: if(eWord1 & 0x8000)
911: val |= 0xFFFF0000;
912: #if USE_SYMBOLS
913: sp = Disass68kSymbolName(val, size);
914: if(sp)
915: {
916: if(options & doptNoBrackets)
917: sprintf(disassbuf, "%s.w", sp);
918: else
919: sprintf(disassbuf, "(%s).w", sp);
920: break;
921: }
922: #endif
923: if(options & doptNoBrackets)
924: {
925: if(val & 0x80000000)
926: sprintf(disassbuf, "$%8.8lx.w", val);
927: else
928: sprintf(disassbuf, "$%4.4lx.w", val);
929: } else {
930: if(val & 0x80000000)
931: sprintf(disassbuf, "($%8.8lx).w", val);
932: else
933: sprintf(disassbuf, "($%4.4lx).w", val);
934: }
935: break;
936:
937: // M=111 = 7, Xn/reg = 001 = 1
938: // Absolute Long Addressing Mode
939: // (xxx).L
940: case 0x39:
941: if((allowedEAs & EA_Abs) != EA_Abs)
942: break;
943: eWord1 = Disass68kGetWord(*addr); *addr += 2;
944: eWord2 = Disass68kGetWord(*addr); *addr += 2;
945: #if USE_SYMBOLS
946: val = (eWord1 << 16) | eWord2;
947: sp = Disass68kSymbolName(val, size);
948: if(sp)
949: {
950: if(options & doptNoBrackets)
951: sprintf(disassbuf, "%s", sp);
952: else
953: sprintf(disassbuf, "(%s).l", sp);
954: break;
955: }
956: #endif
957: if(options & doptNoBrackets)
958: sprintf(disassbuf, "%s", Disass68kNumber((eWord1 << 16) | eWord2));
959: else
960: sprintf(disassbuf, "(%s).l", Disass68kNumber((eWord1 << 16) | eWord2));
961: break;
962:
963: // M=111 = 7, Xn/reg = 010 = 2
964: // Program Counter Indirect with Displacement Mode
965: // (d16,PC)
966: case 0x3A:
967: if((allowedEAs & EA_PCRel) != EA_PCRel)
968: break;
969: eWord1 = Disass68kGetWord(*addr); *addr += 2;
970: sp = Disass68kSpecialRegister(REG_PC);
971: if(!sp) return NULL;
972: #if ADDRESS_ON_PC
973: #if USE_SYMBOLS
974: sp = Disass68kSymbolName(((signed short)eWord1 + *addr - 2), size);
975: if(sp)
976: {
977: sprintf(disassbuf, "%s(%s)", sp, Disass68kSpecialRegister(REG_PC));
978: } else {
979: sprintf(disassbuf, "$%lx(%s)", (signed short)eWord1 + *addr - 2, Disass68kSpecialRegister(REG_PC));
980: }
981: #else
982: sprintf(disassbuf, "$%lx(%s)", (signed short)eWord1 + *addr - 2, Disass68kSpecialRegister(REG_PC));
983: #endif
984: #else
985: sprintf(disassbuf, "%s(%s)", Disass68kNumber(eWord1),sp);
986: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", (signed short)eWord1 + *addr - 2);
987: #endif
988: break;
989:
990: // M=111 = 7, Xn/reg = 100 = 4
991: // Immediate Data
992: // #<xxx>
993: case 0x3C:
994: if((allowedEAs & EA_Immed) != EA_Immed)
995: break;
996: eWord1 = Disass68kGetWord(*addr); *addr += 2;
997: goto immed;
998:
999: case 0x0100: // Immediate Value as a parameter
1000: if((allowedEAs & EA_ImmedParameter) != EA_ImmedParameter)
1001: break;
1002: eWord1 = parameterValue;
1003: immed:
1004: switch(size)
1005: {
1006: case 1: eWord1 &= 0xFF;
1007: case 2:
1008: #if USE_SYMBOLS
1009: if(disassFlag)
1010: {
1011: val = eWord1;
1012: if(eWord1 & 0x8000)
1013: val |= 0xFFFF0000;
1014: sp = Disass68kSymbolName(val, size);
1015: if(sp)
1016: {
1017: sprintf(disassbuf, "#%s", sp);
1018: break;
1019: }
1020: }
1021: #endif
1022: sprintf(disassbuf, "#%s", Disass68kNumber(eWord1));
1023: break;
1024: case 4: eWord2 = Disass68kGetWord(*addr); *addr += 2;
1025: #if USE_SYMBOLS
1026: if(disassFlag)
1027: {
1028: val = (eWord1 << 16) | eWord2;
1029: sp = Disass68kSymbolName(val, size);
1030: if(sp)
1031: {
1032: sprintf(disassbuf, "#%s", sp);
1033: break;
1034: }
1035: }
1036: #endif
1037: sprintf(disassbuf, "#%s", Disass68kNumber((eWord1 << 16) | eWord2));
1038: break;
1039: }
1040: break;
1041:
1042: case 0x0103:
1043: if((allowedEAs & EA_ValueParameter) != EA_ValueParameter)
1044: break;
1045: sprintf(disassbuf, "%d", parameterValue);
1046: break;
1047:
1048: case 0x0101: // Special Registers as in the parameter
1049: if((allowedEAs & EA_SpecialRegister) != EA_SpecialRegister)
1050: break;
1051: sp = Disass68kSpecialRegister(parameterValue);
1052: if(!sp) return NULL;
1053: strcpy(disassbuf, sp);
1054: break;
1055:
1056: case 0x0102: // PC relative jump, like for BRA and friends
1057: if((allowedEAs & EA_PCDisplacement) != EA_PCDisplacement)
1058: break;
1.1.1.4 ! root 1059: pcoffset = 0;
1.1 root 1060: switch(size)
1061: {
1062: case 1: pcoffset = (signed char)parameterValue;
1063: break;
1064: case 2: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1065: pcoffset = (signed short)eWord1;
1066: pcoffset -= 2;
1067: break;
1068: case 4: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1069: eWord2 = Disass68kGetWord(*addr); *addr += 2;
1070: pcoffset = (signed int)((eWord1 << 16) | eWord2);
1071: pcoffset -= 4;
1072: break;
1073: }
1074: #if ADDRESS_ON_PC
1075: #if USE_SYMBOLS
1076: sp = Disass68kSymbolName((*addr + pcoffset), size);
1077: if(sp)
1078: {
1079: strcat(disassbuf, sp);
1080: } else {
1081: sprintf(disassbuf, "$%lx", *addr + pcoffset);
1082: }
1083: #else
1084: sprintf(disassbuf, "$%lx", *addr + pcoffset);
1085: #endif
1086: #else
1087: if(pcoffset < 0)
1088: {
1089: sprintf(disassbuf, "*-$%lx", -pcoffset - 2);
1090: } else {
1091: sprintf(disassbuf, "*+$%lx", pcoffset + 2);
1092: }
1093: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", *addr + pcoffset);
1094: #endif
1095: break;
1096:
1097: default: // 0x3D..0x3F are reserved
1098: break;
1099:
1100: }
1101: if(disassbuf[0] == 0)
1102: return NULL;
1103: return disassbuf + strlen(disassbuf);
1104: }
1105:
1106: /***
1107: * Create a register list for the MOVEM opcode
1108: ***/
1109: static char *Disass68kReglist(char *buf, unsigned short reglist)
1110: {
1111: int bit;
1112: int lastBit = -99;
1113: int lastBitStart = -99;
1114: char regD = options & doptRegisterSmall ? 'd' : 'D';
1115: char regA = options & doptRegisterSmall ? 'a' : 'A';
1116: for(bit=0; bit<=15; ++bit)
1117: {
1118: // bit clear?
1119: if((reglist & (1 << bit)) == 0)
1120: {
1121: // do we have a run? => close it!
1122: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1123: {
1124: *buf++ = '-';
1125: *buf++ = ((bit-1) >= 8) ? regA : regD;
1126: *buf++ = '0' + ((bit-1) & 7);
1127: }
1128: lastBitStart = -1;
1129: continue;
1130: }
1131: // reset when switching from D to A
1132: if(bit == 8 && lastBitStart >= 0)
1133: {
1134: *buf++ = '-';
1135: *buf++ = regD;
1136: *buf++ = '7';
1137: lastBit = 0;
1138: lastBitStart = -99;
1139: }
1140: // separate bits, skip runs of bits to merge them later
1141: if(lastBit >= 0)
1142: {
1143: if(lastBit == bit - 1)
1144: {
1145: lastBit = bit;
1146: continue;
1147: }
1148: *buf++ = '/';
1149: }
1150: *buf++ = (bit >= 8) ? regA : regD;
1151: *buf++ = '0' + (bit & 7);
1152: lastBit = bit;
1153: lastBitStart = bit;
1154: }
1155: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1156: {
1157: *buf++ = '-';
1158: *buf++ = regA;
1159: *buf++ = '7';
1160: }
1161: if(lastBit < 0)
1162: {
1163: *buf++ = '0';
1164: }
1165: *buf = 0;
1166: return buf;
1167: }
1168:
1169: /***
1170: * Flip the bits in an unsigned short, for MOVEM RegList,-(An)
1171: ***/
1172: static unsigned short Disass68kFlipBits(unsigned short mask)
1173: {
1174: unsigned short retMask = 0;
1175: int i;
1176:
1177: for(i=0; i<=15; ++i)
1178: if(mask & (1 << i))
1179: retMask |= (1 << (15-i));
1180: return retMask;
1181: }
1182:
1183: /***
1184: * Create a register list for the MOVEM opcode
1185: ***/
1186: static char *Disass68kFPUReglist(char *buf, unsigned char reglist)
1187: {
1188: int bit;
1189: int lastBit = -99;
1190: int lastBitStart = -99;
1191: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
1192: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
1193: for(bit=0; bit<=7; ++bit)
1194: {
1195: // bit clear?
1196: if((reglist & (1 << bit)) == 0)
1197: {
1198: // do we have a run? => close it!
1199: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1200: {
1201: *buf++ = '-';
1202: *buf++ = regFP1;
1203: *buf++ = regFP2;
1204: *buf++ = '0' + ((bit-1) & 7);
1205: }
1206: lastBitStart = -1;
1207: continue;
1208: }
1209: // separate bits, skip runs of bits to merge them later
1210: if(lastBit >= 0)
1211: {
1212: if(lastBit == bit - 1)
1213: {
1214: lastBit = bit;
1215: continue;
1216: }
1217: *buf++ = '/';
1218: }
1219: *buf++ = regFP1;
1220: *buf++ = regFP2;
1221: *buf++ = '0' + (bit & 7);
1222: lastBit = bit;
1223: lastBitStart = bit;
1224: }
1225: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1226: {
1227: *buf++ = '-';
1228: *buf++ = regFP1;
1229: *buf++ = regFP2;
1230: *buf++ = '7';
1231: }
1232: if(lastBit < 0)
1233: {
1234: *buf++ = '0';
1235: }
1236: *buf = 0;
1237: return buf;
1238: }
1239:
1240:
1241: /***
1242: * List of special cases for the operands
1243: ***/
1244: typedef enum {
1245: ofNone,
1246: ofEa,
1247: ofDn,
1248: ofAn,
1249: ofAni,
1250: ofI,
1251: ofSpecReg,
1252: ofSpecExtReg,
1253: ofD16An,
1254: ofDestDn,
1255: ofDestAn,
1256: ofExtReg,
1257: ofExtAnip,
1258: ofExtReg0,
1259: ofExtRegA0,
1260: ofExtRegD04,
1261: ofExtRegA05,
1262: ofFPUReglist,
1263: ofFPUSRRegList,
1264: ofDestEa6,
1265: ofDestAbsL,
1266: ofIOpcode,
1267: ofCAS,
1268: ofCAS2,
1269: ofI3,
1270: ofExtIm,
1271: ofExtIm32,
1272: ofExtIm4,
1273: ofExtIm10,
1274: ofDisp,
1275: ofPiAn,
1276: ofDestPiAn,
1277: ofAnip,
1278: ofDestAnip,
1279: ofBFEa,
1280: ofRegList,
1281: ofExt4Dn,
1282: ofFPU,
1283: ofFPUMOVE,
1284: ofFMOVECR,
1285: ofFPU3Reg,
1286: ofLineA,
1287: } Disass68kOpcodeFormat;
1288:
1289:
1290: /***
1291: * The order of the table is not important (with the exception of some FPU opcodes, which are commented further down),
1292: * as each opcode should decline if it doesn't match 100%. The 68k CPU also doesn't do guessing based on the context!
1293: ***/
1294: typedef const struct {
1295: int cpuMask;
1296: unsigned long opcodeMask[2*5];
1.1.1.4 ! root 1297: signed char operationSize[4];
1.1 root 1298: char op[5];
1299: const char *opcodeName;
1300: int parameter[5];
1301: int disassFlag;
1302: } OpcodeTableStruct;
1303:
1304: static const OpcodeTableStruct OpcodeTable[] = {
1305: { MC_ALL, {0xff00, 0x0000}, {-1,6,2,0}, {ofI,ofEa}, "ORI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1306: { MC_ALL, {0xf1c0, 0x0100}, {4}, {ofDestDn,ofEa}, "BTST",{0,EA_An|EA_Immed} },
1307: { MC_ALL, {0xf1c0, 0x0140}, {4}, {ofDestDn,ofEa}, "BCHG",{0,EA_Immed|EA_PCRel|EA_An}},
1308: { MC_ALL, {0xf1c0, 0x0180}, {4}, {ofDestDn,ofEa}, "BCLR",{0,EA_Immed|EA_PCRel|EA_An}},
1309: { MC_ALL, {0xf1c0, 0x01C0}, {4}, {ofDestDn,ofEa}, "BSET",{0,EA_Immed|EA_PCRel|EA_An}},
1310: { MC_ALL-MC68060, {0xf1f8, 0x0108}, {2}, {ofD16An,ofDestDn}, "MOVEP.W"},
1311: { MC_ALL-MC68060, {0xf1f8, 0x0148}, {4}, {ofD16An,ofDestDn}, "MOVEP.L"},
1312: { MC_ALL-MC68060, {0xf1f8, 0x0188}, {2}, {ofDestDn,ofD16An}, "MOVEP.W"},
1313: { MC_ALL-MC68060, {0xf1f8, 0x01C8}, {4}, {ofDestDn,ofD16An}, "MOVEP.L"},
1314: { MC_ALL, {0xff00, 0x0200}, {-1,6,2,0}, {ofI,ofEa}, "ANDI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1315: { MC_ALL, {0xff00, 0x0400}, {-1,6,2,0}, {ofI,ofEa}, "SUBI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1316: { MC_ALL, {0xff00, 0x0600}, {-1,6,2,0}, {ofI,ofEa}, "ADDI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1317: { MC_ALL, {0xffc0, 0x0800}, {1}, {ofI,ofEa}, "BTST",{0,EA_An|EA_Immed} },
1318: { MC_ALL, {0xffc0, 0x0840}, {1}, {ofI,ofEa}, "BCHG",{0,EA_Immed|EA_PCRel|EA_An}},
1319: { MC_ALL, {0xffc0, 0x0880}, {1}, {ofI,ofEa}, "BCLR",{0,EA_Immed|EA_PCRel|EA_An}},
1320: { MC_ALL, {0xffc0, 0x08C0}, {1}, {ofI,ofEa}, "BSET",{0,EA_Immed|EA_PCRel|EA_An}},
1321: { MC_ALL, {0xff00, 0x0A00}, {-1,6,2,0}, {ofI,ofEa}, "EORI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1322: { MC_ALL, {0xff00, 0x0C00}, {-1,6,2,0}, {ofI,ofEa}, "CMPI.?",{0,EA_Immed|EA_An}},
1323: { MC_ALL, {0xffff, 0x003C}, {1}, {ofEa,ofSpecReg}, "ORI",{0,REG_CCR} },
1324: { MC_ALL, {0xffff, 0x007C}, {2}, {ofEa,ofSpecReg}, "ORI",{0,REG_SR} },
1325: { MC_ALL, {0xffff, 0x023C}, {1}, {ofEa,ofSpecReg}, "ANDI",{0,REG_CCR} },
1326: { MC_ALL, {0xffff, 0x027C}, {2}, {ofEa,ofSpecReg}, "ANDI",{0,REG_SR} },
1327: { MC_ALL, {0xffff, 0x0A3C}, {1}, {ofEa,ofSpecReg}, "EORI",{0,REG_CCR} },
1328: { MC_ALL, {0xffff, 0x0A7C}, {2}, {ofEa,ofSpecReg}, "EORI",{0,REG_SR} },
1329: { MC68020, {0xffc0, 0x06C0}, {1}, {ofEa}, "CALLM",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1330: { MC68020, {0xfff0, 0x06C0}, {1}, {ofEa}, "RTM"},
1331: { MC_020, {0xf9c0, 0x00C0, 0x0fff,0x0000}, {-1,9,2,0}, {ofEa,ofExtReg}, "CMP2.?",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1332: { MC_020, {0xf9c0, 0x00C0, 0x0fff,0x0800}, {-1,9,2,0}, {ofEa,ofExtReg}, "CHK2.?",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1333: { MC_020&~MC_CPU32, {0xffc0, 0x0AC0, 0xFE38,0x0000}, {1}, {ofCAS,ofEa}, "CAS.B",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1334: { MC_020&~MC_CPU32, {0xffc0, 0x0CC0, 0xFE38,0x0000}, {2}, {ofCAS,ofEa}, "CAS.W",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1335: { MC_020&~MC_CPU32, {0xffc0, 0x0EC0, 0xFE38,0x0000}, {4}, {ofCAS,ofEa}, "CAS.L",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1336: { MC_020&~MC_CPU32, {0xffff, 0x0CFC, 0x0E38,0x0000, 0x0E38,0x0000}, {2}, {ofCAS2}, "CAS2.W"},
1337: { MC_020&~MC_CPU32, {0xffff, 0x0EFC, 0x0E38,0x0000, 0x0E38,0x0000}, {4}, {ofCAS2}, "CAS2.L"},
1338: { MC68010|MC_020, {0xff00, 0x0e00, 0x0fff,0x0000}, {-1,6,2,0}, {ofEa,ofExtReg}, "MOVES.?",{EA_Immed|EA_PCRel|EA_An|EA_Dn,0}},
1339: { MC68010|MC_020, {0xff00, 0x0e00, 0x0fff,0x0800}, {-1,6,2,0}, {ofExtReg,ofEa}, "MOVES.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1340:
1341: { MC_ALL, {0xf000, 0x1000}, {1}, {ofEa,ofDestEa6}, "MOVE.B"},
1342:
1343: { MC_ALL, {0xf000, 0x2000}, {4}, {ofEa,ofDestEa6}, "MOVE.L"},
1344: { MC_ALL, {0xf1c0, 0x2040}, {4}, {ofEa,ofDestAn}, "MOVEA.L",{0},1},
1345:
1346: { MC_ALL, {0xf000, 0x3000}, {2}, {ofEa,ofDestEa6}, "MOVE.W"},
1347: { MC_ALL, {0xf1c0, 0x3040}, {2}, {ofEa,ofDestAn}, "MOVEA.W",{0},1},
1348:
1349: { MC_ALL, {0xff00, 0x4000}, {-1,6,2,0}, {ofEa}, "NEGX.?",{EA_Immed|EA_PCRel|EA_An}},
1350: { MC_020, {0xf1c0, 0x4100}, {4}, {ofEa,ofDestDn}, "CHK.L", {EA_An,0}},
1351: { MC_ALL, {0xf1c0, 0x4180}, {2}, {ofEa,ofDestDn}, "CHK.W", {EA_An,0}},
1352: { MC_ALL, {0xf1c0, 0x41c0}, {4}, {ofEa,ofDestAn}, "LEA",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn,0},1 },
1353: { MC_ALL, {0xff00, 0x4200}, {-1,6,2,0}, {ofEa}, "CLR.?",{EA_Immed|EA_PCRel|EA_An}},
1354: { MC_ALL, {0xff00, 0x4400}, {-1,6,2,0}, {ofEa}, "NEG.?",{EA_Immed|EA_PCRel|EA_An}},
1355: { MC_ALL, {0xff00, 0x4600}, {-1,6,2,0}, {ofEa}, "NOT.?",{EA_Immed|EA_PCRel|EA_An}},
1356: { MC_ALL, {0xffc0, 0x40c0}, {2}, {ofSpecReg,ofEa}, "MOVE",{REG_SR,EA_Immed|EA_PCRel|EA_An} },
1357: { MC_ALL, {0xffc0, 0x42c0}, {1}, {ofSpecReg,ofEa}, "MOVE",{REG_CCR,EA_Immed|EA_PCRel|EA_An} },
1358: { MC_ALL, {0xffc0, 0x44c0}, {1}, {ofEa,ofSpecReg}, "MOVE",{EA_An,REG_CCR} },
1359: { MC_ALL, {0xffc0, 0x46c0}, {2}, {ofEa,ofSpecReg}, "MOVE",{EA_An,REG_SR} },
1360: { MC_ALL, {0xffc0, 0x4800}, {1}, {ofEa}, "NBCD",{EA_Immed|EA_PCRel|EA_An}},
1361: { MC_020, {0xfff8, 0x4808}, {4}, {ofEa,ofI}, "LINK.L"},
1362: { MC_ALL, {0xffc0, 0x4840}, {0}, {ofEa}, "PEA",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn},1 },
1363: { MC_ALL, {0xfff8, 0x4840}, {4}, {ofEa}, "SWAP"},
1364: { MC68010|MC_020, {0xfff8, 0x4848}, {0}, {ofIOpcode}, "BKPT",{0x07} },
1365: { MC_ALL, {0xffc0, 0x4880, 0x10000}, {2}, {ofRegList,ofEa}, "MOVEM.W",{0,EA_Dn|EA_An|EA_Immed|EA_Anip|EA_PCRel} },
1366: { MC_ALL, {0xffc0, 0x48c0, 0x10000}, {4}, {ofRegList,ofEa}, "MOVEM.L",{0,EA_Dn|EA_An|EA_Immed|EA_Anip|EA_PCRel} },
1367: { MC_ALL, {0xfff8, 0x4880}, {2}, {ofEa}, "EXT.W"},
1368: { MC_ALL, {0xfff8, 0x48c0}, {4}, {ofEa}, "EXT.L"},
1369: { MC_020, {0xfff8, 0x49c0}, {4}, {ofEa}, "EXTB.L"},
1370: { MC_ALL, {0xff00, 0x4a00}, {-1,6,2,0}, {ofEa}, "TST.?"},
1371: { MC_ALL, {0xffc0, 0x4ac0}, {1}, {ofEa}, "TAS",{EA_Immed|EA_PCRel|EA_An}},
1372: { MC_CPU32, {0xffff, 0x4afa}, {0}, {ofNone}, "BGND"},
1373: { MC_ALL, {0xffff, 0x4afc}, {0}, {ofNone}, "ILLEGAL"},
1374: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0000}, {4}, {ofEa,ofExtReg}, "MULU.L", {EA_An,0}},
1375: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0800}, {4}, {ofEa,ofExtReg}, "MULS.L", {EA_An,0}},
1376: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0000}, {4}, {ofEa,ofExtReg}, "DIVU.L", {EA_An,0}},
1377: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0800}, {4}, {ofEa,ofExtReg}, "DIVS.L", {EA_An,0}},
1378: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0400}, {4}, {ofEa,ofExtReg,ofExtReg0}, "MULU.L", {EA_An,0,0}},
1379: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0c00}, {4}, {ofEa,ofExtReg,ofExtReg0}, "MULS.L", {EA_An,0,0}},
1380: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0400}, {4}, {ofEa,ofExtReg,ofExtReg0}, "DIVU.L", {EA_An,0,0}},
1381: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0c00}, {4}, {ofEa,ofExtReg,ofExtReg0}, "DIVS.L", {EA_An,0,0}},
1382: { MC_ALL, {0xffc0, 0x4c80, 0x10000}, {2}, {ofEa,ofRegList}, "MOVEM.W",{EA_Dn|EA_An|EA_Immed|EA_piAn,0} },
1383: { MC_ALL, {0xffc0, 0x4cc0, 0x10000}, {4}, {ofEa,ofRegList}, "MOVEM.L",{EA_Dn|EA_An|EA_Immed|EA_piAn,0} },
1384: { MC_ALL, {0xfff0, 0x4e40}, {0}, {ofIOpcode}, "TRAP",{0x0f} },
1385: { MC_ALL, {0xfff8, 0x4e50}, {2}, {ofAn,ofI}, "LINK"},
1386: { MC_ALL, {0xfff8, 0x4e58}, {4}, {ofAn}, "UNLK"},
1387: { MC_ALL, {0xfff8, 0x4e60}, {4}, {ofAn,ofSpecReg}, "MOVE",{0,REG_USP} },
1388: { MC_ALL, {0xfff8, 0x4e68}, {4}, {ofSpecReg,ofAn}, "MOVE",{REG_USP,0} },
1389: { MC_ALL, {0xffff, 0x4e70}, {0}, {ofNone}, "RESET"},
1390: { MC_ALL, {0xffff, 0x4e71}, {0}, {ofNone}, "NOP"},
1391: { MC_ALL, {0xffff, 0x4e72}, {2}, {ofI}, "STOP"},
1392: { MC_ALL, {0xffff, 0x4e73}, {0}, {ofNone}, "RTE"},
1393: { MC68010|MC_020, {0xffff, 0x4e74}, {2}, {ofI}, "RTD"},
1394: { MC_ALL, {0xffff, 0x4e75}, {0}, {ofNone}, "RTS"},
1395: { MC_ALL, {0xffff, 0x4e76}, {0}, {ofNone}, "TRAPV"},
1396: { MC_ALL, {0xffff, 0x4e77}, {0}, {ofNone}, "RTR"},
1397: { MC68010|MC_020, {0xffff, 0x4e7a, 0x10000}, {4}, {ofSpecExtReg,ofExtReg}, "MOVEC"},
1398: { MC68010|MC_020, {0xffff, 0x4e7b, 0x10000}, {4}, {ofExtReg,ofSpecExtReg}, "MOVEC"},
1399: { MC_ALL, {0xffc0, 0x4e80}, {0}, {ofEa}, "JSR",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1400: { MC_ALL, {0xffc0, 0x4ec0}, {0}, {ofEa}, "JMP",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1401:
1402: { MC_ALL, {0xf1c0, 0x5000}, {1}, {ofI3,ofEa}, "ADDQ.B",{0,EA_An|EA_Immed|EA_PCRel} },
1403: { MC_ALL, {0xf1c0, 0x5040}, {2}, {ofI3,ofEa}, "ADDQ.W",{0,EA_Immed|EA_PCRel} },
1404: { MC_ALL, {0xf1c0, 0x5080}, {4}, {ofI3,ofEa}, "ADDQ.L",{0,EA_Immed|EA_PCRel} },
1405: { MC_ALL, {0xf0c0, 0x50C0}, {1}, {ofEa}, "Sci",{EA_Immed|EA_PCRel|EA_An}},
1406: { MC_ALL, {0xf0f8, 0x50C8}, {2}, {ofDn,ofDisp}, "DBcd"},
1407: { MC_020, {0xf0ff, 0x50fa}, {2}, {ofI}, "TRAPci.W"},
1408: { MC_020, {0xf0ff, 0x50fb}, {4}, {ofI}, "TRAPci.L"},
1409: { MC_020, {0xf0ff, 0x50fc}, {0}, {ofNone}, "TRAPci"},
1410: { MC_ALL, {0xf1c0, 0x5100}, {1}, {ofI3,ofEa}, "SUBQ.B",{0,EA_An|EA_Immed|EA_PCRel} },
1411: { MC_ALL, {0xf1c0, 0x5140}, {2}, {ofI3,ofEa}, "SUBQ.W",{0,EA_Immed|EA_PCRel} },
1412: { MC_ALL, {0xf1c0, 0x5180}, {4}, {ofI3,ofEa}, "SUBQ.L",{0,EA_Immed|EA_PCRel} },
1413:
1414: { MC_ALL, {0xf0ff, 0x6000}, {2}, {ofDisp}, "Bcb"},
1415: { MC_ALL, {0xf000, 0x6000}, {1}, {ofDisp}, "Bcb.S"},
1416: { MC_020, {0xf0ff, 0x60FF}, {4}, {ofDisp}, "Bcb.L"},
1417:
1418: { MC_ALL, {0xf100, 0x7000}, {0}, {ofIOpcode,ofDestDn}, "MOVEQ", {0xFF,0}},
1419:
1420: { MC_ALL, {0xf100, 0x8000}, {-1,6,2,0}, {ofEa,ofDestDn}, "OR.?", {EA_An,0}},
1421: { MC_ALL, {0xf100, 0x8100}, {-1,6,2,0}, {ofDestDn,ofEa}, "OR.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1422: { MC_ALL, {0xf1f8, 0x8100}, {1}, {ofDn,ofDestDn}, "SBCD"},
1423: { MC_ALL, {0xf1f8, 0x8108}, {1}, {ofPiAn,ofDestPiAn}, "SBCD"},
1424: { MC_020&~MC_CPU32, {0xf1f8, 0x8140, 0x10000}, {0}, {ofDn,ofDestDn,ofExtIm}, "PACK"},
1425: { MC_020&~MC_CPU32, {0xf1f8, 0x8148, 0x10000}, {0}, {ofPiAn,ofDestPiAn,ofExtIm}, "PACK"},
1426: { MC_020&~MC_CPU32, {0xf1f8, 0x8180, 0x10000}, {0}, {ofDn,ofDestDn,ofExtIm}, "UNPK"},
1427: { MC_020&~MC_CPU32, {0xf1f8, 0x8188, 0x10000}, {0}, {ofPiAn,ofDestPiAn,ofExtIm}, "UNPK"},
1428: { MC_ALL, {0xf1c0, 0x80c0}, {2}, {ofEa,ofDestDn}, "DIVU.W", {EA_An,0}},
1429: { MC_ALL, {0xf1c0, 0x81c0}, {2}, {ofEa,ofDestDn}, "DIVS.W", {EA_An,0}},
1430:
1431: { MC_ALL, {0xf1c0, 0x9000}, {1}, {ofEa,ofDestDn}, "SUB.B", {EA_An,0}},
1432: { MC_ALL, {0xf1c0, 0x9040}, {2}, {ofEa,ofDestDn}, "SUB.W"},
1433: { MC_ALL, {0xf1c0, 0x9080}, {4}, {ofEa,ofDestDn}, "SUB.L"},
1434: { MC_ALL, {0xf1c0, 0x90c0}, {2}, {ofEa,ofDestAn}, "SUBA.W"},
1435: { MC_ALL, {0xf1c0, 0x91c0}, {4}, {ofEa,ofDestAn}, "SUBA.L"},
1436: { MC_ALL, {0xf100, 0x9100}, {-1,6,2,0}, {ofDestDn,ofEa}, "SUB.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1437: { MC_ALL, {0xf138, 0x9100}, {-1,6,2,0}, {ofDn,ofDestDn}, "SUBX.?"},
1438: { MC_ALL, {0xf138, 0x9108}, {-1,6,2,0}, {ofPiAn,ofDestPiAn}, "SUBX.?"},
1439:
1440: { MC_ALL, {0xf000, 0xa000}, {0}, {ofLineA}, "LINEA"},
1441:
1442: { MC_ALL, {0xf1c0, 0xb000}, {1}, {ofEa,ofDestDn}, "CMP.B", {EA_An,0}},
1443: { MC_ALL, {0xf1c0, 0xb040}, {2}, {ofEa,ofDestDn}, "CMP.W"},
1444: { MC_ALL, {0xf1c0, 0xb080}, {4}, {ofEa,ofDestDn}, "CMP.L"},
1445: { MC_ALL, {0xf1c0, 0xb0c0}, {2}, {ofEa,ofDestAn}, "CMPA.W"},
1446: { MC_ALL, {0xf1c0, 0xb1c0}, {4}, {ofEa,ofDestAn}, "CMPA.L"},
1447: { MC_ALL, {0xf100, 0xb100}, {-1,6,2,0}, {ofDestDn,ofEa}, "EOR.?",{0,EA_An|EA_Immed|EA_PCRel} },
1448: { MC_ALL, {0xf138, 0xb108}, {-1,6,2,0}, {ofAnip,ofDestAnip}, "CMPM.?"},
1449:
1450: { MC_ALL, {0xf100, 0xc000}, {-1,6,2,0}, {ofEa,ofDestDn}, "AND.?", {EA_An,0}},
1451: { MC_ALL, {0xf100, 0xc100}, {-1,6,2,0}, {ofDestDn,ofEa}, "AND.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1452: { MC_ALL, {0xf1f8, 0xc100}, {1}, {ofDn,ofDestDn}, "ABCD"},
1453: { MC_ALL, {0xf1f8, 0xc108}, {1}, {ofPiAn,ofDestPiAn}, "ABCD"},
1454: { MC_ALL, {0xf1f8, 0xc140}, {1}, {ofDestDn,ofDn}, "EXG"},
1455: { MC_ALL, {0xf1f8, 0xc148}, {1}, {ofDestAn,ofAn}, "EXG"},
1456: { MC_ALL, {0xf1f8, 0xc188}, {1}, {ofDestDn,ofAn}, "EXG"},
1457: { MC_ALL, {0xf1c0, 0xc0c0}, {2}, {ofEa,ofDestDn}, "MULU.W", {EA_An,0}},
1458: { MC_ALL, {0xf1c0, 0xc1c0}, {2}, {ofEa,ofDestDn}, "MULS.W", {EA_An,0}},
1459:
1460: { MC_ALL, {0xf1c0, 0xd000}, {1}, {ofEa,ofDestDn}, "ADD.B", {EA_An,0}},
1461: { MC_ALL, {0xf1c0, 0xd040}, {2}, {ofEa,ofDestDn}, "ADD.W"},
1462: { MC_ALL, {0xf1c0, 0xd080}, {4}, {ofEa,ofDestDn}, "ADD.L"},
1463: { MC_ALL, {0xf1c0, 0xd0c0}, {2}, {ofEa,ofDestAn}, "ADDA.W"},
1464: { MC_ALL, {0xf1c0, 0xd1c0}, {4}, {ofEa,ofDestAn}, "ADDA.L"},
1465: { MC_ALL, {0xf100, 0xd100}, {-1,6,2,0}, {ofDestDn,ofEa}, "ADD.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1466: { MC_ALL, {0xf138, 0xd100}, {-1,6,2,0}, {ofDn,ofDestDn}, "ADDX.?"},
1467: { MC_ALL, {0xf138, 0xd108}, {-1,6,2,0}, {ofPiAn,ofDestPiAn}, "ADDX.?"},
1468:
1469: { MC_ALL, {0xf138, 0xe000}, {-1,6,2,0}, {ofI3,ofDn}, "ASR.?"},
1470: { MC_ALL, {0xf138, 0xe008}, {-1,6,2,0}, {ofI3,ofDn}, "LSR.?"},
1471: { MC_ALL, {0xf138, 0xe010}, {-1,6,2,0}, {ofI3,ofDn}, "ROXR.?"},
1472: { MC_ALL, {0xf138, 0xe018}, {-1,6,2,0}, {ofI3,ofDn}, "ROR.?"},
1473: { MC_ALL, {0xf138, 0xe020}, {-1,6,2,0}, {ofDestDn,ofDn}, "ASR.?"},
1474: { MC_ALL, {0xf138, 0xe028}, {-1,6,2,0}, {ofDestDn,ofDn}, "LSR.?"},
1475: { MC_ALL, {0xf138, 0xe030}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROXR.?"},
1476: { MC_ALL, {0xf138, 0xe038}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROR.?"},
1477: { MC_ALL, {0xf138, 0xe100}, {-1,6,2,0}, {ofI3,ofDn}, "ASL.?"},
1478: { MC_ALL, {0xf138, 0xe108}, {-1,6,2,0}, {ofI3,ofDn}, "LSL.?"},
1479: { MC_ALL, {0xf138, 0xe110}, {-1,6,2,0}, {ofI3,ofDn}, "ROXL.?"},
1480: { MC_ALL, {0xf138, 0xe118}, {-1,6,2,0}, {ofI3,ofDn}, "ROL.?"},
1481: { MC_ALL, {0xf138, 0xe120}, {-1,6,2,0}, {ofDestDn,ofDn}, "ASL.?"},
1482: { MC_ALL, {0xf138, 0xe128}, {-1,6,2,0}, {ofDestDn,ofDn}, "LSL.?"},
1483: { MC_ALL, {0xf138, 0xe130}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROXL.?"},
1484: { MC_ALL, {0xf138, 0xe138}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROL.?"},
1485: { MC_ALL, {0xffc0, 0xe0c0}, {1}, {ofEa}, "ASR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1486: { MC_ALL, {0xffc0, 0xe1c0}, {1}, {ofEa}, "ASL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1487: { MC_ALL, {0xffc0, 0xe2c0}, {1}, {ofEa}, "LSR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1488: { MC_ALL, {0xffc0, 0xe3c0}, {1}, {ofEa}, "LSL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1489: { MC_ALL, {0xffc0, 0xe4c0}, {1}, {ofEa}, "ROXR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1490: { MC_ALL, {0xffc0, 0xe5c0}, {1}, {ofEa}, "ROXL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1491: { MC_ALL, {0xffc0, 0xe6c0}, {1}, {ofEa}, "ROR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1492: { MC_ALL, {0xffc0, 0xe7c0}, {1}, {ofEa}, "ROL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1493: { MC_020&~MC_CPU32, {0xffc0, 0xe8c0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFTST",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1494: { MC_020&~MC_CPU32, {0xffc0, 0xe9c0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFEXTU",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1495: { MC_020&~MC_CPU32, {0xffc0, 0xeac0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFCHG",{EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1496: { MC_020&~MC_CPU32, {0xffc0, 0xebc0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFEXTS",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1497: { MC_020&~MC_CPU32, {0xffc0, 0xecc0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFCLR",{EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1498: { MC_020&~MC_CPU32, {0xffc0, 0xedc0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFFFO",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1499: { MC_020&~MC_CPU32, {0xffc0, 0xeec0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFSET",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1500: { MC_020&~MC_CPU32, {0xffc0, 0xefc0, 0x8000, 0x0000}, {1}, {ofExtReg,ofBFEa}, "BFINS",{0,EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1501:
1502:
1503: #define PMMU_COPROC_ID 0 // 0 is the standard PMMU
1504:
1505: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2000}, {0}, {ofSpecReg,ofEa}, "PLOADW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1506: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2001}, {0}, {ofSpecReg,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1507: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2008}, {0}, {ofExtReg0,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1508: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff0, 0x2010}, {0}, {ofExtIm4,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1509:
1510: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2200}, {0}, {ofSpecReg,ofEa}, "PLOADR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1511: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2201}, {0}, {ofSpecReg,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1512: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2208}, {0}, {ofExtReg0,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1513: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff0, 0x2210}, {0}, {ofExtIm4,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1514:
1515: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0xa000}, {0}, {ofEa}, "PFLUSHR",{EA_Dn|EA_An} },
1516:
1517: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0800}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1518: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0900}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1519: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0B00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1520: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0C00}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1521: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0C00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1522: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0D00}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1523: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0E00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1524: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0F00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1525: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4000}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1526: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4100}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1527: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4200}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1528: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4300}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1529: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4800}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1530: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4900}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1531: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4A00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1532: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4B00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1533: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4C00}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1534: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4D00}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1535: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4e00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1536: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4f00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1537: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x6000}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_MMUSR} },
1538: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x6200}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_MMUSR} },
1539:
1540: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2800}, {0}, {ofSpecReg,ofEa}, "PVALID",{REG_VAL,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1541: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2C00}, {0}, {ofExtRegA0,ofEa}, "PVALID",{0,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1542:
1543: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8000}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1544: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8001}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1545: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f8, 0x8008}, {0}, {ofExtReg0,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1546: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f0, 0x8010}, {0}, {ofExtIm4,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1547:
1548: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8200}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1549: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8201}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1550: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f8, 0x8208}, {0}, {ofExtReg0,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1551: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f0, 0x8210}, {0}, {ofExtIm4,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1552:
1553: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8100}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1554: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8101}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1555: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe318, 0x8108}, {0}, {ofExtReg0,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1556: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe310, 0x8110}, {0}, {ofExtIm4,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1557:
1558: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8300}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1559: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8301}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1560: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe318, 0x8308}, {0}, {ofExtReg0,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1561: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe310, 0x8310}, {0}, {ofExtIm4,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1562:
1563: { MC_PMMU, {0xffc0, 0xf040|(PMMU_COPROC_ID<<9), 0xfff0, 0x8310}, {0}, {ofEa}, "PScp",{EA_An|EA_Immed|EA_PCRel} },
1564: { MC_PMMU, {0xfff8, 0xf048|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000}, {2}, {ofDn,ofDisp}, "PDBcp"},
1565: { MC_PMMU, {0xffff, 0xf07A|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {2}, {ofExtIm32}, "PTRAPcp.W" },
1566: { MC_PMMU, {0xffff, 0xf07B|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {4}, {ofExtIm32}, "PTRAPcp.L" },
1567: { MC_PMMU, {0xffff, 0xf07C|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000}, {0}, {ofNone}, "PTRAPcp" },
1568: { MC_PMMU, {0xfff0, 0xf080|(PMMU_COPROC_ID<<9)}, {2}, {ofDisp}, "PBcp.W"},
1569: { MC_PMMU, {0xfff0, 0xf0C0|(PMMU_COPROC_ID<<9)}, {4}, {ofDisp}, "PBcp.L"},
1570: { MC_PMMU, {0xffc0, 0xf100|(PMMU_COPROC_ID<<9)}, {0}, {ofEa}, "PSAVE",{EA_Dn|EA_An|EA_Anip|EA_Immed} },
1571: { MC_PMMU, {0xffc0, 0xf140|(PMMU_COPROC_ID<<9)}, {0}, {ofEa}, "PRESTORE",{EA_Dn|EA_An|EA_piAn|EA_Immed} },
1572:
1573:
1574: #define MC040_COPROC_ID 3 // 3 is the code for some 68040/68060 opcodes
1575:
1576: { MC68040|MC68060, {0xfff8, 0xf000|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAnip,ofDestAbsL}, "MOVE16"},
1577: { MC68040|MC68060, {0xfff8, 0xf008|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofDestAbsL,ofAnip}, "MOVE16"},
1578: { MC68040|MC68060, {0xfff8, 0xf010|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAni,ofDestAbsL}, "MOVE16"},
1579: { MC68040|MC68060, {0xfff8, 0xf018|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofDestAbsL,ofAni}, "MOVE16"},
1580: { MC68040|MC68060, {0xfff8, 0xf020|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAnip,ofExtAnip}, "MOVE16"},
1581:
1582:
1583: #define CPU32_COPROC_ID 4 // 4 is the code for some CPU32 opcodes
1584:
1585: { MC68040|MC68060, {0xfff8, 0xf008|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_NONE} },
1586: { MC68040|MC68060, {0xfff8, 0xf048|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_DC} },
1587: { MC68040|MC68060, {0xfff8, 0xf088|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_IC} },
1588: { MC68040|MC68060, {0xfff8, 0xf0C8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_ICDC} },
1589:
1590: { MC68040|MC68060, {0xfff8, 0xf010|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_NONE} },
1591: { MC68040|MC68060, {0xfff8, 0xf050|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_DC} },
1592: { MC68040|MC68060, {0xfff8, 0xf090|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_IC} },
1593: { MC68040|MC68060, {0xfff8, 0xf0D0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_ICDC} },
1594:
1595: { MC68040|MC68060, {0xfff8, 0xf018|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_NONE} },
1596: { MC68040|MC68060, {0xfff8, 0xf058|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_DC} },
1597: { MC68040|MC68060, {0xfff8, 0xf098|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_IC} },
1598: { MC68040|MC68060, {0xfff8, 0xf0D8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_ICDC} },
1599:
1600: { MC68040|MC68060, {0xfff8, 0xf028|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_NONE} },
1601: { MC68040|MC68060, {0xfff8, 0xf068|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_DC} },
1602: { MC68040|MC68060, {0xfff8, 0xf0A8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_IC} },
1603: { MC68040|MC68060, {0xfff8, 0xf0E8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_ICDC} },
1604:
1605: { MC68040|MC68060, {0xfff8, 0xf030|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_NONE} },
1606: { MC68040|MC68060, {0xfff8, 0xf070|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_DC} },
1607: { MC68040|MC68060, {0xfff8, 0xf0B0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_IC} },
1608: { MC68040|MC68060, {0xfff8, 0xf0F0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_ICDC} },
1609:
1610: { MC68040|MC68060, {0xfff8, 0xf038|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_NONE} },
1611: { MC68040|MC68060, {0xfff8, 0xf078|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_DC} },
1612: { MC68040|MC68060, {0xfff8, 0xf0B8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_IC} },
1613: { MC68040|MC68060, {0xfff8, 0xf0F8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_ICDC} },
1614:
1615: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f08, 0x0100}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLU.?" },
1616: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0100}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLU.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1617: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f28, 0x0500}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLUN.?" },
1618: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0500}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLUN.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1619:
1620: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f08, 0x0900}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLS.?" },
1621: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0900}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLS.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1622: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f28, 0x0D00}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLSN.?" },
1623: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0D00}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLSN.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1624:
1625: { MC_CPU32, {0xffff, 0xf000|(CPU32_COPROC_ID<<9), 0xffff, 0x01C0}, {2}, {ofI}, "LPSTOP" },
1626:
1627:
1628: #define FPU_COPROC_ID 1 // 1 is the standard FPU, required to be 1 for the 68040 anyway
1629:
1630: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0000}, {-1,16+10,3,1}, {ofFPU}, "FMOVE.?" },
1631: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0001}, {-1,16+10,3,1}, {ofFPU}, "FINT.?" },
1632: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0002}, {-1,16+10,3,1}, {ofFPU}, "FSINH.?" },
1633: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0003}, {-1,16+10,3,1}, {ofFPU}, "FINTRZ.?" },
1634: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0004}, {-1,16+10,3,1}, {ofFPU}, "FSQRT.?" },
1635: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0006}, {-1,16+10,3,1}, {ofFPU}, "FLOGNP1.?" },
1636: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0008}, {-1,16+10,3,1}, {ofFPU}, "FETOXM1.?" },
1637: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0009}, {-1,16+10,3,1}, {ofFPU}, "FTANH.?" },
1638: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000A}, {-1,16+10,3,1}, {ofFPU}, "FATAN.?" },
1639: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000C}, {-1,16+10,3,1}, {ofFPU}, "FASIN.?" },
1640: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000D}, {-1,16+10,3,1}, {ofFPU}, "FATANH.?" },
1641: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000E}, {-1,16+10,3,1}, {ofFPU}, "FSIN.?" },
1642: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000F}, {-1,16+10,3,1}, {ofFPU}, "FTAN.?" },
1643: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0010}, {-1,16+10,3,1}, {ofFPU}, "FETOX.?" },
1644: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0011}, {-1,16+10,3,1}, {ofFPU}, "FTWOTOX.?" },
1645: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0012}, {-1,16+10,3,1}, {ofFPU}, "FTENTOX.?" },
1646: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0014}, {-1,16+10,3,1}, {ofFPU}, "FLOGN.?" },
1647: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0015}, {-1,16+10,3,1}, {ofFPU}, "FLOG10.?" },
1648: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0016}, {-1,16+10,3,1}, {ofFPU}, "FLOG2.?" },
1649: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0018}, {-1,16+10,3,1}, {ofFPU}, "FABS.?" },
1650: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0019}, {-1,16+10,3,1}, {ofFPU}, "FCOSH.?" },
1651: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001A}, {-1,16+10,3,1}, {ofFPU}, "FNEG.?" },
1652: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001C}, {-1,16+10,3,1}, {ofFPU}, "FACOS.?" },
1653: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001D}, {-1,16+10,3,1}, {ofFPU}, "FCOS.?" },
1654: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001E}, {-1,16+10,3,1}, {ofFPU}, "FGETEXP.?" },
1655: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001F}, {-1,16+10,3,1}, {ofFPU}, "FGETMAN.?" },
1656: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0020}, {-1,16+10,3,1}, {ofFPU}, "FDIV.?" },
1657: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0021}, {-1,16+10,3,1}, {ofFPU}, "FMOD.?" },
1658: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0022}, {-1,16+10,3,1}, {ofFPU}, "FADD.?" },
1659: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0023}, {-1,16+10,3,1}, {ofFPU}, "FMUL.?" },
1660: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0024}, {-1,16+10,3,1}, {ofFPU}, "FSGLDIV.?" },
1661: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0025}, {-1,16+10,3,1}, {ofFPU}, "FREM.?" },
1662: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0026}, {-1,16+10,3,1}, {ofFPU}, "FSCALE.?" },
1663: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0027}, {-1,16+10,3,1}, {ofFPU}, "FSGLMUL.?" },
1664: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0028}, {-1,16+10,3,1}, {ofFPU}, "FSUB.?" },
1665: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA078,0x0030}, {-1,16+10,3,1}, {ofFPU3Reg}, "FSINCOS.?" },
1666: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0038}, {-1,16+10,3,1}, {ofFPU}, "FCMP.?" },
1667: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x003A}, {-1,16+10,3,1}, {ofFPU}, "FTST.?" },
1668: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0040}, {-1,16+10,3,1}, {ofFPU}, "FSMOVE.?" },
1669: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0041}, {-1,16+10,3,1}, {ofFPU}, "FSSQRT.?" },
1670: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0042}, {-1,16+10,3,1}, {ofFPU}, "FSADD.?" },
1671: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0044}, {-1,16+10,3,1}, {ofFPU}, "FDMOVE.?" },
1672: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0045}, {-1,16+10,3,1}, {ofFPU}, "FDSQRT.?" },
1673: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0046}, {-1,16+10,3,1}, {ofFPU}, "FDADD.?" },
1674: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0058}, {-1,16+10,3,1}, {ofFPU}, "FSABS.?" },
1675: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005A}, {-1,16+10,3,1}, {ofFPU}, "FSNEG.?" },
1676: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005C}, {-1,16+10,3,1}, {ofFPU}, "FDABS.?" },
1677: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005E}, {-1,16+10,3,1}, {ofFPU}, "FDNEG.?" },
1678: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0060}, {-1,16+10,3,1}, {ofFPU}, "FSDIV.?" },
1679: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0063}, {-1,16+10,3,1}, {ofFPU}, "FSMUL.?" },
1680: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0064}, {-1,16+10,3,1}, {ofFPU}, "FDDIV.?" },
1681: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0067}, {-1,16+10,3,1}, {ofFPU}, "FDMUL.?" },
1682: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0068}, {-1,16+10,3,1}, {ofFPU}, "FSSUB.?" },
1683: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x006C}, {-1,16+10,3,1}, {ofFPU}, "FDSUB.?" },
1684: { MC68040|MC_FPU, {0xffff, 0xf000|(FPU_COPROC_ID<<9),0xFC00,0x5C00}, {0}, {ofFMOVECR}, "FMOVECR" },
1685:
1686: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE000,0x6000}, {-1,16+10,3,1}, {ofFPUMOVE}, "FMOVE.?" },
1687:
1688: // these 3 are special versions of MOVEM with just one register, they have to be before the FMOVEM version
1689: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x8400}, {0}, {ofEa,ofSpecReg}, "FMOVE", {0,REG_FPU_FPIAR} },
1690: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x8800}, {0}, {ofEa,ofSpecReg}, "FMOVE", {EA_An,REG_FPU_FPSR} },
1691: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x9000}, {0}, {ofEa,ofSpecReg}, "FMOVE", {EA_An,REG_FPU_FPCR} },
1692: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE3FF,0x8000}, {0}, {ofEa,ofFPUSRRegList}, "FMOVEM", {EA_Dn|EA_An,0} },
1693: // these 3 are special versions of MOVEM with just one register, they have to be before the FMOVEM version
1694: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xA400}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPIAR,EA_Immed|EA_PCRel} },
1695: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xA800}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPSR,EA_An|EA_Immed|EA_PCRel} },
1696: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xB000}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPCR,EA_An|EA_Immed|EA_PCRel} },
1697: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE3FF,0xA000}, {0}, {ofFPUSRRegList,ofEa}, "FMOVEM", {0,EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1698:
1699: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE00,0xC000}, {0}, {ofFPUReglist,ofEa}, "FMOVEM.X",{0,EA_Dn|EA_An|EA_Anip|EA_Immed} },
1700: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE8F,0xC800}, {0}, {ofExtRegD04,ofEa}, "FMOVEM.X",{0,EA_Dn|EA_An|EA_piAn|EA_Immed} },
1701: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE00,0xE000}, {0}, {ofEa,ofFPUReglist}, "FMOVEM.X",{EA_Dn|EA_An|EA_piAn|EA_Immed,0} },
1702: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE8F,0xE800}, {0}, {ofEa,ofExtRegD04}, "FMOVEM.X",{EA_Dn|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1703:
1704: { MC68040|MC_FPU, {0xffc0, 0xf040|(FPU_COPROC_ID<<9),0xFFC0,0x0000}, {0}, {ofEa}, "FScf.B",{EA_An|EA_Immed|EA_PCRel} },
1705: { MC68040|MC_FPU, {0xfff8, 0xf048|(FPU_COPROC_ID<<9),0xFFC0,0x0000}, {2}, {ofDn,ofDisp}, "FDBcf" },
1706: { MC68040|MC_FPU, {0xffff, 0xf07A|(FPU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {2}, {ofExtIm32}, "FTRAPcf.W" },
1707: { MC68040|MC_FPU, {0xffff, 0xf07B|(FPU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {4}, {ofExtIm32}, "FTRAPcf.L" },
1708: { MC68040|MC_FPU, {0xffff, 0xf07C|(FPU_COPROC_ID<<9), 0xfff0, 0x0000}, {0}, {ofNone}, "FTRAPcf" },
1709:
1710: // FNOP _has_ to be before FBcf.W, not worth to have a special case for that one
1711: { MC68040|MC_FPU, {0xffff, 0xf080|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {0}, {ofNone}, "FNOP" },
1712: { MC68040|MC_FPU, {0xffc0, 0xf080|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {2}, {ofDisp}, "FBcF.W" },
1713: { MC68040|MC_FPU, {0xffc0, 0xf0c0|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {4}, {ofDisp}, "FBcF.L" },
1714: { MC68040|MC68060|MC_FPU, {0xffc0, 0xf100|(FPU_COPROC_ID<<9)}, {0}, {ofEa}, "FSAVE", {EA_Dn|EA_An|EA_piAn|EA_Immed} },
1715: { MC68040|MC68060|MC_FPU, {0xffc0, 0xf140|(FPU_COPROC_ID<<9)}, {0}, {ofEa}, "FRESTORE", {EA_Dn|EA_An|EA_piAn|EA_Immed} },
1716:
1.1.1.4 ! root 1717: { 0 }
1.1 root 1718: };
1719:
1720: static int Disass68k(long addr, char *labelBuffer, char *opcodeBuffer, char *operandBuffer, char *commentBuffer)
1721: {
1722: long baseAddr = addr;
1723: int val;
1.1.1.4 ! root 1724: int i;
! 1725: int count = 0;
! 1726: char addressLabel[256];
! 1727: char cmtBuffer[256];
! 1728: Disass68kDataType type;
! 1729: int index;
! 1730: long opcodeAddr;
! 1731:
1.1 root 1732: labelBuffer[0] = 0;
1733: opcodeBuffer[0] = 0;
1734: operandBuffer[0] = 0;
1735: commentBuffer[0] = 0;
1736:
1.1.1.4 ! root 1737: type = Disass68kType(baseAddr, addressLabel, cmtBuffer, &count);
1.1 root 1738: if(addressLabel[0])
1739: sprintf(labelBuffer, "%s:", addressLabel);
1740: sprintf(commentBuffer, "%s", cmtBuffer);
1741: switch(type)
1742: {
1.1.1.4 ! root 1743: case dtByte:
! 1744: if(count > 8)
! 1745: count = 8;
! 1746: strcpy(opcodeBuffer,"DC.B");
! 1747: for (i = 0; i < count; ++i)
! 1748: {
! 1749: char hbuf[16];
! 1750: unsigned short val;
! 1751:
! 1752: if((i & 7) > 0)
! 1753: strcat(operandBuffer, ",");
! 1754: val = Disass68kGetWord(addr+(i & ~1));
! 1755: if(i & 1)
! 1756: val &= 0xFF;
! 1757: else
! 1758: val = val >> 8;
! 1759: sprintf(hbuf,"$%2.2x", val);
! 1760: strcat(operandBuffer, hbuf);
! 1761: }
! 1762: return count;
! 1763:
! 1764: case dtWord:
! 1765: if(count > 4)
! 1766: count = 4;
! 1767: strcpy(opcodeBuffer,"DC.W");
! 1768: for (i = 0; i < count; ++i)
! 1769: {
! 1770: char hbuf[16];
! 1771: if((i & 3) > 0)
! 1772: strcat(operandBuffer, ",");
! 1773: sprintf(hbuf,"$%4.4x", Disass68kGetWord(addr+i*2));
! 1774: strcat(operandBuffer, hbuf);
! 1775: }
! 1776: return count * 2;
! 1777:
! 1778: case dtLong:
! 1779: if(count > 2)
! 1780: count = 2;
! 1781: strcpy(opcodeBuffer,"DC.L");
! 1782: for (i = 0; i < count; ++i)
! 1783: {
! 1784: char hbuf[16];
! 1785: if((i & 1) > 0)
! 1786: strcat(operandBuffer, ",");
! 1787: sprintf(hbuf,"$%8.8x", (Disass68kGetWord(addr+i*4) << 16) | Disass68kGetWord(addr+i*4+2));
! 1788: strcat(operandBuffer, hbuf);
! 1789: }
! 1790: return count * 4;
1.1 root 1791:
1792: case dtStringArray:
1.1.1.4 ! root 1793: {
! 1794: char *sp;
! 1795: strcpy(opcodeBuffer,"DC.B");
! 1796: strcat(operandBuffer, "'");
! 1797: sp = operandBuffer + strlen(operandBuffer);
! 1798: for (i = 0; i < count; ++i)
! 1799: {
! 1800: unsigned short val = Disass68kGetWord(addr+(i & ~1));
! 1801: if(i & 1)
! 1802: val &= 0xFF;
! 1803: else
! 1804: val = val >> 8;
! 1805: if(val == 0)
! 1806: break;
! 1807: switch(val)
! 1808: {
! 1809: case 9: *sp++ = '\\'; *sp++ = 't'; break;
! 1810: case 10: *sp++ = '\\'; *sp++ = 'n'; break;
! 1811: case 13: *sp++ = '\\'; *sp++ = 'r'; break;
! 1812: default:
! 1813: if(val >= 0x20 && val <= 0x7E)
! 1814: *sp++ = val;
! 1815: }
! 1816: }
! 1817: *sp = 0;
! 1818: strcat(sp, "'");
! 1819: return count;
! 1820: }
1.1 root 1821:
1822: case dtASCString:
1.1.1.4 ! root 1823: {
! 1824: int count = 1;
! 1825: unsigned short val = Disass68kGetWord(addr+0);
! 1826: strcpy(opcodeBuffer,"DC.B");
! 1827: if((val >> 8) == 0)
! 1828: {
! 1829: strcat(operandBuffer, "0");
! 1830: } else {
! 1831: char *sp;
! 1832: strcat(operandBuffer, "'");
! 1833: sp = operandBuffer + strlen(operandBuffer);
! 1834: for(i=0; ; ++i)
! 1835: {
! 1836: unsigned short val = Disass68kGetWord(addr+(i & ~1));
! 1837: if(i & 1)
! 1838: val &= 0xFF;
! 1839: else
! 1840: val = val >> 8;
! 1841: if(val == 0)
! 1842: break;
! 1843: switch(val)
1.1 root 1844: {
1.1.1.4 ! root 1845: case 9: *sp++ = '\\'; *sp++ = 't'; break;
! 1846: case 10: *sp++ = '\\'; *sp++ = 'n'; break;
! 1847: case 13: *sp++ = '\\'; *sp++ = 'r'; break;
! 1848: default:
! 1849: if(val >= 0x20 && val <= 0x7E)
! 1850: *sp++ = val;
1.1 root 1851: }
1.1.1.4 ! root 1852: ++count;
! 1853: }
! 1854: *sp = 0;
! 1855: strcat(sp, "',0");
! 1856: }
! 1857: return (count + 1) & ~1;
! 1858: }
1.1 root 1859:
1860: case dtPointer:
1861: case dtFunctionPointer:
1.1.1.4 ! root 1862: {
! 1863: const char *sp;
! 1864: val = (Disass68kGetWord(addr) << 16) | Disass68kGetWord(addr+2);
! 1865: sp = Disass68kSymbolName(val, 2);
! 1866: strcpy(opcodeBuffer,"DC.L");
! 1867: if(sp)
! 1868: sprintf(operandBuffer,"%s", sp);
! 1869: else
! 1870: sprintf(operandBuffer,"$%6.6x", val);
! 1871: return 4;
! 1872: }
1.1 root 1873:
1874: default: break;
1875: }
1876:
1.1.1.4 ! root 1877: index = 0;
! 1878: opcodeAddr = addr;
1.1 root 1879: more:
1880: addr = opcodeAddr;
1881:
1882: opcodeBuffer[0] = 0;
1883: operandBuffer[0] = 0;
1884:
1885: commentBuffer[0] = 0;
1886: if(cmtBuffer[0])
1887: sprintf(commentBuffer, "%s ", cmtBuffer);
1888:
1889: while(1)
1890: {
1.1.1.4 ! root 1891: unsigned short opcode[5];
! 1892: unsigned int i;
1.1 root 1893: OpcodeTableStruct *ots = &OpcodeTable[index++];
1.1.1.4 ! root 1894: int size;
! 1895: char sizeChar = 0;
! 1896: char *dbuf;
! 1897: int ea;
! 1898:
1.1 root 1899: if(ots->opcodeName == NULL)
1900: break;
1901: if((ots->cpuMask & optionCPUTypeMask) == 0) // CPU doesn't match?
1902: continue;
1903:
1904: // search for the opcode plus up to 2 extension words
1905: for(i=0; i<5; ++i)
1906: {
1907: if(!ots->opcodeMask[i*2])
1.1.1.4 ! root 1908: {
! 1909: opcode[i] = 0;
1.1 root 1910: break;
1.1.1.4 ! root 1911: }
1.1 root 1912: opcode[i] = Disass68kGetWord(addr);
1913: if(((ots->opcodeMask[i*2] & 0xFFFF) & opcode[i]) != ots->opcodeMask[i*2+1])
1914: goto more;
1915: addr += 2;
1916: }
1917:
1918: // find out the size of the opcode operand
1.1.1.4 ! root 1919: size = ots->operationSize[0];
1.1 root 1920: if(size < 0) // custom size?
1921: {
1922: int opcodeOffset = ots->operationSize[1] >> 4;
1923: int bitShiftOffset = ots->operationSize[1] & 0x0F;
1924: int sizeBitMask = (opcode[opcodeOffset] >> bitShiftOffset) & ((1 << ots->operationSize[2]) - 1);
1925: switch(ots->operationSize[3])
1926: {
1927: case 0: // 2 Bit Size
1928: switch(sizeBitMask)
1929: {
1930: case 0: size = 1; sizeChar = 'B'; break;
1931: case 1: size = 2; sizeChar = 'W'; break;
1932: case 2: size = 4; sizeChar = 'L'; break;
1933: case 3: goto more; // illegal size mask
1934: }
1935: break;
1936: case 1: // 3 Bit FPU Size
1937: if((opcode[1] & 0x4000) == 0x0000) // Register => Register?
1938: sizeBitMask = 2; // => 'X' Format
1939: switch(sizeBitMask)
1940: {
1941: case 0: size = 4; sizeChar = 'L'; break;
1942: case 1: size = 4; sizeChar = 'S'; break;
1943: case 2: size = 12; sizeChar = 'X'; break;
1944: case 7: if((opcode[1] & 0xE000) != 0x6000) // MOVE.P <ea>,FPn{Dn-Factor}
1945: goto more; // illegal size mask
1946: case 3: size = 12; sizeChar = 'P'; break;
1947: case 4: size = 2; sizeChar = 'W'; break;
1948: case 5: size = 8; sizeChar = 'D'; break;
1949: case 6: size = 1; sizeChar = 'B'; break;
1950: }
1951: break;
1952: }
1953: }
1954:
1955: // copy the opcode plus a necessary TAB for the operand
1.1.1.4 ! root 1956: dbuf = opcodeBuffer;
1.1 root 1957: for(i=0; ots->opcodeName[i]; ++i)
1958: {
1959: char c = ots->opcodeName[i];
1960: if(c == 'c') // condition code
1961: {
1962: static const char *pmmuCond[16] = { "BS", "BC", "LS", "LC", "SS", "SC", "AS", "AC", "WS", "WC", "IS", "IC", "GS", "GC", "CS", "CC" };
1963: static const char *braCond[16] = { "RA", "SR", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1964: static const char *sccCond[16] = { "T", "F", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1965: static const char *dbCond[16] = { "T", "RA", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1966: static const char *fpuCond[64] = { "F", "EQ", "OGT", "OGE", "OLT", "OLE", "OGL", "OR", "UN", "UEQ", "UGT", "UGE", "ULT", "ULE", "NE", "T", "SF", "SEQ", "GT", "GE", "LT", "LE", "GL", "GLE", "NGLE", "NGL", "NLE", "NLT", "NGE", "NGT", "SNE", "ST" };
1.1.1.4 ! root 1967: char buf[8];
1.1 root 1968:
1969: const char *sp = NULL;
1970: switch(ots->opcodeName[++i])
1971: {
1972: case 'p': // PMMU conditions
1973: sp = pmmuCond[opcode[1] & 0xF];
1974: break;
1975: case 'b': // BRA conditions
1976: sp = braCond[(opcode[0] >> 8) & 0xF];
1977: break;
1978: case 'i': // Scc,TRAPcc conditions
1979: sp = sccCond[(opcode[0] >> 8) & 0xF];
1980: break;
1981: case 'd': // DBcc conditions
1982: sp = dbCond[(opcode[0] >> 8) & 0xF];
1983: break;
1984: case 'F': // FPU conditions (first word)
1985: sp = fpuCond[opcode[0] & 0x3F];
1986: break;
1987: case 'f': // FPU conditions (second word)
1988: sp = fpuCond[opcode[1] & 0x3F];
1989: break;
1990: }
1991: if(sp)
1992: {
1993: if(options & doptOpcodesSmall)
1994: {
1.1.1.4 ! root 1995: char *bp;
1.1 root 1996: strcpy(buf, sp);
1997: sp = buf;
1.1.1.4 ! root 1998: for (bp = buf; *bp; ++bp)
1.1 root 1999: *bp = tolower(*bp);
2000: }
2001: strcpy(dbuf, sp);
2002: dbuf += strlen(sp);
2003: continue;
2004: }
2005: goto more;
2006: }
2007: if(c == '?') // size mask
2008: c = sizeChar;
2009: if(options & doptOpcodesSmall)
2010: c = tolower(c);
2011: *dbuf++ = c;
2012: }
2013: *dbuf = 0;
2014:
2015: // Parse the EAs for all operands
1.1.1.4 ! root 2016: ea = opcode[0] & 0x3F;
1.1 root 2017: dbuf = operandBuffer;
2018: for(i=0; i<(sizeof(ots->op)/sizeof(ots->op[0])); ++i)
2019: {
1.1.1.4 ! root 2020: int reg;
! 2021:
1.1 root 2022: switch(ots->op[i])
2023: {
2024: case ofNone: // nothing
2025: break;
2026:
2027: case ofEa:
2028: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, EA_All & ~(ots->parameter[i]), 0, ots->disassFlag);
2029: break;
2030:
2031: case ofDn:
2032: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2033: break;
2034: case ofAn:
2035: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x08, size, EA_An, 0, ots->disassFlag);
2036: break;
2037: case ofAni:
2038: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x10, size, EA_Ani, 0, ots->disassFlag);
2039: break;
2040: case ofAnip:
2041: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2042: break;
2043: case ofPiAn:
2044: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x20, size, EA_piAn, 0, ots->disassFlag);
2045: break;
2046: case ofD16An:
2047: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x28, size, EA_dAn, 0, ots->disassFlag);
2048: break;
2049:
2050: case ofI:
2051: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x3C, size, EA_Immed, 0, ots->disassFlag);
2052: break;
2053:
2054: case ofDestDn:
2055: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2056: break;
2057: case ofDestAn:
2058: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x08, size, EA_An, 0, ots->disassFlag);
2059: break;
2060: case ofDestAnip:
2061: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2062: break;
2063: case ofDestPiAn:
2064: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x20, size, EA_piAn, 0, ots->disassFlag);
2065: break;
2066: case ofDestEa6:
2067: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | (((opcode[0] >> 6) & 0x7) << 3), size, EA_Dest-EA_An, 0, ots->disassFlag);
2068: break;
2069: case ofDestAbsL:
2070: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x39, size, EA_Abs, 0, ots->disassFlag);
2071: break;
2072:
2073: case ofIOpcode:
2074: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, opcode[0] & ots->parameter[i], ots->disassFlag);
2075: break;
2076: case ofI3:
2077: val = ((opcode[0] >> 9) & 7);
2078: if(!val) val = 8;
2079: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, val, ots->disassFlag);
2080: break;
2081: case ofExtIm:
2082: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, opcode[1], ots->disassFlag);
2083: break;
2084: case ofExtIm32:
2085: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, size, EA_ImmedParameter, opcode[2], ots->disassFlag);
2086: break;
2087: case ofExtIm4:
2088: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, opcode[1] & 0x0F, ots->disassFlag);
2089: break;
2090: case ofExtIm10:
2091: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, (opcode[1] >> 10) & 0x07, ots->disassFlag);
2092: break;
2093: case ofSpecReg:
2094: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0101, size, EA_SpecialRegister, ots->parameter[i], ots->disassFlag);
2095: break;
2096: case ofSpecExtReg:
2097: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0101, size, EA_SpecialRegister, opcode[1] & 0xFFF, ots->disassFlag);
2098: break;
2099: case ofExtReg0:
2100: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2101: break;
2102: case ofExtRegA0:
2103: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07) | 0x08, size, EA_An, 0, ots->disassFlag);
2104: break;
2105: case ofExtRegD04:
2106: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 4) & 0x07) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2107: break;
2108: case ofExtRegA05:
2109: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 5) & 0x07) | 0x08, size, EA_An, 0, ots->disassFlag);
2110: break;
2111: case ofExtReg:
2112: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2113: break;
2114: case ofExtAnip:
2115: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2116: break;
2117:
2118: case ofDisp:
2119: // branch treats the displacement 0x00 and 0xFF as an indicator how many words follow
2120: // This test will decline a displacement with the wrong word offset
2121: if((opcode[0] & 0xF000) == 0x6000)
2122: {
2123: val = opcode[0] & 0xFF;
2124: if(val == 0x00 && size != 2) goto more;
2125: if(val == 0xFF && size != 4) goto more;
2126: }
2127: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0102, size, EA_PCDisplacement, opcode[0] & 0xFF, ots->disassFlag);
2128: break;
2129:
2130: case ofRegList:
2131: val = opcode[1];
2132: if((ea & 0x38) == 0x20) // -(An) has a flipped bitmask
2133: val = Disass68kFlipBits(val);
2134: dbuf = Disass68kReglist(dbuf, val);
2135: break;
2136:
2137: case ofFPU:
2138: { // default FPU opcode modes
2139: int src = (opcode[1] >> 10) & 7;
2140: int dest = (opcode[1] >> 7) & 7;
2141: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2142: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2143: if(opcode[1] & 0x4000)
2144: {
2145: // <ea>,FPn
2146: int mask = EA_All - EA_An;
2147: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2148: mask -= EA_Dn;
2149: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2150: if(!dbuf) goto more;
2151: *dbuf++ = ',';
2152: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2153: *dbuf = 0;
2154: } else {
2155: // FPn,FPn or FPn
2156:
2157: // <ea> has to be 0
2158: if((opcode[0] & 0x3F) != 0) goto more;
2159:
2160: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+src;
2161: if(src != dest)
2162: {
2163: *dbuf++ = ',';
2164: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2165: }
2166: *dbuf = 0;
2167: }
2168: }
2169: break;
2170: case ofFPUMOVE:
2171: { // MOVE <ea>,FPn{k-Factor}
2172: int src = (opcode[1] >> 10) & 7;
2173: // <ea>,FPn
2174: int mask = EA_All - EA_An;
2175: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2176: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2177: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2178: mask -= EA_Dn;
2179: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2180: if(!dbuf) goto more;
2181: *dbuf++ = ',';
2182: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+((opcode[1] >> 7) & 7);
2183: if(src == 3)
2184: {
2185: int kFactor = opcode[1] & 0x7F;
2186: if(kFactor & 0x40)
2187: kFactor |= 0x80;
2188: *dbuf++ = '{';
2189: sprintf(dbuf, "%d", (signed char)kFactor);
2190: dbuf += strlen(dbuf);
2191: *dbuf++ = '}';
2192: } else if(src == 7)
2193: {
2194: if((opcode[1] & 0x0F) != 0) goto more;
2195: *dbuf++ = '{';
2196: *dbuf++ = options & doptRegisterSmall ? 'd' : 'D';
2197: *dbuf++ = '0' + ((opcode[1] >> 4) & 7);
2198: *dbuf++ = '}';
2199: } else {
2200: if((opcode[1] & 0x7F) != 0) goto more;
2201: }
2202: *dbuf = 0;
2203: }
2204: break;
2205: case ofFMOVECR:
2206: { // MOVECR #const,FPn
2207: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2208: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2209: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, opcode[1] & 0x7F, ots->disassFlag);
2210: if(!dbuf) goto more;
1.1.1.4 ! root 2211: reg = (opcode[1] >> 7) & 7;
1.1 root 2212: *dbuf++ = ',';
2213: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+reg;
2214: *dbuf = 0;
2215: switch(opcode[1] & 0x7F) // document the well-known constants
2216: {
2217: case 0x00: strcat(commentBuffer, "PI"); break;
2218: case 0x0B: strcat(commentBuffer, "Log10(2)"); break;
2219: case 0x0C: strcat(commentBuffer, "e"); break;
2220: case 0x0D: strcat(commentBuffer, "Log2(e)"); break;
2221: case 0x0E: strcat(commentBuffer, "Log10(e)"); break;
2222: case 0x0F: strcat(commentBuffer, "0.0"); break;
2223: case 0x30: strcat(commentBuffer, "1n(2)"); break;
2224: case 0x31: strcat(commentBuffer, "1n(10)"); break;
2225: case 0x32: strcat(commentBuffer, "100"); break;
2226: case 0x33: strcat(commentBuffer, "10^1"); break;
2227: case 0x34: strcat(commentBuffer, "10^2"); break;
2228: case 0x35: strcat(commentBuffer, "10^4"); break;
2229: case 0x36: strcat(commentBuffer, "10^8"); break;
2230: case 0x37: strcat(commentBuffer, "10^16"); break;
2231: case 0x38: strcat(commentBuffer, "10^32"); break;
2232: case 0x39: strcat(commentBuffer, "10^64"); break;
2233: case 0x3A: strcat(commentBuffer, "10^128"); break;
2234: case 0x3B: strcat(commentBuffer, "10^256"); break;
2235: case 0x3C: strcat(commentBuffer, "10^512"); break;
2236: case 0x3D: strcat(commentBuffer, "10^1024"); break;
2237: case 0x3E: strcat(commentBuffer, "10^2048"); break;
2238: case 0x3F: strcat(commentBuffer, "10^4096"); break;
2239: }
2240: }
2241: break;
2242: case ofFPUSRRegList:
2243: {
2244: int hasReg = 0;
2245: *dbuf = 0;
2246: if(opcode[1] & 0x0400)
2247: {
2248: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPIAR));
2249: hasReg = 1;
2250: }
2251: if(opcode[1] & 0x0800)
2252: {
2253: if(hasReg) strcat(dbuf, "/");
2254: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPSR));
2255: hasReg = 1;
2256: }
2257: if(opcode[1] & 0x1000)
2258: {
2259: if(hasReg) strcat(dbuf, "/");
2260: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPCR));
2261: hasReg = 1;
2262: }
2263: if(!hasReg)
2264: strcat(dbuf, "0");
2265: dbuf += strlen(dbuf);
2266: }
2267: break;
2268: case ofFPUReglist: // FMOVEM
2269: {
2270: int mask = opcode[1] & 0xFF;
2271: if(opcode[1] & 0x0100)
2272: mask = Disass68kFlipBits(mask) >> 8;
2273: dbuf = Disass68kFPUReglist(dbuf, mask);
2274: }
2275: break;
2276: case ofFPU3Reg:
2277: { // FSINCOS
2278: int src = (opcode[1] >> 10) & 7;
2279: int dest = (opcode[1] >> 7) & 7;
2280: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2281: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2282: if(opcode[1] & 0x4000)
2283: {
2284: // <ea>,FPn
2285: int mask = EA_All - EA_An;
2286: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2287: mask -= EA_Dn;
2288: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2289: if(!dbuf) goto more;
2290: *dbuf++ = ',';
2291: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+(opcode[1] & 7);
2292: *dbuf++ = ',';
2293: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2294: *dbuf = 0;
2295: } else {
2296: // FPn,FPn or FPn
2297:
2298: // <ea> has to be 0
2299: if((opcode[0] & 0x3F) != 0) goto more;
2300:
2301: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+src;
2302: *dbuf++ = ',';
2303: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+(opcode[1] & 7);
2304: *dbuf++ = ',';
2305: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2306: *dbuf = 0;
2307: }
2308: }
2309: break;
2310:
2311: case ofCAS:
2312: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2313: if(!dbuf) goto more;
2314: *dbuf++ = ',';
2315: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2316: break;
2317: case ofCAS2:
2318: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2319: if(!dbuf) goto more;
2320: *dbuf++ = ':';
2321: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[2] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2322: if(!dbuf) goto more;
2323: *dbuf++ = ',';
2324: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2325: if(!dbuf) goto more;
2326: *dbuf++ = ':';
2327: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[2] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2328: if(!dbuf) goto more;
2329: *dbuf++ = ',';
2330: *dbuf++ = '(';
2331: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2332: if(!dbuf) goto more;
2333: *dbuf++ = ')';
2334: *dbuf++ = ':';
2335: *dbuf++ = '(';
2336: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[2] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2337: if(!dbuf) goto more;
2338: *dbuf++ = ')';
2339: *dbuf = 0;
2340: break;
2341: case ofExt4Dn:
2342: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[0] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2343: if(!dbuf) goto more;
2344: *dbuf++ = ':';
2345: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2346: if(!dbuf) goto more;
2347: *dbuf++ = ',';
2348: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2349: if(!dbuf) goto more;
2350: *dbuf = 0;
2351: break;
2352: case ofBFEa:
2353: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, EA_All & ~(ots->parameter[i]), 0, ots->disassFlag);
2354: if(!dbuf) goto more;
2355: *dbuf++ = '{';
2356: val = (opcode[1] >> 6) & 0x1F;
2357: if(opcode[1] & 0x0800)
2358: {
2359: if(val & 0x18) goto more;
2360: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, val & 0x07, 1, EA_Dn, val, ots->disassFlag);
2361: } else {
2362: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0103, 1, EA_ValueParameter, val, ots->disassFlag);
2363: }
2364: *dbuf++ = ':';
2365: val = opcode[1] & 0x1F;
2366: if(opcode[1] & 0x0020)
2367: {
2368: if(val & 0x18) goto more;
2369: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, val & 0x07, 1, EA_Dn, val, ots->disassFlag);
2370: } else {
2371: if(val == 0) val = 32;
2372: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0103, 1, EA_ValueParameter, val, ots->disassFlag);
2373: }
2374: *dbuf++ = '}';
2375: *dbuf = 0;
2376: break;
2377: case ofLineA:
2378: {
2379: int lineAVal = opcode[0] & 0xFFF;
2380: const char *lineAStr[16] = { "Line-A Initialization",
2381: "Put pixel",
2382: "Get pixel",
2383: "Arbitrary line",
2384: "Horizontal line",
2385: "Filled rectangle",
2386: "Filled polygon",
2387: "Bit block transfer",
2388: "Text block transfer",
2389: "Show mouse",
2390: "Hide mouse",
2391: "Transform mouse",
2392: "Undraw sprite",
2393: "Draw sprite",
2394: "Copy raster form",
2395: "Seedfill"
2396: };
1.1.1.4 ! root 2397: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, lineAVal, ots->disassFlag);
1.1 root 2398: if(lineAVal < 16)
2399: strcat(commentBuffer, lineAStr[lineAVal]);
2400: }
2401: break;
2402:
2403: default:
2404: goto more;
2405: }
2406: if(!dbuf) goto more;
2407:
2408: // does another operand follow => add separator
2409: if(ots->op[i+1] != ofNone)
2410: *dbuf++ = ',';
2411: }
2412: return addr-baseAddr;
2413: }
2414:
2415: // unknown opcode
2416: strcpy(opcodeBuffer, "DC.W");
2417: sprintf(operandBuffer,"$%4.4x", Disass68kGetWord(addr));
2418: return 2;
2419: }
2420:
2421: static void Disass68kComposeStr(char *dbuf, const char *str, int position, int maxPos)
2422: {
2423: int i;
2424: int len = strlen(dbuf);
2425: while(len < position) {
2426: dbuf[len++] = ' '; /* Will give harmless warning from GCC */
2427: }
2428: for(i=0; str[i] && (!maxPos || len+i<maxPos); ++i)
2429: dbuf[len+i] = str[i];
2430: if(str[i])
2431: dbuf[len+i-1] = '+';
2432: dbuf[len+i] = 0;
2433: }
2434:
2435: static void Disass68k_loop (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
2436: {
2437: static bool isInit = false;
2438: if(!isInit)
2439: {
2440: Disass68kInit(Paths_GetHatariHome());
2441: isInit = true;
2442: }
2443:
1.1.1.4 ! root 2444: while (cnt-- > 0) {
! 2445: const int addrWidth = 6; // 6 on an ST, 8 on a TT
1.1 root 2446: char lineBuffer[1024];
2447:
2448: char addressBuffer[32];
2449: char hexdumpBuffer[256];
2450: char labelBuffer[256];
2451: char opcodeBuffer[64];
2452: char operandBuffer[256];
2453: char commentBuffer[256];
1.1.1.4 ! root 2454: int plen, len, j;
! 2455:
! 2456: len = Disass68k(addr, labelBuffer, opcodeBuffer, operandBuffer, commentBuffer);
1.1 root 2457: if(!len) break;
2458:
2459: sprintf(addressBuffer, "$%*.*x :", addrWidth,addrWidth, addr);
2460:
2461: hexdumpBuffer[0] = 0;
1.1.1.4 ! root 2462: plen = len;
1.1 root 2463: if(plen > 80 && (!strncmp(opcodeBuffer, "DC.", 3) || !strncmp(opcodeBuffer, "dc.", 3)))
2464: plen = ((optionPosLabel - optionPosHexdump) / 5) * 2;
1.1.1.4 ! root 2465:
1.1 root 2466: for(j=0; j<plen; j += 2)
2467: {
2468: if(j > 0)
2469: strcat(hexdumpBuffer, " ");
2470: if(j + 2 > plen)
2471: {
2472: sprintf(hexdumpBuffer+strlen(hexdumpBuffer), "%2.2x", Disass68kGetWord(addr+j) >> 8);
2473: } else {
2474: sprintf(hexdumpBuffer+strlen(hexdumpBuffer), "%4.4x", Disass68kGetWord(addr+j));
2475: }
2476: }
2477:
2478: lineBuffer[0] = 0;
2479: if(optionPosAddress >= 0)
2480: Disass68kComposeStr(lineBuffer, addressBuffer, optionPosAddress, 0);
2481: if(optionPosHexdump >= 0)
2482: Disass68kComposeStr(lineBuffer, hexdumpBuffer, optionPosHexdump, optionPosLabel);
2483: if(optionPosLabel >= 0)
2484: Disass68kComposeStr(lineBuffer, labelBuffer, optionPosLabel, 0);
2485: if(optionPosOpcode >= 0)
2486: Disass68kComposeStr(lineBuffer, opcodeBuffer, optionPosOpcode, 0);
2487: if(optionPosOperand >= 0)
2488: {
2489: size_t l = strlen(lineBuffer);
2490: if(lineBuffer[l-1] != ' ') // force at least one space between opcode and operand
2491: {
2492: lineBuffer[l++] = ' ';
2493: lineBuffer[l] = 0;
2494: }
2495: Disass68kComposeStr(lineBuffer, operandBuffer, optionPosOperand, 0);
2496: }
1.1.1.4 ! root 2497: if (optionPosComment >= 0)
1.1.1.3 root 2498: {
1.1.1.4 ! root 2499: float percentage;
! 2500: Uint32 count, cycles, misses;
! 2501: if (Profile_CpuAddressData(addr, &percentage, &count, &cycles, &misses))
1.1.1.3 root 2502: {
1.1.1.4 ! root 2503: sprintf(commentBuffer, "%5.2f%% (%u, %u, %u)", percentage, count, cycles, misses);
1.1.1.3 root 2504: Disass68kComposeStr(lineBuffer, commentBuffer, optionPosComment+1, 0);
2505: }
1.1.1.4 ! root 2506: /* show comments only if profile data is missing */
! 2507: else if (commentBuffer[0])
! 2508: {
! 2509: Disass68kComposeStr(lineBuffer, " ;", optionPosComment, 0);
! 2510: Disass68kComposeStr(lineBuffer, commentBuffer, optionPosComment+3, 0);
! 2511: }
1.1.1.3 root 2512: }
1.1.1.4 ! root 2513: addr += len;
! 2514: if (f)
! 2515: fprintf(f, "%s\n", lineBuffer);
1.1 root 2516: // if(strstr(opcodeBuffer, "RTS") || strstr(opcodeBuffer, "RTE") || strstr(opcodeBuffer, "JMP")
2517: // || strstr(opcodeBuffer, "rts") || strstr(opcodeBuffer, "rte") || strstr(opcodeBuffer, "jmp"))
2518: // fprintf(f, "\n");
2519: }
2520: if (nextpc)
2521: *nextpc = addr;
2522: }
2523:
2524:
1.1.1.4 ! root 2525: /**
! 2526: * Calculate next PC address from given one, without output
! 2527: * @return next PC address
1.1 root 2528: */
1.1.1.4 ! root 2529: Uint32 Disasm_GetNextPC(Uint32 pc)
! 2530: {
! 2531: uaecptr nextpc;
! 2532: Disass68k_loop (NULL, pc, &nextpc, 1);
! 2533: return nextpc;
! 2534: }
1.1 root 2535:
1.1.1.4 ! root 2536: /**
! 2537: * Call disassembly using the selected disassembly method,
! 2538: * either internal UAE one, or the stand alone disassembler above,
! 2539: * whichever is selected in Hatari configuration
! 2540: */
! 2541: void Disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1.1 root 2542: {
1.1.1.4 ! root 2543: if (ConfigureParams.Debugger.bDisasmUAE)
! 2544: return m68k_disasm (f, addr, nextpc, cnt);
! 2545: else
! 2546: return Disass68k_loop (f, addr, nextpc, cnt);
1.1 root 2547: }
2548:
1.1.1.4 ! root 2549: static void Disasm_CheckOptionEngine(void)
! 2550: {
! 2551: if (ConfigureParams.Debugger.bDisasmUAE)
! 2552: fputs("WARNING: disassembly options are supported only for '--disasm ext'!\n", stderr);
! 2553: }
! 2554:
! 2555: /**
! 2556: * query disassembly output column positions.
! 2557: */
! 2558: void Disasm_GetColumns(int *pos)
! 2559: {
! 2560: pos[DISASM_COLUMN_ADDRESS] = optionPosAddress;
! 2561: pos[DISASM_COLUMN_HEXDUMP] = optionPosHexdump;
! 2562: pos[DISASM_COLUMN_LABEL] = optionPosLabel;
! 2563: pos[DISASM_COLUMN_OPCODE] = optionPosOpcode;
! 2564: pos[DISASM_COLUMN_OPERAND] = optionPosOperand;
! 2565: pos[DISASM_COLUMN_COMMENT] = optionPosComment;
! 2566: }
! 2567:
! 2568: /**
! 2569: * set disassembly output column positions.
! 2570: */
! 2571: void Disasm_SetColumns(int *pos)
! 2572: {
! 2573: Disasm_CheckOptionEngine();
! 2574: optionPosAddress = pos[DISASM_COLUMN_ADDRESS];
! 2575: optionPosHexdump = pos[DISASM_COLUMN_HEXDUMP];
! 2576: optionPosLabel = pos[DISASM_COLUMN_LABEL];
! 2577: optionPosOpcode = pos[DISASM_COLUMN_OPCODE];
! 2578: optionPosOperand = pos[DISASM_COLUMN_OPERAND];
! 2579: optionPosComment = pos[DISASM_COLUMN_COMMENT];
! 2580: }
! 2581:
! 2582: /**
! 2583: * function to disable given disassembly output 'column'.
! 2584: * input is current column positions in 'oldcols' array and
! 2585: * output is new column positions/values in 'newcols' array.
! 2586: * It's safe to use same array for both.
! 2587: */
! 2588: void Disasm_DisableColumn(int column, int *oldcols, int *newcols)
! 2589: {
! 2590: int i, diff = 0;
! 2591:
! 2592: assert(column >= 0 && column < DISASM_COLUMNS);
! 2593: if (column+1 < DISASM_COLUMNS)
! 2594: diff = oldcols[column+1] - oldcols[column];
! 2595:
! 2596: for (i = 0; i < DISASM_COLUMNS; i++)
! 2597: {
! 2598: if (i && oldcols[i-1] > oldcols[i])
! 2599: {
! 2600: printf("WARNING: disassembly columns aren't in the expected order!\n");
! 2601: return;
! 2602: }
! 2603: if (i < column)
! 2604: newcols[i] = oldcols[i];
! 2605: else if (i > column)
! 2606: newcols[i] = oldcols[i] - diff;
! 2607: else
! 2608: newcols[column] = DISASM_COLUMN_DISABLE;
! 2609: }
! 2610: }
! 2611:
! 2612: /**
! 2613: * Get current disassembly output option flags
! 2614: * @return current output flags
! 2615: */
! 2616: int Disasm_GetOptions(void)
! 2617: {
! 2618: return options;
! 2619: }
! 2620:
! 2621: /**
! 2622: * Parse disasm command line option argument
! 2623: * @return error string (""=silent 'error') or NULL for success.
! 2624: */
! 2625: const char *Disasm_ParseOption(const char *arg)
! 2626: {
! 2627: if (strcasecmp(arg, "help") == 0)
! 2628: {
! 2629: const struct {
! 2630: int flag;
! 2631: const char *desc;
! 2632: } option[] = {
! 2633: { doptNoBrackets, "no brackets around absolute addressing" },
! 2634: { doptOpcodesSmall, "opcodes in small letters" },
! 2635: { doptRegisterSmall, "register names in small letters" },
! 2636: { doptStackSP, "stack pointer as 'SP', not 'A7'" },
! 2637: { 0, NULL }
! 2638: };
! 2639: int i;
! 2640: fputs("Disassembly settings:\n"
! 2641: "\tuae - use CPU core internal disassembler which has better\n"
! 2642: "\t instruction support\n"
! 2643: "\text - use external disassembler which has nicer output\n"
! 2644: "\t and supports options below\n"
! 2645: "\t<bitmask> - disassembly output option flags\n"
! 2646: "Flag values:\n", stderr);
! 2647: for (i = 0; option[i].desc; i++) {
! 2648: assert(option[i].flag == (1 << i));
! 2649: fprintf(stderr, "\t%d: %s\n", option[i].flag, option[i].desc);
! 2650: }
! 2651: fprintf(stderr, "Current settings are:\n\t--disasm %s --disasm %d\n",
! 2652: ConfigureParams.Debugger.bDisasmUAE ? "uae" : "ext",
! 2653: ConfigureParams.Debugger.nDisasmOptions);
! 2654: return "";
! 2655: }
! 2656: if (strcasecmp(arg, "uae") == 0)
! 2657: {
! 2658: fputs("Selected UAE CPU core internal disassembler.\n", stderr);
! 2659: ConfigureParams.Debugger.bDisasmUAE = true;
! 2660: return NULL;
! 2661: }
! 2662: if (strcasecmp(arg, "ext") == 0)
! 2663: {
! 2664: fputs("Selected external disassembler.\n", stderr);
! 2665: fprintf(stderr, "Disassembly output flags are %d.\n", options);
! 2666: ConfigureParams.Debugger.bDisasmUAE = false;
! 2667: return NULL;
! 2668: }
! 2669: if (isdigit(*arg))
! 2670: {
! 2671: int newopt = atoi(arg);
! 2672: if ((newopt|optionsMask) != optionsMask)
! 2673: {
! 2674: return "unknown flags in the bitmask";
! 2675: }
! 2676: fprintf(stderr, "Changed CPU disassembly output flags from %d to %d.\n", options, newopt);
! 2677: ConfigureParams.Debugger.nDisasmOptions = options = newopt;
! 2678: Disasm_CheckOptionEngine();
! 2679: return NULL;
! 2680: }
! 2681: return "invalid disasm option";
! 2682: }
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