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1.1 root 1: /***
2: * 68k disassembler, written 2010 by Markus Fritze, www.sarnau.com
3: *
1.1.1.4 root 4: * This file is distributed under the GNU General Public License, version 2
5: * or at your option any later version. Read the file gpl.txt for details.
1.1 root 6: ***/
7:
8: #include <stdio.h>
9: #include <ctype.h>
10: #include <strings.h>
11: #include <stdlib.h>
12:
13: #include "config.h"
14: #include "sysdeps.h"
15: #include "main.h"
1.1.1.4 root 16: #include "configuration.h"
1.1 root 17: #include "newcpu.h"
18: #include "paths.h"
1.1.1.3 root 19: #include "profile.h"
1.1 root 20: #include "tos.h"
21: #include "68kDisass.h"
22:
23: #define ADDRESS_ON_PC 1
24: #define USE_SYMBOLS 1
25:
26: typedef enum {
27: doptNoBrackets = 1, // hide brackets around absolute addressing
28: doptOpcodesSmall = 2, // opcodes are small letters
29: doptRegisterSmall = 4, // register names are small letters
1.1.1.5 ! root 30: doptStackSP = 8 // stack pointer is named "SP" instead of "A7" (except for MOVEM)
1.1 root 31: } Diss68kOptions;
32:
33: static Diss68kOptions options = doptOpcodesSmall | doptRegisterSmall | doptStackSP | doptNoBrackets;
34:
1.1.1.4 root 35: /* all options */
36: static const Diss68kOptions optionsMask = doptOpcodesSmall | doptRegisterSmall | doptStackSP | doptNoBrackets;
37:
1.1 root 38: // values <0 will hide the group
1.1.1.4 root 39: static int optionPosAddress = 0; // current address
40: static int optionPosHexdump = 10; // 16-bit words at this address
41: static int optionPosLabel = 35; // label, if defined
42: static int optionPosOpcode = 47; // opcode
43: static int optionPosOperand = 57; // operands for the opcode
44: static int optionPosComment = 82; // comment, if defined
1.1 root 45:
46: /***
47: * Motorola 16-/32-Bit Microprocessor and coprocessor types
48: ***/
49: #define MC68000 0x000001 // 16-/32-Bit Microprocessor
50: #define MC68EC000 0x000002 // 16-/32-Bit Embedded Controller
51: #define MC68HC000 0x000004 // Low Power 16-/32-Bit Microprocessor
52: #define MC68008 0x000008 // 16-Bit Microprocessor with 8-Bit Data Bus
53: #define MC68010 0x000010 // 16-/32-Bit Virtual Memory Microprocessor
54: #define MC68020 0x000020 // 32-Bit Virtual Memory Microprocessor
55: #define MC68EC020 0x000040 // 32-Bit Embedded Controller (no PMMU)
56: #define MC68030 0x000080 // Second-Generation 32-Bit Enhanced Microprocessor
57: #define MC68EC030 0x000100 // 32-Bit Embedded Controller (no PMMU)
58: #define MC68040 0x000200 // Third-Generation 32-Bit Microprocessor
59: #define MC68LC040 0x000400 // Third-Generation 32-Bit Microprocessor (no FPU)
60: #define MC68EC040 0x000800 // 32-Bit Embedded Controller (no FPU, no PMMU)
61: #define MC68330 0x001000 // CPU32 Integrated CPU32 Processor
62: #define MC68340 0x002000 // CPU32 Integrated Processor with DMA
63: #define MC68060 0x004000 // Fourth-Generation 32-Bit Microprocessor
64: #define MC68LC060 0x008000 // Fourth-Generation 32-Bit Microprocessor (no FPU)
65: #define MC68EC060 0x010000 // Fourth-Generation 32-Bit Microprocessor (no FPU, no PMMU)
66: #define MC_CPU32 (MC68330|MC68340)
67:
68: #define MC_020 (MC68020|MC68EC020|MC68030|MC68EC030|MC68040|MC68LC040|MC68EC040|MC_CPU32|MC68060|MC68LC060|MC68EC060)
69: #define MC_ALL (MC68000|MC68EC000|MC68HC000|MC68008|MC68010|MC_020)
70:
71: #define MC68851 0x020000 // Paged Memory Management Unit
72:
73: #define MC68881 0x040000 // Floating-PointCoprocessor
74: #define MC68882 0x080000 // Enhanced Floating-Point Coprocessor
75:
76: #define MC_PMMU (MC68881|MC68882)
77: #define MC_FPU (MC68881|MC68882)
78:
79: static int optionCPUTypeMask = ( MC_ALL & ~MC68040 & ~MC_CPU32 & ~MC68060 ) | MC_PMMU | MC_FPU;
80:
81:
82: typedef enum {
83: dtNone,
84: dtByte, // a specific number of bytes, usually 1
85: dtWord, // one 16-bit value
86: dtLong, // one 32-bit value
87: dtOpcode, // an opcode of variable length
88: dtASCString, // a 0-byte terminated ASCII string
89: dtPointer, // a generic 32-bit pointer
90: dtFunctionPointer, // a 32-bit pointer to a function
1.1.1.5 ! root 91: dtStringArray // a specific number of ASCII bytes
1.1 root 92: } Disass68kDataType;
93:
94: typedef struct {
95: char *name;
96: char *comment;
97: Disass68kDataType type;
98: int size;
99: } disStructElement;
100:
101: typedef struct {
102: char *name; // name of the structure
103: int size; // size of structure
104: int count; // number of lines
105: disStructElement *elements; // array of all elements of the struct
106: } disStructEntry;
107:
108: static int disStructCounts;
109: static disStructEntry *disStructEntries;
110:
111: typedef struct {
112: long addr; // address of the label
113: Disass68kDataType type; // type of the data on the address
114: int size; // size of the label, references inside it are addressed via base address + offset
115: int count; // number of elements at this address with the given size
116: int structIndex; // -1 no struct to describe the element
117: char *name; // name of the label
118: char *comment; // optional comment
119: } disSymbolEntry;
120:
121: static int disSymbolCounts;
122: static disSymbolEntry *disSymbolEntries;
123:
124:
125: static inline unsigned short Disass68kGetWord(long addr)
126: {
127: return get_word(addr);
128: }
129:
130: // Load a text file into memory, count the lines and replace the LF with 0-bytes.
131: static int Disass68kLoadTextFile(const char *filename, char **filebuf)
132: {
133: long index;
1.1.1.4 root 134: long fileLength;
135: int lineCount;
136: char *fbuf;
137: FILE *f;
138:
1.1 root 139: if(filebuf)
140: *filebuf = NULL;
1.1.1.4 root 141: f = fopen(filename, "r");
1.1 root 142: if(!f) return 0;
143: if(fseek(f, 0, SEEK_END))
144: return 0;
1.1.1.4 root 145: fileLength = ftell(f);
146: if(fileLength <= 0) return 0;
1.1 root 147: if(fseek(f, 0, SEEK_SET))
148: return 0;
1.1.1.4 root 149: fbuf = malloc(fileLength);
1.1 root 150: if(!fbuf) return 0;
151: if((size_t)fileLength != fread(fbuf, sizeof(char), fileLength, f))
1.1.1.4 root 152: {
153: free(fbuf);
1.1 root 154: return 0;
1.1.1.4 root 155: }
156: lineCount = 0;
1.1 root 157: for(index=0; index<fileLength; ++index)
158: {
159: if(fbuf[index] == '\r') // convert potential CR into a space (which we ignore at the end of the line anyway)
160: fbuf[index] = ' ';
161: if(fbuf[index] == '\n') // count LF and terminate line
162: {
163: ++lineCount;
164: fbuf[index] = 0;
165: }
166: }
167: if(filebuf)
168: *filebuf = fbuf;
169: return lineCount;
170: }
171:
172: static void Disass68kLoadStructInfo(const char *filename)
173: {
1.1.1.4 root 174: int i,j;
175: char *nextLine;
176: char *line;
1.1 root 177: char *fbuf = NULL;
1.1.1.4 root 178: int lineCount = Disass68kLoadTextFile(filename, &fbuf);
1.1 root 179: disStructEntry *se = NULL;
1.1.1.4 root 180:
181: if(!lineCount) return;
182:
183: disStructEntries = realloc(disStructEntries, sizeof(disStructEntry)
184: * (disStructCounts + lineCount));
1.1 root 185: if(!disStructEntries) { free(fbuf); return; }
1.1.1.4 root 186:
187: line = fbuf;
1.1 root 188:
189: for(i=0; i<lineCount; line = nextLine, ++i)
190: {
191: // strip spaces at the end of the line, remember the ptr to the next line
192: char *sp = line;
193: while(*sp++)
194: ;
195: nextLine = sp--;
1.1.1.5 ! root 196: while (isspace((unsigned char)*--sp))
1.1 root 197: *sp = 0;
198:
199: if(line[0] == '{')
200: {
201: se = &disStructEntries[disStructCounts];
202: se->name = strdup(line+1);
203: se->count = 0;
204: se->elements = malloc(sizeof(disStructElement) * lineCount); // lineCount is way too much, but safe
205: } else if(line[0] == '}') {
206: if(se)
207: {
208: se->size = 0;
209: for(j=0; j<se->count; ++j)
210: se->size += se->elements[j].size;
211: // printf("%s : %d bytes\n", se->name, se->size);
212: ++disStructCounts;
213: se = NULL;
214: }
215: } else if(line[0] == '#') {
216: disStructElement dse;
217: int val = 0;
218: int index = 2;
219: if(line[1] == 'A' || line[1] == 'B')
220: {
1.1.1.5 ! root 221: for(; isdigit((unsigned char)line[index]); ++index)
1.1 root 222: {
223: val *= 10;
224: val += line[index] - '0';
225: }
226: }
227: if(val == 0) val = 1;
228: dse.name = NULL;
229: switch(line[1])
230: {
231: case 'A': dse.type = dtStringArray; dse.size = val; dse.name = strdup(line + index + 1); break;
232: case 'B': dse.type = dtByte; dse.size = val; break;
233: case 'W': dse.type = dtWord; dse.size = 2; break;
234: case 'L': dse.type = dtLong; dse.size = 4; break;
235: case 'C': dse.type = dtOpcode; dse.size = 2; break;
236: case 'f': dse.type = dtFunctionPointer; dse.size = 4; break;
237: case 'p': dse.type = dtPointer; dse.size = 4; break;
238: default: dse.type = dtNone; dse.size = 0;
239: printf("Unknown type in \"%s\"\n", line); break;
240: }
241: if(!dse.name)
242: dse.name = strdup(line+3);
243: dse.comment = NULL;
244: if(se)
245: se->elements[se->count++] = dse;
246: }
247: }
248: free(fbuf);
249: }
250:
251: static void Disass68kLoadSymbols(const char *filename)
252: {
1.1.1.4 root 253: int i,j;
254: char *nextLine;
255: char *line;
1.1 root 256: char *fbuf = NULL;
257: int lineCount = Disass68kLoadTextFile(filename, &fbuf);
1.1.1.4 root 258: if(!lineCount) return;
1.1 root 259: disSymbolEntries = realloc(disSymbolEntries, sizeof(disSymbolEntry) * (disSymbolCounts + lineCount));
260: if(!disSymbolEntries) { free(fbuf); return; }
1.1.1.4 root 261: line = fbuf;
1.1 root 262:
263: for(i=0; i<lineCount; line = nextLine, ++i)
264: {
1.1.1.4 root 265: long addr;
1.1 root 266: char *sp = line;
1.1.1.4 root 267: char *parameterPtr[10];
268: int parameterCount = 0;
269: char *str;
270: long size = 0;
271: int type = 0;
272:
273: // strip spaces at the end of the line, remember the ptr to the next line
1.1 root 274: while(*sp++)
275: ;
276: nextLine = sp--;
1.1.1.5 ! root 277: while(isspace((unsigned char)*--sp))
1.1 root 278: *sp = 0;
279:
280: // ignore empty lines
281: if(line[0] == 0)
282: continue;
283:
284: sscanf(line, "%lx",&addr);
285: disSymbolEntries[disSymbolCounts].addr = addr;
286: disSymbolEntries[disSymbolCounts].structIndex = -1;
287:
1.1.1.4 root 288: str = line;
1.1 root 289: do {
290: str = strchr(str, ',');
291: if(str)
292: {
293: char *ep = str;
1.1.1.5 ! root 294: while(isspace((unsigned char)*--ep))
1.1 root 295: *ep = 0;
296: *str++ = 0;
1.1.1.5 ! root 297: while(*str && isspace((unsigned char)*str))
1.1 root 298: ++str;
299: parameterPtr[parameterCount++] = str;
300: }
301: } while(str != NULL && parameterCount < 10);
302:
303: if(parameterCount != 3 && parameterCount != 4)
304: continue; // ignore line
305:
306: if(strlen(parameterPtr[0]) == 1)
307: {
308: switch(parameterPtr[0][0])
309: {
310: case 'A': type = dtASCString; size = 1; break; // ascii NULL
311: case 'B': type = dtByte; size = 1; break; // byte
312: case 'W': type = dtWord; size = 2; break; // word
313: case 'L': type = dtLong; size = 4; break; // long
314: case 'C': type = dtOpcode; size = 2; break; // code
315: case 'f': type = dtFunctionPointer; size = 4; break; // function pointer
316: case 'p': type = dtPointer; size = 4; break; // regular pointer
317: default: printf("ERROR: $%lx : %s\n", addr, parameterPtr[0]); continue;
318: }
319: } else {
320: for(j=0; j<disStructCounts; ++j)
321: {
322: disStructEntry *se = &disStructEntries[j];
323: if(se->name == NULL)
324: break;
325: if(strcmp(parameterPtr[0], se->name))
326: continue;
327: size = se->size;
328: disSymbolEntries[disSymbolCounts].structIndex = j;
329: }
330: }
331: if(!size)
332: continue;
333:
334: disSymbolEntries[disSymbolCounts].type = type;
335: disSymbolEntries[disSymbolCounts].size = size;
336: disSymbolEntries[disSymbolCounts].count = atol(parameterPtr[1]);
337: disSymbolEntries[disSymbolCounts].name = strdup(parameterPtr[2]);
338: disSymbolEntries[disSymbolCounts].comment = NULL;
339: if(parameterCount == 4)
340: disSymbolEntries[disSymbolCounts].comment = strdup(parameterPtr[3]);
341: ++disSymbolCounts;
342: }
343: free(fbuf);
344: }
345:
346: static void Disass68kInit(const char *baseDirectory)
347: {
1.1.1.2 root 348: char filename[FILENAME_MAX];
1.1 root 349:
350: disStructCounts = 0;
351: sprintf(filename, "%s/DisassStructs.txt", baseDirectory);
352: Disass68kLoadStructInfo(filename);
353: sprintf(filename, "%s/DisassStructs_%4.4X.txt", baseDirectory, TosVersion);
354: Disass68kLoadStructInfo(filename);
355:
356: disSymbolCounts = 0;
357: sprintf(filename, "%s/DisassSymbols.txt", baseDirectory);
358: Disass68kLoadSymbols(filename);
359: sprintf(filename, "%s/DisassSymbols_%4.4X.txt", baseDirectory, TosVersion);
360: Disass68kLoadSymbols(filename);
361: }
362:
363:
364:
365: static Disass68kDataType Disass68kType(long addr, char *addressLabel, char *commentBuffer, int *count)
366: {
367: int i,j;
368:
369: addressLabel[0] = 0;
370: commentBuffer[0] = 0;
371: for(i=0; i<disSymbolCounts; ++i)
372: {
1.1.1.4 root 373: const disStructEntry *se;
1.1 root 374: const disSymbolEntry *dse = &disSymbolEntries[i];
375: int offset = addr - dse->addr;
1.1.1.4 root 376:
1.1 root 377: if(offset < 0 || offset >= dse->count * dse->size)
378: continue;
379:
380: // no special struct that devices this value?
381: if(dse->structIndex < 0)
382: {
383: offset = (offset + dse->size - 1) / dse->size;
384: *count = dse->count - offset;
385: if(offset == 0) // only in the first line
386: {
387: strcpy(addressLabel, dse->name);
388: if(dse->comment)
389: strcpy(commentBuffer, dse->comment);
390: }
391: return dse->type;
392: }
393:
394: *count = 1;
1.1.1.4 root 395: se = &disStructEntries[dse->structIndex];
1.1 root 396: for(j=0; j<se->count; ++j)
397: {
398: const disStructElement *e = &se->elements[j];
399: if(offset < e->size)
400: {
401: if(e->type == dtStringArray)
402: *count = e->size;
403: if(j == 0)
404: strcpy(addressLabel, dse->name);
405:
406: sprintf(commentBuffer, "[%s]", e->name);
407: if(e->comment)
408: strcat(commentBuffer, e->comment);
409: return e->type;
410: }
411: offset -= e->size;
412: }
413: return dse->size;
414: }
415: return dtNone;
416: }
417:
418: /***
419: * Lookup a symbol name
420: ***/
421: static const char *Disass68kSymbolName(long addr, int size)
422: {
423: int i;
424:
425: for(i=0; i<disSymbolCounts; ++i)
426: {
1.1.1.4 root 427: static char symbolName[128];
1.1 root 428: const disSymbolEntry *dse = &disSymbolEntries[i];
1.1.1.4 root 429: int offset = addr - dse->addr;
430: int reminder;
431:
1.1 root 432: if(offset < 0 || offset >= dse->count * dse->size)
433: continue;
434:
435: if(dse->name[0] == 0)
436: return NULL;
437:
1.1.1.4 root 438: reminder = offset % dse->size;
1.1 root 439: offset /= dse->size;
440:
441: strcpy(symbolName, dse->name);
442: if(offset)
443: sprintf(symbolName+strlen(symbolName), "+%d*%d", dse->size, offset);
444: if(reminder)
445: sprintf(symbolName+strlen(symbolName), "+%d", reminder);
446: return symbolName;
447: }
448: return NULL;
449: }
450:
451: /***
452: * return a string pointer to display a register name
453: ***/
454: static const char *Disass68kRegname(int reg)
455: {
456: static char regName[3];
457: switch(reg)
458: {
459: case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
460: sprintf(regName, "%c%d", (options & doptRegisterSmall ? 'd' : 'D'), reg);
461: break;
462:
463: case 0x0F:
464: if(options & doptStackSP) // display A7 as SP
465: {
466: if(options & doptRegisterSmall)
467: return "sp";
468: return "SP";
469: }
470: case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: case 0x0D: case 0x0E:
471: sprintf(regName, "%c%d", (options & doptRegisterSmall ? 'a' : 'A'), reg & 7);
472: break;
473: }
474: return regName;
475: }
476:
477: /***
478: * return a string pointer to display a register name
479: ***/
480: static const char *Disass68kNumber(int val)
481: {
482: static char numString[32];
483: if(val >= -9 && val <= 9)
484: {
485: sprintf(numString, "%d", val);
486: } else {
487: // 4 characters/numbers or underscore (e.g. for cookies)
1.1.1.5 ! root 488: unsigned char c0 = (val >> 24) & 0xFF;
! 489: unsigned char c1 = (val >> 16) & 0xFF;
! 490: unsigned char c2 = (val >> 8) & 0xFF;
! 491: unsigned char c3 = (val >> 0) & 0xFF;
1.1 root 492: if((isalnum(c0) || c0 == '_') && (isalnum(c1) || c1 == '_') && (isalnum(c2) || c2 == '_') && (isalnum(c3) || c3 == '_'))
493: {
494: sprintf(numString, "'%c%c%c%c'", c0, c1, c2, c3);
495: } else {
496: sprintf(numString, "$%x", val);
497: }
498: }
499: return numString;
500: }
501:
502: /***
503: * Supported registers for e.g. MOVEC
504: ***/
505: #define REG_CCR -1
506: #define REG_SR -2
507: #define REG_PC -3
508: #define REG_ZPC -4
509: #define REG_TT0 -8
510: #define REG_TT1 -9
511: #define REG_MMUSR -10
512: #define REG_USP 0x800
513: #define REG_SFC 0x000
514: #define REG_DFC 0x001
515: #define REG_TC 0x10000
516: #define REG_SRP 0x10002
517: #define REG_CRP 0x10003
518: #define REG_VAL 0x20000
519: #define REG_CACHES_NONE 0x20010
520: #define REG_CACHES_IC 0x20011
521: #define REG_CACHES_DC 0x20012
522: #define REG_CACHES_ICDC 0x20013
523: #define REG_FPU_FPCR 0x30004
524: #define REG_FPU_FPSR 0x30002
525: #define REG_FPU_FPIAR 0x30001
526:
527: static const char *Disass68kSpecialRegister(int reg)
528: {
529: static char buf[8];
530: const char *sp = NULL;
531: switch (reg)
532: {
533: case 0x000: sp = "SFC"; break;
534: case 0x001: sp = "DFC"; break;
535: case 0x002: sp = "CACR"; break;
536: case 0x003: sp = "TC"; break;
537: case 0x004: sp = "ITT0"; break; // IACR0 on an 68EC040 only
538: case 0x005: sp = "ITT1"; break; // IACR1 on an 68EC040 only
539: case 0x006: sp = "DTT0"; break; // DACR0 on an 68EC040 only
540: case 0x007: sp = "DTT1"; break; // DACR1 on an 68EC040 only
541: case 0x008: sp = "BUSCR"; break;
542:
543: case 0x800: sp = "USP"; break;
544: case 0x801: sp = "VBR"; break;
545: case 0x802: sp = "CAAR"; break;
546: case 0x803: sp = "MSP"; break;
547: case 0x804: sp = "ISP"; break;
548: case 0x805: sp = "MMUSR"; break;
549: case 0x806: sp = "URP"; break;
550: case 0x807: sp = "SRP"; break;
551: case 0x808: sp = "PCR"; break;
552:
553: // MMU register
554: case 0x10000: sp = "TC"; break;
555: case 0x10001: sp = "DRP"; break;
556: case 0x10002: sp = "SRP"; break;
557: case 0x10003: sp = "CRP"; break;
558: case 0x10004: sp = "CAL"; break;
559: case 0x10005: sp = "VAL"; break;
560: case 0x10006: sp = "SCCR"; break;
561: case 0x10007: sp = "ACR"; break;
562:
563: case REG_CCR: sp = "CCR"; break;
564: case REG_SR: sp = "SR"; break;
565: case REG_PC: sp = "PC"; break;
566: case REG_ZPC: sp = "ZPC"; break;
567: case REG_TT0: sp = "TT0"; break;
568: case REG_TT1: sp = "TT1"; break;
569: case REG_MMUSR: sp = "MMUSR"; break;
570:
571: case REG_VAL: sp = "VAL"; break;
572:
573: case REG_CACHES_NONE: sp = "NC"; break;
574: case REG_CACHES_IC: sp = "IC"; break;
575: case REG_CACHES_DC: sp = "DC"; break;
576: case REG_CACHES_ICDC: sp = "IC/DC"; break; // GCC lists this as "BC"
577:
578: case REG_FPU_FPCR: sp = "FPCR"; break;
579: case REG_FPU_FPSR: sp = "FPSR"; break;
580: case REG_FPU_FPIAR: sp = "FPIAR"; break;
581:
582: // unknown register => unknown opcode!
1.1.1.4 root 583: default: return NULL;
1.1 root 584: }
1.1.1.4 root 585:
1.1 root 586: if(options & doptRegisterSmall)
587: {
1.1.1.4 root 588: char *bp;
1.1 root 589: strcpy(buf, sp);
1.1.1.4 root 590: for (bp = buf; *bp; ++bp)
1.1.1.5 ! root 591: *bp = tolower((unsigned char)*bp);
1.1 root 592: return buf;
593: }
594: return sp;
595: }
596:
597: /***
598: * 680x0 EA disassembly, supports all address modes
599: *
600: * disassbuf = output buffer for the EA, empty string in case of an illegal EA
601: * addr = pointer to the address, which Disass68kGetWord() will allow to read memory.
602: * Incremented by the function to point behind the opcode, when done
603: * ea = 6-bit ea from the opcode
604: * size = addressed size of the opcode in bytes (e.g. 1,2,4 for MOVE.B, MOVE.W, MOVE.L), only used for immediate addressing
605: ***/
606:
607: #define EA_Dn 0x00001 // Dn
608: #define EA_An 0x00002 // An
609: #define EA_Ani 0x00004 // (An)
610: #define EA_Anip 0x00008 // (An)+
611: #define EA_piAn 0x00010 // -(An)
612: #define EA_dAn 0x00020 // d(An), d(An,Dn), etc.
613: #define EA_PCRel 0x00040 // d(PC), d(PC,Dn), etc.
614: #define EA_Abs 0x00080 // abs.w, abs.l
615: #define EA_Immed 0x00100 // #<val>
616:
617: #define EA_ImmedParameter 0x0200 // an immediate value as a parameter
618: #define EA_ValueParameter 0x0400 // an immediate value as a parameter without the "#"
619: #define EA_SpecialRegister 0x0800 // any special register e.g. SR,CCR,USP,etc
620: #define EA_PCDisplacement 0x1000 // PC relative jump, like for BRA and friends
621:
622: #define EA_All (EA_Dn | EA_An | EA_Ani | EA_Anip | EA_piAn | EA_dAn | EA_Abs | EA_Immed | EA_PCRel)
623: #define EA_Dest (EA_Dn | EA_An | EA_Ani | EA_Anip | EA_piAn | EA_dAn | EA_Abs)
624:
625: static char *Disass68kEA(char *disassbuf, char *commentBuffer, long *addr, long opcodeAddr, int ea, int size, int allowedEAs, int parameterValue, int disassFlag)
626: {
627: unsigned short eWord1;
628: unsigned short eWord2;
629: int xn,c,scale;
630: int reg = ea & 7;
631: const char *sp;
632: long val;
1.1.1.4 root 633: char regName[3];
634: signed long pcoffset;
635:
1.1 root 636: disassbuf[0] = 0;
637: switch(ea)
638: {
639: // M=000 = 0 Dn
640: // Data Register Direct Mode
641: // Dn
642: // M=001 = 1 An
643: // Address Register Direct Mode
644: // An
645: case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
646: if((allowedEAs & EA_Dn) != EA_Dn)
647: break;
648: sprintf(disassbuf, "%s", Disass68kRegname(ea & 0x0F));
649: break;
650: case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: case 0x0D: case 0x0E: case 0x0F:
651: if((allowedEAs & EA_An) != EA_An)
652: break;
653: sprintf(disassbuf, "%s", Disass68kRegname(ea & 0x0F));
654: break;
655:
656: // M=010 = 2
657: // Address Register Indirect Mode
658: // (An)
659: case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
660: if((allowedEAs & EA_Ani) != EA_Ani)
661: break;
662: sprintf(disassbuf, "(%s)", Disass68kRegname(reg | 8));
663: break;
664:
665: // M=011 = 3
666: // Address Register Indirect with Postincrement Mode
667: // (An) +
668: case 0x18: case 0x19: case 0x1A: case 0x1B: case 0x1C: case 0x1D: case 0x1E: case 0x1F:
669: if((allowedEAs & EA_Anip) != EA_Anip)
670: break;
671: sprintf(disassbuf, "(%s)+", Disass68kRegname(reg | 8));
672: break;
673:
674: // M=100 = 4
675: // Address Register Indirect with Predecrement Mode
676: // – (An)
677: case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
678: if((allowedEAs & EA_piAn) != EA_piAn)
679: break;
680: sprintf(disassbuf, "-(%s)", Disass68kRegname(reg | 8));
681: break;
682:
683: // M=101 = 5
684: // Address Register Indirect with Displacement Mode
685: // (d16,An)
686: case 0x28: case 0x29: case 0x2A: case 0x2B: case 0x2C: case 0x2D: case 0x2E: case 0x2F:
687: if((allowedEAs & EA_dAn) != EA_dAn)
688: break;
689: eWord1 = Disass68kGetWord(*addr); *addr += 2;
690: sprintf(disassbuf, "%s(%s)", Disass68kNumber(eWord1), Disass68kRegname(reg | 8));
691: break;
692:
693: // M=111 = 7, Xn/reg = 011 = 3
694: // Program Counter Indirect with Index (Base Displacement) Mode
695: // (bd, PC, Xn. SIZE*SCALE)
696: // Program Counter Memory Indirect Postindexed Mode
697: // ([bd,PC],Xn.SIZE*SCALE,od)
698: // Program Counter Memory Indirect Preindexed Mode
699: // ([bd,PC,Xn.SIZE*SCALE],od)
700: case 0x3B:
701: // This is equal to the following, except that instead of An, it is PC relative
702:
703: // M=110 = 6
704: // Address Register Indirect with Index (Base Displacement) Mode
705: // (bd,An,Xn.SIZE*SCALE)
706: // Memory Indirect Postindexed Mode
707: // ([bd,An],Xn.SIZE*SCALE,od)
708: // Memory Indirect Preindexed Mode
709: // ([bd, An, Xn.SIZE*SCALE], od)
710: case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
711: eWord1 = Disass68kGetWord(*addr); *addr += 2;
712: xn = (eWord1 >> 12) & 0x0F; // Register D0..D7/A0..A7
713: c = ((eWord1 >> 11) & 1) ? 'l' : 'w'; // Word/Long-Word Index Size 0 = Sign-Extended Word 1 = Long Word
714: scale = (eWord1 >> 9) & 3; // Scale Factor 00 = 1 01 = 2 10 = 4 11 = 8
1.1.1.4 root 715:
1.1 root 716: if(ea == 0x3B)
717: {
718: sp = Disass68kSpecialRegister(REG_PC);
719: if(!sp) return NULL;
720: strcpy(regName, sp);
721: } else {
722: sprintf(regName, "%s", Disass68kRegname(reg | 8));
723: }
724:
725: if((eWord1 & 0x0100) == 0)
726: {
1.1.1.4 root 727: const char *numStr;
728:
1.1 root 729: // BRIEF EXTENSION WORD FORMAT
730: if(ea == 0x3B)
731: {
732: if((allowedEAs & EA_PCRel) != EA_PCRel)
733: break;
734: } else {
735: if((allowedEAs & EA_dAn) != EA_dAn)
736: break;
737: }
738:
739: // Address Register Indirect with Index (8-Bit Displacement) Mode
740: // (d8 ,An, Xn.SIZE*SCALE)
1.1.1.4 root 741: numStr = Disass68kNumber(eWord1 & 0xFF);
1.1 root 742: if(numStr[0] == '0' && numStr[1] == 0)
743: numStr = "";
744:
745: // scale is only on 68020 and later supported
746: if(scale != 0 && (optionCPUTypeMask & MC_020) == 0)
747: return NULL;
748:
749: if(scale == 0)
750: {
751: #if ADDRESS_ON_PC
752: if(ea == 0x3B)
753: sprintf(disassbuf, "$%lx(%s,%s.%c)", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2, Disass68kSpecialRegister(REG_PC), Disass68kRegname(xn), c);
754: else
755: #endif
756: sprintf(disassbuf, "%s(%s,%s.%c)", numStr, regName, Disass68kRegname(xn), c);
757: } else
758: {
759: #if ADDRESS_ON_PC
760: if(ea == 0x3B)
761: sprintf(disassbuf, "$%lx(%s,%s.%c*%d)", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2, Disass68kSpecialRegister(REG_PC), Disass68kRegname(xn), c, 1 << scale);
762: else
763: #endif
764: sprintf(disassbuf, "%s(%s,%s.%c*%d)", numStr, regName, Disass68kRegname(xn), c, 1 << scale);
765: }
766: #if USE_SYMBOLS
767: if(ea == 0x3B)
768: {
769: const char *symStr = Disass68kSymbolName((signed char)(eWord1 & 0xFF) + opcodeAddr + 2, size);
770: if(symStr)
771: {
772: commentBuffer += strlen(commentBuffer);
773: sprintf(commentBuffer+strlen(commentBuffer), "%s", symStr);
774: }
775: }
776: #endif
777: #if !ADDRESS_ON_PC
778: if(ea == 0x3B)
779: {
780: commentBuffer += strlen(commentBuffer);
781: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2);
782: }
783: #endif
784: } else {
785: // FULL EXTENSION WORD FORMAT
786:
1.1.1.4 root 787: int bs = (eWord1 >> 7) & 1; // Base Register Suppress 0 = Base Register Added 1 = Base Register Suppressed
788: int is = (eWord1 >> 6) & 1; // Index Suppress 0 = Evaluate and Add Index Operand 1 = Suppress Index Operand
789: int bdSize = (eWord1 >> 4) & 3; // Base Displacement Size 00 = Reserved 01 = Null Displacement 10 = Word Displacement 11 = Long Displacement
790: int iis = eWord1 & 7; // Index/Indirect Selection Indirect and Indexing Operand Determined in Conjunction with Bit 6, Index Suppress
1.1 root 791: bool prefixComma;
1.1.1.4 root 792: long bd, od;
1.1 root 793:
794: // reserved, has to be 0
795: if((eWord1 & 8) != 0 || bdSize == 0 || (is && iis > 3) || iis == 4)
796: break;
797:
798: // full extension format is only supported on 68020 or later
799: if((optionCPUTypeMask & MC_020) == 0)
800: return NULL;
801:
802: if(ea == 0x3B)
803: {
804: if((allowedEAs & EA_PCRel) != EA_PCRel)
805: break;
806: } else {
807: if((allowedEAs & EA_dAn) != EA_dAn)
808: break;
809: }
810:
1.1.1.4 root 811: bd = 0;
1.1 root 812: switch(bdSize)
813: {
814: case 3:
815: bd = Disass68kGetWord(*addr); *addr += 2;
816: bd <<= 16;
817: case 2:
818: bd |= Disass68kGetWord(*addr); *addr += 2;
819: break;
820: default:
821: break;
822: }
823:
824: prefixComma = false;
825: if(bdSize >= 2 && iis == 0)
826: sprintf(disassbuf, "%s", Disass68kNumber(bd));
827: strcat(disassbuf, "(");
828: if(iis != 0)
829: {
830: // the CPU32 doesn't support the memory indirect mode
831: if(optionCPUTypeMask & MC_CPU32)
832: return NULL;
833:
834: strcat(disassbuf, "[");
835: }
836: if(bdSize >= 2 && iis != 0)
837: {
838: sprintf(disassbuf+strlen(disassbuf), "%s", Disass68kNumber(bd));
839: prefixComma = true;
840: }
841: if(bdSize == 1 && ((bs && is && iis > 0) || (bs && iis >= 5)))
842: {
843: if(ea == 0x3B)
844: {
845: sp = Disass68kSpecialRegister(REG_ZPC);
846: if(!sp) return NULL;
847: strcat(disassbuf, sp);
848: } else {
849: strcat(disassbuf, "0");
850: }
851: }
852: if(!bs)
853: {
854: if(prefixComma)
855: strcat(disassbuf, ",");
856: strcat(disassbuf, regName);
857: prefixComma = true;
858: }
859: if(iis >= 5 && iis <= 7)
860: {
861: strcat(disassbuf, "]");
862: prefixComma = true;
863: }
864: if(!is)
865: {
866: if(prefixComma)
867: strcat(disassbuf, ",");
868: if(scale == 0)
869: {
870: sprintf(disassbuf+strlen(disassbuf), "%s.%c", Disass68kRegname(xn), c);
871: } else
872: {
873: sprintf(disassbuf+strlen(disassbuf), "%s.%c*%d", Disass68kRegname(xn), c, 1 << scale);
874: }
875: }
876: if(iis >= 1 && iis <= 3)
877: {
878: strcat(disassbuf, "]");
879: prefixComma = true;
880: }
1.1.1.4 root 881: od = 0;
1.1 root 882: switch(iis & 3)
883: {
884: case 3:
885: od = Disass68kGetWord(*addr); *addr += 2;
886: od <<= 16;
887: case 2:
888: od |= Disass68kGetWord(*addr); *addr += 2;
889: if(prefixComma)
890: strcat(disassbuf, ",");
891: sprintf(disassbuf+strlen(disassbuf), "%s", Disass68kNumber(od));
892: break;
893: default:
894: break;
895: }
896: strcat(disassbuf, ")");
897: }
898: break;
899:
900: // M=111 = 7, Xn/reg = 000 = 0
901: // Absolute Short Addressing Mode
902: // (xxx).W
903: case 0x38:
904: if((allowedEAs & EA_Abs) != EA_Abs)
905: break;
906: eWord1 = Disass68kGetWord(*addr); *addr += 2;
907: val = eWord1;
908: if(eWord1 & 0x8000)
909: val |= 0xFFFF0000;
910: #if USE_SYMBOLS
911: sp = Disass68kSymbolName(val, size);
912: if(sp)
913: {
914: if(options & doptNoBrackets)
915: sprintf(disassbuf, "%s.w", sp);
916: else
917: sprintf(disassbuf, "(%s).w", sp);
918: break;
919: }
920: #endif
921: if(options & doptNoBrackets)
922: {
923: if(val & 0x80000000)
924: sprintf(disassbuf, "$%8.8lx.w", val);
925: else
926: sprintf(disassbuf, "$%4.4lx.w", val);
927: } else {
928: if(val & 0x80000000)
929: sprintf(disassbuf, "($%8.8lx).w", val);
930: else
931: sprintf(disassbuf, "($%4.4lx).w", val);
932: }
933: break;
934:
935: // M=111 = 7, Xn/reg = 001 = 1
936: // Absolute Long Addressing Mode
937: // (xxx).L
938: case 0x39:
939: if((allowedEAs & EA_Abs) != EA_Abs)
940: break;
941: eWord1 = Disass68kGetWord(*addr); *addr += 2;
942: eWord2 = Disass68kGetWord(*addr); *addr += 2;
943: #if USE_SYMBOLS
944: val = (eWord1 << 16) | eWord2;
945: sp = Disass68kSymbolName(val, size);
946: if(sp)
947: {
948: if(options & doptNoBrackets)
949: sprintf(disassbuf, "%s", sp);
950: else
951: sprintf(disassbuf, "(%s).l", sp);
952: break;
953: }
954: #endif
955: if(options & doptNoBrackets)
956: sprintf(disassbuf, "%s", Disass68kNumber((eWord1 << 16) | eWord2));
957: else
958: sprintf(disassbuf, "(%s).l", Disass68kNumber((eWord1 << 16) | eWord2));
959: break;
960:
961: // M=111 = 7, Xn/reg = 010 = 2
962: // Program Counter Indirect with Displacement Mode
963: // (d16,PC)
964: case 0x3A:
965: if((allowedEAs & EA_PCRel) != EA_PCRel)
966: break;
967: eWord1 = Disass68kGetWord(*addr); *addr += 2;
968: sp = Disass68kSpecialRegister(REG_PC);
969: if(!sp) return NULL;
970: #if ADDRESS_ON_PC
971: #if USE_SYMBOLS
972: sp = Disass68kSymbolName(((signed short)eWord1 + *addr - 2), size);
973: if(sp)
974: {
975: sprintf(disassbuf, "%s(%s)", sp, Disass68kSpecialRegister(REG_PC));
976: } else {
977: sprintf(disassbuf, "$%lx(%s)", (signed short)eWord1 + *addr - 2, Disass68kSpecialRegister(REG_PC));
978: }
979: #else
980: sprintf(disassbuf, "$%lx(%s)", (signed short)eWord1 + *addr - 2, Disass68kSpecialRegister(REG_PC));
981: #endif
982: #else
983: sprintf(disassbuf, "%s(%s)", Disass68kNumber(eWord1),sp);
984: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", (signed short)eWord1 + *addr - 2);
985: #endif
986: break;
987:
988: // M=111 = 7, Xn/reg = 100 = 4
989: // Immediate Data
990: // #<xxx>
991: case 0x3C:
992: if((allowedEAs & EA_Immed) != EA_Immed)
993: break;
994: eWord1 = Disass68kGetWord(*addr); *addr += 2;
995: goto immed;
996:
997: case 0x0100: // Immediate Value as a parameter
998: if((allowedEAs & EA_ImmedParameter) != EA_ImmedParameter)
999: break;
1000: eWord1 = parameterValue;
1001: immed:
1002: switch(size)
1003: {
1004: case 1: eWord1 &= 0xFF;
1005: case 2:
1006: #if USE_SYMBOLS
1007: if(disassFlag)
1008: {
1009: val = eWord1;
1010: if(eWord1 & 0x8000)
1011: val |= 0xFFFF0000;
1012: sp = Disass68kSymbolName(val, size);
1013: if(sp)
1014: {
1015: sprintf(disassbuf, "#%s", sp);
1016: break;
1017: }
1018: }
1019: #endif
1020: sprintf(disassbuf, "#%s", Disass68kNumber(eWord1));
1021: break;
1022: case 4: eWord2 = Disass68kGetWord(*addr); *addr += 2;
1023: #if USE_SYMBOLS
1024: if(disassFlag)
1025: {
1026: val = (eWord1 << 16) | eWord2;
1027: sp = Disass68kSymbolName(val, size);
1028: if(sp)
1029: {
1030: sprintf(disassbuf, "#%s", sp);
1031: break;
1032: }
1033: }
1034: #endif
1035: sprintf(disassbuf, "#%s", Disass68kNumber((eWord1 << 16) | eWord2));
1036: break;
1037: }
1038: break;
1039:
1040: case 0x0103:
1041: if((allowedEAs & EA_ValueParameter) != EA_ValueParameter)
1042: break;
1043: sprintf(disassbuf, "%d", parameterValue);
1044: break;
1045:
1046: case 0x0101: // Special Registers as in the parameter
1047: if((allowedEAs & EA_SpecialRegister) != EA_SpecialRegister)
1048: break;
1049: sp = Disass68kSpecialRegister(parameterValue);
1050: if(!sp) return NULL;
1051: strcpy(disassbuf, sp);
1052: break;
1053:
1054: case 0x0102: // PC relative jump, like for BRA and friends
1055: if((allowedEAs & EA_PCDisplacement) != EA_PCDisplacement)
1056: break;
1.1.1.4 root 1057: pcoffset = 0;
1.1 root 1058: switch(size)
1059: {
1060: case 1: pcoffset = (signed char)parameterValue;
1061: break;
1062: case 2: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1063: pcoffset = (signed short)eWord1;
1064: pcoffset -= 2;
1065: break;
1066: case 4: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1067: eWord2 = Disass68kGetWord(*addr); *addr += 2;
1068: pcoffset = (signed int)((eWord1 << 16) | eWord2);
1069: pcoffset -= 4;
1070: break;
1071: }
1072: #if ADDRESS_ON_PC
1073: #if USE_SYMBOLS
1074: sp = Disass68kSymbolName((*addr + pcoffset), size);
1075: if(sp)
1076: {
1077: strcat(disassbuf, sp);
1078: } else {
1079: sprintf(disassbuf, "$%lx", *addr + pcoffset);
1080: }
1081: #else
1082: sprintf(disassbuf, "$%lx", *addr + pcoffset);
1083: #endif
1084: #else
1085: if(pcoffset < 0)
1086: {
1087: sprintf(disassbuf, "*-$%lx", -pcoffset - 2);
1088: } else {
1089: sprintf(disassbuf, "*+$%lx", pcoffset + 2);
1090: }
1091: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", *addr + pcoffset);
1092: #endif
1093: break;
1094:
1095: default: // 0x3D..0x3F are reserved
1096: break;
1097:
1098: }
1099: if(disassbuf[0] == 0)
1100: return NULL;
1101: return disassbuf + strlen(disassbuf);
1102: }
1103:
1104: /***
1105: * Create a register list for the MOVEM opcode
1106: ***/
1107: static char *Disass68kReglist(char *buf, unsigned short reglist)
1108: {
1109: int bit;
1110: int lastBit = -99;
1111: int lastBitStart = -99;
1112: char regD = options & doptRegisterSmall ? 'd' : 'D';
1113: char regA = options & doptRegisterSmall ? 'a' : 'A';
1114: for(bit=0; bit<=15; ++bit)
1115: {
1116: // bit clear?
1117: if((reglist & (1 << bit)) == 0)
1118: {
1119: // do we have a run? => close it!
1120: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1121: {
1122: *buf++ = '-';
1123: *buf++ = ((bit-1) >= 8) ? regA : regD;
1124: *buf++ = '0' + ((bit-1) & 7);
1125: }
1126: lastBitStart = -1;
1127: continue;
1128: }
1129: // reset when switching from D to A
1130: if(bit == 8 && lastBitStart >= 0)
1131: {
1132: *buf++ = '-';
1133: *buf++ = regD;
1134: *buf++ = '7';
1135: lastBit = 0;
1136: lastBitStart = -99;
1137: }
1138: // separate bits, skip runs of bits to merge them later
1139: if(lastBit >= 0)
1140: {
1141: if(lastBit == bit - 1)
1142: {
1143: lastBit = bit;
1144: continue;
1145: }
1146: *buf++ = '/';
1147: }
1148: *buf++ = (bit >= 8) ? regA : regD;
1149: *buf++ = '0' + (bit & 7);
1150: lastBit = bit;
1151: lastBitStart = bit;
1152: }
1153: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1154: {
1155: *buf++ = '-';
1156: *buf++ = regA;
1157: *buf++ = '7';
1158: }
1159: if(lastBit < 0)
1160: {
1161: *buf++ = '0';
1162: }
1163: *buf = 0;
1164: return buf;
1165: }
1166:
1167: /***
1168: * Flip the bits in an unsigned short, for MOVEM RegList,-(An)
1169: ***/
1170: static unsigned short Disass68kFlipBits(unsigned short mask)
1171: {
1172: unsigned short retMask = 0;
1173: int i;
1174:
1175: for(i=0; i<=15; ++i)
1176: if(mask & (1 << i))
1177: retMask |= (1 << (15-i));
1178: return retMask;
1179: }
1180:
1181: /***
1182: * Create a register list for the MOVEM opcode
1183: ***/
1184: static char *Disass68kFPUReglist(char *buf, unsigned char reglist)
1185: {
1186: int bit;
1187: int lastBit = -99;
1188: int lastBitStart = -99;
1189: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
1190: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
1191: for(bit=0; bit<=7; ++bit)
1192: {
1193: // bit clear?
1194: if((reglist & (1 << bit)) == 0)
1195: {
1196: // do we have a run? => close it!
1197: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1198: {
1199: *buf++ = '-';
1200: *buf++ = regFP1;
1201: *buf++ = regFP2;
1202: *buf++ = '0' + ((bit-1) & 7);
1203: }
1204: lastBitStart = -1;
1205: continue;
1206: }
1207: // separate bits, skip runs of bits to merge them later
1208: if(lastBit >= 0)
1209: {
1210: if(lastBit == bit - 1)
1211: {
1212: lastBit = bit;
1213: continue;
1214: }
1215: *buf++ = '/';
1216: }
1217: *buf++ = regFP1;
1218: *buf++ = regFP2;
1219: *buf++ = '0' + (bit & 7);
1220: lastBit = bit;
1221: lastBitStart = bit;
1222: }
1223: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1224: {
1225: *buf++ = '-';
1226: *buf++ = regFP1;
1227: *buf++ = regFP2;
1228: *buf++ = '7';
1229: }
1230: if(lastBit < 0)
1231: {
1232: *buf++ = '0';
1233: }
1234: *buf = 0;
1235: return buf;
1236: }
1237:
1238:
1239: /***
1240: * List of special cases for the operands
1241: ***/
1242: typedef enum {
1243: ofNone,
1244: ofEa,
1245: ofDn,
1246: ofAn,
1247: ofAni,
1248: ofI,
1249: ofSpecReg,
1250: ofSpecExtReg,
1251: ofD16An,
1252: ofDestDn,
1253: ofDestAn,
1254: ofExtReg,
1255: ofExtAnip,
1256: ofExtReg0,
1257: ofExtRegA0,
1258: ofExtRegD04,
1259: ofExtRegA05,
1260: ofFPUReglist,
1261: ofFPUSRRegList,
1262: ofDestEa6,
1263: ofDestAbsL,
1264: ofIOpcode,
1265: ofCAS,
1266: ofCAS2,
1267: ofI3,
1268: ofExtIm,
1269: ofExtIm32,
1270: ofExtIm4,
1271: ofExtIm10,
1272: ofDisp,
1273: ofPiAn,
1274: ofDestPiAn,
1275: ofAnip,
1276: ofDestAnip,
1277: ofBFEa,
1278: ofRegList,
1279: ofExt4Dn,
1280: ofFPU,
1281: ofFPUMOVE,
1282: ofFMOVECR,
1283: ofFPU3Reg,
1.1.1.5 ! root 1284: ofLineA
1.1 root 1285: } Disass68kOpcodeFormat;
1286:
1287:
1288: /***
1289: * The order of the table is not important (with the exception of some FPU opcodes, which are commented further down),
1290: * as each opcode should decline if it doesn't match 100%. The 68k CPU also doesn't do guessing based on the context!
1291: ***/
1292: typedef const struct {
1293: int cpuMask;
1294: unsigned long opcodeMask[2*5];
1.1.1.4 root 1295: signed char operationSize[4];
1.1 root 1296: char op[5];
1297: const char *opcodeName;
1298: int parameter[5];
1299: int disassFlag;
1300: } OpcodeTableStruct;
1301:
1302: static const OpcodeTableStruct OpcodeTable[] = {
1303: { MC_ALL, {0xff00, 0x0000}, {-1,6,2,0}, {ofI,ofEa}, "ORI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1304: { MC_ALL, {0xf1c0, 0x0100}, {4}, {ofDestDn,ofEa}, "BTST",{0,EA_An|EA_Immed} },
1305: { MC_ALL, {0xf1c0, 0x0140}, {4}, {ofDestDn,ofEa}, "BCHG",{0,EA_Immed|EA_PCRel|EA_An}},
1306: { MC_ALL, {0xf1c0, 0x0180}, {4}, {ofDestDn,ofEa}, "BCLR",{0,EA_Immed|EA_PCRel|EA_An}},
1307: { MC_ALL, {0xf1c0, 0x01C0}, {4}, {ofDestDn,ofEa}, "BSET",{0,EA_Immed|EA_PCRel|EA_An}},
1308: { MC_ALL-MC68060, {0xf1f8, 0x0108}, {2}, {ofD16An,ofDestDn}, "MOVEP.W"},
1309: { MC_ALL-MC68060, {0xf1f8, 0x0148}, {4}, {ofD16An,ofDestDn}, "MOVEP.L"},
1310: { MC_ALL-MC68060, {0xf1f8, 0x0188}, {2}, {ofDestDn,ofD16An}, "MOVEP.W"},
1311: { MC_ALL-MC68060, {0xf1f8, 0x01C8}, {4}, {ofDestDn,ofD16An}, "MOVEP.L"},
1312: { MC_ALL, {0xff00, 0x0200}, {-1,6,2,0}, {ofI,ofEa}, "ANDI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1313: { MC_ALL, {0xff00, 0x0400}, {-1,6,2,0}, {ofI,ofEa}, "SUBI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1314: { MC_ALL, {0xff00, 0x0600}, {-1,6,2,0}, {ofI,ofEa}, "ADDI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1315: { MC_ALL, {0xffc0, 0x0800}, {1}, {ofI,ofEa}, "BTST",{0,EA_An|EA_Immed} },
1316: { MC_ALL, {0xffc0, 0x0840}, {1}, {ofI,ofEa}, "BCHG",{0,EA_Immed|EA_PCRel|EA_An}},
1317: { MC_ALL, {0xffc0, 0x0880}, {1}, {ofI,ofEa}, "BCLR",{0,EA_Immed|EA_PCRel|EA_An}},
1318: { MC_ALL, {0xffc0, 0x08C0}, {1}, {ofI,ofEa}, "BSET",{0,EA_Immed|EA_PCRel|EA_An}},
1319: { MC_ALL, {0xff00, 0x0A00}, {-1,6,2,0}, {ofI,ofEa}, "EORI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1320: { MC_ALL, {0xff00, 0x0C00}, {-1,6,2,0}, {ofI,ofEa}, "CMPI.?",{0,EA_Immed|EA_An}},
1321: { MC_ALL, {0xffff, 0x003C}, {1}, {ofEa,ofSpecReg}, "ORI",{0,REG_CCR} },
1322: { MC_ALL, {0xffff, 0x007C}, {2}, {ofEa,ofSpecReg}, "ORI",{0,REG_SR} },
1323: { MC_ALL, {0xffff, 0x023C}, {1}, {ofEa,ofSpecReg}, "ANDI",{0,REG_CCR} },
1324: { MC_ALL, {0xffff, 0x027C}, {2}, {ofEa,ofSpecReg}, "ANDI",{0,REG_SR} },
1325: { MC_ALL, {0xffff, 0x0A3C}, {1}, {ofEa,ofSpecReg}, "EORI",{0,REG_CCR} },
1326: { MC_ALL, {0xffff, 0x0A7C}, {2}, {ofEa,ofSpecReg}, "EORI",{0,REG_SR} },
1327: { MC68020, {0xffc0, 0x06C0}, {1}, {ofEa}, "CALLM",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1328: { MC68020, {0xfff0, 0x06C0}, {1}, {ofEa}, "RTM"},
1329: { MC_020, {0xf9c0, 0x00C0, 0x0fff,0x0000}, {-1,9,2,0}, {ofEa,ofExtReg}, "CMP2.?",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1330: { MC_020, {0xf9c0, 0x00C0, 0x0fff,0x0800}, {-1,9,2,0}, {ofEa,ofExtReg}, "CHK2.?",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1331: { MC_020&~MC_CPU32, {0xffc0, 0x0AC0, 0xFE38,0x0000}, {1}, {ofCAS,ofEa}, "CAS.B",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1332: { MC_020&~MC_CPU32, {0xffc0, 0x0CC0, 0xFE38,0x0000}, {2}, {ofCAS,ofEa}, "CAS.W",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1333: { MC_020&~MC_CPU32, {0xffc0, 0x0EC0, 0xFE38,0x0000}, {4}, {ofCAS,ofEa}, "CAS.L",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1334: { MC_020&~MC_CPU32, {0xffff, 0x0CFC, 0x0E38,0x0000, 0x0E38,0x0000}, {2}, {ofCAS2}, "CAS2.W"},
1335: { MC_020&~MC_CPU32, {0xffff, 0x0EFC, 0x0E38,0x0000, 0x0E38,0x0000}, {4}, {ofCAS2}, "CAS2.L"},
1336: { MC68010|MC_020, {0xff00, 0x0e00, 0x0fff,0x0000}, {-1,6,2,0}, {ofEa,ofExtReg}, "MOVES.?",{EA_Immed|EA_PCRel|EA_An|EA_Dn,0}},
1337: { MC68010|MC_020, {0xff00, 0x0e00, 0x0fff,0x0800}, {-1,6,2,0}, {ofExtReg,ofEa}, "MOVES.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1338:
1339: { MC_ALL, {0xf000, 0x1000}, {1}, {ofEa,ofDestEa6}, "MOVE.B"},
1340:
1341: { MC_ALL, {0xf000, 0x2000}, {4}, {ofEa,ofDestEa6}, "MOVE.L"},
1342: { MC_ALL, {0xf1c0, 0x2040}, {4}, {ofEa,ofDestAn}, "MOVEA.L",{0},1},
1343:
1344: { MC_ALL, {0xf000, 0x3000}, {2}, {ofEa,ofDestEa6}, "MOVE.W"},
1345: { MC_ALL, {0xf1c0, 0x3040}, {2}, {ofEa,ofDestAn}, "MOVEA.W",{0},1},
1346:
1347: { MC_ALL, {0xff00, 0x4000}, {-1,6,2,0}, {ofEa}, "NEGX.?",{EA_Immed|EA_PCRel|EA_An}},
1348: { MC_020, {0xf1c0, 0x4100}, {4}, {ofEa,ofDestDn}, "CHK.L", {EA_An,0}},
1349: { MC_ALL, {0xf1c0, 0x4180}, {2}, {ofEa,ofDestDn}, "CHK.W", {EA_An,0}},
1350: { MC_ALL, {0xf1c0, 0x41c0}, {4}, {ofEa,ofDestAn}, "LEA",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn,0},1 },
1351: { MC_ALL, {0xff00, 0x4200}, {-1,6,2,0}, {ofEa}, "CLR.?",{EA_Immed|EA_PCRel|EA_An}},
1352: { MC_ALL, {0xff00, 0x4400}, {-1,6,2,0}, {ofEa}, "NEG.?",{EA_Immed|EA_PCRel|EA_An}},
1353: { MC_ALL, {0xff00, 0x4600}, {-1,6,2,0}, {ofEa}, "NOT.?",{EA_Immed|EA_PCRel|EA_An}},
1354: { MC_ALL, {0xffc0, 0x40c0}, {2}, {ofSpecReg,ofEa}, "MOVE",{REG_SR,EA_Immed|EA_PCRel|EA_An} },
1355: { MC_ALL, {0xffc0, 0x42c0}, {1}, {ofSpecReg,ofEa}, "MOVE",{REG_CCR,EA_Immed|EA_PCRel|EA_An} },
1356: { MC_ALL, {0xffc0, 0x44c0}, {1}, {ofEa,ofSpecReg}, "MOVE",{EA_An,REG_CCR} },
1357: { MC_ALL, {0xffc0, 0x46c0}, {2}, {ofEa,ofSpecReg}, "MOVE",{EA_An,REG_SR} },
1358: { MC_ALL, {0xffc0, 0x4800}, {1}, {ofEa}, "NBCD",{EA_Immed|EA_PCRel|EA_An}},
1359: { MC_020, {0xfff8, 0x4808}, {4}, {ofEa,ofI}, "LINK.L"},
1360: { MC_ALL, {0xffc0, 0x4840}, {0}, {ofEa}, "PEA",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn},1 },
1361: { MC_ALL, {0xfff8, 0x4840}, {4}, {ofEa}, "SWAP"},
1362: { MC68010|MC_020, {0xfff8, 0x4848}, {0}, {ofIOpcode}, "BKPT",{0x07} },
1363: { MC_ALL, {0xffc0, 0x4880, 0x10000}, {2}, {ofRegList,ofEa}, "MOVEM.W",{0,EA_Dn|EA_An|EA_Immed|EA_Anip|EA_PCRel} },
1364: { MC_ALL, {0xffc0, 0x48c0, 0x10000}, {4}, {ofRegList,ofEa}, "MOVEM.L",{0,EA_Dn|EA_An|EA_Immed|EA_Anip|EA_PCRel} },
1365: { MC_ALL, {0xfff8, 0x4880}, {2}, {ofEa}, "EXT.W"},
1366: { MC_ALL, {0xfff8, 0x48c0}, {4}, {ofEa}, "EXT.L"},
1367: { MC_020, {0xfff8, 0x49c0}, {4}, {ofEa}, "EXTB.L"},
1368: { MC_ALL, {0xff00, 0x4a00}, {-1,6,2,0}, {ofEa}, "TST.?"},
1369: { MC_ALL, {0xffc0, 0x4ac0}, {1}, {ofEa}, "TAS",{EA_Immed|EA_PCRel|EA_An}},
1370: { MC_CPU32, {0xffff, 0x4afa}, {0}, {ofNone}, "BGND"},
1371: { MC_ALL, {0xffff, 0x4afc}, {0}, {ofNone}, "ILLEGAL"},
1372: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0000}, {4}, {ofEa,ofExtReg}, "MULU.L", {EA_An,0}},
1373: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0800}, {4}, {ofEa,ofExtReg}, "MULS.L", {EA_An,0}},
1374: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0000}, {4}, {ofEa,ofExtReg}, "DIVU.L", {EA_An,0}},
1375: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0800}, {4}, {ofEa,ofExtReg}, "DIVS.L", {EA_An,0}},
1376: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0400}, {4}, {ofEa,ofExtReg,ofExtReg0}, "MULU.L", {EA_An,0,0}},
1377: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0c00}, {4}, {ofEa,ofExtReg,ofExtReg0}, "MULS.L", {EA_An,0,0}},
1378: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0400}, {4}, {ofEa,ofExtReg,ofExtReg0}, "DIVU.L", {EA_An,0,0}},
1379: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0c00}, {4}, {ofEa,ofExtReg,ofExtReg0}, "DIVS.L", {EA_An,0,0}},
1380: { MC_ALL, {0xffc0, 0x4c80, 0x10000}, {2}, {ofEa,ofRegList}, "MOVEM.W",{EA_Dn|EA_An|EA_Immed|EA_piAn,0} },
1381: { MC_ALL, {0xffc0, 0x4cc0, 0x10000}, {4}, {ofEa,ofRegList}, "MOVEM.L",{EA_Dn|EA_An|EA_Immed|EA_piAn,0} },
1382: { MC_ALL, {0xfff0, 0x4e40}, {0}, {ofIOpcode}, "TRAP",{0x0f} },
1383: { MC_ALL, {0xfff8, 0x4e50}, {2}, {ofAn,ofI}, "LINK"},
1384: { MC_ALL, {0xfff8, 0x4e58}, {4}, {ofAn}, "UNLK"},
1385: { MC_ALL, {0xfff8, 0x4e60}, {4}, {ofAn,ofSpecReg}, "MOVE",{0,REG_USP} },
1386: { MC_ALL, {0xfff8, 0x4e68}, {4}, {ofSpecReg,ofAn}, "MOVE",{REG_USP,0} },
1387: { MC_ALL, {0xffff, 0x4e70}, {0}, {ofNone}, "RESET"},
1388: { MC_ALL, {0xffff, 0x4e71}, {0}, {ofNone}, "NOP"},
1389: { MC_ALL, {0xffff, 0x4e72}, {2}, {ofI}, "STOP"},
1390: { MC_ALL, {0xffff, 0x4e73}, {0}, {ofNone}, "RTE"},
1391: { MC68010|MC_020, {0xffff, 0x4e74}, {2}, {ofI}, "RTD"},
1392: { MC_ALL, {0xffff, 0x4e75}, {0}, {ofNone}, "RTS"},
1393: { MC_ALL, {0xffff, 0x4e76}, {0}, {ofNone}, "TRAPV"},
1394: { MC_ALL, {0xffff, 0x4e77}, {0}, {ofNone}, "RTR"},
1395: { MC68010|MC_020, {0xffff, 0x4e7a, 0x10000}, {4}, {ofSpecExtReg,ofExtReg}, "MOVEC"},
1396: { MC68010|MC_020, {0xffff, 0x4e7b, 0x10000}, {4}, {ofExtReg,ofSpecExtReg}, "MOVEC"},
1397: { MC_ALL, {0xffc0, 0x4e80}, {0}, {ofEa}, "JSR",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1398: { MC_ALL, {0xffc0, 0x4ec0}, {0}, {ofEa}, "JMP",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1399:
1400: { MC_ALL, {0xf1c0, 0x5000}, {1}, {ofI3,ofEa}, "ADDQ.B",{0,EA_An|EA_Immed|EA_PCRel} },
1401: { MC_ALL, {0xf1c0, 0x5040}, {2}, {ofI3,ofEa}, "ADDQ.W",{0,EA_Immed|EA_PCRel} },
1402: { MC_ALL, {0xf1c0, 0x5080}, {4}, {ofI3,ofEa}, "ADDQ.L",{0,EA_Immed|EA_PCRel} },
1403: { MC_ALL, {0xf0c0, 0x50C0}, {1}, {ofEa}, "Sci",{EA_Immed|EA_PCRel|EA_An}},
1404: { MC_ALL, {0xf0f8, 0x50C8}, {2}, {ofDn,ofDisp}, "DBcd"},
1405: { MC_020, {0xf0ff, 0x50fa}, {2}, {ofI}, "TRAPci.W"},
1406: { MC_020, {0xf0ff, 0x50fb}, {4}, {ofI}, "TRAPci.L"},
1407: { MC_020, {0xf0ff, 0x50fc}, {0}, {ofNone}, "TRAPci"},
1408: { MC_ALL, {0xf1c0, 0x5100}, {1}, {ofI3,ofEa}, "SUBQ.B",{0,EA_An|EA_Immed|EA_PCRel} },
1409: { MC_ALL, {0xf1c0, 0x5140}, {2}, {ofI3,ofEa}, "SUBQ.W",{0,EA_Immed|EA_PCRel} },
1410: { MC_ALL, {0xf1c0, 0x5180}, {4}, {ofI3,ofEa}, "SUBQ.L",{0,EA_Immed|EA_PCRel} },
1411:
1412: { MC_ALL, {0xf0ff, 0x6000}, {2}, {ofDisp}, "Bcb"},
1413: { MC_ALL, {0xf000, 0x6000}, {1}, {ofDisp}, "Bcb.S"},
1414: { MC_020, {0xf0ff, 0x60FF}, {4}, {ofDisp}, "Bcb.L"},
1415:
1416: { MC_ALL, {0xf100, 0x7000}, {0}, {ofIOpcode,ofDestDn}, "MOVEQ", {0xFF,0}},
1417:
1418: { MC_ALL, {0xf100, 0x8000}, {-1,6,2,0}, {ofEa,ofDestDn}, "OR.?", {EA_An,0}},
1419: { MC_ALL, {0xf100, 0x8100}, {-1,6,2,0}, {ofDestDn,ofEa}, "OR.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1420: { MC_ALL, {0xf1f8, 0x8100}, {1}, {ofDn,ofDestDn}, "SBCD"},
1421: { MC_ALL, {0xf1f8, 0x8108}, {1}, {ofPiAn,ofDestPiAn}, "SBCD"},
1422: { MC_020&~MC_CPU32, {0xf1f8, 0x8140, 0x10000}, {0}, {ofDn,ofDestDn,ofExtIm}, "PACK"},
1423: { MC_020&~MC_CPU32, {0xf1f8, 0x8148, 0x10000}, {0}, {ofPiAn,ofDestPiAn,ofExtIm}, "PACK"},
1424: { MC_020&~MC_CPU32, {0xf1f8, 0x8180, 0x10000}, {0}, {ofDn,ofDestDn,ofExtIm}, "UNPK"},
1425: { MC_020&~MC_CPU32, {0xf1f8, 0x8188, 0x10000}, {0}, {ofPiAn,ofDestPiAn,ofExtIm}, "UNPK"},
1426: { MC_ALL, {0xf1c0, 0x80c0}, {2}, {ofEa,ofDestDn}, "DIVU.W", {EA_An,0}},
1427: { MC_ALL, {0xf1c0, 0x81c0}, {2}, {ofEa,ofDestDn}, "DIVS.W", {EA_An,0}},
1428:
1429: { MC_ALL, {0xf1c0, 0x9000}, {1}, {ofEa,ofDestDn}, "SUB.B", {EA_An,0}},
1430: { MC_ALL, {0xf1c0, 0x9040}, {2}, {ofEa,ofDestDn}, "SUB.W"},
1431: { MC_ALL, {0xf1c0, 0x9080}, {4}, {ofEa,ofDestDn}, "SUB.L"},
1432: { MC_ALL, {0xf1c0, 0x90c0}, {2}, {ofEa,ofDestAn}, "SUBA.W"},
1433: { MC_ALL, {0xf1c0, 0x91c0}, {4}, {ofEa,ofDestAn}, "SUBA.L"},
1434: { MC_ALL, {0xf100, 0x9100}, {-1,6,2,0}, {ofDestDn,ofEa}, "SUB.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1435: { MC_ALL, {0xf138, 0x9100}, {-1,6,2,0}, {ofDn,ofDestDn}, "SUBX.?"},
1436: { MC_ALL, {0xf138, 0x9108}, {-1,6,2,0}, {ofPiAn,ofDestPiAn}, "SUBX.?"},
1437:
1438: { MC_ALL, {0xf000, 0xa000}, {0}, {ofLineA}, "LINEA"},
1439:
1440: { MC_ALL, {0xf1c0, 0xb000}, {1}, {ofEa,ofDestDn}, "CMP.B", {EA_An,0}},
1441: { MC_ALL, {0xf1c0, 0xb040}, {2}, {ofEa,ofDestDn}, "CMP.W"},
1442: { MC_ALL, {0xf1c0, 0xb080}, {4}, {ofEa,ofDestDn}, "CMP.L"},
1443: { MC_ALL, {0xf1c0, 0xb0c0}, {2}, {ofEa,ofDestAn}, "CMPA.W"},
1444: { MC_ALL, {0xf1c0, 0xb1c0}, {4}, {ofEa,ofDestAn}, "CMPA.L"},
1445: { MC_ALL, {0xf100, 0xb100}, {-1,6,2,0}, {ofDestDn,ofEa}, "EOR.?",{0,EA_An|EA_Immed|EA_PCRel} },
1446: { MC_ALL, {0xf138, 0xb108}, {-1,6,2,0}, {ofAnip,ofDestAnip}, "CMPM.?"},
1447:
1448: { MC_ALL, {0xf100, 0xc000}, {-1,6,2,0}, {ofEa,ofDestDn}, "AND.?", {EA_An,0}},
1449: { MC_ALL, {0xf100, 0xc100}, {-1,6,2,0}, {ofDestDn,ofEa}, "AND.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1450: { MC_ALL, {0xf1f8, 0xc100}, {1}, {ofDn,ofDestDn}, "ABCD"},
1451: { MC_ALL, {0xf1f8, 0xc108}, {1}, {ofPiAn,ofDestPiAn}, "ABCD"},
1452: { MC_ALL, {0xf1f8, 0xc140}, {1}, {ofDestDn,ofDn}, "EXG"},
1453: { MC_ALL, {0xf1f8, 0xc148}, {1}, {ofDestAn,ofAn}, "EXG"},
1454: { MC_ALL, {0xf1f8, 0xc188}, {1}, {ofDestDn,ofAn}, "EXG"},
1455: { MC_ALL, {0xf1c0, 0xc0c0}, {2}, {ofEa,ofDestDn}, "MULU.W", {EA_An,0}},
1456: { MC_ALL, {0xf1c0, 0xc1c0}, {2}, {ofEa,ofDestDn}, "MULS.W", {EA_An,0}},
1457:
1458: { MC_ALL, {0xf1c0, 0xd000}, {1}, {ofEa,ofDestDn}, "ADD.B", {EA_An,0}},
1459: { MC_ALL, {0xf1c0, 0xd040}, {2}, {ofEa,ofDestDn}, "ADD.W"},
1460: { MC_ALL, {0xf1c0, 0xd080}, {4}, {ofEa,ofDestDn}, "ADD.L"},
1461: { MC_ALL, {0xf1c0, 0xd0c0}, {2}, {ofEa,ofDestAn}, "ADDA.W"},
1462: { MC_ALL, {0xf1c0, 0xd1c0}, {4}, {ofEa,ofDestAn}, "ADDA.L"},
1463: { MC_ALL, {0xf100, 0xd100}, {-1,6,2,0}, {ofDestDn,ofEa}, "ADD.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1464: { MC_ALL, {0xf138, 0xd100}, {-1,6,2,0}, {ofDn,ofDestDn}, "ADDX.?"},
1465: { MC_ALL, {0xf138, 0xd108}, {-1,6,2,0}, {ofPiAn,ofDestPiAn}, "ADDX.?"},
1466:
1467: { MC_ALL, {0xf138, 0xe000}, {-1,6,2,0}, {ofI3,ofDn}, "ASR.?"},
1468: { MC_ALL, {0xf138, 0xe008}, {-1,6,2,0}, {ofI3,ofDn}, "LSR.?"},
1469: { MC_ALL, {0xf138, 0xe010}, {-1,6,2,0}, {ofI3,ofDn}, "ROXR.?"},
1470: { MC_ALL, {0xf138, 0xe018}, {-1,6,2,0}, {ofI3,ofDn}, "ROR.?"},
1471: { MC_ALL, {0xf138, 0xe020}, {-1,6,2,0}, {ofDestDn,ofDn}, "ASR.?"},
1472: { MC_ALL, {0xf138, 0xe028}, {-1,6,2,0}, {ofDestDn,ofDn}, "LSR.?"},
1473: { MC_ALL, {0xf138, 0xe030}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROXR.?"},
1474: { MC_ALL, {0xf138, 0xe038}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROR.?"},
1475: { MC_ALL, {0xf138, 0xe100}, {-1,6,2,0}, {ofI3,ofDn}, "ASL.?"},
1476: { MC_ALL, {0xf138, 0xe108}, {-1,6,2,0}, {ofI3,ofDn}, "LSL.?"},
1477: { MC_ALL, {0xf138, 0xe110}, {-1,6,2,0}, {ofI3,ofDn}, "ROXL.?"},
1478: { MC_ALL, {0xf138, 0xe118}, {-1,6,2,0}, {ofI3,ofDn}, "ROL.?"},
1479: { MC_ALL, {0xf138, 0xe120}, {-1,6,2,0}, {ofDestDn,ofDn}, "ASL.?"},
1480: { MC_ALL, {0xf138, 0xe128}, {-1,6,2,0}, {ofDestDn,ofDn}, "LSL.?"},
1481: { MC_ALL, {0xf138, 0xe130}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROXL.?"},
1482: { MC_ALL, {0xf138, 0xe138}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROL.?"},
1483: { MC_ALL, {0xffc0, 0xe0c0}, {1}, {ofEa}, "ASR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1484: { MC_ALL, {0xffc0, 0xe1c0}, {1}, {ofEa}, "ASL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1485: { MC_ALL, {0xffc0, 0xe2c0}, {1}, {ofEa}, "LSR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1486: { MC_ALL, {0xffc0, 0xe3c0}, {1}, {ofEa}, "LSL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1487: { MC_ALL, {0xffc0, 0xe4c0}, {1}, {ofEa}, "ROXR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1488: { MC_ALL, {0xffc0, 0xe5c0}, {1}, {ofEa}, "ROXL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1489: { MC_ALL, {0xffc0, 0xe6c0}, {1}, {ofEa}, "ROR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1490: { MC_ALL, {0xffc0, 0xe7c0}, {1}, {ofEa}, "ROL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1491: { MC_020&~MC_CPU32, {0xffc0, 0xe8c0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFTST",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1492: { MC_020&~MC_CPU32, {0xffc0, 0xe9c0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFEXTU",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1493: { MC_020&~MC_CPU32, {0xffc0, 0xeac0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFCHG",{EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1494: { MC_020&~MC_CPU32, {0xffc0, 0xebc0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFEXTS",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1495: { MC_020&~MC_CPU32, {0xffc0, 0xecc0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFCLR",{EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1496: { MC_020&~MC_CPU32, {0xffc0, 0xedc0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFFFO",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1497: { MC_020&~MC_CPU32, {0xffc0, 0xeec0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFSET",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1498: { MC_020&~MC_CPU32, {0xffc0, 0xefc0, 0x8000, 0x0000}, {1}, {ofExtReg,ofBFEa}, "BFINS",{0,EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1499:
1500:
1501: #define PMMU_COPROC_ID 0 // 0 is the standard PMMU
1502:
1503: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2000}, {0}, {ofSpecReg,ofEa}, "PLOADW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1504: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2001}, {0}, {ofSpecReg,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1505: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2008}, {0}, {ofExtReg0,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1506: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff0, 0x2010}, {0}, {ofExtIm4,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1507:
1508: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2200}, {0}, {ofSpecReg,ofEa}, "PLOADR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1509: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2201}, {0}, {ofSpecReg,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1510: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2208}, {0}, {ofExtReg0,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1511: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff0, 0x2210}, {0}, {ofExtIm4,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1512:
1513: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0xa000}, {0}, {ofEa}, "PFLUSHR",{EA_Dn|EA_An} },
1514:
1515: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0800}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1516: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0900}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1517: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0B00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1518: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0C00}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1519: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0C00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1520: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0D00}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1521: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0E00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1522: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0F00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1523: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4000}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1524: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4100}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1525: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4200}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1526: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4300}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1527: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4800}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1528: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4900}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1529: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4A00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1530: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4B00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1531: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4C00}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1532: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4D00}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1533: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4e00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1534: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4f00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1535: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x6000}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_MMUSR} },
1536: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x6200}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_MMUSR} },
1537:
1538: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2800}, {0}, {ofSpecReg,ofEa}, "PVALID",{REG_VAL,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1539: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2C00}, {0}, {ofExtRegA0,ofEa}, "PVALID",{0,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1540:
1541: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8000}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1542: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8001}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1543: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f8, 0x8008}, {0}, {ofExtReg0,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1544: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f0, 0x8010}, {0}, {ofExtIm4,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1545:
1546: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8200}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1547: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8201}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1548: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f8, 0x8208}, {0}, {ofExtReg0,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1549: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f0, 0x8210}, {0}, {ofExtIm4,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1550:
1551: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8100}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1552: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8101}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1553: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe318, 0x8108}, {0}, {ofExtReg0,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1554: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe310, 0x8110}, {0}, {ofExtIm4,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1555:
1556: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8300}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1557: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8301}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1558: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe318, 0x8308}, {0}, {ofExtReg0,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1559: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe310, 0x8310}, {0}, {ofExtIm4,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1560:
1561: { MC_PMMU, {0xffc0, 0xf040|(PMMU_COPROC_ID<<9), 0xfff0, 0x8310}, {0}, {ofEa}, "PScp",{EA_An|EA_Immed|EA_PCRel} },
1562: { MC_PMMU, {0xfff8, 0xf048|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000}, {2}, {ofDn,ofDisp}, "PDBcp"},
1563: { MC_PMMU, {0xffff, 0xf07A|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {2}, {ofExtIm32}, "PTRAPcp.W" },
1564: { MC_PMMU, {0xffff, 0xf07B|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {4}, {ofExtIm32}, "PTRAPcp.L" },
1565: { MC_PMMU, {0xffff, 0xf07C|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000}, {0}, {ofNone}, "PTRAPcp" },
1566: { MC_PMMU, {0xfff0, 0xf080|(PMMU_COPROC_ID<<9)}, {2}, {ofDisp}, "PBcp.W"},
1567: { MC_PMMU, {0xfff0, 0xf0C0|(PMMU_COPROC_ID<<9)}, {4}, {ofDisp}, "PBcp.L"},
1568: { MC_PMMU, {0xffc0, 0xf100|(PMMU_COPROC_ID<<9)}, {0}, {ofEa}, "PSAVE",{EA_Dn|EA_An|EA_Anip|EA_Immed} },
1569: { MC_PMMU, {0xffc0, 0xf140|(PMMU_COPROC_ID<<9)}, {0}, {ofEa}, "PRESTORE",{EA_Dn|EA_An|EA_piAn|EA_Immed} },
1570:
1571:
1572: #define MC040_COPROC_ID 3 // 3 is the code for some 68040/68060 opcodes
1573:
1574: { MC68040|MC68060, {0xfff8, 0xf000|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAnip,ofDestAbsL}, "MOVE16"},
1575: { MC68040|MC68060, {0xfff8, 0xf008|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofDestAbsL,ofAnip}, "MOVE16"},
1576: { MC68040|MC68060, {0xfff8, 0xf010|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAni,ofDestAbsL}, "MOVE16"},
1577: { MC68040|MC68060, {0xfff8, 0xf018|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofDestAbsL,ofAni}, "MOVE16"},
1578: { MC68040|MC68060, {0xfff8, 0xf020|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAnip,ofExtAnip}, "MOVE16"},
1579:
1580:
1581: #define CPU32_COPROC_ID 4 // 4 is the code for some CPU32 opcodes
1582:
1583: { MC68040|MC68060, {0xfff8, 0xf008|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_NONE} },
1584: { MC68040|MC68060, {0xfff8, 0xf048|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_DC} },
1585: { MC68040|MC68060, {0xfff8, 0xf088|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_IC} },
1586: { MC68040|MC68060, {0xfff8, 0xf0C8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_ICDC} },
1587:
1588: { MC68040|MC68060, {0xfff8, 0xf010|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_NONE} },
1589: { MC68040|MC68060, {0xfff8, 0xf050|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_DC} },
1590: { MC68040|MC68060, {0xfff8, 0xf090|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_IC} },
1591: { MC68040|MC68060, {0xfff8, 0xf0D0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_ICDC} },
1592:
1593: { MC68040|MC68060, {0xfff8, 0xf018|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_NONE} },
1594: { MC68040|MC68060, {0xfff8, 0xf058|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_DC} },
1595: { MC68040|MC68060, {0xfff8, 0xf098|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_IC} },
1596: { MC68040|MC68060, {0xfff8, 0xf0D8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_ICDC} },
1597:
1598: { MC68040|MC68060, {0xfff8, 0xf028|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_NONE} },
1599: { MC68040|MC68060, {0xfff8, 0xf068|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_DC} },
1600: { MC68040|MC68060, {0xfff8, 0xf0A8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_IC} },
1601: { MC68040|MC68060, {0xfff8, 0xf0E8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_ICDC} },
1602:
1603: { MC68040|MC68060, {0xfff8, 0xf030|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_NONE} },
1604: { MC68040|MC68060, {0xfff8, 0xf070|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_DC} },
1605: { MC68040|MC68060, {0xfff8, 0xf0B0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_IC} },
1606: { MC68040|MC68060, {0xfff8, 0xf0F0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_ICDC} },
1607:
1608: { MC68040|MC68060, {0xfff8, 0xf038|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_NONE} },
1609: { MC68040|MC68060, {0xfff8, 0xf078|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_DC} },
1610: { MC68040|MC68060, {0xfff8, 0xf0B8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_IC} },
1611: { MC68040|MC68060, {0xfff8, 0xf0F8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_ICDC} },
1612:
1613: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f08, 0x0100}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLU.?" },
1614: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0100}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLU.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1615: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f28, 0x0500}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLUN.?" },
1616: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0500}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLUN.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1617:
1618: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f08, 0x0900}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLS.?" },
1619: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0900}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLS.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1620: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f28, 0x0D00}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLSN.?" },
1621: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0D00}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLSN.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1622:
1623: { MC_CPU32, {0xffff, 0xf000|(CPU32_COPROC_ID<<9), 0xffff, 0x01C0}, {2}, {ofI}, "LPSTOP" },
1624:
1625:
1626: #define FPU_COPROC_ID 1 // 1 is the standard FPU, required to be 1 for the 68040 anyway
1627:
1628: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0000}, {-1,16+10,3,1}, {ofFPU}, "FMOVE.?" },
1629: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0001}, {-1,16+10,3,1}, {ofFPU}, "FINT.?" },
1630: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0002}, {-1,16+10,3,1}, {ofFPU}, "FSINH.?" },
1631: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0003}, {-1,16+10,3,1}, {ofFPU}, "FINTRZ.?" },
1632: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0004}, {-1,16+10,3,1}, {ofFPU}, "FSQRT.?" },
1633: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0006}, {-1,16+10,3,1}, {ofFPU}, "FLOGNP1.?" },
1634: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0008}, {-1,16+10,3,1}, {ofFPU}, "FETOXM1.?" },
1635: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0009}, {-1,16+10,3,1}, {ofFPU}, "FTANH.?" },
1636: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000A}, {-1,16+10,3,1}, {ofFPU}, "FATAN.?" },
1637: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000C}, {-1,16+10,3,1}, {ofFPU}, "FASIN.?" },
1638: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000D}, {-1,16+10,3,1}, {ofFPU}, "FATANH.?" },
1639: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000E}, {-1,16+10,3,1}, {ofFPU}, "FSIN.?" },
1640: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000F}, {-1,16+10,3,1}, {ofFPU}, "FTAN.?" },
1641: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0010}, {-1,16+10,3,1}, {ofFPU}, "FETOX.?" },
1642: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0011}, {-1,16+10,3,1}, {ofFPU}, "FTWOTOX.?" },
1643: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0012}, {-1,16+10,3,1}, {ofFPU}, "FTENTOX.?" },
1644: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0014}, {-1,16+10,3,1}, {ofFPU}, "FLOGN.?" },
1645: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0015}, {-1,16+10,3,1}, {ofFPU}, "FLOG10.?" },
1646: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0016}, {-1,16+10,3,1}, {ofFPU}, "FLOG2.?" },
1647: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0018}, {-1,16+10,3,1}, {ofFPU}, "FABS.?" },
1648: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0019}, {-1,16+10,3,1}, {ofFPU}, "FCOSH.?" },
1649: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001A}, {-1,16+10,3,1}, {ofFPU}, "FNEG.?" },
1650: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001C}, {-1,16+10,3,1}, {ofFPU}, "FACOS.?" },
1651: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001D}, {-1,16+10,3,1}, {ofFPU}, "FCOS.?" },
1652: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001E}, {-1,16+10,3,1}, {ofFPU}, "FGETEXP.?" },
1653: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001F}, {-1,16+10,3,1}, {ofFPU}, "FGETMAN.?" },
1654: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0020}, {-1,16+10,3,1}, {ofFPU}, "FDIV.?" },
1655: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0021}, {-1,16+10,3,1}, {ofFPU}, "FMOD.?" },
1656: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0022}, {-1,16+10,3,1}, {ofFPU}, "FADD.?" },
1657: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0023}, {-1,16+10,3,1}, {ofFPU}, "FMUL.?" },
1658: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0024}, {-1,16+10,3,1}, {ofFPU}, "FSGLDIV.?" },
1659: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0025}, {-1,16+10,3,1}, {ofFPU}, "FREM.?" },
1660: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0026}, {-1,16+10,3,1}, {ofFPU}, "FSCALE.?" },
1661: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0027}, {-1,16+10,3,1}, {ofFPU}, "FSGLMUL.?" },
1662: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0028}, {-1,16+10,3,1}, {ofFPU}, "FSUB.?" },
1663: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA078,0x0030}, {-1,16+10,3,1}, {ofFPU3Reg}, "FSINCOS.?" },
1664: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0038}, {-1,16+10,3,1}, {ofFPU}, "FCMP.?" },
1665: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x003A}, {-1,16+10,3,1}, {ofFPU}, "FTST.?" },
1666: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0040}, {-1,16+10,3,1}, {ofFPU}, "FSMOVE.?" },
1667: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0041}, {-1,16+10,3,1}, {ofFPU}, "FSSQRT.?" },
1668: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0042}, {-1,16+10,3,1}, {ofFPU}, "FSADD.?" },
1669: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0044}, {-1,16+10,3,1}, {ofFPU}, "FDMOVE.?" },
1670: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0045}, {-1,16+10,3,1}, {ofFPU}, "FDSQRT.?" },
1671: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0046}, {-1,16+10,3,1}, {ofFPU}, "FDADD.?" },
1672: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0058}, {-1,16+10,3,1}, {ofFPU}, "FSABS.?" },
1673: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005A}, {-1,16+10,3,1}, {ofFPU}, "FSNEG.?" },
1674: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005C}, {-1,16+10,3,1}, {ofFPU}, "FDABS.?" },
1675: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005E}, {-1,16+10,3,1}, {ofFPU}, "FDNEG.?" },
1676: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0060}, {-1,16+10,3,1}, {ofFPU}, "FSDIV.?" },
1677: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0063}, {-1,16+10,3,1}, {ofFPU}, "FSMUL.?" },
1678: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0064}, {-1,16+10,3,1}, {ofFPU}, "FDDIV.?" },
1679: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0067}, {-1,16+10,3,1}, {ofFPU}, "FDMUL.?" },
1680: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0068}, {-1,16+10,3,1}, {ofFPU}, "FSSUB.?" },
1681: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x006C}, {-1,16+10,3,1}, {ofFPU}, "FDSUB.?" },
1682: { MC68040|MC_FPU, {0xffff, 0xf000|(FPU_COPROC_ID<<9),0xFC00,0x5C00}, {0}, {ofFMOVECR}, "FMOVECR" },
1683:
1684: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE000,0x6000}, {-1,16+10,3,1}, {ofFPUMOVE}, "FMOVE.?" },
1685:
1686: // these 3 are special versions of MOVEM with just one register, they have to be before the FMOVEM version
1687: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x8400}, {0}, {ofEa,ofSpecReg}, "FMOVE", {0,REG_FPU_FPIAR} },
1688: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x8800}, {0}, {ofEa,ofSpecReg}, "FMOVE", {EA_An,REG_FPU_FPSR} },
1689: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x9000}, {0}, {ofEa,ofSpecReg}, "FMOVE", {EA_An,REG_FPU_FPCR} },
1690: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE3FF,0x8000}, {0}, {ofEa,ofFPUSRRegList}, "FMOVEM", {EA_Dn|EA_An,0} },
1691: // these 3 are special versions of MOVEM with just one register, they have to be before the FMOVEM version
1692: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xA400}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPIAR,EA_Immed|EA_PCRel} },
1693: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xA800}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPSR,EA_An|EA_Immed|EA_PCRel} },
1694: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xB000}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPCR,EA_An|EA_Immed|EA_PCRel} },
1695: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE3FF,0xA000}, {0}, {ofFPUSRRegList,ofEa}, "FMOVEM", {0,EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1696:
1697: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE00,0xC000}, {0}, {ofFPUReglist,ofEa}, "FMOVEM.X",{0,EA_Dn|EA_An|EA_Anip|EA_Immed} },
1698: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE8F,0xC800}, {0}, {ofExtRegD04,ofEa}, "FMOVEM.X",{0,EA_Dn|EA_An|EA_piAn|EA_Immed} },
1699: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE00,0xE000}, {0}, {ofEa,ofFPUReglist}, "FMOVEM.X",{EA_Dn|EA_An|EA_piAn|EA_Immed,0} },
1700: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE8F,0xE800}, {0}, {ofEa,ofExtRegD04}, "FMOVEM.X",{EA_Dn|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1701:
1702: { MC68040|MC_FPU, {0xffc0, 0xf040|(FPU_COPROC_ID<<9),0xFFC0,0x0000}, {0}, {ofEa}, "FScf.B",{EA_An|EA_Immed|EA_PCRel} },
1703: { MC68040|MC_FPU, {0xfff8, 0xf048|(FPU_COPROC_ID<<9),0xFFC0,0x0000}, {2}, {ofDn,ofDisp}, "FDBcf" },
1704: { MC68040|MC_FPU, {0xffff, 0xf07A|(FPU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {2}, {ofExtIm32}, "FTRAPcf.W" },
1705: { MC68040|MC_FPU, {0xffff, 0xf07B|(FPU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {4}, {ofExtIm32}, "FTRAPcf.L" },
1706: { MC68040|MC_FPU, {0xffff, 0xf07C|(FPU_COPROC_ID<<9), 0xfff0, 0x0000}, {0}, {ofNone}, "FTRAPcf" },
1707:
1708: // FNOP _has_ to be before FBcf.W, not worth to have a special case for that one
1709: { MC68040|MC_FPU, {0xffff, 0xf080|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {0}, {ofNone}, "FNOP" },
1710: { MC68040|MC_FPU, {0xffc0, 0xf080|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {2}, {ofDisp}, "FBcF.W" },
1711: { MC68040|MC_FPU, {0xffc0, 0xf0c0|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {4}, {ofDisp}, "FBcF.L" },
1712: { MC68040|MC68060|MC_FPU, {0xffc0, 0xf100|(FPU_COPROC_ID<<9)}, {0}, {ofEa}, "FSAVE", {EA_Dn|EA_An|EA_piAn|EA_Immed} },
1713: { MC68040|MC68060|MC_FPU, {0xffc0, 0xf140|(FPU_COPROC_ID<<9)}, {0}, {ofEa}, "FRESTORE", {EA_Dn|EA_An|EA_piAn|EA_Immed} },
1714:
1.1.1.4 root 1715: { 0 }
1.1 root 1716: };
1717:
1718: static int Disass68k(long addr, char *labelBuffer, char *opcodeBuffer, char *operandBuffer, char *commentBuffer)
1719: {
1720: long baseAddr = addr;
1721: int val;
1.1.1.4 root 1722: int i;
1723: int count = 0;
1724: char addressLabel[256];
1725: char cmtBuffer[256];
1726: Disass68kDataType type;
1727: int index;
1728: long opcodeAddr;
1729:
1.1 root 1730: labelBuffer[0] = 0;
1731: opcodeBuffer[0] = 0;
1732: operandBuffer[0] = 0;
1733: commentBuffer[0] = 0;
1734:
1.1.1.4 root 1735: type = Disass68kType(baseAddr, addressLabel, cmtBuffer, &count);
1.1 root 1736: if(addressLabel[0])
1737: sprintf(labelBuffer, "%s:", addressLabel);
1738: sprintf(commentBuffer, "%s", cmtBuffer);
1739: switch(type)
1740: {
1.1.1.4 root 1741: case dtByte:
1742: if(count > 8)
1743: count = 8;
1744: strcpy(opcodeBuffer,"DC.B");
1745: for (i = 0; i < count; ++i)
1746: {
1747: char hbuf[16];
1748: unsigned short val;
1749:
1750: if((i & 7) > 0)
1751: strcat(operandBuffer, ",");
1752: val = Disass68kGetWord(addr+(i & ~1));
1753: if(i & 1)
1754: val &= 0xFF;
1755: else
1756: val = val >> 8;
1757: sprintf(hbuf,"$%2.2x", val);
1758: strcat(operandBuffer, hbuf);
1759: }
1760: return count;
1761:
1762: case dtWord:
1763: if(count > 4)
1764: count = 4;
1765: strcpy(opcodeBuffer,"DC.W");
1766: for (i = 0; i < count; ++i)
1767: {
1768: char hbuf[16];
1769: if((i & 3) > 0)
1770: strcat(operandBuffer, ",");
1771: sprintf(hbuf,"$%4.4x", Disass68kGetWord(addr+i*2));
1772: strcat(operandBuffer, hbuf);
1773: }
1774: return count * 2;
1775:
1776: case dtLong:
1777: if(count > 2)
1778: count = 2;
1779: strcpy(opcodeBuffer,"DC.L");
1780: for (i = 0; i < count; ++i)
1781: {
1782: char hbuf[16];
1783: if((i & 1) > 0)
1784: strcat(operandBuffer, ",");
1785: sprintf(hbuf,"$%8.8x", (Disass68kGetWord(addr+i*4) << 16) | Disass68kGetWord(addr+i*4+2));
1786: strcat(operandBuffer, hbuf);
1787: }
1788: return count * 4;
1.1 root 1789:
1790: case dtStringArray:
1.1.1.4 root 1791: {
1792: char *sp;
1793: strcpy(opcodeBuffer,"DC.B");
1794: strcat(operandBuffer, "'");
1795: sp = operandBuffer + strlen(operandBuffer);
1796: for (i = 0; i < count; ++i)
1797: {
1798: unsigned short val = Disass68kGetWord(addr+(i & ~1));
1799: if(i & 1)
1800: val &= 0xFF;
1801: else
1802: val = val >> 8;
1803: if(val == 0)
1804: break;
1805: switch(val)
1806: {
1807: case 9: *sp++ = '\\'; *sp++ = 't'; break;
1808: case 10: *sp++ = '\\'; *sp++ = 'n'; break;
1809: case 13: *sp++ = '\\'; *sp++ = 'r'; break;
1810: default:
1811: if(val >= 0x20 && val <= 0x7E)
1812: *sp++ = val;
1813: }
1814: }
1815: *sp = 0;
1816: strcat(sp, "'");
1817: return count;
1818: }
1.1 root 1819:
1820: case dtASCString:
1.1.1.4 root 1821: {
1822: int count = 1;
1823: unsigned short val = Disass68kGetWord(addr+0);
1824: strcpy(opcodeBuffer,"DC.B");
1825: if((val >> 8) == 0)
1826: {
1827: strcat(operandBuffer, "0");
1828: } else {
1829: char *sp;
1830: strcat(operandBuffer, "'");
1831: sp = operandBuffer + strlen(operandBuffer);
1832: for(i=0; ; ++i)
1833: {
1834: unsigned short val = Disass68kGetWord(addr+(i & ~1));
1835: if(i & 1)
1836: val &= 0xFF;
1837: else
1838: val = val >> 8;
1839: if(val == 0)
1840: break;
1841: switch(val)
1.1 root 1842: {
1.1.1.4 root 1843: case 9: *sp++ = '\\'; *sp++ = 't'; break;
1844: case 10: *sp++ = '\\'; *sp++ = 'n'; break;
1845: case 13: *sp++ = '\\'; *sp++ = 'r'; break;
1846: default:
1847: if(val >= 0x20 && val <= 0x7E)
1848: *sp++ = val;
1.1 root 1849: }
1.1.1.4 root 1850: ++count;
1851: }
1852: *sp = 0;
1853: strcat(sp, "',0");
1854: }
1855: return (count + 1) & ~1;
1856: }
1.1 root 1857:
1858: case dtPointer:
1859: case dtFunctionPointer:
1.1.1.4 root 1860: {
1861: const char *sp;
1862: val = (Disass68kGetWord(addr) << 16) | Disass68kGetWord(addr+2);
1863: sp = Disass68kSymbolName(val, 2);
1864: strcpy(opcodeBuffer,"DC.L");
1865: if(sp)
1866: sprintf(operandBuffer,"%s", sp);
1867: else
1868: sprintf(operandBuffer,"$%6.6x", val);
1869: return 4;
1870: }
1.1 root 1871:
1872: default: break;
1873: }
1874:
1.1.1.4 root 1875: index = 0;
1876: opcodeAddr = addr;
1.1 root 1877: more:
1878: addr = opcodeAddr;
1879:
1880: opcodeBuffer[0] = 0;
1881: operandBuffer[0] = 0;
1882:
1883: commentBuffer[0] = 0;
1884: if(cmtBuffer[0])
1885: sprintf(commentBuffer, "%s ", cmtBuffer);
1886:
1887: while(1)
1888: {
1.1.1.4 root 1889: unsigned short opcode[5];
1890: unsigned int i;
1.1 root 1891: OpcodeTableStruct *ots = &OpcodeTable[index++];
1.1.1.4 root 1892: int size;
1893: char sizeChar = 0;
1894: char *dbuf;
1895: int ea;
1.1.1.5 ! root 1896: unsigned int maxop;
1.1.1.4 root 1897:
1.1 root 1898: if(ots->opcodeName == NULL)
1899: break;
1900: if((ots->cpuMask & optionCPUTypeMask) == 0) // CPU doesn't match?
1901: continue;
1902:
1903: // search for the opcode plus up to 2 extension words
1904: for(i=0; i<5; ++i)
1905: {
1906: if(!ots->opcodeMask[i*2])
1.1.1.4 root 1907: {
1908: opcode[i] = 0;
1.1 root 1909: break;
1.1.1.4 root 1910: }
1.1 root 1911: opcode[i] = Disass68kGetWord(addr);
1912: if(((ots->opcodeMask[i*2] & 0xFFFF) & opcode[i]) != ots->opcodeMask[i*2+1])
1913: goto more;
1914: addr += 2;
1915: }
1916:
1917: // find out the size of the opcode operand
1.1.1.4 root 1918: size = ots->operationSize[0];
1.1 root 1919: if(size < 0) // custom size?
1920: {
1921: int opcodeOffset = ots->operationSize[1] >> 4;
1922: int bitShiftOffset = ots->operationSize[1] & 0x0F;
1923: int sizeBitMask = (opcode[opcodeOffset] >> bitShiftOffset) & ((1 << ots->operationSize[2]) - 1);
1924: switch(ots->operationSize[3])
1925: {
1926: case 0: // 2 Bit Size
1927: switch(sizeBitMask)
1928: {
1929: case 0: size = 1; sizeChar = 'B'; break;
1930: case 1: size = 2; sizeChar = 'W'; break;
1931: case 2: size = 4; sizeChar = 'L'; break;
1932: case 3: goto more; // illegal size mask
1933: }
1934: break;
1935: case 1: // 3 Bit FPU Size
1936: if((opcode[1] & 0x4000) == 0x0000) // Register => Register?
1937: sizeBitMask = 2; // => 'X' Format
1938: switch(sizeBitMask)
1939: {
1940: case 0: size = 4; sizeChar = 'L'; break;
1941: case 1: size = 4; sizeChar = 'S'; break;
1942: case 2: size = 12; sizeChar = 'X'; break;
1943: case 7: if((opcode[1] & 0xE000) != 0x6000) // MOVE.P <ea>,FPn{Dn-Factor}
1944: goto more; // illegal size mask
1945: case 3: size = 12; sizeChar = 'P'; break;
1946: case 4: size = 2; sizeChar = 'W'; break;
1947: case 5: size = 8; sizeChar = 'D'; break;
1948: case 6: size = 1; sizeChar = 'B'; break;
1949: }
1950: break;
1951: }
1952: }
1953:
1954: // copy the opcode plus a necessary TAB for the operand
1.1.1.4 root 1955: dbuf = opcodeBuffer;
1.1 root 1956: for(i=0; ots->opcodeName[i]; ++i)
1957: {
1958: char c = ots->opcodeName[i];
1959: if(c == 'c') // condition code
1960: {
1961: static const char *pmmuCond[16] = { "BS", "BC", "LS", "LC", "SS", "SC", "AS", "AC", "WS", "WC", "IS", "IC", "GS", "GC", "CS", "CC" };
1962: static const char *braCond[16] = { "RA", "SR", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1963: static const char *sccCond[16] = { "T", "F", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1964: static const char *dbCond[16] = { "T", "RA", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1965: static const char *fpuCond[64] = { "F", "EQ", "OGT", "OGE", "OLT", "OLE", "OGL", "OR", "UN", "UEQ", "UGT", "UGE", "ULT", "ULE", "NE", "T", "SF", "SEQ", "GT", "GE", "LT", "LE", "GL", "GLE", "NGLE", "NGL", "NLE", "NLT", "NGE", "NGT", "SNE", "ST" };
1.1.1.4 root 1966: char buf[8];
1.1 root 1967:
1968: const char *sp = NULL;
1969: switch(ots->opcodeName[++i])
1970: {
1971: case 'p': // PMMU conditions
1972: sp = pmmuCond[opcode[1] & 0xF];
1973: break;
1974: case 'b': // BRA conditions
1975: sp = braCond[(opcode[0] >> 8) & 0xF];
1976: break;
1977: case 'i': // Scc,TRAPcc conditions
1978: sp = sccCond[(opcode[0] >> 8) & 0xF];
1979: break;
1980: case 'd': // DBcc conditions
1981: sp = dbCond[(opcode[0] >> 8) & 0xF];
1982: break;
1983: case 'F': // FPU conditions (first word)
1984: sp = fpuCond[opcode[0] & 0x3F];
1985: break;
1986: case 'f': // FPU conditions (second word)
1987: sp = fpuCond[opcode[1] & 0x3F];
1988: break;
1989: }
1990: if(sp)
1991: {
1992: if(options & doptOpcodesSmall)
1993: {
1.1.1.4 root 1994: char *bp;
1.1 root 1995: strcpy(buf, sp);
1996: sp = buf;
1.1.1.4 root 1997: for (bp = buf; *bp; ++bp)
1.1.1.5 ! root 1998: *bp = tolower((unsigned char)*bp);
1.1 root 1999: }
2000: strcpy(dbuf, sp);
2001: dbuf += strlen(sp);
2002: continue;
2003: }
2004: goto more;
2005: }
2006: if(c == '?') // size mask
2007: c = sizeChar;
2008: if(options & doptOpcodesSmall)
1.1.1.5 ! root 2009: c = tolower((unsigned char)c);
1.1 root 2010: *dbuf++ = c;
2011: }
2012: *dbuf = 0;
2013:
2014: // Parse the EAs for all operands
1.1.1.4 root 2015: ea = opcode[0] & 0x3F;
1.1 root 2016: dbuf = operandBuffer;
1.1.1.5 ! root 2017:
! 2018: maxop=(sizeof(ots->op)/sizeof(ots->op[0]));
! 2019: for(i=0; i<maxop; ++i)
1.1 root 2020: {
1.1.1.4 root 2021: int reg;
2022:
1.1 root 2023: switch(ots->op[i])
2024: {
2025: case ofNone: // nothing
2026: break;
2027:
2028: case ofEa:
2029: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, EA_All & ~(ots->parameter[i]), 0, ots->disassFlag);
2030: break;
2031:
2032: case ofDn:
2033: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2034: break;
2035: case ofAn:
2036: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x08, size, EA_An, 0, ots->disassFlag);
2037: break;
2038: case ofAni:
2039: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x10, size, EA_Ani, 0, ots->disassFlag);
2040: break;
2041: case ofAnip:
2042: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2043: break;
2044: case ofPiAn:
2045: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x20, size, EA_piAn, 0, ots->disassFlag);
2046: break;
2047: case ofD16An:
2048: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x28, size, EA_dAn, 0, ots->disassFlag);
2049: break;
2050:
2051: case ofI:
2052: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x3C, size, EA_Immed, 0, ots->disassFlag);
2053: break;
2054:
2055: case ofDestDn:
2056: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2057: break;
2058: case ofDestAn:
2059: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x08, size, EA_An, 0, ots->disassFlag);
2060: break;
2061: case ofDestAnip:
2062: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2063: break;
2064: case ofDestPiAn:
2065: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x20, size, EA_piAn, 0, ots->disassFlag);
2066: break;
2067: case ofDestEa6:
2068: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | (((opcode[0] >> 6) & 0x7) << 3), size, EA_Dest-EA_An, 0, ots->disassFlag);
2069: break;
2070: case ofDestAbsL:
2071: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x39, size, EA_Abs, 0, ots->disassFlag);
2072: break;
2073:
2074: case ofIOpcode:
2075: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, opcode[0] & ots->parameter[i], ots->disassFlag);
2076: break;
2077: case ofI3:
2078: val = ((opcode[0] >> 9) & 7);
2079: if(!val) val = 8;
2080: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, val, ots->disassFlag);
2081: break;
2082: case ofExtIm:
2083: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, opcode[1], ots->disassFlag);
2084: break;
2085: case ofExtIm32:
2086: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, size, EA_ImmedParameter, opcode[2], ots->disassFlag);
2087: break;
2088: case ofExtIm4:
2089: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, opcode[1] & 0x0F, ots->disassFlag);
2090: break;
2091: case ofExtIm10:
2092: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, (opcode[1] >> 10) & 0x07, ots->disassFlag);
2093: break;
2094: case ofSpecReg:
2095: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0101, size, EA_SpecialRegister, ots->parameter[i], ots->disassFlag);
2096: break;
2097: case ofSpecExtReg:
2098: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0101, size, EA_SpecialRegister, opcode[1] & 0xFFF, ots->disassFlag);
2099: break;
2100: case ofExtReg0:
2101: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2102: break;
2103: case ofExtRegA0:
2104: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07) | 0x08, size, EA_An, 0, ots->disassFlag);
2105: break;
2106: case ofExtRegD04:
2107: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 4) & 0x07) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2108: break;
2109: case ofExtRegA05:
2110: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 5) & 0x07) | 0x08, size, EA_An, 0, ots->disassFlag);
2111: break;
2112: case ofExtReg:
2113: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2114: break;
2115: case ofExtAnip:
2116: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2117: break;
2118:
2119: case ofDisp:
2120: // branch treats the displacement 0x00 and 0xFF as an indicator how many words follow
2121: // This test will decline a displacement with the wrong word offset
2122: if((opcode[0] & 0xF000) == 0x6000)
2123: {
2124: val = opcode[0] & 0xFF;
2125: if(val == 0x00 && size != 2) goto more;
2126: if(val == 0xFF && size != 4) goto more;
2127: }
2128: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0102, size, EA_PCDisplacement, opcode[0] & 0xFF, ots->disassFlag);
2129: break;
2130:
2131: case ofRegList:
2132: val = opcode[1];
2133: if((ea & 0x38) == 0x20) // -(An) has a flipped bitmask
2134: val = Disass68kFlipBits(val);
2135: dbuf = Disass68kReglist(dbuf, val);
2136: break;
2137:
2138: case ofFPU:
2139: { // default FPU opcode modes
2140: int src = (opcode[1] >> 10) & 7;
2141: int dest = (opcode[1] >> 7) & 7;
2142: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2143: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2144: if(opcode[1] & 0x4000)
2145: {
2146: // <ea>,FPn
2147: int mask = EA_All - EA_An;
2148: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2149: mask -= EA_Dn;
2150: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2151: if(!dbuf) goto more;
2152: *dbuf++ = ',';
2153: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2154: *dbuf = 0;
2155: } else {
2156: // FPn,FPn or FPn
2157:
2158: // <ea> has to be 0
2159: if((opcode[0] & 0x3F) != 0) goto more;
2160:
2161: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+src;
2162: if(src != dest)
2163: {
2164: *dbuf++ = ',';
2165: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2166: }
2167: *dbuf = 0;
2168: }
2169: }
2170: break;
2171: case ofFPUMOVE:
2172: { // MOVE <ea>,FPn{k-Factor}
2173: int src = (opcode[1] >> 10) & 7;
2174: // <ea>,FPn
2175: int mask = EA_All - EA_An;
2176: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2177: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2178: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2179: mask -= EA_Dn;
2180: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2181: if(!dbuf) goto more;
2182: *dbuf++ = ',';
2183: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+((opcode[1] >> 7) & 7);
2184: if(src == 3)
2185: {
2186: int kFactor = opcode[1] & 0x7F;
2187: if(kFactor & 0x40)
2188: kFactor |= 0x80;
2189: *dbuf++ = '{';
2190: sprintf(dbuf, "%d", (signed char)kFactor);
2191: dbuf += strlen(dbuf);
2192: *dbuf++ = '}';
2193: } else if(src == 7)
2194: {
2195: if((opcode[1] & 0x0F) != 0) goto more;
2196: *dbuf++ = '{';
2197: *dbuf++ = options & doptRegisterSmall ? 'd' : 'D';
2198: *dbuf++ = '0' + ((opcode[1] >> 4) & 7);
2199: *dbuf++ = '}';
2200: } else {
2201: if((opcode[1] & 0x7F) != 0) goto more;
2202: }
2203: *dbuf = 0;
2204: }
2205: break;
2206: case ofFMOVECR:
2207: { // MOVECR #const,FPn
2208: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2209: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2210: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, opcode[1] & 0x7F, ots->disassFlag);
2211: if(!dbuf) goto more;
1.1.1.4 root 2212: reg = (opcode[1] >> 7) & 7;
1.1 root 2213: *dbuf++ = ',';
2214: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+reg;
2215: *dbuf = 0;
2216: switch(opcode[1] & 0x7F) // document the well-known constants
2217: {
2218: case 0x00: strcat(commentBuffer, "PI"); break;
2219: case 0x0B: strcat(commentBuffer, "Log10(2)"); break;
2220: case 0x0C: strcat(commentBuffer, "e"); break;
2221: case 0x0D: strcat(commentBuffer, "Log2(e)"); break;
2222: case 0x0E: strcat(commentBuffer, "Log10(e)"); break;
2223: case 0x0F: strcat(commentBuffer, "0.0"); break;
2224: case 0x30: strcat(commentBuffer, "1n(2)"); break;
2225: case 0x31: strcat(commentBuffer, "1n(10)"); break;
2226: case 0x32: strcat(commentBuffer, "100"); break;
2227: case 0x33: strcat(commentBuffer, "10^1"); break;
2228: case 0x34: strcat(commentBuffer, "10^2"); break;
2229: case 0x35: strcat(commentBuffer, "10^4"); break;
2230: case 0x36: strcat(commentBuffer, "10^8"); break;
2231: case 0x37: strcat(commentBuffer, "10^16"); break;
2232: case 0x38: strcat(commentBuffer, "10^32"); break;
2233: case 0x39: strcat(commentBuffer, "10^64"); break;
2234: case 0x3A: strcat(commentBuffer, "10^128"); break;
2235: case 0x3B: strcat(commentBuffer, "10^256"); break;
2236: case 0x3C: strcat(commentBuffer, "10^512"); break;
2237: case 0x3D: strcat(commentBuffer, "10^1024"); break;
2238: case 0x3E: strcat(commentBuffer, "10^2048"); break;
2239: case 0x3F: strcat(commentBuffer, "10^4096"); break;
2240: }
2241: }
2242: break;
2243: case ofFPUSRRegList:
2244: {
2245: int hasReg = 0;
2246: *dbuf = 0;
2247: if(opcode[1] & 0x0400)
2248: {
2249: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPIAR));
2250: hasReg = 1;
2251: }
2252: if(opcode[1] & 0x0800)
2253: {
2254: if(hasReg) strcat(dbuf, "/");
2255: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPSR));
2256: hasReg = 1;
2257: }
2258: if(opcode[1] & 0x1000)
2259: {
2260: if(hasReg) strcat(dbuf, "/");
2261: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPCR));
2262: hasReg = 1;
2263: }
2264: if(!hasReg)
2265: strcat(dbuf, "0");
2266: dbuf += strlen(dbuf);
2267: }
2268: break;
2269: case ofFPUReglist: // FMOVEM
2270: {
2271: int mask = opcode[1] & 0xFF;
2272: if(opcode[1] & 0x0100)
2273: mask = Disass68kFlipBits(mask) >> 8;
2274: dbuf = Disass68kFPUReglist(dbuf, mask);
2275: }
2276: break;
2277: case ofFPU3Reg:
2278: { // FSINCOS
2279: int src = (opcode[1] >> 10) & 7;
2280: int dest = (opcode[1] >> 7) & 7;
2281: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2282: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2283: if(opcode[1] & 0x4000)
2284: {
2285: // <ea>,FPn
2286: int mask = EA_All - EA_An;
2287: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2288: mask -= EA_Dn;
2289: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2290: if(!dbuf) goto more;
2291: *dbuf++ = ',';
2292: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+(opcode[1] & 7);
2293: *dbuf++ = ',';
2294: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2295: *dbuf = 0;
2296: } else {
2297: // FPn,FPn or FPn
2298:
2299: // <ea> has to be 0
2300: if((opcode[0] & 0x3F) != 0) goto more;
2301:
2302: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+src;
2303: *dbuf++ = ',';
2304: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+(opcode[1] & 7);
2305: *dbuf++ = ',';
2306: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2307: *dbuf = 0;
2308: }
2309: }
2310: break;
2311:
2312: case ofCAS:
2313: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2314: if(!dbuf) goto more;
2315: *dbuf++ = ',';
2316: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2317: break;
2318: case ofCAS2:
2319: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2320: if(!dbuf) goto more;
2321: *dbuf++ = ':';
2322: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[2] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2323: if(!dbuf) goto more;
2324: *dbuf++ = ',';
2325: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2326: if(!dbuf) goto more;
2327: *dbuf++ = ':';
2328: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[2] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2329: if(!dbuf) goto more;
2330: *dbuf++ = ',';
2331: *dbuf++ = '(';
2332: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2333: if(!dbuf) goto more;
2334: *dbuf++ = ')';
2335: *dbuf++ = ':';
2336: *dbuf++ = '(';
2337: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[2] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2338: if(!dbuf) goto more;
2339: *dbuf++ = ')';
2340: *dbuf = 0;
2341: break;
2342: case ofExt4Dn:
2343: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[0] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2344: if(!dbuf) goto more;
2345: *dbuf++ = ':';
2346: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2347: if(!dbuf) goto more;
2348: *dbuf++ = ',';
2349: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2350: if(!dbuf) goto more;
2351: *dbuf = 0;
2352: break;
2353: case ofBFEa:
2354: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, EA_All & ~(ots->parameter[i]), 0, ots->disassFlag);
2355: if(!dbuf) goto more;
2356: *dbuf++ = '{';
2357: val = (opcode[1] >> 6) & 0x1F;
2358: if(opcode[1] & 0x0800)
2359: {
2360: if(val & 0x18) goto more;
2361: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, val & 0x07, 1, EA_Dn, val, ots->disassFlag);
2362: } else {
2363: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0103, 1, EA_ValueParameter, val, ots->disassFlag);
2364: }
2365: *dbuf++ = ':';
2366: val = opcode[1] & 0x1F;
2367: if(opcode[1] & 0x0020)
2368: {
2369: if(val & 0x18) goto more;
2370: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, val & 0x07, 1, EA_Dn, val, ots->disassFlag);
2371: } else {
2372: if(val == 0) val = 32;
2373: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0103, 1, EA_ValueParameter, val, ots->disassFlag);
2374: }
2375: *dbuf++ = '}';
2376: *dbuf = 0;
2377: break;
2378: case ofLineA:
2379: {
2380: int lineAVal = opcode[0] & 0xFFF;
2381: const char *lineAStr[16] = { "Line-A Initialization",
2382: "Put pixel",
2383: "Get pixel",
2384: "Arbitrary line",
2385: "Horizontal line",
2386: "Filled rectangle",
2387: "Filled polygon",
2388: "Bit block transfer",
2389: "Text block transfer",
2390: "Show mouse",
2391: "Hide mouse",
2392: "Transform mouse",
2393: "Undraw sprite",
2394: "Draw sprite",
2395: "Copy raster form",
2396: "Seedfill"
2397: };
1.1.1.4 root 2398: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, lineAVal, ots->disassFlag);
1.1 root 2399: if(lineAVal < 16)
2400: strcat(commentBuffer, lineAStr[lineAVal]);
2401: }
2402: break;
2403:
2404: default:
2405: goto more;
2406: }
2407: if(!dbuf) goto more;
2408:
2409: // does another operand follow => add separator
1.1.1.5 ! root 2410: if ( (i+1<maxop) && ( ots->op[i+1] != ofNone) )
1.1 root 2411: *dbuf++ = ',';
2412: }
2413: return addr-baseAddr;
2414: }
2415:
2416: // unknown opcode
2417: strcpy(opcodeBuffer, "DC.W");
2418: sprintf(operandBuffer,"$%4.4x", Disass68kGetWord(addr));
2419: return 2;
2420: }
2421:
2422: static void Disass68kComposeStr(char *dbuf, const char *str, int position, int maxPos)
2423: {
2424: int i;
2425: int len = strlen(dbuf);
2426: while(len < position) {
2427: dbuf[len++] = ' '; /* Will give harmless warning from GCC */
2428: }
2429: for(i=0; str[i] && (!maxPos || len+i<maxPos); ++i)
2430: dbuf[len+i] = str[i];
2431: if(str[i])
2432: dbuf[len+i-1] = '+';
2433: dbuf[len+i] = 0;
2434: }
2435:
2436: static void Disass68k_loop (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
2437: {
2438: static bool isInit = false;
2439: if(!isInit)
2440: {
2441: Disass68kInit(Paths_GetHatariHome());
2442: isInit = true;
2443: }
2444:
1.1.1.4 root 2445: while (cnt-- > 0) {
2446: const int addrWidth = 6; // 6 on an ST, 8 on a TT
1.1 root 2447: char lineBuffer[1024];
2448:
2449: char addressBuffer[32];
2450: char hexdumpBuffer[256];
2451: char labelBuffer[256];
2452: char opcodeBuffer[64];
2453: char operandBuffer[256];
2454: char commentBuffer[256];
1.1.1.4 root 2455: int plen, len, j;
2456:
2457: len = Disass68k(addr, labelBuffer, opcodeBuffer, operandBuffer, commentBuffer);
1.1 root 2458: if(!len) break;
2459:
2460: sprintf(addressBuffer, "$%*.*x :", addrWidth,addrWidth, addr);
2461:
2462: hexdumpBuffer[0] = 0;
1.1.1.4 root 2463: plen = len;
1.1 root 2464: if(plen > 80 && (!strncmp(opcodeBuffer, "DC.", 3) || !strncmp(opcodeBuffer, "dc.", 3)))
2465: plen = ((optionPosLabel - optionPosHexdump) / 5) * 2;
1.1.1.4 root 2466:
1.1 root 2467: for(j=0; j<plen; j += 2)
2468: {
2469: if(j > 0)
2470: strcat(hexdumpBuffer, " ");
2471: if(j + 2 > plen)
2472: {
2473: sprintf(hexdumpBuffer+strlen(hexdumpBuffer), "%2.2x", Disass68kGetWord(addr+j) >> 8);
2474: } else {
2475: sprintf(hexdumpBuffer+strlen(hexdumpBuffer), "%4.4x", Disass68kGetWord(addr+j));
2476: }
2477: }
2478:
2479: lineBuffer[0] = 0;
2480: if(optionPosAddress >= 0)
2481: Disass68kComposeStr(lineBuffer, addressBuffer, optionPosAddress, 0);
2482: if(optionPosHexdump >= 0)
2483: Disass68kComposeStr(lineBuffer, hexdumpBuffer, optionPosHexdump, optionPosLabel);
2484: if(optionPosLabel >= 0)
2485: Disass68kComposeStr(lineBuffer, labelBuffer, optionPosLabel, 0);
2486: if(optionPosOpcode >= 0)
2487: Disass68kComposeStr(lineBuffer, opcodeBuffer, optionPosOpcode, 0);
2488: if(optionPosOperand >= 0)
2489: {
2490: size_t l = strlen(lineBuffer);
2491: if(lineBuffer[l-1] != ' ') // force at least one space between opcode and operand
2492: {
2493: lineBuffer[l++] = ' ';
2494: lineBuffer[l] = 0;
2495: }
2496: Disass68kComposeStr(lineBuffer, operandBuffer, optionPosOperand, 0);
2497: }
1.1.1.4 root 2498: if (optionPosComment >= 0)
1.1.1.3 root 2499: {
1.1.1.4 root 2500: float percentage;
2501: Uint32 count, cycles, misses;
2502: if (Profile_CpuAddressData(addr, &percentage, &count, &cycles, &misses))
1.1.1.3 root 2503: {
1.1.1.4 root 2504: sprintf(commentBuffer, "%5.2f%% (%u, %u, %u)", percentage, count, cycles, misses);
1.1.1.3 root 2505: Disass68kComposeStr(lineBuffer, commentBuffer, optionPosComment+1, 0);
2506: }
1.1.1.4 root 2507: /* show comments only if profile data is missing */
2508: else if (commentBuffer[0])
2509: {
2510: Disass68kComposeStr(lineBuffer, " ;", optionPosComment, 0);
2511: Disass68kComposeStr(lineBuffer, commentBuffer, optionPosComment+3, 0);
2512: }
1.1.1.3 root 2513: }
1.1.1.4 root 2514: addr += len;
2515: if (f)
2516: fprintf(f, "%s\n", lineBuffer);
1.1 root 2517: // if(strstr(opcodeBuffer, "RTS") || strstr(opcodeBuffer, "RTE") || strstr(opcodeBuffer, "JMP")
2518: // || strstr(opcodeBuffer, "rts") || strstr(opcodeBuffer, "rte") || strstr(opcodeBuffer, "jmp"))
2519: // fprintf(f, "\n");
2520: }
2521: if (nextpc)
2522: *nextpc = addr;
2523: }
2524:
2525:
1.1.1.4 root 2526: /**
2527: * Calculate next PC address from given one, without output
2528: * @return next PC address
1.1 root 2529: */
1.1.1.4 root 2530: Uint32 Disasm_GetNextPC(Uint32 pc)
2531: {
2532: uaecptr nextpc;
2533: Disass68k_loop (NULL, pc, &nextpc, 1);
2534: return nextpc;
2535: }
1.1 root 2536:
1.1.1.4 root 2537: /**
2538: * Call disassembly using the selected disassembly method,
2539: * either internal UAE one, or the stand alone disassembler above,
2540: * whichever is selected in Hatari configuration
2541: */
2542: void Disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1.1 root 2543: {
1.1.1.4 root 2544: if (ConfigureParams.Debugger.bDisasmUAE)
1.1.1.5 ! root 2545: m68k_disasm (f, addr, nextpc, cnt);
1.1.1.4 root 2546: else
1.1.1.5 ! root 2547: Disass68k_loop (f, addr, nextpc, cnt);
1.1 root 2548: }
2549:
1.1.1.4 root 2550: static void Disasm_CheckOptionEngine(void)
2551: {
2552: if (ConfigureParams.Debugger.bDisasmUAE)
2553: fputs("WARNING: disassembly options are supported only for '--disasm ext'!\n", stderr);
2554: }
2555:
2556: /**
2557: * query disassembly output column positions.
2558: */
2559: void Disasm_GetColumns(int *pos)
2560: {
2561: pos[DISASM_COLUMN_ADDRESS] = optionPosAddress;
2562: pos[DISASM_COLUMN_HEXDUMP] = optionPosHexdump;
2563: pos[DISASM_COLUMN_LABEL] = optionPosLabel;
2564: pos[DISASM_COLUMN_OPCODE] = optionPosOpcode;
2565: pos[DISASM_COLUMN_OPERAND] = optionPosOperand;
2566: pos[DISASM_COLUMN_COMMENT] = optionPosComment;
2567: }
2568:
2569: /**
2570: * set disassembly output column positions.
2571: */
2572: void Disasm_SetColumns(int *pos)
2573: {
2574: Disasm_CheckOptionEngine();
2575: optionPosAddress = pos[DISASM_COLUMN_ADDRESS];
2576: optionPosHexdump = pos[DISASM_COLUMN_HEXDUMP];
2577: optionPosLabel = pos[DISASM_COLUMN_LABEL];
2578: optionPosOpcode = pos[DISASM_COLUMN_OPCODE];
2579: optionPosOperand = pos[DISASM_COLUMN_OPERAND];
2580: optionPosComment = pos[DISASM_COLUMN_COMMENT];
2581: }
2582:
2583: /**
2584: * function to disable given disassembly output 'column'.
2585: * input is current column positions in 'oldcols' array and
2586: * output is new column positions/values in 'newcols' array.
2587: * It's safe to use same array for both.
2588: */
2589: void Disasm_DisableColumn(int column, int *oldcols, int *newcols)
2590: {
2591: int i, diff = 0;
2592:
2593: assert(column >= 0 && column < DISASM_COLUMNS);
2594: if (column+1 < DISASM_COLUMNS)
2595: diff = oldcols[column+1] - oldcols[column];
2596:
2597: for (i = 0; i < DISASM_COLUMNS; i++)
2598: {
2599: if (i && oldcols[i-1] > oldcols[i])
2600: {
2601: printf("WARNING: disassembly columns aren't in the expected order!\n");
2602: return;
2603: }
2604: if (i < column)
2605: newcols[i] = oldcols[i];
2606: else if (i > column)
2607: newcols[i] = oldcols[i] - diff;
2608: else
2609: newcols[column] = DISASM_COLUMN_DISABLE;
2610: }
2611: }
2612:
2613: /**
2614: * Get current disassembly output option flags
2615: * @return current output flags
2616: */
2617: int Disasm_GetOptions(void)
2618: {
2619: return options;
2620: }
2621:
2622: /**
2623: * Parse disasm command line option argument
2624: * @return error string (""=silent 'error') or NULL for success.
2625: */
2626: const char *Disasm_ParseOption(const char *arg)
2627: {
2628: if (strcasecmp(arg, "help") == 0)
2629: {
2630: const struct {
2631: int flag;
2632: const char *desc;
2633: } option[] = {
2634: { doptNoBrackets, "no brackets around absolute addressing" },
2635: { doptOpcodesSmall, "opcodes in small letters" },
2636: { doptRegisterSmall, "register names in small letters" },
2637: { doptStackSP, "stack pointer as 'SP', not 'A7'" },
2638: { 0, NULL }
2639: };
2640: int i;
2641: fputs("Disassembly settings:\n"
2642: "\tuae - use CPU core internal disassembler which has better\n"
2643: "\t instruction support\n"
2644: "\text - use external disassembler which has nicer output\n"
2645: "\t and supports options below\n"
2646: "\t<bitmask> - disassembly output option flags\n"
2647: "Flag values:\n", stderr);
2648: for (i = 0; option[i].desc; i++) {
2649: assert(option[i].flag == (1 << i));
2650: fprintf(stderr, "\t%d: %s\n", option[i].flag, option[i].desc);
2651: }
2652: fprintf(stderr, "Current settings are:\n\t--disasm %s --disasm %d\n",
2653: ConfigureParams.Debugger.bDisasmUAE ? "uae" : "ext",
2654: ConfigureParams.Debugger.nDisasmOptions);
2655: return "";
2656: }
2657: if (strcasecmp(arg, "uae") == 0)
2658: {
2659: fputs("Selected UAE CPU core internal disassembler.\n", stderr);
2660: ConfigureParams.Debugger.bDisasmUAE = true;
2661: return NULL;
2662: }
2663: if (strcasecmp(arg, "ext") == 0)
2664: {
2665: fputs("Selected external disassembler.\n", stderr);
2666: fprintf(stderr, "Disassembly output flags are %d.\n", options);
2667: ConfigureParams.Debugger.bDisasmUAE = false;
2668: return NULL;
2669: }
1.1.1.5 ! root 2670: if (isdigit((unsigned char)*arg))
1.1.1.4 root 2671: {
2672: int newopt = atoi(arg);
2673: if ((newopt|optionsMask) != optionsMask)
2674: {
2675: return "unknown flags in the bitmask";
2676: }
2677: fprintf(stderr, "Changed CPU disassembly output flags from %d to %d.\n", options, newopt);
2678: ConfigureParams.Debugger.nDisasmOptions = options = newopt;
2679: Disasm_CheckOptionEngine();
2680: return NULL;
2681: }
2682: return "invalid disasm option";
2683: }
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