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1.1 root 1: /***
2: * 68k disassembler, written 2010 by Markus Fritze, www.sarnau.com
3: *
1.1.1.4 root 4: * This file is distributed under the GNU General Public License, version 2
5: * or at your option any later version. Read the file gpl.txt for details.
1.1 root 6: ***/
7:
8: #include <stdio.h>
9: #include <ctype.h>
10: #include <strings.h>
11: #include <stdlib.h>
12:
13: #include "config.h"
14: #include "sysdeps.h"
15: #include "main.h"
1.1.1.4 root 16: #include "configuration.h"
1.1 root 17: #include "newcpu.h"
1.1.1.6 ! root 18: #ifdef WINUAE_FOR_HATARI
! 19: #include "debug.h"
! 20: #endif
1.1 root 21: #include "paths.h"
1.1.1.3 root 22: #include "profile.h"
1.1 root 23: #include "tos.h"
24: #include "68kDisass.h"
25:
26: #define ADDRESS_ON_PC 1
27: #define USE_SYMBOLS 1
28:
29: typedef enum {
30: doptNoBrackets = 1, // hide brackets around absolute addressing
31: doptOpcodesSmall = 2, // opcodes are small letters
32: doptRegisterSmall = 4, // register names are small letters
1.1.1.5 root 33: doptStackSP = 8 // stack pointer is named "SP" instead of "A7" (except for MOVEM)
1.1 root 34: } Diss68kOptions;
35:
36: static Diss68kOptions options = doptOpcodesSmall | doptRegisterSmall | doptStackSP | doptNoBrackets;
37:
1.1.1.4 root 38: /* all options */
39: static const Diss68kOptions optionsMask = doptOpcodesSmall | doptRegisterSmall | doptStackSP | doptNoBrackets;
40:
1.1 root 41: // values <0 will hide the group
1.1.1.4 root 42: static int optionPosAddress = 0; // current address
1.1.1.6 ! root 43: static int optionPosHexdump = 12; // 16-bit words at this address
1.1.1.4 root 44: static int optionPosLabel = 35; // label, if defined
45: static int optionPosOpcode = 47; // opcode
46: static int optionPosOperand = 57; // operands for the opcode
47: static int optionPosComment = 82; // comment, if defined
1.1 root 48:
49: /***
50: * Motorola 16-/32-Bit Microprocessor and coprocessor types
51: ***/
52: #define MC68000 0x000001 // 16-/32-Bit Microprocessor
53: #define MC68EC000 0x000002 // 16-/32-Bit Embedded Controller
54: #define MC68HC000 0x000004 // Low Power 16-/32-Bit Microprocessor
55: #define MC68008 0x000008 // 16-Bit Microprocessor with 8-Bit Data Bus
56: #define MC68010 0x000010 // 16-/32-Bit Virtual Memory Microprocessor
57: #define MC68020 0x000020 // 32-Bit Virtual Memory Microprocessor
58: #define MC68EC020 0x000040 // 32-Bit Embedded Controller (no PMMU)
59: #define MC68030 0x000080 // Second-Generation 32-Bit Enhanced Microprocessor
60: #define MC68EC030 0x000100 // 32-Bit Embedded Controller (no PMMU)
61: #define MC68040 0x000200 // Third-Generation 32-Bit Microprocessor
62: #define MC68LC040 0x000400 // Third-Generation 32-Bit Microprocessor (no FPU)
63: #define MC68EC040 0x000800 // 32-Bit Embedded Controller (no FPU, no PMMU)
64: #define MC68330 0x001000 // CPU32 Integrated CPU32 Processor
65: #define MC68340 0x002000 // CPU32 Integrated Processor with DMA
66: #define MC68060 0x004000 // Fourth-Generation 32-Bit Microprocessor
67: #define MC68LC060 0x008000 // Fourth-Generation 32-Bit Microprocessor (no FPU)
68: #define MC68EC060 0x010000 // Fourth-Generation 32-Bit Microprocessor (no FPU, no PMMU)
69: #define MC_CPU32 (MC68330|MC68340)
70:
71: #define MC_020 (MC68020|MC68EC020|MC68030|MC68EC030|MC68040|MC68LC040|MC68EC040|MC_CPU32|MC68060|MC68LC060|MC68EC060)
72: #define MC_ALL (MC68000|MC68EC000|MC68HC000|MC68008|MC68010|MC_020)
73:
74: #define MC68851 0x020000 // Paged Memory Management Unit
75:
76: #define MC68881 0x040000 // Floating-PointCoprocessor
77: #define MC68882 0x080000 // Enhanced Floating-Point Coprocessor
78:
79: #define MC_PMMU (MC68881|MC68882)
80: #define MC_FPU (MC68881|MC68882)
81:
82: static int optionCPUTypeMask = ( MC_ALL & ~MC68040 & ~MC_CPU32 & ~MC68060 ) | MC_PMMU | MC_FPU;
83:
84:
85: typedef enum {
86: dtNone,
87: dtByte, // a specific number of bytes, usually 1
88: dtWord, // one 16-bit value
89: dtLong, // one 32-bit value
90: dtOpcode, // an opcode of variable length
91: dtASCString, // a 0-byte terminated ASCII string
92: dtPointer, // a generic 32-bit pointer
93: dtFunctionPointer, // a 32-bit pointer to a function
1.1.1.5 root 94: dtStringArray // a specific number of ASCII bytes
1.1 root 95: } Disass68kDataType;
96:
97: typedef struct {
98: char *name;
99: char *comment;
100: Disass68kDataType type;
101: int size;
102: } disStructElement;
103:
104: typedef struct {
105: char *name; // name of the structure
106: int size; // size of structure
107: int count; // number of lines
108: disStructElement *elements; // array of all elements of the struct
109: } disStructEntry;
110:
111: static int disStructCounts;
112: static disStructEntry *disStructEntries;
113:
114: typedef struct {
115: long addr; // address of the label
116: Disass68kDataType type; // type of the data on the address
117: int size; // size of the label, references inside it are addressed via base address + offset
118: int count; // number of elements at this address with the given size
119: int structIndex; // -1 no struct to describe the element
120: char *name; // name of the label
121: char *comment; // optional comment
122: } disSymbolEntry;
123:
124: static int disSymbolCounts;
125: static disSymbolEntry *disSymbolEntries;
126:
127:
128: static inline unsigned short Disass68kGetWord(long addr)
129: {
1.1.1.6 ! root 130: if ( ! valid_address ( addr , 2 ) )
! 131: return 0;
! 132:
! 133: #ifndef WINUAE_FOR_HATARI
1.1 root 134: return get_word(addr);
1.1.1.6 ! root 135: #else
! 136: return get_word_debug(addr);
! 137: #endif
1.1 root 138: }
139:
140: // Load a text file into memory, count the lines and replace the LF with 0-bytes.
141: static int Disass68kLoadTextFile(const char *filename, char **filebuf)
142: {
143: long index;
1.1.1.4 root 144: long fileLength;
1.1.1.6 ! root 145: int lineCount = 0;
1.1.1.4 root 146: char *fbuf;
147: FILE *f;
148:
1.1 root 149: if(filebuf)
150: *filebuf = NULL;
1.1.1.4 root 151: f = fopen(filename, "r");
1.1.1.6 ! root 152: if (!f)
1.1 root 153: return 0;
1.1.1.6 ! root 154: if (fseek(f, 0, SEEK_END))
! 155: goto out;
1.1.1.4 root 156: fileLength = ftell(f);
1.1.1.6 ! root 157: if (fileLength <= 0)
! 158: goto out;
! 159: if (fseek(f, 0, SEEK_SET))
! 160: goto out;
1.1.1.4 root 161: fbuf = malloc(fileLength);
1.1.1.6 ! root 162: if(!fbuf)
! 163: goto out;
1.1 root 164: if((size_t)fileLength != fread(fbuf, sizeof(char), fileLength, f))
1.1.1.4 root 165: {
166: free(fbuf);
1.1.1.6 ! root 167: goto out;
1.1.1.4 root 168: }
1.1.1.6 ! root 169:
1.1 root 170: for(index=0; index<fileLength; ++index)
171: {
172: if(fbuf[index] == '\r') // convert potential CR into a space (which we ignore at the end of the line anyway)
173: fbuf[index] = ' ';
174: if(fbuf[index] == '\n') // count LF and terminate line
175: {
176: ++lineCount;
177: fbuf[index] = 0;
178: }
179: }
180: if(filebuf)
181: *filebuf = fbuf;
1.1.1.6 ! root 182: out:
! 183: fclose(f);
1.1 root 184: return lineCount;
185: }
186:
187: static void Disass68kLoadStructInfo(const char *filename)
188: {
1.1.1.4 root 189: int i,j;
190: char *nextLine;
191: char *line;
1.1 root 192: char *fbuf = NULL;
1.1.1.4 root 193: int lineCount = Disass68kLoadTextFile(filename, &fbuf);
1.1 root 194: disStructEntry *se = NULL;
1.1.1.4 root 195:
196: if(!lineCount) return;
197:
198: disStructEntries = realloc(disStructEntries, sizeof(disStructEntry)
199: * (disStructCounts + lineCount));
1.1 root 200: if(!disStructEntries) { free(fbuf); return; }
1.1.1.4 root 201:
202: line = fbuf;
1.1 root 203:
204: for(i=0; i<lineCount; line = nextLine, ++i)
205: {
206: // strip spaces at the end of the line, remember the ptr to the next line
207: char *sp = line;
208: while(*sp++)
209: ;
210: nextLine = sp--;
1.1.1.5 root 211: while (isspace((unsigned char)*--sp))
1.1 root 212: *sp = 0;
213:
214: if(line[0] == '{')
215: {
216: se = &disStructEntries[disStructCounts];
217: se->name = strdup(line+1);
218: se->count = 0;
219: se->elements = malloc(sizeof(disStructElement) * lineCount); // lineCount is way too much, but safe
220: } else if(line[0] == '}') {
221: if(se)
222: {
223: se->size = 0;
224: for(j=0; j<se->count; ++j)
225: se->size += se->elements[j].size;
226: // printf("%s : %d bytes\n", se->name, se->size);
227: ++disStructCounts;
228: se = NULL;
229: }
230: } else if(line[0] == '#') {
231: disStructElement dse;
232: int val = 0;
233: int index = 2;
234: if(line[1] == 'A' || line[1] == 'B')
235: {
1.1.1.5 root 236: for(; isdigit((unsigned char)line[index]); ++index)
1.1 root 237: {
238: val *= 10;
239: val += line[index] - '0';
240: }
241: }
242: if(val == 0) val = 1;
243: dse.name = NULL;
244: switch(line[1])
245: {
246: case 'A': dse.type = dtStringArray; dse.size = val; dse.name = strdup(line + index + 1); break;
247: case 'B': dse.type = dtByte; dse.size = val; break;
248: case 'W': dse.type = dtWord; dse.size = 2; break;
249: case 'L': dse.type = dtLong; dse.size = 4; break;
250: case 'C': dse.type = dtOpcode; dse.size = 2; break;
251: case 'f': dse.type = dtFunctionPointer; dse.size = 4; break;
252: case 'p': dse.type = dtPointer; dse.size = 4; break;
253: default: dse.type = dtNone; dse.size = 0;
254: printf("Unknown type in \"%s\"\n", line); break;
255: }
256: if(!dse.name)
257: dse.name = strdup(line+3);
258: dse.comment = NULL;
259: if(se)
260: se->elements[se->count++] = dse;
261: }
262: }
263: free(fbuf);
264: }
265:
266: static void Disass68kLoadSymbols(const char *filename)
267: {
1.1.1.4 root 268: int i,j;
269: char *nextLine;
270: char *line;
1.1 root 271: char *fbuf = NULL;
272: int lineCount = Disass68kLoadTextFile(filename, &fbuf);
1.1.1.4 root 273: if(!lineCount) return;
1.1 root 274: disSymbolEntries = realloc(disSymbolEntries, sizeof(disSymbolEntry) * (disSymbolCounts + lineCount));
275: if(!disSymbolEntries) { free(fbuf); return; }
1.1.1.4 root 276: line = fbuf;
1.1 root 277:
278: for(i=0; i<lineCount; line = nextLine, ++i)
279: {
1.1.1.4 root 280: long addr;
1.1 root 281: char *sp = line;
1.1.1.4 root 282: char *parameterPtr[10];
283: int parameterCount = 0;
284: char *str;
285: long size = 0;
286: int type = 0;
287:
288: // strip spaces at the end of the line, remember the ptr to the next line
1.1 root 289: while(*sp++)
290: ;
291: nextLine = sp--;
1.1.1.5 root 292: while(isspace((unsigned char)*--sp))
1.1 root 293: *sp = 0;
294:
295: // ignore empty lines
296: if(line[0] == 0)
297: continue;
298:
299: sscanf(line, "%lx",&addr);
300: disSymbolEntries[disSymbolCounts].addr = addr;
301: disSymbolEntries[disSymbolCounts].structIndex = -1;
302:
1.1.1.4 root 303: str = line;
1.1 root 304: do {
305: str = strchr(str, ',');
306: if(str)
307: {
308: char *ep = str;
1.1.1.5 root 309: while(isspace((unsigned char)*--ep))
1.1 root 310: *ep = 0;
311: *str++ = 0;
1.1.1.5 root 312: while(*str && isspace((unsigned char)*str))
1.1 root 313: ++str;
314: parameterPtr[parameterCount++] = str;
315: }
316: } while(str != NULL && parameterCount < 10);
317:
318: if(parameterCount != 3 && parameterCount != 4)
319: continue; // ignore line
320:
321: if(strlen(parameterPtr[0]) == 1)
322: {
323: switch(parameterPtr[0][0])
324: {
325: case 'A': type = dtASCString; size = 1; break; // ascii NULL
326: case 'B': type = dtByte; size = 1; break; // byte
327: case 'W': type = dtWord; size = 2; break; // word
328: case 'L': type = dtLong; size = 4; break; // long
329: case 'C': type = dtOpcode; size = 2; break; // code
330: case 'f': type = dtFunctionPointer; size = 4; break; // function pointer
331: case 'p': type = dtPointer; size = 4; break; // regular pointer
332: default: printf("ERROR: $%lx : %s\n", addr, parameterPtr[0]); continue;
333: }
334: } else {
335: for(j=0; j<disStructCounts; ++j)
336: {
337: disStructEntry *se = &disStructEntries[j];
338: if(se->name == NULL)
339: break;
340: if(strcmp(parameterPtr[0], se->name))
341: continue;
342: size = se->size;
343: disSymbolEntries[disSymbolCounts].structIndex = j;
344: }
345: }
346: if(!size)
347: continue;
348:
349: disSymbolEntries[disSymbolCounts].type = type;
350: disSymbolEntries[disSymbolCounts].size = size;
351: disSymbolEntries[disSymbolCounts].count = atol(parameterPtr[1]);
352: disSymbolEntries[disSymbolCounts].name = strdup(parameterPtr[2]);
353: disSymbolEntries[disSymbolCounts].comment = NULL;
354: if(parameterCount == 4)
355: disSymbolEntries[disSymbolCounts].comment = strdup(parameterPtr[3]);
356: ++disSymbolCounts;
357: }
358: free(fbuf);
359: }
360:
361: static void Disass68kInit(const char *baseDirectory)
362: {
1.1.1.2 root 363: char filename[FILENAME_MAX];
1.1 root 364:
365: disStructCounts = 0;
366: sprintf(filename, "%s/DisassStructs.txt", baseDirectory);
367: Disass68kLoadStructInfo(filename);
368: sprintf(filename, "%s/DisassStructs_%4.4X.txt", baseDirectory, TosVersion);
369: Disass68kLoadStructInfo(filename);
370:
371: disSymbolCounts = 0;
372: sprintf(filename, "%s/DisassSymbols.txt", baseDirectory);
373: Disass68kLoadSymbols(filename);
374: sprintf(filename, "%s/DisassSymbols_%4.4X.txt", baseDirectory, TosVersion);
375: Disass68kLoadSymbols(filename);
376: }
377:
378:
379:
380: static Disass68kDataType Disass68kType(long addr, char *addressLabel, char *commentBuffer, int *count)
381: {
382: int i,j;
383:
384: addressLabel[0] = 0;
385: commentBuffer[0] = 0;
386: for(i=0; i<disSymbolCounts; ++i)
387: {
1.1.1.4 root 388: const disStructEntry *se;
1.1 root 389: const disSymbolEntry *dse = &disSymbolEntries[i];
390: int offset = addr - dse->addr;
1.1.1.4 root 391:
1.1 root 392: if(offset < 0 || offset >= dse->count * dse->size)
393: continue;
394:
395: // no special struct that devices this value?
396: if(dse->structIndex < 0)
397: {
398: offset = (offset + dse->size - 1) / dse->size;
399: *count = dse->count - offset;
400: if(offset == 0) // only in the first line
401: {
402: strcpy(addressLabel, dse->name);
403: if(dse->comment)
404: strcpy(commentBuffer, dse->comment);
405: }
406: return dse->type;
407: }
408:
409: *count = 1;
1.1.1.4 root 410: se = &disStructEntries[dse->structIndex];
1.1 root 411: for(j=0; j<se->count; ++j)
412: {
413: const disStructElement *e = &se->elements[j];
414: if(offset < e->size)
415: {
416: if(e->type == dtStringArray)
417: *count = e->size;
418: if(j == 0)
419: strcpy(addressLabel, dse->name);
420:
421: sprintf(commentBuffer, "[%s]", e->name);
422: if(e->comment)
423: strcat(commentBuffer, e->comment);
424: return e->type;
425: }
426: offset -= e->size;
427: }
428: return dse->size;
429: }
430: return dtNone;
431: }
432:
433: /***
434: * Lookup a symbol name
435: ***/
436: static const char *Disass68kSymbolName(long addr, int size)
437: {
438: int i;
439:
440: for(i=0; i<disSymbolCounts; ++i)
441: {
1.1.1.4 root 442: static char symbolName[128];
1.1 root 443: const disSymbolEntry *dse = &disSymbolEntries[i];
1.1.1.4 root 444: int offset = addr - dse->addr;
445: int reminder;
446:
1.1 root 447: if(offset < 0 || offset >= dse->count * dse->size)
448: continue;
449:
450: if(dse->name[0] == 0)
451: return NULL;
452:
1.1.1.4 root 453: reminder = offset % dse->size;
1.1 root 454: offset /= dse->size;
455:
456: strcpy(symbolName, dse->name);
457: if(offset)
458: sprintf(symbolName+strlen(symbolName), "+%d*%d", dse->size, offset);
459: if(reminder)
460: sprintf(symbolName+strlen(symbolName), "+%d", reminder);
461: return symbolName;
462: }
463: return NULL;
464: }
465:
466: /***
467: * return a string pointer to display a register name
468: ***/
469: static const char *Disass68kRegname(int reg)
470: {
471: static char regName[3];
472: switch(reg)
473: {
474: case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
475: sprintf(regName, "%c%d", (options & doptRegisterSmall ? 'd' : 'D'), reg);
476: break;
477:
478: case 0x0F:
479: if(options & doptStackSP) // display A7 as SP
480: {
481: if(options & doptRegisterSmall)
482: return "sp";
483: return "SP";
484: }
485: case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: case 0x0D: case 0x0E:
486: sprintf(regName, "%c%d", (options & doptRegisterSmall ? 'a' : 'A'), reg & 7);
487: break;
488: }
489: return regName;
490: }
491:
492: /***
493: * return a string pointer to display a register name
494: ***/
495: static const char *Disass68kNumber(int val)
496: {
497: static char numString[32];
498: if(val >= -9 && val <= 9)
499: {
500: sprintf(numString, "%d", val);
501: } else {
502: // 4 characters/numbers or underscore (e.g. for cookies)
1.1.1.5 root 503: unsigned char c0 = (val >> 24) & 0xFF;
504: unsigned char c1 = (val >> 16) & 0xFF;
505: unsigned char c2 = (val >> 8) & 0xFF;
506: unsigned char c3 = (val >> 0) & 0xFF;
1.1 root 507: if((isalnum(c0) || c0 == '_') && (isalnum(c1) || c1 == '_') && (isalnum(c2) || c2 == '_') && (isalnum(c3) || c3 == '_'))
508: {
509: sprintf(numString, "'%c%c%c%c'", c0, c1, c2, c3);
510: } else {
511: sprintf(numString, "$%x", val);
512: }
513: }
514: return numString;
515: }
516:
517: /***
518: * Supported registers for e.g. MOVEC
519: ***/
520: #define REG_CCR -1
521: #define REG_SR -2
522: #define REG_PC -3
523: #define REG_ZPC -4
524: #define REG_TT0 -8
525: #define REG_TT1 -9
526: #define REG_MMUSR -10
527: #define REG_USP 0x800
528: #define REG_SFC 0x000
529: #define REG_DFC 0x001
530: #define REG_TC 0x10000
531: #define REG_SRP 0x10002
532: #define REG_CRP 0x10003
533: #define REG_VAL 0x20000
534: #define REG_CACHES_NONE 0x20010
535: #define REG_CACHES_IC 0x20011
536: #define REG_CACHES_DC 0x20012
537: #define REG_CACHES_ICDC 0x20013
538: #define REG_FPU_FPCR 0x30004
539: #define REG_FPU_FPSR 0x30002
540: #define REG_FPU_FPIAR 0x30001
541:
542: static const char *Disass68kSpecialRegister(int reg)
543: {
544: static char buf[8];
545: const char *sp = NULL;
546: switch (reg)
547: {
548: case 0x000: sp = "SFC"; break;
549: case 0x001: sp = "DFC"; break;
550: case 0x002: sp = "CACR"; break;
551: case 0x003: sp = "TC"; break;
552: case 0x004: sp = "ITT0"; break; // IACR0 on an 68EC040 only
553: case 0x005: sp = "ITT1"; break; // IACR1 on an 68EC040 only
554: case 0x006: sp = "DTT0"; break; // DACR0 on an 68EC040 only
555: case 0x007: sp = "DTT1"; break; // DACR1 on an 68EC040 only
556: case 0x008: sp = "BUSCR"; break;
557:
558: case 0x800: sp = "USP"; break;
559: case 0x801: sp = "VBR"; break;
560: case 0x802: sp = "CAAR"; break;
561: case 0x803: sp = "MSP"; break;
562: case 0x804: sp = "ISP"; break;
563: case 0x805: sp = "MMUSR"; break;
564: case 0x806: sp = "URP"; break;
565: case 0x807: sp = "SRP"; break;
566: case 0x808: sp = "PCR"; break;
567:
568: // MMU register
569: case 0x10000: sp = "TC"; break;
570: case 0x10001: sp = "DRP"; break;
571: case 0x10002: sp = "SRP"; break;
572: case 0x10003: sp = "CRP"; break;
573: case 0x10004: sp = "CAL"; break;
574: case 0x10005: sp = "VAL"; break;
575: case 0x10006: sp = "SCCR"; break;
576: case 0x10007: sp = "ACR"; break;
577:
578: case REG_CCR: sp = "CCR"; break;
579: case REG_SR: sp = "SR"; break;
580: case REG_PC: sp = "PC"; break;
581: case REG_ZPC: sp = "ZPC"; break;
582: case REG_TT0: sp = "TT0"; break;
583: case REG_TT1: sp = "TT1"; break;
584: case REG_MMUSR: sp = "MMUSR"; break;
585:
586: case REG_VAL: sp = "VAL"; break;
587:
588: case REG_CACHES_NONE: sp = "NC"; break;
589: case REG_CACHES_IC: sp = "IC"; break;
590: case REG_CACHES_DC: sp = "DC"; break;
591: case REG_CACHES_ICDC: sp = "IC/DC"; break; // GCC lists this as "BC"
592:
593: case REG_FPU_FPCR: sp = "FPCR"; break;
594: case REG_FPU_FPSR: sp = "FPSR"; break;
595: case REG_FPU_FPIAR: sp = "FPIAR"; break;
596:
597: // unknown register => unknown opcode!
1.1.1.4 root 598: default: return NULL;
1.1 root 599: }
1.1.1.4 root 600:
1.1 root 601: if(options & doptRegisterSmall)
602: {
1.1.1.4 root 603: char *bp;
1.1 root 604: strcpy(buf, sp);
1.1.1.4 root 605: for (bp = buf; *bp; ++bp)
1.1.1.5 root 606: *bp = tolower((unsigned char)*bp);
1.1 root 607: return buf;
608: }
609: return sp;
610: }
611:
612: /***
613: * 680x0 EA disassembly, supports all address modes
614: *
615: * disassbuf = output buffer for the EA, empty string in case of an illegal EA
616: * addr = pointer to the address, which Disass68kGetWord() will allow to read memory.
617: * Incremented by the function to point behind the opcode, when done
618: * ea = 6-bit ea from the opcode
619: * size = addressed size of the opcode in bytes (e.g. 1,2,4 for MOVE.B, MOVE.W, MOVE.L), only used for immediate addressing
620: ***/
621:
622: #define EA_Dn 0x00001 // Dn
623: #define EA_An 0x00002 // An
624: #define EA_Ani 0x00004 // (An)
625: #define EA_Anip 0x00008 // (An)+
626: #define EA_piAn 0x00010 // -(An)
627: #define EA_dAn 0x00020 // d(An), d(An,Dn), etc.
628: #define EA_PCRel 0x00040 // d(PC), d(PC,Dn), etc.
629: #define EA_Abs 0x00080 // abs.w, abs.l
630: #define EA_Immed 0x00100 // #<val>
631:
632: #define EA_ImmedParameter 0x0200 // an immediate value as a parameter
633: #define EA_ValueParameter 0x0400 // an immediate value as a parameter without the "#"
634: #define EA_SpecialRegister 0x0800 // any special register e.g. SR,CCR,USP,etc
635: #define EA_PCDisplacement 0x1000 // PC relative jump, like for BRA and friends
636:
637: #define EA_All (EA_Dn | EA_An | EA_Ani | EA_Anip | EA_piAn | EA_dAn | EA_Abs | EA_Immed | EA_PCRel)
638: #define EA_Dest (EA_Dn | EA_An | EA_Ani | EA_Anip | EA_piAn | EA_dAn | EA_Abs)
639:
640: static char *Disass68kEA(char *disassbuf, char *commentBuffer, long *addr, long opcodeAddr, int ea, int size, int allowedEAs, int parameterValue, int disassFlag)
641: {
642: unsigned short eWord1;
643: unsigned short eWord2;
644: int xn,c,scale;
645: int reg = ea & 7;
646: const char *sp;
647: long val;
1.1.1.4 root 648: char regName[3];
649: signed long pcoffset;
650:
1.1 root 651: disassbuf[0] = 0;
652: switch(ea)
653: {
654: // M=000 = 0 Dn
655: // Data Register Direct Mode
656: // Dn
657: // M=001 = 1 An
658: // Address Register Direct Mode
659: // An
660: case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
661: if((allowedEAs & EA_Dn) != EA_Dn)
662: break;
663: sprintf(disassbuf, "%s", Disass68kRegname(ea & 0x0F));
664: break;
665: case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: case 0x0D: case 0x0E: case 0x0F:
666: if((allowedEAs & EA_An) != EA_An)
667: break;
668: sprintf(disassbuf, "%s", Disass68kRegname(ea & 0x0F));
669: break;
670:
671: // M=010 = 2
672: // Address Register Indirect Mode
673: // (An)
674: case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
675: if((allowedEAs & EA_Ani) != EA_Ani)
676: break;
677: sprintf(disassbuf, "(%s)", Disass68kRegname(reg | 8));
678: break;
679:
680: // M=011 = 3
681: // Address Register Indirect with Postincrement Mode
682: // (An) +
683: case 0x18: case 0x19: case 0x1A: case 0x1B: case 0x1C: case 0x1D: case 0x1E: case 0x1F:
684: if((allowedEAs & EA_Anip) != EA_Anip)
685: break;
686: sprintf(disassbuf, "(%s)+", Disass68kRegname(reg | 8));
687: break;
688:
689: // M=100 = 4
690: // Address Register Indirect with Predecrement Mode
691: // – (An)
692: case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
693: if((allowedEAs & EA_piAn) != EA_piAn)
694: break;
695: sprintf(disassbuf, "-(%s)", Disass68kRegname(reg | 8));
696: break;
697:
698: // M=101 = 5
699: // Address Register Indirect with Displacement Mode
700: // (d16,An)
701: case 0x28: case 0x29: case 0x2A: case 0x2B: case 0x2C: case 0x2D: case 0x2E: case 0x2F:
702: if((allowedEAs & EA_dAn) != EA_dAn)
703: break;
704: eWord1 = Disass68kGetWord(*addr); *addr += 2;
705: sprintf(disassbuf, "%s(%s)", Disass68kNumber(eWord1), Disass68kRegname(reg | 8));
706: break;
707:
708: // M=111 = 7, Xn/reg = 011 = 3
709: // Program Counter Indirect with Index (Base Displacement) Mode
710: // (bd, PC, Xn. SIZE*SCALE)
711: // Program Counter Memory Indirect Postindexed Mode
712: // ([bd,PC],Xn.SIZE*SCALE,od)
713: // Program Counter Memory Indirect Preindexed Mode
714: // ([bd,PC,Xn.SIZE*SCALE],od)
715: case 0x3B:
716: // This is equal to the following, except that instead of An, it is PC relative
717:
718: // M=110 = 6
719: // Address Register Indirect with Index (Base Displacement) Mode
720: // (bd,An,Xn.SIZE*SCALE)
721: // Memory Indirect Postindexed Mode
722: // ([bd,An],Xn.SIZE*SCALE,od)
723: // Memory Indirect Preindexed Mode
724: // ([bd, An, Xn.SIZE*SCALE], od)
725: case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
726: eWord1 = Disass68kGetWord(*addr); *addr += 2;
727: xn = (eWord1 >> 12) & 0x0F; // Register D0..D7/A0..A7
728: c = ((eWord1 >> 11) & 1) ? 'l' : 'w'; // Word/Long-Word Index Size 0 = Sign-Extended Word 1 = Long Word
729: scale = (eWord1 >> 9) & 3; // Scale Factor 00 = 1 01 = 2 10 = 4 11 = 8
1.1.1.4 root 730:
1.1 root 731: if(ea == 0x3B)
732: {
733: sp = Disass68kSpecialRegister(REG_PC);
734: if(!sp) return NULL;
735: strcpy(regName, sp);
736: } else {
737: sprintf(regName, "%s", Disass68kRegname(reg | 8));
738: }
739:
740: if((eWord1 & 0x0100) == 0)
741: {
1.1.1.4 root 742: const char *numStr;
743:
1.1 root 744: // BRIEF EXTENSION WORD FORMAT
745: if(ea == 0x3B)
746: {
747: if((allowedEAs & EA_PCRel) != EA_PCRel)
748: break;
749: } else {
750: if((allowedEAs & EA_dAn) != EA_dAn)
751: break;
752: }
753:
754: // Address Register Indirect with Index (8-Bit Displacement) Mode
755: // (d8 ,An, Xn.SIZE*SCALE)
1.1.1.4 root 756: numStr = Disass68kNumber(eWord1 & 0xFF);
1.1 root 757: if(numStr[0] == '0' && numStr[1] == 0)
758: numStr = "";
759:
760: // scale is only on 68020 and later supported
761: if(scale != 0 && (optionCPUTypeMask & MC_020) == 0)
762: return NULL;
763:
764: if(scale == 0)
765: {
766: #if ADDRESS_ON_PC
767: if(ea == 0x3B)
768: sprintf(disassbuf, "$%lx(%s,%s.%c)", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2, Disass68kSpecialRegister(REG_PC), Disass68kRegname(xn), c);
769: else
770: #endif
771: sprintf(disassbuf, "%s(%s,%s.%c)", numStr, regName, Disass68kRegname(xn), c);
772: } else
773: {
774: #if ADDRESS_ON_PC
775: if(ea == 0x3B)
776: sprintf(disassbuf, "$%lx(%s,%s.%c*%d)", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2, Disass68kSpecialRegister(REG_PC), Disass68kRegname(xn), c, 1 << scale);
777: else
778: #endif
779: sprintf(disassbuf, "%s(%s,%s.%c*%d)", numStr, regName, Disass68kRegname(xn), c, 1 << scale);
780: }
781: #if USE_SYMBOLS
782: if(ea == 0x3B)
783: {
784: const char *symStr = Disass68kSymbolName((signed char)(eWord1 & 0xFF) + opcodeAddr + 2, size);
785: if(symStr)
786: {
787: commentBuffer += strlen(commentBuffer);
788: sprintf(commentBuffer+strlen(commentBuffer), "%s", symStr);
789: }
790: }
791: #endif
792: #if !ADDRESS_ON_PC
793: if(ea == 0x3B)
794: {
795: commentBuffer += strlen(commentBuffer);
796: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2);
797: }
798: #endif
799: } else {
800: // FULL EXTENSION WORD FORMAT
801:
1.1.1.4 root 802: int bs = (eWord1 >> 7) & 1; // Base Register Suppress 0 = Base Register Added 1 = Base Register Suppressed
803: int is = (eWord1 >> 6) & 1; // Index Suppress 0 = Evaluate and Add Index Operand 1 = Suppress Index Operand
804: int bdSize = (eWord1 >> 4) & 3; // Base Displacement Size 00 = Reserved 01 = Null Displacement 10 = Word Displacement 11 = Long Displacement
805: int iis = eWord1 & 7; // Index/Indirect Selection Indirect and Indexing Operand Determined in Conjunction with Bit 6, Index Suppress
1.1 root 806: bool prefixComma;
1.1.1.4 root 807: long bd, od;
1.1 root 808:
809: // reserved, has to be 0
810: if((eWord1 & 8) != 0 || bdSize == 0 || (is && iis > 3) || iis == 4)
811: break;
812:
813: // full extension format is only supported on 68020 or later
814: if((optionCPUTypeMask & MC_020) == 0)
815: return NULL;
816:
817: if(ea == 0x3B)
818: {
819: if((allowedEAs & EA_PCRel) != EA_PCRel)
820: break;
821: } else {
822: if((allowedEAs & EA_dAn) != EA_dAn)
823: break;
824: }
825:
1.1.1.4 root 826: bd = 0;
1.1 root 827: switch(bdSize)
828: {
829: case 3:
830: bd = Disass68kGetWord(*addr); *addr += 2;
831: bd <<= 16;
832: case 2:
833: bd |= Disass68kGetWord(*addr); *addr += 2;
834: break;
835: default:
836: break;
837: }
838:
839: prefixComma = false;
840: if(bdSize >= 2 && iis == 0)
841: sprintf(disassbuf, "%s", Disass68kNumber(bd));
842: strcat(disassbuf, "(");
843: if(iis != 0)
844: {
845: // the CPU32 doesn't support the memory indirect mode
846: if(optionCPUTypeMask & MC_CPU32)
847: return NULL;
848:
849: strcat(disassbuf, "[");
850: }
851: if(bdSize >= 2 && iis != 0)
852: {
853: sprintf(disassbuf+strlen(disassbuf), "%s", Disass68kNumber(bd));
854: prefixComma = true;
855: }
856: if(bdSize == 1 && ((bs && is && iis > 0) || (bs && iis >= 5)))
857: {
858: if(ea == 0x3B)
859: {
860: sp = Disass68kSpecialRegister(REG_ZPC);
861: if(!sp) return NULL;
862: strcat(disassbuf, sp);
863: } else {
864: strcat(disassbuf, "0");
865: }
866: }
867: if(!bs)
868: {
869: if(prefixComma)
870: strcat(disassbuf, ",");
871: strcat(disassbuf, regName);
872: prefixComma = true;
873: }
874: if(iis >= 5 && iis <= 7)
875: {
876: strcat(disassbuf, "]");
877: prefixComma = true;
878: }
879: if(!is)
880: {
881: if(prefixComma)
882: strcat(disassbuf, ",");
883: if(scale == 0)
884: {
885: sprintf(disassbuf+strlen(disassbuf), "%s.%c", Disass68kRegname(xn), c);
886: } else
887: {
888: sprintf(disassbuf+strlen(disassbuf), "%s.%c*%d", Disass68kRegname(xn), c, 1 << scale);
889: }
890: }
891: if(iis >= 1 && iis <= 3)
892: {
893: strcat(disassbuf, "]");
894: prefixComma = true;
895: }
1.1.1.4 root 896: od = 0;
1.1 root 897: switch(iis & 3)
898: {
899: case 3:
900: od = Disass68kGetWord(*addr); *addr += 2;
901: od <<= 16;
902: case 2:
903: od |= Disass68kGetWord(*addr); *addr += 2;
904: if(prefixComma)
905: strcat(disassbuf, ",");
906: sprintf(disassbuf+strlen(disassbuf), "%s", Disass68kNumber(od));
907: break;
908: default:
909: break;
910: }
911: strcat(disassbuf, ")");
912: }
913: break;
914:
915: // M=111 = 7, Xn/reg = 000 = 0
916: // Absolute Short Addressing Mode
917: // (xxx).W
918: case 0x38:
919: if((allowedEAs & EA_Abs) != EA_Abs)
920: break;
921: eWord1 = Disass68kGetWord(*addr); *addr += 2;
922: val = eWord1;
923: if(eWord1 & 0x8000)
924: val |= 0xFFFF0000;
925: #if USE_SYMBOLS
926: sp = Disass68kSymbolName(val, size);
927: if(sp)
928: {
929: if(options & doptNoBrackets)
930: sprintf(disassbuf, "%s.w", sp);
931: else
932: sprintf(disassbuf, "(%s).w", sp);
933: break;
934: }
935: #endif
936: if(options & doptNoBrackets)
937: {
938: if(val & 0x80000000)
939: sprintf(disassbuf, "$%8.8lx.w", val);
940: else
941: sprintf(disassbuf, "$%4.4lx.w", val);
942: } else {
943: if(val & 0x80000000)
944: sprintf(disassbuf, "($%8.8lx).w", val);
945: else
946: sprintf(disassbuf, "($%4.4lx).w", val);
947: }
948: break;
949:
950: // M=111 = 7, Xn/reg = 001 = 1
951: // Absolute Long Addressing Mode
952: // (xxx).L
953: case 0x39:
954: if((allowedEAs & EA_Abs) != EA_Abs)
955: break;
956: eWord1 = Disass68kGetWord(*addr); *addr += 2;
957: eWord2 = Disass68kGetWord(*addr); *addr += 2;
958: #if USE_SYMBOLS
959: val = (eWord1 << 16) | eWord2;
960: sp = Disass68kSymbolName(val, size);
961: if(sp)
962: {
963: if(options & doptNoBrackets)
964: sprintf(disassbuf, "%s", sp);
965: else
966: sprintf(disassbuf, "(%s).l", sp);
967: break;
968: }
969: #endif
970: if(options & doptNoBrackets)
971: sprintf(disassbuf, "%s", Disass68kNumber((eWord1 << 16) | eWord2));
972: else
973: sprintf(disassbuf, "(%s).l", Disass68kNumber((eWord1 << 16) | eWord2));
974: break;
975:
976: // M=111 = 7, Xn/reg = 010 = 2
977: // Program Counter Indirect with Displacement Mode
978: // (d16,PC)
979: case 0x3A:
980: if((allowedEAs & EA_PCRel) != EA_PCRel)
981: break;
982: eWord1 = Disass68kGetWord(*addr); *addr += 2;
983: sp = Disass68kSpecialRegister(REG_PC);
984: if(!sp) return NULL;
985: #if ADDRESS_ON_PC
986: #if USE_SYMBOLS
987: sp = Disass68kSymbolName(((signed short)eWord1 + *addr - 2), size);
988: if(sp)
989: {
990: sprintf(disassbuf, "%s(%s)", sp, Disass68kSpecialRegister(REG_PC));
991: } else {
992: sprintf(disassbuf, "$%lx(%s)", (signed short)eWord1 + *addr - 2, Disass68kSpecialRegister(REG_PC));
993: }
994: #else
995: sprintf(disassbuf, "$%lx(%s)", (signed short)eWord1 + *addr - 2, Disass68kSpecialRegister(REG_PC));
996: #endif
997: #else
998: sprintf(disassbuf, "%s(%s)", Disass68kNumber(eWord1),sp);
999: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", (signed short)eWord1 + *addr - 2);
1000: #endif
1001: break;
1002:
1003: // M=111 = 7, Xn/reg = 100 = 4
1004: // Immediate Data
1005: // #<xxx>
1006: case 0x3C:
1007: if((allowedEAs & EA_Immed) != EA_Immed)
1008: break;
1009: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1010: goto immed;
1011:
1012: case 0x0100: // Immediate Value as a parameter
1013: if((allowedEAs & EA_ImmedParameter) != EA_ImmedParameter)
1014: break;
1015: eWord1 = parameterValue;
1016: immed:
1017: switch(size)
1018: {
1019: case 1: eWord1 &= 0xFF;
1020: case 2:
1021: #if USE_SYMBOLS
1022: if(disassFlag)
1023: {
1024: val = eWord1;
1025: if(eWord1 & 0x8000)
1026: val |= 0xFFFF0000;
1027: sp = Disass68kSymbolName(val, size);
1028: if(sp)
1029: {
1030: sprintf(disassbuf, "#%s", sp);
1031: break;
1032: }
1033: }
1034: #endif
1035: sprintf(disassbuf, "#%s", Disass68kNumber(eWord1));
1036: break;
1037: case 4: eWord2 = Disass68kGetWord(*addr); *addr += 2;
1038: #if USE_SYMBOLS
1039: if(disassFlag)
1040: {
1041: val = (eWord1 << 16) | eWord2;
1042: sp = Disass68kSymbolName(val, size);
1043: if(sp)
1044: {
1045: sprintf(disassbuf, "#%s", sp);
1046: break;
1047: }
1048: }
1049: #endif
1050: sprintf(disassbuf, "#%s", Disass68kNumber((eWord1 << 16) | eWord2));
1051: break;
1052: }
1053: break;
1054:
1055: case 0x0103:
1056: if((allowedEAs & EA_ValueParameter) != EA_ValueParameter)
1057: break;
1058: sprintf(disassbuf, "%d", parameterValue);
1059: break;
1060:
1061: case 0x0101: // Special Registers as in the parameter
1062: if((allowedEAs & EA_SpecialRegister) != EA_SpecialRegister)
1063: break;
1064: sp = Disass68kSpecialRegister(parameterValue);
1065: if(!sp) return NULL;
1066: strcpy(disassbuf, sp);
1067: break;
1068:
1069: case 0x0102: // PC relative jump, like for BRA and friends
1070: if((allowedEAs & EA_PCDisplacement) != EA_PCDisplacement)
1071: break;
1.1.1.4 root 1072: pcoffset = 0;
1.1 root 1073: switch(size)
1074: {
1075: case 1: pcoffset = (signed char)parameterValue;
1076: break;
1077: case 2: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1078: pcoffset = (signed short)eWord1;
1079: pcoffset -= 2;
1080: break;
1081: case 4: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1082: eWord2 = Disass68kGetWord(*addr); *addr += 2;
1083: pcoffset = (signed int)((eWord1 << 16) | eWord2);
1084: pcoffset -= 4;
1085: break;
1086: }
1087: #if ADDRESS_ON_PC
1088: #if USE_SYMBOLS
1089: sp = Disass68kSymbolName((*addr + pcoffset), size);
1090: if(sp)
1091: {
1092: strcat(disassbuf, sp);
1093: } else {
1094: sprintf(disassbuf, "$%lx", *addr + pcoffset);
1095: }
1096: #else
1097: sprintf(disassbuf, "$%lx", *addr + pcoffset);
1098: #endif
1099: #else
1100: if(pcoffset < 0)
1101: {
1102: sprintf(disassbuf, "*-$%lx", -pcoffset - 2);
1103: } else {
1104: sprintf(disassbuf, "*+$%lx", pcoffset + 2);
1105: }
1106: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", *addr + pcoffset);
1107: #endif
1108: break;
1109:
1110: default: // 0x3D..0x3F are reserved
1111: break;
1112:
1113: }
1114: if(disassbuf[0] == 0)
1115: return NULL;
1116: return disassbuf + strlen(disassbuf);
1117: }
1118:
1119: /***
1120: * Create a register list for the MOVEM opcode
1121: ***/
1122: static char *Disass68kReglist(char *buf, unsigned short reglist)
1123: {
1124: int bit;
1125: int lastBit = -99;
1126: int lastBitStart = -99;
1127: char regD = options & doptRegisterSmall ? 'd' : 'D';
1128: char regA = options & doptRegisterSmall ? 'a' : 'A';
1129: for(bit=0; bit<=15; ++bit)
1130: {
1131: // bit clear?
1132: if((reglist & (1 << bit)) == 0)
1133: {
1134: // do we have a run? => close it!
1135: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1136: {
1137: *buf++ = '-';
1138: *buf++ = ((bit-1) >= 8) ? regA : regD;
1139: *buf++ = '0' + ((bit-1) & 7);
1140: }
1141: lastBitStart = -1;
1142: continue;
1143: }
1144: // reset when switching from D to A
1145: if(bit == 8 && lastBitStart >= 0)
1146: {
1147: *buf++ = '-';
1148: *buf++ = regD;
1149: *buf++ = '7';
1150: lastBit = 0;
1151: lastBitStart = -99;
1152: }
1153: // separate bits, skip runs of bits to merge them later
1154: if(lastBit >= 0)
1155: {
1156: if(lastBit == bit - 1)
1157: {
1158: lastBit = bit;
1159: continue;
1160: }
1161: *buf++ = '/';
1162: }
1163: *buf++ = (bit >= 8) ? regA : regD;
1164: *buf++ = '0' + (bit & 7);
1165: lastBit = bit;
1166: lastBitStart = bit;
1167: }
1168: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1169: {
1170: *buf++ = '-';
1171: *buf++ = regA;
1172: *buf++ = '7';
1173: }
1174: if(lastBit < 0)
1175: {
1176: *buf++ = '0';
1177: }
1178: *buf = 0;
1179: return buf;
1180: }
1181:
1182: /***
1183: * Flip the bits in an unsigned short, for MOVEM RegList,-(An)
1184: ***/
1185: static unsigned short Disass68kFlipBits(unsigned short mask)
1186: {
1187: unsigned short retMask = 0;
1188: int i;
1189:
1190: for(i=0; i<=15; ++i)
1191: if(mask & (1 << i))
1192: retMask |= (1 << (15-i));
1193: return retMask;
1194: }
1195:
1196: /***
1197: * Create a register list for the MOVEM opcode
1198: ***/
1199: static char *Disass68kFPUReglist(char *buf, unsigned char reglist)
1200: {
1201: int bit;
1202: int lastBit = -99;
1203: int lastBitStart = -99;
1204: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
1205: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
1206: for(bit=0; bit<=7; ++bit)
1207: {
1208: // bit clear?
1209: if((reglist & (1 << bit)) == 0)
1210: {
1211: // do we have a run? => close it!
1212: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1213: {
1214: *buf++ = '-';
1215: *buf++ = regFP1;
1216: *buf++ = regFP2;
1217: *buf++ = '0' + ((bit-1) & 7);
1218: }
1219: lastBitStart = -1;
1220: continue;
1221: }
1222: // separate bits, skip runs of bits to merge them later
1223: if(lastBit >= 0)
1224: {
1225: if(lastBit == bit - 1)
1226: {
1227: lastBit = bit;
1228: continue;
1229: }
1230: *buf++ = '/';
1231: }
1232: *buf++ = regFP1;
1233: *buf++ = regFP2;
1234: *buf++ = '0' + (bit & 7);
1235: lastBit = bit;
1236: lastBitStart = bit;
1237: }
1238: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1239: {
1240: *buf++ = '-';
1241: *buf++ = regFP1;
1242: *buf++ = regFP2;
1243: *buf++ = '7';
1244: }
1245: if(lastBit < 0)
1246: {
1247: *buf++ = '0';
1248: }
1249: *buf = 0;
1250: return buf;
1251: }
1252:
1253:
1254: /***
1255: * List of special cases for the operands
1256: ***/
1257: typedef enum {
1258: ofNone,
1259: ofEa,
1260: ofDn,
1261: ofAn,
1262: ofAni,
1263: ofI,
1264: ofSpecReg,
1265: ofSpecExtReg,
1266: ofD16An,
1267: ofDestDn,
1268: ofDestAn,
1269: ofExtReg,
1270: ofExtAnip,
1271: ofExtReg0,
1272: ofExtRegA0,
1273: ofExtRegD04,
1274: ofExtRegA05,
1275: ofFPUReglist,
1276: ofFPUSRRegList,
1277: ofDestEa6,
1278: ofDestAbsL,
1279: ofIOpcode,
1280: ofCAS,
1281: ofCAS2,
1282: ofI3,
1283: ofExtIm,
1284: ofExtIm32,
1285: ofExtIm4,
1286: ofExtIm10,
1287: ofDisp,
1288: ofPiAn,
1289: ofDestPiAn,
1290: ofAnip,
1291: ofDestAnip,
1292: ofBFEa,
1293: ofRegList,
1294: ofExt4Dn,
1295: ofFPU,
1296: ofFPUMOVE,
1297: ofFMOVECR,
1298: ofFPU3Reg,
1.1.1.5 root 1299: ofLineA
1.1 root 1300: } Disass68kOpcodeFormat;
1301:
1302:
1303: /***
1304: * The order of the table is not important (with the exception of some FPU opcodes, which are commented further down),
1305: * as each opcode should decline if it doesn't match 100%. The 68k CPU also doesn't do guessing based on the context!
1306: ***/
1307: typedef const struct {
1308: int cpuMask;
1309: unsigned long opcodeMask[2*5];
1.1.1.4 root 1310: signed char operationSize[4];
1.1 root 1311: char op[5];
1312: const char *opcodeName;
1313: int parameter[5];
1314: int disassFlag;
1315: } OpcodeTableStruct;
1316:
1.1.1.6 ! root 1317: static OpcodeTableStruct OpcodeTable[] = {
1.1 root 1318: { MC_ALL, {0xff00, 0x0000}, {-1,6,2,0}, {ofI,ofEa}, "ORI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1319: { MC_ALL, {0xf1c0, 0x0100}, {4}, {ofDestDn,ofEa}, "BTST",{0,EA_An|EA_Immed} },
1320: { MC_ALL, {0xf1c0, 0x0140}, {4}, {ofDestDn,ofEa}, "BCHG",{0,EA_Immed|EA_PCRel|EA_An}},
1321: { MC_ALL, {0xf1c0, 0x0180}, {4}, {ofDestDn,ofEa}, "BCLR",{0,EA_Immed|EA_PCRel|EA_An}},
1322: { MC_ALL, {0xf1c0, 0x01C0}, {4}, {ofDestDn,ofEa}, "BSET",{0,EA_Immed|EA_PCRel|EA_An}},
1323: { MC_ALL-MC68060, {0xf1f8, 0x0108}, {2}, {ofD16An,ofDestDn}, "MOVEP.W"},
1324: { MC_ALL-MC68060, {0xf1f8, 0x0148}, {4}, {ofD16An,ofDestDn}, "MOVEP.L"},
1325: { MC_ALL-MC68060, {0xf1f8, 0x0188}, {2}, {ofDestDn,ofD16An}, "MOVEP.W"},
1326: { MC_ALL-MC68060, {0xf1f8, 0x01C8}, {4}, {ofDestDn,ofD16An}, "MOVEP.L"},
1327: { MC_ALL, {0xff00, 0x0200}, {-1,6,2,0}, {ofI,ofEa}, "ANDI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1328: { MC_ALL, {0xff00, 0x0400}, {-1,6,2,0}, {ofI,ofEa}, "SUBI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1329: { MC_ALL, {0xff00, 0x0600}, {-1,6,2,0}, {ofI,ofEa}, "ADDI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1330: { MC_ALL, {0xffc0, 0x0800}, {1}, {ofI,ofEa}, "BTST",{0,EA_An|EA_Immed} },
1331: { MC_ALL, {0xffc0, 0x0840}, {1}, {ofI,ofEa}, "BCHG",{0,EA_Immed|EA_PCRel|EA_An}},
1332: { MC_ALL, {0xffc0, 0x0880}, {1}, {ofI,ofEa}, "BCLR",{0,EA_Immed|EA_PCRel|EA_An}},
1333: { MC_ALL, {0xffc0, 0x08C0}, {1}, {ofI,ofEa}, "BSET",{0,EA_Immed|EA_PCRel|EA_An}},
1334: { MC_ALL, {0xff00, 0x0A00}, {-1,6,2,0}, {ofI,ofEa}, "EORI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1335: { MC_ALL, {0xff00, 0x0C00}, {-1,6,2,0}, {ofI,ofEa}, "CMPI.?",{0,EA_Immed|EA_An}},
1336: { MC_ALL, {0xffff, 0x003C}, {1}, {ofEa,ofSpecReg}, "ORI",{0,REG_CCR} },
1337: { MC_ALL, {0xffff, 0x007C}, {2}, {ofEa,ofSpecReg}, "ORI",{0,REG_SR} },
1338: { MC_ALL, {0xffff, 0x023C}, {1}, {ofEa,ofSpecReg}, "ANDI",{0,REG_CCR} },
1339: { MC_ALL, {0xffff, 0x027C}, {2}, {ofEa,ofSpecReg}, "ANDI",{0,REG_SR} },
1340: { MC_ALL, {0xffff, 0x0A3C}, {1}, {ofEa,ofSpecReg}, "EORI",{0,REG_CCR} },
1341: { MC_ALL, {0xffff, 0x0A7C}, {2}, {ofEa,ofSpecReg}, "EORI",{0,REG_SR} },
1342: { MC68020, {0xffc0, 0x06C0}, {1}, {ofEa}, "CALLM",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1343: { MC68020, {0xfff0, 0x06C0}, {1}, {ofEa}, "RTM"},
1344: { MC_020, {0xf9c0, 0x00C0, 0x0fff,0x0000}, {-1,9,2,0}, {ofEa,ofExtReg}, "CMP2.?",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1345: { MC_020, {0xf9c0, 0x00C0, 0x0fff,0x0800}, {-1,9,2,0}, {ofEa,ofExtReg}, "CHK2.?",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1346: { MC_020&~MC_CPU32, {0xffc0, 0x0AC0, 0xFE38,0x0000}, {1}, {ofCAS,ofEa}, "CAS.B",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1347: { MC_020&~MC_CPU32, {0xffc0, 0x0CC0, 0xFE38,0x0000}, {2}, {ofCAS,ofEa}, "CAS.W",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1348: { MC_020&~MC_CPU32, {0xffc0, 0x0EC0, 0xFE38,0x0000}, {4}, {ofCAS,ofEa}, "CAS.L",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1349: { MC_020&~MC_CPU32, {0xffff, 0x0CFC, 0x0E38,0x0000, 0x0E38,0x0000}, {2}, {ofCAS2}, "CAS2.W"},
1350: { MC_020&~MC_CPU32, {0xffff, 0x0EFC, 0x0E38,0x0000, 0x0E38,0x0000}, {4}, {ofCAS2}, "CAS2.L"},
1351: { MC68010|MC_020, {0xff00, 0x0e00, 0x0fff,0x0000}, {-1,6,2,0}, {ofEa,ofExtReg}, "MOVES.?",{EA_Immed|EA_PCRel|EA_An|EA_Dn,0}},
1352: { MC68010|MC_020, {0xff00, 0x0e00, 0x0fff,0x0800}, {-1,6,2,0}, {ofExtReg,ofEa}, "MOVES.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1353:
1354: { MC_ALL, {0xf000, 0x1000}, {1}, {ofEa,ofDestEa6}, "MOVE.B"},
1355:
1356: { MC_ALL, {0xf000, 0x2000}, {4}, {ofEa,ofDestEa6}, "MOVE.L"},
1357: { MC_ALL, {0xf1c0, 0x2040}, {4}, {ofEa,ofDestAn}, "MOVEA.L",{0},1},
1358:
1359: { MC_ALL, {0xf000, 0x3000}, {2}, {ofEa,ofDestEa6}, "MOVE.W"},
1360: { MC_ALL, {0xf1c0, 0x3040}, {2}, {ofEa,ofDestAn}, "MOVEA.W",{0},1},
1361:
1362: { MC_ALL, {0xff00, 0x4000}, {-1,6,2,0}, {ofEa}, "NEGX.?",{EA_Immed|EA_PCRel|EA_An}},
1363: { MC_020, {0xf1c0, 0x4100}, {4}, {ofEa,ofDestDn}, "CHK.L", {EA_An,0}},
1364: { MC_ALL, {0xf1c0, 0x4180}, {2}, {ofEa,ofDestDn}, "CHK.W", {EA_An,0}},
1365: { MC_ALL, {0xf1c0, 0x41c0}, {4}, {ofEa,ofDestAn}, "LEA",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn,0},1 },
1366: { MC_ALL, {0xff00, 0x4200}, {-1,6,2,0}, {ofEa}, "CLR.?",{EA_Immed|EA_PCRel|EA_An}},
1367: { MC_ALL, {0xff00, 0x4400}, {-1,6,2,0}, {ofEa}, "NEG.?",{EA_Immed|EA_PCRel|EA_An}},
1368: { MC_ALL, {0xff00, 0x4600}, {-1,6,2,0}, {ofEa}, "NOT.?",{EA_Immed|EA_PCRel|EA_An}},
1369: { MC_ALL, {0xffc0, 0x40c0}, {2}, {ofSpecReg,ofEa}, "MOVE",{REG_SR,EA_Immed|EA_PCRel|EA_An} },
1370: { MC_ALL, {0xffc0, 0x42c0}, {1}, {ofSpecReg,ofEa}, "MOVE",{REG_CCR,EA_Immed|EA_PCRel|EA_An} },
1371: { MC_ALL, {0xffc0, 0x44c0}, {1}, {ofEa,ofSpecReg}, "MOVE",{EA_An,REG_CCR} },
1372: { MC_ALL, {0xffc0, 0x46c0}, {2}, {ofEa,ofSpecReg}, "MOVE",{EA_An,REG_SR} },
1373: { MC_ALL, {0xffc0, 0x4800}, {1}, {ofEa}, "NBCD",{EA_Immed|EA_PCRel|EA_An}},
1374: { MC_020, {0xfff8, 0x4808}, {4}, {ofEa,ofI}, "LINK.L"},
1375: { MC_ALL, {0xffc0, 0x4840}, {0}, {ofEa}, "PEA",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn},1 },
1376: { MC_ALL, {0xfff8, 0x4840}, {4}, {ofEa}, "SWAP"},
1377: { MC68010|MC_020, {0xfff8, 0x4848}, {0}, {ofIOpcode}, "BKPT",{0x07} },
1378: { MC_ALL, {0xffc0, 0x4880, 0x10000}, {2}, {ofRegList,ofEa}, "MOVEM.W",{0,EA_Dn|EA_An|EA_Immed|EA_Anip|EA_PCRel} },
1379: { MC_ALL, {0xffc0, 0x48c0, 0x10000}, {4}, {ofRegList,ofEa}, "MOVEM.L",{0,EA_Dn|EA_An|EA_Immed|EA_Anip|EA_PCRel} },
1380: { MC_ALL, {0xfff8, 0x4880}, {2}, {ofEa}, "EXT.W"},
1381: { MC_ALL, {0xfff8, 0x48c0}, {4}, {ofEa}, "EXT.L"},
1382: { MC_020, {0xfff8, 0x49c0}, {4}, {ofEa}, "EXTB.L"},
1383: { MC_ALL, {0xff00, 0x4a00}, {-1,6,2,0}, {ofEa}, "TST.?"},
1384: { MC_ALL, {0xffc0, 0x4ac0}, {1}, {ofEa}, "TAS",{EA_Immed|EA_PCRel|EA_An}},
1385: { MC_CPU32, {0xffff, 0x4afa}, {0}, {ofNone}, "BGND"},
1386: { MC_ALL, {0xffff, 0x4afc}, {0}, {ofNone}, "ILLEGAL"},
1387: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0000}, {4}, {ofEa,ofExtReg}, "MULU.L", {EA_An,0}},
1388: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0800}, {4}, {ofEa,ofExtReg}, "MULS.L", {EA_An,0}},
1389: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0000}, {4}, {ofEa,ofExtReg}, "DIVU.L", {EA_An,0}},
1390: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0800}, {4}, {ofEa,ofExtReg}, "DIVS.L", {EA_An,0}},
1391: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0400}, {4}, {ofEa,ofExtReg,ofExtReg0}, "MULU.L", {EA_An,0,0}},
1392: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0c00}, {4}, {ofEa,ofExtReg,ofExtReg0}, "MULS.L", {EA_An,0,0}},
1393: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0400}, {4}, {ofEa,ofExtReg,ofExtReg0}, "DIVU.L", {EA_An,0,0}},
1394: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0c00}, {4}, {ofEa,ofExtReg,ofExtReg0}, "DIVS.L", {EA_An,0,0}},
1395: { MC_ALL, {0xffc0, 0x4c80, 0x10000}, {2}, {ofEa,ofRegList}, "MOVEM.W",{EA_Dn|EA_An|EA_Immed|EA_piAn,0} },
1396: { MC_ALL, {0xffc0, 0x4cc0, 0x10000}, {4}, {ofEa,ofRegList}, "MOVEM.L",{EA_Dn|EA_An|EA_Immed|EA_piAn,0} },
1397: { MC_ALL, {0xfff0, 0x4e40}, {0}, {ofIOpcode}, "TRAP",{0x0f} },
1398: { MC_ALL, {0xfff8, 0x4e50}, {2}, {ofAn,ofI}, "LINK"},
1399: { MC_ALL, {0xfff8, 0x4e58}, {4}, {ofAn}, "UNLK"},
1400: { MC_ALL, {0xfff8, 0x4e60}, {4}, {ofAn,ofSpecReg}, "MOVE",{0,REG_USP} },
1401: { MC_ALL, {0xfff8, 0x4e68}, {4}, {ofSpecReg,ofAn}, "MOVE",{REG_USP,0} },
1402: { MC_ALL, {0xffff, 0x4e70}, {0}, {ofNone}, "RESET"},
1403: { MC_ALL, {0xffff, 0x4e71}, {0}, {ofNone}, "NOP"},
1404: { MC_ALL, {0xffff, 0x4e72}, {2}, {ofI}, "STOP"},
1405: { MC_ALL, {0xffff, 0x4e73}, {0}, {ofNone}, "RTE"},
1406: { MC68010|MC_020, {0xffff, 0x4e74}, {2}, {ofI}, "RTD"},
1407: { MC_ALL, {0xffff, 0x4e75}, {0}, {ofNone}, "RTS"},
1408: { MC_ALL, {0xffff, 0x4e76}, {0}, {ofNone}, "TRAPV"},
1409: { MC_ALL, {0xffff, 0x4e77}, {0}, {ofNone}, "RTR"},
1410: { MC68010|MC_020, {0xffff, 0x4e7a, 0x10000}, {4}, {ofSpecExtReg,ofExtReg}, "MOVEC"},
1411: { MC68010|MC_020, {0xffff, 0x4e7b, 0x10000}, {4}, {ofExtReg,ofSpecExtReg}, "MOVEC"},
1412: { MC_ALL, {0xffc0, 0x4e80}, {0}, {ofEa}, "JSR",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1413: { MC_ALL, {0xffc0, 0x4ec0}, {0}, {ofEa}, "JMP",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1414:
1415: { MC_ALL, {0xf1c0, 0x5000}, {1}, {ofI3,ofEa}, "ADDQ.B",{0,EA_An|EA_Immed|EA_PCRel} },
1416: { MC_ALL, {0xf1c0, 0x5040}, {2}, {ofI3,ofEa}, "ADDQ.W",{0,EA_Immed|EA_PCRel} },
1417: { MC_ALL, {0xf1c0, 0x5080}, {4}, {ofI3,ofEa}, "ADDQ.L",{0,EA_Immed|EA_PCRel} },
1418: { MC_ALL, {0xf0c0, 0x50C0}, {1}, {ofEa}, "Sci",{EA_Immed|EA_PCRel|EA_An}},
1419: { MC_ALL, {0xf0f8, 0x50C8}, {2}, {ofDn,ofDisp}, "DBcd"},
1420: { MC_020, {0xf0ff, 0x50fa}, {2}, {ofI}, "TRAPci.W"},
1421: { MC_020, {0xf0ff, 0x50fb}, {4}, {ofI}, "TRAPci.L"},
1422: { MC_020, {0xf0ff, 0x50fc}, {0}, {ofNone}, "TRAPci"},
1423: { MC_ALL, {0xf1c0, 0x5100}, {1}, {ofI3,ofEa}, "SUBQ.B",{0,EA_An|EA_Immed|EA_PCRel} },
1424: { MC_ALL, {0xf1c0, 0x5140}, {2}, {ofI3,ofEa}, "SUBQ.W",{0,EA_Immed|EA_PCRel} },
1425: { MC_ALL, {0xf1c0, 0x5180}, {4}, {ofI3,ofEa}, "SUBQ.L",{0,EA_Immed|EA_PCRel} },
1426:
1427: { MC_ALL, {0xf0ff, 0x6000}, {2}, {ofDisp}, "Bcb"},
1428: { MC_ALL, {0xf000, 0x6000}, {1}, {ofDisp}, "Bcb.S"},
1429: { MC_020, {0xf0ff, 0x60FF}, {4}, {ofDisp}, "Bcb.L"},
1430:
1431: { MC_ALL, {0xf100, 0x7000}, {0}, {ofIOpcode,ofDestDn}, "MOVEQ", {0xFF,0}},
1432:
1433: { MC_ALL, {0xf100, 0x8000}, {-1,6,2,0}, {ofEa,ofDestDn}, "OR.?", {EA_An,0}},
1434: { MC_ALL, {0xf100, 0x8100}, {-1,6,2,0}, {ofDestDn,ofEa}, "OR.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1435: { MC_ALL, {0xf1f8, 0x8100}, {1}, {ofDn,ofDestDn}, "SBCD"},
1436: { MC_ALL, {0xf1f8, 0x8108}, {1}, {ofPiAn,ofDestPiAn}, "SBCD"},
1437: { MC_020&~MC_CPU32, {0xf1f8, 0x8140, 0x10000}, {0}, {ofDn,ofDestDn,ofExtIm}, "PACK"},
1438: { MC_020&~MC_CPU32, {0xf1f8, 0x8148, 0x10000}, {0}, {ofPiAn,ofDestPiAn,ofExtIm}, "PACK"},
1439: { MC_020&~MC_CPU32, {0xf1f8, 0x8180, 0x10000}, {0}, {ofDn,ofDestDn,ofExtIm}, "UNPK"},
1440: { MC_020&~MC_CPU32, {0xf1f8, 0x8188, 0x10000}, {0}, {ofPiAn,ofDestPiAn,ofExtIm}, "UNPK"},
1441: { MC_ALL, {0xf1c0, 0x80c0}, {2}, {ofEa,ofDestDn}, "DIVU.W", {EA_An,0}},
1442: { MC_ALL, {0xf1c0, 0x81c0}, {2}, {ofEa,ofDestDn}, "DIVS.W", {EA_An,0}},
1443:
1444: { MC_ALL, {0xf1c0, 0x9000}, {1}, {ofEa,ofDestDn}, "SUB.B", {EA_An,0}},
1445: { MC_ALL, {0xf1c0, 0x9040}, {2}, {ofEa,ofDestDn}, "SUB.W"},
1446: { MC_ALL, {0xf1c0, 0x9080}, {4}, {ofEa,ofDestDn}, "SUB.L"},
1447: { MC_ALL, {0xf1c0, 0x90c0}, {2}, {ofEa,ofDestAn}, "SUBA.W"},
1448: { MC_ALL, {0xf1c0, 0x91c0}, {4}, {ofEa,ofDestAn}, "SUBA.L"},
1449: { MC_ALL, {0xf100, 0x9100}, {-1,6,2,0}, {ofDestDn,ofEa}, "SUB.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1450: { MC_ALL, {0xf138, 0x9100}, {-1,6,2,0}, {ofDn,ofDestDn}, "SUBX.?"},
1451: { MC_ALL, {0xf138, 0x9108}, {-1,6,2,0}, {ofPiAn,ofDestPiAn}, "SUBX.?"},
1452:
1453: { MC_ALL, {0xf000, 0xa000}, {0}, {ofLineA}, "LINEA"},
1454:
1455: { MC_ALL, {0xf1c0, 0xb000}, {1}, {ofEa,ofDestDn}, "CMP.B", {EA_An,0}},
1456: { MC_ALL, {0xf1c0, 0xb040}, {2}, {ofEa,ofDestDn}, "CMP.W"},
1457: { MC_ALL, {0xf1c0, 0xb080}, {4}, {ofEa,ofDestDn}, "CMP.L"},
1458: { MC_ALL, {0xf1c0, 0xb0c0}, {2}, {ofEa,ofDestAn}, "CMPA.W"},
1459: { MC_ALL, {0xf1c0, 0xb1c0}, {4}, {ofEa,ofDestAn}, "CMPA.L"},
1460: { MC_ALL, {0xf100, 0xb100}, {-1,6,2,0}, {ofDestDn,ofEa}, "EOR.?",{0,EA_An|EA_Immed|EA_PCRel} },
1461: { MC_ALL, {0xf138, 0xb108}, {-1,6,2,0}, {ofAnip,ofDestAnip}, "CMPM.?"},
1462:
1463: { MC_ALL, {0xf100, 0xc000}, {-1,6,2,0}, {ofEa,ofDestDn}, "AND.?", {EA_An,0}},
1464: { MC_ALL, {0xf100, 0xc100}, {-1,6,2,0}, {ofDestDn,ofEa}, "AND.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1465: { MC_ALL, {0xf1f8, 0xc100}, {1}, {ofDn,ofDestDn}, "ABCD"},
1466: { MC_ALL, {0xf1f8, 0xc108}, {1}, {ofPiAn,ofDestPiAn}, "ABCD"},
1467: { MC_ALL, {0xf1f8, 0xc140}, {1}, {ofDestDn,ofDn}, "EXG"},
1468: { MC_ALL, {0xf1f8, 0xc148}, {1}, {ofDestAn,ofAn}, "EXG"},
1469: { MC_ALL, {0xf1f8, 0xc188}, {1}, {ofDestDn,ofAn}, "EXG"},
1470: { MC_ALL, {0xf1c0, 0xc0c0}, {2}, {ofEa,ofDestDn}, "MULU.W", {EA_An,0}},
1471: { MC_ALL, {0xf1c0, 0xc1c0}, {2}, {ofEa,ofDestDn}, "MULS.W", {EA_An,0}},
1472:
1473: { MC_ALL, {0xf1c0, 0xd000}, {1}, {ofEa,ofDestDn}, "ADD.B", {EA_An,0}},
1474: { MC_ALL, {0xf1c0, 0xd040}, {2}, {ofEa,ofDestDn}, "ADD.W"},
1475: { MC_ALL, {0xf1c0, 0xd080}, {4}, {ofEa,ofDestDn}, "ADD.L"},
1476: { MC_ALL, {0xf1c0, 0xd0c0}, {2}, {ofEa,ofDestAn}, "ADDA.W"},
1477: { MC_ALL, {0xf1c0, 0xd1c0}, {4}, {ofEa,ofDestAn}, "ADDA.L"},
1478: { MC_ALL, {0xf100, 0xd100}, {-1,6,2,0}, {ofDestDn,ofEa}, "ADD.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1479: { MC_ALL, {0xf138, 0xd100}, {-1,6,2,0}, {ofDn,ofDestDn}, "ADDX.?"},
1480: { MC_ALL, {0xf138, 0xd108}, {-1,6,2,0}, {ofPiAn,ofDestPiAn}, "ADDX.?"},
1481:
1482: { MC_ALL, {0xf138, 0xe000}, {-1,6,2,0}, {ofI3,ofDn}, "ASR.?"},
1483: { MC_ALL, {0xf138, 0xe008}, {-1,6,2,0}, {ofI3,ofDn}, "LSR.?"},
1484: { MC_ALL, {0xf138, 0xe010}, {-1,6,2,0}, {ofI3,ofDn}, "ROXR.?"},
1485: { MC_ALL, {0xf138, 0xe018}, {-1,6,2,0}, {ofI3,ofDn}, "ROR.?"},
1486: { MC_ALL, {0xf138, 0xe020}, {-1,6,2,0}, {ofDestDn,ofDn}, "ASR.?"},
1487: { MC_ALL, {0xf138, 0xe028}, {-1,6,2,0}, {ofDestDn,ofDn}, "LSR.?"},
1488: { MC_ALL, {0xf138, 0xe030}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROXR.?"},
1489: { MC_ALL, {0xf138, 0xe038}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROR.?"},
1490: { MC_ALL, {0xf138, 0xe100}, {-1,6,2,0}, {ofI3,ofDn}, "ASL.?"},
1491: { MC_ALL, {0xf138, 0xe108}, {-1,6,2,0}, {ofI3,ofDn}, "LSL.?"},
1492: { MC_ALL, {0xf138, 0xe110}, {-1,6,2,0}, {ofI3,ofDn}, "ROXL.?"},
1493: { MC_ALL, {0xf138, 0xe118}, {-1,6,2,0}, {ofI3,ofDn}, "ROL.?"},
1494: { MC_ALL, {0xf138, 0xe120}, {-1,6,2,0}, {ofDestDn,ofDn}, "ASL.?"},
1495: { MC_ALL, {0xf138, 0xe128}, {-1,6,2,0}, {ofDestDn,ofDn}, "LSL.?"},
1496: { MC_ALL, {0xf138, 0xe130}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROXL.?"},
1497: { MC_ALL, {0xf138, 0xe138}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROL.?"},
1498: { MC_ALL, {0xffc0, 0xe0c0}, {1}, {ofEa}, "ASR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1499: { MC_ALL, {0xffc0, 0xe1c0}, {1}, {ofEa}, "ASL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1500: { MC_ALL, {0xffc0, 0xe2c0}, {1}, {ofEa}, "LSR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1501: { MC_ALL, {0xffc0, 0xe3c0}, {1}, {ofEa}, "LSL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1502: { MC_ALL, {0xffc0, 0xe4c0}, {1}, {ofEa}, "ROXR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1503: { MC_ALL, {0xffc0, 0xe5c0}, {1}, {ofEa}, "ROXL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1504: { MC_ALL, {0xffc0, 0xe6c0}, {1}, {ofEa}, "ROR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1505: { MC_ALL, {0xffc0, 0xe7c0}, {1}, {ofEa}, "ROL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1506: { MC_020&~MC_CPU32, {0xffc0, 0xe8c0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFTST",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1507: { MC_020&~MC_CPU32, {0xffc0, 0xe9c0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFEXTU",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1508: { MC_020&~MC_CPU32, {0xffc0, 0xeac0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFCHG",{EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1509: { MC_020&~MC_CPU32, {0xffc0, 0xebc0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFEXTS",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1510: { MC_020&~MC_CPU32, {0xffc0, 0xecc0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFCLR",{EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1511: { MC_020&~MC_CPU32, {0xffc0, 0xedc0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFFFO",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1512: { MC_020&~MC_CPU32, {0xffc0, 0xeec0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFSET",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1513: { MC_020&~MC_CPU32, {0xffc0, 0xefc0, 0x8000, 0x0000}, {1}, {ofExtReg,ofBFEa}, "BFINS",{0,EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1514:
1515:
1516: #define PMMU_COPROC_ID 0 // 0 is the standard PMMU
1517:
1518: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2000}, {0}, {ofSpecReg,ofEa}, "PLOADW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1519: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2001}, {0}, {ofSpecReg,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1520: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2008}, {0}, {ofExtReg0,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1521: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff0, 0x2010}, {0}, {ofExtIm4,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1522:
1523: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2200}, {0}, {ofSpecReg,ofEa}, "PLOADR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1524: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2201}, {0}, {ofSpecReg,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1525: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2208}, {0}, {ofExtReg0,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1526: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff0, 0x2210}, {0}, {ofExtIm4,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1527:
1528: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0xa000}, {0}, {ofEa}, "PFLUSHR",{EA_Dn|EA_An} },
1529:
1530: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0800}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1531: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0900}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1532: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0B00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1533: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0C00}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1534: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0C00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1535: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0D00}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1536: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0E00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1537: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0F00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1538: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4000}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1539: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4100}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1540: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4200}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1541: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4300}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1542: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4800}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1543: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4900}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1544: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4A00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1545: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4B00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1546: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4C00}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1547: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4D00}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1548: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4e00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1549: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4f00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1550: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x6000}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_MMUSR} },
1551: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x6200}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_MMUSR} },
1552:
1553: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2800}, {0}, {ofSpecReg,ofEa}, "PVALID",{REG_VAL,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1554: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2C00}, {0}, {ofExtRegA0,ofEa}, "PVALID",{0,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1555:
1556: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8000}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1557: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8001}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1558: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f8, 0x8008}, {0}, {ofExtReg0,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1559: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f0, 0x8010}, {0}, {ofExtIm4,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1560:
1561: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8200}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1562: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8201}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1563: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f8, 0x8208}, {0}, {ofExtReg0,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1564: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f0, 0x8210}, {0}, {ofExtIm4,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1565:
1566: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8100}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1567: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8101}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1568: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe318, 0x8108}, {0}, {ofExtReg0,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1569: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe310, 0x8110}, {0}, {ofExtIm4,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1570:
1571: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8300}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1572: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8301}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1573: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe318, 0x8308}, {0}, {ofExtReg0,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1574: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe310, 0x8310}, {0}, {ofExtIm4,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1575:
1576: { MC_PMMU, {0xffc0, 0xf040|(PMMU_COPROC_ID<<9), 0xfff0, 0x8310}, {0}, {ofEa}, "PScp",{EA_An|EA_Immed|EA_PCRel} },
1577: { MC_PMMU, {0xfff8, 0xf048|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000}, {2}, {ofDn,ofDisp}, "PDBcp"},
1578: { MC_PMMU, {0xffff, 0xf07A|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {2}, {ofExtIm32}, "PTRAPcp.W" },
1579: { MC_PMMU, {0xffff, 0xf07B|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {4}, {ofExtIm32}, "PTRAPcp.L" },
1580: { MC_PMMU, {0xffff, 0xf07C|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000}, {0}, {ofNone}, "PTRAPcp" },
1581: { MC_PMMU, {0xfff0, 0xf080|(PMMU_COPROC_ID<<9)}, {2}, {ofDisp}, "PBcp.W"},
1582: { MC_PMMU, {0xfff0, 0xf0C0|(PMMU_COPROC_ID<<9)}, {4}, {ofDisp}, "PBcp.L"},
1583: { MC_PMMU, {0xffc0, 0xf100|(PMMU_COPROC_ID<<9)}, {0}, {ofEa}, "PSAVE",{EA_Dn|EA_An|EA_Anip|EA_Immed} },
1584: { MC_PMMU, {0xffc0, 0xf140|(PMMU_COPROC_ID<<9)}, {0}, {ofEa}, "PRESTORE",{EA_Dn|EA_An|EA_piAn|EA_Immed} },
1585:
1586:
1587: #define MC040_COPROC_ID 3 // 3 is the code for some 68040/68060 opcodes
1588:
1589: { MC68040|MC68060, {0xfff8, 0xf000|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAnip,ofDestAbsL}, "MOVE16"},
1590: { MC68040|MC68060, {0xfff8, 0xf008|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofDestAbsL,ofAnip}, "MOVE16"},
1591: { MC68040|MC68060, {0xfff8, 0xf010|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAni,ofDestAbsL}, "MOVE16"},
1592: { MC68040|MC68060, {0xfff8, 0xf018|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofDestAbsL,ofAni}, "MOVE16"},
1593: { MC68040|MC68060, {0xfff8, 0xf020|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAnip,ofExtAnip}, "MOVE16"},
1594:
1595:
1596: #define CPU32_COPROC_ID 4 // 4 is the code for some CPU32 opcodes
1597:
1598: { MC68040|MC68060, {0xfff8, 0xf008|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_NONE} },
1599: { MC68040|MC68060, {0xfff8, 0xf048|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_DC} },
1600: { MC68040|MC68060, {0xfff8, 0xf088|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_IC} },
1601: { MC68040|MC68060, {0xfff8, 0xf0C8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_ICDC} },
1602:
1603: { MC68040|MC68060, {0xfff8, 0xf010|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_NONE} },
1604: { MC68040|MC68060, {0xfff8, 0xf050|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_DC} },
1605: { MC68040|MC68060, {0xfff8, 0xf090|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_IC} },
1606: { MC68040|MC68060, {0xfff8, 0xf0D0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_ICDC} },
1607:
1608: { MC68040|MC68060, {0xfff8, 0xf018|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_NONE} },
1609: { MC68040|MC68060, {0xfff8, 0xf058|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_DC} },
1610: { MC68040|MC68060, {0xfff8, 0xf098|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_IC} },
1611: { MC68040|MC68060, {0xfff8, 0xf0D8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_ICDC} },
1612:
1613: { MC68040|MC68060, {0xfff8, 0xf028|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_NONE} },
1614: { MC68040|MC68060, {0xfff8, 0xf068|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_DC} },
1615: { MC68040|MC68060, {0xfff8, 0xf0A8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_IC} },
1616: { MC68040|MC68060, {0xfff8, 0xf0E8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_ICDC} },
1617:
1618: { MC68040|MC68060, {0xfff8, 0xf030|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_NONE} },
1619: { MC68040|MC68060, {0xfff8, 0xf070|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_DC} },
1620: { MC68040|MC68060, {0xfff8, 0xf0B0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_IC} },
1621: { MC68040|MC68060, {0xfff8, 0xf0F0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_ICDC} },
1622:
1623: { MC68040|MC68060, {0xfff8, 0xf038|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_NONE} },
1624: { MC68040|MC68060, {0xfff8, 0xf078|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_DC} },
1625: { MC68040|MC68060, {0xfff8, 0xf0B8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_IC} },
1626: { MC68040|MC68060, {0xfff8, 0xf0F8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_ICDC} },
1627:
1628: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f08, 0x0100}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLU.?" },
1629: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0100}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLU.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1630: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f28, 0x0500}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLUN.?" },
1631: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0500}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLUN.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1632:
1633: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f08, 0x0900}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLS.?" },
1634: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0900}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLS.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1635: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f28, 0x0D00}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLSN.?" },
1636: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0D00}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLSN.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1637:
1638: { MC_CPU32, {0xffff, 0xf000|(CPU32_COPROC_ID<<9), 0xffff, 0x01C0}, {2}, {ofI}, "LPSTOP" },
1639:
1640:
1641: #define FPU_COPROC_ID 1 // 1 is the standard FPU, required to be 1 for the 68040 anyway
1642:
1643: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0000}, {-1,16+10,3,1}, {ofFPU}, "FMOVE.?" },
1644: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0001}, {-1,16+10,3,1}, {ofFPU}, "FINT.?" },
1645: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0002}, {-1,16+10,3,1}, {ofFPU}, "FSINH.?" },
1646: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0003}, {-1,16+10,3,1}, {ofFPU}, "FINTRZ.?" },
1647: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0004}, {-1,16+10,3,1}, {ofFPU}, "FSQRT.?" },
1648: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0006}, {-1,16+10,3,1}, {ofFPU}, "FLOGNP1.?" },
1649: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0008}, {-1,16+10,3,1}, {ofFPU}, "FETOXM1.?" },
1650: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0009}, {-1,16+10,3,1}, {ofFPU}, "FTANH.?" },
1651: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000A}, {-1,16+10,3,1}, {ofFPU}, "FATAN.?" },
1652: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000C}, {-1,16+10,3,1}, {ofFPU}, "FASIN.?" },
1653: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000D}, {-1,16+10,3,1}, {ofFPU}, "FATANH.?" },
1654: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000E}, {-1,16+10,3,1}, {ofFPU}, "FSIN.?" },
1655: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000F}, {-1,16+10,3,1}, {ofFPU}, "FTAN.?" },
1656: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0010}, {-1,16+10,3,1}, {ofFPU}, "FETOX.?" },
1657: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0011}, {-1,16+10,3,1}, {ofFPU}, "FTWOTOX.?" },
1658: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0012}, {-1,16+10,3,1}, {ofFPU}, "FTENTOX.?" },
1659: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0014}, {-1,16+10,3,1}, {ofFPU}, "FLOGN.?" },
1660: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0015}, {-1,16+10,3,1}, {ofFPU}, "FLOG10.?" },
1661: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0016}, {-1,16+10,3,1}, {ofFPU}, "FLOG2.?" },
1662: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0018}, {-1,16+10,3,1}, {ofFPU}, "FABS.?" },
1663: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0019}, {-1,16+10,3,1}, {ofFPU}, "FCOSH.?" },
1664: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001A}, {-1,16+10,3,1}, {ofFPU}, "FNEG.?" },
1665: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001C}, {-1,16+10,3,1}, {ofFPU}, "FACOS.?" },
1666: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001D}, {-1,16+10,3,1}, {ofFPU}, "FCOS.?" },
1667: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001E}, {-1,16+10,3,1}, {ofFPU}, "FGETEXP.?" },
1668: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001F}, {-1,16+10,3,1}, {ofFPU}, "FGETMAN.?" },
1669: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0020}, {-1,16+10,3,1}, {ofFPU}, "FDIV.?" },
1670: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0021}, {-1,16+10,3,1}, {ofFPU}, "FMOD.?" },
1671: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0022}, {-1,16+10,3,1}, {ofFPU}, "FADD.?" },
1672: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0023}, {-1,16+10,3,1}, {ofFPU}, "FMUL.?" },
1673: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0024}, {-1,16+10,3,1}, {ofFPU}, "FSGLDIV.?" },
1674: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0025}, {-1,16+10,3,1}, {ofFPU}, "FREM.?" },
1675: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0026}, {-1,16+10,3,1}, {ofFPU}, "FSCALE.?" },
1676: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0027}, {-1,16+10,3,1}, {ofFPU}, "FSGLMUL.?" },
1677: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0028}, {-1,16+10,3,1}, {ofFPU}, "FSUB.?" },
1678: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA078,0x0030}, {-1,16+10,3,1}, {ofFPU3Reg}, "FSINCOS.?" },
1679: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0038}, {-1,16+10,3,1}, {ofFPU}, "FCMP.?" },
1680: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x003A}, {-1,16+10,3,1}, {ofFPU}, "FTST.?" },
1681: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0040}, {-1,16+10,3,1}, {ofFPU}, "FSMOVE.?" },
1682: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0041}, {-1,16+10,3,1}, {ofFPU}, "FSSQRT.?" },
1683: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0042}, {-1,16+10,3,1}, {ofFPU}, "FSADD.?" },
1684: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0044}, {-1,16+10,3,1}, {ofFPU}, "FDMOVE.?" },
1685: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0045}, {-1,16+10,3,1}, {ofFPU}, "FDSQRT.?" },
1686: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0046}, {-1,16+10,3,1}, {ofFPU}, "FDADD.?" },
1687: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0058}, {-1,16+10,3,1}, {ofFPU}, "FSABS.?" },
1688: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005A}, {-1,16+10,3,1}, {ofFPU}, "FSNEG.?" },
1689: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005C}, {-1,16+10,3,1}, {ofFPU}, "FDABS.?" },
1690: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005E}, {-1,16+10,3,1}, {ofFPU}, "FDNEG.?" },
1691: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0060}, {-1,16+10,3,1}, {ofFPU}, "FSDIV.?" },
1692: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0063}, {-1,16+10,3,1}, {ofFPU}, "FSMUL.?" },
1693: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0064}, {-1,16+10,3,1}, {ofFPU}, "FDDIV.?" },
1694: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0067}, {-1,16+10,3,1}, {ofFPU}, "FDMUL.?" },
1695: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0068}, {-1,16+10,3,1}, {ofFPU}, "FSSUB.?" },
1696: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x006C}, {-1,16+10,3,1}, {ofFPU}, "FDSUB.?" },
1697: { MC68040|MC_FPU, {0xffff, 0xf000|(FPU_COPROC_ID<<9),0xFC00,0x5C00}, {0}, {ofFMOVECR}, "FMOVECR" },
1698:
1699: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE000,0x6000}, {-1,16+10,3,1}, {ofFPUMOVE}, "FMOVE.?" },
1700:
1701: // these 3 are special versions of MOVEM with just one register, they have to be before the FMOVEM version
1702: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x8400}, {0}, {ofEa,ofSpecReg}, "FMOVE", {0,REG_FPU_FPIAR} },
1703: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x8800}, {0}, {ofEa,ofSpecReg}, "FMOVE", {EA_An,REG_FPU_FPSR} },
1704: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x9000}, {0}, {ofEa,ofSpecReg}, "FMOVE", {EA_An,REG_FPU_FPCR} },
1705: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE3FF,0x8000}, {0}, {ofEa,ofFPUSRRegList}, "FMOVEM", {EA_Dn|EA_An,0} },
1706: // these 3 are special versions of MOVEM with just one register, they have to be before the FMOVEM version
1707: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xA400}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPIAR,EA_Immed|EA_PCRel} },
1708: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xA800}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPSR,EA_An|EA_Immed|EA_PCRel} },
1709: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xB000}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPCR,EA_An|EA_Immed|EA_PCRel} },
1710: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE3FF,0xA000}, {0}, {ofFPUSRRegList,ofEa}, "FMOVEM", {0,EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1711:
1712: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE00,0xC000}, {0}, {ofFPUReglist,ofEa}, "FMOVEM.X",{0,EA_Dn|EA_An|EA_Anip|EA_Immed} },
1713: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE8F,0xC800}, {0}, {ofExtRegD04,ofEa}, "FMOVEM.X",{0,EA_Dn|EA_An|EA_piAn|EA_Immed} },
1714: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE00,0xE000}, {0}, {ofEa,ofFPUReglist}, "FMOVEM.X",{EA_Dn|EA_An|EA_piAn|EA_Immed,0} },
1715: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE8F,0xE800}, {0}, {ofEa,ofExtRegD04}, "FMOVEM.X",{EA_Dn|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1716:
1717: { MC68040|MC_FPU, {0xffc0, 0xf040|(FPU_COPROC_ID<<9),0xFFC0,0x0000}, {0}, {ofEa}, "FScf.B",{EA_An|EA_Immed|EA_PCRel} },
1718: { MC68040|MC_FPU, {0xfff8, 0xf048|(FPU_COPROC_ID<<9),0xFFC0,0x0000}, {2}, {ofDn,ofDisp}, "FDBcf" },
1719: { MC68040|MC_FPU, {0xffff, 0xf07A|(FPU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {2}, {ofExtIm32}, "FTRAPcf.W" },
1720: { MC68040|MC_FPU, {0xffff, 0xf07B|(FPU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {4}, {ofExtIm32}, "FTRAPcf.L" },
1721: { MC68040|MC_FPU, {0xffff, 0xf07C|(FPU_COPROC_ID<<9), 0xfff0, 0x0000}, {0}, {ofNone}, "FTRAPcf" },
1722:
1723: // FNOP _has_ to be before FBcf.W, not worth to have a special case for that one
1724: { MC68040|MC_FPU, {0xffff, 0xf080|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {0}, {ofNone}, "FNOP" },
1725: { MC68040|MC_FPU, {0xffc0, 0xf080|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {2}, {ofDisp}, "FBcF.W" },
1726: { MC68040|MC_FPU, {0xffc0, 0xf0c0|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {4}, {ofDisp}, "FBcF.L" },
1727: { MC68040|MC68060|MC_FPU, {0xffc0, 0xf100|(FPU_COPROC_ID<<9)}, {0}, {ofEa}, "FSAVE", {EA_Dn|EA_An|EA_piAn|EA_Immed} },
1728: { MC68040|MC68060|MC_FPU, {0xffc0, 0xf140|(FPU_COPROC_ID<<9)}, {0}, {ofEa}, "FRESTORE", {EA_Dn|EA_An|EA_piAn|EA_Immed} },
1729:
1.1.1.4 root 1730: { 0 }
1.1 root 1731: };
1732:
1733: static int Disass68k(long addr, char *labelBuffer, char *opcodeBuffer, char *operandBuffer, char *commentBuffer)
1734: {
1735: long baseAddr = addr;
1736: int val;
1.1.1.4 root 1737: int i;
1738: int count = 0;
1739: char addressLabel[256];
1740: char cmtBuffer[256];
1741: Disass68kDataType type;
1742: int index;
1743: long opcodeAddr;
1744:
1.1 root 1745: labelBuffer[0] = 0;
1746: opcodeBuffer[0] = 0;
1747: operandBuffer[0] = 0;
1748: commentBuffer[0] = 0;
1749:
1.1.1.4 root 1750: type = Disass68kType(baseAddr, addressLabel, cmtBuffer, &count);
1.1 root 1751: if(addressLabel[0])
1752: sprintf(labelBuffer, "%s:", addressLabel);
1753: sprintf(commentBuffer, "%s", cmtBuffer);
1754: switch(type)
1755: {
1.1.1.4 root 1756: case dtByte:
1757: if(count > 8)
1758: count = 8;
1759: strcpy(opcodeBuffer,"DC.B");
1760: for (i = 0; i < count; ++i)
1761: {
1762: char hbuf[16];
1763: unsigned short val;
1764:
1765: if((i & 7) > 0)
1766: strcat(operandBuffer, ",");
1767: val = Disass68kGetWord(addr+(i & ~1));
1768: if(i & 1)
1769: val &= 0xFF;
1770: else
1771: val = val >> 8;
1772: sprintf(hbuf,"$%2.2x", val);
1773: strcat(operandBuffer, hbuf);
1774: }
1775: return count;
1776:
1777: case dtWord:
1778: if(count > 4)
1779: count = 4;
1780: strcpy(opcodeBuffer,"DC.W");
1781: for (i = 0; i < count; ++i)
1782: {
1783: char hbuf[16];
1784: if((i & 3) > 0)
1785: strcat(operandBuffer, ",");
1786: sprintf(hbuf,"$%4.4x", Disass68kGetWord(addr+i*2));
1787: strcat(operandBuffer, hbuf);
1788: }
1789: return count * 2;
1790:
1791: case dtLong:
1792: if(count > 2)
1793: count = 2;
1794: strcpy(opcodeBuffer,"DC.L");
1795: for (i = 0; i < count; ++i)
1796: {
1797: char hbuf[16];
1798: if((i & 1) > 0)
1799: strcat(operandBuffer, ",");
1800: sprintf(hbuf,"$%8.8x", (Disass68kGetWord(addr+i*4) << 16) | Disass68kGetWord(addr+i*4+2));
1801: strcat(operandBuffer, hbuf);
1802: }
1803: return count * 4;
1.1 root 1804:
1805: case dtStringArray:
1.1.1.4 root 1806: {
1807: char *sp;
1808: strcpy(opcodeBuffer,"DC.B");
1809: strcat(operandBuffer, "'");
1810: sp = operandBuffer + strlen(operandBuffer);
1811: for (i = 0; i < count; ++i)
1812: {
1813: unsigned short val = Disass68kGetWord(addr+(i & ~1));
1814: if(i & 1)
1815: val &= 0xFF;
1816: else
1817: val = val >> 8;
1818: if(val == 0)
1819: break;
1820: switch(val)
1821: {
1822: case 9: *sp++ = '\\'; *sp++ = 't'; break;
1823: case 10: *sp++ = '\\'; *sp++ = 'n'; break;
1824: case 13: *sp++ = '\\'; *sp++ = 'r'; break;
1825: default:
1826: if(val >= 0x20 && val <= 0x7E)
1827: *sp++ = val;
1828: }
1829: }
1830: *sp = 0;
1831: strcat(sp, "'");
1832: return count;
1833: }
1.1 root 1834:
1835: case dtASCString:
1.1.1.4 root 1836: {
1837: int count = 1;
1838: unsigned short val = Disass68kGetWord(addr+0);
1839: strcpy(opcodeBuffer,"DC.B");
1840: if((val >> 8) == 0)
1841: {
1842: strcat(operandBuffer, "0");
1843: } else {
1844: char *sp;
1845: strcat(operandBuffer, "'");
1846: sp = operandBuffer + strlen(operandBuffer);
1847: for(i=0; ; ++i)
1848: {
1849: unsigned short val = Disass68kGetWord(addr+(i & ~1));
1850: if(i & 1)
1851: val &= 0xFF;
1852: else
1853: val = val >> 8;
1854: if(val == 0)
1855: break;
1856: switch(val)
1.1 root 1857: {
1.1.1.4 root 1858: case 9: *sp++ = '\\'; *sp++ = 't'; break;
1859: case 10: *sp++ = '\\'; *sp++ = 'n'; break;
1860: case 13: *sp++ = '\\'; *sp++ = 'r'; break;
1861: default:
1862: if(val >= 0x20 && val <= 0x7E)
1863: *sp++ = val;
1.1 root 1864: }
1.1.1.4 root 1865: ++count;
1866: }
1867: *sp = 0;
1868: strcat(sp, "',0");
1869: }
1870: return (count + 1) & ~1;
1871: }
1.1 root 1872:
1873: case dtPointer:
1874: case dtFunctionPointer:
1.1.1.4 root 1875: {
1876: const char *sp;
1877: val = (Disass68kGetWord(addr) << 16) | Disass68kGetWord(addr+2);
1878: sp = Disass68kSymbolName(val, 2);
1879: strcpy(opcodeBuffer,"DC.L");
1880: if(sp)
1881: sprintf(operandBuffer,"%s", sp);
1882: else
1.1.1.6 ! root 1883: sprintf(operandBuffer,"$%8.8x", val);
1.1.1.4 root 1884: return 4;
1885: }
1.1 root 1886:
1887: default: break;
1888: }
1889:
1.1.1.4 root 1890: index = 0;
1891: opcodeAddr = addr;
1.1 root 1892: more:
1893: addr = opcodeAddr;
1894:
1895: opcodeBuffer[0] = 0;
1896: operandBuffer[0] = 0;
1897:
1898: commentBuffer[0] = 0;
1899: if(cmtBuffer[0])
1900: sprintf(commentBuffer, "%s ", cmtBuffer);
1901:
1902: while(1)
1903: {
1.1.1.4 root 1904: unsigned short opcode[5];
1905: unsigned int i;
1.1 root 1906: OpcodeTableStruct *ots = &OpcodeTable[index++];
1.1.1.4 root 1907: int size;
1908: char sizeChar = 0;
1909: char *dbuf;
1910: int ea;
1.1.1.5 root 1911: unsigned int maxop;
1.1.1.4 root 1912:
1.1 root 1913: if(ots->opcodeName == NULL)
1914: break;
1915: if((ots->cpuMask & optionCPUTypeMask) == 0) // CPU doesn't match?
1916: continue;
1917:
1918: // search for the opcode plus up to 2 extension words
1919: for(i=0; i<5; ++i)
1920: {
1921: if(!ots->opcodeMask[i*2])
1.1.1.4 root 1922: {
1923: opcode[i] = 0;
1.1 root 1924: break;
1.1.1.4 root 1925: }
1.1 root 1926: opcode[i] = Disass68kGetWord(addr);
1927: if(((ots->opcodeMask[i*2] & 0xFFFF) & opcode[i]) != ots->opcodeMask[i*2+1])
1928: goto more;
1929: addr += 2;
1930: }
1931:
1932: // find out the size of the opcode operand
1.1.1.4 root 1933: size = ots->operationSize[0];
1.1 root 1934: if(size < 0) // custom size?
1935: {
1936: int opcodeOffset = ots->operationSize[1] >> 4;
1937: int bitShiftOffset = ots->operationSize[1] & 0x0F;
1938: int sizeBitMask = (opcode[opcodeOffset] >> bitShiftOffset) & ((1 << ots->operationSize[2]) - 1);
1939: switch(ots->operationSize[3])
1940: {
1941: case 0: // 2 Bit Size
1942: switch(sizeBitMask)
1943: {
1944: case 0: size = 1; sizeChar = 'B'; break;
1945: case 1: size = 2; sizeChar = 'W'; break;
1946: case 2: size = 4; sizeChar = 'L'; break;
1947: case 3: goto more; // illegal size mask
1948: }
1949: break;
1950: case 1: // 3 Bit FPU Size
1951: if((opcode[1] & 0x4000) == 0x0000) // Register => Register?
1952: sizeBitMask = 2; // => 'X' Format
1953: switch(sizeBitMask)
1954: {
1955: case 0: size = 4; sizeChar = 'L'; break;
1956: case 1: size = 4; sizeChar = 'S'; break;
1957: case 2: size = 12; sizeChar = 'X'; break;
1958: case 7: if((opcode[1] & 0xE000) != 0x6000) // MOVE.P <ea>,FPn{Dn-Factor}
1959: goto more; // illegal size mask
1960: case 3: size = 12; sizeChar = 'P'; break;
1961: case 4: size = 2; sizeChar = 'W'; break;
1962: case 5: size = 8; sizeChar = 'D'; break;
1963: case 6: size = 1; sizeChar = 'B'; break;
1964: }
1965: break;
1966: }
1967: }
1968:
1969: // copy the opcode plus a necessary TAB for the operand
1.1.1.4 root 1970: dbuf = opcodeBuffer;
1.1 root 1971: for(i=0; ots->opcodeName[i]; ++i)
1972: {
1973: char c = ots->opcodeName[i];
1974: if(c == 'c') // condition code
1975: {
1976: static const char *pmmuCond[16] = { "BS", "BC", "LS", "LC", "SS", "SC", "AS", "AC", "WS", "WC", "IS", "IC", "GS", "GC", "CS", "CC" };
1977: static const char *braCond[16] = { "RA", "SR", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1978: static const char *sccCond[16] = { "T", "F", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1979: static const char *dbCond[16] = { "T", "RA", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1980: static const char *fpuCond[64] = { "F", "EQ", "OGT", "OGE", "OLT", "OLE", "OGL", "OR", "UN", "UEQ", "UGT", "UGE", "ULT", "ULE", "NE", "T", "SF", "SEQ", "GT", "GE", "LT", "LE", "GL", "GLE", "NGLE", "NGL", "NLE", "NLT", "NGE", "NGT", "SNE", "ST" };
1.1.1.4 root 1981: char buf[8];
1.1 root 1982:
1983: const char *sp = NULL;
1984: switch(ots->opcodeName[++i])
1985: {
1986: case 'p': // PMMU conditions
1987: sp = pmmuCond[opcode[1] & 0xF];
1988: break;
1989: case 'b': // BRA conditions
1990: sp = braCond[(opcode[0] >> 8) & 0xF];
1991: break;
1992: case 'i': // Scc,TRAPcc conditions
1993: sp = sccCond[(opcode[0] >> 8) & 0xF];
1994: break;
1995: case 'd': // DBcc conditions
1996: sp = dbCond[(opcode[0] >> 8) & 0xF];
1997: break;
1998: case 'F': // FPU conditions (first word)
1999: sp = fpuCond[opcode[0] & 0x3F];
2000: break;
2001: case 'f': // FPU conditions (second word)
2002: sp = fpuCond[opcode[1] & 0x3F];
2003: break;
2004: }
2005: if(sp)
2006: {
2007: if(options & doptOpcodesSmall)
2008: {
1.1.1.4 root 2009: char *bp;
1.1 root 2010: strcpy(buf, sp);
2011: sp = buf;
1.1.1.4 root 2012: for (bp = buf; *bp; ++bp)
1.1.1.5 root 2013: *bp = tolower((unsigned char)*bp);
1.1 root 2014: }
2015: strcpy(dbuf, sp);
2016: dbuf += strlen(sp);
2017: continue;
2018: }
2019: goto more;
2020: }
2021: if(c == '?') // size mask
2022: c = sizeChar;
2023: if(options & doptOpcodesSmall)
1.1.1.5 root 2024: c = tolower((unsigned char)c);
1.1 root 2025: *dbuf++ = c;
2026: }
2027: *dbuf = 0;
2028:
2029: // Parse the EAs for all operands
1.1.1.4 root 2030: ea = opcode[0] & 0x3F;
1.1 root 2031: dbuf = operandBuffer;
1.1.1.5 root 2032:
2033: maxop=(sizeof(ots->op)/sizeof(ots->op[0]));
2034: for(i=0; i<maxop; ++i)
1.1 root 2035: {
1.1.1.4 root 2036: int reg;
2037:
1.1 root 2038: switch(ots->op[i])
2039: {
2040: case ofNone: // nothing
2041: break;
2042:
2043: case ofEa:
2044: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, EA_All & ~(ots->parameter[i]), 0, ots->disassFlag);
2045: break;
2046:
2047: case ofDn:
2048: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2049: break;
2050: case ofAn:
2051: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x08, size, EA_An, 0, ots->disassFlag);
2052: break;
2053: case ofAni:
2054: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x10, size, EA_Ani, 0, ots->disassFlag);
2055: break;
2056: case ofAnip:
2057: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2058: break;
2059: case ofPiAn:
2060: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x20, size, EA_piAn, 0, ots->disassFlag);
2061: break;
2062: case ofD16An:
2063: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x28, size, EA_dAn, 0, ots->disassFlag);
2064: break;
2065:
2066: case ofI:
2067: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x3C, size, EA_Immed, 0, ots->disassFlag);
2068: break;
2069:
2070: case ofDestDn:
2071: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2072: break;
2073: case ofDestAn:
2074: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x08, size, EA_An, 0, ots->disassFlag);
2075: break;
2076: case ofDestAnip:
2077: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2078: break;
2079: case ofDestPiAn:
2080: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x20, size, EA_piAn, 0, ots->disassFlag);
2081: break;
2082: case ofDestEa6:
2083: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | (((opcode[0] >> 6) & 0x7) << 3), size, EA_Dest-EA_An, 0, ots->disassFlag);
2084: break;
2085: case ofDestAbsL:
2086: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x39, size, EA_Abs, 0, ots->disassFlag);
2087: break;
2088:
2089: case ofIOpcode:
2090: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, opcode[0] & ots->parameter[i], ots->disassFlag);
2091: break;
2092: case ofI3:
2093: val = ((opcode[0] >> 9) & 7);
2094: if(!val) val = 8;
2095: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, val, ots->disassFlag);
2096: break;
2097: case ofExtIm:
2098: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, opcode[1], ots->disassFlag);
2099: break;
2100: case ofExtIm32:
2101: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, size, EA_ImmedParameter, opcode[2], ots->disassFlag);
2102: break;
2103: case ofExtIm4:
2104: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, opcode[1] & 0x0F, ots->disassFlag);
2105: break;
2106: case ofExtIm10:
2107: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, (opcode[1] >> 10) & 0x07, ots->disassFlag);
2108: break;
2109: case ofSpecReg:
2110: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0101, size, EA_SpecialRegister, ots->parameter[i], ots->disassFlag);
2111: break;
2112: case ofSpecExtReg:
2113: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0101, size, EA_SpecialRegister, opcode[1] & 0xFFF, ots->disassFlag);
2114: break;
2115: case ofExtReg0:
2116: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2117: break;
2118: case ofExtRegA0:
2119: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07) | 0x08, size, EA_An, 0, ots->disassFlag);
2120: break;
2121: case ofExtRegD04:
2122: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 4) & 0x07) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2123: break;
2124: case ofExtRegA05:
2125: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 5) & 0x07) | 0x08, size, EA_An, 0, ots->disassFlag);
2126: break;
2127: case ofExtReg:
2128: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2129: break;
2130: case ofExtAnip:
2131: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2132: break;
2133:
2134: case ofDisp:
2135: // branch treats the displacement 0x00 and 0xFF as an indicator how many words follow
2136: // This test will decline a displacement with the wrong word offset
2137: if((opcode[0] & 0xF000) == 0x6000)
2138: {
2139: val = opcode[0] & 0xFF;
2140: if(val == 0x00 && size != 2) goto more;
2141: if(val == 0xFF && size != 4) goto more;
2142: }
2143: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0102, size, EA_PCDisplacement, opcode[0] & 0xFF, ots->disassFlag);
2144: break;
2145:
2146: case ofRegList:
2147: val = opcode[1];
2148: if((ea & 0x38) == 0x20) // -(An) has a flipped bitmask
2149: val = Disass68kFlipBits(val);
2150: dbuf = Disass68kReglist(dbuf, val);
2151: break;
2152:
2153: case ofFPU:
2154: { // default FPU opcode modes
2155: int src = (opcode[1] >> 10) & 7;
2156: int dest = (opcode[1] >> 7) & 7;
2157: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2158: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2159: if(opcode[1] & 0x4000)
2160: {
2161: // <ea>,FPn
2162: int mask = EA_All - EA_An;
2163: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2164: mask -= EA_Dn;
2165: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2166: if(!dbuf) goto more;
2167: *dbuf++ = ',';
2168: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2169: *dbuf = 0;
2170: } else {
2171: // FPn,FPn or FPn
2172:
2173: // <ea> has to be 0
2174: if((opcode[0] & 0x3F) != 0) goto more;
2175:
2176: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+src;
2177: if(src != dest)
2178: {
2179: *dbuf++ = ',';
2180: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2181: }
2182: *dbuf = 0;
2183: }
2184: }
2185: break;
2186: case ofFPUMOVE:
2187: { // MOVE <ea>,FPn{k-Factor}
2188: int src = (opcode[1] >> 10) & 7;
2189: // <ea>,FPn
2190: int mask = EA_All - EA_An;
2191: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2192: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2193: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2194: mask -= EA_Dn;
2195: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2196: if(!dbuf) goto more;
2197: *dbuf++ = ',';
2198: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+((opcode[1] >> 7) & 7);
2199: if(src == 3)
2200: {
2201: int kFactor = opcode[1] & 0x7F;
2202: if(kFactor & 0x40)
2203: kFactor |= 0x80;
2204: *dbuf++ = '{';
2205: sprintf(dbuf, "%d", (signed char)kFactor);
2206: dbuf += strlen(dbuf);
2207: *dbuf++ = '}';
2208: } else if(src == 7)
2209: {
2210: if((opcode[1] & 0x0F) != 0) goto more;
2211: *dbuf++ = '{';
2212: *dbuf++ = options & doptRegisterSmall ? 'd' : 'D';
2213: *dbuf++ = '0' + ((opcode[1] >> 4) & 7);
2214: *dbuf++ = '}';
2215: } else {
2216: if((opcode[1] & 0x7F) != 0) goto more;
2217: }
2218: *dbuf = 0;
2219: }
2220: break;
2221: case ofFMOVECR:
2222: { // MOVECR #const,FPn
2223: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2224: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2225: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, opcode[1] & 0x7F, ots->disassFlag);
2226: if(!dbuf) goto more;
1.1.1.4 root 2227: reg = (opcode[1] >> 7) & 7;
1.1 root 2228: *dbuf++ = ',';
2229: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+reg;
2230: *dbuf = 0;
2231: switch(opcode[1] & 0x7F) // document the well-known constants
2232: {
2233: case 0x00: strcat(commentBuffer, "PI"); break;
2234: case 0x0B: strcat(commentBuffer, "Log10(2)"); break;
2235: case 0x0C: strcat(commentBuffer, "e"); break;
2236: case 0x0D: strcat(commentBuffer, "Log2(e)"); break;
2237: case 0x0E: strcat(commentBuffer, "Log10(e)"); break;
2238: case 0x0F: strcat(commentBuffer, "0.0"); break;
2239: case 0x30: strcat(commentBuffer, "1n(2)"); break;
2240: case 0x31: strcat(commentBuffer, "1n(10)"); break;
2241: case 0x32: strcat(commentBuffer, "100"); break;
2242: case 0x33: strcat(commentBuffer, "10^1"); break;
2243: case 0x34: strcat(commentBuffer, "10^2"); break;
2244: case 0x35: strcat(commentBuffer, "10^4"); break;
2245: case 0x36: strcat(commentBuffer, "10^8"); break;
2246: case 0x37: strcat(commentBuffer, "10^16"); break;
2247: case 0x38: strcat(commentBuffer, "10^32"); break;
2248: case 0x39: strcat(commentBuffer, "10^64"); break;
2249: case 0x3A: strcat(commentBuffer, "10^128"); break;
2250: case 0x3B: strcat(commentBuffer, "10^256"); break;
2251: case 0x3C: strcat(commentBuffer, "10^512"); break;
2252: case 0x3D: strcat(commentBuffer, "10^1024"); break;
2253: case 0x3E: strcat(commentBuffer, "10^2048"); break;
2254: case 0x3F: strcat(commentBuffer, "10^4096"); break;
2255: }
2256: }
2257: break;
2258: case ofFPUSRRegList:
2259: {
2260: int hasReg = 0;
2261: *dbuf = 0;
2262: if(opcode[1] & 0x0400)
2263: {
2264: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPIAR));
2265: hasReg = 1;
2266: }
2267: if(opcode[1] & 0x0800)
2268: {
2269: if(hasReg) strcat(dbuf, "/");
2270: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPSR));
2271: hasReg = 1;
2272: }
2273: if(opcode[1] & 0x1000)
2274: {
2275: if(hasReg) strcat(dbuf, "/");
2276: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPCR));
2277: hasReg = 1;
2278: }
2279: if(!hasReg)
2280: strcat(dbuf, "0");
2281: dbuf += strlen(dbuf);
2282: }
2283: break;
2284: case ofFPUReglist: // FMOVEM
2285: {
2286: int mask = opcode[1] & 0xFF;
2287: if(opcode[1] & 0x0100)
2288: mask = Disass68kFlipBits(mask) >> 8;
2289: dbuf = Disass68kFPUReglist(dbuf, mask);
2290: }
2291: break;
2292: case ofFPU3Reg:
2293: { // FSINCOS
2294: int src = (opcode[1] >> 10) & 7;
2295: int dest = (opcode[1] >> 7) & 7;
2296: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2297: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2298: if(opcode[1] & 0x4000)
2299: {
2300: // <ea>,FPn
2301: int mask = EA_All - EA_An;
2302: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2303: mask -= EA_Dn;
2304: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2305: if(!dbuf) goto more;
2306: *dbuf++ = ',';
2307: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+(opcode[1] & 7);
2308: *dbuf++ = ',';
2309: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2310: *dbuf = 0;
2311: } else {
2312: // FPn,FPn or FPn
2313:
2314: // <ea> has to be 0
2315: if((opcode[0] & 0x3F) != 0) goto more;
2316:
2317: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+src;
2318: *dbuf++ = ',';
2319: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+(opcode[1] & 7);
2320: *dbuf++ = ',';
2321: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2322: *dbuf = 0;
2323: }
2324: }
2325: break;
2326:
2327: case ofCAS:
2328: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2329: if(!dbuf) goto more;
2330: *dbuf++ = ',';
2331: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2332: break;
2333: case ofCAS2:
2334: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2335: if(!dbuf) goto more;
2336: *dbuf++ = ':';
2337: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[2] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2338: if(!dbuf) goto more;
2339: *dbuf++ = ',';
2340: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2341: if(!dbuf) goto more;
2342: *dbuf++ = ':';
2343: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[2] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2344: if(!dbuf) goto more;
2345: *dbuf++ = ',';
2346: *dbuf++ = '(';
2347: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2348: if(!dbuf) goto more;
2349: *dbuf++ = ')';
2350: *dbuf++ = ':';
2351: *dbuf++ = '(';
2352: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[2] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2353: if(!dbuf) goto more;
2354: *dbuf++ = ')';
2355: *dbuf = 0;
2356: break;
2357: case ofExt4Dn:
2358: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[0] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2359: if(!dbuf) goto more;
2360: *dbuf++ = ':';
2361: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2362: if(!dbuf) goto more;
2363: *dbuf++ = ',';
2364: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2365: if(!dbuf) goto more;
2366: *dbuf = 0;
2367: break;
2368: case ofBFEa:
2369: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, EA_All & ~(ots->parameter[i]), 0, ots->disassFlag);
2370: if(!dbuf) goto more;
2371: *dbuf++ = '{';
2372: val = (opcode[1] >> 6) & 0x1F;
2373: if(opcode[1] & 0x0800)
2374: {
2375: if(val & 0x18) goto more;
2376: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, val & 0x07, 1, EA_Dn, val, ots->disassFlag);
2377: } else {
2378: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0103, 1, EA_ValueParameter, val, ots->disassFlag);
2379: }
2380: *dbuf++ = ':';
2381: val = opcode[1] & 0x1F;
2382: if(opcode[1] & 0x0020)
2383: {
2384: if(val & 0x18) goto more;
2385: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, val & 0x07, 1, EA_Dn, val, ots->disassFlag);
2386: } else {
2387: if(val == 0) val = 32;
2388: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0103, 1, EA_ValueParameter, val, ots->disassFlag);
2389: }
2390: *dbuf++ = '}';
2391: *dbuf = 0;
2392: break;
2393: case ofLineA:
2394: {
2395: int lineAVal = opcode[0] & 0xFFF;
2396: const char *lineAStr[16] = { "Line-A Initialization",
2397: "Put pixel",
2398: "Get pixel",
2399: "Arbitrary line",
2400: "Horizontal line",
2401: "Filled rectangle",
2402: "Filled polygon",
2403: "Bit block transfer",
2404: "Text block transfer",
2405: "Show mouse",
2406: "Hide mouse",
2407: "Transform mouse",
2408: "Undraw sprite",
2409: "Draw sprite",
2410: "Copy raster form",
2411: "Seedfill"
2412: };
1.1.1.4 root 2413: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, lineAVal, ots->disassFlag);
1.1 root 2414: if(lineAVal < 16)
2415: strcat(commentBuffer, lineAStr[lineAVal]);
2416: }
2417: break;
2418:
2419: default:
2420: goto more;
2421: }
2422: if(!dbuf) goto more;
2423:
2424: // does another operand follow => add separator
1.1.1.5 root 2425: if ( (i+1<maxop) && ( ots->op[i+1] != ofNone) )
1.1 root 2426: *dbuf++ = ',';
2427: }
2428: return addr-baseAddr;
2429: }
2430:
2431: // unknown opcode
2432: strcpy(opcodeBuffer, "DC.W");
2433: sprintf(operandBuffer,"$%4.4x", Disass68kGetWord(addr));
2434: return 2;
2435: }
2436:
2437: static void Disass68kComposeStr(char *dbuf, const char *str, int position, int maxPos)
2438: {
2439: int i;
2440: int len = strlen(dbuf);
2441: while(len < position) {
2442: dbuf[len++] = ' '; /* Will give harmless warning from GCC */
2443: }
2444: for(i=0; str[i] && (!maxPos || len+i<maxPos); ++i)
2445: dbuf[len+i] = str[i];
2446: if(str[i])
2447: dbuf[len+i-1] = '+';
2448: dbuf[len+i] = 0;
2449: }
2450:
2451: static void Disass68k_loop (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
2452: {
2453: static bool isInit = false;
2454: if(!isInit)
2455: {
2456: Disass68kInit(Paths_GetHatariHome());
2457: isInit = true;
2458: }
2459:
1.1.1.4 root 2460: while (cnt-- > 0) {
1.1.1.6 ! root 2461: const int addrWidth = 8; // 6 on an ST (24 bit addressing), 8 on a TT (32 bit addressing)
1.1 root 2462: char lineBuffer[1024];
2463:
2464: char addressBuffer[32];
2465: char hexdumpBuffer[256];
2466: char labelBuffer[256];
2467: char opcodeBuffer[64];
2468: char operandBuffer[256];
2469: char commentBuffer[256];
1.1.1.4 root 2470: int plen, len, j;
2471:
2472: len = Disass68k(addr, labelBuffer, opcodeBuffer, operandBuffer, commentBuffer);
1.1 root 2473: if(!len) break;
2474:
2475: sprintf(addressBuffer, "$%*.*x :", addrWidth,addrWidth, addr);
2476:
2477: hexdumpBuffer[0] = 0;
1.1.1.4 root 2478: plen = len;
1.1 root 2479: if(plen > 80 && (!strncmp(opcodeBuffer, "DC.", 3) || !strncmp(opcodeBuffer, "dc.", 3)))
2480: plen = ((optionPosLabel - optionPosHexdump) / 5) * 2;
1.1.1.4 root 2481:
1.1 root 2482: for(j=0; j<plen; j += 2)
2483: {
2484: if(j > 0)
2485: strcat(hexdumpBuffer, " ");
2486: if(j + 2 > plen)
2487: {
2488: sprintf(hexdumpBuffer+strlen(hexdumpBuffer), "%2.2x", Disass68kGetWord(addr+j) >> 8);
2489: } else {
2490: sprintf(hexdumpBuffer+strlen(hexdumpBuffer), "%4.4x", Disass68kGetWord(addr+j));
2491: }
2492: }
2493:
2494: lineBuffer[0] = 0;
2495: if(optionPosAddress >= 0)
2496: Disass68kComposeStr(lineBuffer, addressBuffer, optionPosAddress, 0);
2497: if(optionPosHexdump >= 0)
2498: Disass68kComposeStr(lineBuffer, hexdumpBuffer, optionPosHexdump, optionPosLabel);
2499: if(optionPosLabel >= 0)
2500: Disass68kComposeStr(lineBuffer, labelBuffer, optionPosLabel, 0);
2501: if(optionPosOpcode >= 0)
2502: Disass68kComposeStr(lineBuffer, opcodeBuffer, optionPosOpcode, 0);
2503: if(optionPosOperand >= 0)
2504: {
2505: size_t l = strlen(lineBuffer);
2506: if(lineBuffer[l-1] != ' ') // force at least one space between opcode and operand
2507: {
2508: lineBuffer[l++] = ' ';
2509: lineBuffer[l] = 0;
2510: }
2511: Disass68kComposeStr(lineBuffer, operandBuffer, optionPosOperand, 0);
2512: }
1.1.1.4 root 2513: if (optionPosComment >= 0)
1.1.1.3 root 2514: {
1.1.1.4 root 2515: float percentage;
1.1.1.6 ! root 2516: Uint32 count, cycles, i_misses, d_hits;
! 2517: if (Profile_CpuAddressData(addr, &percentage, &count, &cycles, &i_misses, &d_hits))
1.1.1.3 root 2518: {
1.1.1.6 ! root 2519: sprintf(commentBuffer, "%5.2f%% (%u, %u, %u, %u)", percentage, count, cycles, i_misses, d_hits);
1.1.1.3 root 2520: Disass68kComposeStr(lineBuffer, commentBuffer, optionPosComment+1, 0);
2521: }
1.1.1.4 root 2522: /* show comments only if profile data is missing */
2523: else if (commentBuffer[0])
2524: {
2525: Disass68kComposeStr(lineBuffer, " ;", optionPosComment, 0);
2526: Disass68kComposeStr(lineBuffer, commentBuffer, optionPosComment+3, 0);
2527: }
1.1.1.3 root 2528: }
1.1.1.4 root 2529: addr += len;
2530: if (f)
2531: fprintf(f, "%s\n", lineBuffer);
1.1 root 2532: // if(strstr(opcodeBuffer, "RTS") || strstr(opcodeBuffer, "RTE") || strstr(opcodeBuffer, "JMP")
2533: // || strstr(opcodeBuffer, "rts") || strstr(opcodeBuffer, "rte") || strstr(opcodeBuffer, "jmp"))
2534: // fprintf(f, "\n");
2535: }
2536: if (nextpc)
2537: *nextpc = addr;
2538: }
2539:
2540:
1.1.1.4 root 2541: /**
2542: * Calculate next PC address from given one, without output
2543: * @return next PC address
1.1 root 2544: */
1.1.1.4 root 2545: Uint32 Disasm_GetNextPC(Uint32 pc)
2546: {
2547: uaecptr nextpc;
2548: Disass68k_loop (NULL, pc, &nextpc, 1);
2549: return nextpc;
2550: }
1.1 root 2551:
1.1.1.4 root 2552: /**
2553: * Call disassembly using the selected disassembly method,
2554: * either internal UAE one, or the stand alone disassembler above,
2555: * whichever is selected in Hatari configuration
2556: */
2557: void Disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1.1 root 2558: {
1.1.1.4 root 2559: if (ConfigureParams.Debugger.bDisasmUAE)
1.1.1.6 ! root 2560: #ifdef WINUAE_FOR_HATARI
! 2561: m68k_disasm_file (f, addr, nextpc, cnt);
! 2562: #else
1.1.1.5 root 2563: m68k_disasm (f, addr, nextpc, cnt);
1.1.1.6 ! root 2564: #endif
1.1.1.4 root 2565: else
1.1.1.5 root 2566: Disass68k_loop (f, addr, nextpc, cnt);
1.1 root 2567: }
2568:
1.1.1.4 root 2569: static void Disasm_CheckOptionEngine(void)
2570: {
2571: if (ConfigureParams.Debugger.bDisasmUAE)
2572: fputs("WARNING: disassembly options are supported only for '--disasm ext'!\n", stderr);
2573: }
2574:
2575: /**
2576: * query disassembly output column positions.
2577: */
2578: void Disasm_GetColumns(int *pos)
2579: {
2580: pos[DISASM_COLUMN_ADDRESS] = optionPosAddress;
2581: pos[DISASM_COLUMN_HEXDUMP] = optionPosHexdump;
2582: pos[DISASM_COLUMN_LABEL] = optionPosLabel;
2583: pos[DISASM_COLUMN_OPCODE] = optionPosOpcode;
2584: pos[DISASM_COLUMN_OPERAND] = optionPosOperand;
2585: pos[DISASM_COLUMN_COMMENT] = optionPosComment;
2586: }
2587:
2588: /**
2589: * set disassembly output column positions.
2590: */
2591: void Disasm_SetColumns(int *pos)
2592: {
2593: Disasm_CheckOptionEngine();
2594: optionPosAddress = pos[DISASM_COLUMN_ADDRESS];
2595: optionPosHexdump = pos[DISASM_COLUMN_HEXDUMP];
2596: optionPosLabel = pos[DISASM_COLUMN_LABEL];
2597: optionPosOpcode = pos[DISASM_COLUMN_OPCODE];
2598: optionPosOperand = pos[DISASM_COLUMN_OPERAND];
2599: optionPosComment = pos[DISASM_COLUMN_COMMENT];
2600: }
2601:
2602: /**
2603: * function to disable given disassembly output 'column'.
2604: * input is current column positions in 'oldcols' array and
2605: * output is new column positions/values in 'newcols' array.
2606: * It's safe to use same array for both.
2607: */
2608: void Disasm_DisableColumn(int column, int *oldcols, int *newcols)
2609: {
2610: int i, diff = 0;
2611:
2612: assert(column >= 0 && column < DISASM_COLUMNS);
2613: if (column+1 < DISASM_COLUMNS)
2614: diff = oldcols[column+1] - oldcols[column];
2615:
2616: for (i = 0; i < DISASM_COLUMNS; i++)
2617: {
2618: if (i && oldcols[i-1] > oldcols[i])
2619: {
2620: printf("WARNING: disassembly columns aren't in the expected order!\n");
2621: return;
2622: }
2623: if (i < column)
2624: newcols[i] = oldcols[i];
2625: else if (i > column)
2626: newcols[i] = oldcols[i] - diff;
2627: else
2628: newcols[column] = DISASM_COLUMN_DISABLE;
2629: }
2630: }
2631:
2632: /**
2633: * Get current disassembly output option flags
2634: * @return current output flags
2635: */
2636: int Disasm_GetOptions(void)
2637: {
2638: return options;
2639: }
2640:
2641: /**
1.1.1.6 ! root 2642: * Set CPU and FPU mask used for disassembly (when changed from the UI or the options)
! 2643: */
! 2644: void Disasm_SetCPUType ( int CPU , int FPU )
! 2645: {
! 2646: optionCPUTypeMask = 0;
! 2647:
! 2648: if ( ( FPU == 68881 ) || ( FPU == 68882 ) )
! 2649: optionCPUTypeMask |= MC_FPU;
! 2650:
! 2651: switch ( CPU )
! 2652: {
! 2653: case 0 : optionCPUTypeMask |= MC68000 ; break;
! 2654: case 1 : optionCPUTypeMask |= MC68010 ; break;
! 2655: case 2 : optionCPUTypeMask |= MC68020 ; break;
! 2656: case 3 : optionCPUTypeMask |= MC68030 ; break;
! 2657: case 4 : optionCPUTypeMask |= MC68040 ; break;
! 2658: default : optionCPUTypeMask |= MC68000 ; break;
! 2659: }
! 2660: }
! 2661:
! 2662: /**
1.1.1.4 root 2663: * Parse disasm command line option argument
2664: * @return error string (""=silent 'error') or NULL for success.
2665: */
2666: const char *Disasm_ParseOption(const char *arg)
2667: {
2668: if (strcasecmp(arg, "help") == 0)
2669: {
2670: const struct {
2671: int flag;
2672: const char *desc;
2673: } option[] = {
2674: { doptNoBrackets, "no brackets around absolute addressing" },
2675: { doptOpcodesSmall, "opcodes in small letters" },
2676: { doptRegisterSmall, "register names in small letters" },
2677: { doptStackSP, "stack pointer as 'SP', not 'A7'" },
2678: { 0, NULL }
2679: };
2680: int i;
2681: fputs("Disassembly settings:\n"
2682: "\tuae - use CPU core internal disassembler which has better\n"
2683: "\t instruction support\n"
2684: "\text - use external disassembler which has nicer output\n"
2685: "\t and supports options below\n"
2686: "\t<bitmask> - disassembly output option flags\n"
2687: "Flag values:\n", stderr);
2688: for (i = 0; option[i].desc; i++) {
2689: assert(option[i].flag == (1 << i));
2690: fprintf(stderr, "\t%d: %s\n", option[i].flag, option[i].desc);
2691: }
2692: fprintf(stderr, "Current settings are:\n\t--disasm %s --disasm %d\n",
2693: ConfigureParams.Debugger.bDisasmUAE ? "uae" : "ext",
2694: ConfigureParams.Debugger.nDisasmOptions);
2695: return "";
2696: }
2697: if (strcasecmp(arg, "uae") == 0)
2698: {
2699: fputs("Selected UAE CPU core internal disassembler.\n", stderr);
2700: ConfigureParams.Debugger.bDisasmUAE = true;
2701: return NULL;
2702: }
2703: if (strcasecmp(arg, "ext") == 0)
2704: {
2705: fputs("Selected external disassembler.\n", stderr);
2706: fprintf(stderr, "Disassembly output flags are %d.\n", options);
2707: ConfigureParams.Debugger.bDisasmUAE = false;
2708: return NULL;
2709: }
1.1.1.5 root 2710: if (isdigit((unsigned char)*arg))
1.1.1.4 root 2711: {
2712: int newopt = atoi(arg);
2713: if ((newopt|optionsMask) != optionsMask)
2714: {
2715: return "unknown flags in the bitmask";
2716: }
2717: fprintf(stderr, "Changed CPU disassembly output flags from %d to %d.\n", options, newopt);
2718: ConfigureParams.Debugger.nDisasmOptions = options = newopt;
2719: Disasm_CheckOptionEngine();
2720: return NULL;
2721: }
2722: return "invalid disasm option";
2723: }
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