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1.1 root 1: /***
2: * 68k disassembler, written 2010 by Markus Fritze, www.sarnau.com
3: *
1.1.1.4 root 4: * This file is distributed under the GNU General Public License, version 2
5: * or at your option any later version. Read the file gpl.txt for details.
1.1 root 6: ***/
7:
1.1.1.7 ! root 8: #include "main.h"
1.1 root 9: #include <ctype.h>
1.1.1.7 ! root 10: #if HAVE_STRINGS_H
! 11: # include <strings.h>
! 12: #endif
1.1 root 13:
14: #include "sysdeps.h"
1.1.1.4 root 15: #include "configuration.h"
1.1 root 16: #include "newcpu.h"
1.1.1.7 ! root 17: #include "stMemory.h"
1.1.1.6 root 18: #ifdef WINUAE_FOR_HATARI
19: #include "debug.h"
20: #endif
1.1 root 21: #include "paths.h"
1.1.1.3 root 22: #include "profile.h"
1.1 root 23: #include "tos.h"
24: #include "68kDisass.h"
25:
26: #define ADDRESS_ON_PC 1
27: #define USE_SYMBOLS 1
28:
29: typedef enum {
30: doptNoBrackets = 1, // hide brackets around absolute addressing
31: doptOpcodesSmall = 2, // opcodes are small letters
32: doptRegisterSmall = 4, // register names are small letters
1.1.1.5 root 33: doptStackSP = 8 // stack pointer is named "SP" instead of "A7" (except for MOVEM)
1.1 root 34: } Diss68kOptions;
35:
36: static Diss68kOptions options = doptOpcodesSmall | doptRegisterSmall | doptStackSP | doptNoBrackets;
37:
1.1.1.4 root 38: /* all options */
39: static const Diss68kOptions optionsMask = doptOpcodesSmall | doptRegisterSmall | doptStackSP | doptNoBrackets;
40:
1.1 root 41: // values <0 will hide the group
1.1.1.4 root 42: static int optionPosAddress = 0; // current address
1.1.1.6 root 43: static int optionPosHexdump = 12; // 16-bit words at this address
1.1.1.4 root 44: static int optionPosLabel = 35; // label, if defined
45: static int optionPosOpcode = 47; // opcode
46: static int optionPosOperand = 57; // operands for the opcode
47: static int optionPosComment = 82; // comment, if defined
1.1 root 48:
49: /***
50: * Motorola 16-/32-Bit Microprocessor and coprocessor types
51: ***/
52: #define MC68000 0x000001 // 16-/32-Bit Microprocessor
53: #define MC68EC000 0x000002 // 16-/32-Bit Embedded Controller
54: #define MC68HC000 0x000004 // Low Power 16-/32-Bit Microprocessor
55: #define MC68008 0x000008 // 16-Bit Microprocessor with 8-Bit Data Bus
56: #define MC68010 0x000010 // 16-/32-Bit Virtual Memory Microprocessor
57: #define MC68020 0x000020 // 32-Bit Virtual Memory Microprocessor
58: #define MC68EC020 0x000040 // 32-Bit Embedded Controller (no PMMU)
59: #define MC68030 0x000080 // Second-Generation 32-Bit Enhanced Microprocessor
60: #define MC68EC030 0x000100 // 32-Bit Embedded Controller (no PMMU)
61: #define MC68040 0x000200 // Third-Generation 32-Bit Microprocessor
62: #define MC68LC040 0x000400 // Third-Generation 32-Bit Microprocessor (no FPU)
63: #define MC68EC040 0x000800 // 32-Bit Embedded Controller (no FPU, no PMMU)
64: #define MC68330 0x001000 // CPU32 Integrated CPU32 Processor
65: #define MC68340 0x002000 // CPU32 Integrated Processor with DMA
66: #define MC68060 0x004000 // Fourth-Generation 32-Bit Microprocessor
67: #define MC68LC060 0x008000 // Fourth-Generation 32-Bit Microprocessor (no FPU)
68: #define MC68EC060 0x010000 // Fourth-Generation 32-Bit Microprocessor (no FPU, no PMMU)
69: #define MC_CPU32 (MC68330|MC68340)
70:
71: #define MC_020 (MC68020|MC68EC020|MC68030|MC68EC030|MC68040|MC68LC040|MC68EC040|MC_CPU32|MC68060|MC68LC060|MC68EC060)
72: #define MC_ALL (MC68000|MC68EC000|MC68HC000|MC68008|MC68010|MC_020)
73:
74: #define MC68851 0x020000 // Paged Memory Management Unit
75:
76: #define MC68881 0x040000 // Floating-PointCoprocessor
77: #define MC68882 0x080000 // Enhanced Floating-Point Coprocessor
78:
79: #define MC_PMMU (MC68881|MC68882)
80: #define MC_FPU (MC68881|MC68882)
81:
82: static int optionCPUTypeMask = ( MC_ALL & ~MC68040 & ~MC_CPU32 & ~MC68060 ) | MC_PMMU | MC_FPU;
83:
84:
85: typedef enum {
86: dtNone,
87: dtByte, // a specific number of bytes, usually 1
88: dtWord, // one 16-bit value
89: dtLong, // one 32-bit value
90: dtOpcode, // an opcode of variable length
91: dtASCString, // a 0-byte terminated ASCII string
92: dtPointer, // a generic 32-bit pointer
93: dtFunctionPointer, // a 32-bit pointer to a function
1.1.1.5 root 94: dtStringArray // a specific number of ASCII bytes
1.1 root 95: } Disass68kDataType;
96:
97: typedef struct {
98: char *name;
99: char *comment;
100: Disass68kDataType type;
101: int size;
102: } disStructElement;
103:
104: typedef struct {
105: char *name; // name of the structure
106: int size; // size of structure
107: int count; // number of lines
108: disStructElement *elements; // array of all elements of the struct
109: } disStructEntry;
110:
111: static int disStructCounts;
112: static disStructEntry *disStructEntries;
113:
114: typedef struct {
115: long addr; // address of the label
116: Disass68kDataType type; // type of the data on the address
117: int size; // size of the label, references inside it are addressed via base address + offset
118: int count; // number of elements at this address with the given size
119: int structIndex; // -1 no struct to describe the element
120: char *name; // name of the label
121: char *comment; // optional comment
122: } disSymbolEntry;
123:
124: static int disSymbolCounts;
125: static disSymbolEntry *disSymbolEntries;
126:
127:
128: static inline unsigned short Disass68kGetWord(long addr)
129: {
1.1.1.6 root 130: if ( ! valid_address ( addr , 2 ) )
131: return 0;
132:
1.1.1.7 ! root 133: return STMemory_ReadWord ( addr );
1.1 root 134: }
135:
136: // Load a text file into memory, count the lines and replace the LF with 0-bytes.
137: static int Disass68kLoadTextFile(const char *filename, char **filebuf)
138: {
139: long index;
1.1.1.4 root 140: long fileLength;
1.1.1.6 root 141: int lineCount = 0;
1.1.1.4 root 142: char *fbuf;
143: FILE *f;
144:
1.1 root 145: if(filebuf)
146: *filebuf = NULL;
1.1.1.4 root 147: f = fopen(filename, "r");
1.1.1.6 root 148: if (!f)
1.1 root 149: return 0;
1.1.1.6 root 150: if (fseek(f, 0, SEEK_END))
151: goto out;
1.1.1.4 root 152: fileLength = ftell(f);
1.1.1.6 root 153: if (fileLength <= 0)
154: goto out;
155: if (fseek(f, 0, SEEK_SET))
156: goto out;
1.1.1.4 root 157: fbuf = malloc(fileLength);
1.1.1.6 root 158: if(!fbuf)
159: goto out;
1.1 root 160: if((size_t)fileLength != fread(fbuf, sizeof(char), fileLength, f))
1.1.1.4 root 161: {
162: free(fbuf);
1.1.1.6 root 163: goto out;
1.1.1.4 root 164: }
1.1.1.6 root 165:
1.1 root 166: for(index=0; index<fileLength; ++index)
167: {
168: if(fbuf[index] == '\r') // convert potential CR into a space (which we ignore at the end of the line anyway)
169: fbuf[index] = ' ';
170: if(fbuf[index] == '\n') // count LF and terminate line
171: {
172: ++lineCount;
173: fbuf[index] = 0;
174: }
175: }
176: if(filebuf)
177: *filebuf = fbuf;
1.1.1.6 root 178: out:
179: fclose(f);
1.1 root 180: return lineCount;
181: }
182:
183: static void Disass68kLoadStructInfo(const char *filename)
184: {
1.1.1.4 root 185: int i,j;
186: char *nextLine;
187: char *line;
1.1 root 188: char *fbuf = NULL;
1.1.1.4 root 189: int lineCount = Disass68kLoadTextFile(filename, &fbuf);
1.1 root 190: disStructEntry *se = NULL;
1.1.1.4 root 191:
192: if(!lineCount) return;
193:
194: disStructEntries = realloc(disStructEntries, sizeof(disStructEntry)
195: * (disStructCounts + lineCount));
1.1 root 196: if(!disStructEntries) { free(fbuf); return; }
1.1.1.4 root 197:
198: line = fbuf;
1.1 root 199:
200: for(i=0; i<lineCount; line = nextLine, ++i)
201: {
202: // strip spaces at the end of the line, remember the ptr to the next line
203: char *sp = line;
204: while(*sp++)
205: ;
206: nextLine = sp--;
1.1.1.5 root 207: while (isspace((unsigned char)*--sp))
1.1 root 208: *sp = 0;
209:
210: if(line[0] == '{')
211: {
212: se = &disStructEntries[disStructCounts];
213: se->name = strdup(line+1);
214: se->count = 0;
215: se->elements = malloc(sizeof(disStructElement) * lineCount); // lineCount is way too much, but safe
216: } else if(line[0] == '}') {
217: if(se)
218: {
219: se->size = 0;
220: for(j=0; j<se->count; ++j)
221: se->size += se->elements[j].size;
222: // printf("%s : %d bytes\n", se->name, se->size);
223: ++disStructCounts;
224: se = NULL;
225: }
226: } else if(line[0] == '#') {
227: disStructElement dse;
228: int val = 0;
229: int index = 2;
230: if(line[1] == 'A' || line[1] == 'B')
231: {
1.1.1.5 root 232: for(; isdigit((unsigned char)line[index]); ++index)
1.1 root 233: {
234: val *= 10;
235: val += line[index] - '0';
236: }
237: }
238: if(val == 0) val = 1;
239: dse.name = NULL;
240: switch(line[1])
241: {
242: case 'A': dse.type = dtStringArray; dse.size = val; dse.name = strdup(line + index + 1); break;
243: case 'B': dse.type = dtByte; dse.size = val; break;
244: case 'W': dse.type = dtWord; dse.size = 2; break;
245: case 'L': dse.type = dtLong; dse.size = 4; break;
246: case 'C': dse.type = dtOpcode; dse.size = 2; break;
247: case 'f': dse.type = dtFunctionPointer; dse.size = 4; break;
248: case 'p': dse.type = dtPointer; dse.size = 4; break;
249: default: dse.type = dtNone; dse.size = 0;
250: printf("Unknown type in \"%s\"\n", line); break;
251: }
252: if(!dse.name)
253: dse.name = strdup(line+3);
254: dse.comment = NULL;
255: if(se)
256: se->elements[se->count++] = dse;
257: }
258: }
259: free(fbuf);
260: }
261:
262: static void Disass68kLoadSymbols(const char *filename)
263: {
1.1.1.4 root 264: int i,j;
265: char *nextLine;
266: char *line;
1.1 root 267: char *fbuf = NULL;
268: int lineCount = Disass68kLoadTextFile(filename, &fbuf);
1.1.1.4 root 269: if(!lineCount) return;
1.1 root 270: disSymbolEntries = realloc(disSymbolEntries, sizeof(disSymbolEntry) * (disSymbolCounts + lineCount));
271: if(!disSymbolEntries) { free(fbuf); return; }
1.1.1.4 root 272: line = fbuf;
1.1 root 273:
274: for(i=0; i<lineCount; line = nextLine, ++i)
275: {
1.1.1.4 root 276: long addr;
1.1 root 277: char *sp = line;
1.1.1.4 root 278: char *parameterPtr[10];
279: int parameterCount = 0;
280: char *str;
281: long size = 0;
282: int type = 0;
283:
284: // strip spaces at the end of the line, remember the ptr to the next line
1.1 root 285: while(*sp++)
286: ;
287: nextLine = sp--;
1.1.1.5 root 288: while(isspace((unsigned char)*--sp))
1.1 root 289: *sp = 0;
290:
291: // ignore empty lines
292: if(line[0] == 0)
293: continue;
294:
295: sscanf(line, "%lx",&addr);
296: disSymbolEntries[disSymbolCounts].addr = addr;
297: disSymbolEntries[disSymbolCounts].structIndex = -1;
298:
1.1.1.4 root 299: str = line;
1.1 root 300: do {
301: str = strchr(str, ',');
302: if(str)
303: {
304: char *ep = str;
1.1.1.5 root 305: while(isspace((unsigned char)*--ep))
1.1 root 306: *ep = 0;
307: *str++ = 0;
1.1.1.5 root 308: while(*str && isspace((unsigned char)*str))
1.1 root 309: ++str;
310: parameterPtr[parameterCount++] = str;
311: }
312: } while(str != NULL && parameterCount < 10);
313:
314: if(parameterCount != 3 && parameterCount != 4)
315: continue; // ignore line
316:
317: if(strlen(parameterPtr[0]) == 1)
318: {
319: switch(parameterPtr[0][0])
320: {
321: case 'A': type = dtASCString; size = 1; break; // ascii NULL
322: case 'B': type = dtByte; size = 1; break; // byte
323: case 'W': type = dtWord; size = 2; break; // word
324: case 'L': type = dtLong; size = 4; break; // long
325: case 'C': type = dtOpcode; size = 2; break; // code
326: case 'f': type = dtFunctionPointer; size = 4; break; // function pointer
327: case 'p': type = dtPointer; size = 4; break; // regular pointer
328: default: printf("ERROR: $%lx : %s\n", addr, parameterPtr[0]); continue;
329: }
330: } else {
331: for(j=0; j<disStructCounts; ++j)
332: {
333: disStructEntry *se = &disStructEntries[j];
334: if(se->name == NULL)
335: break;
336: if(strcmp(parameterPtr[0], se->name))
337: continue;
338: size = se->size;
339: disSymbolEntries[disSymbolCounts].structIndex = j;
340: }
341: }
342: if(!size)
343: continue;
344:
345: disSymbolEntries[disSymbolCounts].type = type;
346: disSymbolEntries[disSymbolCounts].size = size;
347: disSymbolEntries[disSymbolCounts].count = atol(parameterPtr[1]);
348: disSymbolEntries[disSymbolCounts].name = strdup(parameterPtr[2]);
349: disSymbolEntries[disSymbolCounts].comment = NULL;
350: if(parameterCount == 4)
351: disSymbolEntries[disSymbolCounts].comment = strdup(parameterPtr[3]);
352: ++disSymbolCounts;
353: }
354: free(fbuf);
355: }
356:
357: static void Disass68kInit(const char *baseDirectory)
358: {
1.1.1.2 root 359: char filename[FILENAME_MAX];
1.1 root 360:
361: disStructCounts = 0;
362: sprintf(filename, "%s/DisassStructs.txt", baseDirectory);
363: Disass68kLoadStructInfo(filename);
364: sprintf(filename, "%s/DisassStructs_%4.4X.txt", baseDirectory, TosVersion);
365: Disass68kLoadStructInfo(filename);
366:
367: disSymbolCounts = 0;
368: sprintf(filename, "%s/DisassSymbols.txt", baseDirectory);
369: Disass68kLoadSymbols(filename);
370: sprintf(filename, "%s/DisassSymbols_%4.4X.txt", baseDirectory, TosVersion);
371: Disass68kLoadSymbols(filename);
372: }
373:
374:
375:
376: static Disass68kDataType Disass68kType(long addr, char *addressLabel, char *commentBuffer, int *count)
377: {
378: int i,j;
379:
380: addressLabel[0] = 0;
381: commentBuffer[0] = 0;
382: for(i=0; i<disSymbolCounts; ++i)
383: {
1.1.1.4 root 384: const disStructEntry *se;
1.1 root 385: const disSymbolEntry *dse = &disSymbolEntries[i];
386: int offset = addr - dse->addr;
1.1.1.4 root 387:
1.1 root 388: if(offset < 0 || offset >= dse->count * dse->size)
389: continue;
390:
391: // no special struct that devices this value?
392: if(dse->structIndex < 0)
393: {
394: offset = (offset + dse->size - 1) / dse->size;
395: *count = dse->count - offset;
396: if(offset == 0) // only in the first line
397: {
398: strcpy(addressLabel, dse->name);
399: if(dse->comment)
400: strcpy(commentBuffer, dse->comment);
401: }
402: return dse->type;
403: }
404:
405: *count = 1;
1.1.1.4 root 406: se = &disStructEntries[dse->structIndex];
1.1 root 407: for(j=0; j<se->count; ++j)
408: {
409: const disStructElement *e = &se->elements[j];
410: if(offset < e->size)
411: {
412: if(e->type == dtStringArray)
413: *count = e->size;
414: if(j == 0)
415: strcpy(addressLabel, dse->name);
416:
417: sprintf(commentBuffer, "[%s]", e->name);
418: if(e->comment)
419: strcat(commentBuffer, e->comment);
420: return e->type;
421: }
422: offset -= e->size;
423: }
424: return dse->size;
425: }
426: return dtNone;
427: }
428:
429: /***
430: * Lookup a symbol name
431: ***/
432: static const char *Disass68kSymbolName(long addr, int size)
433: {
434: int i;
435:
436: for(i=0; i<disSymbolCounts; ++i)
437: {
1.1.1.4 root 438: static char symbolName[128];
1.1 root 439: const disSymbolEntry *dse = &disSymbolEntries[i];
1.1.1.4 root 440: int offset = addr - dse->addr;
441: int reminder;
442:
1.1 root 443: if(offset < 0 || offset >= dse->count * dse->size)
444: continue;
445:
446: if(dse->name[0] == 0)
447: return NULL;
448:
1.1.1.4 root 449: reminder = offset % dse->size;
1.1 root 450: offset /= dse->size;
451:
452: strcpy(symbolName, dse->name);
453: if(offset)
454: sprintf(symbolName+strlen(symbolName), "+%d*%d", dse->size, offset);
455: if(reminder)
456: sprintf(symbolName+strlen(symbolName), "+%d", reminder);
457: return symbolName;
458: }
459: return NULL;
460: }
461:
462: /***
463: * return a string pointer to display a register name
464: ***/
465: static const char *Disass68kRegname(int reg)
466: {
467: static char regName[3];
468: switch(reg)
469: {
470: case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
471: sprintf(regName, "%c%d", (options & doptRegisterSmall ? 'd' : 'D'), reg);
472: break;
473:
474: case 0x0F:
475: if(options & doptStackSP) // display A7 as SP
476: {
477: if(options & doptRegisterSmall)
478: return "sp";
479: return "SP";
480: }
481: case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: case 0x0D: case 0x0E:
482: sprintf(regName, "%c%d", (options & doptRegisterSmall ? 'a' : 'A'), reg & 7);
483: break;
484: }
485: return regName;
486: }
487:
488: /***
489: * return a string pointer to display a register name
490: ***/
491: static const char *Disass68kNumber(int val)
492: {
493: static char numString[32];
494: if(val >= -9 && val <= 9)
495: {
496: sprintf(numString, "%d", val);
497: } else {
498: // 4 characters/numbers or underscore (e.g. for cookies)
1.1.1.5 root 499: unsigned char c0 = (val >> 24) & 0xFF;
500: unsigned char c1 = (val >> 16) & 0xFF;
501: unsigned char c2 = (val >> 8) & 0xFF;
502: unsigned char c3 = (val >> 0) & 0xFF;
1.1 root 503: if((isalnum(c0) || c0 == '_') && (isalnum(c1) || c1 == '_') && (isalnum(c2) || c2 == '_') && (isalnum(c3) || c3 == '_'))
504: {
505: sprintf(numString, "'%c%c%c%c'", c0, c1, c2, c3);
506: } else {
507: sprintf(numString, "$%x", val);
508: }
509: }
510: return numString;
511: }
512:
513: /***
514: * Supported registers for e.g. MOVEC
515: ***/
516: #define REG_CCR -1
517: #define REG_SR -2
518: #define REG_PC -3
519: #define REG_ZPC -4
520: #define REG_TT0 -8
521: #define REG_TT1 -9
522: #define REG_MMUSR -10
523: #define REG_USP 0x800
524: #define REG_SFC 0x000
525: #define REG_DFC 0x001
526: #define REG_TC 0x10000
527: #define REG_SRP 0x10002
528: #define REG_CRP 0x10003
529: #define REG_VAL 0x20000
530: #define REG_CACHES_NONE 0x20010
531: #define REG_CACHES_IC 0x20011
532: #define REG_CACHES_DC 0x20012
533: #define REG_CACHES_ICDC 0x20013
534: #define REG_FPU_FPCR 0x30004
535: #define REG_FPU_FPSR 0x30002
536: #define REG_FPU_FPIAR 0x30001
537:
538: static const char *Disass68kSpecialRegister(int reg)
539: {
540: static char buf[8];
541: const char *sp = NULL;
542: switch (reg)
543: {
544: case 0x000: sp = "SFC"; break;
545: case 0x001: sp = "DFC"; break;
546: case 0x002: sp = "CACR"; break;
547: case 0x003: sp = "TC"; break;
548: case 0x004: sp = "ITT0"; break; // IACR0 on an 68EC040 only
549: case 0x005: sp = "ITT1"; break; // IACR1 on an 68EC040 only
550: case 0x006: sp = "DTT0"; break; // DACR0 on an 68EC040 only
551: case 0x007: sp = "DTT1"; break; // DACR1 on an 68EC040 only
552: case 0x008: sp = "BUSCR"; break;
553:
554: case 0x800: sp = "USP"; break;
555: case 0x801: sp = "VBR"; break;
556: case 0x802: sp = "CAAR"; break;
557: case 0x803: sp = "MSP"; break;
558: case 0x804: sp = "ISP"; break;
559: case 0x805: sp = "MMUSR"; break;
560: case 0x806: sp = "URP"; break;
561: case 0x807: sp = "SRP"; break;
562: case 0x808: sp = "PCR"; break;
563:
564: // MMU register
565: case 0x10000: sp = "TC"; break;
566: case 0x10001: sp = "DRP"; break;
567: case 0x10002: sp = "SRP"; break;
568: case 0x10003: sp = "CRP"; break;
569: case 0x10004: sp = "CAL"; break;
570: case 0x10005: sp = "VAL"; break;
571: case 0x10006: sp = "SCCR"; break;
572: case 0x10007: sp = "ACR"; break;
573:
574: case REG_CCR: sp = "CCR"; break;
575: case REG_SR: sp = "SR"; break;
576: case REG_PC: sp = "PC"; break;
577: case REG_ZPC: sp = "ZPC"; break;
578: case REG_TT0: sp = "TT0"; break;
579: case REG_TT1: sp = "TT1"; break;
580: case REG_MMUSR: sp = "MMUSR"; break;
581:
582: case REG_VAL: sp = "VAL"; break;
583:
584: case REG_CACHES_NONE: sp = "NC"; break;
585: case REG_CACHES_IC: sp = "IC"; break;
586: case REG_CACHES_DC: sp = "DC"; break;
587: case REG_CACHES_ICDC: sp = "IC/DC"; break; // GCC lists this as "BC"
588:
589: case REG_FPU_FPCR: sp = "FPCR"; break;
590: case REG_FPU_FPSR: sp = "FPSR"; break;
591: case REG_FPU_FPIAR: sp = "FPIAR"; break;
592:
593: // unknown register => unknown opcode!
1.1.1.4 root 594: default: return NULL;
1.1 root 595: }
1.1.1.4 root 596:
1.1 root 597: if(options & doptRegisterSmall)
598: {
1.1.1.4 root 599: char *bp;
1.1 root 600: strcpy(buf, sp);
1.1.1.4 root 601: for (bp = buf; *bp; ++bp)
1.1.1.5 root 602: *bp = tolower((unsigned char)*bp);
1.1 root 603: return buf;
604: }
605: return sp;
606: }
607:
608: /***
609: * 680x0 EA disassembly, supports all address modes
610: *
611: * disassbuf = output buffer for the EA, empty string in case of an illegal EA
612: * addr = pointer to the address, which Disass68kGetWord() will allow to read memory.
613: * Incremented by the function to point behind the opcode, when done
614: * ea = 6-bit ea from the opcode
615: * size = addressed size of the opcode in bytes (e.g. 1,2,4 for MOVE.B, MOVE.W, MOVE.L), only used for immediate addressing
616: ***/
617:
618: #define EA_Dn 0x00001 // Dn
619: #define EA_An 0x00002 // An
620: #define EA_Ani 0x00004 // (An)
621: #define EA_Anip 0x00008 // (An)+
622: #define EA_piAn 0x00010 // -(An)
623: #define EA_dAn 0x00020 // d(An), d(An,Dn), etc.
624: #define EA_PCRel 0x00040 // d(PC), d(PC,Dn), etc.
625: #define EA_Abs 0x00080 // abs.w, abs.l
626: #define EA_Immed 0x00100 // #<val>
627:
628: #define EA_ImmedParameter 0x0200 // an immediate value as a parameter
629: #define EA_ValueParameter 0x0400 // an immediate value as a parameter without the "#"
630: #define EA_SpecialRegister 0x0800 // any special register e.g. SR,CCR,USP,etc
631: #define EA_PCDisplacement 0x1000 // PC relative jump, like for BRA and friends
632:
633: #define EA_All (EA_Dn | EA_An | EA_Ani | EA_Anip | EA_piAn | EA_dAn | EA_Abs | EA_Immed | EA_PCRel)
634: #define EA_Dest (EA_Dn | EA_An | EA_Ani | EA_Anip | EA_piAn | EA_dAn | EA_Abs)
635:
636: static char *Disass68kEA(char *disassbuf, char *commentBuffer, long *addr, long opcodeAddr, int ea, int size, int allowedEAs, int parameterValue, int disassFlag)
637: {
638: unsigned short eWord1;
639: unsigned short eWord2;
640: int xn,c,scale;
641: int reg = ea & 7;
642: const char *sp;
643: long val;
1.1.1.4 root 644: char regName[3];
645: signed long pcoffset;
646:
1.1 root 647: disassbuf[0] = 0;
648: switch(ea)
649: {
650: // M=000 = 0 Dn
651: // Data Register Direct Mode
652: // Dn
653: // M=001 = 1 An
654: // Address Register Direct Mode
655: // An
656: case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
657: if((allowedEAs & EA_Dn) != EA_Dn)
658: break;
659: sprintf(disassbuf, "%s", Disass68kRegname(ea & 0x0F));
660: break;
661: case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: case 0x0D: case 0x0E: case 0x0F:
662: if((allowedEAs & EA_An) != EA_An)
663: break;
664: sprintf(disassbuf, "%s", Disass68kRegname(ea & 0x0F));
665: break;
666:
667: // M=010 = 2
668: // Address Register Indirect Mode
669: // (An)
670: case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
671: if((allowedEAs & EA_Ani) != EA_Ani)
672: break;
673: sprintf(disassbuf, "(%s)", Disass68kRegname(reg | 8));
674: break;
675:
676: // M=011 = 3
677: // Address Register Indirect with Postincrement Mode
678: // (An) +
679: case 0x18: case 0x19: case 0x1A: case 0x1B: case 0x1C: case 0x1D: case 0x1E: case 0x1F:
680: if((allowedEAs & EA_Anip) != EA_Anip)
681: break;
682: sprintf(disassbuf, "(%s)+", Disass68kRegname(reg | 8));
683: break;
684:
685: // M=100 = 4
686: // Address Register Indirect with Predecrement Mode
687: // – (An)
688: case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
689: if((allowedEAs & EA_piAn) != EA_piAn)
690: break;
691: sprintf(disassbuf, "-(%s)", Disass68kRegname(reg | 8));
692: break;
693:
694: // M=101 = 5
695: // Address Register Indirect with Displacement Mode
696: // (d16,An)
697: case 0x28: case 0x29: case 0x2A: case 0x2B: case 0x2C: case 0x2D: case 0x2E: case 0x2F:
698: if((allowedEAs & EA_dAn) != EA_dAn)
699: break;
700: eWord1 = Disass68kGetWord(*addr); *addr += 2;
701: sprintf(disassbuf, "%s(%s)", Disass68kNumber(eWord1), Disass68kRegname(reg | 8));
702: break;
703:
704: // M=111 = 7, Xn/reg = 011 = 3
705: // Program Counter Indirect with Index (Base Displacement) Mode
706: // (bd, PC, Xn. SIZE*SCALE)
707: // Program Counter Memory Indirect Postindexed Mode
708: // ([bd,PC],Xn.SIZE*SCALE,od)
709: // Program Counter Memory Indirect Preindexed Mode
710: // ([bd,PC,Xn.SIZE*SCALE],od)
711: case 0x3B:
712: // This is equal to the following, except that instead of An, it is PC relative
713:
714: // M=110 = 6
715: // Address Register Indirect with Index (Base Displacement) Mode
716: // (bd,An,Xn.SIZE*SCALE)
717: // Memory Indirect Postindexed Mode
718: // ([bd,An],Xn.SIZE*SCALE,od)
719: // Memory Indirect Preindexed Mode
720: // ([bd, An, Xn.SIZE*SCALE], od)
721: case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
722: eWord1 = Disass68kGetWord(*addr); *addr += 2;
723: xn = (eWord1 >> 12) & 0x0F; // Register D0..D7/A0..A7
724: c = ((eWord1 >> 11) & 1) ? 'l' : 'w'; // Word/Long-Word Index Size 0 = Sign-Extended Word 1 = Long Word
725: scale = (eWord1 >> 9) & 3; // Scale Factor 00 = 1 01 = 2 10 = 4 11 = 8
1.1.1.4 root 726:
1.1 root 727: if(ea == 0x3B)
728: {
729: sp = Disass68kSpecialRegister(REG_PC);
730: if(!sp) return NULL;
731: strcpy(regName, sp);
732: } else {
733: sprintf(regName, "%s", Disass68kRegname(reg | 8));
734: }
735:
736: if((eWord1 & 0x0100) == 0)
737: {
1.1.1.4 root 738: const char *numStr;
739:
1.1 root 740: // BRIEF EXTENSION WORD FORMAT
741: if(ea == 0x3B)
742: {
743: if((allowedEAs & EA_PCRel) != EA_PCRel)
744: break;
745: } else {
746: if((allowedEAs & EA_dAn) != EA_dAn)
747: break;
748: }
749:
750: // Address Register Indirect with Index (8-Bit Displacement) Mode
751: // (d8 ,An, Xn.SIZE*SCALE)
1.1.1.4 root 752: numStr = Disass68kNumber(eWord1 & 0xFF);
1.1 root 753: if(numStr[0] == '0' && numStr[1] == 0)
754: numStr = "";
755:
756: // scale is only on 68020 and later supported
757: if(scale != 0 && (optionCPUTypeMask & MC_020) == 0)
758: return NULL;
759:
760: if(scale == 0)
761: {
762: #if ADDRESS_ON_PC
763: if(ea == 0x3B)
764: sprintf(disassbuf, "$%lx(%s,%s.%c)", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2, Disass68kSpecialRegister(REG_PC), Disass68kRegname(xn), c);
765: else
766: #endif
767: sprintf(disassbuf, "%s(%s,%s.%c)", numStr, regName, Disass68kRegname(xn), c);
768: } else
769: {
770: #if ADDRESS_ON_PC
771: if(ea == 0x3B)
772: sprintf(disassbuf, "$%lx(%s,%s.%c*%d)", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2, Disass68kSpecialRegister(REG_PC), Disass68kRegname(xn), c, 1 << scale);
773: else
774: #endif
775: sprintf(disassbuf, "%s(%s,%s.%c*%d)", numStr, regName, Disass68kRegname(xn), c, 1 << scale);
776: }
777: #if USE_SYMBOLS
778: if(ea == 0x3B)
779: {
780: const char *symStr = Disass68kSymbolName((signed char)(eWord1 & 0xFF) + opcodeAddr + 2, size);
781: if(symStr)
782: {
783: commentBuffer += strlen(commentBuffer);
784: sprintf(commentBuffer+strlen(commentBuffer), "%s", symStr);
785: }
786: }
787: #endif
788: #if !ADDRESS_ON_PC
789: if(ea == 0x3B)
790: {
791: commentBuffer += strlen(commentBuffer);
792: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2);
793: }
794: #endif
795: } else {
796: // FULL EXTENSION WORD FORMAT
797:
1.1.1.4 root 798: int bs = (eWord1 >> 7) & 1; // Base Register Suppress 0 = Base Register Added 1 = Base Register Suppressed
799: int is = (eWord1 >> 6) & 1; // Index Suppress 0 = Evaluate and Add Index Operand 1 = Suppress Index Operand
800: int bdSize = (eWord1 >> 4) & 3; // Base Displacement Size 00 = Reserved 01 = Null Displacement 10 = Word Displacement 11 = Long Displacement
801: int iis = eWord1 & 7; // Index/Indirect Selection Indirect and Indexing Operand Determined in Conjunction with Bit 6, Index Suppress
1.1 root 802: bool prefixComma;
1.1.1.4 root 803: long bd, od;
1.1 root 804:
805: // reserved, has to be 0
806: if((eWord1 & 8) != 0 || bdSize == 0 || (is && iis > 3) || iis == 4)
807: break;
808:
809: // full extension format is only supported on 68020 or later
810: if((optionCPUTypeMask & MC_020) == 0)
811: return NULL;
812:
813: if(ea == 0x3B)
814: {
815: if((allowedEAs & EA_PCRel) != EA_PCRel)
816: break;
817: } else {
818: if((allowedEAs & EA_dAn) != EA_dAn)
819: break;
820: }
821:
1.1.1.4 root 822: bd = 0;
1.1 root 823: switch(bdSize)
824: {
825: case 3:
826: bd = Disass68kGetWord(*addr); *addr += 2;
827: bd <<= 16;
828: case 2:
829: bd |= Disass68kGetWord(*addr); *addr += 2;
830: break;
831: default:
832: break;
833: }
834:
835: prefixComma = false;
836: if(bdSize >= 2 && iis == 0)
837: sprintf(disassbuf, "%s", Disass68kNumber(bd));
838: strcat(disassbuf, "(");
839: if(iis != 0)
840: {
841: // the CPU32 doesn't support the memory indirect mode
842: if(optionCPUTypeMask & MC_CPU32)
843: return NULL;
844:
845: strcat(disassbuf, "[");
846: }
847: if(bdSize >= 2 && iis != 0)
848: {
849: sprintf(disassbuf+strlen(disassbuf), "%s", Disass68kNumber(bd));
850: prefixComma = true;
851: }
852: if(bdSize == 1 && ((bs && is && iis > 0) || (bs && iis >= 5)))
853: {
854: if(ea == 0x3B)
855: {
856: sp = Disass68kSpecialRegister(REG_ZPC);
857: if(!sp) return NULL;
858: strcat(disassbuf, sp);
859: } else {
860: strcat(disassbuf, "0");
861: }
862: }
863: if(!bs)
864: {
865: if(prefixComma)
866: strcat(disassbuf, ",");
867: strcat(disassbuf, regName);
868: prefixComma = true;
869: }
870: if(iis >= 5 && iis <= 7)
871: {
872: strcat(disassbuf, "]");
873: prefixComma = true;
874: }
875: if(!is)
876: {
877: if(prefixComma)
878: strcat(disassbuf, ",");
879: if(scale == 0)
880: {
881: sprintf(disassbuf+strlen(disassbuf), "%s.%c", Disass68kRegname(xn), c);
882: } else
883: {
884: sprintf(disassbuf+strlen(disassbuf), "%s.%c*%d", Disass68kRegname(xn), c, 1 << scale);
885: }
886: }
887: if(iis >= 1 && iis <= 3)
888: {
889: strcat(disassbuf, "]");
890: prefixComma = true;
891: }
1.1.1.4 root 892: od = 0;
1.1 root 893: switch(iis & 3)
894: {
895: case 3:
896: od = Disass68kGetWord(*addr); *addr += 2;
897: od <<= 16;
898: case 2:
899: od |= Disass68kGetWord(*addr); *addr += 2;
900: if(prefixComma)
901: strcat(disassbuf, ",");
902: sprintf(disassbuf+strlen(disassbuf), "%s", Disass68kNumber(od));
903: break;
904: default:
905: break;
906: }
907: strcat(disassbuf, ")");
908: }
909: break;
910:
911: // M=111 = 7, Xn/reg = 000 = 0
912: // Absolute Short Addressing Mode
913: // (xxx).W
914: case 0x38:
915: if((allowedEAs & EA_Abs) != EA_Abs)
916: break;
917: eWord1 = Disass68kGetWord(*addr); *addr += 2;
918: val = eWord1;
919: if(eWord1 & 0x8000)
920: val |= 0xFFFF0000;
921: #if USE_SYMBOLS
922: sp = Disass68kSymbolName(val, size);
923: if(sp)
924: {
925: if(options & doptNoBrackets)
926: sprintf(disassbuf, "%s.w", sp);
927: else
928: sprintf(disassbuf, "(%s).w", sp);
929: break;
930: }
931: #endif
932: if(options & doptNoBrackets)
933: {
934: if(val & 0x80000000)
935: sprintf(disassbuf, "$%8.8lx.w", val);
936: else
937: sprintf(disassbuf, "$%4.4lx.w", val);
938: } else {
939: if(val & 0x80000000)
940: sprintf(disassbuf, "($%8.8lx).w", val);
941: else
942: sprintf(disassbuf, "($%4.4lx).w", val);
943: }
944: break;
945:
946: // M=111 = 7, Xn/reg = 001 = 1
947: // Absolute Long Addressing Mode
948: // (xxx).L
949: case 0x39:
950: if((allowedEAs & EA_Abs) != EA_Abs)
951: break;
952: eWord1 = Disass68kGetWord(*addr); *addr += 2;
953: eWord2 = Disass68kGetWord(*addr); *addr += 2;
954: #if USE_SYMBOLS
955: val = (eWord1 << 16) | eWord2;
956: sp = Disass68kSymbolName(val, size);
957: if(sp)
958: {
959: if(options & doptNoBrackets)
960: sprintf(disassbuf, "%s", sp);
961: else
962: sprintf(disassbuf, "(%s).l", sp);
963: break;
964: }
965: #endif
966: if(options & doptNoBrackets)
967: sprintf(disassbuf, "%s", Disass68kNumber((eWord1 << 16) | eWord2));
968: else
969: sprintf(disassbuf, "(%s).l", Disass68kNumber((eWord1 << 16) | eWord2));
970: break;
971:
972: // M=111 = 7, Xn/reg = 010 = 2
973: // Program Counter Indirect with Displacement Mode
974: // (d16,PC)
975: case 0x3A:
976: if((allowedEAs & EA_PCRel) != EA_PCRel)
977: break;
978: eWord1 = Disass68kGetWord(*addr); *addr += 2;
979: sp = Disass68kSpecialRegister(REG_PC);
980: if(!sp) return NULL;
981: #if ADDRESS_ON_PC
982: #if USE_SYMBOLS
983: sp = Disass68kSymbolName(((signed short)eWord1 + *addr - 2), size);
984: if(sp)
985: {
986: sprintf(disassbuf, "%s(%s)", sp, Disass68kSpecialRegister(REG_PC));
987: } else {
988: sprintf(disassbuf, "$%lx(%s)", (signed short)eWord1 + *addr - 2, Disass68kSpecialRegister(REG_PC));
989: }
990: #else
991: sprintf(disassbuf, "$%lx(%s)", (signed short)eWord1 + *addr - 2, Disass68kSpecialRegister(REG_PC));
992: #endif
993: #else
994: sprintf(disassbuf, "%s(%s)", Disass68kNumber(eWord1),sp);
995: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", (signed short)eWord1 + *addr - 2);
996: #endif
997: break;
998:
999: // M=111 = 7, Xn/reg = 100 = 4
1000: // Immediate Data
1001: // #<xxx>
1002: case 0x3C:
1003: if((allowedEAs & EA_Immed) != EA_Immed)
1004: break;
1005: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1006: goto immed;
1007:
1008: case 0x0100: // Immediate Value as a parameter
1009: if((allowedEAs & EA_ImmedParameter) != EA_ImmedParameter)
1010: break;
1011: eWord1 = parameterValue;
1012: immed:
1013: switch(size)
1014: {
1015: case 1: eWord1 &= 0xFF;
1016: case 2:
1017: #if USE_SYMBOLS
1018: if(disassFlag)
1019: {
1020: val = eWord1;
1021: if(eWord1 & 0x8000)
1022: val |= 0xFFFF0000;
1023: sp = Disass68kSymbolName(val, size);
1024: if(sp)
1025: {
1026: sprintf(disassbuf, "#%s", sp);
1027: break;
1028: }
1029: }
1030: #endif
1031: sprintf(disassbuf, "#%s", Disass68kNumber(eWord1));
1032: break;
1033: case 4: eWord2 = Disass68kGetWord(*addr); *addr += 2;
1034: #if USE_SYMBOLS
1035: if(disassFlag)
1036: {
1037: val = (eWord1 << 16) | eWord2;
1038: sp = Disass68kSymbolName(val, size);
1039: if(sp)
1040: {
1041: sprintf(disassbuf, "#%s", sp);
1042: break;
1043: }
1044: }
1045: #endif
1046: sprintf(disassbuf, "#%s", Disass68kNumber((eWord1 << 16) | eWord2));
1047: break;
1048: }
1049: break;
1050:
1051: case 0x0103:
1052: if((allowedEAs & EA_ValueParameter) != EA_ValueParameter)
1053: break;
1054: sprintf(disassbuf, "%d", parameterValue);
1055: break;
1056:
1057: case 0x0101: // Special Registers as in the parameter
1058: if((allowedEAs & EA_SpecialRegister) != EA_SpecialRegister)
1059: break;
1060: sp = Disass68kSpecialRegister(parameterValue);
1061: if(!sp) return NULL;
1062: strcpy(disassbuf, sp);
1063: break;
1064:
1065: case 0x0102: // PC relative jump, like for BRA and friends
1066: if((allowedEAs & EA_PCDisplacement) != EA_PCDisplacement)
1067: break;
1.1.1.4 root 1068: pcoffset = 0;
1.1 root 1069: switch(size)
1070: {
1071: case 1: pcoffset = (signed char)parameterValue;
1072: break;
1073: case 2: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1074: pcoffset = (signed short)eWord1;
1075: pcoffset -= 2;
1076: break;
1077: case 4: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1078: eWord2 = Disass68kGetWord(*addr); *addr += 2;
1079: pcoffset = (signed int)((eWord1 << 16) | eWord2);
1080: pcoffset -= 4;
1081: break;
1082: }
1083: #if ADDRESS_ON_PC
1084: #if USE_SYMBOLS
1085: sp = Disass68kSymbolName((*addr + pcoffset), size);
1086: if(sp)
1087: {
1088: strcat(disassbuf, sp);
1089: } else {
1090: sprintf(disassbuf, "$%lx", *addr + pcoffset);
1091: }
1092: #else
1093: sprintf(disassbuf, "$%lx", *addr + pcoffset);
1094: #endif
1095: #else
1096: if(pcoffset < 0)
1097: {
1098: sprintf(disassbuf, "*-$%lx", -pcoffset - 2);
1099: } else {
1100: sprintf(disassbuf, "*+$%lx", pcoffset + 2);
1101: }
1102: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", *addr + pcoffset);
1103: #endif
1104: break;
1105:
1106: default: // 0x3D..0x3F are reserved
1107: break;
1108:
1109: }
1110: if(disassbuf[0] == 0)
1111: return NULL;
1112: return disassbuf + strlen(disassbuf);
1113: }
1114:
1115: /***
1116: * Create a register list for the MOVEM opcode
1117: ***/
1118: static char *Disass68kReglist(char *buf, unsigned short reglist)
1119: {
1120: int bit;
1121: int lastBit = -99;
1122: int lastBitStart = -99;
1123: char regD = options & doptRegisterSmall ? 'd' : 'D';
1124: char regA = options & doptRegisterSmall ? 'a' : 'A';
1125: for(bit=0; bit<=15; ++bit)
1126: {
1127: // bit clear?
1128: if((reglist & (1 << bit)) == 0)
1129: {
1130: // do we have a run? => close it!
1131: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1132: {
1133: *buf++ = '-';
1134: *buf++ = ((bit-1) >= 8) ? regA : regD;
1135: *buf++ = '0' + ((bit-1) & 7);
1136: }
1137: lastBitStart = -1;
1138: continue;
1139: }
1140: // reset when switching from D to A
1141: if(bit == 8 && lastBitStart >= 0)
1142: {
1143: *buf++ = '-';
1144: *buf++ = regD;
1145: *buf++ = '7';
1146: lastBit = 0;
1147: lastBitStart = -99;
1148: }
1149: // separate bits, skip runs of bits to merge them later
1150: if(lastBit >= 0)
1151: {
1152: if(lastBit == bit - 1)
1153: {
1154: lastBit = bit;
1155: continue;
1156: }
1157: *buf++ = '/';
1158: }
1159: *buf++ = (bit >= 8) ? regA : regD;
1160: *buf++ = '0' + (bit & 7);
1161: lastBit = bit;
1162: lastBitStart = bit;
1163: }
1164: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1165: {
1166: *buf++ = '-';
1167: *buf++ = regA;
1168: *buf++ = '7';
1169: }
1170: if(lastBit < 0)
1171: {
1172: *buf++ = '0';
1173: }
1174: *buf = 0;
1175: return buf;
1176: }
1177:
1178: /***
1179: * Flip the bits in an unsigned short, for MOVEM RegList,-(An)
1180: ***/
1181: static unsigned short Disass68kFlipBits(unsigned short mask)
1182: {
1183: unsigned short retMask = 0;
1184: int i;
1185:
1186: for(i=0; i<=15; ++i)
1187: if(mask & (1 << i))
1188: retMask |= (1 << (15-i));
1189: return retMask;
1190: }
1191:
1192: /***
1193: * Create a register list for the MOVEM opcode
1194: ***/
1195: static char *Disass68kFPUReglist(char *buf, unsigned char reglist)
1196: {
1197: int bit;
1198: int lastBit = -99;
1199: int lastBitStart = -99;
1200: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
1201: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
1202: for(bit=0; bit<=7; ++bit)
1203: {
1204: // bit clear?
1205: if((reglist & (1 << bit)) == 0)
1206: {
1207: // do we have a run? => close it!
1208: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1209: {
1210: *buf++ = '-';
1211: *buf++ = regFP1;
1212: *buf++ = regFP2;
1213: *buf++ = '0' + ((bit-1) & 7);
1214: }
1215: lastBitStart = -1;
1216: continue;
1217: }
1218: // separate bits, skip runs of bits to merge them later
1219: if(lastBit >= 0)
1220: {
1221: if(lastBit == bit - 1)
1222: {
1223: lastBit = bit;
1224: continue;
1225: }
1226: *buf++ = '/';
1227: }
1228: *buf++ = regFP1;
1229: *buf++ = regFP2;
1230: *buf++ = '0' + (bit & 7);
1231: lastBit = bit;
1232: lastBitStart = bit;
1233: }
1234: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1235: {
1236: *buf++ = '-';
1237: *buf++ = regFP1;
1238: *buf++ = regFP2;
1239: *buf++ = '7';
1240: }
1241: if(lastBit < 0)
1242: {
1243: *buf++ = '0';
1244: }
1245: *buf = 0;
1246: return buf;
1247: }
1248:
1249:
1250: /***
1251: * List of special cases for the operands
1252: ***/
1253: typedef enum {
1254: ofNone,
1255: ofEa,
1256: ofDn,
1257: ofAn,
1258: ofAni,
1259: ofI,
1260: ofSpecReg,
1261: ofSpecExtReg,
1262: ofD16An,
1263: ofDestDn,
1264: ofDestAn,
1265: ofExtReg,
1266: ofExtAnip,
1267: ofExtReg0,
1268: ofExtRegA0,
1269: ofExtRegD04,
1270: ofExtRegA05,
1271: ofFPUReglist,
1272: ofFPUSRRegList,
1273: ofDestEa6,
1274: ofDestAbsL,
1275: ofIOpcode,
1276: ofCAS,
1277: ofCAS2,
1278: ofI3,
1279: ofExtIm,
1280: ofExtIm32,
1281: ofExtIm4,
1282: ofExtIm10,
1283: ofDisp,
1284: ofPiAn,
1285: ofDestPiAn,
1286: ofAnip,
1287: ofDestAnip,
1288: ofBFEa,
1289: ofRegList,
1290: ofExt4Dn,
1291: ofFPU,
1292: ofFPUMOVE,
1293: ofFMOVECR,
1294: ofFPU3Reg,
1.1.1.5 root 1295: ofLineA
1.1 root 1296: } Disass68kOpcodeFormat;
1297:
1298:
1299: /***
1300: * The order of the table is not important (with the exception of some FPU opcodes, which are commented further down),
1301: * as each opcode should decline if it doesn't match 100%. The 68k CPU also doesn't do guessing based on the context!
1302: ***/
1303: typedef const struct {
1304: int cpuMask;
1305: unsigned long opcodeMask[2*5];
1.1.1.4 root 1306: signed char operationSize[4];
1.1 root 1307: char op[5];
1308: const char *opcodeName;
1309: int parameter[5];
1310: int disassFlag;
1311: } OpcodeTableStruct;
1312:
1.1.1.6 root 1313: static OpcodeTableStruct OpcodeTable[] = {
1.1 root 1314: { MC_ALL, {0xff00, 0x0000}, {-1,6,2,0}, {ofI,ofEa}, "ORI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1315: { MC_ALL, {0xf1c0, 0x0100}, {4}, {ofDestDn,ofEa}, "BTST",{0,EA_An|EA_Immed} },
1316: { MC_ALL, {0xf1c0, 0x0140}, {4}, {ofDestDn,ofEa}, "BCHG",{0,EA_Immed|EA_PCRel|EA_An}},
1317: { MC_ALL, {0xf1c0, 0x0180}, {4}, {ofDestDn,ofEa}, "BCLR",{0,EA_Immed|EA_PCRel|EA_An}},
1318: { MC_ALL, {0xf1c0, 0x01C0}, {4}, {ofDestDn,ofEa}, "BSET",{0,EA_Immed|EA_PCRel|EA_An}},
1319: { MC_ALL-MC68060, {0xf1f8, 0x0108}, {2}, {ofD16An,ofDestDn}, "MOVEP.W"},
1320: { MC_ALL-MC68060, {0xf1f8, 0x0148}, {4}, {ofD16An,ofDestDn}, "MOVEP.L"},
1321: { MC_ALL-MC68060, {0xf1f8, 0x0188}, {2}, {ofDestDn,ofD16An}, "MOVEP.W"},
1322: { MC_ALL-MC68060, {0xf1f8, 0x01C8}, {4}, {ofDestDn,ofD16An}, "MOVEP.L"},
1323: { MC_ALL, {0xff00, 0x0200}, {-1,6,2,0}, {ofI,ofEa}, "ANDI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1324: { MC_ALL, {0xff00, 0x0400}, {-1,6,2,0}, {ofI,ofEa}, "SUBI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1325: { MC_ALL, {0xff00, 0x0600}, {-1,6,2,0}, {ofI,ofEa}, "ADDI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1326: { MC_ALL, {0xffc0, 0x0800}, {1}, {ofI,ofEa}, "BTST",{0,EA_An|EA_Immed} },
1327: { MC_ALL, {0xffc0, 0x0840}, {1}, {ofI,ofEa}, "BCHG",{0,EA_Immed|EA_PCRel|EA_An}},
1328: { MC_ALL, {0xffc0, 0x0880}, {1}, {ofI,ofEa}, "BCLR",{0,EA_Immed|EA_PCRel|EA_An}},
1329: { MC_ALL, {0xffc0, 0x08C0}, {1}, {ofI,ofEa}, "BSET",{0,EA_Immed|EA_PCRel|EA_An}},
1330: { MC_ALL, {0xff00, 0x0A00}, {-1,6,2,0}, {ofI,ofEa}, "EORI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1331: { MC_ALL, {0xff00, 0x0C00}, {-1,6,2,0}, {ofI,ofEa}, "CMPI.?",{0,EA_Immed|EA_An}},
1332: { MC_ALL, {0xffff, 0x003C}, {1}, {ofEa,ofSpecReg}, "ORI",{0,REG_CCR} },
1333: { MC_ALL, {0xffff, 0x007C}, {2}, {ofEa,ofSpecReg}, "ORI",{0,REG_SR} },
1334: { MC_ALL, {0xffff, 0x023C}, {1}, {ofEa,ofSpecReg}, "ANDI",{0,REG_CCR} },
1335: { MC_ALL, {0xffff, 0x027C}, {2}, {ofEa,ofSpecReg}, "ANDI",{0,REG_SR} },
1336: { MC_ALL, {0xffff, 0x0A3C}, {1}, {ofEa,ofSpecReg}, "EORI",{0,REG_CCR} },
1337: { MC_ALL, {0xffff, 0x0A7C}, {2}, {ofEa,ofSpecReg}, "EORI",{0,REG_SR} },
1338: { MC68020, {0xffc0, 0x06C0}, {1}, {ofEa}, "CALLM",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1339: { MC68020, {0xfff0, 0x06C0}, {1}, {ofEa}, "RTM"},
1340: { MC_020, {0xf9c0, 0x00C0, 0x0fff,0x0000}, {-1,9,2,0}, {ofEa,ofExtReg}, "CMP2.?",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1341: { MC_020, {0xf9c0, 0x00C0, 0x0fff,0x0800}, {-1,9,2,0}, {ofEa,ofExtReg}, "CHK2.?",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1342: { MC_020&~MC_CPU32, {0xffc0, 0x0AC0, 0xFE38,0x0000}, {1}, {ofCAS,ofEa}, "CAS.B",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1343: { MC_020&~MC_CPU32, {0xffc0, 0x0CC0, 0xFE38,0x0000}, {2}, {ofCAS,ofEa}, "CAS.W",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1344: { MC_020&~MC_CPU32, {0xffc0, 0x0EC0, 0xFE38,0x0000}, {4}, {ofCAS,ofEa}, "CAS.L",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1345: { MC_020&~MC_CPU32, {0xffff, 0x0CFC, 0x0E38,0x0000, 0x0E38,0x0000}, {2}, {ofCAS2}, "CAS2.W"},
1346: { MC_020&~MC_CPU32, {0xffff, 0x0EFC, 0x0E38,0x0000, 0x0E38,0x0000}, {4}, {ofCAS2}, "CAS2.L"},
1347: { MC68010|MC_020, {0xff00, 0x0e00, 0x0fff,0x0000}, {-1,6,2,0}, {ofEa,ofExtReg}, "MOVES.?",{EA_Immed|EA_PCRel|EA_An|EA_Dn,0}},
1348: { MC68010|MC_020, {0xff00, 0x0e00, 0x0fff,0x0800}, {-1,6,2,0}, {ofExtReg,ofEa}, "MOVES.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1349:
1350: { MC_ALL, {0xf000, 0x1000}, {1}, {ofEa,ofDestEa6}, "MOVE.B"},
1351:
1352: { MC_ALL, {0xf000, 0x2000}, {4}, {ofEa,ofDestEa6}, "MOVE.L"},
1353: { MC_ALL, {0xf1c0, 0x2040}, {4}, {ofEa,ofDestAn}, "MOVEA.L",{0},1},
1354:
1355: { MC_ALL, {0xf000, 0x3000}, {2}, {ofEa,ofDestEa6}, "MOVE.W"},
1356: { MC_ALL, {0xf1c0, 0x3040}, {2}, {ofEa,ofDestAn}, "MOVEA.W",{0},1},
1357:
1358: { MC_ALL, {0xff00, 0x4000}, {-1,6,2,0}, {ofEa}, "NEGX.?",{EA_Immed|EA_PCRel|EA_An}},
1359: { MC_020, {0xf1c0, 0x4100}, {4}, {ofEa,ofDestDn}, "CHK.L", {EA_An,0}},
1360: { MC_ALL, {0xf1c0, 0x4180}, {2}, {ofEa,ofDestDn}, "CHK.W", {EA_An,0}},
1361: { MC_ALL, {0xf1c0, 0x41c0}, {4}, {ofEa,ofDestAn}, "LEA",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn,0},1 },
1362: { MC_ALL, {0xff00, 0x4200}, {-1,6,2,0}, {ofEa}, "CLR.?",{EA_Immed|EA_PCRel|EA_An}},
1363: { MC_ALL, {0xff00, 0x4400}, {-1,6,2,0}, {ofEa}, "NEG.?",{EA_Immed|EA_PCRel|EA_An}},
1364: { MC_ALL, {0xff00, 0x4600}, {-1,6,2,0}, {ofEa}, "NOT.?",{EA_Immed|EA_PCRel|EA_An}},
1365: { MC_ALL, {0xffc0, 0x40c0}, {2}, {ofSpecReg,ofEa}, "MOVE",{REG_SR,EA_Immed|EA_PCRel|EA_An} },
1366: { MC_ALL, {0xffc0, 0x42c0}, {1}, {ofSpecReg,ofEa}, "MOVE",{REG_CCR,EA_Immed|EA_PCRel|EA_An} },
1367: { MC_ALL, {0xffc0, 0x44c0}, {1}, {ofEa,ofSpecReg}, "MOVE",{EA_An,REG_CCR} },
1368: { MC_ALL, {0xffc0, 0x46c0}, {2}, {ofEa,ofSpecReg}, "MOVE",{EA_An,REG_SR} },
1369: { MC_ALL, {0xffc0, 0x4800}, {1}, {ofEa}, "NBCD",{EA_Immed|EA_PCRel|EA_An}},
1370: { MC_020, {0xfff8, 0x4808}, {4}, {ofEa,ofI}, "LINK.L"},
1371: { MC_ALL, {0xffc0, 0x4840}, {0}, {ofEa}, "PEA",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn},1 },
1372: { MC_ALL, {0xfff8, 0x4840}, {4}, {ofEa}, "SWAP"},
1373: { MC68010|MC_020, {0xfff8, 0x4848}, {0}, {ofIOpcode}, "BKPT",{0x07} },
1374: { MC_ALL, {0xffc0, 0x4880, 0x10000}, {2}, {ofRegList,ofEa}, "MOVEM.W",{0,EA_Dn|EA_An|EA_Immed|EA_Anip|EA_PCRel} },
1375: { MC_ALL, {0xffc0, 0x48c0, 0x10000}, {4}, {ofRegList,ofEa}, "MOVEM.L",{0,EA_Dn|EA_An|EA_Immed|EA_Anip|EA_PCRel} },
1376: { MC_ALL, {0xfff8, 0x4880}, {2}, {ofEa}, "EXT.W"},
1377: { MC_ALL, {0xfff8, 0x48c0}, {4}, {ofEa}, "EXT.L"},
1378: { MC_020, {0xfff8, 0x49c0}, {4}, {ofEa}, "EXTB.L"},
1379: { MC_ALL, {0xff00, 0x4a00}, {-1,6,2,0}, {ofEa}, "TST.?"},
1380: { MC_ALL, {0xffc0, 0x4ac0}, {1}, {ofEa}, "TAS",{EA_Immed|EA_PCRel|EA_An}},
1381: { MC_CPU32, {0xffff, 0x4afa}, {0}, {ofNone}, "BGND"},
1382: { MC_ALL, {0xffff, 0x4afc}, {0}, {ofNone}, "ILLEGAL"},
1383: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0000}, {4}, {ofEa,ofExtReg}, "MULU.L", {EA_An,0}},
1384: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0800}, {4}, {ofEa,ofExtReg}, "MULS.L", {EA_An,0}},
1385: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0000}, {4}, {ofEa,ofExtReg}, "DIVU.L", {EA_An,0}},
1386: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0800}, {4}, {ofEa,ofExtReg}, "DIVS.L", {EA_An,0}},
1387: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0400}, {4}, {ofEa,ofExtReg,ofExtReg0}, "MULU.L", {EA_An,0,0}},
1388: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0c00}, {4}, {ofEa,ofExtReg,ofExtReg0}, "MULS.L", {EA_An,0,0}},
1389: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0400}, {4}, {ofEa,ofExtReg,ofExtReg0}, "DIVU.L", {EA_An,0,0}},
1390: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0c00}, {4}, {ofEa,ofExtReg,ofExtReg0}, "DIVS.L", {EA_An,0,0}},
1391: { MC_ALL, {0xffc0, 0x4c80, 0x10000}, {2}, {ofEa,ofRegList}, "MOVEM.W",{EA_Dn|EA_An|EA_Immed|EA_piAn,0} },
1392: { MC_ALL, {0xffc0, 0x4cc0, 0x10000}, {4}, {ofEa,ofRegList}, "MOVEM.L",{EA_Dn|EA_An|EA_Immed|EA_piAn,0} },
1393: { MC_ALL, {0xfff0, 0x4e40}, {0}, {ofIOpcode}, "TRAP",{0x0f} },
1394: { MC_ALL, {0xfff8, 0x4e50}, {2}, {ofAn,ofI}, "LINK"},
1395: { MC_ALL, {0xfff8, 0x4e58}, {4}, {ofAn}, "UNLK"},
1396: { MC_ALL, {0xfff8, 0x4e60}, {4}, {ofAn,ofSpecReg}, "MOVE",{0,REG_USP} },
1397: { MC_ALL, {0xfff8, 0x4e68}, {4}, {ofSpecReg,ofAn}, "MOVE",{REG_USP,0} },
1398: { MC_ALL, {0xffff, 0x4e70}, {0}, {ofNone}, "RESET"},
1399: { MC_ALL, {0xffff, 0x4e71}, {0}, {ofNone}, "NOP"},
1400: { MC_ALL, {0xffff, 0x4e72}, {2}, {ofI}, "STOP"},
1401: { MC_ALL, {0xffff, 0x4e73}, {0}, {ofNone}, "RTE"},
1402: { MC68010|MC_020, {0xffff, 0x4e74}, {2}, {ofI}, "RTD"},
1403: { MC_ALL, {0xffff, 0x4e75}, {0}, {ofNone}, "RTS"},
1404: { MC_ALL, {0xffff, 0x4e76}, {0}, {ofNone}, "TRAPV"},
1405: { MC_ALL, {0xffff, 0x4e77}, {0}, {ofNone}, "RTR"},
1406: { MC68010|MC_020, {0xffff, 0x4e7a, 0x10000}, {4}, {ofSpecExtReg,ofExtReg}, "MOVEC"},
1407: { MC68010|MC_020, {0xffff, 0x4e7b, 0x10000}, {4}, {ofExtReg,ofSpecExtReg}, "MOVEC"},
1408: { MC_ALL, {0xffc0, 0x4e80}, {0}, {ofEa}, "JSR",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1409: { MC_ALL, {0xffc0, 0x4ec0}, {0}, {ofEa}, "JMP",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1410:
1411: { MC_ALL, {0xf1c0, 0x5000}, {1}, {ofI3,ofEa}, "ADDQ.B",{0,EA_An|EA_Immed|EA_PCRel} },
1412: { MC_ALL, {0xf1c0, 0x5040}, {2}, {ofI3,ofEa}, "ADDQ.W",{0,EA_Immed|EA_PCRel} },
1413: { MC_ALL, {0xf1c0, 0x5080}, {4}, {ofI3,ofEa}, "ADDQ.L",{0,EA_Immed|EA_PCRel} },
1414: { MC_ALL, {0xf0c0, 0x50C0}, {1}, {ofEa}, "Sci",{EA_Immed|EA_PCRel|EA_An}},
1415: { MC_ALL, {0xf0f8, 0x50C8}, {2}, {ofDn,ofDisp}, "DBcd"},
1416: { MC_020, {0xf0ff, 0x50fa}, {2}, {ofI}, "TRAPci.W"},
1417: { MC_020, {0xf0ff, 0x50fb}, {4}, {ofI}, "TRAPci.L"},
1418: { MC_020, {0xf0ff, 0x50fc}, {0}, {ofNone}, "TRAPci"},
1419: { MC_ALL, {0xf1c0, 0x5100}, {1}, {ofI3,ofEa}, "SUBQ.B",{0,EA_An|EA_Immed|EA_PCRel} },
1420: { MC_ALL, {0xf1c0, 0x5140}, {2}, {ofI3,ofEa}, "SUBQ.W",{0,EA_Immed|EA_PCRel} },
1421: { MC_ALL, {0xf1c0, 0x5180}, {4}, {ofI3,ofEa}, "SUBQ.L",{0,EA_Immed|EA_PCRel} },
1422:
1423: { MC_ALL, {0xf0ff, 0x6000}, {2}, {ofDisp}, "Bcb"},
1424: { MC_ALL, {0xf000, 0x6000}, {1}, {ofDisp}, "Bcb.S"},
1425: { MC_020, {0xf0ff, 0x60FF}, {4}, {ofDisp}, "Bcb.L"},
1426:
1427: { MC_ALL, {0xf100, 0x7000}, {0}, {ofIOpcode,ofDestDn}, "MOVEQ", {0xFF,0}},
1428:
1429: { MC_ALL, {0xf100, 0x8000}, {-1,6,2,0}, {ofEa,ofDestDn}, "OR.?", {EA_An,0}},
1430: { MC_ALL, {0xf100, 0x8100}, {-1,6,2,0}, {ofDestDn,ofEa}, "OR.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1431: { MC_ALL, {0xf1f8, 0x8100}, {1}, {ofDn,ofDestDn}, "SBCD"},
1432: { MC_ALL, {0xf1f8, 0x8108}, {1}, {ofPiAn,ofDestPiAn}, "SBCD"},
1433: { MC_020&~MC_CPU32, {0xf1f8, 0x8140, 0x10000}, {0}, {ofDn,ofDestDn,ofExtIm}, "PACK"},
1434: { MC_020&~MC_CPU32, {0xf1f8, 0x8148, 0x10000}, {0}, {ofPiAn,ofDestPiAn,ofExtIm}, "PACK"},
1435: { MC_020&~MC_CPU32, {0xf1f8, 0x8180, 0x10000}, {0}, {ofDn,ofDestDn,ofExtIm}, "UNPK"},
1436: { MC_020&~MC_CPU32, {0xf1f8, 0x8188, 0x10000}, {0}, {ofPiAn,ofDestPiAn,ofExtIm}, "UNPK"},
1437: { MC_ALL, {0xf1c0, 0x80c0}, {2}, {ofEa,ofDestDn}, "DIVU.W", {EA_An,0}},
1438: { MC_ALL, {0xf1c0, 0x81c0}, {2}, {ofEa,ofDestDn}, "DIVS.W", {EA_An,0}},
1439:
1440: { MC_ALL, {0xf1c0, 0x9000}, {1}, {ofEa,ofDestDn}, "SUB.B", {EA_An,0}},
1441: { MC_ALL, {0xf1c0, 0x9040}, {2}, {ofEa,ofDestDn}, "SUB.W"},
1442: { MC_ALL, {0xf1c0, 0x9080}, {4}, {ofEa,ofDestDn}, "SUB.L"},
1443: { MC_ALL, {0xf1c0, 0x90c0}, {2}, {ofEa,ofDestAn}, "SUBA.W"},
1444: { MC_ALL, {0xf1c0, 0x91c0}, {4}, {ofEa,ofDestAn}, "SUBA.L"},
1445: { MC_ALL, {0xf100, 0x9100}, {-1,6,2,0}, {ofDestDn,ofEa}, "SUB.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1446: { MC_ALL, {0xf138, 0x9100}, {-1,6,2,0}, {ofDn,ofDestDn}, "SUBX.?"},
1447: { MC_ALL, {0xf138, 0x9108}, {-1,6,2,0}, {ofPiAn,ofDestPiAn}, "SUBX.?"},
1448:
1449: { MC_ALL, {0xf000, 0xa000}, {0}, {ofLineA}, "LINEA"},
1450:
1451: { MC_ALL, {0xf1c0, 0xb000}, {1}, {ofEa,ofDestDn}, "CMP.B", {EA_An,0}},
1452: { MC_ALL, {0xf1c0, 0xb040}, {2}, {ofEa,ofDestDn}, "CMP.W"},
1453: { MC_ALL, {0xf1c0, 0xb080}, {4}, {ofEa,ofDestDn}, "CMP.L"},
1454: { MC_ALL, {0xf1c0, 0xb0c0}, {2}, {ofEa,ofDestAn}, "CMPA.W"},
1455: { MC_ALL, {0xf1c0, 0xb1c0}, {4}, {ofEa,ofDestAn}, "CMPA.L"},
1456: { MC_ALL, {0xf100, 0xb100}, {-1,6,2,0}, {ofDestDn,ofEa}, "EOR.?",{0,EA_An|EA_Immed|EA_PCRel} },
1457: { MC_ALL, {0xf138, 0xb108}, {-1,6,2,0}, {ofAnip,ofDestAnip}, "CMPM.?"},
1458:
1459: { MC_ALL, {0xf100, 0xc000}, {-1,6,2,0}, {ofEa,ofDestDn}, "AND.?", {EA_An,0}},
1460: { MC_ALL, {0xf100, 0xc100}, {-1,6,2,0}, {ofDestDn,ofEa}, "AND.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1461: { MC_ALL, {0xf1f8, 0xc100}, {1}, {ofDn,ofDestDn}, "ABCD"},
1462: { MC_ALL, {0xf1f8, 0xc108}, {1}, {ofPiAn,ofDestPiAn}, "ABCD"},
1463: { MC_ALL, {0xf1f8, 0xc140}, {1}, {ofDestDn,ofDn}, "EXG"},
1464: { MC_ALL, {0xf1f8, 0xc148}, {1}, {ofDestAn,ofAn}, "EXG"},
1465: { MC_ALL, {0xf1f8, 0xc188}, {1}, {ofDestDn,ofAn}, "EXG"},
1466: { MC_ALL, {0xf1c0, 0xc0c0}, {2}, {ofEa,ofDestDn}, "MULU.W", {EA_An,0}},
1467: { MC_ALL, {0xf1c0, 0xc1c0}, {2}, {ofEa,ofDestDn}, "MULS.W", {EA_An,0}},
1468:
1469: { MC_ALL, {0xf1c0, 0xd000}, {1}, {ofEa,ofDestDn}, "ADD.B", {EA_An,0}},
1470: { MC_ALL, {0xf1c0, 0xd040}, {2}, {ofEa,ofDestDn}, "ADD.W"},
1471: { MC_ALL, {0xf1c0, 0xd080}, {4}, {ofEa,ofDestDn}, "ADD.L"},
1472: { MC_ALL, {0xf1c0, 0xd0c0}, {2}, {ofEa,ofDestAn}, "ADDA.W"},
1473: { MC_ALL, {0xf1c0, 0xd1c0}, {4}, {ofEa,ofDestAn}, "ADDA.L"},
1474: { MC_ALL, {0xf100, 0xd100}, {-1,6,2,0}, {ofDestDn,ofEa}, "ADD.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1475: { MC_ALL, {0xf138, 0xd100}, {-1,6,2,0}, {ofDn,ofDestDn}, "ADDX.?"},
1476: { MC_ALL, {0xf138, 0xd108}, {-1,6,2,0}, {ofPiAn,ofDestPiAn}, "ADDX.?"},
1477:
1478: { MC_ALL, {0xf138, 0xe000}, {-1,6,2,0}, {ofI3,ofDn}, "ASR.?"},
1479: { MC_ALL, {0xf138, 0xe008}, {-1,6,2,0}, {ofI3,ofDn}, "LSR.?"},
1480: { MC_ALL, {0xf138, 0xe010}, {-1,6,2,0}, {ofI3,ofDn}, "ROXR.?"},
1481: { MC_ALL, {0xf138, 0xe018}, {-1,6,2,0}, {ofI3,ofDn}, "ROR.?"},
1482: { MC_ALL, {0xf138, 0xe020}, {-1,6,2,0}, {ofDestDn,ofDn}, "ASR.?"},
1483: { MC_ALL, {0xf138, 0xe028}, {-1,6,2,0}, {ofDestDn,ofDn}, "LSR.?"},
1484: { MC_ALL, {0xf138, 0xe030}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROXR.?"},
1485: { MC_ALL, {0xf138, 0xe038}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROR.?"},
1486: { MC_ALL, {0xf138, 0xe100}, {-1,6,2,0}, {ofI3,ofDn}, "ASL.?"},
1487: { MC_ALL, {0xf138, 0xe108}, {-1,6,2,0}, {ofI3,ofDn}, "LSL.?"},
1488: { MC_ALL, {0xf138, 0xe110}, {-1,6,2,0}, {ofI3,ofDn}, "ROXL.?"},
1489: { MC_ALL, {0xf138, 0xe118}, {-1,6,2,0}, {ofI3,ofDn}, "ROL.?"},
1490: { MC_ALL, {0xf138, 0xe120}, {-1,6,2,0}, {ofDestDn,ofDn}, "ASL.?"},
1491: { MC_ALL, {0xf138, 0xe128}, {-1,6,2,0}, {ofDestDn,ofDn}, "LSL.?"},
1492: { MC_ALL, {0xf138, 0xe130}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROXL.?"},
1493: { MC_ALL, {0xf138, 0xe138}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROL.?"},
1494: { MC_ALL, {0xffc0, 0xe0c0}, {1}, {ofEa}, "ASR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1495: { MC_ALL, {0xffc0, 0xe1c0}, {1}, {ofEa}, "ASL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1496: { MC_ALL, {0xffc0, 0xe2c0}, {1}, {ofEa}, "LSR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1497: { MC_ALL, {0xffc0, 0xe3c0}, {1}, {ofEa}, "LSL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1498: { MC_ALL, {0xffc0, 0xe4c0}, {1}, {ofEa}, "ROXR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1499: { MC_ALL, {0xffc0, 0xe5c0}, {1}, {ofEa}, "ROXL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1500: { MC_ALL, {0xffc0, 0xe6c0}, {1}, {ofEa}, "ROR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1501: { MC_ALL, {0xffc0, 0xe7c0}, {1}, {ofEa}, "ROL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1502: { MC_020&~MC_CPU32, {0xffc0, 0xe8c0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFTST",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1503: { MC_020&~MC_CPU32, {0xffc0, 0xe9c0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFEXTU",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1504: { MC_020&~MC_CPU32, {0xffc0, 0xeac0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFCHG",{EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1505: { MC_020&~MC_CPU32, {0xffc0, 0xebc0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFEXTS",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1506: { MC_020&~MC_CPU32, {0xffc0, 0xecc0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFCLR",{EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1507: { MC_020&~MC_CPU32, {0xffc0, 0xedc0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFFFO",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1508: { MC_020&~MC_CPU32, {0xffc0, 0xeec0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFSET",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1509: { MC_020&~MC_CPU32, {0xffc0, 0xefc0, 0x8000, 0x0000}, {1}, {ofExtReg,ofBFEa}, "BFINS",{0,EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1510:
1511:
1512: #define PMMU_COPROC_ID 0 // 0 is the standard PMMU
1513:
1514: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2000}, {0}, {ofSpecReg,ofEa}, "PLOADW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1515: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2001}, {0}, {ofSpecReg,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1516: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2008}, {0}, {ofExtReg0,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1517: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff0, 0x2010}, {0}, {ofExtIm4,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1518:
1519: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2200}, {0}, {ofSpecReg,ofEa}, "PLOADR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1520: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2201}, {0}, {ofSpecReg,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1521: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2208}, {0}, {ofExtReg0,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1522: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff0, 0x2210}, {0}, {ofExtIm4,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1523:
1524: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0xa000}, {0}, {ofEa}, "PFLUSHR",{EA_Dn|EA_An} },
1525:
1526: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0800}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1527: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0900}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1528: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0B00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1529: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0C00}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1530: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0C00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1531: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0D00}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1532: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0E00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1533: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0F00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1534: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4000}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1535: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4100}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1536: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4200}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1537: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4300}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1538: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4800}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1539: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4900}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1540: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4A00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1541: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4B00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1542: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4C00}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1543: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4D00}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1544: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4e00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1545: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4f00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1546: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x6000}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_MMUSR} },
1547: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x6200}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_MMUSR} },
1548:
1549: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2800}, {0}, {ofSpecReg,ofEa}, "PVALID",{REG_VAL,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1550: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2C00}, {0}, {ofExtRegA0,ofEa}, "PVALID",{0,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1551:
1552: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8000}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1553: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8001}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1554: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f8, 0x8008}, {0}, {ofExtReg0,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1555: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f0, 0x8010}, {0}, {ofExtIm4,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1556:
1557: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8200}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1558: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8201}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1559: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f8, 0x8208}, {0}, {ofExtReg0,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1560: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f0, 0x8210}, {0}, {ofExtIm4,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1561:
1562: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8100}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1563: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8101}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1564: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe318, 0x8108}, {0}, {ofExtReg0,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1565: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe310, 0x8110}, {0}, {ofExtIm4,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1566:
1567: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8300}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1568: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8301}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1569: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe318, 0x8308}, {0}, {ofExtReg0,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1570: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe310, 0x8310}, {0}, {ofExtIm4,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1571:
1572: { MC_PMMU, {0xffc0, 0xf040|(PMMU_COPROC_ID<<9), 0xfff0, 0x8310}, {0}, {ofEa}, "PScp",{EA_An|EA_Immed|EA_PCRel} },
1573: { MC_PMMU, {0xfff8, 0xf048|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000}, {2}, {ofDn,ofDisp}, "PDBcp"},
1574: { MC_PMMU, {0xffff, 0xf07A|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {2}, {ofExtIm32}, "PTRAPcp.W" },
1575: { MC_PMMU, {0xffff, 0xf07B|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {4}, {ofExtIm32}, "PTRAPcp.L" },
1576: { MC_PMMU, {0xffff, 0xf07C|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000}, {0}, {ofNone}, "PTRAPcp" },
1577: { MC_PMMU, {0xfff0, 0xf080|(PMMU_COPROC_ID<<9)}, {2}, {ofDisp}, "PBcp.W"},
1578: { MC_PMMU, {0xfff0, 0xf0C0|(PMMU_COPROC_ID<<9)}, {4}, {ofDisp}, "PBcp.L"},
1579: { MC_PMMU, {0xffc0, 0xf100|(PMMU_COPROC_ID<<9)}, {0}, {ofEa}, "PSAVE",{EA_Dn|EA_An|EA_Anip|EA_Immed} },
1580: { MC_PMMU, {0xffc0, 0xf140|(PMMU_COPROC_ID<<9)}, {0}, {ofEa}, "PRESTORE",{EA_Dn|EA_An|EA_piAn|EA_Immed} },
1581:
1582:
1583: #define MC040_COPROC_ID 3 // 3 is the code for some 68040/68060 opcodes
1584:
1585: { MC68040|MC68060, {0xfff8, 0xf000|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAnip,ofDestAbsL}, "MOVE16"},
1586: { MC68040|MC68060, {0xfff8, 0xf008|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofDestAbsL,ofAnip}, "MOVE16"},
1587: { MC68040|MC68060, {0xfff8, 0xf010|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAni,ofDestAbsL}, "MOVE16"},
1588: { MC68040|MC68060, {0xfff8, 0xf018|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofDestAbsL,ofAni}, "MOVE16"},
1589: { MC68040|MC68060, {0xfff8, 0xf020|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAnip,ofExtAnip}, "MOVE16"},
1590:
1591:
1592: #define CPU32_COPROC_ID 4 // 4 is the code for some CPU32 opcodes
1593:
1594: { MC68040|MC68060, {0xfff8, 0xf008|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_NONE} },
1595: { MC68040|MC68060, {0xfff8, 0xf048|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_DC} },
1596: { MC68040|MC68060, {0xfff8, 0xf088|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_IC} },
1597: { MC68040|MC68060, {0xfff8, 0xf0C8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_ICDC} },
1598:
1599: { MC68040|MC68060, {0xfff8, 0xf010|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_NONE} },
1600: { MC68040|MC68060, {0xfff8, 0xf050|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_DC} },
1601: { MC68040|MC68060, {0xfff8, 0xf090|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_IC} },
1602: { MC68040|MC68060, {0xfff8, 0xf0D0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_ICDC} },
1603:
1604: { MC68040|MC68060, {0xfff8, 0xf018|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_NONE} },
1605: { MC68040|MC68060, {0xfff8, 0xf058|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_DC} },
1606: { MC68040|MC68060, {0xfff8, 0xf098|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_IC} },
1607: { MC68040|MC68060, {0xfff8, 0xf0D8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_ICDC} },
1608:
1609: { MC68040|MC68060, {0xfff8, 0xf028|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_NONE} },
1610: { MC68040|MC68060, {0xfff8, 0xf068|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_DC} },
1611: { MC68040|MC68060, {0xfff8, 0xf0A8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_IC} },
1612: { MC68040|MC68060, {0xfff8, 0xf0E8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_ICDC} },
1613:
1614: { MC68040|MC68060, {0xfff8, 0xf030|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_NONE} },
1615: { MC68040|MC68060, {0xfff8, 0xf070|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_DC} },
1616: { MC68040|MC68060, {0xfff8, 0xf0B0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_IC} },
1617: { MC68040|MC68060, {0xfff8, 0xf0F0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_ICDC} },
1618:
1619: { MC68040|MC68060, {0xfff8, 0xf038|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_NONE} },
1620: { MC68040|MC68060, {0xfff8, 0xf078|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_DC} },
1621: { MC68040|MC68060, {0xfff8, 0xf0B8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_IC} },
1622: { MC68040|MC68060, {0xfff8, 0xf0F8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_ICDC} },
1623:
1624: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f08, 0x0100}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLU.?" },
1625: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0100}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLU.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1626: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f28, 0x0500}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLUN.?" },
1627: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0500}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLUN.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1628:
1629: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f08, 0x0900}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLS.?" },
1630: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0900}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLS.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1631: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f28, 0x0D00}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLSN.?" },
1632: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0D00}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLSN.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1633:
1634: { MC_CPU32, {0xffff, 0xf000|(CPU32_COPROC_ID<<9), 0xffff, 0x01C0}, {2}, {ofI}, "LPSTOP" },
1635:
1636:
1637: #define FPU_COPROC_ID 1 // 1 is the standard FPU, required to be 1 for the 68040 anyway
1638:
1639: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0000}, {-1,16+10,3,1}, {ofFPU}, "FMOVE.?" },
1640: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0001}, {-1,16+10,3,1}, {ofFPU}, "FINT.?" },
1641: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0002}, {-1,16+10,3,1}, {ofFPU}, "FSINH.?" },
1642: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0003}, {-1,16+10,3,1}, {ofFPU}, "FINTRZ.?" },
1643: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0004}, {-1,16+10,3,1}, {ofFPU}, "FSQRT.?" },
1644: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0006}, {-1,16+10,3,1}, {ofFPU}, "FLOGNP1.?" },
1645: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0008}, {-1,16+10,3,1}, {ofFPU}, "FETOXM1.?" },
1646: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0009}, {-1,16+10,3,1}, {ofFPU}, "FTANH.?" },
1647: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000A}, {-1,16+10,3,1}, {ofFPU}, "FATAN.?" },
1648: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000C}, {-1,16+10,3,1}, {ofFPU}, "FASIN.?" },
1649: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000D}, {-1,16+10,3,1}, {ofFPU}, "FATANH.?" },
1650: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000E}, {-1,16+10,3,1}, {ofFPU}, "FSIN.?" },
1651: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000F}, {-1,16+10,3,1}, {ofFPU}, "FTAN.?" },
1652: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0010}, {-1,16+10,3,1}, {ofFPU}, "FETOX.?" },
1653: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0011}, {-1,16+10,3,1}, {ofFPU}, "FTWOTOX.?" },
1654: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0012}, {-1,16+10,3,1}, {ofFPU}, "FTENTOX.?" },
1655: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0014}, {-1,16+10,3,1}, {ofFPU}, "FLOGN.?" },
1656: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0015}, {-1,16+10,3,1}, {ofFPU}, "FLOG10.?" },
1657: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0016}, {-1,16+10,3,1}, {ofFPU}, "FLOG2.?" },
1658: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0018}, {-1,16+10,3,1}, {ofFPU}, "FABS.?" },
1659: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0019}, {-1,16+10,3,1}, {ofFPU}, "FCOSH.?" },
1660: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001A}, {-1,16+10,3,1}, {ofFPU}, "FNEG.?" },
1661: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001C}, {-1,16+10,3,1}, {ofFPU}, "FACOS.?" },
1662: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001D}, {-1,16+10,3,1}, {ofFPU}, "FCOS.?" },
1663: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001E}, {-1,16+10,3,1}, {ofFPU}, "FGETEXP.?" },
1664: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001F}, {-1,16+10,3,1}, {ofFPU}, "FGETMAN.?" },
1665: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0020}, {-1,16+10,3,1}, {ofFPU}, "FDIV.?" },
1666: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0021}, {-1,16+10,3,1}, {ofFPU}, "FMOD.?" },
1667: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0022}, {-1,16+10,3,1}, {ofFPU}, "FADD.?" },
1668: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0023}, {-1,16+10,3,1}, {ofFPU}, "FMUL.?" },
1669: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0024}, {-1,16+10,3,1}, {ofFPU}, "FSGLDIV.?" },
1670: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0025}, {-1,16+10,3,1}, {ofFPU}, "FREM.?" },
1671: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0026}, {-1,16+10,3,1}, {ofFPU}, "FSCALE.?" },
1672: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0027}, {-1,16+10,3,1}, {ofFPU}, "FSGLMUL.?" },
1673: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0028}, {-1,16+10,3,1}, {ofFPU}, "FSUB.?" },
1674: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA078,0x0030}, {-1,16+10,3,1}, {ofFPU3Reg}, "FSINCOS.?" },
1675: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0038}, {-1,16+10,3,1}, {ofFPU}, "FCMP.?" },
1676: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x003A}, {-1,16+10,3,1}, {ofFPU}, "FTST.?" },
1677: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0040}, {-1,16+10,3,1}, {ofFPU}, "FSMOVE.?" },
1678: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0041}, {-1,16+10,3,1}, {ofFPU}, "FSSQRT.?" },
1679: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0042}, {-1,16+10,3,1}, {ofFPU}, "FSADD.?" },
1680: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0044}, {-1,16+10,3,1}, {ofFPU}, "FDMOVE.?" },
1681: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0045}, {-1,16+10,3,1}, {ofFPU}, "FDSQRT.?" },
1682: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0046}, {-1,16+10,3,1}, {ofFPU}, "FDADD.?" },
1683: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0058}, {-1,16+10,3,1}, {ofFPU}, "FSABS.?" },
1684: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005A}, {-1,16+10,3,1}, {ofFPU}, "FSNEG.?" },
1685: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005C}, {-1,16+10,3,1}, {ofFPU}, "FDABS.?" },
1686: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005E}, {-1,16+10,3,1}, {ofFPU}, "FDNEG.?" },
1687: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0060}, {-1,16+10,3,1}, {ofFPU}, "FSDIV.?" },
1688: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0063}, {-1,16+10,3,1}, {ofFPU}, "FSMUL.?" },
1689: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0064}, {-1,16+10,3,1}, {ofFPU}, "FDDIV.?" },
1690: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0067}, {-1,16+10,3,1}, {ofFPU}, "FDMUL.?" },
1691: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0068}, {-1,16+10,3,1}, {ofFPU}, "FSSUB.?" },
1692: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x006C}, {-1,16+10,3,1}, {ofFPU}, "FDSUB.?" },
1693: { MC68040|MC_FPU, {0xffff, 0xf000|(FPU_COPROC_ID<<9),0xFC00,0x5C00}, {0}, {ofFMOVECR}, "FMOVECR" },
1694:
1695: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE000,0x6000}, {-1,16+10,3,1}, {ofFPUMOVE}, "FMOVE.?" },
1696:
1697: // these 3 are special versions of MOVEM with just one register, they have to be before the FMOVEM version
1698: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x8400}, {0}, {ofEa,ofSpecReg}, "FMOVE", {0,REG_FPU_FPIAR} },
1699: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x8800}, {0}, {ofEa,ofSpecReg}, "FMOVE", {EA_An,REG_FPU_FPSR} },
1700: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x9000}, {0}, {ofEa,ofSpecReg}, "FMOVE", {EA_An,REG_FPU_FPCR} },
1701: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE3FF,0x8000}, {0}, {ofEa,ofFPUSRRegList}, "FMOVEM", {EA_Dn|EA_An,0} },
1702: // these 3 are special versions of MOVEM with just one register, they have to be before the FMOVEM version
1703: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xA400}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPIAR,EA_Immed|EA_PCRel} },
1704: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xA800}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPSR,EA_An|EA_Immed|EA_PCRel} },
1705: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xB000}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPCR,EA_An|EA_Immed|EA_PCRel} },
1706: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE3FF,0xA000}, {0}, {ofFPUSRRegList,ofEa}, "FMOVEM", {0,EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1707:
1708: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE00,0xC000}, {0}, {ofFPUReglist,ofEa}, "FMOVEM.X",{0,EA_Dn|EA_An|EA_Anip|EA_Immed} },
1709: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE8F,0xC800}, {0}, {ofExtRegD04,ofEa}, "FMOVEM.X",{0,EA_Dn|EA_An|EA_piAn|EA_Immed} },
1710: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE00,0xE000}, {0}, {ofEa,ofFPUReglist}, "FMOVEM.X",{EA_Dn|EA_An|EA_piAn|EA_Immed,0} },
1711: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE8F,0xE800}, {0}, {ofEa,ofExtRegD04}, "FMOVEM.X",{EA_Dn|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1712:
1713: { MC68040|MC_FPU, {0xffc0, 0xf040|(FPU_COPROC_ID<<9),0xFFC0,0x0000}, {0}, {ofEa}, "FScf.B",{EA_An|EA_Immed|EA_PCRel} },
1714: { MC68040|MC_FPU, {0xfff8, 0xf048|(FPU_COPROC_ID<<9),0xFFC0,0x0000}, {2}, {ofDn,ofDisp}, "FDBcf" },
1715: { MC68040|MC_FPU, {0xffff, 0xf07A|(FPU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {2}, {ofExtIm32}, "FTRAPcf.W" },
1716: { MC68040|MC_FPU, {0xffff, 0xf07B|(FPU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {4}, {ofExtIm32}, "FTRAPcf.L" },
1717: { MC68040|MC_FPU, {0xffff, 0xf07C|(FPU_COPROC_ID<<9), 0xfff0, 0x0000}, {0}, {ofNone}, "FTRAPcf" },
1718:
1719: // FNOP _has_ to be before FBcf.W, not worth to have a special case for that one
1720: { MC68040|MC_FPU, {0xffff, 0xf080|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {0}, {ofNone}, "FNOP" },
1721: { MC68040|MC_FPU, {0xffc0, 0xf080|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {2}, {ofDisp}, "FBcF.W" },
1722: { MC68040|MC_FPU, {0xffc0, 0xf0c0|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {4}, {ofDisp}, "FBcF.L" },
1723: { MC68040|MC68060|MC_FPU, {0xffc0, 0xf100|(FPU_COPROC_ID<<9)}, {0}, {ofEa}, "FSAVE", {EA_Dn|EA_An|EA_piAn|EA_Immed} },
1724: { MC68040|MC68060|MC_FPU, {0xffc0, 0xf140|(FPU_COPROC_ID<<9)}, {0}, {ofEa}, "FRESTORE", {EA_Dn|EA_An|EA_piAn|EA_Immed} },
1725:
1.1.1.4 root 1726: { 0 }
1.1 root 1727: };
1728:
1729: static int Disass68k(long addr, char *labelBuffer, char *opcodeBuffer, char *operandBuffer, char *commentBuffer)
1730: {
1731: long baseAddr = addr;
1.1.1.4 root 1732: int i;
1733: int count = 0;
1734: char addressLabel[256];
1735: char cmtBuffer[256];
1736: Disass68kDataType type;
1737: int index;
1738: long opcodeAddr;
1739:
1.1 root 1740: labelBuffer[0] = 0;
1741: opcodeBuffer[0] = 0;
1742: operandBuffer[0] = 0;
1743: commentBuffer[0] = 0;
1744:
1.1.1.4 root 1745: type = Disass68kType(baseAddr, addressLabel, cmtBuffer, &count);
1.1 root 1746: if(addressLabel[0])
1747: sprintf(labelBuffer, "%s:", addressLabel);
1748: sprintf(commentBuffer, "%s", cmtBuffer);
1749: switch(type)
1750: {
1.1.1.4 root 1751: case dtByte:
1752: if(count > 8)
1753: count = 8;
1754: strcpy(opcodeBuffer,"DC.B");
1755: for (i = 0; i < count; ++i)
1756: {
1757: char hbuf[16];
1758: unsigned short val;
1759:
1760: if((i & 7) > 0)
1761: strcat(operandBuffer, ",");
1762: val = Disass68kGetWord(addr+(i & ~1));
1763: if(i & 1)
1764: val &= 0xFF;
1765: else
1766: val = val >> 8;
1767: sprintf(hbuf,"$%2.2x", val);
1768: strcat(operandBuffer, hbuf);
1769: }
1770: return count;
1771:
1772: case dtWord:
1773: if(count > 4)
1774: count = 4;
1775: strcpy(opcodeBuffer,"DC.W");
1776: for (i = 0; i < count; ++i)
1777: {
1778: char hbuf[16];
1779: if((i & 3) > 0)
1780: strcat(operandBuffer, ",");
1781: sprintf(hbuf,"$%4.4x", Disass68kGetWord(addr+i*2));
1782: strcat(operandBuffer, hbuf);
1783: }
1784: return count * 2;
1785:
1786: case dtLong:
1787: if(count > 2)
1788: count = 2;
1789: strcpy(opcodeBuffer,"DC.L");
1790: for (i = 0; i < count; ++i)
1791: {
1792: char hbuf[16];
1793: if((i & 1) > 0)
1794: strcat(operandBuffer, ",");
1795: sprintf(hbuf,"$%8.8x", (Disass68kGetWord(addr+i*4) << 16) | Disass68kGetWord(addr+i*4+2));
1796: strcat(operandBuffer, hbuf);
1797: }
1798: return count * 4;
1.1 root 1799:
1800: case dtStringArray:
1.1.1.4 root 1801: {
1802: char *sp;
1803: strcpy(opcodeBuffer,"DC.B");
1804: strcat(operandBuffer, "'");
1805: sp = operandBuffer + strlen(operandBuffer);
1806: for (i = 0; i < count; ++i)
1807: {
1808: unsigned short val = Disass68kGetWord(addr+(i & ~1));
1809: if(i & 1)
1810: val &= 0xFF;
1811: else
1812: val = val >> 8;
1813: if(val == 0)
1814: break;
1815: switch(val)
1816: {
1817: case 9: *sp++ = '\\'; *sp++ = 't'; break;
1818: case 10: *sp++ = '\\'; *sp++ = 'n'; break;
1819: case 13: *sp++ = '\\'; *sp++ = 'r'; break;
1820: default:
1821: if(val >= 0x20 && val <= 0x7E)
1822: *sp++ = val;
1823: }
1824: }
1825: *sp = 0;
1826: strcat(sp, "'");
1827: return count;
1828: }
1.1 root 1829:
1830: case dtASCString:
1.1.1.4 root 1831: {
1.1.1.7 ! root 1832: unsigned short opcval = Disass68kGetWord(addr+0);
! 1833: count = 1;
1.1.1.4 root 1834: strcpy(opcodeBuffer,"DC.B");
1.1.1.7 ! root 1835: if ((opcval >> 8) == 0)
1.1.1.4 root 1836: {
1837: strcat(operandBuffer, "0");
1838: } else {
1839: char *sp;
1840: strcat(operandBuffer, "'");
1841: sp = operandBuffer + strlen(operandBuffer);
1842: for(i=0; ; ++i)
1843: {
1844: unsigned short val = Disass68kGetWord(addr+(i & ~1));
1845: if(i & 1)
1846: val &= 0xFF;
1847: else
1848: val = val >> 8;
1849: if(val == 0)
1850: break;
1851: switch(val)
1.1 root 1852: {
1.1.1.4 root 1853: case 9: *sp++ = '\\'; *sp++ = 't'; break;
1854: case 10: *sp++ = '\\'; *sp++ = 'n'; break;
1855: case 13: *sp++ = '\\'; *sp++ = 'r'; break;
1856: default:
1857: if(val >= 0x20 && val <= 0x7E)
1858: *sp++ = val;
1.1 root 1859: }
1.1.1.4 root 1860: ++count;
1861: }
1862: *sp = 0;
1863: strcat(sp, "',0");
1864: }
1865: return (count + 1) & ~1;
1866: }
1.1 root 1867:
1868: case dtPointer:
1869: case dtFunctionPointer:
1.1.1.4 root 1870: {
1871: const char *sp;
1.1.1.7 ! root 1872: int val;
1.1.1.4 root 1873: val = (Disass68kGetWord(addr) << 16) | Disass68kGetWord(addr+2);
1874: sp = Disass68kSymbolName(val, 2);
1875: strcpy(opcodeBuffer,"DC.L");
1876: if(sp)
1877: sprintf(operandBuffer,"%s", sp);
1878: else
1.1.1.6 root 1879: sprintf(operandBuffer,"$%8.8x", val);
1.1.1.4 root 1880: return 4;
1881: }
1.1 root 1882:
1883: default: break;
1884: }
1885:
1.1.1.4 root 1886: index = 0;
1887: opcodeAddr = addr;
1.1 root 1888: more:
1889: addr = opcodeAddr;
1890:
1891: opcodeBuffer[0] = 0;
1892: operandBuffer[0] = 0;
1893:
1894: commentBuffer[0] = 0;
1895: if(cmtBuffer[0])
1896: sprintf(commentBuffer, "%s ", cmtBuffer);
1897:
1898: while(1)
1899: {
1.1.1.4 root 1900: unsigned short opcode[5];
1.1 root 1901: OpcodeTableStruct *ots = &OpcodeTable[index++];
1.1.1.4 root 1902: int size;
1903: char sizeChar = 0;
1904: char *dbuf;
1905: int ea;
1.1.1.7 ! root 1906: int maxop;
1.1.1.4 root 1907:
1.1 root 1908: if(ots->opcodeName == NULL)
1909: break;
1910: if((ots->cpuMask & optionCPUTypeMask) == 0) // CPU doesn't match?
1911: continue;
1912:
1913: // search for the opcode plus up to 2 extension words
1914: for(i=0; i<5; ++i)
1915: {
1916: if(!ots->opcodeMask[i*2])
1.1.1.4 root 1917: {
1918: opcode[i] = 0;
1.1 root 1919: break;
1.1.1.4 root 1920: }
1.1 root 1921: opcode[i] = Disass68kGetWord(addr);
1922: if(((ots->opcodeMask[i*2] & 0xFFFF) & opcode[i]) != ots->opcodeMask[i*2+1])
1923: goto more;
1924: addr += 2;
1925: }
1926:
1927: // find out the size of the opcode operand
1.1.1.4 root 1928: size = ots->operationSize[0];
1.1 root 1929: if(size < 0) // custom size?
1930: {
1931: int opcodeOffset = ots->operationSize[1] >> 4;
1932: int bitShiftOffset = ots->operationSize[1] & 0x0F;
1933: int sizeBitMask = (opcode[opcodeOffset] >> bitShiftOffset) & ((1 << ots->operationSize[2]) - 1);
1934: switch(ots->operationSize[3])
1935: {
1936: case 0: // 2 Bit Size
1937: switch(sizeBitMask)
1938: {
1939: case 0: size = 1; sizeChar = 'B'; break;
1940: case 1: size = 2; sizeChar = 'W'; break;
1941: case 2: size = 4; sizeChar = 'L'; break;
1942: case 3: goto more; // illegal size mask
1943: }
1944: break;
1945: case 1: // 3 Bit FPU Size
1946: if((opcode[1] & 0x4000) == 0x0000) // Register => Register?
1947: sizeBitMask = 2; // => 'X' Format
1948: switch(sizeBitMask)
1949: {
1950: case 0: size = 4; sizeChar = 'L'; break;
1951: case 1: size = 4; sizeChar = 'S'; break;
1952: case 2: size = 12; sizeChar = 'X'; break;
1953: case 7: if((opcode[1] & 0xE000) != 0x6000) // MOVE.P <ea>,FPn{Dn-Factor}
1954: goto more; // illegal size mask
1955: case 3: size = 12; sizeChar = 'P'; break;
1956: case 4: size = 2; sizeChar = 'W'; break;
1957: case 5: size = 8; sizeChar = 'D'; break;
1958: case 6: size = 1; sizeChar = 'B'; break;
1959: }
1960: break;
1961: }
1962: }
1963:
1964: // copy the opcode plus a necessary TAB for the operand
1.1.1.4 root 1965: dbuf = opcodeBuffer;
1.1 root 1966: for(i=0; ots->opcodeName[i]; ++i)
1967: {
1968: char c = ots->opcodeName[i];
1969: if(c == 'c') // condition code
1970: {
1971: static const char *pmmuCond[16] = { "BS", "BC", "LS", "LC", "SS", "SC", "AS", "AC", "WS", "WC", "IS", "IC", "GS", "GC", "CS", "CC" };
1972: static const char *braCond[16] = { "RA", "SR", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1973: static const char *sccCond[16] = { "T", "F", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1974: static const char *dbCond[16] = { "T", "RA", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
1975: static const char *fpuCond[64] = { "F", "EQ", "OGT", "OGE", "OLT", "OLE", "OGL", "OR", "UN", "UEQ", "UGT", "UGE", "ULT", "ULE", "NE", "T", "SF", "SEQ", "GT", "GE", "LT", "LE", "GL", "GLE", "NGLE", "NGL", "NLE", "NLT", "NGE", "NGT", "SNE", "ST" };
1.1.1.4 root 1976: char buf[8];
1.1 root 1977:
1978: const char *sp = NULL;
1979: switch(ots->opcodeName[++i])
1980: {
1981: case 'p': // PMMU conditions
1982: sp = pmmuCond[opcode[1] & 0xF];
1983: break;
1984: case 'b': // BRA conditions
1985: sp = braCond[(opcode[0] >> 8) & 0xF];
1986: break;
1987: case 'i': // Scc,TRAPcc conditions
1988: sp = sccCond[(opcode[0] >> 8) & 0xF];
1989: break;
1990: case 'd': // DBcc conditions
1991: sp = dbCond[(opcode[0] >> 8) & 0xF];
1992: break;
1993: case 'F': // FPU conditions (first word)
1994: sp = fpuCond[opcode[0] & 0x3F];
1995: break;
1996: case 'f': // FPU conditions (second word)
1997: sp = fpuCond[opcode[1] & 0x3F];
1998: break;
1999: }
2000: if(sp)
2001: {
2002: if(options & doptOpcodesSmall)
2003: {
1.1.1.4 root 2004: char *bp;
1.1 root 2005: strcpy(buf, sp);
2006: sp = buf;
1.1.1.4 root 2007: for (bp = buf; *bp; ++bp)
1.1.1.5 root 2008: *bp = tolower((unsigned char)*bp);
1.1 root 2009: }
2010: strcpy(dbuf, sp);
2011: dbuf += strlen(sp);
2012: continue;
2013: }
2014: goto more;
2015: }
2016: if(c == '?') // size mask
2017: c = sizeChar;
2018: if(options & doptOpcodesSmall)
1.1.1.5 root 2019: c = tolower((unsigned char)c);
1.1 root 2020: *dbuf++ = c;
2021: }
2022: *dbuf = 0;
2023:
2024: // Parse the EAs for all operands
1.1.1.4 root 2025: ea = opcode[0] & 0x3F;
1.1 root 2026: dbuf = operandBuffer;
1.1.1.5 root 2027:
1.1.1.7 ! root 2028: maxop = (int)(sizeof(ots->op)/sizeof(ots->op[0]));
1.1.1.5 root 2029: for(i=0; i<maxop; ++i)
1.1 root 2030: {
1.1.1.7 ! root 2031: int reg, val;
1.1.1.4 root 2032:
1.1 root 2033: switch(ots->op[i])
2034: {
2035: case ofNone: // nothing
2036: break;
2037:
2038: case ofEa:
2039: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, EA_All & ~(ots->parameter[i]), 0, ots->disassFlag);
2040: break;
2041:
2042: case ofDn:
2043: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2044: break;
2045: case ofAn:
2046: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x08, size, EA_An, 0, ots->disassFlag);
2047: break;
2048: case ofAni:
2049: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x10, size, EA_Ani, 0, ots->disassFlag);
2050: break;
2051: case ofAnip:
2052: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2053: break;
2054: case ofPiAn:
2055: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x20, size, EA_piAn, 0, ots->disassFlag);
2056: break;
2057: case ofD16An:
2058: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x28, size, EA_dAn, 0, ots->disassFlag);
2059: break;
2060:
2061: case ofI:
2062: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x3C, size, EA_Immed, 0, ots->disassFlag);
2063: break;
2064:
2065: case ofDestDn:
2066: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2067: break;
2068: case ofDestAn:
2069: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x08, size, EA_An, 0, ots->disassFlag);
2070: break;
2071: case ofDestAnip:
2072: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2073: break;
2074: case ofDestPiAn:
2075: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x20, size, EA_piAn, 0, ots->disassFlag);
2076: break;
2077: case ofDestEa6:
2078: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | (((opcode[0] >> 6) & 0x7) << 3), size, EA_Dest-EA_An, 0, ots->disassFlag);
2079: break;
2080: case ofDestAbsL:
2081: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x39, size, EA_Abs, 0, ots->disassFlag);
2082: break;
2083:
2084: case ofIOpcode:
2085: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, opcode[0] & ots->parameter[i], ots->disassFlag);
2086: break;
2087: case ofI3:
2088: val = ((opcode[0] >> 9) & 7);
2089: if(!val) val = 8;
2090: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, val, ots->disassFlag);
2091: break;
2092: case ofExtIm:
2093: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, opcode[1], ots->disassFlag);
2094: break;
2095: case ofExtIm32:
2096: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, size, EA_ImmedParameter, opcode[2], ots->disassFlag);
2097: break;
2098: case ofExtIm4:
2099: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, opcode[1] & 0x0F, ots->disassFlag);
2100: break;
2101: case ofExtIm10:
2102: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, (opcode[1] >> 10) & 0x07, ots->disassFlag);
2103: break;
2104: case ofSpecReg:
2105: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0101, size, EA_SpecialRegister, ots->parameter[i], ots->disassFlag);
2106: break;
2107: case ofSpecExtReg:
2108: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0101, size, EA_SpecialRegister, opcode[1] & 0xFFF, ots->disassFlag);
2109: break;
2110: case ofExtReg0:
2111: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2112: break;
2113: case ofExtRegA0:
2114: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07) | 0x08, size, EA_An, 0, ots->disassFlag);
2115: break;
2116: case ofExtRegD04:
2117: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 4) & 0x07) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2118: break;
2119: case ofExtRegA05:
2120: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 5) & 0x07) | 0x08, size, EA_An, 0, ots->disassFlag);
2121: break;
2122: case ofExtReg:
2123: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2124: break;
2125: case ofExtAnip:
2126: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2127: break;
2128:
2129: case ofDisp:
2130: // branch treats the displacement 0x00 and 0xFF as an indicator how many words follow
2131: // This test will decline a displacement with the wrong word offset
2132: if((opcode[0] & 0xF000) == 0x6000)
2133: {
2134: val = opcode[0] & 0xFF;
2135: if(val == 0x00 && size != 2) goto more;
2136: if(val == 0xFF && size != 4) goto more;
2137: }
2138: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0102, size, EA_PCDisplacement, opcode[0] & 0xFF, ots->disassFlag);
2139: break;
2140:
2141: case ofRegList:
2142: val = opcode[1];
2143: if((ea & 0x38) == 0x20) // -(An) has a flipped bitmask
2144: val = Disass68kFlipBits(val);
2145: dbuf = Disass68kReglist(dbuf, val);
2146: break;
2147:
2148: case ofFPU:
2149: { // default FPU opcode modes
2150: int src = (opcode[1] >> 10) & 7;
2151: int dest = (opcode[1] >> 7) & 7;
2152: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2153: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2154: if(opcode[1] & 0x4000)
2155: {
2156: // <ea>,FPn
2157: int mask = EA_All - EA_An;
2158: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2159: mask -= EA_Dn;
2160: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2161: if(!dbuf) goto more;
2162: *dbuf++ = ',';
2163: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2164: *dbuf = 0;
2165: } else {
2166: // FPn,FPn or FPn
2167:
2168: // <ea> has to be 0
2169: if((opcode[0] & 0x3F) != 0) goto more;
2170:
2171: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+src;
2172: if(src != dest)
2173: {
2174: *dbuf++ = ',';
2175: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2176: }
2177: *dbuf = 0;
2178: }
2179: }
2180: break;
2181: case ofFPUMOVE:
2182: { // MOVE <ea>,FPn{k-Factor}
2183: int src = (opcode[1] >> 10) & 7;
2184: // <ea>,FPn
2185: int mask = EA_All - EA_An;
2186: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2187: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2188: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2189: mask -= EA_Dn;
2190: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2191: if(!dbuf) goto more;
2192: *dbuf++ = ',';
2193: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+((opcode[1] >> 7) & 7);
2194: if(src == 3)
2195: {
2196: int kFactor = opcode[1] & 0x7F;
2197: if(kFactor & 0x40)
2198: kFactor |= 0x80;
2199: *dbuf++ = '{';
2200: sprintf(dbuf, "%d", (signed char)kFactor);
2201: dbuf += strlen(dbuf);
2202: *dbuf++ = '}';
2203: } else if(src == 7)
2204: {
2205: if((opcode[1] & 0x0F) != 0) goto more;
2206: *dbuf++ = '{';
2207: *dbuf++ = options & doptRegisterSmall ? 'd' : 'D';
2208: *dbuf++ = '0' + ((opcode[1] >> 4) & 7);
2209: *dbuf++ = '}';
2210: } else {
2211: if((opcode[1] & 0x7F) != 0) goto more;
2212: }
2213: *dbuf = 0;
2214: }
2215: break;
2216: case ofFMOVECR:
2217: { // MOVECR #const,FPn
2218: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2219: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2220: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, opcode[1] & 0x7F, ots->disassFlag);
2221: if(!dbuf) goto more;
1.1.1.4 root 2222: reg = (opcode[1] >> 7) & 7;
1.1 root 2223: *dbuf++ = ',';
2224: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+reg;
2225: *dbuf = 0;
2226: switch(opcode[1] & 0x7F) // document the well-known constants
2227: {
2228: case 0x00: strcat(commentBuffer, "PI"); break;
2229: case 0x0B: strcat(commentBuffer, "Log10(2)"); break;
2230: case 0x0C: strcat(commentBuffer, "e"); break;
2231: case 0x0D: strcat(commentBuffer, "Log2(e)"); break;
2232: case 0x0E: strcat(commentBuffer, "Log10(e)"); break;
2233: case 0x0F: strcat(commentBuffer, "0.0"); break;
2234: case 0x30: strcat(commentBuffer, "1n(2)"); break;
2235: case 0x31: strcat(commentBuffer, "1n(10)"); break;
2236: case 0x32: strcat(commentBuffer, "100"); break;
2237: case 0x33: strcat(commentBuffer, "10^1"); break;
2238: case 0x34: strcat(commentBuffer, "10^2"); break;
2239: case 0x35: strcat(commentBuffer, "10^4"); break;
2240: case 0x36: strcat(commentBuffer, "10^8"); break;
2241: case 0x37: strcat(commentBuffer, "10^16"); break;
2242: case 0x38: strcat(commentBuffer, "10^32"); break;
2243: case 0x39: strcat(commentBuffer, "10^64"); break;
2244: case 0x3A: strcat(commentBuffer, "10^128"); break;
2245: case 0x3B: strcat(commentBuffer, "10^256"); break;
2246: case 0x3C: strcat(commentBuffer, "10^512"); break;
2247: case 0x3D: strcat(commentBuffer, "10^1024"); break;
2248: case 0x3E: strcat(commentBuffer, "10^2048"); break;
2249: case 0x3F: strcat(commentBuffer, "10^4096"); break;
2250: }
2251: }
2252: break;
2253: case ofFPUSRRegList:
2254: {
2255: int hasReg = 0;
2256: *dbuf = 0;
2257: if(opcode[1] & 0x0400)
2258: {
2259: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPIAR));
2260: hasReg = 1;
2261: }
2262: if(opcode[1] & 0x0800)
2263: {
2264: if(hasReg) strcat(dbuf, "/");
2265: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPSR));
2266: hasReg = 1;
2267: }
2268: if(opcode[1] & 0x1000)
2269: {
2270: if(hasReg) strcat(dbuf, "/");
2271: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPCR));
2272: hasReg = 1;
2273: }
2274: if(!hasReg)
2275: strcat(dbuf, "0");
2276: dbuf += strlen(dbuf);
2277: }
2278: break;
2279: case ofFPUReglist: // FMOVEM
2280: {
2281: int mask = opcode[1] & 0xFF;
2282: if(opcode[1] & 0x0100)
2283: mask = Disass68kFlipBits(mask) >> 8;
2284: dbuf = Disass68kFPUReglist(dbuf, mask);
2285: }
2286: break;
2287: case ofFPU3Reg:
2288: { // FSINCOS
2289: int src = (opcode[1] >> 10) & 7;
2290: int dest = (opcode[1] >> 7) & 7;
2291: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2292: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2293: if(opcode[1] & 0x4000)
2294: {
2295: // <ea>,FPn
2296: int mask = EA_All - EA_An;
2297: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2298: mask -= EA_Dn;
2299: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2300: if(!dbuf) goto more;
2301: *dbuf++ = ',';
2302: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+(opcode[1] & 7);
2303: *dbuf++ = ',';
2304: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2305: *dbuf = 0;
2306: } else {
2307: // FPn,FPn or FPn
2308:
2309: // <ea> has to be 0
2310: if((opcode[0] & 0x3F) != 0) goto more;
2311:
2312: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+src;
2313: *dbuf++ = ',';
2314: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+(opcode[1] & 7);
2315: *dbuf++ = ',';
2316: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2317: *dbuf = 0;
2318: }
2319: }
2320: break;
2321:
2322: case ofCAS:
2323: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2324: if(!dbuf) goto more;
2325: *dbuf++ = ',';
2326: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2327: break;
2328: case ofCAS2:
2329: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2330: if(!dbuf) goto more;
2331: *dbuf++ = ':';
2332: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[2] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2333: if(!dbuf) goto more;
2334: *dbuf++ = ',';
2335: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2336: if(!dbuf) goto more;
2337: *dbuf++ = ':';
2338: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[2] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2339: if(!dbuf) goto more;
2340: *dbuf++ = ',';
2341: *dbuf++ = '(';
2342: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2343: if(!dbuf) goto more;
2344: *dbuf++ = ')';
2345: *dbuf++ = ':';
2346: *dbuf++ = '(';
2347: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[2] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2348: if(!dbuf) goto more;
2349: *dbuf++ = ')';
2350: *dbuf = 0;
2351: break;
2352: case ofExt4Dn:
2353: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[0] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2354: if(!dbuf) goto more;
2355: *dbuf++ = ':';
2356: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2357: if(!dbuf) goto more;
2358: *dbuf++ = ',';
2359: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2360: if(!dbuf) goto more;
2361: *dbuf = 0;
2362: break;
2363: case ofBFEa:
2364: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, EA_All & ~(ots->parameter[i]), 0, ots->disassFlag);
2365: if(!dbuf) goto more;
2366: *dbuf++ = '{';
2367: val = (opcode[1] >> 6) & 0x1F;
2368: if(opcode[1] & 0x0800)
2369: {
2370: if(val & 0x18) goto more;
2371: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, val & 0x07, 1, EA_Dn, val, ots->disassFlag);
2372: } else {
2373: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0103, 1, EA_ValueParameter, val, ots->disassFlag);
2374: }
2375: *dbuf++ = ':';
2376: val = opcode[1] & 0x1F;
2377: if(opcode[1] & 0x0020)
2378: {
2379: if(val & 0x18) goto more;
2380: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, val & 0x07, 1, EA_Dn, val, ots->disassFlag);
2381: } else {
2382: if(val == 0) val = 32;
2383: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0103, 1, EA_ValueParameter, val, ots->disassFlag);
2384: }
2385: *dbuf++ = '}';
2386: *dbuf = 0;
2387: break;
2388: case ofLineA:
2389: {
2390: int lineAVal = opcode[0] & 0xFFF;
2391: const char *lineAStr[16] = { "Line-A Initialization",
2392: "Put pixel",
2393: "Get pixel",
2394: "Arbitrary line",
2395: "Horizontal line",
2396: "Filled rectangle",
2397: "Filled polygon",
2398: "Bit block transfer",
2399: "Text block transfer",
2400: "Show mouse",
2401: "Hide mouse",
2402: "Transform mouse",
2403: "Undraw sprite",
2404: "Draw sprite",
2405: "Copy raster form",
2406: "Seedfill"
2407: };
1.1.1.4 root 2408: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, lineAVal, ots->disassFlag);
1.1 root 2409: if(lineAVal < 16)
2410: strcat(commentBuffer, lineAStr[lineAVal]);
2411: }
2412: break;
2413:
2414: default:
2415: goto more;
2416: }
2417: if(!dbuf) goto more;
2418:
2419: // does another operand follow => add separator
1.1.1.5 root 2420: if ( (i+1<maxop) && ( ots->op[i+1] != ofNone) )
1.1 root 2421: *dbuf++ = ',';
2422: }
2423: return addr-baseAddr;
2424: }
2425:
2426: // unknown opcode
2427: strcpy(opcodeBuffer, "DC.W");
2428: sprintf(operandBuffer,"$%4.4x", Disass68kGetWord(addr));
2429: return 2;
2430: }
2431:
2432: static void Disass68kComposeStr(char *dbuf, const char *str, int position, int maxPos)
2433: {
2434: int i;
2435: int len = strlen(dbuf);
2436: while(len < position) {
2437: dbuf[len++] = ' '; /* Will give harmless warning from GCC */
2438: }
2439: for(i=0; str[i] && (!maxPos || len+i<maxPos); ++i)
2440: dbuf[len+i] = str[i];
2441: if(str[i])
2442: dbuf[len+i-1] = '+';
2443: dbuf[len+i] = 0;
2444: }
2445:
2446: static void Disass68k_loop (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
2447: {
2448: static bool isInit = false;
2449: if(!isInit)
2450: {
2451: Disass68kInit(Paths_GetHatariHome());
2452: isInit = true;
2453: }
2454:
1.1.1.4 root 2455: while (cnt-- > 0) {
1.1.1.6 root 2456: const int addrWidth = 8; // 6 on an ST (24 bit addressing), 8 on a TT (32 bit addressing)
1.1 root 2457: char lineBuffer[1024];
2458:
2459: char addressBuffer[32];
2460: char hexdumpBuffer[256];
2461: char labelBuffer[256];
2462: char opcodeBuffer[64];
2463: char operandBuffer[256];
2464: char commentBuffer[256];
1.1.1.4 root 2465: int plen, len, j;
2466:
2467: len = Disass68k(addr, labelBuffer, opcodeBuffer, operandBuffer, commentBuffer);
1.1 root 2468: if(!len) break;
2469:
2470: sprintf(addressBuffer, "$%*.*x :", addrWidth,addrWidth, addr);
2471:
2472: hexdumpBuffer[0] = 0;
1.1.1.4 root 2473: plen = len;
1.1 root 2474: if(plen > 80 && (!strncmp(opcodeBuffer, "DC.", 3) || !strncmp(opcodeBuffer, "dc.", 3)))
2475: plen = ((optionPosLabel - optionPosHexdump) / 5) * 2;
1.1.1.4 root 2476:
1.1 root 2477: for(j=0; j<plen; j += 2)
2478: {
2479: if(j > 0)
2480: strcat(hexdumpBuffer, " ");
2481: if(j + 2 > plen)
2482: {
2483: sprintf(hexdumpBuffer+strlen(hexdumpBuffer), "%2.2x", Disass68kGetWord(addr+j) >> 8);
2484: } else {
2485: sprintf(hexdumpBuffer+strlen(hexdumpBuffer), "%4.4x", Disass68kGetWord(addr+j));
2486: }
2487: }
2488:
2489: lineBuffer[0] = 0;
2490: if(optionPosAddress >= 0)
2491: Disass68kComposeStr(lineBuffer, addressBuffer, optionPosAddress, 0);
2492: if(optionPosHexdump >= 0)
2493: Disass68kComposeStr(lineBuffer, hexdumpBuffer, optionPosHexdump, optionPosLabel);
2494: if(optionPosLabel >= 0)
2495: Disass68kComposeStr(lineBuffer, labelBuffer, optionPosLabel, 0);
2496: if(optionPosOpcode >= 0)
2497: Disass68kComposeStr(lineBuffer, opcodeBuffer, optionPosOpcode, 0);
2498: if(optionPosOperand >= 0)
2499: {
2500: size_t l = strlen(lineBuffer);
2501: if(lineBuffer[l-1] != ' ') // force at least one space between opcode and operand
2502: {
2503: lineBuffer[l++] = ' ';
2504: lineBuffer[l] = 0;
2505: }
2506: Disass68kComposeStr(lineBuffer, operandBuffer, optionPosOperand, 0);
2507: }
1.1.1.4 root 2508: if (optionPosComment >= 0)
1.1.1.3 root 2509: {
1.1.1.4 root 2510: float percentage;
1.1.1.6 root 2511: Uint32 count, cycles, i_misses, d_hits;
2512: if (Profile_CpuAddressData(addr, &percentage, &count, &cycles, &i_misses, &d_hits))
1.1.1.3 root 2513: {
1.1.1.6 root 2514: sprintf(commentBuffer, "%5.2f%% (%u, %u, %u, %u)", percentage, count, cycles, i_misses, d_hits);
1.1.1.3 root 2515: Disass68kComposeStr(lineBuffer, commentBuffer, optionPosComment+1, 0);
2516: }
1.1.1.4 root 2517: /* show comments only if profile data is missing */
2518: else if (commentBuffer[0])
2519: {
2520: Disass68kComposeStr(lineBuffer, " ;", optionPosComment, 0);
2521: Disass68kComposeStr(lineBuffer, commentBuffer, optionPosComment+3, 0);
2522: }
1.1.1.3 root 2523: }
1.1.1.4 root 2524: addr += len;
2525: if (f)
2526: fprintf(f, "%s\n", lineBuffer);
1.1 root 2527: // if(strstr(opcodeBuffer, "RTS") || strstr(opcodeBuffer, "RTE") || strstr(opcodeBuffer, "JMP")
2528: // || strstr(opcodeBuffer, "rts") || strstr(opcodeBuffer, "rte") || strstr(opcodeBuffer, "jmp"))
2529: // fprintf(f, "\n");
2530: }
2531: if (nextpc)
2532: *nextpc = addr;
2533: }
2534:
2535:
1.1.1.4 root 2536: /**
2537: * Calculate next PC address from given one, without output
2538: * @return next PC address
1.1 root 2539: */
1.1.1.4 root 2540: Uint32 Disasm_GetNextPC(Uint32 pc)
2541: {
2542: uaecptr nextpc;
2543: Disass68k_loop (NULL, pc, &nextpc, 1);
2544: return nextpc;
2545: }
1.1 root 2546:
1.1.1.4 root 2547: /**
2548: * Call disassembly using the selected disassembly method,
2549: * either internal UAE one, or the stand alone disassembler above,
2550: * whichever is selected in Hatari configuration
2551: */
2552: void Disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1.1 root 2553: {
1.1.1.4 root 2554: if (ConfigureParams.Debugger.bDisasmUAE)
1.1.1.6 root 2555: #ifdef WINUAE_FOR_HATARI
2556: m68k_disasm_file (f, addr, nextpc, cnt);
2557: #else
1.1.1.5 root 2558: m68k_disasm (f, addr, nextpc, cnt);
1.1.1.6 root 2559: #endif
1.1.1.4 root 2560: else
1.1.1.5 root 2561: Disass68k_loop (f, addr, nextpc, cnt);
1.1 root 2562: }
2563:
1.1.1.4 root 2564: static void Disasm_CheckOptionEngine(void)
2565: {
2566: if (ConfigureParams.Debugger.bDisasmUAE)
2567: fputs("WARNING: disassembly options are supported only for '--disasm ext'!\n", stderr);
2568: }
2569:
2570: /**
2571: * query disassembly output column positions.
2572: */
2573: void Disasm_GetColumns(int *pos)
2574: {
2575: pos[DISASM_COLUMN_ADDRESS] = optionPosAddress;
2576: pos[DISASM_COLUMN_HEXDUMP] = optionPosHexdump;
2577: pos[DISASM_COLUMN_LABEL] = optionPosLabel;
2578: pos[DISASM_COLUMN_OPCODE] = optionPosOpcode;
2579: pos[DISASM_COLUMN_OPERAND] = optionPosOperand;
2580: pos[DISASM_COLUMN_COMMENT] = optionPosComment;
2581: }
2582:
2583: /**
2584: * set disassembly output column positions.
2585: */
2586: void Disasm_SetColumns(int *pos)
2587: {
2588: Disasm_CheckOptionEngine();
2589: optionPosAddress = pos[DISASM_COLUMN_ADDRESS];
2590: optionPosHexdump = pos[DISASM_COLUMN_HEXDUMP];
2591: optionPosLabel = pos[DISASM_COLUMN_LABEL];
2592: optionPosOpcode = pos[DISASM_COLUMN_OPCODE];
2593: optionPosOperand = pos[DISASM_COLUMN_OPERAND];
2594: optionPosComment = pos[DISASM_COLUMN_COMMENT];
2595: }
2596:
2597: /**
2598: * function to disable given disassembly output 'column'.
2599: * input is current column positions in 'oldcols' array and
2600: * output is new column positions/values in 'newcols' array.
2601: * It's safe to use same array for both.
2602: */
2603: void Disasm_DisableColumn(int column, int *oldcols, int *newcols)
2604: {
2605: int i, diff = 0;
2606:
2607: assert(column >= 0 && column < DISASM_COLUMNS);
2608: if (column+1 < DISASM_COLUMNS)
2609: diff = oldcols[column+1] - oldcols[column];
2610:
2611: for (i = 0; i < DISASM_COLUMNS; i++)
2612: {
2613: if (i && oldcols[i-1] > oldcols[i])
2614: {
2615: printf("WARNING: disassembly columns aren't in the expected order!\n");
2616: return;
2617: }
2618: if (i < column)
2619: newcols[i] = oldcols[i];
2620: else if (i > column)
2621: newcols[i] = oldcols[i] - diff;
2622: else
2623: newcols[column] = DISASM_COLUMN_DISABLE;
2624: }
2625: }
2626:
2627: /**
2628: * Get current disassembly output option flags
2629: * @return current output flags
2630: */
2631: int Disasm_GetOptions(void)
2632: {
2633: return options;
2634: }
2635:
2636: /**
1.1.1.6 root 2637: * Set CPU and FPU mask used for disassembly (when changed from the UI or the options)
2638: */
2639: void Disasm_SetCPUType ( int CPU , int FPU )
2640: {
2641: optionCPUTypeMask = 0;
2642:
2643: if ( ( FPU == 68881 ) || ( FPU == 68882 ) )
2644: optionCPUTypeMask |= MC_FPU;
2645:
2646: switch ( CPU )
2647: {
2648: case 0 : optionCPUTypeMask |= MC68000 ; break;
2649: case 1 : optionCPUTypeMask |= MC68010 ; break;
2650: case 2 : optionCPUTypeMask |= MC68020 ; break;
2651: case 3 : optionCPUTypeMask |= MC68030 ; break;
2652: case 4 : optionCPUTypeMask |= MC68040 ; break;
2653: default : optionCPUTypeMask |= MC68000 ; break;
2654: }
2655: }
2656:
2657: /**
1.1.1.4 root 2658: * Parse disasm command line option argument
2659: * @return error string (""=silent 'error') or NULL for success.
2660: */
2661: const char *Disasm_ParseOption(const char *arg)
2662: {
2663: if (strcasecmp(arg, "help") == 0)
2664: {
2665: const struct {
2666: int flag;
2667: const char *desc;
2668: } option[] = {
2669: { doptNoBrackets, "no brackets around absolute addressing" },
2670: { doptOpcodesSmall, "opcodes in small letters" },
2671: { doptRegisterSmall, "register names in small letters" },
2672: { doptStackSP, "stack pointer as 'SP', not 'A7'" },
2673: { 0, NULL }
2674: };
2675: int i;
2676: fputs("Disassembly settings:\n"
2677: "\tuae - use CPU core internal disassembler which has better\n"
2678: "\t instruction support\n"
2679: "\text - use external disassembler which has nicer output\n"
2680: "\t and supports options below\n"
2681: "\t<bitmask> - disassembly output option flags\n"
2682: "Flag values:\n", stderr);
2683: for (i = 0; option[i].desc; i++) {
2684: assert(option[i].flag == (1 << i));
2685: fprintf(stderr, "\t%d: %s\n", option[i].flag, option[i].desc);
2686: }
2687: fprintf(stderr, "Current settings are:\n\t--disasm %s --disasm %d\n",
2688: ConfigureParams.Debugger.bDisasmUAE ? "uae" : "ext",
2689: ConfigureParams.Debugger.nDisasmOptions);
2690: return "";
2691: }
2692: if (strcasecmp(arg, "uae") == 0)
2693: {
2694: fputs("Selected UAE CPU core internal disassembler.\n", stderr);
2695: ConfigureParams.Debugger.bDisasmUAE = true;
2696: return NULL;
2697: }
2698: if (strcasecmp(arg, "ext") == 0)
2699: {
2700: fputs("Selected external disassembler.\n", stderr);
2701: fprintf(stderr, "Disassembly output flags are %d.\n", options);
2702: ConfigureParams.Debugger.bDisasmUAE = false;
2703: return NULL;
2704: }
1.1.1.5 root 2705: if (isdigit((unsigned char)*arg))
1.1.1.4 root 2706: {
2707: int newopt = atoi(arg);
2708: if ((newopt|optionsMask) != optionsMask)
2709: {
2710: return "unknown flags in the bitmask";
2711: }
2712: fprintf(stderr, "Changed CPU disassembly output flags from %d to %d.\n", options, newopt);
2713: ConfigureParams.Debugger.nDisasmOptions = options = newopt;
2714: Disasm_CheckOptionEngine();
2715: return NULL;
2716: }
2717: return "invalid disasm option";
2718: }
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