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1.1 root 1: /***
2: * 68k disassembler, written 2010 by Markus Fritze, www.sarnau.com
3: *
1.1.1.4 root 4: * This file is distributed under the GNU General Public License, version 2
5: * or at your option any later version. Read the file gpl.txt for details.
1.1 root 6: ***/
7:
1.1.1.7 root 8: #include "main.h"
1.1 root 9: #include <ctype.h>
1.1.1.7 root 10: #if HAVE_STRINGS_H
11: # include <strings.h>
12: #endif
1.1 root 13:
14: #include "sysdeps.h"
1.1.1.4 root 15: #include "configuration.h"
1.1 root 16: #include "newcpu.h"
1.1.1.7 root 17: #include "stMemory.h"
1.1.1.6 root 18: #ifdef WINUAE_FOR_HATARI
19: #include "debug.h"
20: #endif
1.1 root 21: #include "paths.h"
1.1.1.3 root 22: #include "profile.h"
1.1 root 23: #include "tos.h"
24: #include "68kDisass.h"
25:
26: #define ADDRESS_ON_PC 1
27: #define USE_SYMBOLS 1
28:
29: typedef enum {
30: doptNoBrackets = 1, // hide brackets around absolute addressing
31: doptOpcodesSmall = 2, // opcodes are small letters
32: doptRegisterSmall = 4, // register names are small letters
1.1.1.5 root 33: doptStackSP = 8 // stack pointer is named "SP" instead of "A7" (except for MOVEM)
1.1 root 34: } Diss68kOptions;
35:
36: static Diss68kOptions options = doptOpcodesSmall | doptRegisterSmall | doptStackSP | doptNoBrackets;
37:
1.1.1.4 root 38: /* all options */
39: static const Diss68kOptions optionsMask = doptOpcodesSmall | doptRegisterSmall | doptStackSP | doptNoBrackets;
40:
1.1 root 41: // values <0 will hide the group
1.1.1.4 root 42: static int optionPosAddress = 0; // current address
1.1.1.6 root 43: static int optionPosHexdump = 12; // 16-bit words at this address
1.1.1.4 root 44: static int optionPosLabel = 35; // label, if defined
45: static int optionPosOpcode = 47; // opcode
46: static int optionPosOperand = 57; // operands for the opcode
47: static int optionPosComment = 82; // comment, if defined
1.1 root 48:
49: /***
50: * Motorola 16-/32-Bit Microprocessor and coprocessor types
51: ***/
52: #define MC68000 0x000001 // 16-/32-Bit Microprocessor
53: #define MC68EC000 0x000002 // 16-/32-Bit Embedded Controller
54: #define MC68HC000 0x000004 // Low Power 16-/32-Bit Microprocessor
55: #define MC68008 0x000008 // 16-Bit Microprocessor with 8-Bit Data Bus
56: #define MC68010 0x000010 // 16-/32-Bit Virtual Memory Microprocessor
57: #define MC68020 0x000020 // 32-Bit Virtual Memory Microprocessor
58: #define MC68EC020 0x000040 // 32-Bit Embedded Controller (no PMMU)
59: #define MC68030 0x000080 // Second-Generation 32-Bit Enhanced Microprocessor
60: #define MC68EC030 0x000100 // 32-Bit Embedded Controller (no PMMU)
61: #define MC68040 0x000200 // Third-Generation 32-Bit Microprocessor
62: #define MC68LC040 0x000400 // Third-Generation 32-Bit Microprocessor (no FPU)
63: #define MC68EC040 0x000800 // 32-Bit Embedded Controller (no FPU, no PMMU)
64: #define MC68330 0x001000 // CPU32 Integrated CPU32 Processor
65: #define MC68340 0x002000 // CPU32 Integrated Processor with DMA
66: #define MC68060 0x004000 // Fourth-Generation 32-Bit Microprocessor
67: #define MC68LC060 0x008000 // Fourth-Generation 32-Bit Microprocessor (no FPU)
68: #define MC68EC060 0x010000 // Fourth-Generation 32-Bit Microprocessor (no FPU, no PMMU)
69: #define MC_CPU32 (MC68330|MC68340)
70:
71: #define MC_020 (MC68020|MC68EC020|MC68030|MC68EC030|MC68040|MC68LC040|MC68EC040|MC_CPU32|MC68060|MC68LC060|MC68EC060)
72: #define MC_ALL (MC68000|MC68EC000|MC68HC000|MC68008|MC68010|MC_020)
73:
74: #define MC68851 0x020000 // Paged Memory Management Unit
75:
76: #define MC68881 0x040000 // Floating-PointCoprocessor
77: #define MC68882 0x080000 // Enhanced Floating-Point Coprocessor
78:
79: #define MC_PMMU (MC68881|MC68882)
80: #define MC_FPU (MC68881|MC68882)
81:
82: static int optionCPUTypeMask = ( MC_ALL & ~MC68040 & ~MC_CPU32 & ~MC68060 ) | MC_PMMU | MC_FPU;
83:
84:
85: typedef enum {
86: dtNone,
87: dtByte, // a specific number of bytes, usually 1
88: dtWord, // one 16-bit value
89: dtLong, // one 32-bit value
90: dtOpcode, // an opcode of variable length
91: dtASCString, // a 0-byte terminated ASCII string
92: dtPointer, // a generic 32-bit pointer
93: dtFunctionPointer, // a 32-bit pointer to a function
1.1.1.5 root 94: dtStringArray // a specific number of ASCII bytes
1.1 root 95: } Disass68kDataType;
96:
97: typedef struct {
98: char *name;
99: char *comment;
100: Disass68kDataType type;
101: int size;
102: } disStructElement;
103:
104: typedef struct {
105: char *name; // name of the structure
106: int size; // size of structure
107: int count; // number of lines
108: disStructElement *elements; // array of all elements of the struct
109: } disStructEntry;
110:
111: static int disStructCounts;
112: static disStructEntry *disStructEntries;
113:
114: typedef struct {
115: long addr; // address of the label
116: Disass68kDataType type; // type of the data on the address
117: int size; // size of the label, references inside it are addressed via base address + offset
118: int count; // number of elements at this address with the given size
119: int structIndex; // -1 no struct to describe the element
120: char *name; // name of the label
121: char *comment; // optional comment
122: } disSymbolEntry;
123:
124: static int disSymbolCounts;
125: static disSymbolEntry *disSymbolEntries;
126:
127:
128: static inline unsigned short Disass68kGetWord(long addr)
129: {
1.1.1.6 root 130: if ( ! valid_address ( addr , 2 ) )
131: return 0;
132:
1.1.1.7 root 133: return STMemory_ReadWord ( addr );
1.1 root 134: }
135:
136: // Load a text file into memory, count the lines and replace the LF with 0-bytes.
137: static int Disass68kLoadTextFile(const char *filename, char **filebuf)
138: {
139: long index;
1.1.1.4 root 140: long fileLength;
1.1.1.6 root 141: int lineCount = 0;
1.1.1.4 root 142: char *fbuf;
143: FILE *f;
144:
1.1 root 145: if(filebuf)
146: *filebuf = NULL;
1.1.1.4 root 147: f = fopen(filename, "r");
1.1.1.6 root 148: if (!f)
1.1 root 149: return 0;
1.1.1.6 root 150: if (fseek(f, 0, SEEK_END))
151: goto out;
1.1.1.4 root 152: fileLength = ftell(f);
1.1.1.6 root 153: if (fileLength <= 0)
154: goto out;
155: if (fseek(f, 0, SEEK_SET))
156: goto out;
1.1.1.4 root 157: fbuf = malloc(fileLength);
1.1.1.6 root 158: if(!fbuf)
159: goto out;
1.1 root 160: if((size_t)fileLength != fread(fbuf, sizeof(char), fileLength, f))
1.1.1.4 root 161: {
162: free(fbuf);
1.1.1.6 root 163: goto out;
1.1.1.4 root 164: }
1.1.1.6 root 165:
1.1 root 166: for(index=0; index<fileLength; ++index)
167: {
168: if(fbuf[index] == '\r') // convert potential CR into a space (which we ignore at the end of the line anyway)
169: fbuf[index] = ' ';
170: if(fbuf[index] == '\n') // count LF and terminate line
171: {
172: ++lineCount;
173: fbuf[index] = 0;
174: }
175: }
176: if(filebuf)
177: *filebuf = fbuf;
1.1.1.6 root 178: out:
179: fclose(f);
1.1 root 180: return lineCount;
181: }
182:
183: static void Disass68kLoadStructInfo(const char *filename)
184: {
1.1.1.4 root 185: int i,j;
186: char *nextLine;
187: char *line;
1.1 root 188: char *fbuf = NULL;
1.1.1.4 root 189: int lineCount = Disass68kLoadTextFile(filename, &fbuf);
1.1 root 190: disStructEntry *se = NULL;
1.1.1.4 root 191:
192: if(!lineCount) return;
193:
1.1.1.8 ! root 194: se = realloc(disStructEntries, sizeof(disStructEntry) * (disStructCounts + lineCount));
! 195: if (!se)
! 196: {
! 197: perror("Disass68kLoadStructInfo");
! 198: free(disStructEntries);
! 199: disStructEntries = NULL;
! 200: free(fbuf);
! 201: return;
! 202: }
! 203: disStructEntries = se;
! 204: se = NULL;
1.1.1.4 root 205:
206: line = fbuf;
1.1 root 207:
208: for(i=0; i<lineCount; line = nextLine, ++i)
209: {
210: // strip spaces at the end of the line, remember the ptr to the next line
211: char *sp = line;
212: while(*sp++)
213: ;
214: nextLine = sp--;
1.1.1.5 root 215: while (isspace((unsigned char)*--sp))
1.1 root 216: *sp = 0;
217:
218: if(line[0] == '{')
219: {
220: se = &disStructEntries[disStructCounts];
221: se->name = strdup(line+1);
222: se->count = 0;
223: se->elements = malloc(sizeof(disStructElement) * lineCount); // lineCount is way too much, but safe
224: } else if(line[0] == '}') {
225: if(se)
226: {
227: se->size = 0;
228: for(j=0; j<se->count; ++j)
229: se->size += se->elements[j].size;
230: // printf("%s : %d bytes\n", se->name, se->size);
231: ++disStructCounts;
232: se = NULL;
233: }
234: } else if(line[0] == '#') {
235: disStructElement dse;
236: int val = 0;
237: int index = 2;
238: if(line[1] == 'A' || line[1] == 'B')
239: {
1.1.1.5 root 240: for(; isdigit((unsigned char)line[index]); ++index)
1.1 root 241: {
242: val *= 10;
243: val += line[index] - '0';
244: }
245: }
246: if(val == 0) val = 1;
247: dse.name = NULL;
248: switch(line[1])
249: {
250: case 'A': dse.type = dtStringArray; dse.size = val; dse.name = strdup(line + index + 1); break;
251: case 'B': dse.type = dtByte; dse.size = val; break;
252: case 'W': dse.type = dtWord; dse.size = 2; break;
253: case 'L': dse.type = dtLong; dse.size = 4; break;
254: case 'C': dse.type = dtOpcode; dse.size = 2; break;
255: case 'f': dse.type = dtFunctionPointer; dse.size = 4; break;
256: case 'p': dse.type = dtPointer; dse.size = 4; break;
257: default: dse.type = dtNone; dse.size = 0;
258: printf("Unknown type in \"%s\"\n", line); break;
259: }
260: if(!dse.name)
261: dse.name = strdup(line+3);
262: dse.comment = NULL;
263: if(se)
264: se->elements[se->count++] = dse;
265: }
266: }
267: free(fbuf);
268: }
269:
270: static void Disass68kLoadSymbols(const char *filename)
271: {
1.1.1.4 root 272: int i,j;
273: char *nextLine;
274: char *line;
1.1 root 275: char *fbuf = NULL;
1.1.1.8 ! root 276: int lineCount = Disass68kLoadTextFile(filename, &fbuf);
! 277: disSymbolEntry *nde;
! 278:
! 279: if (!lineCount)
! 280: return;
! 281:
! 282: nde = realloc(disSymbolEntries, sizeof(disSymbolEntry) * (disSymbolCounts + lineCount));
! 283: if (!nde)
! 284: {
! 285: perror("Disass68kLoadSymbols");
! 286: free(disSymbolEntries);
! 287: disSymbolEntries = NULL;
! 288: free(fbuf);
! 289: return;
! 290: }
! 291: disSymbolEntries = nde;
! 292:
1.1.1.4 root 293: line = fbuf;
1.1 root 294:
295: for(i=0; i<lineCount; line = nextLine, ++i)
296: {
1.1.1.4 root 297: long addr;
1.1 root 298: char *sp = line;
1.1.1.4 root 299: char *parameterPtr[10];
300: int parameterCount = 0;
301: char *str;
302: long size = 0;
303: int type = 0;
304:
305: // strip spaces at the end of the line, remember the ptr to the next line
1.1 root 306: while(*sp++)
307: ;
308: nextLine = sp--;
1.1.1.5 root 309: while(isspace((unsigned char)*--sp))
1.1 root 310: *sp = 0;
311:
312: // ignore empty lines
313: if(line[0] == 0)
314: continue;
315:
316: sscanf(line, "%lx",&addr);
317: disSymbolEntries[disSymbolCounts].addr = addr;
318: disSymbolEntries[disSymbolCounts].structIndex = -1;
319:
1.1.1.4 root 320: str = line;
1.1 root 321: do {
322: str = strchr(str, ',');
323: if(str)
324: {
325: char *ep = str;
1.1.1.5 root 326: while(isspace((unsigned char)*--ep))
1.1 root 327: *ep = 0;
328: *str++ = 0;
1.1.1.5 root 329: while(*str && isspace((unsigned char)*str))
1.1 root 330: ++str;
331: parameterPtr[parameterCount++] = str;
332: }
333: } while(str != NULL && parameterCount < 10);
334:
335: if(parameterCount != 3 && parameterCount != 4)
336: continue; // ignore line
337:
338: if(strlen(parameterPtr[0]) == 1)
339: {
340: switch(parameterPtr[0][0])
341: {
342: case 'A': type = dtASCString; size = 1; break; // ascii NULL
343: case 'B': type = dtByte; size = 1; break; // byte
344: case 'W': type = dtWord; size = 2; break; // word
345: case 'L': type = dtLong; size = 4; break; // long
346: case 'C': type = dtOpcode; size = 2; break; // code
347: case 'f': type = dtFunctionPointer; size = 4; break; // function pointer
348: case 'p': type = dtPointer; size = 4; break; // regular pointer
349: default: printf("ERROR: $%lx : %s\n", addr, parameterPtr[0]); continue;
350: }
351: } else {
352: for(j=0; j<disStructCounts; ++j)
353: {
354: disStructEntry *se = &disStructEntries[j];
355: if(se->name == NULL)
356: break;
357: if(strcmp(parameterPtr[0], se->name))
358: continue;
359: size = se->size;
360: disSymbolEntries[disSymbolCounts].structIndex = j;
361: }
362: }
363: if(!size)
364: continue;
365:
366: disSymbolEntries[disSymbolCounts].type = type;
367: disSymbolEntries[disSymbolCounts].size = size;
368: disSymbolEntries[disSymbolCounts].count = atol(parameterPtr[1]);
369: disSymbolEntries[disSymbolCounts].name = strdup(parameterPtr[2]);
370: disSymbolEntries[disSymbolCounts].comment = NULL;
371: if(parameterCount == 4)
372: disSymbolEntries[disSymbolCounts].comment = strdup(parameterPtr[3]);
373: ++disSymbolCounts;
374: }
375: free(fbuf);
376: }
377:
378: static void Disass68kInit(const char *baseDirectory)
379: {
1.1.1.2 root 380: char filename[FILENAME_MAX];
1.1 root 381:
382: disStructCounts = 0;
383: sprintf(filename, "%s/DisassStructs.txt", baseDirectory);
384: Disass68kLoadStructInfo(filename);
385: sprintf(filename, "%s/DisassStructs_%4.4X.txt", baseDirectory, TosVersion);
386: Disass68kLoadStructInfo(filename);
387:
388: disSymbolCounts = 0;
389: sprintf(filename, "%s/DisassSymbols.txt", baseDirectory);
390: Disass68kLoadSymbols(filename);
391: sprintf(filename, "%s/DisassSymbols_%4.4X.txt", baseDirectory, TosVersion);
392: Disass68kLoadSymbols(filename);
393: }
394:
395:
396:
397: static Disass68kDataType Disass68kType(long addr, char *addressLabel, char *commentBuffer, int *count)
398: {
399: int i,j;
400:
401: addressLabel[0] = 0;
402: commentBuffer[0] = 0;
403: for(i=0; i<disSymbolCounts; ++i)
404: {
1.1.1.4 root 405: const disStructEntry *se;
1.1 root 406: const disSymbolEntry *dse = &disSymbolEntries[i];
407: int offset = addr - dse->addr;
1.1.1.4 root 408:
1.1 root 409: if(offset < 0 || offset >= dse->count * dse->size)
410: continue;
411:
412: // no special struct that devices this value?
413: if(dse->structIndex < 0)
414: {
415: offset = (offset + dse->size - 1) / dse->size;
416: *count = dse->count - offset;
417: if(offset == 0) // only in the first line
418: {
419: strcpy(addressLabel, dse->name);
420: if(dse->comment)
421: strcpy(commentBuffer, dse->comment);
422: }
423: return dse->type;
424: }
425:
426: *count = 1;
1.1.1.4 root 427: se = &disStructEntries[dse->structIndex];
1.1 root 428: for(j=0; j<se->count; ++j)
429: {
430: const disStructElement *e = &se->elements[j];
431: if(offset < e->size)
432: {
433: if(e->type == dtStringArray)
434: *count = e->size;
435: if(j == 0)
436: strcpy(addressLabel, dse->name);
437:
438: sprintf(commentBuffer, "[%s]", e->name);
439: if(e->comment)
440: strcat(commentBuffer, e->comment);
441: return e->type;
442: }
443: offset -= e->size;
444: }
445: return dse->size;
446: }
447: return dtNone;
448: }
449:
450: /***
451: * Lookup a symbol name
452: ***/
453: static const char *Disass68kSymbolName(long addr, int size)
454: {
455: int i;
456:
457: for(i=0; i<disSymbolCounts; ++i)
458: {
1.1.1.4 root 459: static char symbolName[128];
1.1 root 460: const disSymbolEntry *dse = &disSymbolEntries[i];
1.1.1.4 root 461: int offset = addr - dse->addr;
462: int reminder;
463:
1.1 root 464: if(offset < 0 || offset >= dse->count * dse->size)
465: continue;
466:
467: if(dse->name[0] == 0)
468: return NULL;
469:
1.1.1.4 root 470: reminder = offset % dse->size;
1.1 root 471: offset /= dse->size;
472:
473: strcpy(symbolName, dse->name);
474: if(offset)
475: sprintf(symbolName+strlen(symbolName), "+%d*%d", dse->size, offset);
476: if(reminder)
477: sprintf(symbolName+strlen(symbolName), "+%d", reminder);
478: return symbolName;
479: }
480: return NULL;
481: }
482:
483: /***
484: * return a string pointer to display a register name
485: ***/
486: static const char *Disass68kRegname(int reg)
487: {
488: static char regName[3];
1.1.1.8 ! root 489:
! 490: if (reg == 0x0F && (options & doptStackSP) != 0)
1.1 root 491: {
1.1.1.8 ! root 492: /* display A7 as SP */
! 493: return (options & doptRegisterSmall) ? "sp" : "SP";
! 494: }
1.1 root 495:
1.1.1.8 ! root 496: if (reg >= 0x0 && reg <= 0x7)
! 497: {
! 498: regName[0] = (options & doptRegisterSmall) ? 'd' : 'D';
! 499: }
! 500: else if (reg >= 0x8 && reg <= 0xf)
! 501: {
! 502: regName[0] = (options & doptRegisterSmall) ? 'a' : 'A';
1.1 root 503: }
1.1.1.8 ! root 504: else
! 505: {
! 506: regName[0] = '?';
! 507: }
! 508:
! 509: regName[1] = '0' + (reg & 7);
! 510: regName[2] = 0;
! 511:
1.1 root 512: return regName;
513: }
514:
515: /***
516: * return a string pointer to display a register name
517: ***/
518: static const char *Disass68kNumber(int val)
519: {
520: static char numString[32];
521: if(val >= -9 && val <= 9)
522: {
523: sprintf(numString, "%d", val);
524: } else {
525: // 4 characters/numbers or underscore (e.g. for cookies)
1.1.1.5 root 526: unsigned char c0 = (val >> 24) & 0xFF;
527: unsigned char c1 = (val >> 16) & 0xFF;
528: unsigned char c2 = (val >> 8) & 0xFF;
529: unsigned char c3 = (val >> 0) & 0xFF;
1.1 root 530: if((isalnum(c0) || c0 == '_') && (isalnum(c1) || c1 == '_') && (isalnum(c2) || c2 == '_') && (isalnum(c3) || c3 == '_'))
531: {
532: sprintf(numString, "'%c%c%c%c'", c0, c1, c2, c3);
533: } else {
534: sprintf(numString, "$%x", val);
535: }
536: }
537: return numString;
538: }
539:
540: /***
541: * Supported registers for e.g. MOVEC
542: ***/
543: #define REG_CCR -1
544: #define REG_SR -2
545: #define REG_PC -3
546: #define REG_ZPC -4
547: #define REG_TT0 -8
548: #define REG_TT1 -9
549: #define REG_MMUSR -10
550: #define REG_USP 0x800
551: #define REG_SFC 0x000
552: #define REG_DFC 0x001
553: #define REG_TC 0x10000
554: #define REG_SRP 0x10002
555: #define REG_CRP 0x10003
556: #define REG_VAL 0x20000
557: #define REG_CACHES_NONE 0x20010
558: #define REG_CACHES_IC 0x20011
559: #define REG_CACHES_DC 0x20012
560: #define REG_CACHES_ICDC 0x20013
561: #define REG_FPU_FPCR 0x30004
562: #define REG_FPU_FPSR 0x30002
563: #define REG_FPU_FPIAR 0x30001
564:
565: static const char *Disass68kSpecialRegister(int reg)
566: {
567: static char buf[8];
568: const char *sp = NULL;
569: switch (reg)
570: {
571: case 0x000: sp = "SFC"; break;
572: case 0x001: sp = "DFC"; break;
573: case 0x002: sp = "CACR"; break;
574: case 0x003: sp = "TC"; break;
575: case 0x004: sp = "ITT0"; break; // IACR0 on an 68EC040 only
576: case 0x005: sp = "ITT1"; break; // IACR1 on an 68EC040 only
577: case 0x006: sp = "DTT0"; break; // DACR0 on an 68EC040 only
578: case 0x007: sp = "DTT1"; break; // DACR1 on an 68EC040 only
579: case 0x008: sp = "BUSCR"; break;
580:
581: case 0x800: sp = "USP"; break;
582: case 0x801: sp = "VBR"; break;
583: case 0x802: sp = "CAAR"; break;
584: case 0x803: sp = "MSP"; break;
585: case 0x804: sp = "ISP"; break;
586: case 0x805: sp = "MMUSR"; break;
587: case 0x806: sp = "URP"; break;
588: case 0x807: sp = "SRP"; break;
589: case 0x808: sp = "PCR"; break;
590:
591: // MMU register
592: case 0x10000: sp = "TC"; break;
593: case 0x10001: sp = "DRP"; break;
594: case 0x10002: sp = "SRP"; break;
595: case 0x10003: sp = "CRP"; break;
596: case 0x10004: sp = "CAL"; break;
597: case 0x10005: sp = "VAL"; break;
598: case 0x10006: sp = "SCCR"; break;
599: case 0x10007: sp = "ACR"; break;
600:
601: case REG_CCR: sp = "CCR"; break;
602: case REG_SR: sp = "SR"; break;
603: case REG_PC: sp = "PC"; break;
604: case REG_ZPC: sp = "ZPC"; break;
605: case REG_TT0: sp = "TT0"; break;
606: case REG_TT1: sp = "TT1"; break;
607: case REG_MMUSR: sp = "MMUSR"; break;
608:
609: case REG_VAL: sp = "VAL"; break;
610:
611: case REG_CACHES_NONE: sp = "NC"; break;
612: case REG_CACHES_IC: sp = "IC"; break;
613: case REG_CACHES_DC: sp = "DC"; break;
614: case REG_CACHES_ICDC: sp = "IC/DC"; break; // GCC lists this as "BC"
615:
616: case REG_FPU_FPCR: sp = "FPCR"; break;
617: case REG_FPU_FPSR: sp = "FPSR"; break;
618: case REG_FPU_FPIAR: sp = "FPIAR"; break;
619:
620: // unknown register => unknown opcode!
1.1.1.4 root 621: default: return NULL;
1.1 root 622: }
1.1.1.4 root 623:
1.1 root 624: if(options & doptRegisterSmall)
625: {
1.1.1.4 root 626: char *bp;
1.1 root 627: strcpy(buf, sp);
1.1.1.4 root 628: for (bp = buf; *bp; ++bp)
1.1.1.5 root 629: *bp = tolower((unsigned char)*bp);
1.1 root 630: return buf;
631: }
632: return sp;
633: }
634:
635: /***
636: * 680x0 EA disassembly, supports all address modes
637: *
638: * disassbuf = output buffer for the EA, empty string in case of an illegal EA
639: * addr = pointer to the address, which Disass68kGetWord() will allow to read memory.
640: * Incremented by the function to point behind the opcode, when done
641: * ea = 6-bit ea from the opcode
642: * size = addressed size of the opcode in bytes (e.g. 1,2,4 for MOVE.B, MOVE.W, MOVE.L), only used for immediate addressing
643: ***/
644:
645: #define EA_Dn 0x00001 // Dn
646: #define EA_An 0x00002 // An
647: #define EA_Ani 0x00004 // (An)
648: #define EA_Anip 0x00008 // (An)+
649: #define EA_piAn 0x00010 // -(An)
650: #define EA_dAn 0x00020 // d(An), d(An,Dn), etc.
651: #define EA_PCRel 0x00040 // d(PC), d(PC,Dn), etc.
652: #define EA_Abs 0x00080 // abs.w, abs.l
653: #define EA_Immed 0x00100 // #<val>
654:
655: #define EA_ImmedParameter 0x0200 // an immediate value as a parameter
656: #define EA_ValueParameter 0x0400 // an immediate value as a parameter without the "#"
657: #define EA_SpecialRegister 0x0800 // any special register e.g. SR,CCR,USP,etc
658: #define EA_PCDisplacement 0x1000 // PC relative jump, like for BRA and friends
659:
660: #define EA_All (EA_Dn | EA_An | EA_Ani | EA_Anip | EA_piAn | EA_dAn | EA_Abs | EA_Immed | EA_PCRel)
661: #define EA_Dest (EA_Dn | EA_An | EA_Ani | EA_Anip | EA_piAn | EA_dAn | EA_Abs)
662:
663: static char *Disass68kEA(char *disassbuf, char *commentBuffer, long *addr, long opcodeAddr, int ea, int size, int allowedEAs, int parameterValue, int disassFlag)
664: {
665: unsigned short eWord1;
666: unsigned short eWord2;
667: int xn,c,scale;
668: int reg = ea & 7;
669: const char *sp;
670: long val;
1.1.1.4 root 671: char regName[3];
672: signed long pcoffset;
673:
1.1 root 674: disassbuf[0] = 0;
675: switch(ea)
676: {
677: // M=000 = 0 Dn
678: // Data Register Direct Mode
679: // Dn
680: // M=001 = 1 An
681: // Address Register Direct Mode
682: // An
683: case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
684: if((allowedEAs & EA_Dn) != EA_Dn)
685: break;
686: sprintf(disassbuf, "%s", Disass68kRegname(ea & 0x0F));
687: break;
688: case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: case 0x0D: case 0x0E: case 0x0F:
689: if((allowedEAs & EA_An) != EA_An)
690: break;
691: sprintf(disassbuf, "%s", Disass68kRegname(ea & 0x0F));
692: break;
693:
694: // M=010 = 2
695: // Address Register Indirect Mode
696: // (An)
697: case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
698: if((allowedEAs & EA_Ani) != EA_Ani)
699: break;
700: sprintf(disassbuf, "(%s)", Disass68kRegname(reg | 8));
701: break;
702:
703: // M=011 = 3
704: // Address Register Indirect with Postincrement Mode
705: // (An) +
706: case 0x18: case 0x19: case 0x1A: case 0x1B: case 0x1C: case 0x1D: case 0x1E: case 0x1F:
707: if((allowedEAs & EA_Anip) != EA_Anip)
708: break;
709: sprintf(disassbuf, "(%s)+", Disass68kRegname(reg | 8));
710: break;
711:
712: // M=100 = 4
713: // Address Register Indirect with Predecrement Mode
714: // – (An)
715: case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
716: if((allowedEAs & EA_piAn) != EA_piAn)
717: break;
718: sprintf(disassbuf, "-(%s)", Disass68kRegname(reg | 8));
719: break;
720:
721: // M=101 = 5
722: // Address Register Indirect with Displacement Mode
723: // (d16,An)
724: case 0x28: case 0x29: case 0x2A: case 0x2B: case 0x2C: case 0x2D: case 0x2E: case 0x2F:
725: if((allowedEAs & EA_dAn) != EA_dAn)
726: break;
727: eWord1 = Disass68kGetWord(*addr); *addr += 2;
728: sprintf(disassbuf, "%s(%s)", Disass68kNumber(eWord1), Disass68kRegname(reg | 8));
729: break;
730:
731: // M=111 = 7, Xn/reg = 011 = 3
732: // Program Counter Indirect with Index (Base Displacement) Mode
733: // (bd, PC, Xn. SIZE*SCALE)
734: // Program Counter Memory Indirect Postindexed Mode
735: // ([bd,PC],Xn.SIZE*SCALE,od)
736: // Program Counter Memory Indirect Preindexed Mode
737: // ([bd,PC,Xn.SIZE*SCALE],od)
738: case 0x3B:
739: // This is equal to the following, except that instead of An, it is PC relative
740:
741: // M=110 = 6
742: // Address Register Indirect with Index (Base Displacement) Mode
743: // (bd,An,Xn.SIZE*SCALE)
744: // Memory Indirect Postindexed Mode
745: // ([bd,An],Xn.SIZE*SCALE,od)
746: // Memory Indirect Preindexed Mode
747: // ([bd, An, Xn.SIZE*SCALE], od)
748: case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
749: eWord1 = Disass68kGetWord(*addr); *addr += 2;
750: xn = (eWord1 >> 12) & 0x0F; // Register D0..D7/A0..A7
751: c = ((eWord1 >> 11) & 1) ? 'l' : 'w'; // Word/Long-Word Index Size 0 = Sign-Extended Word 1 = Long Word
752: scale = (eWord1 >> 9) & 3; // Scale Factor 00 = 1 01 = 2 10 = 4 11 = 8
1.1.1.4 root 753:
1.1 root 754: if(ea == 0x3B)
755: {
756: sp = Disass68kSpecialRegister(REG_PC);
757: if(!sp) return NULL;
758: strcpy(regName, sp);
759: } else {
760: sprintf(regName, "%s", Disass68kRegname(reg | 8));
761: }
762:
763: if((eWord1 & 0x0100) == 0)
764: {
1.1.1.4 root 765: const char *numStr;
766:
1.1 root 767: // BRIEF EXTENSION WORD FORMAT
768: if(ea == 0x3B)
769: {
770: if((allowedEAs & EA_PCRel) != EA_PCRel)
771: break;
772: } else {
773: if((allowedEAs & EA_dAn) != EA_dAn)
774: break;
775: }
776:
777: // Address Register Indirect with Index (8-Bit Displacement) Mode
778: // (d8 ,An, Xn.SIZE*SCALE)
1.1.1.4 root 779: numStr = Disass68kNumber(eWord1 & 0xFF);
1.1 root 780: if(numStr[0] == '0' && numStr[1] == 0)
781: numStr = "";
782:
783: // scale is only on 68020 and later supported
784: if(scale != 0 && (optionCPUTypeMask & MC_020) == 0)
785: return NULL;
786:
787: if(scale == 0)
788: {
789: #if ADDRESS_ON_PC
790: if(ea == 0x3B)
791: sprintf(disassbuf, "$%lx(%s,%s.%c)", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2, Disass68kSpecialRegister(REG_PC), Disass68kRegname(xn), c);
792: else
793: #endif
794: sprintf(disassbuf, "%s(%s,%s.%c)", numStr, regName, Disass68kRegname(xn), c);
795: } else
796: {
797: #if ADDRESS_ON_PC
798: if(ea == 0x3B)
799: sprintf(disassbuf, "$%lx(%s,%s.%c*%d)", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2, Disass68kSpecialRegister(REG_PC), Disass68kRegname(xn), c, 1 << scale);
800: else
801: #endif
802: sprintf(disassbuf, "%s(%s,%s.%c*%d)", numStr, regName, Disass68kRegname(xn), c, 1 << scale);
803: }
804: #if USE_SYMBOLS
805: if(ea == 0x3B)
806: {
807: const char *symStr = Disass68kSymbolName((signed char)(eWord1 & 0xFF) + opcodeAddr + 2, size);
808: if(symStr)
809: {
810: commentBuffer += strlen(commentBuffer);
811: sprintf(commentBuffer+strlen(commentBuffer), "%s", symStr);
812: }
813: }
814: #endif
815: #if !ADDRESS_ON_PC
816: if(ea == 0x3B)
817: {
818: commentBuffer += strlen(commentBuffer);
819: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2);
820: }
821: #endif
822: } else {
823: // FULL EXTENSION WORD FORMAT
824:
1.1.1.4 root 825: int bs = (eWord1 >> 7) & 1; // Base Register Suppress 0 = Base Register Added 1 = Base Register Suppressed
826: int is = (eWord1 >> 6) & 1; // Index Suppress 0 = Evaluate and Add Index Operand 1 = Suppress Index Operand
827: int bdSize = (eWord1 >> 4) & 3; // Base Displacement Size 00 = Reserved 01 = Null Displacement 10 = Word Displacement 11 = Long Displacement
828: int iis = eWord1 & 7; // Index/Indirect Selection Indirect and Indexing Operand Determined in Conjunction with Bit 6, Index Suppress
1.1 root 829: bool prefixComma;
1.1.1.4 root 830: long bd, od;
1.1 root 831:
832: // reserved, has to be 0
833: if((eWord1 & 8) != 0 || bdSize == 0 || (is && iis > 3) || iis == 4)
834: break;
835:
836: // full extension format is only supported on 68020 or later
837: if((optionCPUTypeMask & MC_020) == 0)
838: return NULL;
839:
840: if(ea == 0x3B)
841: {
842: if((allowedEAs & EA_PCRel) != EA_PCRel)
843: break;
844: } else {
845: if((allowedEAs & EA_dAn) != EA_dAn)
846: break;
847: }
848:
1.1.1.4 root 849: bd = 0;
1.1 root 850: switch(bdSize)
851: {
852: case 3:
853: bd = Disass68kGetWord(*addr); *addr += 2;
854: bd <<= 16;
855: case 2:
856: bd |= Disass68kGetWord(*addr); *addr += 2;
857: break;
858: default:
859: break;
860: }
861:
862: prefixComma = false;
863: if(bdSize >= 2 && iis == 0)
864: sprintf(disassbuf, "%s", Disass68kNumber(bd));
865: strcat(disassbuf, "(");
866: if(iis != 0)
867: {
868: // the CPU32 doesn't support the memory indirect mode
869: if(optionCPUTypeMask & MC_CPU32)
870: return NULL;
871:
872: strcat(disassbuf, "[");
873: }
874: if(bdSize >= 2 && iis != 0)
875: {
876: sprintf(disassbuf+strlen(disassbuf), "%s", Disass68kNumber(bd));
877: prefixComma = true;
878: }
879: if(bdSize == 1 && ((bs && is && iis > 0) || (bs && iis >= 5)))
880: {
881: if(ea == 0x3B)
882: {
883: sp = Disass68kSpecialRegister(REG_ZPC);
884: if(!sp) return NULL;
885: strcat(disassbuf, sp);
886: } else {
887: strcat(disassbuf, "0");
888: }
889: }
890: if(!bs)
891: {
892: if(prefixComma)
893: strcat(disassbuf, ",");
894: strcat(disassbuf, regName);
895: prefixComma = true;
896: }
897: if(iis >= 5 && iis <= 7)
898: {
899: strcat(disassbuf, "]");
900: prefixComma = true;
901: }
902: if(!is)
903: {
904: if(prefixComma)
905: strcat(disassbuf, ",");
906: if(scale == 0)
907: {
908: sprintf(disassbuf+strlen(disassbuf), "%s.%c", Disass68kRegname(xn), c);
909: } else
910: {
911: sprintf(disassbuf+strlen(disassbuf), "%s.%c*%d", Disass68kRegname(xn), c, 1 << scale);
912: }
913: }
914: if(iis >= 1 && iis <= 3)
915: {
916: strcat(disassbuf, "]");
917: prefixComma = true;
918: }
1.1.1.4 root 919: od = 0;
1.1 root 920: switch(iis & 3)
921: {
922: case 3:
923: od = Disass68kGetWord(*addr); *addr += 2;
924: od <<= 16;
925: case 2:
926: od |= Disass68kGetWord(*addr); *addr += 2;
927: if(prefixComma)
928: strcat(disassbuf, ",");
929: sprintf(disassbuf+strlen(disassbuf), "%s", Disass68kNumber(od));
930: break;
931: default:
932: break;
933: }
934: strcat(disassbuf, ")");
935: }
936: break;
937:
938: // M=111 = 7, Xn/reg = 000 = 0
939: // Absolute Short Addressing Mode
940: // (xxx).W
941: case 0x38:
942: if((allowedEAs & EA_Abs) != EA_Abs)
943: break;
944: eWord1 = Disass68kGetWord(*addr); *addr += 2;
945: val = eWord1;
946: if(eWord1 & 0x8000)
947: val |= 0xFFFF0000;
948: #if USE_SYMBOLS
949: sp = Disass68kSymbolName(val, size);
950: if(sp)
951: {
952: if(options & doptNoBrackets)
953: sprintf(disassbuf, "%s.w", sp);
954: else
955: sprintf(disassbuf, "(%s).w", sp);
956: break;
957: }
958: #endif
959: if(options & doptNoBrackets)
960: {
961: if(val & 0x80000000)
962: sprintf(disassbuf, "$%8.8lx.w", val);
963: else
964: sprintf(disassbuf, "$%4.4lx.w", val);
965: } else {
966: if(val & 0x80000000)
967: sprintf(disassbuf, "($%8.8lx).w", val);
968: else
969: sprintf(disassbuf, "($%4.4lx).w", val);
970: }
971: break;
972:
973: // M=111 = 7, Xn/reg = 001 = 1
974: // Absolute Long Addressing Mode
975: // (xxx).L
976: case 0x39:
977: if((allowedEAs & EA_Abs) != EA_Abs)
978: break;
979: eWord1 = Disass68kGetWord(*addr); *addr += 2;
980: eWord2 = Disass68kGetWord(*addr); *addr += 2;
981: #if USE_SYMBOLS
982: val = (eWord1 << 16) | eWord2;
983: sp = Disass68kSymbolName(val, size);
984: if(sp)
985: {
986: if(options & doptNoBrackets)
987: sprintf(disassbuf, "%s", sp);
988: else
989: sprintf(disassbuf, "(%s).l", sp);
990: break;
991: }
992: #endif
993: if(options & doptNoBrackets)
994: sprintf(disassbuf, "%s", Disass68kNumber((eWord1 << 16) | eWord2));
995: else
996: sprintf(disassbuf, "(%s).l", Disass68kNumber((eWord1 << 16) | eWord2));
997: break;
998:
999: // M=111 = 7, Xn/reg = 010 = 2
1000: // Program Counter Indirect with Displacement Mode
1001: // (d16,PC)
1002: case 0x3A:
1003: if((allowedEAs & EA_PCRel) != EA_PCRel)
1004: break;
1005: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1006: sp = Disass68kSpecialRegister(REG_PC);
1007: if(!sp) return NULL;
1008: #if ADDRESS_ON_PC
1009: #if USE_SYMBOLS
1010: sp = Disass68kSymbolName(((signed short)eWord1 + *addr - 2), size);
1011: if(sp)
1012: {
1013: sprintf(disassbuf, "%s(%s)", sp, Disass68kSpecialRegister(REG_PC));
1014: } else {
1015: sprintf(disassbuf, "$%lx(%s)", (signed short)eWord1 + *addr - 2, Disass68kSpecialRegister(REG_PC));
1016: }
1017: #else
1018: sprintf(disassbuf, "$%lx(%s)", (signed short)eWord1 + *addr - 2, Disass68kSpecialRegister(REG_PC));
1019: #endif
1020: #else
1021: sprintf(disassbuf, "%s(%s)", Disass68kNumber(eWord1),sp);
1022: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", (signed short)eWord1 + *addr - 2);
1023: #endif
1024: break;
1025:
1026: // M=111 = 7, Xn/reg = 100 = 4
1027: // Immediate Data
1028: // #<xxx>
1029: case 0x3C:
1030: if((allowedEAs & EA_Immed) != EA_Immed)
1031: break;
1032: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1033: goto immed;
1034:
1035: case 0x0100: // Immediate Value as a parameter
1036: if((allowedEAs & EA_ImmedParameter) != EA_ImmedParameter)
1037: break;
1038: eWord1 = parameterValue;
1039: immed:
1040: switch(size)
1041: {
1042: case 1: eWord1 &= 0xFF;
1.1.1.8 ! root 1043: /* fall through */
1.1 root 1044: case 2:
1045: #if USE_SYMBOLS
1046: if(disassFlag)
1047: {
1048: val = eWord1;
1049: if(eWord1 & 0x8000)
1050: val |= 0xFFFF0000;
1051: sp = Disass68kSymbolName(val, size);
1052: if(sp)
1053: {
1054: sprintf(disassbuf, "#%s", sp);
1055: break;
1056: }
1057: }
1058: #endif
1059: sprintf(disassbuf, "#%s", Disass68kNumber(eWord1));
1060: break;
1061: case 4: eWord2 = Disass68kGetWord(*addr); *addr += 2;
1062: #if USE_SYMBOLS
1063: if(disassFlag)
1064: {
1065: val = (eWord1 << 16) | eWord2;
1066: sp = Disass68kSymbolName(val, size);
1067: if(sp)
1068: {
1069: sprintf(disassbuf, "#%s", sp);
1070: break;
1071: }
1072: }
1073: #endif
1074: sprintf(disassbuf, "#%s", Disass68kNumber((eWord1 << 16) | eWord2));
1075: break;
1076: }
1077: break;
1078:
1079: case 0x0103:
1080: if((allowedEAs & EA_ValueParameter) != EA_ValueParameter)
1081: break;
1082: sprintf(disassbuf, "%d", parameterValue);
1083: break;
1084:
1085: case 0x0101: // Special Registers as in the parameter
1086: if((allowedEAs & EA_SpecialRegister) != EA_SpecialRegister)
1087: break;
1088: sp = Disass68kSpecialRegister(parameterValue);
1089: if(!sp) return NULL;
1090: strcpy(disassbuf, sp);
1091: break;
1092:
1093: case 0x0102: // PC relative jump, like for BRA and friends
1094: if((allowedEAs & EA_PCDisplacement) != EA_PCDisplacement)
1095: break;
1.1.1.4 root 1096: pcoffset = 0;
1.1 root 1097: switch(size)
1098: {
1099: case 1: pcoffset = (signed char)parameterValue;
1100: break;
1101: case 2: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1102: pcoffset = (signed short)eWord1;
1103: pcoffset -= 2;
1104: break;
1105: case 4: eWord1 = Disass68kGetWord(*addr); *addr += 2;
1106: eWord2 = Disass68kGetWord(*addr); *addr += 2;
1107: pcoffset = (signed int)((eWord1 << 16) | eWord2);
1108: pcoffset -= 4;
1109: break;
1110: }
1111: #if ADDRESS_ON_PC
1112: #if USE_SYMBOLS
1113: sp = Disass68kSymbolName((*addr + pcoffset), size);
1114: if(sp)
1115: {
1116: strcat(disassbuf, sp);
1117: } else {
1118: sprintf(disassbuf, "$%lx", *addr + pcoffset);
1119: }
1120: #else
1121: sprintf(disassbuf, "$%lx", *addr + pcoffset);
1122: #endif
1123: #else
1124: if(pcoffset < 0)
1125: {
1126: sprintf(disassbuf, "*-$%lx", -pcoffset - 2);
1127: } else {
1128: sprintf(disassbuf, "*+$%lx", pcoffset + 2);
1129: }
1130: sprintf(commentBuffer+strlen(commentBuffer), "$%lx", *addr + pcoffset);
1131: #endif
1132: break;
1133:
1134: default: // 0x3D..0x3F are reserved
1135: break;
1136:
1137: }
1138: if(disassbuf[0] == 0)
1139: return NULL;
1140: return disassbuf + strlen(disassbuf);
1141: }
1142:
1143: /***
1144: * Create a register list for the MOVEM opcode
1145: ***/
1146: static char *Disass68kReglist(char *buf, unsigned short reglist)
1147: {
1148: int bit;
1149: int lastBit = -99;
1150: int lastBitStart = -99;
1151: char regD = options & doptRegisterSmall ? 'd' : 'D';
1152: char regA = options & doptRegisterSmall ? 'a' : 'A';
1153: for(bit=0; bit<=15; ++bit)
1154: {
1155: // bit clear?
1156: if((reglist & (1 << bit)) == 0)
1157: {
1158: // do we have a run? => close it!
1159: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1160: {
1161: *buf++ = '-';
1162: *buf++ = ((bit-1) >= 8) ? regA : regD;
1163: *buf++ = '0' + ((bit-1) & 7);
1164: }
1165: lastBitStart = -1;
1166: continue;
1167: }
1168: // reset when switching from D to A
1169: if(bit == 8 && lastBitStart >= 0)
1170: {
1171: *buf++ = '-';
1172: *buf++ = regD;
1173: *buf++ = '7';
1174: lastBit = 0;
1175: lastBitStart = -99;
1176: }
1177: // separate bits, skip runs of bits to merge them later
1178: if(lastBit >= 0)
1179: {
1180: if(lastBit == bit - 1)
1181: {
1182: lastBit = bit;
1183: continue;
1184: }
1185: *buf++ = '/';
1186: }
1187: *buf++ = (bit >= 8) ? regA : regD;
1188: *buf++ = '0' + (bit & 7);
1189: lastBit = bit;
1190: lastBitStart = bit;
1191: }
1192: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1193: {
1194: *buf++ = '-';
1195: *buf++ = regA;
1196: *buf++ = '7';
1197: }
1198: if(lastBit < 0)
1199: {
1200: *buf++ = '0';
1201: }
1202: *buf = 0;
1203: return buf;
1204: }
1205:
1206: /***
1207: * Flip the bits in an unsigned short, for MOVEM RegList,-(An)
1208: ***/
1209: static unsigned short Disass68kFlipBits(unsigned short mask)
1210: {
1211: unsigned short retMask = 0;
1212: int i;
1213:
1214: for(i=0; i<=15; ++i)
1215: if(mask & (1 << i))
1216: retMask |= (1 << (15-i));
1217: return retMask;
1218: }
1219:
1220: /***
1221: * Create a register list for the MOVEM opcode
1222: ***/
1223: static char *Disass68kFPUReglist(char *buf, unsigned char reglist)
1224: {
1225: int bit;
1226: int lastBit = -99;
1227: int lastBitStart = -99;
1228: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
1229: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
1230: for(bit=0; bit<=7; ++bit)
1231: {
1232: // bit clear?
1233: if((reglist & (1 << bit)) == 0)
1234: {
1235: // do we have a run? => close it!
1236: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1237: {
1238: *buf++ = '-';
1239: *buf++ = regFP1;
1240: *buf++ = regFP2;
1241: *buf++ = '0' + ((bit-1) & 7);
1242: }
1243: lastBitStart = -1;
1244: continue;
1245: }
1246: // separate bits, skip runs of bits to merge them later
1247: if(lastBit >= 0)
1248: {
1249: if(lastBit == bit - 1)
1250: {
1251: lastBit = bit;
1252: continue;
1253: }
1254: *buf++ = '/';
1255: }
1256: *buf++ = regFP1;
1257: *buf++ = regFP2;
1258: *buf++ = '0' + (bit & 7);
1259: lastBit = bit;
1260: lastBitStart = bit;
1261: }
1262: if(lastBitStart >= 0 && lastBitStart != (bit - 1))
1263: {
1264: *buf++ = '-';
1265: *buf++ = regFP1;
1266: *buf++ = regFP2;
1267: *buf++ = '7';
1268: }
1269: if(lastBit < 0)
1270: {
1271: *buf++ = '0';
1272: }
1273: *buf = 0;
1274: return buf;
1275: }
1276:
1277:
1278: /***
1279: * List of special cases for the operands
1280: ***/
1281: typedef enum {
1282: ofNone,
1283: ofEa,
1284: ofDn,
1285: ofAn,
1286: ofAni,
1287: ofI,
1288: ofSpecReg,
1289: ofSpecExtReg,
1290: ofD16An,
1291: ofDestDn,
1292: ofDestAn,
1293: ofExtReg,
1294: ofExtAnip,
1295: ofExtReg0,
1296: ofExtRegA0,
1297: ofExtRegD04,
1298: ofExtRegA05,
1299: ofFPUReglist,
1300: ofFPUSRRegList,
1301: ofDestEa6,
1302: ofDestAbsL,
1303: ofIOpcode,
1304: ofCAS,
1305: ofCAS2,
1306: ofI3,
1307: ofExtIm,
1308: ofExtIm32,
1309: ofExtIm4,
1310: ofExtIm10,
1311: ofDisp,
1312: ofPiAn,
1313: ofDestPiAn,
1314: ofAnip,
1315: ofDestAnip,
1316: ofBFEa,
1317: ofRegList,
1318: ofExt4Dn,
1319: ofFPU,
1320: ofFPUMOVE,
1321: ofFMOVECR,
1322: ofFPU3Reg,
1.1.1.5 root 1323: ofLineA
1.1 root 1324: } Disass68kOpcodeFormat;
1325:
1326:
1327: /***
1328: * The order of the table is not important (with the exception of some FPU opcodes, which are commented further down),
1329: * as each opcode should decline if it doesn't match 100%. The 68k CPU also doesn't do guessing based on the context!
1330: ***/
1331: typedef const struct {
1332: int cpuMask;
1333: unsigned long opcodeMask[2*5];
1.1.1.4 root 1334: signed char operationSize[4];
1.1 root 1335: char op[5];
1336: const char *opcodeName;
1337: int parameter[5];
1338: int disassFlag;
1339: } OpcodeTableStruct;
1340:
1.1.1.6 root 1341: static OpcodeTableStruct OpcodeTable[] = {
1.1 root 1342: { MC_ALL, {0xff00, 0x0000}, {-1,6,2,0}, {ofI,ofEa}, "ORI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1343: { MC_ALL, {0xf1c0, 0x0100}, {4}, {ofDestDn,ofEa}, "BTST",{0,EA_An|EA_Immed} },
1344: { MC_ALL, {0xf1c0, 0x0140}, {4}, {ofDestDn,ofEa}, "BCHG",{0,EA_Immed|EA_PCRel|EA_An}},
1345: { MC_ALL, {0xf1c0, 0x0180}, {4}, {ofDestDn,ofEa}, "BCLR",{0,EA_Immed|EA_PCRel|EA_An}},
1346: { MC_ALL, {0xf1c0, 0x01C0}, {4}, {ofDestDn,ofEa}, "BSET",{0,EA_Immed|EA_PCRel|EA_An}},
1347: { MC_ALL-MC68060, {0xf1f8, 0x0108}, {2}, {ofD16An,ofDestDn}, "MOVEP.W"},
1348: { MC_ALL-MC68060, {0xf1f8, 0x0148}, {4}, {ofD16An,ofDestDn}, "MOVEP.L"},
1349: { MC_ALL-MC68060, {0xf1f8, 0x0188}, {2}, {ofDestDn,ofD16An}, "MOVEP.W"},
1350: { MC_ALL-MC68060, {0xf1f8, 0x01C8}, {4}, {ofDestDn,ofD16An}, "MOVEP.L"},
1351: { MC_ALL, {0xff00, 0x0200}, {-1,6,2,0}, {ofI,ofEa}, "ANDI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1352: { MC_ALL, {0xff00, 0x0400}, {-1,6,2,0}, {ofI,ofEa}, "SUBI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1353: { MC_ALL, {0xff00, 0x0600}, {-1,6,2,0}, {ofI,ofEa}, "ADDI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1354: { MC_ALL, {0xffc0, 0x0800}, {1}, {ofI,ofEa}, "BTST",{0,EA_An|EA_Immed} },
1355: { MC_ALL, {0xffc0, 0x0840}, {1}, {ofI,ofEa}, "BCHG",{0,EA_Immed|EA_PCRel|EA_An}},
1356: { MC_ALL, {0xffc0, 0x0880}, {1}, {ofI,ofEa}, "BCLR",{0,EA_Immed|EA_PCRel|EA_An}},
1357: { MC_ALL, {0xffc0, 0x08C0}, {1}, {ofI,ofEa}, "BSET",{0,EA_Immed|EA_PCRel|EA_An}},
1358: { MC_ALL, {0xff00, 0x0A00}, {-1,6,2,0}, {ofI,ofEa}, "EORI.?",{0,EA_Immed|EA_PCRel|EA_An}},
1359: { MC_ALL, {0xff00, 0x0C00}, {-1,6,2,0}, {ofI,ofEa}, "CMPI.?",{0,EA_Immed|EA_An}},
1360: { MC_ALL, {0xffff, 0x003C}, {1}, {ofEa,ofSpecReg}, "ORI",{0,REG_CCR} },
1361: { MC_ALL, {0xffff, 0x007C}, {2}, {ofEa,ofSpecReg}, "ORI",{0,REG_SR} },
1362: { MC_ALL, {0xffff, 0x023C}, {1}, {ofEa,ofSpecReg}, "ANDI",{0,REG_CCR} },
1363: { MC_ALL, {0xffff, 0x027C}, {2}, {ofEa,ofSpecReg}, "ANDI",{0,REG_SR} },
1364: { MC_ALL, {0xffff, 0x0A3C}, {1}, {ofEa,ofSpecReg}, "EORI",{0,REG_CCR} },
1365: { MC_ALL, {0xffff, 0x0A7C}, {2}, {ofEa,ofSpecReg}, "EORI",{0,REG_SR} },
1366: { MC68020, {0xffc0, 0x06C0}, {1}, {ofEa}, "CALLM",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1367: { MC68020, {0xfff0, 0x06C0}, {1}, {ofEa}, "RTM"},
1368: { MC_020, {0xf9c0, 0x00C0, 0x0fff,0x0000}, {-1,9,2,0}, {ofEa,ofExtReg}, "CMP2.?",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1369: { MC_020, {0xf9c0, 0x00C0, 0x0fff,0x0800}, {-1,9,2,0}, {ofEa,ofExtReg}, "CHK2.?",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1370: { MC_020&~MC_CPU32, {0xffc0, 0x0AC0, 0xFE38,0x0000}, {1}, {ofCAS,ofEa}, "CAS.B",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1371: { MC_020&~MC_CPU32, {0xffc0, 0x0CC0, 0xFE38,0x0000}, {2}, {ofCAS,ofEa}, "CAS.W",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1372: { MC_020&~MC_CPU32, {0xffc0, 0x0EC0, 0xFE38,0x0000}, {4}, {ofCAS,ofEa}, "CAS.L",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1373: { MC_020&~MC_CPU32, {0xffff, 0x0CFC, 0x0E38,0x0000, 0x0E38,0x0000}, {2}, {ofCAS2}, "CAS2.W"},
1374: { MC_020&~MC_CPU32, {0xffff, 0x0EFC, 0x0E38,0x0000, 0x0E38,0x0000}, {4}, {ofCAS2}, "CAS2.L"},
1375: { MC68010|MC_020, {0xff00, 0x0e00, 0x0fff,0x0000}, {-1,6,2,0}, {ofEa,ofExtReg}, "MOVES.?",{EA_Immed|EA_PCRel|EA_An|EA_Dn,0}},
1376: { MC68010|MC_020, {0xff00, 0x0e00, 0x0fff,0x0800}, {-1,6,2,0}, {ofExtReg,ofEa}, "MOVES.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1377:
1378: { MC_ALL, {0xf000, 0x1000}, {1}, {ofEa,ofDestEa6}, "MOVE.B"},
1379:
1380: { MC_ALL, {0xf000, 0x2000}, {4}, {ofEa,ofDestEa6}, "MOVE.L"},
1381: { MC_ALL, {0xf1c0, 0x2040}, {4}, {ofEa,ofDestAn}, "MOVEA.L",{0},1},
1382:
1383: { MC_ALL, {0xf000, 0x3000}, {2}, {ofEa,ofDestEa6}, "MOVE.W"},
1384: { MC_ALL, {0xf1c0, 0x3040}, {2}, {ofEa,ofDestAn}, "MOVEA.W",{0},1},
1385:
1386: { MC_ALL, {0xff00, 0x4000}, {-1,6,2,0}, {ofEa}, "NEGX.?",{EA_Immed|EA_PCRel|EA_An}},
1387: { MC_020, {0xf1c0, 0x4100}, {4}, {ofEa,ofDestDn}, "CHK.L", {EA_An,0}},
1388: { MC_ALL, {0xf1c0, 0x4180}, {2}, {ofEa,ofDestDn}, "CHK.W", {EA_An,0}},
1389: { MC_ALL, {0xf1c0, 0x41c0}, {4}, {ofEa,ofDestAn}, "LEA",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn,0},1 },
1390: { MC_ALL, {0xff00, 0x4200}, {-1,6,2,0}, {ofEa}, "CLR.?",{EA_Immed|EA_PCRel|EA_An}},
1391: { MC_ALL, {0xff00, 0x4400}, {-1,6,2,0}, {ofEa}, "NEG.?",{EA_Immed|EA_PCRel|EA_An}},
1392: { MC_ALL, {0xff00, 0x4600}, {-1,6,2,0}, {ofEa}, "NOT.?",{EA_Immed|EA_PCRel|EA_An}},
1393: { MC_ALL, {0xffc0, 0x40c0}, {2}, {ofSpecReg,ofEa}, "MOVE",{REG_SR,EA_Immed|EA_PCRel|EA_An} },
1394: { MC_ALL, {0xffc0, 0x42c0}, {1}, {ofSpecReg,ofEa}, "MOVE",{REG_CCR,EA_Immed|EA_PCRel|EA_An} },
1395: { MC_ALL, {0xffc0, 0x44c0}, {1}, {ofEa,ofSpecReg}, "MOVE",{EA_An,REG_CCR} },
1396: { MC_ALL, {0xffc0, 0x46c0}, {2}, {ofEa,ofSpecReg}, "MOVE",{EA_An,REG_SR} },
1397: { MC_ALL, {0xffc0, 0x4800}, {1}, {ofEa}, "NBCD",{EA_Immed|EA_PCRel|EA_An}},
1398: { MC_020, {0xfff8, 0x4808}, {4}, {ofEa,ofI}, "LINK.L"},
1399: { MC_ALL, {0xffc0, 0x4840}, {0}, {ofEa}, "PEA",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn},1 },
1400: { MC_ALL, {0xfff8, 0x4840}, {4}, {ofEa}, "SWAP"},
1401: { MC68010|MC_020, {0xfff8, 0x4848}, {0}, {ofIOpcode}, "BKPT",{0x07} },
1402: { MC_ALL, {0xffc0, 0x4880, 0x10000}, {2}, {ofRegList,ofEa}, "MOVEM.W",{0,EA_Dn|EA_An|EA_Immed|EA_Anip|EA_PCRel} },
1403: { MC_ALL, {0xffc0, 0x48c0, 0x10000}, {4}, {ofRegList,ofEa}, "MOVEM.L",{0,EA_Dn|EA_An|EA_Immed|EA_Anip|EA_PCRel} },
1404: { MC_ALL, {0xfff8, 0x4880}, {2}, {ofEa}, "EXT.W"},
1405: { MC_ALL, {0xfff8, 0x48c0}, {4}, {ofEa}, "EXT.L"},
1406: { MC_020, {0xfff8, 0x49c0}, {4}, {ofEa}, "EXTB.L"},
1407: { MC_ALL, {0xff00, 0x4a00}, {-1,6,2,0}, {ofEa}, "TST.?"},
1408: { MC_ALL, {0xffc0, 0x4ac0}, {1}, {ofEa}, "TAS",{EA_Immed|EA_PCRel|EA_An}},
1409: { MC_CPU32, {0xffff, 0x4afa}, {0}, {ofNone}, "BGND"},
1410: { MC_ALL, {0xffff, 0x4afc}, {0}, {ofNone}, "ILLEGAL"},
1411: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0000}, {4}, {ofEa,ofExtReg}, "MULU.L", {EA_An,0}},
1412: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0800}, {4}, {ofEa,ofExtReg}, "MULS.L", {EA_An,0}},
1413: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0000}, {4}, {ofEa,ofExtReg}, "DIVU.L", {EA_An,0}},
1414: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0800}, {4}, {ofEa,ofExtReg}, "DIVS.L", {EA_An,0}},
1415: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0400}, {4}, {ofEa,ofExtReg,ofExtReg0}, "MULU.L", {EA_An,0,0}},
1416: { MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0c00}, {4}, {ofEa,ofExtReg,ofExtReg0}, "MULS.L", {EA_An,0,0}},
1417: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0400}, {4}, {ofEa,ofExtReg,ofExtReg0}, "DIVU.L", {EA_An,0,0}},
1418: { MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0c00}, {4}, {ofEa,ofExtReg,ofExtReg0}, "DIVS.L", {EA_An,0,0}},
1419: { MC_ALL, {0xffc0, 0x4c80, 0x10000}, {2}, {ofEa,ofRegList}, "MOVEM.W",{EA_Dn|EA_An|EA_Immed|EA_piAn,0} },
1420: { MC_ALL, {0xffc0, 0x4cc0, 0x10000}, {4}, {ofEa,ofRegList}, "MOVEM.L",{EA_Dn|EA_An|EA_Immed|EA_piAn,0} },
1421: { MC_ALL, {0xfff0, 0x4e40}, {0}, {ofIOpcode}, "TRAP",{0x0f} },
1422: { MC_ALL, {0xfff8, 0x4e50}, {2}, {ofAn,ofI}, "LINK"},
1423: { MC_ALL, {0xfff8, 0x4e58}, {4}, {ofAn}, "UNLK"},
1424: { MC_ALL, {0xfff8, 0x4e60}, {4}, {ofAn,ofSpecReg}, "MOVE",{0,REG_USP} },
1425: { MC_ALL, {0xfff8, 0x4e68}, {4}, {ofSpecReg,ofAn}, "MOVE",{REG_USP,0} },
1426: { MC_ALL, {0xffff, 0x4e70}, {0}, {ofNone}, "RESET"},
1427: { MC_ALL, {0xffff, 0x4e71}, {0}, {ofNone}, "NOP"},
1428: { MC_ALL, {0xffff, 0x4e72}, {2}, {ofI}, "STOP"},
1429: { MC_ALL, {0xffff, 0x4e73}, {0}, {ofNone}, "RTE"},
1430: { MC68010|MC_020, {0xffff, 0x4e74}, {2}, {ofI}, "RTD"},
1431: { MC_ALL, {0xffff, 0x4e75}, {0}, {ofNone}, "RTS"},
1432: { MC_ALL, {0xffff, 0x4e76}, {0}, {ofNone}, "TRAPV"},
1433: { MC_ALL, {0xffff, 0x4e77}, {0}, {ofNone}, "RTR"},
1434: { MC68010|MC_020, {0xffff, 0x4e7a, 0x10000}, {4}, {ofSpecExtReg,ofExtReg}, "MOVEC"},
1435: { MC68010|MC_020, {0xffff, 0x4e7b, 0x10000}, {4}, {ofExtReg,ofSpecExtReg}, "MOVEC"},
1436: { MC_ALL, {0xffc0, 0x4e80}, {0}, {ofEa}, "JSR",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1437: { MC_ALL, {0xffc0, 0x4ec0}, {0}, {ofEa}, "JMP",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
1438:
1439: { MC_ALL, {0xf1c0, 0x5000}, {1}, {ofI3,ofEa}, "ADDQ.B",{0,EA_An|EA_Immed|EA_PCRel} },
1440: { MC_ALL, {0xf1c0, 0x5040}, {2}, {ofI3,ofEa}, "ADDQ.W",{0,EA_Immed|EA_PCRel} },
1441: { MC_ALL, {0xf1c0, 0x5080}, {4}, {ofI3,ofEa}, "ADDQ.L",{0,EA_Immed|EA_PCRel} },
1442: { MC_ALL, {0xf0c0, 0x50C0}, {1}, {ofEa}, "Sci",{EA_Immed|EA_PCRel|EA_An}},
1443: { MC_ALL, {0xf0f8, 0x50C8}, {2}, {ofDn,ofDisp}, "DBcd"},
1444: { MC_020, {0xf0ff, 0x50fa}, {2}, {ofI}, "TRAPci.W"},
1445: { MC_020, {0xf0ff, 0x50fb}, {4}, {ofI}, "TRAPci.L"},
1446: { MC_020, {0xf0ff, 0x50fc}, {0}, {ofNone}, "TRAPci"},
1447: { MC_ALL, {0xf1c0, 0x5100}, {1}, {ofI3,ofEa}, "SUBQ.B",{0,EA_An|EA_Immed|EA_PCRel} },
1448: { MC_ALL, {0xf1c0, 0x5140}, {2}, {ofI3,ofEa}, "SUBQ.W",{0,EA_Immed|EA_PCRel} },
1449: { MC_ALL, {0xf1c0, 0x5180}, {4}, {ofI3,ofEa}, "SUBQ.L",{0,EA_Immed|EA_PCRel} },
1450:
1451: { MC_ALL, {0xf0ff, 0x6000}, {2}, {ofDisp}, "Bcb"},
1452: { MC_ALL, {0xf000, 0x6000}, {1}, {ofDisp}, "Bcb.S"},
1453: { MC_020, {0xf0ff, 0x60FF}, {4}, {ofDisp}, "Bcb.L"},
1454:
1455: { MC_ALL, {0xf100, 0x7000}, {0}, {ofIOpcode,ofDestDn}, "MOVEQ", {0xFF,0}},
1456:
1457: { MC_ALL, {0xf100, 0x8000}, {-1,6,2,0}, {ofEa,ofDestDn}, "OR.?", {EA_An,0}},
1458: { MC_ALL, {0xf100, 0x8100}, {-1,6,2,0}, {ofDestDn,ofEa}, "OR.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1459: { MC_ALL, {0xf1f8, 0x8100}, {1}, {ofDn,ofDestDn}, "SBCD"},
1460: { MC_ALL, {0xf1f8, 0x8108}, {1}, {ofPiAn,ofDestPiAn}, "SBCD"},
1461: { MC_020&~MC_CPU32, {0xf1f8, 0x8140, 0x10000}, {0}, {ofDn,ofDestDn,ofExtIm}, "PACK"},
1462: { MC_020&~MC_CPU32, {0xf1f8, 0x8148, 0x10000}, {0}, {ofPiAn,ofDestPiAn,ofExtIm}, "PACK"},
1463: { MC_020&~MC_CPU32, {0xf1f8, 0x8180, 0x10000}, {0}, {ofDn,ofDestDn,ofExtIm}, "UNPK"},
1464: { MC_020&~MC_CPU32, {0xf1f8, 0x8188, 0x10000}, {0}, {ofPiAn,ofDestPiAn,ofExtIm}, "UNPK"},
1465: { MC_ALL, {0xf1c0, 0x80c0}, {2}, {ofEa,ofDestDn}, "DIVU.W", {EA_An,0}},
1466: { MC_ALL, {0xf1c0, 0x81c0}, {2}, {ofEa,ofDestDn}, "DIVS.W", {EA_An,0}},
1467:
1468: { MC_ALL, {0xf1c0, 0x9000}, {1}, {ofEa,ofDestDn}, "SUB.B", {EA_An,0}},
1469: { MC_ALL, {0xf1c0, 0x9040}, {2}, {ofEa,ofDestDn}, "SUB.W"},
1470: { MC_ALL, {0xf1c0, 0x9080}, {4}, {ofEa,ofDestDn}, "SUB.L"},
1471: { MC_ALL, {0xf1c0, 0x90c0}, {2}, {ofEa,ofDestAn}, "SUBA.W"},
1472: { MC_ALL, {0xf1c0, 0x91c0}, {4}, {ofEa,ofDestAn}, "SUBA.L"},
1473: { MC_ALL, {0xf100, 0x9100}, {-1,6,2,0}, {ofDestDn,ofEa}, "SUB.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1474: { MC_ALL, {0xf138, 0x9100}, {-1,6,2,0}, {ofDn,ofDestDn}, "SUBX.?"},
1475: { MC_ALL, {0xf138, 0x9108}, {-1,6,2,0}, {ofPiAn,ofDestPiAn}, "SUBX.?"},
1476:
1477: { MC_ALL, {0xf000, 0xa000}, {0}, {ofLineA}, "LINEA"},
1478:
1479: { MC_ALL, {0xf1c0, 0xb000}, {1}, {ofEa,ofDestDn}, "CMP.B", {EA_An,0}},
1480: { MC_ALL, {0xf1c0, 0xb040}, {2}, {ofEa,ofDestDn}, "CMP.W"},
1481: { MC_ALL, {0xf1c0, 0xb080}, {4}, {ofEa,ofDestDn}, "CMP.L"},
1482: { MC_ALL, {0xf1c0, 0xb0c0}, {2}, {ofEa,ofDestAn}, "CMPA.W"},
1483: { MC_ALL, {0xf1c0, 0xb1c0}, {4}, {ofEa,ofDestAn}, "CMPA.L"},
1484: { MC_ALL, {0xf100, 0xb100}, {-1,6,2,0}, {ofDestDn,ofEa}, "EOR.?",{0,EA_An|EA_Immed|EA_PCRel} },
1485: { MC_ALL, {0xf138, 0xb108}, {-1,6,2,0}, {ofAnip,ofDestAnip}, "CMPM.?"},
1486:
1487: { MC_ALL, {0xf100, 0xc000}, {-1,6,2,0}, {ofEa,ofDestDn}, "AND.?", {EA_An,0}},
1488: { MC_ALL, {0xf100, 0xc100}, {-1,6,2,0}, {ofDestDn,ofEa}, "AND.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1489: { MC_ALL, {0xf1f8, 0xc100}, {1}, {ofDn,ofDestDn}, "ABCD"},
1490: { MC_ALL, {0xf1f8, 0xc108}, {1}, {ofPiAn,ofDestPiAn}, "ABCD"},
1491: { MC_ALL, {0xf1f8, 0xc140}, {1}, {ofDestDn,ofDn}, "EXG"},
1492: { MC_ALL, {0xf1f8, 0xc148}, {1}, {ofDestAn,ofAn}, "EXG"},
1493: { MC_ALL, {0xf1f8, 0xc188}, {1}, {ofDestDn,ofAn}, "EXG"},
1494: { MC_ALL, {0xf1c0, 0xc0c0}, {2}, {ofEa,ofDestDn}, "MULU.W", {EA_An,0}},
1495: { MC_ALL, {0xf1c0, 0xc1c0}, {2}, {ofEa,ofDestDn}, "MULS.W", {EA_An,0}},
1496:
1497: { MC_ALL, {0xf1c0, 0xd000}, {1}, {ofEa,ofDestDn}, "ADD.B", {EA_An,0}},
1498: { MC_ALL, {0xf1c0, 0xd040}, {2}, {ofEa,ofDestDn}, "ADD.W"},
1499: { MC_ALL, {0xf1c0, 0xd080}, {4}, {ofEa,ofDestDn}, "ADD.L"},
1500: { MC_ALL, {0xf1c0, 0xd0c0}, {2}, {ofEa,ofDestAn}, "ADDA.W"},
1501: { MC_ALL, {0xf1c0, 0xd1c0}, {4}, {ofEa,ofDestAn}, "ADDA.L"},
1502: { MC_ALL, {0xf100, 0xd100}, {-1,6,2,0}, {ofDestDn,ofEa}, "ADD.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
1503: { MC_ALL, {0xf138, 0xd100}, {-1,6,2,0}, {ofDn,ofDestDn}, "ADDX.?"},
1504: { MC_ALL, {0xf138, 0xd108}, {-1,6,2,0}, {ofPiAn,ofDestPiAn}, "ADDX.?"},
1505:
1506: { MC_ALL, {0xf138, 0xe000}, {-1,6,2,0}, {ofI3,ofDn}, "ASR.?"},
1507: { MC_ALL, {0xf138, 0xe008}, {-1,6,2,0}, {ofI3,ofDn}, "LSR.?"},
1508: { MC_ALL, {0xf138, 0xe010}, {-1,6,2,0}, {ofI3,ofDn}, "ROXR.?"},
1509: { MC_ALL, {0xf138, 0xe018}, {-1,6,2,0}, {ofI3,ofDn}, "ROR.?"},
1510: { MC_ALL, {0xf138, 0xe020}, {-1,6,2,0}, {ofDestDn,ofDn}, "ASR.?"},
1511: { MC_ALL, {0xf138, 0xe028}, {-1,6,2,0}, {ofDestDn,ofDn}, "LSR.?"},
1512: { MC_ALL, {0xf138, 0xe030}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROXR.?"},
1513: { MC_ALL, {0xf138, 0xe038}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROR.?"},
1514: { MC_ALL, {0xf138, 0xe100}, {-1,6,2,0}, {ofI3,ofDn}, "ASL.?"},
1515: { MC_ALL, {0xf138, 0xe108}, {-1,6,2,0}, {ofI3,ofDn}, "LSL.?"},
1516: { MC_ALL, {0xf138, 0xe110}, {-1,6,2,0}, {ofI3,ofDn}, "ROXL.?"},
1517: { MC_ALL, {0xf138, 0xe118}, {-1,6,2,0}, {ofI3,ofDn}, "ROL.?"},
1518: { MC_ALL, {0xf138, 0xe120}, {-1,6,2,0}, {ofDestDn,ofDn}, "ASL.?"},
1519: { MC_ALL, {0xf138, 0xe128}, {-1,6,2,0}, {ofDestDn,ofDn}, "LSL.?"},
1520: { MC_ALL, {0xf138, 0xe130}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROXL.?"},
1521: { MC_ALL, {0xf138, 0xe138}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROL.?"},
1522: { MC_ALL, {0xffc0, 0xe0c0}, {1}, {ofEa}, "ASR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1523: { MC_ALL, {0xffc0, 0xe1c0}, {1}, {ofEa}, "ASL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1524: { MC_ALL, {0xffc0, 0xe2c0}, {1}, {ofEa}, "LSR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1525: { MC_ALL, {0xffc0, 0xe3c0}, {1}, {ofEa}, "LSL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1526: { MC_ALL, {0xffc0, 0xe4c0}, {1}, {ofEa}, "ROXR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1527: { MC_ALL, {0xffc0, 0xe5c0}, {1}, {ofEa}, "ROXL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1528: { MC_ALL, {0xffc0, 0xe6c0}, {1}, {ofEa}, "ROR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1529: { MC_ALL, {0xffc0, 0xe7c0}, {1}, {ofEa}, "ROL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1530: { MC_020&~MC_CPU32, {0xffc0, 0xe8c0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFTST",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1531: { MC_020&~MC_CPU32, {0xffc0, 0xe9c0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFEXTU",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1532: { MC_020&~MC_CPU32, {0xffc0, 0xeac0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFCHG",{EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1533: { MC_020&~MC_CPU32, {0xffc0, 0xebc0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFEXTS",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1534: { MC_020&~MC_CPU32, {0xffc0, 0xecc0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFCLR",{EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1535: { MC_020&~MC_CPU32, {0xffc0, 0xedc0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFFFO",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1536: { MC_020&~MC_CPU32, {0xffc0, 0xeec0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFSET",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
1537: { MC_020&~MC_CPU32, {0xffc0, 0xefc0, 0x8000, 0x0000}, {1}, {ofExtReg,ofBFEa}, "BFINS",{0,EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
1538:
1539:
1540: #define PMMU_COPROC_ID 0 // 0 is the standard PMMU
1541:
1542: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2000}, {0}, {ofSpecReg,ofEa}, "PLOADW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1543: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2001}, {0}, {ofSpecReg,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1544: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2008}, {0}, {ofExtReg0,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1545: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff0, 0x2010}, {0}, {ofExtIm4,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1546:
1547: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2200}, {0}, {ofSpecReg,ofEa}, "PLOADR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1548: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2201}, {0}, {ofSpecReg,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1549: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2208}, {0}, {ofExtReg0,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1550: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff0, 0x2210}, {0}, {ofExtIm4,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1551:
1552: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0xa000}, {0}, {ofEa}, "PFLUSHR",{EA_Dn|EA_An} },
1553:
1554: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0800}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1555: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0900}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
1.1.1.8 ! root 1556: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0B00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{REG_TT0,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1.1 root 1557: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0C00}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1.1.1.8 ! root 1558: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0C00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{REG_TT0,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1.1 root 1559: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0D00}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
1.1.1.8 ! root 1560: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0E00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{REG_TT1,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
! 1561: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0F00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{REG_TT1,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1.1 root 1562: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4000}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1563: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4100}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
1.1.1.8 ! root 1564: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4200}, {0}, {ofSpecReg,ofEa}, "PMOVE",{REG_TC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
! 1565: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4300}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{REG_TC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1.1 root 1566: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4800}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1567: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4900}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1.1.1.8 ! root 1568: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4A00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{REG_SRP,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
! 1569: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4B00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{REG_SRP,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
1.1 root 1570: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4C00}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1571: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4D00}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
1.1.1.8 ! root 1572: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4e00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{REG_CRP,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
! 1573: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4f00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{REG_CRP,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1.1 root 1574: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x6000}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_MMUSR} },
1.1.1.8 ! root 1575: { MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x6200}, {0}, {ofSpecReg,ofEa}, "PMOVE",{REG_MMUSR,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1.1 root 1576:
1577: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2800}, {0}, {ofSpecReg,ofEa}, "PVALID",{REG_VAL,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1578: { MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2C00}, {0}, {ofExtRegA0,ofEa}, "PVALID",{0,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1579:
1580: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8000}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1581: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8001}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1582: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f8, 0x8008}, {0}, {ofExtReg0,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1583: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f0, 0x8010}, {0}, {ofExtIm4,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1584:
1585: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8200}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1586: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8201}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1587: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f8, 0x8208}, {0}, {ofExtReg0,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1588: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f0, 0x8210}, {0}, {ofExtIm4,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1589:
1590: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8100}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1591: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8101}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1592: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe318, 0x8108}, {0}, {ofExtReg0,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1593: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe310, 0x8110}, {0}, {ofExtIm4,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1594:
1595: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8300}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1596: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8301}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1597: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe318, 0x8308}, {0}, {ofExtReg0,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1598: { MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe310, 0x8310}, {0}, {ofExtIm4,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
1599:
1600: { MC_PMMU, {0xffc0, 0xf040|(PMMU_COPROC_ID<<9), 0xfff0, 0x8310}, {0}, {ofEa}, "PScp",{EA_An|EA_Immed|EA_PCRel} },
1601: { MC_PMMU, {0xfff8, 0xf048|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000}, {2}, {ofDn,ofDisp}, "PDBcp"},
1602: { MC_PMMU, {0xffff, 0xf07A|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {2}, {ofExtIm32}, "PTRAPcp.W" },
1603: { MC_PMMU, {0xffff, 0xf07B|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {4}, {ofExtIm32}, "PTRAPcp.L" },
1604: { MC_PMMU, {0xffff, 0xf07C|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000}, {0}, {ofNone}, "PTRAPcp" },
1605: { MC_PMMU, {0xfff0, 0xf080|(PMMU_COPROC_ID<<9)}, {2}, {ofDisp}, "PBcp.W"},
1606: { MC_PMMU, {0xfff0, 0xf0C0|(PMMU_COPROC_ID<<9)}, {4}, {ofDisp}, "PBcp.L"},
1607: { MC_PMMU, {0xffc0, 0xf100|(PMMU_COPROC_ID<<9)}, {0}, {ofEa}, "PSAVE",{EA_Dn|EA_An|EA_Anip|EA_Immed} },
1608: { MC_PMMU, {0xffc0, 0xf140|(PMMU_COPROC_ID<<9)}, {0}, {ofEa}, "PRESTORE",{EA_Dn|EA_An|EA_piAn|EA_Immed} },
1609:
1610:
1611: #define MC040_COPROC_ID 3 // 3 is the code for some 68040/68060 opcodes
1612:
1613: { MC68040|MC68060, {0xfff8, 0xf000|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAnip,ofDestAbsL}, "MOVE16"},
1614: { MC68040|MC68060, {0xfff8, 0xf008|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofDestAbsL,ofAnip}, "MOVE16"},
1615: { MC68040|MC68060, {0xfff8, 0xf010|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAni,ofDestAbsL}, "MOVE16"},
1616: { MC68040|MC68060, {0xfff8, 0xf018|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofDestAbsL,ofAni}, "MOVE16"},
1617: { MC68040|MC68060, {0xfff8, 0xf020|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAnip,ofExtAnip}, "MOVE16"},
1618:
1619:
1620: #define CPU32_COPROC_ID 4 // 4 is the code for some CPU32 opcodes
1621:
1622: { MC68040|MC68060, {0xfff8, 0xf008|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_NONE} },
1623: { MC68040|MC68060, {0xfff8, 0xf048|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_DC} },
1624: { MC68040|MC68060, {0xfff8, 0xf088|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_IC} },
1625: { MC68040|MC68060, {0xfff8, 0xf0C8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_ICDC} },
1626:
1627: { MC68040|MC68060, {0xfff8, 0xf010|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_NONE} },
1628: { MC68040|MC68060, {0xfff8, 0xf050|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_DC} },
1629: { MC68040|MC68060, {0xfff8, 0xf090|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_IC} },
1630: { MC68040|MC68060, {0xfff8, 0xf0D0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_ICDC} },
1631:
1632: { MC68040|MC68060, {0xfff8, 0xf018|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_NONE} },
1633: { MC68040|MC68060, {0xfff8, 0xf058|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_DC} },
1634: { MC68040|MC68060, {0xfff8, 0xf098|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_IC} },
1635: { MC68040|MC68060, {0xfff8, 0xf0D8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_ICDC} },
1636:
1637: { MC68040|MC68060, {0xfff8, 0xf028|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_NONE} },
1638: { MC68040|MC68060, {0xfff8, 0xf068|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_DC} },
1639: { MC68040|MC68060, {0xfff8, 0xf0A8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_IC} },
1640: { MC68040|MC68060, {0xfff8, 0xf0E8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_ICDC} },
1641:
1642: { MC68040|MC68060, {0xfff8, 0xf030|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_NONE} },
1643: { MC68040|MC68060, {0xfff8, 0xf070|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_DC} },
1644: { MC68040|MC68060, {0xfff8, 0xf0B0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_IC} },
1645: { MC68040|MC68060, {0xfff8, 0xf0F0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_ICDC} },
1646:
1647: { MC68040|MC68060, {0xfff8, 0xf038|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_NONE} },
1648: { MC68040|MC68060, {0xfff8, 0xf078|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_DC} },
1649: { MC68040|MC68060, {0xfff8, 0xf0B8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_IC} },
1650: { MC68040|MC68060, {0xfff8, 0xf0F8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_ICDC} },
1651:
1652: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f08, 0x0100}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLU.?" },
1653: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0100}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLU.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1654: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f28, 0x0500}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLUN.?" },
1655: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0500}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLUN.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1656:
1657: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f08, 0x0900}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLS.?" },
1658: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0900}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLS.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1659: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f28, 0x0D00}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLSN.?" },
1660: { MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0D00}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLSN.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1661:
1662: { MC_CPU32, {0xffff, 0xf000|(CPU32_COPROC_ID<<9), 0xffff, 0x01C0}, {2}, {ofI}, "LPSTOP" },
1663:
1664:
1665: #define FPU_COPROC_ID 1 // 1 is the standard FPU, required to be 1 for the 68040 anyway
1666:
1667: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0000}, {-1,16+10,3,1}, {ofFPU}, "FMOVE.?" },
1668: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0001}, {-1,16+10,3,1}, {ofFPU}, "FINT.?" },
1669: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0002}, {-1,16+10,3,1}, {ofFPU}, "FSINH.?" },
1670: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0003}, {-1,16+10,3,1}, {ofFPU}, "FINTRZ.?" },
1671: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0004}, {-1,16+10,3,1}, {ofFPU}, "FSQRT.?" },
1672: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0006}, {-1,16+10,3,1}, {ofFPU}, "FLOGNP1.?" },
1673: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0008}, {-1,16+10,3,1}, {ofFPU}, "FETOXM1.?" },
1674: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0009}, {-1,16+10,3,1}, {ofFPU}, "FTANH.?" },
1675: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000A}, {-1,16+10,3,1}, {ofFPU}, "FATAN.?" },
1676: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000C}, {-1,16+10,3,1}, {ofFPU}, "FASIN.?" },
1677: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000D}, {-1,16+10,3,1}, {ofFPU}, "FATANH.?" },
1678: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000E}, {-1,16+10,3,1}, {ofFPU}, "FSIN.?" },
1679: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000F}, {-1,16+10,3,1}, {ofFPU}, "FTAN.?" },
1680: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0010}, {-1,16+10,3,1}, {ofFPU}, "FETOX.?" },
1681: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0011}, {-1,16+10,3,1}, {ofFPU}, "FTWOTOX.?" },
1682: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0012}, {-1,16+10,3,1}, {ofFPU}, "FTENTOX.?" },
1683: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0014}, {-1,16+10,3,1}, {ofFPU}, "FLOGN.?" },
1684: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0015}, {-1,16+10,3,1}, {ofFPU}, "FLOG10.?" },
1685: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0016}, {-1,16+10,3,1}, {ofFPU}, "FLOG2.?" },
1686: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0018}, {-1,16+10,3,1}, {ofFPU}, "FABS.?" },
1687: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0019}, {-1,16+10,3,1}, {ofFPU}, "FCOSH.?" },
1688: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001A}, {-1,16+10,3,1}, {ofFPU}, "FNEG.?" },
1689: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001C}, {-1,16+10,3,1}, {ofFPU}, "FACOS.?" },
1690: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001D}, {-1,16+10,3,1}, {ofFPU}, "FCOS.?" },
1691: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001E}, {-1,16+10,3,1}, {ofFPU}, "FGETEXP.?" },
1692: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001F}, {-1,16+10,3,1}, {ofFPU}, "FGETMAN.?" },
1693: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0020}, {-1,16+10,3,1}, {ofFPU}, "FDIV.?" },
1694: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0021}, {-1,16+10,3,1}, {ofFPU}, "FMOD.?" },
1695: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0022}, {-1,16+10,3,1}, {ofFPU}, "FADD.?" },
1696: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0023}, {-1,16+10,3,1}, {ofFPU}, "FMUL.?" },
1697: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0024}, {-1,16+10,3,1}, {ofFPU}, "FSGLDIV.?" },
1698: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0025}, {-1,16+10,3,1}, {ofFPU}, "FREM.?" },
1699: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0026}, {-1,16+10,3,1}, {ofFPU}, "FSCALE.?" },
1700: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0027}, {-1,16+10,3,1}, {ofFPU}, "FSGLMUL.?" },
1701: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0028}, {-1,16+10,3,1}, {ofFPU}, "FSUB.?" },
1702: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA078,0x0030}, {-1,16+10,3,1}, {ofFPU3Reg}, "FSINCOS.?" },
1703: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0038}, {-1,16+10,3,1}, {ofFPU}, "FCMP.?" },
1704: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x003A}, {-1,16+10,3,1}, {ofFPU}, "FTST.?" },
1705: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0040}, {-1,16+10,3,1}, {ofFPU}, "FSMOVE.?" },
1706: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0041}, {-1,16+10,3,1}, {ofFPU}, "FSSQRT.?" },
1707: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0042}, {-1,16+10,3,1}, {ofFPU}, "FSADD.?" },
1708: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0044}, {-1,16+10,3,1}, {ofFPU}, "FDMOVE.?" },
1709: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0045}, {-1,16+10,3,1}, {ofFPU}, "FDSQRT.?" },
1710: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0046}, {-1,16+10,3,1}, {ofFPU}, "FDADD.?" },
1711: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0058}, {-1,16+10,3,1}, {ofFPU}, "FSABS.?" },
1712: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005A}, {-1,16+10,3,1}, {ofFPU}, "FSNEG.?" },
1713: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005C}, {-1,16+10,3,1}, {ofFPU}, "FDABS.?" },
1714: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005E}, {-1,16+10,3,1}, {ofFPU}, "FDNEG.?" },
1715: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0060}, {-1,16+10,3,1}, {ofFPU}, "FSDIV.?" },
1716: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0063}, {-1,16+10,3,1}, {ofFPU}, "FSMUL.?" },
1717: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0064}, {-1,16+10,3,1}, {ofFPU}, "FDDIV.?" },
1718: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0067}, {-1,16+10,3,1}, {ofFPU}, "FDMUL.?" },
1719: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0068}, {-1,16+10,3,1}, {ofFPU}, "FSSUB.?" },
1720: { MC68040, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x006C}, {-1,16+10,3,1}, {ofFPU}, "FDSUB.?" },
1721: { MC68040|MC_FPU, {0xffff, 0xf000|(FPU_COPROC_ID<<9),0xFC00,0x5C00}, {0}, {ofFMOVECR}, "FMOVECR" },
1722:
1723: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE000,0x6000}, {-1,16+10,3,1}, {ofFPUMOVE}, "FMOVE.?" },
1724:
1725: // these 3 are special versions of MOVEM with just one register, they have to be before the FMOVEM version
1726: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x8400}, {0}, {ofEa,ofSpecReg}, "FMOVE", {0,REG_FPU_FPIAR} },
1727: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x8800}, {0}, {ofEa,ofSpecReg}, "FMOVE", {EA_An,REG_FPU_FPSR} },
1728: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x9000}, {0}, {ofEa,ofSpecReg}, "FMOVE", {EA_An,REG_FPU_FPCR} },
1729: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE3FF,0x8000}, {0}, {ofEa,ofFPUSRRegList}, "FMOVEM", {EA_Dn|EA_An,0} },
1730: // these 3 are special versions of MOVEM with just one register, they have to be before the FMOVEM version
1731: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xA400}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPIAR,EA_Immed|EA_PCRel} },
1732: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xA800}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPSR,EA_An|EA_Immed|EA_PCRel} },
1733: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xB000}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPCR,EA_An|EA_Immed|EA_PCRel} },
1734: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE3FF,0xA000}, {0}, {ofFPUSRRegList,ofEa}, "FMOVEM", {0,EA_Dn|EA_An|EA_Immed|EA_PCRel} },
1735:
1736: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE00,0xC000}, {0}, {ofFPUReglist,ofEa}, "FMOVEM.X",{0,EA_Dn|EA_An|EA_Anip|EA_Immed} },
1737: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE8F,0xC800}, {0}, {ofExtRegD04,ofEa}, "FMOVEM.X",{0,EA_Dn|EA_An|EA_piAn|EA_Immed} },
1738: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE00,0xE000}, {0}, {ofEa,ofFPUReglist}, "FMOVEM.X",{EA_Dn|EA_An|EA_piAn|EA_Immed,0} },
1739: { MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE8F,0xE800}, {0}, {ofEa,ofExtRegD04}, "FMOVEM.X",{EA_Dn|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
1740:
1741: { MC68040|MC_FPU, {0xffc0, 0xf040|(FPU_COPROC_ID<<9),0xFFC0,0x0000}, {0}, {ofEa}, "FScf.B",{EA_An|EA_Immed|EA_PCRel} },
1742: { MC68040|MC_FPU, {0xfff8, 0xf048|(FPU_COPROC_ID<<9),0xFFC0,0x0000}, {2}, {ofDn,ofDisp}, "FDBcf" },
1743: { MC68040|MC_FPU, {0xffff, 0xf07A|(FPU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {2}, {ofExtIm32}, "FTRAPcf.W" },
1744: { MC68040|MC_FPU, {0xffff, 0xf07B|(FPU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {4}, {ofExtIm32}, "FTRAPcf.L" },
1745: { MC68040|MC_FPU, {0xffff, 0xf07C|(FPU_COPROC_ID<<9), 0xfff0, 0x0000}, {0}, {ofNone}, "FTRAPcf" },
1746:
1747: // FNOP _has_ to be before FBcf.W, not worth to have a special case for that one
1748: { MC68040|MC_FPU, {0xffff, 0xf080|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {0}, {ofNone}, "FNOP" },
1749: { MC68040|MC_FPU, {0xffc0, 0xf080|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {2}, {ofDisp}, "FBcF.W" },
1750: { MC68040|MC_FPU, {0xffc0, 0xf0c0|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {4}, {ofDisp}, "FBcF.L" },
1751: { MC68040|MC68060|MC_FPU, {0xffc0, 0xf100|(FPU_COPROC_ID<<9)}, {0}, {ofEa}, "FSAVE", {EA_Dn|EA_An|EA_piAn|EA_Immed} },
1752: { MC68040|MC68060|MC_FPU, {0xffc0, 0xf140|(FPU_COPROC_ID<<9)}, {0}, {ofEa}, "FRESTORE", {EA_Dn|EA_An|EA_piAn|EA_Immed} },
1753:
1.1.1.4 root 1754: { 0 }
1.1 root 1755: };
1756:
1757: static int Disass68k(long addr, char *labelBuffer, char *opcodeBuffer, char *operandBuffer, char *commentBuffer)
1758: {
1759: long baseAddr = addr;
1.1.1.4 root 1760: int i;
1761: int count = 0;
1762: char addressLabel[256];
1763: char cmtBuffer[256];
1764: Disass68kDataType type;
1765: int index;
1766: long opcodeAddr;
1767:
1.1 root 1768: labelBuffer[0] = 0;
1769: opcodeBuffer[0] = 0;
1770: operandBuffer[0] = 0;
1771: commentBuffer[0] = 0;
1772:
1.1.1.4 root 1773: type = Disass68kType(baseAddr, addressLabel, cmtBuffer, &count);
1.1 root 1774: if(addressLabel[0])
1775: sprintf(labelBuffer, "%s:", addressLabel);
1776: sprintf(commentBuffer, "%s", cmtBuffer);
1777: switch(type)
1778: {
1.1.1.4 root 1779: case dtByte:
1780: if(count > 8)
1781: count = 8;
1782: strcpy(opcodeBuffer,"DC.B");
1783: for (i = 0; i < count; ++i)
1784: {
1785: char hbuf[16];
1786: unsigned short val;
1787:
1788: if((i & 7) > 0)
1789: strcat(operandBuffer, ",");
1790: val = Disass68kGetWord(addr+(i & ~1));
1791: if(i & 1)
1792: val &= 0xFF;
1793: else
1794: val = val >> 8;
1795: sprintf(hbuf,"$%2.2x", val);
1796: strcat(operandBuffer, hbuf);
1797: }
1798: return count;
1799:
1800: case dtWord:
1801: if(count > 4)
1802: count = 4;
1803: strcpy(opcodeBuffer,"DC.W");
1804: for (i = 0; i < count; ++i)
1805: {
1806: char hbuf[16];
1807: if((i & 3) > 0)
1808: strcat(operandBuffer, ",");
1809: sprintf(hbuf,"$%4.4x", Disass68kGetWord(addr+i*2));
1810: strcat(operandBuffer, hbuf);
1811: }
1812: return count * 2;
1813:
1814: case dtLong:
1815: if(count > 2)
1816: count = 2;
1817: strcpy(opcodeBuffer,"DC.L");
1818: for (i = 0; i < count; ++i)
1819: {
1820: char hbuf[16];
1821: if((i & 1) > 0)
1822: strcat(operandBuffer, ",");
1823: sprintf(hbuf,"$%8.8x", (Disass68kGetWord(addr+i*4) << 16) | Disass68kGetWord(addr+i*4+2));
1824: strcat(operandBuffer, hbuf);
1825: }
1826: return count * 4;
1.1 root 1827:
1828: case dtStringArray:
1.1.1.4 root 1829: {
1830: char *sp;
1831: strcpy(opcodeBuffer,"DC.B");
1832: strcat(operandBuffer, "'");
1833: sp = operandBuffer + strlen(operandBuffer);
1834: for (i = 0; i < count; ++i)
1835: {
1836: unsigned short val = Disass68kGetWord(addr+(i & ~1));
1837: if(i & 1)
1838: val &= 0xFF;
1839: else
1840: val = val >> 8;
1841: if(val == 0)
1842: break;
1843: switch(val)
1844: {
1845: case 9: *sp++ = '\\'; *sp++ = 't'; break;
1846: case 10: *sp++ = '\\'; *sp++ = 'n'; break;
1847: case 13: *sp++ = '\\'; *sp++ = 'r'; break;
1848: default:
1849: if(val >= 0x20 && val <= 0x7E)
1850: *sp++ = val;
1851: }
1852: }
1853: *sp = 0;
1854: strcat(sp, "'");
1855: return count;
1856: }
1.1 root 1857:
1858: case dtASCString:
1.1.1.4 root 1859: {
1.1.1.7 root 1860: unsigned short opcval = Disass68kGetWord(addr+0);
1861: count = 1;
1.1.1.4 root 1862: strcpy(opcodeBuffer,"DC.B");
1.1.1.7 root 1863: if ((opcval >> 8) == 0)
1.1.1.4 root 1864: {
1865: strcat(operandBuffer, "0");
1866: } else {
1867: char *sp;
1868: strcat(operandBuffer, "'");
1869: sp = operandBuffer + strlen(operandBuffer);
1870: for(i=0; ; ++i)
1871: {
1872: unsigned short val = Disass68kGetWord(addr+(i & ~1));
1873: if(i & 1)
1874: val &= 0xFF;
1875: else
1876: val = val >> 8;
1877: if(val == 0)
1878: break;
1879: switch(val)
1.1 root 1880: {
1.1.1.4 root 1881: case 9: *sp++ = '\\'; *sp++ = 't'; break;
1882: case 10: *sp++ = '\\'; *sp++ = 'n'; break;
1883: case 13: *sp++ = '\\'; *sp++ = 'r'; break;
1884: default:
1885: if(val >= 0x20 && val <= 0x7E)
1886: *sp++ = val;
1.1 root 1887: }
1.1.1.4 root 1888: ++count;
1889: }
1890: *sp = 0;
1891: strcat(sp, "',0");
1892: }
1893: return (count + 1) & ~1;
1894: }
1.1 root 1895:
1896: case dtPointer:
1897: case dtFunctionPointer:
1.1.1.4 root 1898: {
1899: const char *sp;
1.1.1.7 root 1900: int val;
1.1.1.4 root 1901: val = (Disass68kGetWord(addr) << 16) | Disass68kGetWord(addr+2);
1902: sp = Disass68kSymbolName(val, 2);
1903: strcpy(opcodeBuffer,"DC.L");
1904: if(sp)
1905: sprintf(operandBuffer,"%s", sp);
1906: else
1.1.1.6 root 1907: sprintf(operandBuffer,"$%8.8x", val);
1.1.1.4 root 1908: return 4;
1909: }
1.1 root 1910:
1911: default: break;
1912: }
1913:
1.1.1.4 root 1914: index = 0;
1915: opcodeAddr = addr;
1.1 root 1916: more:
1917: addr = opcodeAddr;
1918:
1919: opcodeBuffer[0] = 0;
1920: operandBuffer[0] = 0;
1921:
1922: commentBuffer[0] = 0;
1923: if(cmtBuffer[0])
1924: sprintf(commentBuffer, "%s ", cmtBuffer);
1925:
1926: while(1)
1927: {
1.1.1.4 root 1928: unsigned short opcode[5];
1.1 root 1929: OpcodeTableStruct *ots = &OpcodeTable[index++];
1.1.1.4 root 1930: int size;
1931: char sizeChar = 0;
1932: char *dbuf;
1933: int ea;
1.1.1.7 root 1934: int maxop;
1.1.1.4 root 1935:
1.1 root 1936: if(ots->opcodeName == NULL)
1937: break;
1938: if((ots->cpuMask & optionCPUTypeMask) == 0) // CPU doesn't match?
1939: continue;
1940:
1941: // search for the opcode plus up to 2 extension words
1942: for(i=0; i<5; ++i)
1943: {
1944: if(!ots->opcodeMask[i*2])
1.1.1.4 root 1945: {
1946: opcode[i] = 0;
1.1 root 1947: break;
1.1.1.4 root 1948: }
1.1 root 1949: opcode[i] = Disass68kGetWord(addr);
1950: if(((ots->opcodeMask[i*2] & 0xFFFF) & opcode[i]) != ots->opcodeMask[i*2+1])
1951: goto more;
1952: addr += 2;
1953: }
1954:
1955: // find out the size of the opcode operand
1.1.1.4 root 1956: size = ots->operationSize[0];
1.1 root 1957: if(size < 0) // custom size?
1958: {
1959: int opcodeOffset = ots->operationSize[1] >> 4;
1960: int bitShiftOffset = ots->operationSize[1] & 0x0F;
1961: int sizeBitMask = (opcode[opcodeOffset] >> bitShiftOffset) & ((1 << ots->operationSize[2]) - 1);
1962: switch(ots->operationSize[3])
1963: {
1964: case 0: // 2 Bit Size
1965: switch(sizeBitMask)
1966: {
1967: case 0: size = 1; sizeChar = 'B'; break;
1968: case 1: size = 2; sizeChar = 'W'; break;
1969: case 2: size = 4; sizeChar = 'L'; break;
1970: case 3: goto more; // illegal size mask
1971: }
1972: break;
1973: case 1: // 3 Bit FPU Size
1974: if((opcode[1] & 0x4000) == 0x0000) // Register => Register?
1975: sizeBitMask = 2; // => 'X' Format
1976: switch(sizeBitMask)
1977: {
1978: case 0: size = 4; sizeChar = 'L'; break;
1979: case 1: size = 4; sizeChar = 'S'; break;
1980: case 2: size = 12; sizeChar = 'X'; break;
1981: case 7: if((opcode[1] & 0xE000) != 0x6000) // MOVE.P <ea>,FPn{Dn-Factor}
1982: goto more; // illegal size mask
1983: case 3: size = 12; sizeChar = 'P'; break;
1984: case 4: size = 2; sizeChar = 'W'; break;
1985: case 5: size = 8; sizeChar = 'D'; break;
1986: case 6: size = 1; sizeChar = 'B'; break;
1987: }
1988: break;
1989: }
1990: }
1991:
1992: // copy the opcode plus a necessary TAB for the operand
1.1.1.4 root 1993: dbuf = opcodeBuffer;
1.1 root 1994: for(i=0; ots->opcodeName[i]; ++i)
1995: {
1996: char c = ots->opcodeName[i];
1997: if(c == 'c') // condition code
1998: {
1999: static const char *pmmuCond[16] = { "BS", "BC", "LS", "LC", "SS", "SC", "AS", "AC", "WS", "WC", "IS", "IC", "GS", "GC", "CS", "CC" };
2000: static const char *braCond[16] = { "RA", "SR", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
2001: static const char *sccCond[16] = { "T", "F", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
2002: static const char *dbCond[16] = { "T", "RA", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
2003: static const char *fpuCond[64] = { "F", "EQ", "OGT", "OGE", "OLT", "OLE", "OGL", "OR", "UN", "UEQ", "UGT", "UGE", "ULT", "ULE", "NE", "T", "SF", "SEQ", "GT", "GE", "LT", "LE", "GL", "GLE", "NGLE", "NGL", "NLE", "NLT", "NGE", "NGT", "SNE", "ST" };
1.1.1.4 root 2004: char buf[8];
1.1 root 2005:
2006: const char *sp = NULL;
2007: switch(ots->opcodeName[++i])
2008: {
2009: case 'p': // PMMU conditions
2010: sp = pmmuCond[opcode[1] & 0xF];
2011: break;
2012: case 'b': // BRA conditions
2013: sp = braCond[(opcode[0] >> 8) & 0xF];
2014: break;
2015: case 'i': // Scc,TRAPcc conditions
2016: sp = sccCond[(opcode[0] >> 8) & 0xF];
2017: break;
2018: case 'd': // DBcc conditions
2019: sp = dbCond[(opcode[0] >> 8) & 0xF];
2020: break;
2021: case 'F': // FPU conditions (first word)
2022: sp = fpuCond[opcode[0] & 0x3F];
2023: break;
2024: case 'f': // FPU conditions (second word)
2025: sp = fpuCond[opcode[1] & 0x3F];
2026: break;
2027: }
2028: if(sp)
2029: {
2030: if(options & doptOpcodesSmall)
2031: {
1.1.1.4 root 2032: char *bp;
1.1 root 2033: strcpy(buf, sp);
2034: sp = buf;
1.1.1.4 root 2035: for (bp = buf; *bp; ++bp)
1.1.1.5 root 2036: *bp = tolower((unsigned char)*bp);
1.1 root 2037: }
2038: strcpy(dbuf, sp);
2039: dbuf += strlen(sp);
2040: continue;
2041: }
2042: goto more;
2043: }
2044: if(c == '?') // size mask
2045: c = sizeChar;
2046: if(options & doptOpcodesSmall)
1.1.1.5 root 2047: c = tolower((unsigned char)c);
1.1 root 2048: *dbuf++ = c;
2049: }
2050: *dbuf = 0;
2051:
2052: // Parse the EAs for all operands
1.1.1.4 root 2053: ea = opcode[0] & 0x3F;
1.1 root 2054: dbuf = operandBuffer;
1.1.1.5 root 2055:
1.1.1.7 root 2056: maxop = (int)(sizeof(ots->op)/sizeof(ots->op[0]));
1.1.1.5 root 2057: for(i=0; i<maxop; ++i)
1.1 root 2058: {
1.1.1.7 root 2059: int reg, val;
1.1.1.4 root 2060:
1.1 root 2061: switch(ots->op[i])
2062: {
2063: case ofNone: // nothing
2064: break;
2065:
2066: case ofEa:
2067: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, EA_All & ~(ots->parameter[i]), 0, ots->disassFlag);
2068: break;
2069:
2070: case ofDn:
2071: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2072: break;
2073: case ofAn:
2074: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x08, size, EA_An, 0, ots->disassFlag);
2075: break;
2076: case ofAni:
2077: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x10, size, EA_Ani, 0, ots->disassFlag);
2078: break;
2079: case ofAnip:
2080: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2081: break;
2082: case ofPiAn:
2083: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x20, size, EA_piAn, 0, ots->disassFlag);
2084: break;
2085: case ofD16An:
2086: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x28, size, EA_dAn, 0, ots->disassFlag);
2087: break;
2088:
2089: case ofI:
2090: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x3C, size, EA_Immed, 0, ots->disassFlag);
2091: break;
2092:
2093: case ofDestDn:
2094: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2095: break;
2096: case ofDestAn:
2097: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x08, size, EA_An, 0, ots->disassFlag);
2098: break;
2099: case ofDestAnip:
2100: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2101: break;
2102: case ofDestPiAn:
2103: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x20, size, EA_piAn, 0, ots->disassFlag);
2104: break;
2105: case ofDestEa6:
2106: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | (((opcode[0] >> 6) & 0x7) << 3), size, EA_Dest-EA_An, 0, ots->disassFlag);
2107: break;
2108: case ofDestAbsL:
2109: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x39, size, EA_Abs, 0, ots->disassFlag);
2110: break;
2111:
2112: case ofIOpcode:
2113: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, opcode[0] & ots->parameter[i], ots->disassFlag);
2114: break;
2115: case ofI3:
2116: val = ((opcode[0] >> 9) & 7);
2117: if(!val) val = 8;
2118: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, val, ots->disassFlag);
2119: break;
2120: case ofExtIm:
2121: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, opcode[1], ots->disassFlag);
2122: break;
2123: case ofExtIm32:
2124: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, size, EA_ImmedParameter, opcode[2], ots->disassFlag);
2125: break;
2126: case ofExtIm4:
2127: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, opcode[1] & 0x0F, ots->disassFlag);
2128: break;
2129: case ofExtIm10:
2130: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, (opcode[1] >> 10) & 0x07, ots->disassFlag);
2131: break;
2132: case ofSpecReg:
2133: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0101, size, EA_SpecialRegister, ots->parameter[i], ots->disassFlag);
2134: break;
2135: case ofSpecExtReg:
2136: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0101, size, EA_SpecialRegister, opcode[1] & 0xFFF, ots->disassFlag);
2137: break;
2138: case ofExtReg0:
2139: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2140: break;
2141: case ofExtRegA0:
2142: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07) | 0x08, size, EA_An, 0, ots->disassFlag);
2143: break;
2144: case ofExtRegD04:
2145: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 4) & 0x07) | 0x00, size, EA_Dn, 0, ots->disassFlag);
2146: break;
2147: case ofExtRegA05:
2148: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 5) & 0x07) | 0x08, size, EA_An, 0, ots->disassFlag);
2149: break;
2150: case ofExtReg:
2151: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2152: break;
2153: case ofExtAnip:
2154: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
2155: break;
2156:
2157: case ofDisp:
2158: // branch treats the displacement 0x00 and 0xFF as an indicator how many words follow
2159: // This test will decline a displacement with the wrong word offset
2160: if((opcode[0] & 0xF000) == 0x6000)
2161: {
2162: val = opcode[0] & 0xFF;
2163: if(val == 0x00 && size != 2) goto more;
2164: if(val == 0xFF && size != 4) goto more;
2165: }
2166: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0102, size, EA_PCDisplacement, opcode[0] & 0xFF, ots->disassFlag);
2167: break;
2168:
2169: case ofRegList:
2170: val = opcode[1];
2171: if((ea & 0x38) == 0x20) // -(An) has a flipped bitmask
2172: val = Disass68kFlipBits(val);
2173: dbuf = Disass68kReglist(dbuf, val);
2174: break;
2175:
2176: case ofFPU:
2177: { // default FPU opcode modes
2178: int src = (opcode[1] >> 10) & 7;
2179: int dest = (opcode[1] >> 7) & 7;
2180: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2181: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2182: if(opcode[1] & 0x4000)
2183: {
2184: // <ea>,FPn
2185: int mask = EA_All - EA_An;
2186: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2187: mask -= EA_Dn;
2188: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2189: if(!dbuf) goto more;
2190: *dbuf++ = ',';
2191: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2192: *dbuf = 0;
2193: } else {
2194: // FPn,FPn or FPn
2195:
2196: // <ea> has to be 0
2197: if((opcode[0] & 0x3F) != 0) goto more;
2198:
2199: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+src;
2200: if(src != dest)
2201: {
2202: *dbuf++ = ',';
2203: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2204: }
2205: *dbuf = 0;
2206: }
2207: }
2208: break;
2209: case ofFPUMOVE:
2210: { // MOVE <ea>,FPn{k-Factor}
2211: int src = (opcode[1] >> 10) & 7;
2212: // <ea>,FPn
2213: int mask = EA_All - EA_An;
2214: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2215: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2216: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2217: mask -= EA_Dn;
2218: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2219: if(!dbuf) goto more;
2220: *dbuf++ = ',';
2221: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+((opcode[1] >> 7) & 7);
2222: if(src == 3)
2223: {
2224: int kFactor = opcode[1] & 0x7F;
2225: if(kFactor & 0x40)
2226: kFactor |= 0x80;
2227: *dbuf++ = '{';
2228: sprintf(dbuf, "%d", (signed char)kFactor);
2229: dbuf += strlen(dbuf);
2230: *dbuf++ = '}';
2231: } else if(src == 7)
2232: {
2233: if((opcode[1] & 0x0F) != 0) goto more;
2234: *dbuf++ = '{';
2235: *dbuf++ = options & doptRegisterSmall ? 'd' : 'D';
2236: *dbuf++ = '0' + ((opcode[1] >> 4) & 7);
2237: *dbuf++ = '}';
2238: } else {
2239: if((opcode[1] & 0x7F) != 0) goto more;
2240: }
2241: *dbuf = 0;
2242: }
2243: break;
2244: case ofFMOVECR:
2245: { // MOVECR #const,FPn
2246: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2247: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2248: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, opcode[1] & 0x7F, ots->disassFlag);
2249: if(!dbuf) goto more;
1.1.1.4 root 2250: reg = (opcode[1] >> 7) & 7;
1.1 root 2251: *dbuf++ = ',';
2252: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+reg;
2253: *dbuf = 0;
2254: switch(opcode[1] & 0x7F) // document the well-known constants
2255: {
2256: case 0x00: strcat(commentBuffer, "PI"); break;
2257: case 0x0B: strcat(commentBuffer, "Log10(2)"); break;
2258: case 0x0C: strcat(commentBuffer, "e"); break;
2259: case 0x0D: strcat(commentBuffer, "Log2(e)"); break;
2260: case 0x0E: strcat(commentBuffer, "Log10(e)"); break;
2261: case 0x0F: strcat(commentBuffer, "0.0"); break;
2262: case 0x30: strcat(commentBuffer, "1n(2)"); break;
2263: case 0x31: strcat(commentBuffer, "1n(10)"); break;
2264: case 0x32: strcat(commentBuffer, "100"); break;
2265: case 0x33: strcat(commentBuffer, "10^1"); break;
2266: case 0x34: strcat(commentBuffer, "10^2"); break;
2267: case 0x35: strcat(commentBuffer, "10^4"); break;
2268: case 0x36: strcat(commentBuffer, "10^8"); break;
2269: case 0x37: strcat(commentBuffer, "10^16"); break;
2270: case 0x38: strcat(commentBuffer, "10^32"); break;
2271: case 0x39: strcat(commentBuffer, "10^64"); break;
2272: case 0x3A: strcat(commentBuffer, "10^128"); break;
2273: case 0x3B: strcat(commentBuffer, "10^256"); break;
2274: case 0x3C: strcat(commentBuffer, "10^512"); break;
2275: case 0x3D: strcat(commentBuffer, "10^1024"); break;
2276: case 0x3E: strcat(commentBuffer, "10^2048"); break;
2277: case 0x3F: strcat(commentBuffer, "10^4096"); break;
2278: }
2279: }
2280: break;
2281: case ofFPUSRRegList:
2282: {
2283: int hasReg = 0;
2284: *dbuf = 0;
2285: if(opcode[1] & 0x0400)
2286: {
2287: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPIAR));
2288: hasReg = 1;
2289: }
2290: if(opcode[1] & 0x0800)
2291: {
2292: if(hasReg) strcat(dbuf, "/");
2293: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPSR));
2294: hasReg = 1;
2295: }
2296: if(opcode[1] & 0x1000)
2297: {
2298: if(hasReg) strcat(dbuf, "/");
2299: strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPCR));
2300: hasReg = 1;
2301: }
2302: if(!hasReg)
2303: strcat(dbuf, "0");
2304: dbuf += strlen(dbuf);
2305: }
2306: break;
2307: case ofFPUReglist: // FMOVEM
2308: {
2309: int mask = opcode[1] & 0xFF;
2310: if(opcode[1] & 0x0100)
2311: mask = Disass68kFlipBits(mask) >> 8;
2312: dbuf = Disass68kFPUReglist(dbuf, mask);
2313: }
2314: break;
2315: case ofFPU3Reg:
2316: { // FSINCOS
2317: int src = (opcode[1] >> 10) & 7;
2318: int dest = (opcode[1] >> 7) & 7;
2319: char regFP1 = options & doptRegisterSmall ? 'f' : 'F';
2320: char regFP2 = options & doptRegisterSmall ? 'p' : 'P';
2321: if(opcode[1] & 0x4000)
2322: {
2323: // <ea>,FPn
2324: int mask = EA_All - EA_An;
2325: if(src != 0 && src != 4 && src != 6) // only .B,.W and .L allow Dn as a source
2326: mask -= EA_Dn;
2327: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
2328: if(!dbuf) goto more;
2329: *dbuf++ = ',';
2330: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+(opcode[1] & 7);
2331: *dbuf++ = ',';
2332: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2333: *dbuf = 0;
2334: } else {
2335: // FPn,FPn or FPn
2336:
2337: // <ea> has to be 0
2338: if((opcode[0] & 0x3F) != 0) goto more;
2339:
2340: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+src;
2341: *dbuf++ = ',';
2342: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+(opcode[1] & 7);
2343: *dbuf++ = ',';
2344: *dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
2345: *dbuf = 0;
2346: }
2347: }
2348: break;
2349:
2350: case ofCAS:
2351: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2352: if(!dbuf) goto more;
2353: *dbuf++ = ',';
2354: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2355: break;
2356: case ofCAS2:
2357: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2358: if(!dbuf) goto more;
2359: *dbuf++ = ':';
2360: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[2] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2361: if(!dbuf) goto more;
2362: *dbuf++ = ',';
2363: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2364: if(!dbuf) goto more;
2365: *dbuf++ = ':';
2366: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[2] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2367: if(!dbuf) goto more;
2368: *dbuf++ = ',';
2369: *dbuf++ = '(';
2370: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2371: if(!dbuf) goto more;
2372: *dbuf++ = ')';
2373: *dbuf++ = ':';
2374: *dbuf++ = '(';
2375: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[2] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
2376: if(!dbuf) goto more;
2377: *dbuf++ = ')';
2378: *dbuf = 0;
2379: break;
2380: case ofExt4Dn:
2381: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[0] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2382: if(!dbuf) goto more;
2383: *dbuf++ = ':';
2384: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
2385: if(!dbuf) goto more;
2386: *dbuf++ = ',';
2387: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x07), size, EA_Dn, 0, ots->disassFlag);
2388: if(!dbuf) goto more;
2389: *dbuf = 0;
2390: break;
2391: case ofBFEa:
2392: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, EA_All & ~(ots->parameter[i]), 0, ots->disassFlag);
2393: if(!dbuf) goto more;
2394: *dbuf++ = '{';
2395: val = (opcode[1] >> 6) & 0x1F;
2396: if(opcode[1] & 0x0800)
2397: {
2398: if(val & 0x18) goto more;
2399: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, val & 0x07, 1, EA_Dn, val, ots->disassFlag);
2400: } else {
2401: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0103, 1, EA_ValueParameter, val, ots->disassFlag);
2402: }
2403: *dbuf++ = ':';
2404: val = opcode[1] & 0x1F;
2405: if(opcode[1] & 0x0020)
2406: {
2407: if(val & 0x18) goto more;
2408: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, val & 0x07, 1, EA_Dn, val, ots->disassFlag);
2409: } else {
2410: if(val == 0) val = 32;
2411: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0103, 1, EA_ValueParameter, val, ots->disassFlag);
2412: }
2413: *dbuf++ = '}';
2414: *dbuf = 0;
2415: break;
2416: case ofLineA:
2417: {
2418: int lineAVal = opcode[0] & 0xFFF;
2419: const char *lineAStr[16] = { "Line-A Initialization",
2420: "Put pixel",
2421: "Get pixel",
2422: "Arbitrary line",
2423: "Horizontal line",
2424: "Filled rectangle",
2425: "Filled polygon",
2426: "Bit block transfer",
2427: "Text block transfer",
2428: "Show mouse",
2429: "Hide mouse",
2430: "Transform mouse",
2431: "Undraw sprite",
2432: "Draw sprite",
2433: "Copy raster form",
2434: "Seedfill"
2435: };
1.1.1.4 root 2436: dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, lineAVal, ots->disassFlag);
1.1 root 2437: if(lineAVal < 16)
2438: strcat(commentBuffer, lineAStr[lineAVal]);
2439: }
2440: break;
2441:
2442: default:
2443: goto more;
2444: }
2445: if(!dbuf) goto more;
2446:
2447: // does another operand follow => add separator
1.1.1.5 root 2448: if ( (i+1<maxop) && ( ots->op[i+1] != ofNone) )
1.1 root 2449: *dbuf++ = ',';
2450: }
2451: return addr-baseAddr;
2452: }
2453:
2454: // unknown opcode
2455: strcpy(opcodeBuffer, "DC.W");
2456: sprintf(operandBuffer,"$%4.4x", Disass68kGetWord(addr));
2457: return 2;
2458: }
2459:
2460: static void Disass68kComposeStr(char *dbuf, const char *str, int position, int maxPos)
2461: {
2462: int i;
2463: int len = strlen(dbuf);
2464: while(len < position) {
2465: dbuf[len++] = ' '; /* Will give harmless warning from GCC */
2466: }
2467: for(i=0; str[i] && (!maxPos || len+i<maxPos); ++i)
2468: dbuf[len+i] = str[i];
2469: if(str[i])
2470: dbuf[len+i-1] = '+';
2471: dbuf[len+i] = 0;
2472: }
2473:
2474: static void Disass68k_loop (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
2475: {
2476: static bool isInit = false;
2477: if(!isInit)
2478: {
2479: Disass68kInit(Paths_GetHatariHome());
2480: isInit = true;
2481: }
2482:
1.1.1.4 root 2483: while (cnt-- > 0) {
1.1.1.6 root 2484: const int addrWidth = 8; // 6 on an ST (24 bit addressing), 8 on a TT (32 bit addressing)
1.1 root 2485: char lineBuffer[1024];
2486:
2487: char addressBuffer[32];
2488: char hexdumpBuffer[256];
2489: char labelBuffer[256];
2490: char opcodeBuffer[64];
2491: char operandBuffer[256];
2492: char commentBuffer[256];
1.1.1.4 root 2493: int plen, len, j;
2494:
2495: len = Disass68k(addr, labelBuffer, opcodeBuffer, operandBuffer, commentBuffer);
1.1 root 2496: if(!len) break;
2497:
2498: sprintf(addressBuffer, "$%*.*x :", addrWidth,addrWidth, addr);
2499:
2500: hexdumpBuffer[0] = 0;
1.1.1.4 root 2501: plen = len;
1.1 root 2502: if(plen > 80 && (!strncmp(opcodeBuffer, "DC.", 3) || !strncmp(opcodeBuffer, "dc.", 3)))
2503: plen = ((optionPosLabel - optionPosHexdump) / 5) * 2;
1.1.1.4 root 2504:
1.1 root 2505: for(j=0; j<plen; j += 2)
2506: {
2507: if(j > 0)
2508: strcat(hexdumpBuffer, " ");
2509: if(j + 2 > plen)
2510: {
2511: sprintf(hexdumpBuffer+strlen(hexdumpBuffer), "%2.2x", Disass68kGetWord(addr+j) >> 8);
2512: } else {
2513: sprintf(hexdumpBuffer+strlen(hexdumpBuffer), "%4.4x", Disass68kGetWord(addr+j));
2514: }
2515: }
2516:
2517: lineBuffer[0] = 0;
2518: if(optionPosAddress >= 0)
2519: Disass68kComposeStr(lineBuffer, addressBuffer, optionPosAddress, 0);
2520: if(optionPosHexdump >= 0)
2521: Disass68kComposeStr(lineBuffer, hexdumpBuffer, optionPosHexdump, optionPosLabel);
2522: if(optionPosLabel >= 0)
2523: Disass68kComposeStr(lineBuffer, labelBuffer, optionPosLabel, 0);
2524: if(optionPosOpcode >= 0)
2525: Disass68kComposeStr(lineBuffer, opcodeBuffer, optionPosOpcode, 0);
2526: if(optionPosOperand >= 0)
2527: {
2528: size_t l = strlen(lineBuffer);
2529: if(lineBuffer[l-1] != ' ') // force at least one space between opcode and operand
2530: {
2531: lineBuffer[l++] = ' ';
2532: lineBuffer[l] = 0;
2533: }
2534: Disass68kComposeStr(lineBuffer, operandBuffer, optionPosOperand, 0);
2535: }
1.1.1.4 root 2536: if (optionPosComment >= 0)
1.1.1.3 root 2537: {
1.1.1.8 ! root 2538: if (Profile_CpuAddressDataStr(commentBuffer, sizeof(commentBuffer), addr))
1.1.1.3 root 2539: {
2540: Disass68kComposeStr(lineBuffer, commentBuffer, optionPosComment+1, 0);
2541: }
1.1.1.4 root 2542: /* show comments only if profile data is missing */
2543: else if (commentBuffer[0])
2544: {
2545: Disass68kComposeStr(lineBuffer, " ;", optionPosComment, 0);
2546: Disass68kComposeStr(lineBuffer, commentBuffer, optionPosComment+3, 0);
2547: }
1.1.1.3 root 2548: }
1.1.1.4 root 2549: addr += len;
2550: if (f)
2551: fprintf(f, "%s\n", lineBuffer);
1.1 root 2552: // if(strstr(opcodeBuffer, "RTS") || strstr(opcodeBuffer, "RTE") || strstr(opcodeBuffer, "JMP")
2553: // || strstr(opcodeBuffer, "rts") || strstr(opcodeBuffer, "rte") || strstr(opcodeBuffer, "jmp"))
2554: // fprintf(f, "\n");
2555: }
2556: if (nextpc)
2557: *nextpc = addr;
2558: }
2559:
2560:
1.1.1.4 root 2561: /**
2562: * Calculate next PC address from given one, without output
2563: * @return next PC address
1.1 root 2564: */
1.1.1.4 root 2565: Uint32 Disasm_GetNextPC(Uint32 pc)
2566: {
2567: uaecptr nextpc;
2568: Disass68k_loop (NULL, pc, &nextpc, 1);
2569: return nextpc;
2570: }
1.1 root 2571:
1.1.1.4 root 2572: /**
2573: * Call disassembly using the selected disassembly method,
2574: * either internal UAE one, or the stand alone disassembler above,
2575: * whichever is selected in Hatari configuration
2576: */
2577: void Disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1.1 root 2578: {
1.1.1.4 root 2579: if (ConfigureParams.Debugger.bDisasmUAE)
1.1.1.6 root 2580: #ifdef WINUAE_FOR_HATARI
2581: m68k_disasm_file (f, addr, nextpc, cnt);
2582: #else
1.1.1.5 root 2583: m68k_disasm (f, addr, nextpc, cnt);
1.1.1.6 root 2584: #endif
1.1.1.4 root 2585: else
1.1.1.5 root 2586: Disass68k_loop (f, addr, nextpc, cnt);
1.1 root 2587: }
2588:
1.1.1.4 root 2589: static void Disasm_CheckOptionEngine(void)
2590: {
2591: if (ConfigureParams.Debugger.bDisasmUAE)
2592: fputs("WARNING: disassembly options are supported only for '--disasm ext'!\n", stderr);
2593: }
2594:
2595: /**
2596: * query disassembly output column positions.
2597: */
2598: void Disasm_GetColumns(int *pos)
2599: {
2600: pos[DISASM_COLUMN_ADDRESS] = optionPosAddress;
2601: pos[DISASM_COLUMN_HEXDUMP] = optionPosHexdump;
2602: pos[DISASM_COLUMN_LABEL] = optionPosLabel;
2603: pos[DISASM_COLUMN_OPCODE] = optionPosOpcode;
2604: pos[DISASM_COLUMN_OPERAND] = optionPosOperand;
2605: pos[DISASM_COLUMN_COMMENT] = optionPosComment;
2606: }
2607:
2608: /**
2609: * set disassembly output column positions.
2610: */
2611: void Disasm_SetColumns(int *pos)
2612: {
2613: Disasm_CheckOptionEngine();
2614: optionPosAddress = pos[DISASM_COLUMN_ADDRESS];
2615: optionPosHexdump = pos[DISASM_COLUMN_HEXDUMP];
2616: optionPosLabel = pos[DISASM_COLUMN_LABEL];
2617: optionPosOpcode = pos[DISASM_COLUMN_OPCODE];
2618: optionPosOperand = pos[DISASM_COLUMN_OPERAND];
2619: optionPosComment = pos[DISASM_COLUMN_COMMENT];
2620: }
2621:
2622: /**
2623: * function to disable given disassembly output 'column'.
2624: * input is current column positions in 'oldcols' array and
2625: * output is new column positions/values in 'newcols' array.
2626: * It's safe to use same array for both.
2627: */
2628: void Disasm_DisableColumn(int column, int *oldcols, int *newcols)
2629: {
2630: int i, diff = 0;
2631:
2632: assert(column >= 0 && column < DISASM_COLUMNS);
2633: if (column+1 < DISASM_COLUMNS)
2634: diff = oldcols[column+1] - oldcols[column];
2635:
2636: for (i = 0; i < DISASM_COLUMNS; i++)
2637: {
2638: if (i && oldcols[i-1] > oldcols[i])
2639: {
2640: printf("WARNING: disassembly columns aren't in the expected order!\n");
2641: return;
2642: }
2643: if (i < column)
2644: newcols[i] = oldcols[i];
2645: else if (i > column)
2646: newcols[i] = oldcols[i] - diff;
2647: else
2648: newcols[column] = DISASM_COLUMN_DISABLE;
2649: }
2650: }
2651:
2652: /**
2653: * Get current disassembly output option flags
2654: * @return current output flags
2655: */
2656: int Disasm_GetOptions(void)
2657: {
2658: return options;
2659: }
2660:
2661: /**
1.1.1.6 root 2662: * Set CPU and FPU mask used for disassembly (when changed from the UI or the options)
2663: */
2664: void Disasm_SetCPUType ( int CPU , int FPU )
2665: {
2666: optionCPUTypeMask = 0;
2667:
2668: if ( ( FPU == 68881 ) || ( FPU == 68882 ) )
2669: optionCPUTypeMask |= MC_FPU;
2670:
2671: switch ( CPU )
2672: {
2673: case 0 : optionCPUTypeMask |= MC68000 ; break;
2674: case 1 : optionCPUTypeMask |= MC68010 ; break;
2675: case 2 : optionCPUTypeMask |= MC68020 ; break;
2676: case 3 : optionCPUTypeMask |= MC68030 ; break;
2677: case 4 : optionCPUTypeMask |= MC68040 ; break;
2678: default : optionCPUTypeMask |= MC68000 ; break;
2679: }
2680: }
2681:
2682: /**
1.1.1.4 root 2683: * Parse disasm command line option argument
2684: * @return error string (""=silent 'error') or NULL for success.
2685: */
2686: const char *Disasm_ParseOption(const char *arg)
2687: {
2688: if (strcasecmp(arg, "help") == 0)
2689: {
2690: const struct {
2691: int flag;
2692: const char *desc;
2693: } option[] = {
2694: { doptNoBrackets, "no brackets around absolute addressing" },
2695: { doptOpcodesSmall, "opcodes in small letters" },
2696: { doptRegisterSmall, "register names in small letters" },
2697: { doptStackSP, "stack pointer as 'SP', not 'A7'" },
2698: { 0, NULL }
2699: };
2700: int i;
2701: fputs("Disassembly settings:\n"
2702: "\tuae - use CPU core internal disassembler which has better\n"
2703: "\t instruction support\n"
2704: "\text - use external disassembler which has nicer output\n"
2705: "\t and supports options below\n"
2706: "\t<bitmask> - disassembly output option flags\n"
2707: "Flag values:\n", stderr);
2708: for (i = 0; option[i].desc; i++) {
2709: assert(option[i].flag == (1 << i));
2710: fprintf(stderr, "\t%d: %s\n", option[i].flag, option[i].desc);
2711: }
2712: fprintf(stderr, "Current settings are:\n\t--disasm %s --disasm %d\n",
2713: ConfigureParams.Debugger.bDisasmUAE ? "uae" : "ext",
2714: ConfigureParams.Debugger.nDisasmOptions);
2715: return "";
2716: }
2717: if (strcasecmp(arg, "uae") == 0)
2718: {
2719: fputs("Selected UAE CPU core internal disassembler.\n", stderr);
2720: ConfigureParams.Debugger.bDisasmUAE = true;
2721: return NULL;
2722: }
2723: if (strcasecmp(arg, "ext") == 0)
2724: {
2725: fputs("Selected external disassembler.\n", stderr);
2726: fprintf(stderr, "Disassembly output flags are %d.\n", options);
2727: ConfigureParams.Debugger.bDisasmUAE = false;
2728: return NULL;
2729: }
1.1.1.5 root 2730: if (isdigit((unsigned char)*arg))
1.1.1.4 root 2731: {
2732: int newopt = atoi(arg);
2733: if ((newopt|optionsMask) != optionsMask)
2734: {
2735: return "unknown flags in the bitmask";
2736: }
2737: fprintf(stderr, "Changed CPU disassembly output flags from %d to %d.\n", options, newopt);
2738: ConfigureParams.Debugger.nDisasmOptions = options = newopt;
2739: Disasm_CheckOptionEngine();
2740: return NULL;
2741: }
2742: return "invalid disasm option";
2743: }
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