--- hatari/src/falcon/dsp.c	2019/04/09 08:47:21	1.1.1.3
+++ hatari/src/falcon/dsp.c	2019/04/09 08:53:22	1.1.1.9
@@ -26,8 +26,13 @@
 #include "memorySnapShot.h"
 #include "ioMem.h"
 #include "dsp.h"
+#include "crossbar.h"
+#include "configuration.h"
+#include "cycInt.h"
+#include "m68000.h"
+
 #if ENABLE_DSP_EMU
-#include "debugui.h"
+#include "debugdsp.h"
 #include "dsp_cpu.h"
 #include "dsp_disasm.h"
 #endif
@@ -39,16 +44,59 @@
 #define Dprintf(a)
 #endif
 
-#define BITMASK(x)	((1<<(x))-1)
-
 #define DSP_HW_OFFSET  0xFFA200
 
+
 #if ENABLE_DSP_EMU
-static dsp_core_t dsp_core;
+static const char* x_ext_memory_addr_name[] = {
+	"", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+	"", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+	"PBC", "PCC", "PBDDR", "PCDDR", "PBD", "PCD", "", "",
+	"HCR", "HSR", "", "HRX/HTX", "CRA", "CRB", "SSISR/TSR", "RX/TX",
+	"SCR", "SSR", "SCCR", "STXA", "SRX/STX", "SRX/STX", "SRX/STX", "",
+	"", "", "", "", "", "", "BCR", "IPR"
+};
+
+static Sint32 save_cycles;
 #endif
+
 static bool bDspDebugging;
 
 bool bDspEnabled = false;
+bool bDspHostInterruptPending = false;
+
+
+/**
+ * Trigger HREQ interrupt at the host CPU.
+ */
+#if ENABLE_DSP_EMU
+static void DSP_TriggerHostInterrupt(void)
+{
+	bDspHostInterruptPending = true;
+	M68000_SetSpecial(SPCFLAG_DSP);
+}
+#endif
+
+
+/**
+ * This function is called from the CPU emulation part when SPCFLAG_DSP is set.
+ * If the DSP's IRQ signal is set, we check that SR allows a level 6 interrupt,
+ * and if so, we call M68000_Exception.
+ */
+#if ENABLE_DSP_EMU
+bool	DSP_ProcessIRQ(void)
+{
+	if (bDspHostInterruptPending && regs.intmask < 6)
+	{
+		M68000_Exception(IoMem_ReadByte(0xffa203)*4, M68000_EXC_SRC_INT_DSP);
+		bDspHostInterruptPending = false;
+		M68000_UnsetSpecial(SPCFLAG_DSP);
+		return true;
+	}
+
+	return false;
+}
+#endif
 
 
 /**
@@ -57,9 +105,12 @@ bool bDspEnabled = false;
 void DSP_Init(void)
 {
 #if ENABLE_DSP_EMU
-	dsp_core_init(&dsp_core);
-	dsp56k_init_cpu(&dsp_core);
+	if (bDspEnabled || ConfigureParams.System.nDSPType != DSP_TYPE_EMU)
+		return;
+	dsp_core_init(DSP_TriggerHostInterrupt);
+	dsp56k_init_cpu();
 	bDspEnabled = true;
+	save_cycles = 0;
 #endif
 }
 
@@ -70,7 +121,9 @@ void DSP_Init(void)
 void DSP_UnInit(void)
 {
 #if ENABLE_DSP_EMU
-	dsp_core_shutdown(&dsp_core);
+	if (!bDspEnabled)
+		return;
+	dsp_core_shutdown();
 	bDspEnabled = false;
 #endif
 }
@@ -82,7 +135,9 @@ void DSP_UnInit(void)
 void DSP_Reset(void)
 {
 #if ENABLE_DSP_EMU
-	dsp_core_reset(&dsp_core);
+	dsp_core_reset();
+	bDspHostInterruptPending = false;
+	save_cycles = 0;
 #endif
 }
 
@@ -98,31 +153,42 @@ void DSP_MemorySnapShot_Capture(bool bSa
 
 	MemorySnapShot_Store(&bDspEnabled, sizeof(bDspEnabled));
 	MemorySnapShot_Store(&dsp_core, sizeof(dsp_core));
+	MemorySnapShot_Store(&save_cycles, sizeof(save_cycles));
 #endif
 }
 
-
 /**
  * Run DSP for certain cycles
  */
 void DSP_Run(int nHostCycles)
 {
 #if ENABLE_DSP_EMU
-	/* Cycles emulation is just a rough approximation by now.
-	 * (to be tuned ...) */
-	int i = nHostCycles * 2 + 2;
-	int dsp_cycle = 0;
+        save_cycles += nHostCycles * 2;
 
-	while (dsp_core.running == 1 && i >= dsp_cycle)
-	{
-		if (unlikely(bDspDebugging))
-			DebugUI_DspCheck();
+        if (dsp_core.running == 0)
+                return;
+
+        if (save_cycles <= 0)
+                return;
+
+        if (unlikely(bDspDebugging)) {
+                while (save_cycles > 0)
+                {
+                        dsp56k_execute_instruction();
+                        save_cycles -= dsp_core.instr_cycle;
+                        DebugDsp_Check();
+                }
+        } else {
+		//	fprintf(stderr, "--> %d\n", save_cycles);
+                while (save_cycles > 0)
+                {
+                        dsp56k_execute_instruction();
+                        save_cycles -= dsp_core.instr_cycle;
+                }
+        }
 
-		dsp56k_execute_instruction();
-		dsp_cycle += dsp_core.instr_cycle;
-	}
 #endif
-}
+} 
 
 /**
  * Enable/disable DSP debugging mode
@@ -133,7 +199,7 @@ void DSP_SetDebugging(bool enabled)
 }
 
 /**
- * Get DSP program counter (for disassembler)
+ * Get DSP program counter (for debugging)
  */
 Uint16 DSP_GetPC(void)
 {
@@ -145,22 +211,63 @@ Uint16 DSP_GetPC(void)
 	return 0;
 }
 
+/**
+ * Get next DSP PC without output (for debugging)
+ */
+Uint16 DSP_GetNextPC(Uint16 pc)
+{
+#if ENABLE_DSP_EMU
+	/* code is reduced copy from dsp56k_execute_one_disasm_instruction() */
+	dsp_core_t dsp_core_save;
+	Uint16 instruction_length;
+
+	if (!bDspEnabled)
+		return 0;
+
+	/* Save DSP context */
+	memcpy(&dsp_core_save, &dsp_core, sizeof(dsp_core));
+
+	/* Disasm instruction */
+	dsp_core.pc = pc;
+	/* why dsp56k_execute_one_disasm_instruction() does "-1"
+	 * for this value, that doesn't seem right???
+	 */
+	instruction_length = dsp56k_disasm(DSP_DISASM_MODE);
+
+	/* Restore DSP context */
+	memcpy(&dsp_core, &dsp_core_save, sizeof(dsp_core));
+
+	return pc + instruction_length;
+#else
+	return 0;
+#endif
+}
 
 /**
- * Disassemble DSP code between given addresses
+ * Get current DSP instruction cycles (for profiling)
  */
-Uint32 DSP_DisasmAddress(Uint16 lowerAdr, Uint16 UpperAdr)
+Uint16 DSP_GetInstrCycles(void)
 {
 #if ENABLE_DSP_EMU
-	Uint32 dsp_pc, save_curPC;
-	
-	save_curPC = dsp_core.pc;
+	if (bDspEnabled)
+		return dsp_core.instr_cycle;
+	else
+#endif
+	return 0;
+}
+
+
+/**
+ * Disassemble DSP code between given addresses, return next PC address
+ */
+Uint16 DSP_DisasmAddress(FILE *out, Uint16 lowerAdr, Uint16 UpperAdr)
+{
+#if ENABLE_DSP_EMU
+	Uint16 dsp_pc;
 
 	for (dsp_pc=lowerAdr; dsp_pc<=UpperAdr; dsp_pc++) {
-		dsp_core.pc = dsp_pc;
-		dsp_pc += dsp56k_disasm() - 1;
+		dsp_pc += dsp56k_execute_one_disasm_instruction(out, dsp_pc);
 	}
-	dsp_core.pc = save_curPC;
 	return dsp_pc;
 #else
 	return 0;
@@ -256,8 +363,9 @@ Uint32 DSP_ReadMemory(Uint16 address, ch
 
 /**
  * Output memory values between given addresses in given DSP address space.
+ * Return next DSP address value.
  */
-void DSP_DisasmMemory(Uint16 dsp_memdump_addr, Uint16 dsp_memdump_upper, char space)
+Uint16 DSP_DisasmMemory(Uint16 dsp_memdump_addr, Uint16 dsp_memdump_upper, char space)
 {
 #if ENABLE_DSP_EMU
 	Uint32 mem, mem2, value;
@@ -265,7 +373,7 @@ void DSP_DisasmMemory(Uint16 dsp_memdump
 
 	for (mem = dsp_memdump_addr; mem <= dsp_memdump_upper; mem++) {
 		/* special printing of host communication/transmit registers */
-		if (space == 'X' && (mem == 0xffeb || mem == 0xffef)) {
+		if (space == 'X' && mem >= 0xffc0) {
 			if (mem == 0xffeb) {
 				fprintf(stderr,"X periph:%04x  HTX : %06x   RTX:%06x\n", 
 					mem, dsp_core.dsp_host_htx, dsp_core.dsp_host_rtx);
@@ -274,6 +382,10 @@ void DSP_DisasmMemory(Uint16 dsp_memdump
 				fprintf(stderr,"X periph:%04x  SSI TX : %06x   SSI RX:%06x\n", 
 					mem, dsp_core.ssi.transmit_value, dsp_core.ssi.received_value);
 			}
+			else {
+				value = DSP_ReadMemory(mem, space, &mem_str);
+				fprintf(stderr,"%s:%04x  %06x\t%s\n", mem_str, mem, value, x_ext_memory_addr_name[mem-0xffc0]);
+			}
 			continue;
 		}
 		/* special printing of X & Y external RAM values */
@@ -291,9 +403,52 @@ void DSP_DisasmMemory(Uint16 dsp_memdump
 		fprintf(stderr,"%s:%04x  %06x\n", mem_str, mem, value);
 	}
 #endif
+	return dsp_memdump_upper+1;
 }
 
+/**
+ * Show information on DSP core state which isn't
+ * shown by any of the other commands (dd, dm, dr).
+ */
+void DSP_Info(Uint32 dummy)
+{
+#if ENABLE_DSP_EMU
+	int i, j;
+	const char *stackname[] = { "SSH", "SSL" };
 
+	fputs("DSP core information:\n", stderr);
+
+	for (i = 0; i < ARRAYSIZE(stackname); i++) {
+		fprintf(stderr, "- %s stack:", stackname[i]);
+		for (j = 0; j < ARRAYSIZE(dsp_core.stack[0]); j++) {
+			fprintf(stderr, " %04hx", dsp_core.stack[i][j]);
+		}
+		fputs("\n", stderr);
+	}
+
+	fprintf(stderr, "- Interrupt IPL:");
+	for (i = 0; i < ARRAYSIZE(dsp_core.interrupt_ipl); i++) {
+		fprintf(stderr, " %04hx", dsp_core.interrupt_ipl[i]);
+	}
+	fputs("\n", stderr);
+
+	fprintf(stderr, "- Pending ints: ");
+	for (i = 0; i < ARRAYSIZE(dsp_core.interrupt_isPending); i++) {
+		fprintf(stderr, " %04hx", dsp_core.interrupt_isPending[i]);
+	}
+	fputs("\n", stderr);
+
+	fprintf(stderr, "- Hostport:");
+	for (i = 0; i < ARRAYSIZE(dsp_core.hostport); i++) {
+		fprintf(stderr, " %02x", dsp_core.hostport[i]);
+	}
+	fputs("\n", stderr);
+#endif
+}
+
+/**
+ * Show DSP register contents
+ */
 void DSP_DisasmRegisters(void)
 {
 #if ENABLE_DSP_EMU
@@ -408,10 +563,14 @@ int DSP_GetRegisterAddress(const char *r
 		{ "Y1",  &dsp_core.registers[DSP_REG_Y1],  32, BITMASK(24) }
 	};
 	/* left, right, middle, direction */
-        int l, r, m, dir;
-	unsigned int i;
+        int l, r, m, dir = 0;
+	unsigned int i, len;
 	char reg[MAX_REGNAME_LEN];
 
+	if (!bDspEnabled) {
+		return 0;
+	}
+
 	for (i = 0; i < sizeof(reg) && regname[i]; i++) {
 		reg[i] = toupper(regname[i]);
 	}
@@ -419,13 +578,14 @@ int DSP_GetRegisterAddress(const char *r
 		/* too short or longer than any of the names */
 		return 0;
 	}
-
+	len = i;
+	
 	/* bisect */
 	l = 0;
-	r = sizeof (registers) / sizeof (*registers) - 1;
+	r = ARRAYSIZE(registers) - 1;
 	do {
 		m = (l+r) >> 1;
-		for (i = 0; i < sizeof(reg); i++) {
+		for (i = 0; i < len; i++) {
 			dir = (int)reg[i] - registers[m].name[i];
 			if (dir) {
 				break;
@@ -449,9 +609,9 @@ int DSP_GetRegisterAddress(const char *r
 
 
 /**
- * Set given DSP register value
+ * Set given DSP register value, return false if unknown register given
  */
-void DSP_Disasm_SetRegister(char *arg, Uint32 value)
+bool DSP_Disasm_SetRegister(const char *arg, Uint32 value)
 {
 #if ENABLE_DSP_EMU
 	Uint32 *addr, mask, sp_value;
@@ -464,7 +624,7 @@ void DSP_Disasm_SetRegister(char *arg, U
 			value &= BITMASK(4); 
 			dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][value];
 			dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][value];
-			return;
+			return true;
 		}
 		if (arg[1]=='S' || arg[1]=='s') {
 			sp_value = dsp_core.registers[DSP_REG_SP] & BITMASK(4);
@@ -476,7 +636,7 @@ void DSP_Disasm_SetRegister(char *arg, U
 					dsp_core.registers[DSP_REG_SSH] = value & BITMASK(16);
 					dsp_core.stack[0][sp_value] = value & BITMASK(16);
 				}
-				return;
+				return true;
 			}
 			if (arg[2]=='L' || arg[2]=='l') {
 				if (sp_value == 0) {
@@ -486,7 +646,7 @@ void DSP_Disasm_SetRegister(char *arg, U
 					dsp_core.registers[DSP_REG_SSL] = value & BITMASK(16);
 					dsp_core.stack[1][sp_value] = value & BITMASK(16);
 				}
-				return;
+				return true;
 			}
 		}
 	}
@@ -496,17 +656,13 @@ void DSP_Disasm_SetRegister(char *arg, U
 	switch (bits) {
 	case 32:
 		*addr = value & mask;
-		return;
+		return true;
 	case 16:
 		*(Uint16*)addr = value & mask;
-		return;
+		return true;
 	}
-	fprintf(stderr,"\tError, usage:  reg=value  where: \n\t \
-			reg=A0-A2, B0-B2, X0, X1, Y0, Y1, \n\t \
-			R0-R7, N0-N7, M0-M7, LA, LC, PC \n\t \
-			SR, SP, OMR, SSH, SSL \n\t \
-			and value is a hex value.\n");
 #endif
+	return false;
 }
 
 /**
@@ -534,73 +690,108 @@ void DSP_SsiWriteRxValue(Uint32 value)
 /**
  * Signal SSI clock tick to DSP
  */
-void DSP_SsiReceiveSerialClock(void)
+
+void DSP_SsiReceive_SC0(void)
 {
 #if ENABLE_DSP_EMU
-	dsp_core_ssi_receive_serial_clock(&dsp_core);
+	dsp_core_ssi_Receive_SC0();
 #endif
 }
 
-void DSP_SsiReceive_SC2(Uint32 FrameCounter)
+void DSP_SsiTransmit_SC0(void)
 {
 #if ENABLE_DSP_EMU
-	dsp_core_ssi_receive_SC2(&dsp_core, FrameCounter);
 #endif
 }
 
-/**
- * Hardware IO address read by CPU
- */
-static Uint8 DSP_handleRead(Uint32 addr)
+void DSP_SsiReceive_SC1(Uint32 FrameCounter)
 {
-	Uint8 value;
 #if ENABLE_DSP_EMU
-	value = dsp_core_read_host(&dsp_core, addr-DSP_HW_OFFSET);
-#else
-	/* this value prevents TOS from hanging in the DSP init code */
-	value = 0xff;
+	dsp_core_ssi_Receive_SC1(FrameCounter);
+#endif
+}
+
+void DSP_SsiTransmit_SC1(void)
+{
+#if ENABLE_DSP_EMU
+	Crossbar_DmaPlayInHandShakeMode();
 #endif
+}
 
-	Dprintf(("HWget_b(0x%08x)=0x%02x at 0x%08x\n", addr, value, m68k_getpc()));
-	return value;
+void DSP_SsiReceive_SC2(Uint32 FrameCounter)
+{
+#if ENABLE_DSP_EMU
+	dsp_core_ssi_Receive_SC2(FrameCounter);
+#endif
 }
 
-/**
- * Read access wrapper for ioMemTabFalcon
- */
-void DSP_HandleReadAccess(void)
+void DSP_SsiTransmit_SC2(Uint32 frame)
 {
-	Uint32 a;
-	Uint8 v;
-	for (a = IoAccessBaseAddress; a < IoAccessBaseAddress+nIoMemAccessSize; a++)
-	{
-		v = DSP_handleRead(a);
-		IoMem_WriteByte(a, v);
-	}
+#if ENABLE_DSP_EMU
+	Crossbar_DmaRecordInHandShakeMode_Frame(frame);
+#endif
 }
 
+void DSP_SsiReceive_SCK(void)
+{
+#if ENABLE_DSP_EMU
+	dsp_core_ssi_Receive_SCK();
+#endif
+}
+
+void DSP_SsiTransmit_SCK(void)
+{
+#if ENABLE_DSP_EMU
+#endif
+}
 
 /**
- * Hardware IO address write by CPU
+ * Read access wrapper for ioMemTabFalcon (DSP Host port)
+ * DSP Host interface port is accessed by the 68030 in Byte mode.
+ * A move.w value,$ffA206 results in 2 bus access for the 68030.
  */
-static void DSP_handleWrite(Uint32 addr, Uint8 value)
+void DSP_HandleReadAccess(void)
 {
-	Dprintf(("HWput_b(0x%08x,0x%02x) at 0x%08x\n", addr, value, m68k_getpc()));
+	Uint32 addr;
+	Uint8 value;
+	bool multi_access = false; 
+	
+	for (addr = IoAccessBaseAddress; addr < IoAccessBaseAddress+nIoMemAccessSize; addr++)
+	{
 #if ENABLE_DSP_EMU
-	dsp_core_write_host(&dsp_core, addr-DSP_HW_OFFSET, value);
+		value = dsp_core_read_host(addr-DSP_HW_OFFSET);
+#else
+		/* this value prevents TOS from hanging in the DSP init code */
+		value = 0xff;
 #endif
+		if (multi_access == true)
+			M68000_AddCycles(4);
+		multi_access = true;
+
+		Dprintf(("HWget_b(0x%08x)=0x%02x at 0x%08x\n", addr, value, m68k_getpc()));
+		IoMem_WriteByte(addr, value);
+	}
 }
 
 /**
- * Write access wrapper for ioMemTabFalcon
+ * Write access wrapper for ioMemTabFalcon (DSP Host port)
+ * DSP Host interface port is accessed by the 68030 in Byte mode.
+ * A move.w value,$ffA206 results in 2 bus access for the 68030.
  */
 void DSP_HandleWriteAccess(void)
 {
-	Uint32 a;
-	Uint8 v;
-	for (a = IoAccessBaseAddress; a < IoAccessBaseAddress+nIoMemAccessSize; a++)
+	Uint32 addr;
+	bool multi_access = false; 
+
+	for (addr = IoAccessBaseAddress; addr < IoAccessBaseAddress+nIoMemAccessSize; addr++)
 	{
-		v = IoMem_ReadByte(a);
-		DSP_handleWrite(a,v);
+#if ENABLE_DSP_EMU
+		Uint8 value = IoMem_ReadByte(addr);
+		Dprintf(("HWput_b(0x%08x,0x%02x) at 0x%08x\n", addr, value, m68k_getpc()));
+		dsp_core_write_host(addr-DSP_HW_OFFSET, value);
+#endif
+		if (multi_access == true)
+			M68000_AddCycles(4);
+		multi_access = true;
 	}
 }