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1.1 root 1: /*
1.1.1.2 root 2: DSP M56001 emulation
3: Dummy emulation, Hatari glue
1.1 root 4:
1.1.1.2 root 5: (C) 2001-2008 ARAnyM developer team
6: Adaption to Hatari (C) 2008 by Thomas Huth
7:
8: This program is free software; you can redistribute it and/or modify
9: it under the terms of the GNU General Public License as published by
10: the Free Software Foundation; either version 2 of the License, or
11: (at your option) any later version.
12:
13: This program is distributed in the hope that it will be useful,
14: but WITHOUT ANY WARRANTY; without even the implied warranty of
15: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16: GNU General Public License for more details.
17:
18: You should have received a copy of the GNU General Public License
19: along with this program; if not, write to the Free Software
20: Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21: */
22:
1.1 root 23: #include "main.h"
24: #include "sysdeps.h"
1.1.1.2 root 25: #include "newcpu.h"
1.1.1.3 ! root 26: #include "memorySnapShot.h"
1.1 root 27: #include "ioMem.h"
28: #include "dsp.h"
1.1.1.3 ! root 29: #if ENABLE_DSP_EMU
! 30: #include "debugui.h"
! 31: #include "dsp_cpu.h"
! 32: #include "dsp_disasm.h"
! 33: #endif
1.1 root 34:
1.1.1.2 root 35: #define DEBUG 0
1.1.1.3 ! root 36: #if DEBUG
! 37: #define Dprintf(a) printf a
! 38: #else
! 39: #define Dprintf(a)
! 40: #endif
! 41:
! 42: #define BITMASK(x) ((1<<(x))-1)
1.1 root 43:
1.1.1.3 ! root 44: #define DSP_HW_OFFSET 0xFFA200
! 45:
! 46: #if ENABLE_DSP_EMU
1.1.1.2 root 47: static dsp_core_t dsp_core;
48: #endif
1.1.1.3 ! root 49: static bool bDspDebugging;
1.1 root 50:
1.1.1.3 ! root 51: bool bDspEnabled = false;
1.1 root 52:
53:
1.1.1.3 ! root 54: /**
! 55: * Initialize the DSP emulation
! 56: */
1.1 root 57: void DSP_Init(void)
58: {
1.1.1.3 ! root 59: #if ENABLE_DSP_EMU
1.1.1.2 root 60: dsp_core_init(&dsp_core);
1.1.1.3 ! root 61: dsp56k_init_cpu(&dsp_core);
! 62: bDspEnabled = true;
1.1 root 63: #endif
64: }
65:
1.1.1.3 ! root 66:
! 67: /**
! 68: * Shut down the DSP emulation
! 69: */
1.1 root 70: void DSP_UnInit(void)
71: {
1.1.1.3 ! root 72: #if ENABLE_DSP_EMU
1.1.1.2 root 73: dsp_core_shutdown(&dsp_core);
1.1.1.3 ! root 74: bDspEnabled = false;
1.1.1.2 root 75: #endif
1.1 root 76: }
77:
1.1.1.3 ! root 78:
! 79: /**
! 80: * Reset the DSP emulation
! 81: */
1.1 root 82: void DSP_Reset(void)
83: {
1.1.1.3 ! root 84: #if ENABLE_DSP_EMU
1.1.1.2 root 85: dsp_core_reset(&dsp_core);
1.1 root 86: #endif
87: }
88:
89:
1.1.1.3 ! root 90: /**
! 91: * Save/Restore snapshot of CPU variables ('MemorySnapShot_Store' handles type)
! 92: */
! 93: void DSP_MemorySnapShot_Capture(bool bSave)
! 94: {
! 95: #if ENABLE_DSP_EMU
! 96: if (!bSave)
! 97: DSP_Reset();
! 98:
! 99: MemorySnapShot_Store(&bDspEnabled, sizeof(bDspEnabled));
! 100: MemorySnapShot_Store(&dsp_core, sizeof(dsp_core));
! 101: #endif
! 102: }
! 103:
! 104:
! 105: /**
! 106: * Run DSP for certain cycles
! 107: */
! 108: void DSP_Run(int nHostCycles)
! 109: {
! 110: #if ENABLE_DSP_EMU
! 111: /* Cycles emulation is just a rough approximation by now.
! 112: * (to be tuned ...) */
! 113: int i = nHostCycles * 2 + 2;
! 114: int dsp_cycle = 0;
! 115:
! 116: while (dsp_core.running == 1 && i >= dsp_cycle)
! 117: {
! 118: if (unlikely(bDspDebugging))
! 119: DebugUI_DspCheck();
! 120:
! 121: dsp56k_execute_instruction();
! 122: dsp_cycle += dsp_core.instr_cycle;
! 123: }
! 124: #endif
! 125: }
! 126:
! 127: /**
! 128: * Enable/disable DSP debugging mode
! 129: */
! 130: void DSP_SetDebugging(bool enabled)
! 131: {
! 132: bDspDebugging = enabled;
! 133: }
! 134:
! 135: /**
! 136: * Get DSP program counter (for disassembler)
! 137: */
! 138: Uint16 DSP_GetPC(void)
! 139: {
! 140: #if ENABLE_DSP_EMU
! 141: if (bDspEnabled)
! 142: return dsp_core.pc;
! 143: else
! 144: #endif
! 145: return 0;
! 146: }
! 147:
! 148:
! 149: /**
! 150: * Disassemble DSP code between given addresses
! 151: */
! 152: Uint32 DSP_DisasmAddress(Uint16 lowerAdr, Uint16 UpperAdr)
! 153: {
! 154: #if ENABLE_DSP_EMU
! 155: Uint32 dsp_pc, save_curPC;
! 156:
! 157: save_curPC = dsp_core.pc;
! 158:
! 159: for (dsp_pc=lowerAdr; dsp_pc<=UpperAdr; dsp_pc++) {
! 160: dsp_core.pc = dsp_pc;
! 161: dsp_pc += dsp56k_disasm() - 1;
! 162: }
! 163: dsp_core.pc = save_curPC;
! 164: return dsp_pc;
! 165: #else
! 166: return 0;
! 167: #endif
! 168: }
! 169:
! 170:
! 171: /**
! 172: * Get the value from the given (16-bit) DSP memory address / space
! 173: * exactly the same way as in dsp_cpu.c::read_memory() (except for
! 174: * the host/transmit peripheral register values which access has
! 175: * side-effects). Set the mem_str to suitable string for that
! 176: * address / space.
! 177: * Return the value at given address. For valid values AND the return
! 178: * value with BITMASK(24).
! 179: */
! 180: Uint32 DSP_ReadMemory(Uint16 address, char space_id, const char **mem_str)
! 181: {
! 182: #if ENABLE_DSP_EMU
! 183: static const char *spaces[3][4] = {
! 184: { "X ram", "X rom", "X", "X periph" },
! 185: { "Y ram", "Y rom", "Y", "Y periph" },
! 186: { "P ram", "P ram", "P ext memory", "P ext memory" }
! 187: };
! 188: int idx, space;
! 189:
! 190: switch (space_id) {
! 191: case 'X':
! 192: space = DSP_SPACE_X;
! 193: idx = 0;
! 194: break;
! 195: case 'Y':
! 196: space = DSP_SPACE_Y;
! 197: idx = 1;
! 198: break;
! 199: case 'P':
! 200: space = DSP_SPACE_P;
! 201: idx = 2;
! 202: break;
! 203: default:
! 204: space = DSP_SPACE_X;
! 205: idx = 0;
! 206: }
! 207: address &= 0xFFFF;
! 208:
! 209: /* Internal RAM ? */
! 210: if (address < 0x100) {
! 211: *mem_str = spaces[idx][0];
! 212: return dsp_core.ramint[space][address];
! 213: }
! 214:
! 215: if (space == DSP_SPACE_P) {
! 216: /* Internal RAM ? */
! 217: if (address < 0x200) {
! 218: *mem_str = spaces[idx][0];
! 219: return dsp_core.ramint[DSP_SPACE_P][address];
! 220: }
! 221: /* External RAM, mask address to available ram size */
! 222: *mem_str = spaces[idx][2];
! 223: return dsp_core.ramext[address & (DSP_RAMSIZE-1)];
! 224: }
! 225:
! 226: /* Internal ROM ? */
! 227: if (address < 0x200) {
! 228: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
! 229: *mem_str = spaces[idx][1];
! 230: return dsp_core.rom[space][address];
! 231: }
! 232: }
! 233:
! 234: /* Peripheral address ? */
! 235: if (address >= 0xffc0) {
! 236: *mem_str = spaces[idx][3];
! 237: /* reading host/transmit regs has side-effects,
! 238: * so just give the memory value.
! 239: */
! 240: return dsp_core.periph[space][address-0xffc0];
! 241: }
! 242:
! 243: /* Falcon: External RAM, map X to upper 16K of matching space in Y,P */
! 244: address &= (DSP_RAMSIZE>>1) - 1;
! 245: if (space == DSP_SPACE_X) {
! 246: address += DSP_RAMSIZE>>1;
! 247: }
! 248:
! 249: /* Falcon: External RAM, finally map X,Y to P */
! 250: *mem_str = spaces[idx][2];
! 251: return dsp_core.ramext[address & (DSP_RAMSIZE-1)];
! 252: #endif
! 253: return 0;
! 254: }
! 255:
! 256:
! 257: /**
! 258: * Output memory values between given addresses in given DSP address space.
! 259: */
! 260: void DSP_DisasmMemory(Uint16 dsp_memdump_addr, Uint16 dsp_memdump_upper, char space)
! 261: {
! 262: #if ENABLE_DSP_EMU
! 263: Uint32 mem, mem2, value;
! 264: const char *mem_str;
! 265:
! 266: for (mem = dsp_memdump_addr; mem <= dsp_memdump_upper; mem++) {
! 267: /* special printing of host communication/transmit registers */
! 268: if (space == 'X' && (mem == 0xffeb || mem == 0xffef)) {
! 269: if (mem == 0xffeb) {
! 270: fprintf(stderr,"X periph:%04x HTX : %06x RTX:%06x\n",
! 271: mem, dsp_core.dsp_host_htx, dsp_core.dsp_host_rtx);
! 272: }
! 273: else if (mem == 0xffef) {
! 274: fprintf(stderr,"X periph:%04x SSI TX : %06x SSI RX:%06x\n",
! 275: mem, dsp_core.ssi.transmit_value, dsp_core.ssi.received_value);
! 276: }
! 277: continue;
! 278: }
! 279: /* special printing of X & Y external RAM values */
! 280: if ((space == 'X' || space == 'Y') &&
! 281: mem >= 0x200 && mem < 0xffc0) {
! 282: mem2 = mem & ((DSP_RAMSIZE>>1)-1);
! 283: if (space == 'X') {
! 284: mem2 += (DSP_RAMSIZE>>1);
! 285: }
! 286: fprintf(stderr,"%c:%04x (P:%04x): %06x\n", space,
! 287: mem, mem2, dsp_core.ramext[mem2 & (DSP_RAMSIZE-1)]);
! 288: continue;
! 289: }
! 290: value = DSP_ReadMemory(mem, space, &mem_str);
! 291: fprintf(stderr,"%s:%04x %06x\n", mem_str, mem, value);
! 292: }
! 293: #endif
! 294: }
! 295:
! 296:
! 297: void DSP_DisasmRegisters(void)
! 298: {
! 299: #if ENABLE_DSP_EMU
! 300: Uint32 i;
! 301:
! 302: fprintf(stderr,"A: A2: %02x A1: %06x A0: %06x\n",
! 303: dsp_core.registers[DSP_REG_A2], dsp_core.registers[DSP_REG_A1], dsp_core.registers[DSP_REG_A0]);
! 304: fprintf(stderr,"B: B2: %02x B1: %06x B0: %06x\n",
! 305: dsp_core.registers[DSP_REG_B2], dsp_core.registers[DSP_REG_B1], dsp_core.registers[DSP_REG_B0]);
! 306:
! 307: fprintf(stderr,"X: X1: %06x X0: %06x\n", dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0]);
! 308: fprintf(stderr,"Y: Y1: %06x Y0: %06x\n", dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0]);
! 309:
! 310: for (i=0; i<8; i++) {
! 311: fprintf(stderr,"R%01x: %04x N%01x: %04x M%01x: %04x\n",
! 312: i, dsp_core.registers[DSP_REG_R0+i],
! 313: i, dsp_core.registers[DSP_REG_N0+i],
! 314: i, dsp_core.registers[DSP_REG_M0+i]);
! 315: }
! 316:
! 317: fprintf(stderr,"LA: %04x LC: %04x PC: %04x\n", dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], dsp_core.pc);
! 318: fprintf(stderr,"SR: %04x OMR: %02x\n", dsp_core.registers[DSP_REG_SR], dsp_core.registers[DSP_REG_OMR]);
! 319: fprintf(stderr,"SP: %02x SSH: %04x SSL: %04x\n",
! 320: dsp_core.registers[DSP_REG_SP], dsp_core.registers[DSP_REG_SSH], dsp_core.registers[DSP_REG_SSL]);
! 321: #endif
! 322: }
! 323:
! 324:
! 325: /**
! 326: * Get given DSP register address and required bit mask.
! 327: * Works for A0-2, B0-2, LA, LC, M0-7, N0-7, R0-7, X0-1, Y0-1, PC, SR, SP,
! 328: * OMR, SSH & SSL registers, but note that the SP, SSH & SSL registers
! 329: * need special handling (in DSP*SetRegister()) when they are set.
! 330: * Return the register width in bits or zero for an error.
! 331: */
! 332: int DSP_GetRegisterAddress(const char *regname, Uint32 **addr, Uint32 *mask)
! 333: {
! 334: #if ENABLE_DSP_EMU
! 335: #define MAX_REGNAME_LEN 4
! 336: typedef struct {
! 337: const char name[MAX_REGNAME_LEN];
! 338: Uint32 *addr;
! 339: size_t bits;
! 340: Uint32 mask;
! 341: } reg_addr_t;
! 342:
! 343: /* sorted by name so that this can be bisected */
! 344: static const reg_addr_t registers[] = {
! 345:
! 346: /* 56-bit A register */
! 347: { "A0", &dsp_core.registers[DSP_REG_A0], 32, BITMASK(24) },
! 348: { "A1", &dsp_core.registers[DSP_REG_A1], 32, BITMASK(24) },
! 349: { "A2", &dsp_core.registers[DSP_REG_A2], 32, BITMASK(8) },
! 350:
! 351: /* 56-bit B register */
! 352: { "B0", &dsp_core.registers[DSP_REG_B0], 32, BITMASK(24) },
! 353: { "B1", &dsp_core.registers[DSP_REG_B1], 32, BITMASK(24) },
! 354: { "B2", &dsp_core.registers[DSP_REG_B2], 32, BITMASK(8) },
! 355:
! 356: /* 16-bit LA & LC registers */
! 357: { "LA", &dsp_core.registers[DSP_REG_LA], 32, BITMASK(16) },
! 358: { "LC", &dsp_core.registers[DSP_REG_LC], 32, BITMASK(16) },
! 359:
! 360: /* 16-bit M registers */
! 361: { "M0", &dsp_core.registers[DSP_REG_M0], 32, BITMASK(16) },
! 362: { "M1", &dsp_core.registers[DSP_REG_M1], 32, BITMASK(16) },
! 363: { "M2", &dsp_core.registers[DSP_REG_M2], 32, BITMASK(16) },
! 364: { "M3", &dsp_core.registers[DSP_REG_M3], 32, BITMASK(16) },
! 365: { "M4", &dsp_core.registers[DSP_REG_M4], 32, BITMASK(16) },
! 366: { "M5", &dsp_core.registers[DSP_REG_M5], 32, BITMASK(16) },
! 367: { "M6", &dsp_core.registers[DSP_REG_M6], 32, BITMASK(16) },
! 368: { "M7", &dsp_core.registers[DSP_REG_M7], 32, BITMASK(16) },
! 369:
! 370: /* 16-bit N registers */
! 371: { "N0", &dsp_core.registers[DSP_REG_N0], 32, BITMASK(16) },
! 372: { "N1", &dsp_core.registers[DSP_REG_N1], 32, BITMASK(16) },
! 373: { "N2", &dsp_core.registers[DSP_REG_N2], 32, BITMASK(16) },
! 374: { "N3", &dsp_core.registers[DSP_REG_N3], 32, BITMASK(16) },
! 375: { "N4", &dsp_core.registers[DSP_REG_N4], 32, BITMASK(16) },
! 376: { "N5", &dsp_core.registers[DSP_REG_N5], 32, BITMASK(16) },
! 377: { "N6", &dsp_core.registers[DSP_REG_N6], 32, BITMASK(16) },
! 378: { "N7", &dsp_core.registers[DSP_REG_N7], 32, BITMASK(16) },
! 379:
! 380: { "OMR", &dsp_core.registers[DSP_REG_OMR], 32, 0x5f },
! 381:
! 382: /* 16-bit program counter */
! 383: { "PC", (Uint32*)(&dsp_core.pc), 16, BITMASK(16) },
! 384:
! 385: /* 16-bit DSP R (address) registers */
! 386: { "R0", &dsp_core.registers[DSP_REG_R0], 32, BITMASK(16) },
! 387: { "R1", &dsp_core.registers[DSP_REG_R1], 32, BITMASK(16) },
! 388: { "R2", &dsp_core.registers[DSP_REG_R2], 32, BITMASK(16) },
! 389: { "R3", &dsp_core.registers[DSP_REG_R3], 32, BITMASK(16) },
! 390: { "R4", &dsp_core.registers[DSP_REG_R4], 32, BITMASK(16) },
! 391: { "R5", &dsp_core.registers[DSP_REG_R5], 32, BITMASK(16) },
! 392: { "R6", &dsp_core.registers[DSP_REG_R6], 32, BITMASK(16) },
! 393: { "R7", &dsp_core.registers[DSP_REG_R7], 32, BITMASK(16) },
! 394:
! 395: { "SSH", &dsp_core.registers[DSP_REG_SSH], 32, BITMASK(16) },
! 396: { "SSL", &dsp_core.registers[DSP_REG_SSL], 32, BITMASK(16) },
! 397: { "SP", &dsp_core.registers[DSP_REG_SP], 32, BITMASK(6) },
! 398:
! 399: /* 16-bit status register */
! 400: { "SR", &dsp_core.registers[DSP_REG_SR], 32, 0xefff },
! 401:
! 402: /* 48-bit X register */
! 403: { "X0", &dsp_core.registers[DSP_REG_X0], 32, BITMASK(24) },
! 404: { "X1", &dsp_core.registers[DSP_REG_X1], 32, BITMASK(24) },
! 405:
! 406: /* 48-bit Y register */
! 407: { "Y0", &dsp_core.registers[DSP_REG_Y0], 32, BITMASK(24) },
! 408: { "Y1", &dsp_core.registers[DSP_REG_Y1], 32, BITMASK(24) }
! 409: };
! 410: /* left, right, middle, direction */
! 411: int l, r, m, dir;
! 412: unsigned int i;
! 413: char reg[MAX_REGNAME_LEN];
! 414:
! 415: for (i = 0; i < sizeof(reg) && regname[i]; i++) {
! 416: reg[i] = toupper(regname[i]);
! 417: }
! 418: if (i < 2 || regname[i]) {
! 419: /* too short or longer than any of the names */
! 420: return 0;
! 421: }
! 422:
! 423: /* bisect */
! 424: l = 0;
! 425: r = sizeof (registers) / sizeof (*registers) - 1;
! 426: do {
! 427: m = (l+r) >> 1;
! 428: for (i = 0; i < sizeof(reg); i++) {
! 429: dir = (int)reg[i] - registers[m].name[i];
! 430: if (dir) {
! 431: break;
! 432: }
! 433: }
! 434: if (dir == 0) {
! 435: *addr = registers[m].addr;
! 436: *mask = registers[m].mask;
! 437: return registers[m].bits;
! 438: }
! 439: if (dir < 0) {
! 440: r = m-1;
! 441: } else {
! 442: l = m+1;
! 443: }
! 444: } while (l <= r);
! 445: #undef MAX_REGNAME_LEN
! 446: #endif
! 447: return 0;
! 448: }
! 449:
! 450:
! 451: /**
! 452: * Set given DSP register value
! 453: */
! 454: void DSP_Disasm_SetRegister(char *arg, Uint32 value)
! 455: {
! 456: #if ENABLE_DSP_EMU
! 457: Uint32 *addr, mask, sp_value;
! 458: int bits;
! 459:
! 460: /* first check registers needing special handling... */
! 461: if (arg[0]=='S' || arg[0]=='s') {
! 462: if (arg[1]=='P' || arg[1]=='p') {
! 463: dsp_core.registers[DSP_REG_SP] = value & BITMASK(6);
! 464: value &= BITMASK(4);
! 465: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][value];
! 466: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][value];
! 467: return;
! 468: }
! 469: if (arg[1]=='S' || arg[1]=='s') {
! 470: sp_value = dsp_core.registers[DSP_REG_SP] & BITMASK(4);
! 471: if (arg[2]=='H' || arg[2]=='h') {
! 472: if (sp_value == 0) {
! 473: dsp_core.registers[DSP_REG_SSH] = 0;
! 474: dsp_core.stack[0][sp_value] = 0;
! 475: } else {
! 476: dsp_core.registers[DSP_REG_SSH] = value & BITMASK(16);
! 477: dsp_core.stack[0][sp_value] = value & BITMASK(16);
! 478: }
! 479: return;
! 480: }
! 481: if (arg[2]=='L' || arg[2]=='l') {
! 482: if (sp_value == 0) {
! 483: dsp_core.registers[DSP_REG_SSL] = 0;
! 484: dsp_core.stack[1][sp_value] = 0;
! 485: } else {
! 486: dsp_core.registers[DSP_REG_SSL] = value & BITMASK(16);
! 487: dsp_core.stack[1][sp_value] = value & BITMASK(16);
! 488: }
! 489: return;
! 490: }
! 491: }
! 492: }
! 493:
! 494: /* ...then registers where address & mask are enough */
! 495: bits = DSP_GetRegisterAddress(arg, &addr, &mask);
! 496: switch (bits) {
! 497: case 32:
! 498: *addr = value & mask;
! 499: return;
! 500: case 16:
! 501: *(Uint16*)addr = value & mask;
! 502: return;
! 503: }
! 504: fprintf(stderr,"\tError, usage: reg=value where: \n\t \
! 505: reg=A0-A2, B0-B2, X0, X1, Y0, Y1, \n\t \
! 506: R0-R7, N0-N7, M0-M7, LA, LC, PC \n\t \
! 507: SR, SP, OMR, SSH, SSL \n\t \
! 508: and value is a hex value.\n");
! 509: #endif
! 510: }
! 511:
! 512: /**
! 513: * Read SSI transmit value
! 514: */
! 515: Uint32 DSP_SsiReadTxValue(void)
! 516: {
! 517: #if ENABLE_DSP_EMU
! 518: return dsp_core.ssi.transmit_value;
! 519: #else
! 520: return 0;
! 521: #endif
! 522: }
! 523:
! 524: /**
! 525: * Write SSI receive value
! 526: */
! 527: void DSP_SsiWriteRxValue(Uint32 value)
! 528: {
! 529: #if ENABLE_DSP_EMU
! 530: dsp_core.ssi.received_value = value & 0xffffff;
! 531: #endif
! 532: }
! 533:
! 534: /**
! 535: * Signal SSI clock tick to DSP
! 536: */
! 537: void DSP_SsiReceiveSerialClock(void)
! 538: {
! 539: #if ENABLE_DSP_EMU
! 540: dsp_core_ssi_receive_serial_clock(&dsp_core);
! 541: #endif
! 542: }
! 543:
! 544: void DSP_SsiReceive_SC2(Uint32 FrameCounter)
! 545: {
! 546: #if ENABLE_DSP_EMU
! 547: dsp_core_ssi_receive_SC2(&dsp_core, FrameCounter);
! 548: #endif
! 549: }
! 550:
! 551: /**
! 552: * Hardware IO address read by CPU
! 553: */
1.1.1.2 root 554: static Uint8 DSP_handleRead(Uint32 addr)
1.1 root 555: {
1.1.1.2 root 556: Uint8 value;
1.1.1.3 ! root 557: #if ENABLE_DSP_EMU
1.1.1.2 root 558: value = dsp_core_read_host(&dsp_core, addr-DSP_HW_OFFSET);
559: #else
560: /* this value prevents TOS from hanging in the DSP init code */
561: value = 0xff;
1.1 root 562: #endif
563:
1.1.1.3 ! root 564: Dprintf(("HWget_b(0x%08x)=0x%02x at 0x%08x\n", addr, value, m68k_getpc()));
1.1 root 565: return value;
566: }
567:
1.1.1.3 ! root 568: /**
! 569: * Read access wrapper for ioMemTabFalcon
! 570: */
1.1 root 571: void DSP_HandleReadAccess(void)
572: {
573: Uint32 a;
574: Uint8 v;
575: for (a = IoAccessBaseAddress; a < IoAccessBaseAddress+nIoMemAccessSize; a++)
576: {
577: v = DSP_handleRead(a);
578: IoMem_WriteByte(a, v);
579: }
580: }
581:
1.1.1.2 root 582:
1.1.1.3 ! root 583: /**
! 584: * Hardware IO address write by CPU
! 585: */
1.1.1.2 root 586: static void DSP_handleWrite(Uint32 addr, Uint8 value)
1.1 root 587: {
1.1.1.3 ! root 588: Dprintf(("HWput_b(0x%08x,0x%02x) at 0x%08x\n", addr, value, m68k_getpc()));
! 589: #if ENABLE_DSP_EMU
1.1.1.2 root 590: dsp_core_write_host(&dsp_core, addr-DSP_HW_OFFSET, value);
1.1 root 591: #endif
592: }
593:
1.1.1.3 ! root 594: /**
! 595: * Write access wrapper for ioMemTabFalcon
! 596: */
1.1 root 597: void DSP_HandleWriteAccess(void)
598: {
599: Uint32 a;
600: Uint8 v;
601: for (a = IoAccessBaseAddress; a < IoAccessBaseAddress+nIoMemAccessSize; a++)
602: {
603: v = IoMem_ReadByte(a);
604: DSP_handleWrite(a,v);
605: }
606: }
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