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1.1 root 1: /*
2: * dsp.h - Atari DSP56001 emulation code - declaration
3: *
4: * Copyright (c) 2001-2004 Petr Stehlik of ARAnyM dev team
5: * Adaption to Hatari (C) 2006 by Thomas Huth
6: *
7: * This program is free software; you can redistribute it and/or modify
8: * it under the terms of the GNU General Public License as published by
9: * the Free Software Foundation; either version 2 of the License, or
10: * (at your option) any later version.
11: *
12: * This program is distributed in the hope that it will be useful,
13: * but WITHOUT ANY WARRANTY; without even the implied warranty of
14: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: * GNU General Public License for more details.
16: *
17: * You should have received a copy of the GNU General Public License
18: * along with ARAnyM; if not, write to the Free Software
19: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20: */
21:
22: #ifndef _DSP_H
23: #define _DSP_H
24:
25: #include <SDL.h>
26: #include "araglue.h"
27:
28: #define DSP_RAMSIZE 32768
29:
30: /* Dsp State */
31: #define DSP_BOOTING 0 /* Dsp loads bootstrap code */
32: #define DSP_RUNNING 1 /* Execute instructions */
33: #define DSP_WAITHOSTWRITE 2 /* Dsp waits for host to write data */
34: #define DSP_WAITHOSTREAD 3 /* Dsp waits for host to read data */
35: #define DSP_HALT 4 /* Dsp is halted */
36: #define DSP_STOPTHREAD 5 /* Stop emulation thread */
37: #define DSP_STOPPEDTHREAD 6 /* Dsp thread stopped and finished */
38:
39: /* Host port, CPU side */
40: #define CPU_HOST_ICR 0x00
41: #define CPU_HOST_CVR 0x01
42: #define CPU_HOST_ISR 0x02
43: #define CPU_HOST_IVR 0x03
44: #define CPU_HOST_RX0 0x04
45: #define CPU_HOST_RXH 0x05
46: #define CPU_HOST_RXM 0x06
47: #define CPU_HOST_RXL 0x07
48: #define CPU_HOST_TX0 0x04
49: #define CPU_HOST_TXH 0x05
50: #define CPU_HOST_TXM 0x06
51: #define CPU_HOST_TXL 0x07
52:
53: #define CPU_HOST_ICR_RREQ 0x00
54: #define CPU_HOST_ICR_TREQ 0x01
55: #define CPU_HOST_ICR_HF0 0x03
56: #define CPU_HOST_ICR_HF1 0x04
57: #define CPU_HOST_ICR_HM0 0x05
58: #define CPU_HOST_ICR_HM1 0x06
59: #define CPU_HOST_ICR_INIT 0x07
60:
61: #define CPU_HOST_CVR_HC 0x07
62:
63: #define CPU_HOST_ISR_RXDF 0x00
64: #define CPU_HOST_ISR_TXDE 0x01
65: #define CPU_HOST_ISR_TRDY 0x02
66: #define CPU_HOST_ISR_HF2 0x03
67: #define CPU_HOST_ISR_HF3 0x04
68: #define CPU_HOST_ISR_DMA 0x06
69: #define CPU_HOST_ISR_HREQ 0x07
70:
71: /* Host port, DSP side, DSP addresses are 0xffc0+value */
72: #define DSP_PBC 0x20 /* Port B control register */
73: #define DSP_PCC 0x21 /* Port C control register */
74: #define DSP_PBDDR 0x22 /* Port B data direction register */
75: #define DSP_PCDDR 0x23 /* Port C data direction register */
76: #define DSP_PBD 0x24 /* Port B data register */
77: #define DSP_PCD 0x25 /* Port C data register */
78: #define DSP_HOST_HCR 0x28 /* Host control register */
79: #define DSP_HOST_HSR 0x29 /* Host status register */
80: #define DSP_HOST_HRX 0x2b /* Host receive register */
81: #define DSP_HOST_HTX 0x2b /* Host transmit register */
82: #define DSP_SSI_CRA 0x2c /* Ssi control register A */
83: #define DSP_SSI_CRB 0x2d /* Ssi control register B */
84: #define DSP_SSI_SR 0x2e /* Ssi status register */
85: #define DSP_SSI_TSR 0x2e /* Ssi time slot register */
86: #define DSP_SSI_RX 0x2f /* Ssi receive register */
87: #define DSP_SSI_TX 0x2f /* Ssi transmit register */
88: #define DSP_BCR 0x3e /* Port A bus control register */
89: #define DSP_IPR 0x3f /* Interrupt priority register */
90:
91: #define DSP_HOST_HCR_HRIE 0x00
92: #define DSP_HOST_HCR_HTIE 0x01
93: #define DSP_HOST_HCR_HCIE 0x02
94: #define DSP_HOST_HCR_HF2 0x03
95: #define DSP_HOST_HCR_HF3 0x04
96:
97: #define DSP_HOST_HSR_HRDF 0x00
98: #define DSP_HOST_HSR_HTDE 0x01
99: #define DSP_HOST_HSR_HCP 0x02
100: #define DSP_HOST_HSR_HF0 0x03
101: #define DSP_HOST_HSR_HF1 0x04
102: #define DSP_HOST_HSR_DMA 0x07
103:
104:
105: /* DSP state */
106: extern uint8 dsp_state;
107:
108: /* Registers */
109: extern uint16 dsp_pc;
110: extern uint32 dsp_registers[64];
111:
112: /* stack[0=ssh], stack[1=ssl] */
113: extern uint16 dsp_stack[2][15];
114:
115: /* ram[0] is x:, ram[1] is y:, ram[2] is p: */
116: extern uint32 dsp_ram[3][DSP_RAMSIZE];
117:
118: /* rom[0] is x:, rom[1] is y: */
119: extern uint32 dsp_rom[2][512];
120:
121: /* peripheral space, [x|y]:0xffc0-0xffff */
122: extern uint32 dsp_periph[2][64];
123:
124: /* host port, CPU side */
125: extern uint8 dsp_hostport[8];
126:
127: /* Misc */
128: extern uint32 dsp_loop_rep; /* executing rep ? */
129: extern uint32 dsp_last_loop_inst; /* executing the last instruction in DO ? */
130: extern uint32 dsp_first_host_write; /* first byte written to host port */
131:
132: extern SDL_sem *dsp56k_sem;
133:
134:
135: void DSP_HandleReadAccess(void);
136: void DSP_HandleWriteAccess(void);
137:
138: extern void DSP_Init(void);
139: extern void DSP_UnInit(void);
140:
141: /* Setup functions */
142: extern void DSP_Reset(void);
143: extern void DSP_shutdown(void);
144:
145: /* Host port transfer */
146: extern void DSP_host2dsp(void);
147: extern void DSP_dsp2host(void);
148:
149:
150: #endif /* _DSP_H */
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