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1.1 root 1: /*
2: DSP M56001 emulation
3: Host/Emulator <-> DSP glue
4:
5: (C) 2003-2008 ARAnyM developer team
6:
7: This program is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2 of the License, or
10: (at your option) any later version.
11:
12: This program is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
1.1.1.9 root 18: along with this program; if not, write to the Free Software Foundation,
19: 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335 USA
1.1 root 20: */
21:
22: #ifdef HAVE_CONFIG_H
23: #include "config.h"
24: #endif
25:
1.1.1.7 root 26: #include <stdio.h>
1.1 root 27: #include <string.h>
1.1.1.4 root 28: #include <math.h>
1.1 root 29:
30: #include "dsp_core.h"
31: #include "dsp_cpu.h"
1.1.1.3 root 32: #include "ioMem.h"
33: #include "dsp.h"
1.1.1.4 root 34: #include "log.h"
1.1.1.3 root 35:
1.1.1.4 root 36: /*--- the DSP core itself ---*/
37: dsp_core_t dsp_core;
1.1 root 38:
1.1.1.2 root 39: /*--- Defines ---*/
1.1 root 40: #ifndef M_PI
41: #define M_PI 3.141592653589793238462643383279502
42: #endif
43:
1.1.1.2 root 44: /*--- Functions prototypes ---*/
1.1.1.4 root 45: static void dsp_core_dsp2host(void);
46: static void dsp_core_host2dsp(void);
1.1 root 47:
1.1.1.8 root 48: static void (*dsp_host_interrupt)(int); /* Function to set/clear host interrupt */
1.1.1.3 root 49:
1.1.1.10! root 50: static Uint32 const x_rom[0x100] = {
! 51: /* mulaw table */
! 52: /* M_00 */ 0x7D7C00, /* 8031 */
! 53: /* M_01 */ 0x797C00, /* 7775 */
! 54: /* M_02 */ 0x757C00, /* 7519 */
! 55: /* M_03 */ 0x717C00, /* 7263 */
! 56: /* M_04 */ 0x6D7C00, /* 7007 */
! 57: /* M_05 */ 0x697C00, /* 6751 */
! 58: /* M_06 */ 0x657C00, /* 6495 */
! 59: /* M_07 */ 0x617C00, /* 6239 */
! 60: /* M_08 */ 0x5D7C00, /* 5983 */
! 61: /* M_09 */ 0x597C00, /* 5727 */
! 62: /* M_0A */ 0x557C00, /* 5471 */
! 63: /* M_0B */ 0x517C00, /* 5215 */
! 64: /* M_0C */ 0x4D7C00, /* 4959 */
! 65: /* M_0D */ 0x497C00, /* 4703 */
! 66: /* M_0E */ 0x457C00, /* 4447 */
! 67: /* M_0F */ 0x417C00, /* 4191 */
! 68: /* M_10 */ 0x3E7C00, /* 3999 */
! 69: /* M_11 */ 0x3C7C00, /* 3871 */
! 70: /* M_12 */ 0x3A7C00, /* 3743 */
! 71: /* M_13 */ 0x387C00, /* 3615 */
! 72: /* M_14 */ 0x367C00, /* 3487 */
! 73: /* M_15 */ 0x347C00, /* 3359 */
! 74: /* M_16 */ 0x327C00, /* 3231 */
! 75: /* M_17 */ 0x307C00, /* 3103 */
! 76: /* M_18 */ 0x2E7C00, /* 2975 */
! 77: /* M_19 */ 0x2C7C00, /* 2847 */
! 78: /* M_1A */ 0x2A7C00, /* 2719 */
! 79: /* M_1B */ 0x287C00, /* 2591 */
! 80: /* M_1C */ 0x267C00, /* 2463 */
! 81: /* M_1D */ 0x247C00, /* 2335 */
! 82: /* M_1E */ 0x227C00, /* 2207 */
! 83: /* M_1F */ 0x207C00, /* 2079 */
! 84: /* M_20 */ 0x1EFC00, /* 1983 */
! 85: /* M_21 */ 0x1DFC00, /* 1919 */
! 86: /* M_22 */ 0x1CFC00, /* 1855 */
! 87: /* M_23 */ 0x1BFC00, /* 1791 */
! 88: /* M_24 */ 0x1AFC00, /* 1727 */
! 89: /* M_25 */ 0x19FC00, /* 1663 */
! 90: /* M_26 */ 0x18FC00, /* 1599 */
! 91: /* M_27 */ 0x17FC00, /* 1535 */
! 92: /* M_28 */ 0x16FC00, /* 1471 */
! 93: /* M_29 */ 0x15FC00, /* 1407 */
! 94: /* M_2A */ 0x14FC00, /* 1343 */
! 95: /* M_2B */ 0x13FC00, /* 1279 */
! 96: /* M_2C */ 0x12FC00, /* 1215 */
! 97: /* M_2D */ 0x11FC00, /* 1151 */
! 98: /* M_2E */ 0x10FC00, /* 1087 */
! 99: /* M_2F */ 0x0FFC00, /* 1023 */
! 100: /* M_30 */ 0x0F3C00, /* 975 */
! 101: /* M_31 */ 0x0EBC00, /* 943 */
! 102: /* M_32 */ 0x0E3C00, /* 911 */
! 103: /* M_33 */ 0x0DBC00, /* 879 */
! 104: /* M_34 */ 0x0D3C00, /* 847 */
! 105: /* M_35 */ 0x0CBC00, /* 815 */
! 106: /* M_36 */ 0x0C3C00, /* 783 */
! 107: /* M_37 */ 0x0BBC00, /* 751 */
! 108: /* M_38 */ 0x0B3C00, /* 719 */
! 109: /* M_39 */ 0x0ABC00, /* 687 */
! 110: /* M_3A */ 0x0A3C00, /* 655 */
! 111: /* M_3B */ 0x09BC00, /* 623 */
! 112: /* M_3C */ 0x093C00, /* 591 */
! 113: /* M_3D */ 0x08BC00, /* 559 */
! 114: /* M_3E */ 0x083C00, /* 527 */
! 115: /* M_3F */ 0x07BC00, /* 495 */
! 116: /* M_40 */ 0x075C00, /* 471 */
! 117: /* M_41 */ 0x071C00, /* 455 */
! 118: /* M_42 */ 0x06DC00, /* 439 */
! 119: /* M_43 */ 0x069C00, /* 423 */
! 120: /* M_44 */ 0x065C00, /* 407 */
! 121: /* M_45 */ 0x061C00, /* 391 */
! 122: /* M_46 */ 0x05DC00, /* 375 */
! 123: /* M_47 */ 0x059C00, /* 359 */
! 124: /* M_48 */ 0x055C00, /* 343 */
! 125: /* M_49 */ 0x051C00, /* 327 */
! 126: /* M_4A */ 0x04DC00, /* 311 */
! 127: /* M_4B */ 0x049C00, /* 295 */
! 128: /* M_4C */ 0x045C00, /* 279 */
! 129: /* M_4D */ 0x041C00, /* 263 */
! 130: /* M_4E */ 0x03DC00, /* 247 */
! 131: /* M_4F */ 0x039C00, /* 231 */
! 132: /* M_50 */ 0x036C00, /* 219 */
! 133: /* M_51 */ 0x034C00, /* 211 */
! 134: /* M_52 */ 0x032C00, /* 203 */
! 135: /* M_53 */ 0x030C00, /* 195 */
! 136: /* M_54 */ 0x02EC00, /* 187 */
! 137: /* M_55 */ 0x02CC00, /* 179 */
! 138: /* M_56 */ 0x02AC00, /* 171 */
! 139: /* M_57 */ 0x028C00, /* 163 */
! 140: /* M_58 */ 0x026C00, /* 155 */
! 141: /* M_59 */ 0x024C00, /* 147 */
! 142: /* M_5A */ 0x022C00, /* 139 */
! 143: /* M_5B */ 0x020C00, /* 131 */
! 144: /* M_5C */ 0x01EC00, /* 123 */
! 145: /* M_5D */ 0x01CC00, /* 115 */
! 146: /* M_5E */ 0x01AC00, /* 107 */
! 147: /* M_5F */ 0x018C00, /* 99 */
! 148: /* M_60 */ 0x017400, /* 93 */
! 149: /* M_61 */ 0x016400, /* 89 */
! 150: /* M_62 */ 0x015400, /* 85 */
! 151: /* M_63 */ 0x014400, /* 81 */
! 152: /* M_64 */ 0x013400, /* 77 */
! 153: /* M_65 */ 0x012400, /* 73 */
! 154: /* M_66 */ 0x011400, /* 69 */
! 155: /* M_67 */ 0x010400, /* 65 */
! 156: /* M_68 */ 0x00F400, /* 61 */
! 157: /* M_69 */ 0x00E400, /* 57 */
! 158: /* M_6A */ 0x00D400, /* 53 */
! 159: /* M_6B */ 0x00C400, /* 49 */
! 160: /* M_6C */ 0x00B400, /* 45 */
! 161: /* M_6D */ 0x00A400, /* 41 */
! 162: /* M_6E */ 0x009400, /* 37 */
! 163: /* M_6F */ 0x008400, /* 33 */
! 164: /* M_70 */ 0x007800, /* 30 */
! 165: /* M_71 */ 0x007000, /* 28 */
! 166: /* M_72 */ 0x006800, /* 26 */
! 167: /* M_73 */ 0x006000, /* 24 */
! 168: /* M_74 */ 0x005800, /* 22 */
! 169: /* M_75 */ 0x005000, /* 20 */
! 170: /* M_76 */ 0x004800, /* 18 */
! 171: /* M_77 */ 0x004000, /* 16 */
! 172: /* M_78 */ 0x003800, /* 14 */
! 173: /* M_79 */ 0x003000, /* 12 */
! 174: /* M_7A */ 0x002800, /* 10 */
! 175: /* M_7B */ 0x002000, /* 8 */
! 176: /* M_7C */ 0x001800, /* 6 */
! 177: /* M_7D */ 0x001000, /* 4 */
! 178: /* M_7E */ 0x000800, /* 2 */
! 179: /* M_7F */ 0x000000, /* 0 */
! 180:
! 181: /* a-law table */
! 182: /* A_80 */ 0x158000, /* 688 */
! 183: /* A_81 */ 0x148000, /* 656 */
! 184: /* A_82 */ 0x178000, /* 752 */
! 185: /* A_83 */ 0x168000, /* 720 */
! 186: /* A_84 */ 0x118000, /* 560 */
! 187: /* A_85 */ 0x108000, /* 528 */
! 188: /* A_86 */ 0x138000, /* 624 */
! 189: /* A_87 */ 0x128000, /* 592 */
! 190: /* A_88 */ 0x1D8000, /* 944 */
! 191: /* A_89 */ 0x1C8000, /* 912 */
! 192: /* A_8A */ 0x1F8000, /* 1008 */
! 193: /* A_8B */ 0x1E8000, /* 976 */
! 194: /* A_8C */ 0x198000, /* 816 */
! 195: /* A_8D */ 0x188000, /* 784 */
! 196: /* A_8E */ 0x1B8000, /* 880 */
! 197: /* A_8F */ 0x1A8000, /* 848 */
! 198: /* A_90 */ 0x0AC000, /* 344 */
! 199: /* A_91 */ 0x0A4000, /* 328 */
! 200: /* A_92 */ 0x0BC000, /* 376 */
! 201: /* A_93 */ 0x0B4000, /* 360 */
! 202: /* A_94 */ 0x08C000, /* 280 */
! 203: /* A_95 */ 0x084000, /* 264 */
! 204: /* A_96 */ 0x09C000, /* 312 */
! 205: /* A_97 */ 0x094000, /* 296 */
! 206: /* A_98 */ 0x0EC000, /* 472 */
! 207: /* A_99 */ 0x0E4000, /* 456 */
! 208: /* A_9A */ 0x0FC000, /* 504 */
! 209: /* A_9B */ 0x0F4000, /* 488 */
! 210: /* A_9C */ 0x0CC000, /* 408 */
! 211: /* A_9D */ 0x0C4000, /* 392 */
! 212: /* A_9E */ 0x0DC000, /* 440 */
! 213: /* A_9F */ 0x0D4000, /* 424 */
! 214: /* A_A0 */ 0x560000, /* 2752 */
! 215: /* A_A1 */ 0x520000, /* 2624 */
! 216: /* A_A2 */ 0x5E0000, /* 3008 */
! 217: /* A_A3 */ 0x5A0000, /* 2880 */
! 218: /* A_A4 */ 0x460000, /* 2240 */
! 219: /* A_A5 */ 0x420000, /* 2112 */
! 220: /* A_A6 */ 0x4E0000, /* 2496 */
! 221: /* A_A7 */ 0x4A0000, /* 2368 */
! 222: /* A_A8 */ 0x760000, /* 3776 */
! 223: /* A_A9 */ 0x720000, /* 3648 */
! 224: /* A_AA */ 0x7E0000, /* 4032 */
! 225: /* A_AB */ 0x7A0000, /* 3904 */
! 226: /* A_AC */ 0x660000, /* 3264 */
! 227: /* A_AD */ 0x620000, /* 3136 */
! 228: /* A_AE */ 0x6E0000, /* 3520 */
! 229: /* A_AF */ 0x6A0000, /* 3392 */
! 230: /* A_B0 */ 0x2B0000, /* 1376 */
! 231: /* A_B1 */ 0x290000, /* 1312 */
! 232: /* A_B2 */ 0x2F0000, /* 1504 */
! 233: /* A_B3 */ 0x2D0000, /* 1440 */
! 234: /* A_B4 */ 0x230000, /* 1120 */
! 235: /* A_B5 */ 0x210000, /* 1056 */
! 236: /* A_B6 */ 0x270000, /* 1248 */
! 237: /* A_B7 */ 0x250000, /* 1184 */
! 238: /* A_B8 */ 0x3B0000, /* 1888 */
! 239: /* A_B9 */ 0x390000, /* 1824 */
! 240: /* A_BA */ 0x3F0000, /* 2016 */
! 241: /* A_BB */ 0x3D0000, /* 1952 */
! 242: /* A_BC */ 0x330000, /* 1632 */
! 243: /* A_BD */ 0x310000, /* 1568 */
! 244: /* A_BE */ 0x370000, /* 1760 */
! 245: /* A_BF */ 0x350000, /* 1696 */
! 246: /* A_C0 */ 0x015800, /* 43 */
! 247: /* A_C1 */ 0x014800, /* 41 */
! 248: /* A_C2 */ 0x017800, /* 47 */
! 249: /* A_C3 */ 0x016800, /* 45 */
! 250: /* A_C4 */ 0x011800, /* 35 */
! 251: /* A_C5 */ 0x010800, /* 33 */
! 252: /* A_C6 */ 0x013800, /* 39 */
! 253: /* A_C7 */ 0x012800, /* 37 */
! 254: /* A_C8 */ 0x01D800, /* 59 */
! 255: /* A_C9 */ 0x01C800, /* 57 */
! 256: /* A_CA */ 0x01F800, /* 63 */
! 257: /* A_CB */ 0x01E800, /* 61 */
! 258: /* A_CC */ 0x019800, /* 51 */
! 259: /* A_CD */ 0x018800, /* 49 */
! 260: /* A_CE */ 0x01B800, /* 55 */
! 261: /* A_CF */ 0x01A800, /* 53 */
! 262: /* A_D0 */ 0x005800, /* 11 */
! 263: /* A_D1 */ 0x004800, /* 9 */
! 264: /* A_D2 */ 0x007800, /* 15 */
! 265: /* A_D3 */ 0x006800, /* 13 */
! 266: /* A_D4 */ 0x001800, /* 3 */
! 267: /* A_D5 */ 0x000800, /* 1 */
! 268: /* A_D6 */ 0x003800, /* 7 */
! 269: /* A_D7 */ 0x002800, /* 5 */
! 270: /* A_D8 */ 0x00D800, /* 27 */
! 271: /* A_D9 */ 0x00C800, /* 25 */
! 272: /* A_DA */ 0x00F800, /* 31 */
! 273: /* A_DB */ 0x00E800, /* 29 */
! 274: /* A_DC */ 0x009800, /* 19 */
! 275: /* A_DD */ 0x008800, /* 17 */
! 276: /* A_DE */ 0x00B800, /* 23 */
! 277: /* A_DF */ 0x00A800, /* 21 */
! 278: /* A_E0 */ 0x056000, /* 172 */
! 279: /* A_E1 */ 0x052000, /* 164 */
! 280: /* A_E2 */ 0x05E000, /* 188 */
! 281: /* A_E3 */ 0x05A000, /* 180 */
! 282: /* A_E4 */ 0x046000, /* 140 */
! 283: /* A_E5 */ 0x042000, /* 132 */
! 284: /* A_E6 */ 0x04E000, /* 156 */
! 285: /* A_E7 */ 0x04A000, /* 148 */
! 286: /* A_E8 */ 0x076000, /* 236 */
! 287: /* A_E9 */ 0x072000, /* 228 */
! 288: /* A_EA */ 0x07E000, /* 252 */
! 289: /* A_EB */ 0x07A000, /* 244 */
! 290: /* A_EC */ 0x066000, /* 204 */
! 291: /* A_ED */ 0x062000, /* 196 */
! 292: /* A_EE */ 0x06E000, /* 220 */
! 293: /* A_EF */ 0x06A000, /* 212 */
! 294: /* A_F0 */ 0x02B000, /* 86 */
! 295: /* A_F1 */ 0x029000, /* 82 */
! 296: /* A_F2 */ 0x02F000, /* 94 */
! 297: /* A_F3 */ 0x02D000, /* 90 */
! 298: /* A_F4 */ 0x023000, /* 70 */
! 299: /* A_F5 */ 0x021000, /* 66 */
! 300: /* A_F6 */ 0x027000, /* 78 */
! 301: /* A_F7 */ 0x025000, /* 74 */
! 302: /* A_F8 */ 0x03B000, /* 118 */
! 303: /* A_F9 */ 0x039000, /* 114 */
! 304: /* A_FA */ 0x03F000, /* 126 */
! 305: /* A_FB */ 0x03D000, /* 122 */
! 306: /* A_FC */ 0x033000, /* 102 */
! 307: /* A_FD */ 0x031000, /* 98 */
! 308: /* A_FE */ 0x037000, /* 110 */
! 309: /* A_FF */ 0x035000 /* 106 */
! 310: };
! 311:
! 312: /* sin table */
! 313: static Uint32 const y_rom[0x100] = {
! 314: /* S_00 */ 0x000000, /* +0.0000000000 */
! 315: /* S_01 */ 0x03242b, /* +0.0245412588 */
! 316: /* S_02 */ 0x0647d9, /* +0.0490676165 */
! 317: /* S_03 */ 0x096a90, /* +0.0735645294 */
! 318: /* S_04 */ 0x0c8bd3, /* +0.0980170965 */
! 319: /* S_05 */ 0x0fab27, /* +0.1224106550 */
! 320: /* S_06 */ 0x12c810, /* +0.1467304230 */
! 321: /* S_07 */ 0x15e214, /* +0.1709618568 */
! 322: /* S_08 */ 0x18f8b8, /* +0.1950902939 */
! 323: /* S_09 */ 0x1c0b82, /* +0.2191011906 */
! 324: /* S_0A */ 0x1f19f9, /* +0.2429801226 */
! 325: /* S_0B */ 0x2223a5, /* +0.2667127848 */
! 326: /* S_0C */ 0x25280c, /* +0.2902846336 */
! 327: /* S_0D */ 0x2826b9, /* +0.3136817217 */
! 328: /* S_0E */ 0x2b1f35, /* +0.3368898630 */
! 329: /* S_0F */ 0x2e110a, /* +0.3598949909 */
! 330: /* S_10 */ 0x30fbc5, /* +0.3826833963 */
! 331: /* S_11 */ 0x33def3, /* +0.4052413702 */
! 332: /* S_12 */ 0x36ba20, /* +0.4275550842 */
! 333: /* S_13 */ 0x398cdd, /* +0.4496113062 */
! 334: /* S_14 */ 0x3c56ba, /* +0.4713966846 */
! 335: /* S_15 */ 0x3f174a, /* +0.4928982258 */
! 336: /* S_16 */ 0x41ce1e, /* +0.5141026974 */
! 337: /* S_17 */ 0x447acd, /* +0.5349975824 */
! 338: /* S_18 */ 0x471ced, /* +0.5555702448 */
! 339: /* S_19 */ 0x49b415, /* +0.5758081675 */
! 340: /* S_1A */ 0x4c3fe0, /* +0.5956993103 */
! 341: /* S_1B */ 0x4ebfe9, /* +0.6152316332 */
! 342: /* S_1C */ 0x5133cd, /* +0.6343933344 */
! 343: /* S_1D */ 0x539b2b, /* +0.6531728506 */
! 344: /* S_1E */ 0x55f5a5, /* +0.6715589762 */
! 345: /* S_1F */ 0x5842dd, /* +0.6895405054 */
! 346: /* S_20 */ 0x5a827a, /* +0.7071068287 */
! 347: /* S_21 */ 0x5cb421, /* +0.7242470980 */
! 348: /* S_22 */ 0x5ed77d, /* +0.7409511805 */
! 349: /* S_23 */ 0x60ec38, /* +0.7572088242 */
! 350: /* S_24 */ 0x62f202, /* +0.7730104923 */
! 351: /* S_25 */ 0x64e889, /* +0.7883464098 */
! 352: /* S_26 */ 0x66cf81, /* +0.8032075167 */
! 353: /* S_27 */ 0x68a69f, /* +0.8175848722 */
! 354: /* S_28 */ 0x6a6d99, /* +0.8314696550 */
! 355: /* S_29 */ 0x6c2429, /* +0.8448535204 */
! 356: /* S_2A */ 0x6dca0d, /* +0.8577286005 */
! 357: /* S_2B */ 0x6f5f03, /* +0.8700870275 */
! 358: /* S_2C */ 0x70e2cc, /* +0.8819212914 */
! 359: /* S_2D */ 0x72552d, /* +0.8932243586 */
! 360: /* S_2E */ 0x73b5ec, /* +0.9039893150 */
! 361: /* S_2F */ 0x7504d3, /* +0.9142097235 */
! 362: /* S_30 */ 0x7641af, /* +0.9238795042 */
! 363: /* S_31 */ 0x776c4f, /* +0.9329928160 */
! 364: /* S_32 */ 0x788484, /* +0.9415440559 */
! 365: /* S_33 */ 0x798a24, /* +0.9495282173 */
! 366: /* S_34 */ 0x7a7d05, /* +0.9569402933 */
! 367: /* S_35 */ 0x7b5d04, /* +0.9637761116 */
! 368: /* S_36 */ 0x7c29fc, /* +0.9700312614 */
! 369: /* S_37 */ 0x7ce3cf, /* +0.9757021666 */
! 370: /* S_38 */ 0x7d8a5f, /* +0.9807852507 */
! 371: /* S_39 */ 0x7e1d94, /* +0.9852776527 */
! 372: /* S_3A */ 0x7e9d56, /* +0.9891765118 */
! 373: /* S_3B */ 0x7f0992, /* +0.9924795628 */
! 374: /* S_3C */ 0x7f6237, /* +0.9951847792 */
! 375: /* S_3D */ 0x7fa737, /* +0.9972904921 */
! 376: /* S_3E */ 0x7fd888, /* +0.9987955093 */
! 377: /* S_3F */ 0x7ff622, /* +0.9996988773 */
! 378: /* S_40 */ 0x7fffff, /* +1.0000000000 */
! 379: /* S_41 */ 0x7ff622, /* +0.9996988773 */
! 380: /* S_42 */ 0x7fd888, /* +0.9987955093 */
! 381: /* S_43 */ 0x7fa737, /* +0.9972904921 */
! 382: /* S_44 */ 0x7f6237, /* +0.9951847792 */
! 383: /* S_45 */ 0x7f0992, /* +0.9924795628 */
! 384: /* S_46 */ 0x7e9d56, /* +0.9891765118 */
! 385: /* S_47 */ 0x7e1d94, /* +0.9852776527 */
! 386: /* S_48 */ 0x7d8a5f, /* +0.9807852507 */
! 387: /* S_49 */ 0x7ce3cf, /* +0.9757021666 */
! 388: /* S_4A */ 0x7c29fc, /* +0.9700312614 */
! 389: /* S_4B */ 0x7b5d04, /* +0.9637761116 */
! 390: /* S_4C */ 0x7a7d05, /* +0.9569402933 */
! 391: /* S_4D */ 0x798a24, /* +0.9495282173 */
! 392: /* S_4E */ 0x788484, /* +0.9415440559 */
! 393: /* S_4F */ 0x776c4f, /* +0.9329928160 */
! 394: /* S_50 */ 0x7641af, /* +0.9238795042 */
! 395: /* S_51 */ 0x7504d3, /* +0.9142097235 */
! 396: /* S_52 */ 0x73b5ec, /* +0.9039893150 */
! 397: /* S_53 */ 0x72552d, /* +0.8932243586 */
! 398: /* S_54 */ 0x70e2cc, /* +0.8819212914 */
! 399: /* S_55 */ 0x6f5f03, /* +0.8700870275 */
! 400: /* S_56 */ 0x6dca0d, /* +0.8577286005 */
! 401: /* S_57 */ 0x6c2429, /* +0.8448535204 */
! 402: /* S_58 */ 0x6a6d99, /* +0.8314696550 */
! 403: /* S_59 */ 0x68a69f, /* +0.8175848722 */
! 404: /* S_5A */ 0x66cf81, /* +0.8032075167 */
! 405: /* S_5B */ 0x64e889, /* +0.7883464098 */
! 406: /* S_5C */ 0x62f202, /* +0.7730104923 */
! 407: /* S_5D */ 0x60ec38, /* +0.7572088242 */
! 408: /* S_5E */ 0x5ed77d, /* +0.7409511805 */
! 409: /* S_5F */ 0x5cb421, /* +0.7242470980 */
! 410: /* S_60 */ 0x5a827a, /* +0.7071068287 */
! 411: /* S_61 */ 0x5842dd, /* +0.6895405054 */
! 412: /* S_62 */ 0x55f5a5, /* +0.6715589762 */
! 413: /* S_63 */ 0x539b2b, /* +0.6531728506 */
! 414: /* S_64 */ 0x5133cd, /* +0.6343933344 */
! 415: /* S_65 */ 0x4ebfe9, /* +0.6152316332 */
! 416: /* S_66 */ 0x4c3fe0, /* +0.5956993103 */
! 417: /* S_67 */ 0x49b415, /* +0.5758081675 */
! 418: /* S_68 */ 0x471ced, /* +0.5555702448 */
! 419: /* S_69 */ 0x447acd, /* +0.5349975824 */
! 420: /* S_6A */ 0x41ce1e, /* +0.5141026974 */
! 421: /* S_6B */ 0x3f174a, /* +0.4928982258 */
! 422: /* S_6C */ 0x3c56ba, /* +0.4713966846 */
! 423: /* S_6D */ 0x398cdd, /* +0.4496113062 */
! 424: /* S_6E */ 0x36ba20, /* +0.4275550842 */
! 425: /* S_6F */ 0x33def3, /* +0.4052413702 */
! 426: /* S_70 */ 0x30fbc5, /* +0.3826833963 */
! 427: /* S_71 */ 0x2e110a, /* +0.3598949909 */
! 428: /* S_72 */ 0x2b1f35, /* +0.3368898630 */
! 429: /* S_73 */ 0x2826b9, /* +0.3136817217 */
! 430: /* S_74 */ 0x25280c, /* +0.2902846336 */
! 431: /* S_75 */ 0x2223a5, /* +0.2667127848 */
! 432: /* S_76 */ 0x1f19f9, /* +0.2429801226 */
! 433: /* S_77 */ 0x1c0b82, /* +0.2191011906 */
! 434: /* S_78 */ 0x18f8b8, /* +0.1950902939 */
! 435: /* S_79 */ 0x15e214, /* +0.1709618568 */
! 436: /* S_7A */ 0x12c810, /* +0.1467304230 */
! 437: /* S_7B */ 0x0fab27, /* +0.1224106550 */
! 438: /* S_7C */ 0x0c8bd3, /* +0.0980170965 */
! 439: /* S_7D */ 0x096a90, /* +0.0735645294 */
! 440: /* S_7E */ 0x0647d9, /* +0.0490676165 */
! 441: /* S_7F */ 0x03242b, /* +0.0245412588 */
! 442: /* S_80 */ 0x000000, /* +0.0000000000 */
! 443: /* S_81 */ 0xfcdbd5, /* -0.0245412588 */
! 444: /* S_82 */ 0xf9b827, /* -0.0490676165 */
! 445: /* S_83 */ 0xf69570, /* -0.0735645294 */
! 446: /* S_84 */ 0xf3742d, /* -0.0980170965 */
! 447: /* S_85 */ 0xf054d9, /* -0.1224106550 */
! 448: /* S_86 */ 0xed37f0, /* -0.1467304230 */
! 449: /* S_87 */ 0xea1dec, /* -0.1709618568 */
! 450: /* S_88 */ 0xe70748, /* -0.1950902939 */
! 451: /* S_89 */ 0xe3f47e, /* -0.2191011906 */
! 452: /* S_8A */ 0xe0e607, /* -0.2429801226 */
! 453: /* S_8B */ 0xdddc5b, /* -0.2667127848 */
! 454: /* S_8C */ 0xdad7f4, /* -0.2902846336 */
! 455: /* S_8D */ 0xd7d947, /* -0.3136817217 */
! 456: /* S_8E */ 0xd4e0cb, /* -0.3368898630 */
! 457: /* S_8F */ 0xd1eef6, /* -0.3598949909 */
! 458: /* S_90 */ 0xcf043b, /* -0.3826833963 */
! 459: /* S_91 */ 0xcc210d, /* -0.4052413702 */
! 460: /* S_92 */ 0xc945e0, /* -0.4275550842 */
! 461: /* S_93 */ 0xc67323, /* -0.4496113062 */
! 462: /* S_94 */ 0xc3a946, /* -0.4713966846 */
! 463: /* S_95 */ 0xc0e8b6, /* -0.4928982258 */
! 464: /* S_96 */ 0xbe31e2, /* -0.5141026974 */
! 465: /* S_97 */ 0xbb8533, /* -0.5349975824 */
! 466: /* S_98 */ 0xb8e313, /* -0.5555702448 */
! 467: /* S_99 */ 0xb64beb, /* -0.5758081675 */
! 468: /* S_9A */ 0xb3c020, /* -0.5956993103 */
! 469: /* S_9B */ 0xb14017, /* -0.6152316332 */
! 470: /* S_9C */ 0xaecc33, /* -0.6343933344 */
! 471: /* S_9D */ 0xac64d5, /* -0.6531728506 */
! 472: /* S_9E */ 0xaa0a5b, /* -0.6715589762 */
! 473: /* S_9F */ 0xa7bd23, /* -0.6895405054 */
! 474: /* S_A0 */ 0xa57d86, /* -0.7071068287 */
! 475: /* S_A1 */ 0xa34bdf, /* -0.7242470980 */
! 476: /* S_A2 */ 0xa12883, /* -0.7409511805 */
! 477: /* S_A3 */ 0x9f13c8, /* -0.7572088242 */
! 478: /* S_A4 */ 0x9d0dfe, /* -0.7730104923 */
! 479: /* S_A5 */ 0x9b1777, /* -0.7883464098 */
! 480: /* S_A6 */ 0x99307f, /* -0.8032075167 */
! 481: /* S_A7 */ 0x975961, /* -0.8175848722 */
! 482: /* S_A8 */ 0x959267, /* -0.8314696550 */
! 483: /* S_A9 */ 0x93dbd7, /* -0.8448535204 */
! 484: /* S_AA */ 0x9235f3, /* -0.8577286005 */
! 485: /* S_AB */ 0x90a0fd, /* -0.8700870275 */
! 486: /* S_AC */ 0x8f1d34, /* -0.8819212914 */
! 487: /* S_AD */ 0x8daad3, /* -0.8932243586 */
! 488: /* S_AE */ 0x8c4a14, /* -0.9039893150 */
! 489: /* S_AF */ 0x8afb2d, /* -0.9142097235 */
! 490: /* S_B0 */ 0x89be51, /* -0.9238795042 */
! 491: /* S_B1 */ 0x8893b1, /* -0.9329928160 */
! 492: /* S_B2 */ 0x877b7c, /* -0.9415440559 */
! 493: /* S_B3 */ 0x8675dc, /* -0.9495282173 */
! 494: /* S_B4 */ 0x8582fb, /* -0.9569402933 */
! 495: /* S_B5 */ 0x84a2fc, /* -0.9637761116 */
! 496: /* S_B6 */ 0x83d604, /* -0.9700312614 */
! 497: /* S_B7 */ 0x831c31, /* -0.9757021666 */
! 498: /* S_B8 */ 0x8275a1, /* -0.9807852507 */
! 499: /* S_B9 */ 0x81e26c, /* -0.9852776527 */
! 500: /* S_BA */ 0x8162aa, /* -0.9891765118 */
! 501: /* S_BB */ 0x80f66e, /* -0.9924795628 */
! 502: /* S_BC */ 0x809dc9, /* -0.9951847792 */
! 503: /* S_BD */ 0x8058c9, /* -0.9972904921 */
! 504: /* S_BE */ 0x802778, /* -0.9987955093 */
! 505: /* S_BF */ 0x8009de, /* -0.9996988773 */
! 506: /* S_C0 */ 0x800000, /* -1.0000000000 */
! 507: /* S_C1 */ 0x8009de, /* -0.9996988773 */
! 508: /* S_C2 */ 0x802778, /* -0.9987955093 */
! 509: /* S_C3 */ 0x8058c9, /* -0.9972904921 */
! 510: /* S_C4 */ 0x809dc9, /* -0.9951847792 */
! 511: /* S_C5 */ 0x80f66e, /* -0.9924795628 */
! 512: /* S_C6 */ 0x8162aa, /* -0.9891765118 */
! 513: /* S_C7 */ 0x81e26c, /* -0.9852776527 */
! 514: /* S_C8 */ 0x8275a1, /* -0.9807852507 */
! 515: /* S_C9 */ 0x831c31, /* -0.9757021666 */
! 516: /* S_CA */ 0x83d604, /* -0.9700312614 */
! 517: /* S_CB */ 0x84a2fc, /* -0.9637761116 */
! 518: /* S_CC */ 0x8582fb, /* -0.9569402933 */
! 519: /* S_CD */ 0x8675dc, /* -0.9495282173 */
! 520: /* S_CE */ 0x877b7c, /* -0.9415440559 */
! 521: /* S_CF */ 0x8893b1, /* -0.9329928160 */
! 522: /* S_D0 */ 0x89be51, /* -0.9238795042 */
! 523: /* S_D1 */ 0x8afb2d, /* -0.9142097235 */
! 524: /* S_D2 */ 0x8c4a14, /* -0.9039893150 */
! 525: /* S_D3 */ 0x8daad3, /* -0.8932243586 */
! 526: /* S_D4 */ 0x8f1d34, /* -0.8819212914 */
! 527: /* S_D5 */ 0x90a0fd, /* -0.8700870275 */
! 528: /* S_D6 */ 0x9235f3, /* -0.8577286005 */
! 529: /* S_D7 */ 0x93dbd7, /* -0.8448535204 */
! 530: /* S_D8 */ 0x959267, /* -0.8314696550 */
! 531: /* S_D9 */ 0x975961, /* -0.8175848722 */
! 532: /* S_DA */ 0x99307f, /* -0.8032075167 */
! 533: /* S_DB */ 0x9b1777, /* -0.7883464098 */
! 534: /* S_DC */ 0x9d0dfe, /* -0.7730104923 */
! 535: /* S_DD */ 0x9f13c8, /* -0.7572088242 */
! 536: /* S_DE */ 0xa12883, /* -0.7409511805 */
! 537: /* S_DF */ 0xa34bdf, /* -0.7242470980 */
! 538: /* S_E0 */ 0xa57d86, /* -0.7071068287 */
! 539: /* S_E1 */ 0xa7bd23, /* -0.6895405054 */
! 540: /* S_E2 */ 0xaa0a5b, /* -0.6715589762 */
! 541: /* S_E3 */ 0xac64d5, /* -0.6531728506 */
! 542: /* S_E4 */ 0xaecc33, /* -0.6343933344 */
! 543: /* S_E5 */ 0xb14017, /* -0.6152316332 */
! 544: /* S_E6 */ 0xb3c020, /* -0.5956993103 */
! 545: /* S_E7 */ 0xb64beb, /* -0.5758081675 */
! 546: /* S_E8 */ 0xb8e313, /* -0.5555702448 */
! 547: /* S_E9 */ 0xbb8533, /* -0.5349975824 */
! 548: /* S_EA */ 0xbe31e2, /* -0.5141026974 */
! 549: /* S_EB */ 0xc0e8b6, /* -0.4928982258 */
! 550: /* S_EC */ 0xc3a946, /* -0.4713966846 */
! 551: /* S_ED */ 0xc67323, /* -0.4496113062 */
! 552: /* S_EE */ 0xc945e0, /* -0.4275550842 */
! 553: /* S_EF */ 0xcc210d, /* -0.4052413702 */
! 554: /* S_F0 */ 0xcf043b, /* -0.3826833963 */
! 555: /* S_F1 */ 0xd1eef6, /* -0.3598949909 */
! 556: /* S_F2 */ 0xd4e0cb, /* -0.3368898630 */
! 557: /* S_F3 */ 0xd7d947, /* -0.3136817217 */
! 558: /* S_F4 */ 0xdad7f4, /* -0.2902846336 */
! 559: /* S_F5 */ 0xdddc5b, /* -0.2667127848 */
! 560: /* S_F6 */ 0xe0e607, /* -0.2429801226 */
! 561: /* S_F7 */ 0xe3f47e, /* -0.2191011906 */
! 562: /* S_F8 */ 0xe70748, /* -0.1950902939 */
! 563: /* S_F9 */ 0xea1dec, /* -0.1709618568 */
! 564: /* S_FA */ 0xed37f0, /* -0.1467304230 */
! 565: /* S_FB */ 0xf054d9, /* -0.1224106550 */
! 566: /* S_FC */ 0xf3742d, /* -0.0980170965 */
! 567: /* S_FD */ 0xf69570, /* -0.0735645294 */
! 568: /* S_FE */ 0xf9b827, /* -0.0490676165 */
! 569: /* S_FF */ 0xfcdbd5 /* -0.0245412588 */
! 570: };
! 571:
! 572:
1.1 root 573: /* Init DSP emulation */
1.1.1.8 root 574: void dsp_core_init(void (*host_interrupt)(int))
1.1 root 575: {
1.1.1.4 root 576: LOG_TRACE(TRACE_DSP_STATE, "Dsp: core init\n");
1.1 root 577:
1.1.1.3 root 578: dsp_host_interrupt = host_interrupt;
1.1.1.4 root 579: memset(&dsp_core, 0, sizeof(dsp_core_t));
1.1.1.10! root 580: memcpy(&dsp_core.rom[DSP_SPACE_X][0x100], x_rom, sizeof(x_rom));
! 581: memcpy(&dsp_core.rom[DSP_SPACE_Y][0x100], y_rom, sizeof(y_rom));
1.1 root 582: }
583:
584: /* Shutdown DSP emulation */
1.1.1.4 root 585: void dsp_core_shutdown(void)
1.1 root 586: {
1.1.1.4 root 587: dsp_core.running = 0;
588: LOG_TRACE(TRACE_DSP_STATE, "Dsp: core shutdown\n");
1.1 root 589: }
590:
591: /* Reset */
1.1.1.4 root 592: void dsp_core_reset(void)
1.1 root 593: {
594: int i;
595:
1.1.1.4 root 596: LOG_TRACE(TRACE_DSP_STATE, "Dsp: core reset\n");
597: dsp_core_shutdown();
1.1 root 598:
599: /* Memory */
1.1.1.4 root 600: memset((void*)dsp_core.periph, 0, sizeof(dsp_core.periph));
601: memset(dsp_core.stack, 0, sizeof(dsp_core.stack));
602: memset(dsp_core.registers, 0, sizeof(dsp_core.registers));
603: dsp_core.dsp_host_rtx = 0;
604: dsp_core.dsp_host_htx = 0;
1.1 root 605:
1.1.1.4 root 606: dsp_core.bootstrap_pos = 0;
1.1.1.8 root 607:
1.1 root 608: /* Registers */
1.1.1.4 root 609: dsp_core.pc = 0x0000;
610: dsp_core.registers[DSP_REG_OMR]=0x02;
1.1 root 611: for (i=0;i<8;i++) {
1.1.1.4 root 612: dsp_core.registers[DSP_REG_M0+i]=0x00ffff;
1.1 root 613: }
614:
1.1.1.2 root 615: /* Interruptions */
1.1.1.4 root 616: memset((void*)dsp_core.interrupt_isPending, 0, sizeof(dsp_core.interrupt_isPending));
617: dsp_core.interrupt_state = DSP_INTERRUPT_NONE;
618: dsp_core.interrupt_instr_fetch = -1;
619: dsp_core.interrupt_save_pc = -1;
620: dsp_core.interrupt_counter = 0;
621: dsp_core.interrupt_pipeline_count = 0;
1.1.1.3 root 622: for (i=0;i<5;i++) {
1.1.1.4 root 623: dsp_core.interrupt_ipl[i] = 3;
1.1.1.3 root 624: }
625: for (i=5;i<12;i++) {
1.1.1.4 root 626: dsp_core.interrupt_ipl[i] = -1;
1.1.1.3 root 627: }
1.1.1.2 root 628:
1.1 root 629: /* host port init, dsp side */
1.1.1.4 root 630: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR]=(1<<DSP_HOST_HSR_HTDE);
1.1 root 631:
632: /* host port init, cpu side */
1.1.1.5 root 633: dsp_core.hostport[CPU_HOST_ICR] = 0x0;
634: dsp_core.hostport[CPU_HOST_CVR] = 0x12;
635: dsp_core.hostport[CPU_HOST_ISR] = (1<<CPU_HOST_ISR_TRDY)|(1<<CPU_HOST_ISR_TXDE);
636: dsp_core.hostport[CPU_HOST_IVR] = 0x0f;
637: dsp_core.hostport[CPU_HOST_RX0] = 0x0;
1.1 root 638:
1.1.1.2 root 639: /* SSI registers */
1.1.1.4 root 640: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR]=1<<DSP_SSI_SR_TDE;
641: dsp_core.ssi.waitFrameTX = 1;
642: dsp_core.ssi.waitFrameRX = 1;
643: dsp_core.ssi.TX = 0;
644: dsp_core.ssi.RX = 0;
645: dsp_core.ssi.dspPlay_handshakeMode_frame = 0;
1.1.1.5 root 646: dsp_core_ssi_configure(DSP_SSI_CRA, 0);
647: dsp_core_ssi_configure(DSP_SSI_CRB, 0);
648:
1.1 root 649: /* Other hardware registers */
1.1.1.4 root 650: dsp_core.periph[DSP_SPACE_X][DSP_IPR]=0;
651: dsp_core.periph[DSP_SPACE_X][DSP_BCR]=0xffff;
1.1 root 652:
653: /* Misc */
1.1.1.4 root 654: dsp_core.loop_rep = 0;
1.1 root 655:
1.1.1.4 root 656: LOG_TRACE(TRACE_DSP_STATE, "Dsp: reset done\n");
657: dsp56k_init_cpu();
1.1.1.2 root 658: }
659:
1.1.1.8 root 660: /*
1.1.1.2 root 661: SSI INTERFACE processing
662: */
663:
1.1.1.3 root 664: /* Set PortC data register : send a frame order to the DMA in handshake mode */
1.1.1.4 root 665: void dsp_core_setPortCDataRegister(Uint32 value)
1.1.1.2 root 666: {
1.1.1.3 root 667: /* if DSP Record is in handshake mode with DMA Play */
1.1.1.4 root 668: if ((dsp_core.periph[DSP_SPACE_X][DSP_PCDDR] & 0x10) == 0x10) {
1.1.1.3 root 669: if ((value & 0x10) == 0x10) {
1.1.1.4 root 670: dsp_core.ssi.waitFrameRX = 0;
1.1.1.3 root 671: DSP_SsiTransmit_SC1();
1.1.1.4 root 672: LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp record in handshake mode: SSI send SC1 to crossbar\n");
1.1.1.3 root 673: }
674: }
675:
676: /* if DSP Play is in handshake mode with DMA Record, high or low frame sync */
677: /* to allow / disable transfer of the data */
1.1.1.4 root 678: if ((dsp_core.periph[DSP_SPACE_X][DSP_PCDDR] & 0x20) == 0x20) {
1.1.1.3 root 679: if ((value & 0x20) == 0x20) {
1.1.1.4 root 680: dsp_core.ssi.dspPlay_handshakeMode_frame = 1;
681: dsp_core.ssi.waitFrameTX = 0;
682: LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp play in handshake mode: frame = 1\n");
1.1.1.3 root 683: }
684: else {
1.1.1.4 root 685: dsp_core.ssi.dspPlay_handshakeMode_frame = 0;
1.1.1.3 root 686: DSP_SsiTransmit_SC2(0);
1.1.1.4 root 687: LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp play in handshake mode: SSI send SC2 to crossbar, frame sync = 0\n");
1.1.1.3 root 688: }
689: }
1.1.1.2 root 690: }
691:
692: /* SSI set TX register */
1.1.1.4 root 693: void dsp_core_ssi_writeTX(Uint32 value)
1.1.1.2 root 694: {
695: /* Clear SSI TDE bit */
1.1.1.4 root 696: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_TDE);
697: dsp_core.ssi.TX = value;
698: LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp set TX register: 0x%06x\n", value);
1.1.1.3 root 699:
700: /* if DSP Play is in handshake mode with DMA Record, send frame sync */
701: /* to allow transfer of the data */
1.1.1.4 root 702: if (dsp_core.ssi.dspPlay_handshakeMode_frame) {
1.1.1.3 root 703: DSP_SsiTransmit_SC2(1);
1.1.1.4 root 704: LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp play in handshake mode: SSI send SC2 to crossbar, frame sync = 1\n");
1.1.1.3 root 705: }
1.1.1.2 root 706: }
707:
708: /* SSI set TDE register (dummy write) */
1.1.1.4 root 709: void dsp_core_ssi_writeTSR(void)
1.1.1.2 root 710: {
711: /* Dummy write : Just clear SSI TDE bit */
1.1.1.4 root 712: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_TDE);
1.1.1.2 root 713: }
714:
715: /* SSI get RX register */
1.1.1.4 root 716: Uint32 dsp_core_ssi_readRX(void)
1.1.1.2 root 717: {
1.1.1.3 root 718: /* Clear SSI RDF bit */
1.1.1.4 root 719: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_RDF);
720: LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp read RX register: 0x%06x\n", dsp_core.ssi.RX);
721: return dsp_core.ssi.RX;
1.1.1.2 root 722: }
723:
1.1 root 724:
1.1.1.3 root 725: /**
726: * SSI receive serial clock.
727: *
728: */
1.1.1.4 root 729: void dsp_core_ssi_Receive_SC0(void)
1.1.1.3 root 730: {
731: Uint32 value, i, temp=0;
1.1.1.2 root 732:
733: /* Receive data from crossbar to SSI */
1.1.1.4 root 734: value = dsp_core.ssi.received_value;
1.1.1.2 root 735:
736: /* adjust value to receive size word */
1.1.1.4 root 737: value <<= (24 - dsp_core.ssi.cra_word_length);
1.1.1.2 root 738: value &= 0xffffff;
739:
740: /* if bit SHFD in CRB is set, swap received data */
1.1.1.4 root 741: if (dsp_core.ssi.crb_shifter) {
1.1.1.2 root 742: temp=0;
1.1.1.4 root 743: for (i=0; i<dsp_core.ssi.cra_word_length; i++) {
1.1.1.2 root 744: temp += value & 1;
745: temp <<= 1;
746: value >>= 1;
747: }
748: value = temp;
749: }
750:
1.1.1.4 root 751: LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp SSI received value from crossbar: 0x%06x\n", value);
752:
753: if (dsp_core.ssi.crb_re && dsp_core.ssi.waitFrameRX == 0) {
1.1.1.3 root 754: /* Send value to DSP receive */
1.1.1.4 root 755: dsp_core.ssi.RX = value;
1.1.1.3 root 756:
757: /* generate interrupt ? */
1.1.1.4 root 758: if (dsp_core.periph[DSP_SPACE_X][DSP_SSI_CRB] & (1<<DSP_SSI_CRB_RIE)) {
759: if (dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] & (1<<DSP_SSI_SR_RDF)) {
1.1.1.3 root 760: dsp_add_interrupt(DSP_INTER_SSI_RCV_DATA);
761: } else {
762: dsp_add_interrupt(DSP_INTER_SSI_RCV_DATA);
763: }
1.1.1.2 root 764: }
1.1.1.3 root 765: }else{
1.1.1.4 root 766: dsp_core.ssi.RX = 0;
1.1 root 767: }
1.1.1.3 root 768:
769: /* set RDF */
1.1.1.4 root 770: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] |= 1<<DSP_SSI_SR_RDF;
1.1 root 771: }
772:
1.1.1.3 root 773: /**
774: * SSI receive SC1 bit : frame sync for receiver
775: * value = 1 : beginning of a new frame
776: * value = 0 : not beginning of a new frame
777: */
1.1.1.4 root 778: void dsp_core_ssi_Receive_SC1(Uint32 value)
1.1.1.2 root 779: {
1.1.1.3 root 780: /* SSI runs in network mode ? */
1.1.1.4 root 781: if (dsp_core.ssi.crb_mode) {
1.1.1.3 root 782: if (value) {
783: /* Beginning of a new frame */
1.1.1.4 root 784: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] |= (1<<DSP_SSI_SR_RFS);
785: dsp_core.ssi.waitFrameRX = 0;
1.1.1.3 root 786: }else{
1.1.1.4 root 787: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_RFS);
1.1.1.3 root 788: }
789: }else{
790: /* SSI runs in normal mode */
1.1.1.4 root 791: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] |= (1<<DSP_SSI_SR_RFS);
1.1.1.3 root 792: }
1.1.1.4 root 793:
794: LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp SSI receive frame sync: 0x%01x\n", value);
1.1.1.2 root 795: }
1.1 root 796:
1.1.1.3 root 797: /**
798: * SSI receive SC2 bit : frame sync for transmitter
799: * value = 1 : beginning of a new frame
800: * value = 0 : not beginning of a new frame
801: */
1.1.1.4 root 802: void dsp_core_ssi_Receive_SC2(Uint32 value)
1.1 root 803: {
1.1.1.2 root 804: /* SSI runs in network mode ? */
1.1.1.4 root 805: if (dsp_core.ssi.crb_mode) {
1.1.1.3 root 806: if (value) {
807: /* Beginning of a new frame */
1.1.1.4 root 808: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] |= (1<<DSP_SSI_SR_TFS);
809: dsp_core.ssi.waitFrameTX = 0;
1.1.1.2 root 810: }else{
1.1.1.4 root 811: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_TFS);
1.1.1.2 root 812: }
813: }else{
814: /* SSI runs in normal mode */
1.1.1.4 root 815: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] |= (1<<DSP_SSI_SR_TFS);
1.1 root 816: }
1.1.1.4 root 817:
818: LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp SSI transmit frame sync: 0x%01x\n", value);
1.1 root 819: }
1.1.1.2 root 820:
1.1.1.3 root 821: /**
822: * SSI transmit serial clock.
823: *
824: */
1.1.1.4 root 825: void dsp_core_ssi_Receive_SCK(void)
1.1.1.3 root 826: {
827: Uint32 value, i, temp=0;
828:
1.1.1.4 root 829: value = dsp_core.ssi.TX;
1.1.1.3 root 830:
831: /* Transfer data from SSI to crossbar*/
832:
833: /* adjust value to transnmit size word */
1.1.1.4 root 834: value >>= (24 - dsp_core.ssi.cra_word_length);
835: value &= dsp_core.ssi.cra_word_mask;
1.1.1.3 root 836:
837: /* if bit SHFD in CRB is set, swap data to transmit */
1.1.1.4 root 838: if (dsp_core.ssi.crb_shifter) {
839: for (i=0; i<dsp_core.ssi.cra_word_length; i++) {
1.1.1.3 root 840: temp += value & 1;
841: temp <<= 1;
842: value >>= 1;
843: }
844: value = temp;
845: }
846:
1.1.1.4 root 847: LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp SSI transmit value to crossbar: 0x%06x\n", value);
848:
1.1.1.3 root 849: /* Transmit the data */
1.1.1.4 root 850: if (dsp_core.ssi.crb_te && dsp_core.ssi.waitFrameTX == 0) {
1.1.1.3 root 851: /* Send value to crossbar */
1.1.1.4 root 852: dsp_core.ssi.transmit_value = value;
1.1.1.3 root 853:
854: /* generate interrupt ? */
1.1.1.4 root 855: if (dsp_core.periph[DSP_SPACE_X][DSP_SSI_CRB] & (1<<DSP_SSI_CRB_TIE)) {
856: if (dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] & (1<<DSP_SSI_SR_TDE)) {
1.1.1.3 root 857: dsp_add_interrupt(DSP_INTER_SSI_TRX_DATA);
858: } else {
859: dsp_add_interrupt(DSP_INTER_SSI_TRX_DATA);
860: }
861: }
862: }else{
1.1.1.4 root 863: dsp_core.ssi.transmit_value = 0;
1.1.1.3 root 864: }
865:
866: /* set TDE */
1.1.1.4 root 867: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] |= (1<<DSP_SSI_SR_TDE);
1.1.1.3 root 868: }
869:
870:
871: /* SSI initialisations and state management */
1.1.1.6 root 872: void dsp_core_ssi_configure(Uint32 address, Uint32 value)
1.1.1.2 root 873: {
1.1.1.3 root 874: Uint32 crb_te, crb_re;
1.1.1.2 root 875:
1.1.1.6 root 876: switch (address) {
1.1.1.2 root 877: case DSP_SSI_CRA:
1.1.1.4 root 878: dsp_core.periph[DSP_SPACE_X][DSP_SSI_CRA] = value;
1.1.1.2 root 879: /* get word size for transfers */
880: switch ((value>>DSP_SSI_CRA_WL0) & 3) {
881: case 0:
1.1.1.4 root 882: dsp_core.ssi.cra_word_length = 8;
883: dsp_core.ssi.cra_word_mask = 0xff;
1.1.1.2 root 884: break;
885: case 1:
1.1.1.4 root 886: dsp_core.ssi.cra_word_length = 12;
887: dsp_core.ssi.cra_word_mask = 0xfff;
1.1.1.2 root 888: break;
889: case 2:
1.1.1.4 root 890: dsp_core.ssi.cra_word_length = 16;
891: dsp_core.ssi.cra_word_mask = 0xffff;
1.1.1.2 root 892: break;
893: case 3:
1.1.1.4 root 894: dsp_core.ssi.cra_word_length = 24;
895: dsp_core.ssi.cra_word_mask = 0xffffff;
1.1.1.2 root 896: break;
897: }
898:
1.1.1.4 root 899: LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp SSI CRA write: 0x%06x\n", value);
900:
1.1.1.2 root 901: /* Get the Frame rate divider ( 2 < value <32) */
1.1.1.4 root 902: dsp_core.ssi.cra_frame_rate_divider = ((value >> DSP_SSI_CRA_DC0) & 0x1f)+1;
1.1.1.2 root 903: break;
904: case DSP_SSI_CRB:
1.1.1.4 root 905: crb_te = dsp_core.periph[DSP_SPACE_X][DSP_SSI_CRB] & (1<<DSP_SSI_CRB_TE);
906: crb_re = dsp_core.periph[DSP_SPACE_X][DSP_SSI_CRB] & (1<<DSP_SSI_CRB_RE);
907: dsp_core.periph[DSP_SPACE_X][DSP_SSI_CRB] = value;
1.1.1.8 root 908:
1.1.1.4 root 909: dsp_core.ssi.crb_src_clock = (value>>DSP_SSI_CRB_SCKD) & 1;
910: dsp_core.ssi.crb_shifter = (value>>DSP_SSI_CRB_SHFD) & 1;
911: dsp_core.ssi.crb_synchro = (value>>DSP_SSI_CRB_SYN) & 1;
912: dsp_core.ssi.crb_mode = (value>>DSP_SSI_CRB_MOD) & 1;
913: dsp_core.ssi.crb_te = (value>>DSP_SSI_CRB_TE) & 1;
914: dsp_core.ssi.crb_re = (value>>DSP_SSI_CRB_RE) & 1;
915: dsp_core.ssi.crb_tie = (value>>DSP_SSI_CRB_TIE) & 1;
916: dsp_core.ssi.crb_rie = (value>>DSP_SSI_CRB_RIE) & 1;
1.1.1.2 root 917:
1.1.1.4 root 918: if (crb_te == 0 && dsp_core.ssi.crb_te) {
919: dsp_core.ssi.waitFrameTX = 1;
1.1.1.3 root 920: }
1.1.1.4 root 921: if (crb_re == 0 && dsp_core.ssi.crb_re) {
922: dsp_core.ssi.waitFrameRX = 1;
1.1.1.2 root 923: }
1.1.1.4 root 924:
925: LOG_TRACE(TRACE_DSP_HOST_SSI, "Dsp SSI CRB write: 0x%06x\n", value);
926:
1.1.1.2 root 927: break;
928: }
929: }
930:
1.1.1.3 root 931:
1.1.1.8 root 932: /*
1.1.1.2 root 933: HOST INTERFACE processing
934: */
935:
1.1.1.4 root 936: static void dsp_core_hostport_update_trdy(void)
1.1 root 937: {
938: int trdy;
939:
940: /* Clear/set TRDY bit */
1.1.1.4 root 941: dsp_core.hostport[CPU_HOST_ISR] &= 0xff-(1<<CPU_HOST_ISR_TRDY);
942: trdy = (dsp_core.hostport[CPU_HOST_ISR]>>CPU_HOST_ISR_TXDE)
943: & ~(dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR]>>DSP_HOST_HSR_HRDF);
944: dsp_core.hostport[CPU_HOST_ISR] |= (trdy & 1)<< CPU_HOST_ISR_TRDY;
1.1 root 945: }
946:
1.1.1.4 root 947: static void dsp_core_hostport_update_hreq(void)
1.1.1.2 root 948: {
949: int hreq;
950:
1.1.1.8 root 951: #if 0
1.1.1.4 root 952: hreq = (dsp_core.hostport[CPU_HOST_ICR] & dsp_core.hostport[CPU_HOST_ISR]) & 0x3;
1.1.1.3 root 953:
954: /* Trigger host interrupt? */
1.1.1.4 root 955: if (hreq && (dsp_core.hostport[CPU_HOST_ISR] & (1<<CPU_HOST_ISR_HREQ)) == 0) {
1.1.1.3 root 956: dsp_host_interrupt();
957: }
958:
959: /* Set HREQ bit in hostport */
1.1.1.4 root 960: dsp_core.hostport[CPU_HOST_ISR] &= 0x7f;
961: dsp_core.hostport[CPU_HOST_ISR] |= (hreq?1:0) << CPU_HOST_ISR_HREQ;
1.1.1.8 root 962: #else
963: hreq = (dsp_core.hostport[CPU_HOST_ICR] & dsp_core.hostport[CPU_HOST_ISR]) & 0x3;
964:
965: if ( hreq != 0 )
966: hreq = 1 << CPU_HOST_ISR_HREQ;
967:
968: /* If hreq doesn't change, we do nothing */
969: if ( hreq == ( dsp_core.hostport[CPU_HOST_ISR] & 0x80 ) )
970: return;
971:
972: if ( hreq ) /* 0->1 transition */
973: dsp_host_interrupt ( 1 ); /* set host interrupt */
974: else /* 1->0 transition */
975: dsp_host_interrupt ( 0 ); /* unset host interrupt */
976:
977: /* Set/clear HREQ bit in hostport */
978: dsp_core.hostport[CPU_HOST_ISR] &= 0x7f;
979: dsp_core.hostport[CPU_HOST_ISR] |= hreq;
980: //fprintf ( stderr , "dsp_core_hostport_update_hreq %x\n" , hreq );
981: #endif
982: }
1.1.1.2 root 983:
1.1 root 984: /* Host port transfer ? (dsp->host) */
1.1.1.4 root 985: static void dsp_core_dsp2host(void)
1.1 root 986: {
1.1.1.2 root 987: /* RXDF = 1 ==> host hasn't read the last value yet */
1.1.1.4 root 988: if (dsp_core.hostport[CPU_HOST_ISR] & (1<<CPU_HOST_ISR_RXDF)) {
1.1 root 989: return;
990: }
1.1.1.2 root 991:
992: /* HTDE = 1 ==> nothing to tranfert from DSP port */
1.1.1.4 root 993: if (dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] & (1<<DSP_HOST_HSR_HTDE)) {
1.1 root 994: return;
995: }
996:
1.1.1.4 root 997: dsp_core.hostport[CPU_HOST_RXL] = dsp_core.dsp_host_htx;
998: dsp_core.hostport[CPU_HOST_RXM] = dsp_core.dsp_host_htx>>8;
999: dsp_core.hostport[CPU_HOST_RXH] = dsp_core.dsp_host_htx>>16;
1.1 root 1000:
1001: /* Set HTDE bit to say that DSP can write */
1.1.1.4 root 1002: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] |= 1<<DSP_HOST_HSR_HTDE;
1.1.1.2 root 1003:
1004: /* Is there an interrupt to send ? */
1.1.1.4 root 1005: if (dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] & (1<<DSP_HOST_HCR_HTIE)) {
1.1.1.3 root 1006: dsp_add_interrupt(DSP_INTER_HOST_TRX_DATA);
1.1.1.2 root 1007: }
1.1 root 1008:
1009: /* Set RXDF bit to say that host can read */
1.1.1.4 root 1010: dsp_core.hostport[CPU_HOST_ISR] |= 1<<CPU_HOST_ISR_RXDF;
1011: dsp_core_hostport_update_hreq();
1.1.1.2 root 1012:
1.1.1.4 root 1013: LOG_TRACE(TRACE_DSP_HOST_INTERFACE, "Dsp: (DSP->Host): Transfer 0x%06x, Dsp HTDE=1, Host RXDF=1\n", dsp_core.dsp_host_htx);
1.1 root 1014: }
1015:
1016: /* Host port transfer ? (host->dsp) */
1.1.1.4 root 1017: static void dsp_core_host2dsp(void)
1.1 root 1018: {
1.1.1.2 root 1019: /* TXDE = 1 ==> nothing to tranfert from host port */
1.1.1.4 root 1020: if (dsp_core.hostport[CPU_HOST_ISR] & (1<<CPU_HOST_ISR_TXDE)) {
1.1 root 1021: return;
1022: }
1.1.1.8 root 1023:
1.1.1.2 root 1024: /* HRDF = 1 ==> DSP hasn't read the last value yet */
1.1.1.4 root 1025: if (dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] & (1<<DSP_HOST_HSR_HRDF)) {
1.1 root 1026: return;
1027: }
1028:
1.1.1.4 root 1029: dsp_core.dsp_host_rtx = dsp_core.hostport[CPU_HOST_TXL];
1030: dsp_core.dsp_host_rtx |= dsp_core.hostport[CPU_HOST_TXM]<<8;
1031: dsp_core.dsp_host_rtx |= dsp_core.hostport[CPU_HOST_TXH]<<16;
1.1 root 1032:
1033: /* Set HRDF bit to say that DSP can read */
1.1.1.4 root 1034: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] |= 1<<DSP_HOST_HSR_HRDF;
1.1.1.2 root 1035:
1036: /* Is there an interrupt to send ? */
1.1.1.4 root 1037: if (dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] & (1<<DSP_HOST_HCR_HRIE)) {
1.1.1.3 root 1038: dsp_add_interrupt(DSP_INTER_HOST_RCV_DATA);
1.1.1.2 root 1039: }
1.1 root 1040:
1041: /* Set TXDE bit to say that host can write */
1.1.1.4 root 1042: dsp_core.hostport[CPU_HOST_ISR] |= 1<<CPU_HOST_ISR_TXDE;
1043: dsp_core_hostport_update_hreq();
1.1.1.2 root 1044:
1.1.1.4 root 1045: LOG_TRACE(TRACE_DSP_HOST_INTERFACE, "Dsp: (Host->DSP): Transfer 0x%06x, Dsp HRDF=1, Host TXDE=1\n", dsp_core.dsp_host_rtx);
1.1 root 1046:
1.1.1.4 root 1047: dsp_core_hostport_update_trdy();
1.1 root 1048: }
1049:
1.1.1.4 root 1050: void dsp_core_hostport_dspread(void)
1.1 root 1051: {
1052: /* Clear HRDF bit to say that DSP has read */
1.1.1.4 root 1053: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] &= 0xff-(1<<DSP_HOST_HSR_HRDF);
1054:
1055: LOG_TRACE(TRACE_DSP_HOST_INTERFACE, "Dsp: (Host->DSP): Dsp HRDF cleared\n");
1056:
1057: dsp_core_hostport_update_trdy();
1058: dsp_core_host2dsp();
1.1 root 1059: }
1060:
1.1.1.4 root 1061: void dsp_core_hostport_dspwrite(void)
1.1 root 1062: {
1063: /* Clear HTDE bit to say that DSP has written */
1.1.1.4 root 1064: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] &= 0xff-(1<<DSP_HOST_HSR_HTDE);
1065:
1066: LOG_TRACE(TRACE_DSP_HOST_INTERFACE, "Dsp: (DSP->Host): Dsp HTDE cleared\n");
1.1.1.3 root 1067:
1.1.1.4 root 1068: dsp_core_dsp2host();
1.1 root 1069: }
1070:
1071: /* Read/writes on host port */
1.1.1.4 root 1072: Uint8 dsp_core_read_host(int addr)
1.1 root 1073: {
1.1.1.2 root 1074: Uint8 value;
1.1 root 1075:
1.1.1.4 root 1076: value = dsp_core.hostport[addr];
1.1.1.2 root 1077: if (addr == CPU_HOST_TRXL) {
1078: /* Clear RXDF bit to say that CPU has read */
1.1.1.4 root 1079: dsp_core.hostport[CPU_HOST_ISR] &= 0xff-(1<<CPU_HOST_ISR_RXDF);
1080: dsp_core_dsp2host();
1081: dsp_core_hostport_update_hreq();
1.1.1.8 root 1082:
1.1.1.4 root 1083: LOG_TRACE(TRACE_DSP_HOST_INTERFACE, "Dsp: (DSP->Host): Host RXDF=0\n");
1.1 root 1084: }
1085: return value;
1086: }
1087:
1.1.1.4 root 1088: void dsp_core_write_host(int addr, Uint8 value)
1.1 root 1089: {
1090: switch(addr) {
1091: case CPU_HOST_ICR:
1.1.1.4 root 1092: dsp_core.hostport[CPU_HOST_ICR]=value & 0xfb;
1.1 root 1093: /* Set HF1 and HF0 accordingly on the host side */
1.1.1.4 root 1094: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] &=
1.1 root 1095: 0xff-((1<<DSP_HOST_HSR_HF1)|(1<<DSP_HOST_HSR_HF0));
1.1.1.4 root 1096: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] |=
1097: dsp_core.hostport[CPU_HOST_ICR] & ((1<<DSP_HOST_HSR_HF1)|(1<<DSP_HOST_HSR_HF0));
1098: dsp_core_hostport_update_hreq();
1.1 root 1099: break;
1100: case CPU_HOST_CVR:
1.1.1.4 root 1101: dsp_core.hostport[CPU_HOST_CVR]=value & 0x9f;
1.1.1.2 root 1102: /* if bit 7=1, host command . HSR(bit HCP) is set*/
1.1 root 1103: if (value & (1<<7)) {
1.1.1.4 root 1104: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] |= (1<<DSP_HOST_HSR_HCP);
1.1.1.2 root 1105: /* Is there an interrupt to send ? */
1.1.1.4 root 1106: if (dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] & (1<<DSP_HOST_HCR_HCIE)) {
1.1.1.3 root 1107: dsp_add_interrupt(DSP_INTER_HOST_COMMAND);
1.1.1.2 root 1108: }
1.1 root 1109: }
1.1.1.2 root 1110: else{
1.1.1.4 root 1111: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] &= 0xff - (1<<DSP_HOST_HSR_HCP);
1.1.1.2 root 1112: }
1.1.1.4 root 1113:
1114: LOG_TRACE(TRACE_DSP_HOST_COMMAND, "Dsp: (Host->DSP): Host command = %06x\n", value & 0x9f);
1115:
1.1 root 1116: break;
1117: case CPU_HOST_ISR:
1.1.1.2 root 1118: case CPU_HOST_TRX0:
1.1 root 1119: /* Read only */
1120: break;
1121: case CPU_HOST_IVR:
1.1.1.4 root 1122: dsp_core.hostport[CPU_HOST_IVR]=value;
1.1 root 1123: break;
1.1.1.2 root 1124: case CPU_HOST_TRXH:
1.1.1.4 root 1125: dsp_core.hostport[CPU_HOST_TXH]=value;
1.1.1.2 root 1126: break;
1127: case CPU_HOST_TRXM:
1.1.1.4 root 1128: dsp_core.hostport[CPU_HOST_TXM]=value;
1.1.1.2 root 1129: break;
1130: case CPU_HOST_TRXL:
1.1.1.4 root 1131: dsp_core.hostport[CPU_HOST_TXL]=value;
1.1 root 1132:
1.1.1.4 root 1133: if (!dsp_core.running) {
1134: dsp_core.ramint[DSP_SPACE_P][dsp_core.bootstrap_pos] =
1135: (dsp_core.hostport[CPU_HOST_TXH]<<16) |
1136: (dsp_core.hostport[CPU_HOST_TXM]<<8) |
1137: dsp_core.hostport[CPU_HOST_TXL];
1.1.1.8 root 1138:
1.1.1.4 root 1139: LOG_TRACE(TRACE_DSP_STATE, "Dsp: bootstrap p:0x%04x = 0x%06x\n",
1140: dsp_core.bootstrap_pos,
1141: dsp_core.ramint[DSP_SPACE_P][dsp_core.bootstrap_pos]);
1142:
1143: if (++dsp_core.bootstrap_pos == 0x200) {
1144: LOG_TRACE(TRACE_DSP_STATE, "Dsp: wait bootstrap done\n");
1145: dsp_core.running = 1;
1.1.1.2 root 1146: }
1.1 root 1147: } else {
1148:
1.1.1.2 root 1149: /* If TRDY is set, the tranfert is direct to DSP (Burst mode) */
1.1.1.4 root 1150: if (dsp_core.hostport[CPU_HOST_ISR] & (1<<CPU_HOST_ISR_TRDY)){
1151: dsp_core.dsp_host_rtx = dsp_core.hostport[CPU_HOST_TXL];
1152: dsp_core.dsp_host_rtx |= dsp_core.hostport[CPU_HOST_TXM]<<8;
1153: dsp_core.dsp_host_rtx |= dsp_core.hostport[CPU_HOST_TXH]<<16;
1154:
1155: LOG_TRACE(TRACE_DSP_HOST_INTERFACE, "Dsp: (Host->DSP): Direct Transfer 0x%06x\n", dsp_core.dsp_host_rtx);
1.1.1.2 root 1156:
1157: /* Set HRDF bit to say that DSP can read */
1.1.1.4 root 1158: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] |= 1<<DSP_HOST_HSR_HRDF;
1.1.1.2 root 1159:
1160: /* Is there an interrupt to send ? */
1.1.1.4 root 1161: if (dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] & (1<<DSP_HOST_HCR_HRIE)) {
1.1.1.3 root 1162: dsp_add_interrupt(DSP_INTER_HOST_RCV_DATA);
1.1.1.2 root 1163: }
1.1.1.4 root 1164:
1165: LOG_TRACE(TRACE_DSP_HOST_INTERFACE, "Dsp: (Host->DSP): Dsp HRDF set\n");
1.1.1.2 root 1166: }
1167: else{
1168: /* Clear TXDE to say that CPU has written */
1.1.1.4 root 1169: dsp_core.hostport[CPU_HOST_ISR] &= 0xff-(1<<CPU_HOST_ISR_TXDE);
1170: dsp_core_hostport_update_hreq();
1171:
1172: LOG_TRACE(TRACE_DSP_HOST_INTERFACE, "Dsp: (Host->DSP): Host TXDE cleared\n");
1.1.1.2 root 1173: }
1.1.1.4 root 1174: dsp_core_hostport_update_trdy();
1175: dsp_core_host2dsp();
1.1 root 1176: }
1177: break;
1178: }
1179: }
1180:
1181: /*
1182: vim:ts=4:sw=4:
1183: */
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