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Annotation of hatari/src/falcon/dsp_core.h, revision 1.1

1.1     ! root        1: /*
        !             2:        DSP M56001 emulation
        !             3:        Core of DSP emulation
        !             4: 
        !             5:        (C) 2003-2008 ARAnyM developer team
        !             6: 
        !             7:        This program is free software; you can redistribute it and/or modify
        !             8:        it under the terms of the GNU General Public License as published by
        !             9:        the Free Software Foundation; either version 2 of the License, or
        !            10:        (at your option) any later version.
        !            11: 
        !            12:        This program is distributed in the hope that it will be useful,
        !            13:        but WITHOUT ANY WARRANTY; without even the implied warranty of
        !            14:        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
        !            15:        GNU General Public License for more details.
        !            16: 
        !            17:        You should have received a copy of the GNU General Public License
        !            18:        along with this program; if not, write to the Free Software
        !            19:        Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
        !            20: */
        !            21: 
        !            22: #ifndef DSP_CORE_H
        !            23: #define DSP_CORE_H
        !            24: 
        !            25: #include <SDL.h>
        !            26: #include <SDL_thread.h>
        !            27: 
        !            28: #ifdef __cplusplus
        !            29: extern "C" {
        !            30: #endif
        !            31: 
        !            32: #define DSP_RAMSIZE 32768
        !            33: 
        !            34: /* Host port, CPU side */
        !            35: #define CPU_HOST_ICR   0x00
        !            36: #define CPU_HOST_CVR   0x01
        !            37: #define CPU_HOST_ISR   0x02
        !            38: #define CPU_HOST_IVR   0x03
        !            39: #define CPU_HOST_RX0   0x04
        !            40: #define CPU_HOST_RXH   0x05
        !            41: #define CPU_HOST_RXM   0x06
        !            42: #define CPU_HOST_RXL   0x07
        !            43: #define CPU_HOST_TX0   0x04
        !            44: #define CPU_HOST_TXH   0x05
        !            45: #define CPU_HOST_TXM   0x06
        !            46: #define CPU_HOST_TXL   0x07
        !            47: 
        !            48: #define CPU_HOST_ICR_RREQ      0x00
        !            49: #define CPU_HOST_ICR_TREQ      0x01
        !            50: #define CPU_HOST_ICR_HF0       0x03
        !            51: #define CPU_HOST_ICR_HF1       0x04
        !            52: #define CPU_HOST_ICR_HM0       0x05
        !            53: #define CPU_HOST_ICR_HM1       0x06
        !            54: #define CPU_HOST_ICR_INIT      0x07
        !            55: 
        !            56: #define CPU_HOST_CVR_HC                0x07
        !            57: 
        !            58: #define CPU_HOST_ISR_RXDF      0x00
        !            59: #define CPU_HOST_ISR_TXDE      0x01
        !            60: #define CPU_HOST_ISR_TRDY      0x02
        !            61: #define CPU_HOST_ISR_HF2       0x03
        !            62: #define CPU_HOST_ISR_HF3       0x04
        !            63: #define CPU_HOST_ISR_DMA       0x06
        !            64: #define CPU_HOST_ISR_HREQ      0x07
        !            65: 
        !            66: /* Host port, DSP side, DSP addresses are 0xffc0+value */
        !            67: #define DSP_PBC                        0x20    /* Port B control register */
        !            68: #define DSP_PCC                        0x21    /* Port C control register */
        !            69: #define DSP_PBDDR              0x22    /* Port B data direction register */
        !            70: #define DSP_PCDDR              0x23    /* Port C data direction register */
        !            71: #define DSP_PBD                        0x24    /* Port B data register */
        !            72: #define DSP_PCD                        0x25    /* Port C data register */
        !            73: #define DSP_HOST_HCR   0x28    /* Host control register */
        !            74: #define DSP_HOST_HSR   0x29    /* Host status register */
        !            75: #define DSP_HOST_HRX   0x2b    /* Host receive register */
        !            76: #define DSP_HOST_HTX   0x2b    /* Host transmit register */
        !            77: #define DSP_SSI_CRA            0x2c    /* Ssi control register A */
        !            78: #define DSP_SSI_CRB            0x2d    /* Ssi control register B */
        !            79: #define DSP_SSI_SR             0x2e    /* Ssi status register */
        !            80: #define DSP_SSI_TSR            0x2e    /* Ssi time slot register */
        !            81: #define DSP_SSI_RX             0x2f    /* Ssi receive register */
        !            82: #define DSP_SSI_TX             0x2f    /* Ssi transmit register */
        !            83: #define DSP_BCR                        0x3e    /* Port A bus control register */
        !            84: #define DSP_IPR                        0x3f    /* Interrupt priority register */
        !            85: 
        !            86: #define DSP_HOST_HCR_HRIE      0x00
        !            87: #define DSP_HOST_HCR_HTIE      0x01
        !            88: #define DSP_HOST_HCR_HCIE      0x02
        !            89: #define DSP_HOST_HCR_HF2       0x03
        !            90: #define DSP_HOST_HCR_HF3       0x04
        !            91: 
        !            92: #define DSP_HOST_HSR_HRDF      0x00
        !            93: #define DSP_HOST_HSR_HTDE      0x01
        !            94: #define DSP_HOST_HSR_HCP       0x02
        !            95: #define DSP_HOST_HSR_HF0       0x03
        !            96: #define DSP_HOST_HSR_HF1       0x04
        !            97: #define DSP_HOST_HSR_DMA       0x07
        !            98: 
        !            99: typedef struct {
        !           100:        SDL_Thread      *thread;        /* Thread in which DSP emulation runs */
        !           101:        SDL_sem         *semaphore;     /* Semaphore used to pause/unpause thread */
        !           102:        SDL_mutex       *mutex;         /* Mutex for read/writes through host port */
        !           103: 
        !           104:        /* DSP executing instructions ? */
        !           105:        volatile int running;
        !           106: 
        !           107:        /* Registers */
        !           108:        Uint16  pc;
        !           109:        Uint32  registers[64];
        !           110: 
        !           111:        /* stack[0=ssh], stack[1=ssl] */
        !           112:        Uint16  stack[2][15];
        !           113: 
        !           114:        /* External ram[0] is x:, ram[1] is y:, ram[2] is p: */
        !           115:        Uint32  ram[3][DSP_RAMSIZE];
        !           116: 
        !           117:        /* rom[0] is x:, rom[1] is y: */
        !           118:        Uint32  rom[2][512];
        !           119: 
        !           120:        /* Internal ram[0] is x:, ram[1] is y:, ram[2] is p: */
        !           121:        Uint32  ramint[3][512];
        !           122: 
        !           123:        /* peripheral space, [x|y]:0xffc0-0xffff */
        !           124:        volatile Uint32 periph[2][64];
        !           125: 
        !           126:        /* host port, CPU side */
        !           127:        volatile Uint8 hostport[8];
        !           128: 
        !           129:        /* Misc */
        !           130:        Uint32 loop_rep;                /* executing rep ? */
        !           131: 
        !           132:        /* For bootstrap routine */
        !           133:        Uint16  bootstrap_pos;
        !           134: } dsp_core_t;
        !           135: 
        !           136: /* Emulator call these to init/stop/reset DSP emulation */
        !           137: void dsp_core_init(dsp_core_t *dsp_core);
        !           138: void dsp_core_shutdown(dsp_core_t *dsp_core);
        !           139: void dsp_core_reset(dsp_core_t *dsp_core);
        !           140: 
        !           141: /* host port read/write by emulator, addr is 0-7, not 0xffa200-0xffa207 */
        !           142: Uint8 dsp_core_read_host(dsp_core_t *dsp_core, int addr);
        !           143: void dsp_core_write_host(dsp_core_t *dsp_core, int addr, Uint8 value);
        !           144: 
        !           145: /* dsp_cpu call these to signal state change */
        !           146: void dsp_core_set_state(dsp_core_t *dsp_core, int new_state);
        !           147: void dsp_core_set_state_sem(dsp_core_t *dsp_core, int new_state, int use_semaphore);
        !           148: 
        !           149: /* dsp_cpu call these to read/write host port */
        !           150: void dsp_core_hostport_dspread(dsp_core_t *dsp_core);
        !           151: void dsp_core_hostport_dspwrite(dsp_core_t *dsp_core);
        !           152: 
        !           153: #ifdef __cplusplus
        !           154: }
        !           155: #endif
        !           156: 
        !           157: #endif /* DSP_CORE_H */

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