![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to dsp_core.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [HATARI the Atari ST Emulator] / hatari / src / falcon|
Return to dsp_core.h CVS log | Up to [HATARI the Atari ST Emulator] / hatari / src / falcon |
1.1 root 1: /*
2: DSP M56001 emulation
3: Core of DSP emulation
4:
5: (C) 2003-2008 ARAnyM developer team
6:
7: This program is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2 of the License, or
10: (at your option) any later version.
11:
12: This program is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
18: along with this program; if not, write to the Free Software
19: Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20: */
21:
22: #ifndef DSP_CORE_H
23: #define DSP_CORE_H
24:
25: #include <SDL.h>
26:
27: #ifdef __cplusplus
28: extern "C" {
29: #endif
30:
31: #define DSP_RAMSIZE 32768
32:
33: /* Host port, CPU side */
34: #define CPU_HOST_ICR 0x00
35: #define CPU_HOST_CVR 0x01
36: #define CPU_HOST_ISR 0x02
37: #define CPU_HOST_IVR 0x03
1.1.1.2 root 38: #define CPU_HOST_TRX0 0x04
39: #define CPU_HOST_TRXH 0x05
40: #define CPU_HOST_TRXM 0x06
41: #define CPU_HOST_TRXL 0x07
1.1 root 42: #define CPU_HOST_RX0 0x04
43: #define CPU_HOST_RXH 0x05
44: #define CPU_HOST_RXM 0x06
45: #define CPU_HOST_RXL 0x07
1.1.1.2 root 46: #define CPU_HOST_TXH 0x09
47: #define CPU_HOST_TXM 0x0a
48: #define CPU_HOST_TXL 0x0b
1.1 root 49:
50: #define CPU_HOST_ICR_RREQ 0x00
51: #define CPU_HOST_ICR_TREQ 0x01
52: #define CPU_HOST_ICR_HF0 0x03
53: #define CPU_HOST_ICR_HF1 0x04
54: #define CPU_HOST_ICR_HM0 0x05
55: #define CPU_HOST_ICR_HM1 0x06
56: #define CPU_HOST_ICR_INIT 0x07
57:
58: #define CPU_HOST_CVR_HC 0x07
59:
60: #define CPU_HOST_ISR_RXDF 0x00
61: #define CPU_HOST_ISR_TXDE 0x01
62: #define CPU_HOST_ISR_TRDY 0x02
63: #define CPU_HOST_ISR_HF2 0x03
64: #define CPU_HOST_ISR_HF3 0x04
65: #define CPU_HOST_ISR_DMA 0x06
66: #define CPU_HOST_ISR_HREQ 0x07
67:
68: /* Host port, DSP side, DSP addresses are 0xffc0+value */
69: #define DSP_PBC 0x20 /* Port B control register */
70: #define DSP_PCC 0x21 /* Port C control register */
71: #define DSP_PBDDR 0x22 /* Port B data direction register */
72: #define DSP_PCDDR 0x23 /* Port C data direction register */
73: #define DSP_PBD 0x24 /* Port B data register */
74: #define DSP_PCD 0x25 /* Port C data register */
1.1.1.2 root 75: #define DSP_HOST_HCR 0x28 /* Host control register */
76: #define DSP_HOST_HSR 0x29 /* Host status register */
77: #define DSP_HOST_HRX 0x2b /* Host receive register */
78: #define DSP_HOST_HTX 0x2b /* Host transmit register */
1.1 root 79: #define DSP_SSI_CRA 0x2c /* Ssi control register A */
80: #define DSP_SSI_CRB 0x2d /* Ssi control register B */
81: #define DSP_SSI_SR 0x2e /* Ssi status register */
82: #define DSP_SSI_TSR 0x2e /* Ssi time slot register */
83: #define DSP_SSI_RX 0x2f /* Ssi receive register */
84: #define DSP_SSI_TX 0x2f /* Ssi transmit register */
85: #define DSP_BCR 0x3e /* Port A bus control register */
86: #define DSP_IPR 0x3f /* Interrupt priority register */
87:
88: #define DSP_HOST_HCR_HRIE 0x00
89: #define DSP_HOST_HCR_HTIE 0x01
90: #define DSP_HOST_HCR_HCIE 0x02
91: #define DSP_HOST_HCR_HF2 0x03
92: #define DSP_HOST_HCR_HF3 0x04
93:
94: #define DSP_HOST_HSR_HRDF 0x00
95: #define DSP_HOST_HSR_HTDE 0x01
96: #define DSP_HOST_HSR_HCP 0x02
97: #define DSP_HOST_HSR_HF0 0x03
98: #define DSP_HOST_HSR_HF1 0x04
99: #define DSP_HOST_HSR_DMA 0x07
100:
1.1.1.2 root 101: #define DSP_SSI_CRA_DC0 0x8
102: #define DSP_SSI_CRA_DC1 0x9
103: #define DSP_SSI_CRA_DC2 0xa
104: #define DSP_SSI_CRA_DC3 0xb
105: #define DSP_SSI_CRA_DC4 0xc
106: #define DSP_SSI_CRA_WL0 0xd
107: #define DSP_SSI_CRA_WL1 0xe
108:
109: #define DSP_SSI_CRB_OF0 0x0
110: #define DSP_SSI_CRB_OF1 0x1
111: #define DSP_SSI_CRB_SCD0 0x2
112: #define DSP_SSI_CRB_SCD1 0x3
113: #define DSP_SSI_CRB_SCD2 0x4
114: #define DSP_SSI_CRB_SCKD 0x5
115: #define DSP_SSI_CRB_SHFD 0x6
116: #define DSP_SSI_CRB_FSL0 0x7
117: #define DSP_SSI_CRB_FSL1 0x8
118: #define DSP_SSI_CRB_SYN 0x9
119: #define DSP_SSI_CRB_GCK 0xa
120: #define DSP_SSI_CRB_MOD 0xb
121: #define DSP_SSI_CRB_TE 0xc
122: #define DSP_SSI_CRB_RE 0xd
123: #define DSP_SSI_CRB_TIE 0xe
124: #define DSP_SSI_CRB_RIE 0xf
125:
126: #define DSP_SSI_SR_IF0 0x0
127: #define DSP_SSI_SR_IF1 0x1
128: #define DSP_SSI_SR_TFS 0x2
129: #define DSP_SSI_SR_RFS 0x3
130: #define DSP_SSI_SR_TUE 0x4
131: #define DSP_SSI_SR_ROE 0x5
132: #define DSP_SSI_SR_TDE 0x6
133: #define DSP_SSI_SR_RDF 0x7
134:
135: #define DSP_INTERRUPT_NONE 0x0
1.1.1.3 root 136: #define DSP_INTERRUPT_DISABLED 0x1
1.1.1.2 root 137: #define DSP_INTERRUPT_LONG 0x2
138:
139: #define DSP_INTER_RESET 0x0
140: #define DSP_INTER_ILLEGAL 0x1
141: #define DSP_INTER_STACK_ERROR 0x2
142: #define DSP_INTER_TRACE 0x3
143: #define DSP_INTER_SWI 0x4
144: #define DSP_INTER_HOST_COMMAND 0x5
145: #define DSP_INTER_HOST_RCV_DATA 0x6
146: #define DSP_INTER_HOST_TRX_DATA 0x7
1.1.1.3 root 147: #define DSP_INTER_SSI_RCV_DATA_E 0x8
148: #define DSP_INTER_SSI_RCV_DATA 0x9
149: #define DSP_INTER_SSI_TRX_DATA_E 0xa
150: #define DSP_INTER_SSI_TRX_DATA 0xb
1.1.1.2 root 151:
152:
153: typedef struct dsp_core_ssi_s dsp_core_ssi_t;
1.1.1.3 root 154: typedef struct dsp_core_s dsp_core_t;
155: typedef struct dsp_interrupt_s dsp_interrupt_t;
1.1.1.2 root 156:
157: struct dsp_core_ssi_s {
158: Uint16 cra_word_length;
159: Uint32 cra_word_mask;
160: Uint16 cra_frame_rate_divider;
161:
162: Uint16 crb_src_clock;
163: Uint16 crb_shifter;
164: Uint16 crb_synchro;
165: Uint16 crb_mode;
166: Uint16 crb_te;
167: Uint16 crb_re;
168: Uint16 crb_tie;
169: Uint16 crb_rie;
170:
171: Uint32 TX;
172: Uint32 RX;
173: Uint32 transmit_value; /* DSP Transmit --> SSI */
174: Uint32 received_value; /* DSP Receive --> SSI */
1.1.1.3 root 175: Uint16 waitFrameTX;
176: Uint16 waitFrameRX;
177: Uint32 dspPlay_handshakeMode_frame;
1.1.1.2 root 178: };
179:
1.1.1.3 root 180: struct dsp_interrupt_s {
181: const Uint16 inter;
182: const Uint16 vectorAddr;
183: const Uint16 periph;
184: const char *name;
185: };
1.1.1.2 root 186:
187:
188: struct dsp_core_s {
1.1 root 189:
190: /* DSP executing instructions ? */
191: volatile int running;
1.1.1.2 root 192:
193: /* DSP instruction Cycle counter */
194: Uint16 instr_cycle;
1.1 root 195:
196: /* Registers */
197: Uint16 pc;
198: Uint32 registers[64];
199:
200: /* stack[0=ssh], stack[1=ssl] */
1.1.1.2 root 201: Uint16 stack[2][16];
1.1 root 202:
1.1.1.3 root 203: /* External ram[] (mapped to p:) */
1.1.1.2 root 204: Uint32 ramext[DSP_RAMSIZE];
1.1 root 205:
206: /* rom[0] is x:, rom[1] is y: */
207: Uint32 rom[2][512];
208:
209: /* Internal ram[0] is x:, ram[1] is y:, ram[2] is p: */
210: Uint32 ramint[3][512];
211:
212: /* peripheral space, [x|y]:0xffc0-0xffff */
213: volatile Uint32 periph[2][64];
1.1.1.2 root 214: volatile Uint32 dsp_host_htx;
215: volatile Uint32 dsp_host_rtx;
1.1.1.3 root 216: Uint16 dsp_host_isr_HREQ;
1.1.1.2 root 217:
1.1 root 218:
219: /* host port, CPU side */
1.1.1.2 root 220: volatile Uint8 hostport[12];
221:
222: /* SSI */
223: dsp_core_ssi_t ssi;
1.1 root 224:
225: /* Misc */
226: Uint32 loop_rep; /* executing rep ? */
1.1.1.2 root 227: Uint32 pc_on_rep; /* True if PC is on REP instruction */
1.1 root 228:
229: /* For bootstrap routine */
230: Uint16 bootstrap_pos;
1.1.1.2 root 231:
232: /* Interruptions */
1.1.1.3 root 233: Uint16 interrupt_state; /* NONE, FAST or LONG interrupt */
234: Uint16 interrupt_instr_fetch; /* vector of the current interrupt */
235: Uint16 interrupt_save_pc; /* save next pc value before interrupt */
236: Uint16 interrupt_counter; /* count number of pending interrupts */
237: Uint16 interrupt_IplToRaise; /* save the IPL level to save in the SR register */
238: Uint16 interrupt_pipeline_count; /* used to prefetch correctly the 2 inter instructions */
239: Sint16 interrupt_ipl[12]; /* store the current IPL for each interrupt */
240: Uint16 interrupt_isPending[12]; /* store if interrupt is pending for each interrupt */
1.1.1.2 root 241: };
242:
1.1 root 243:
1.1.1.4 root 244: /* DSP */
245: extern dsp_core_t dsp_core;
246:
1.1 root 247: /* Emulator call these to init/stop/reset DSP emulation */
1.1.1.4 root 248: extern void dsp_core_init(void (*host_interrupt)(void));
249: extern void dsp_core_shutdown(void);
250: extern void dsp_core_reset(void);
1.1 root 251:
1.1.1.2 root 252: /* host port read/write by emulator, addr is 0-7, not 0xffa200-0xffa207 */
1.1.1.4 root 253: extern Uint8 dsp_core_read_host(int addr);
254: extern void dsp_core_write_host(int addr, Uint8 value);
1.1 root 255:
256: /* dsp_cpu call these to read/write host port */
1.1.1.4 root 257: extern void dsp_core_hostport_dspread(void);
258: extern void dsp_core_hostport_dspwrite(void);
1.1.1.2 root 259:
260: /* dsp_cpu call these to read/write/configure SSI port */
1.1.1.5 ! root 261: extern void dsp_core_ssi_configure(Uint32 address, Uint32 value);
1.1.1.4 root 262: extern void dsp_core_ssi_writeTX(Uint32 value);
263: extern void dsp_core_ssi_writeTSR(void);
264: extern Uint32 dsp_core_ssi_readRX(void);
265: extern void dsp_core_ssi_Receive_SC0(void);
266: extern void dsp_core_ssi_Receive_SC1(Uint32 value);
267: extern void dsp_core_ssi_Receive_SC2(Uint32 value);
268: extern void dsp_core_ssi_Receive_SCK(void);
269: extern void dsp_core_setPortCDataRegister(Uint32 value);
1.1 root 270:
271: #ifdef __cplusplus
272: }
273: #endif
274:
275: #endif /* DSP_CORE_H */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.