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1.1 root 1: /*
2: DSP M56001 emulation
3: Core of DSP emulation
4:
5: (C) 2003-2008 ARAnyM developer team
6:
7: This program is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2 of the License, or
10: (at your option) any later version.
11:
12: This program is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
1.1.1.7 ! root 18: along with this program; if not, write to the Free Software Foundation,
! 19: 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335 USA
1.1 root 20: */
21:
22: #ifndef DSP_CORE_H
23: #define DSP_CORE_H
24:
25: #include <SDL.h>
26:
27: #ifdef __cplusplus
28: extern "C" {
29: #endif
30:
31: #define DSP_RAMSIZE 32768
32:
33: /* Host port, CPU side */
34: #define CPU_HOST_ICR 0x00
35: #define CPU_HOST_CVR 0x01
36: #define CPU_HOST_ISR 0x02
37: #define CPU_HOST_IVR 0x03
1.1.1.2 root 38: #define CPU_HOST_TRX0 0x04
39: #define CPU_HOST_TRXH 0x05
40: #define CPU_HOST_TRXM 0x06
41: #define CPU_HOST_TRXL 0x07
1.1 root 42: #define CPU_HOST_RX0 0x04
43: #define CPU_HOST_RXH 0x05
44: #define CPU_HOST_RXM 0x06
45: #define CPU_HOST_RXL 0x07
1.1.1.2 root 46: #define CPU_HOST_TXH 0x09
47: #define CPU_HOST_TXM 0x0a
48: #define CPU_HOST_TXL 0x0b
1.1 root 49:
50: #define CPU_HOST_ICR_RREQ 0x00
51: #define CPU_HOST_ICR_TREQ 0x01
52: #define CPU_HOST_ICR_HF0 0x03
53: #define CPU_HOST_ICR_HF1 0x04
54: #define CPU_HOST_ICR_HM0 0x05
55: #define CPU_HOST_ICR_HM1 0x06
56: #define CPU_HOST_ICR_INIT 0x07
57:
58: #define CPU_HOST_CVR_HC 0x07
59:
60: #define CPU_HOST_ISR_RXDF 0x00
61: #define CPU_HOST_ISR_TXDE 0x01
62: #define CPU_HOST_ISR_TRDY 0x02
63: #define CPU_HOST_ISR_HF2 0x03
64: #define CPU_HOST_ISR_HF3 0x04
65: #define CPU_HOST_ISR_DMA 0x06
66: #define CPU_HOST_ISR_HREQ 0x07
67:
68: /* Host port, DSP side, DSP addresses are 0xffc0+value */
69: #define DSP_PBC 0x20 /* Port B control register */
70: #define DSP_PCC 0x21 /* Port C control register */
71: #define DSP_PBDDR 0x22 /* Port B data direction register */
72: #define DSP_PCDDR 0x23 /* Port C data direction register */
73: #define DSP_PBD 0x24 /* Port B data register */
74: #define DSP_PCD 0x25 /* Port C data register */
1.1.1.2 root 75: #define DSP_HOST_HCR 0x28 /* Host control register */
76: #define DSP_HOST_HSR 0x29 /* Host status register */
77: #define DSP_HOST_HRX 0x2b /* Host receive register */
78: #define DSP_HOST_HTX 0x2b /* Host transmit register */
1.1.1.7 ! root 79: #define DSP_SSI_CRA 0x2c /* SSI control register A */
! 80: #define DSP_SSI_CRB 0x2d /* SSI control register B */
! 81: #define DSP_SSI_SR 0x2e /* SSI status register */
! 82: #define DSP_SSI_TSR 0x2e /* SSI time slot register */
! 83: #define DSP_SSI_RX 0x2f /* SSI receive register */
! 84: #define DSP_SSI_TX 0x2f /* SSI transmit register */
! 85: #define DSP_SCI_SCR 0x30 /* SCI control register */
! 86: #define DSP_SCI_SSR 0x31 /* SCI status register */
! 87: #define DSP_SCI_SCCR 0x32 /* SCI clock control register */
1.1 root 88: #define DSP_BCR 0x3e /* Port A bus control register */
89: #define DSP_IPR 0x3f /* Interrupt priority register */
90:
91: #define DSP_HOST_HCR_HRIE 0x00
92: #define DSP_HOST_HCR_HTIE 0x01
93: #define DSP_HOST_HCR_HCIE 0x02
94: #define DSP_HOST_HCR_HF2 0x03
95: #define DSP_HOST_HCR_HF3 0x04
96:
97: #define DSP_HOST_HSR_HRDF 0x00
98: #define DSP_HOST_HSR_HTDE 0x01
99: #define DSP_HOST_HSR_HCP 0x02
100: #define DSP_HOST_HSR_HF0 0x03
101: #define DSP_HOST_HSR_HF1 0x04
102: #define DSP_HOST_HSR_DMA 0x07
103:
1.1.1.2 root 104: #define DSP_SSI_CRA_DC0 0x8
105: #define DSP_SSI_CRA_DC1 0x9
106: #define DSP_SSI_CRA_DC2 0xa
107: #define DSP_SSI_CRA_DC3 0xb
108: #define DSP_SSI_CRA_DC4 0xc
109: #define DSP_SSI_CRA_WL0 0xd
110: #define DSP_SSI_CRA_WL1 0xe
111:
112: #define DSP_SSI_CRB_OF0 0x0
113: #define DSP_SSI_CRB_OF1 0x1
114: #define DSP_SSI_CRB_SCD0 0x2
115: #define DSP_SSI_CRB_SCD1 0x3
116: #define DSP_SSI_CRB_SCD2 0x4
117: #define DSP_SSI_CRB_SCKD 0x5
118: #define DSP_SSI_CRB_SHFD 0x6
119: #define DSP_SSI_CRB_FSL0 0x7
120: #define DSP_SSI_CRB_FSL1 0x8
121: #define DSP_SSI_CRB_SYN 0x9
122: #define DSP_SSI_CRB_GCK 0xa
123: #define DSP_SSI_CRB_MOD 0xb
124: #define DSP_SSI_CRB_TE 0xc
125: #define DSP_SSI_CRB_RE 0xd
126: #define DSP_SSI_CRB_TIE 0xe
127: #define DSP_SSI_CRB_RIE 0xf
128:
129: #define DSP_SSI_SR_IF0 0x0
130: #define DSP_SSI_SR_IF1 0x1
131: #define DSP_SSI_SR_TFS 0x2
132: #define DSP_SSI_SR_RFS 0x3
133: #define DSP_SSI_SR_TUE 0x4
134: #define DSP_SSI_SR_ROE 0x5
135: #define DSP_SSI_SR_TDE 0x6
136: #define DSP_SSI_SR_RDF 0x7
137:
138: #define DSP_INTERRUPT_NONE 0x0
1.1.1.3 root 139: #define DSP_INTERRUPT_DISABLED 0x1
1.1.1.2 root 140: #define DSP_INTERRUPT_LONG 0x2
141:
142: #define DSP_INTER_RESET 0x0
143: #define DSP_INTER_ILLEGAL 0x1
144: #define DSP_INTER_STACK_ERROR 0x2
145: #define DSP_INTER_TRACE 0x3
146: #define DSP_INTER_SWI 0x4
147: #define DSP_INTER_HOST_COMMAND 0x5
148: #define DSP_INTER_HOST_RCV_DATA 0x6
149: #define DSP_INTER_HOST_TRX_DATA 0x7
1.1.1.3 root 150: #define DSP_INTER_SSI_RCV_DATA_E 0x8
151: #define DSP_INTER_SSI_RCV_DATA 0x9
152: #define DSP_INTER_SSI_TRX_DATA_E 0xa
153: #define DSP_INTER_SSI_TRX_DATA 0xb
1.1.1.2 root 154:
155:
156: typedef struct dsp_core_ssi_s dsp_core_ssi_t;
1.1.1.3 root 157: typedef struct dsp_core_s dsp_core_t;
158: typedef struct dsp_interrupt_s dsp_interrupt_t;
1.1.1.2 root 159:
160: struct dsp_core_ssi_s {
161: Uint16 cra_word_length;
162: Uint32 cra_word_mask;
163: Uint16 cra_frame_rate_divider;
164:
165: Uint16 crb_src_clock;
166: Uint16 crb_shifter;
167: Uint16 crb_synchro;
168: Uint16 crb_mode;
169: Uint16 crb_te;
170: Uint16 crb_re;
171: Uint16 crb_tie;
172: Uint16 crb_rie;
173:
174: Uint32 TX;
175: Uint32 RX;
176: Uint32 transmit_value; /* DSP Transmit --> SSI */
177: Uint32 received_value; /* DSP Receive --> SSI */
1.1.1.3 root 178: Uint16 waitFrameTX;
179: Uint16 waitFrameRX;
180: Uint32 dspPlay_handshakeMode_frame;
1.1.1.2 root 181: };
182:
1.1.1.3 root 183: struct dsp_interrupt_s {
184: const Uint16 inter;
185: const Uint16 vectorAddr;
186: const Uint16 periph;
187: const char *name;
188: };
1.1.1.2 root 189:
190:
191: struct dsp_core_s {
1.1 root 192:
193: /* DSP executing instructions ? */
1.1.1.6 root 194: int running;
195:
1.1.1.2 root 196: /* DSP instruction Cycle counter */
197: Uint16 instr_cycle;
1.1 root 198:
199: /* Registers */
200: Uint16 pc;
201: Uint32 registers[64];
202:
203: /* stack[0=ssh], stack[1=ssl] */
1.1.1.2 root 204: Uint16 stack[2][16];
1.1 root 205:
1.1.1.3 root 206: /* External ram[] (mapped to p:) */
1.1.1.2 root 207: Uint32 ramext[DSP_RAMSIZE];
1.1 root 208:
209: /* rom[0] is x:, rom[1] is y: */
210: Uint32 rom[2][512];
211:
212: /* Internal ram[0] is x:, ram[1] is y:, ram[2] is p: */
213: Uint32 ramint[3][512];
214:
215: /* peripheral space, [x|y]:0xffc0-0xffff */
1.1.1.6 root 216: Uint32 periph[2][64];
217: Uint32 dsp_host_htx;
218: Uint32 dsp_host_rtx;
1.1.1.3 root 219: Uint16 dsp_host_isr_HREQ;
1.1.1.2 root 220:
1.1 root 221:
222: /* host port, CPU side */
1.1.1.6 root 223: Uint8 hostport[12];
1.1.1.2 root 224:
225: /* SSI */
226: dsp_core_ssi_t ssi;
1.1 root 227:
228: /* Misc */
229: Uint32 loop_rep; /* executing rep ? */
1.1.1.2 root 230: Uint32 pc_on_rep; /* True if PC is on REP instruction */
1.1 root 231:
232: /* For bootstrap routine */
233: Uint16 bootstrap_pos;
1.1.1.2 root 234:
235: /* Interruptions */
1.1.1.3 root 236: Uint16 interrupt_state; /* NONE, FAST or LONG interrupt */
237: Uint16 interrupt_instr_fetch; /* vector of the current interrupt */
238: Uint16 interrupt_save_pc; /* save next pc value before interrupt */
239: Uint16 interrupt_counter; /* count number of pending interrupts */
240: Uint16 interrupt_IplToRaise; /* save the IPL level to save in the SR register */
241: Uint16 interrupt_pipeline_count; /* used to prefetch correctly the 2 inter instructions */
242: Sint16 interrupt_ipl[12]; /* store the current IPL for each interrupt */
243: Uint16 interrupt_isPending[12]; /* store if interrupt is pending for each interrupt */
1.1.1.6 root 244:
245: /* AGU pipeline simulation for indirect move ea instructions */
246: Uint16 agu_move_indirect_instr; /* is the current instruction an indirect move ? (LUA, MOVE, MOVEC, MOVEM, TCC) (0=no ; 1 = yes)*/
1.1.1.2 root 247: };
248:
1.1 root 249:
1.1.1.4 root 250: /* DSP */
251: extern dsp_core_t dsp_core;
252:
1.1 root 253: /* Emulator call these to init/stop/reset DSP emulation */
1.1.1.6 root 254: extern void dsp_core_init(void (*host_interrupt)(int));
1.1.1.4 root 255: extern void dsp_core_shutdown(void);
256: extern void dsp_core_reset(void);
1.1 root 257:
1.1.1.2 root 258: /* host port read/write by emulator, addr is 0-7, not 0xffa200-0xffa207 */
1.1.1.4 root 259: extern Uint8 dsp_core_read_host(int addr);
260: extern void dsp_core_write_host(int addr, Uint8 value);
1.1 root 261:
262: /* dsp_cpu call these to read/write host port */
1.1.1.4 root 263: extern void dsp_core_hostport_dspread(void);
264: extern void dsp_core_hostport_dspwrite(void);
1.1.1.2 root 265:
266: /* dsp_cpu call these to read/write/configure SSI port */
1.1.1.5 root 267: extern void dsp_core_ssi_configure(Uint32 address, Uint32 value);
1.1.1.4 root 268: extern void dsp_core_ssi_writeTX(Uint32 value);
269: extern void dsp_core_ssi_writeTSR(void);
270: extern Uint32 dsp_core_ssi_readRX(void);
271: extern void dsp_core_ssi_Receive_SC0(void);
272: extern void dsp_core_ssi_Receive_SC1(Uint32 value);
273: extern void dsp_core_ssi_Receive_SC2(Uint32 value);
274: extern void dsp_core_ssi_Receive_SCK(void);
275: extern void dsp_core_setPortCDataRegister(Uint32 value);
1.1 root 276:
277: #ifdef __cplusplus
278: }
279: #endif
280:
281: #endif /* DSP_CORE_H */
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