--- hatari/src/falcon/dsp_cpu.c 2019/04/09 08:57:02 1.1.1.12 +++ hatari/src/falcon/dsp_cpu.c 2019/04/09 08:59:33 1.1.1.14 @@ -15,8 +15,8 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + along with this program; if not, write to the Free Software Foundation, + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335 USA */ /* @@ -83,6 +83,12 @@ #define DSP_COUNT_IPS 0 /* Count instruction per seconds */ +#if DSP_COUNT_IPS +/* For counting instructions per second */ +#include +static Uint32 start_time; +static Uint32 num_inst; +#endif /********************************** * Defines @@ -103,10 +109,6 @@ * Variables **********************************/ -/* Instructions per second */ -static Uint32 start_time; -static Uint32 num_inst; - /* Length of current instruction */ static Uint32 cur_inst_len; /* =0:jump, >0:increment */ @@ -697,6 +699,13 @@ static const dsp_interrupt_t dsp_interru {DSP_INTER_SSI_TRX_DATA , 0x10, 2, "SSI tramsmit"} }; +static struct { + int limit; + int count; + Uint32 inst; + Uint16 pc; +} dsp_error; + /********************************** * Emulator kernel @@ -706,8 +715,12 @@ void dsp56k_init_cpu(void) { dsp56k_disasm_init(); isDsp_in_disasm_mode = false; + memset(&dsp_error, 0, sizeof(dsp_error)); + dsp_error.limit = 1; +#if DSP_COUNT_IPS start_time = SDL_GetTicks(); num_inst = 0; +#endif } /** @@ -1286,7 +1299,7 @@ static void write_memory_raw(int space, dsp_core_hostport_dspwrite(); break; case DSP_HOST_HCR: - dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] = value; + dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] = value & 0x1f; /* Set HF3 and HF2 accordingly on the host side */ dsp_core.hostport[CPU_HOST_ISR] &= BITMASK(8)-((1<= dsp_error.limit) { + dsp_error.inst = cur_inst; + dsp_error.pc = dsp_core.pc; + fprintf(stderr, "Dsp: 0x%04hx: 0x%06x Illegal instruction (%dx times)\n", + dsp_error.pc, dsp_error.inst, dsp_error.count); + if (dsp_error.count >= dsp_error.limit) { + /* next message after 2x more hits */ + dsp_error.limit *= 2; + } else { + dsp_error.limit = 1; + } + dsp_error.count = 0; + } + } else { cur_inst_len = 1; dsp_core.instr_cycle = 0; } @@ -3324,7 +3354,44 @@ static void dsp_rep_reg(void) static void dsp_reset(void) { - /* Reset external peripherals */ + /* Clear the IPR register */ + write_memory(DSP_SPACE_X, 0xffc0 + DSP_IPR, 0); + + /* Software reset all on-chip peripherals */ + + /* HOST_HCR x:$FFE8 : clear the full register */ + write_memory(DSP_SPACE_X, 0xffc0 + DSP_HOST_HCR, 0); + + /* HOST_ICR $0 : clear the full register */ + dsp_core_write_host(CPU_HOST_ICR, 0); + + /* HOST_CVR $1 : set the register to $12 */ + dsp_core_write_host(CPU_HOST_CVR, 0x12); + + /* HOST_ISR $2 : set the bits TRDY and TXDE 1, other bits to 0 */ + dsp_core.hostport[CPU_HOST_ISR] = (1<>23) & 1; dsp_core.registers[DSP_REG_A1] <<= 1; - dsp_core.registers[DSP_REG_A1] |= newcarry; + dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_SR] & 1; dsp_core.registers[DSP_REG_A1] &= BITMASK(24); dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<>23) & 1; dsp_core.registers[DSP_REG_B1] <<= 1; - dsp_core.registers[DSP_REG_B1] |= newcarry; + dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_SR] & 1; dsp_core.registers[DSP_REG_B1] &= BITMASK(24); dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<>= 1; - dsp_core.registers[DSP_REG_A1] |= newcarry<<23; + dsp_core.registers[DSP_REG_A1] |= (dsp_core.registers[DSP_REG_SR] & 1)<<23; dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<>= 1; - dsp_core.registers[DSP_REG_B1] |= newcarry<<23; + dsp_core.registers[DSP_REG_B1] |= (dsp_core.registers[DSP_REG_SR] & 1)<<23; dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<