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1.1 root 1: /*
1.1.1.2 root 2: DSP M56001 emulation
1.1.1.4 root 3: Instructions interpreter
1.1.1.2 root 4:
5: (C) 2003-2008 ARAnyM developer team
6:
7: This program is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2 of the License, or
10: (at your option) any later version.
11:
12: This program is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
18: along with this program; if not, write to the Free Software
19: Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20: */
21:
1.1.1.7 root 22: /*
23: DSP memory mapping
24: ------------------
25:
26: The memory map is configured as follows :
27: Program space P is one contiguous block of 32K dsp Words
28: X and Y data space are each separate 16K dsp Word blocks.
29: Both X and Y can be accessed as blocks starting at 0 or 16K.
30: Program space physically overlaps both X and Y data spaces.
31: Y: memory is mapped at address $0 in P memory
32: X: memory is mapped at address $4000 in P memory
33:
34: The DSP external RAM is zero waitstate, but there is a penalty for
1.1.1.9 root 35: accessing it twice or more in a single instruction, because there is only
36: one external data bus. The extra access costs 2 cycles penalty.
37:
1.1.1.7 root 38: The internal buses are all separate (0 waitstate)
39:
40:
41: X: Y: P:
42: $ffff |--------------+--------------+--------------|
43: | Int. I/O | Ext. I/O | |
44: $ffc0 |--------------+--------------+ |
45: | | | |
46: | Reserved | Reserved | Reserved |
47: | | | |
48: | | | |
49: | | | |
50: $8000 |--------------+--------------+--------------|
51: | | | |
52: | 16k Shadow | 16k Shadow | |
53: | | | 32K |
54: $4000 |--------------+--------------| Program |
55: | 16K | 16K | RAM |
56: | External | External | |
57: | RAM | RAM | |
58: $0200 |--------------+--------------+--------------|
59: | Log table or | Sin table or | |
60: | external mem | external mem | Internal |
61: $0100 |--------------+--------------+ program |
62: | Internal X | Internal Y | memory |
63: | memory | memory | |
64: $0000 |--------------+--------------+--------------|
65:
66:
67: Special Note : As the Falcon DSP is a 0 waitstate access memory, I've simplified a little the cycle counting.
68: If this DSP emulator code is used in another project, one should take into account the bus control register (BCR) waitstates.
69: */
70:
1.1.1.2 root 71: #ifdef HAVE_CONFIG_H
72: #include "config.h"
73: #endif
74:
1.1.1.6 root 75: #include <stdbool.h>
76:
1.1.1.10! root 77: #include "main.h"
1.1.1.2 root 78: #include "dsp_core.h"
1.1 root 79: #include "dsp_cpu.h"
80: #include "dsp_disasm.h"
1.1.1.6 root 81: #include "log.h"
1.1.1.9 root 82: #include "debugui.h"
1.1 root 83:
1.1.1.2 root 84: #define DSP_COUNT_IPS 0 /* Count instruction per seconds */
85:
1.1 root 86:
87: /**********************************
88: * Defines
89: **********************************/
90:
1.1.1.6 root 91: #define SIGN_PLUS 0
92: #define SIGN_MINUS 1
1.1.1.4 root 93:
1.1.1.9 root 94: /* Defines some bits values for access to external memory (X, Y, P) */
95: /* These values will set/unset the corresponding bits in the variable access_to_ext_memory */
96: /* to detect how many access to the external memory were done for a single instruction */
97: #define EXT_X_MEMORY 0
98: #define EXT_Y_MEMORY 1
99: #define EXT_P_MEMORY 2
100:
101:
1.1 root 102: /**********************************
103: * Variables
104: **********************************/
105:
1.1.1.4 root 106: /* Instructions per second */
107: static Uint32 start_time;
108: static Uint32 num_inst;
109:
1.1 root 110: /* Length of current instruction */
1.1.1.2 root 111: static Uint32 cur_inst_len; /* =0:jump, >0:increment */
1.1 root 112:
113: /* Current instruction */
1.1.1.4 root 114: static Uint32 cur_inst;
1.1 root 115:
1.1.1.7 root 116: /* Counts the number of access to the external memory for one instruction */
1.1.1.9 root 117: static Uint16 access_to_ext_memory;
1.1.1.7 root 118:
1.1.1.6 root 119: /* DSP is in disasm mode ? */
120: /* If yes, stack overflow, underflow and illegal instructions messages are not displayed */
121: static bool isDsp_in_disasm_mode;
1.1 root 122:
1.1.1.7 root 123: static char str_disasm_memory[2][50]; /* Buffer for memory change text in disasm mode */
1.1.1.5 root 124: static Uint16 disasm_memory_ptr; /* Pointer for memory change in disasm mode */
1.1 root 125:
126: /**********************************
127: * Functions
128: **********************************/
129:
130: typedef void (*dsp_emul_t)(void);
131:
132: static void dsp_postexecute_update_pc(void);
133: static void dsp_postexecute_interrupts(void);
134:
1.1.1.5 root 135: static void dsp_setInterruptIPL(Uint32 value);
136:
1.1.1.6 root 137: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2);
1.1.1.2 root 138:
139: static Uint32 read_memory(int space, Uint16 address);
1.1.1.6 root 140: static inline Uint32 read_memory_p(Uint16 address);
1.1.1.2 root 141: static Uint32 read_memory_disasm(int space, Uint16 address);
1.1.1.6 root 142:
143: static inline void write_memory(int space, Uint16 address, Uint32 value);
144: static void write_memory_raw(int space, Uint16 address, Uint32 value);
1.1.1.4 root 145: static void write_memory_disasm(int space, Uint16 address, Uint32 value);
1.1.1.6 root 146:
1.1.1.4 root 147: static void dsp_write_reg(Uint32 numreg, Uint32 value);
1.1 root 148:
1.1.1.4 root 149: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly);
1.1.1.2 root 150: static void dsp_stack_pop(Uint32 *curpc, Uint32 *cursr);
1.1.1.4 root 151: static void dsp_compute_ssh_ssl(void);
1.1 root 152:
153: static void opcode8h_0(void);
154:
1.1.1.2 root 155: static void dsp_update_rn(Uint32 numreg, Sint16 modifier);
156: static void dsp_update_rn_bitreverse(Uint32 numreg);
157: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier);
158: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr);
159: static int dsp_calc_cc(Uint32 cc_code);
1.1 root 160:
161: static void dsp_undefined(void);
162:
163: /* Instructions without parallel moves */
164: static void dsp_andi(void);
1.1.1.4 root 165: static void dsp_bchg_aa(void);
166: static void dsp_bchg_ea(void);
167: static void dsp_bchg_pp(void);
168: static void dsp_bchg_reg(void);
169: static void dsp_bclr_aa(void);
170: static void dsp_bclr_ea(void);
171: static void dsp_bclr_pp(void);
172: static void dsp_bclr_reg(void);
173: static void dsp_bset_aa(void);
174: static void dsp_bset_ea(void);
175: static void dsp_bset_pp(void);
176: static void dsp_bset_reg(void);
177: static void dsp_btst_aa(void);
178: static void dsp_btst_ea(void);
179: static void dsp_btst_pp(void);
180: static void dsp_btst_reg(void);
1.1 root 181: static void dsp_div(void);
182: static void dsp_enddo(void);
183: static void dsp_illegal(void);
1.1.1.4 root 184: static void dsp_jcc_imm(void);
185: static void dsp_jcc_ea(void);
186: static void dsp_jclr_aa(void);
187: static void dsp_jclr_ea(void);
188: static void dsp_jclr_pp(void);
189: static void dsp_jclr_reg(void);
190: static void dsp_jmp_ea(void);
191: static void dsp_jmp_imm(void);
192: static void dsp_jscc_ea(void);
193: static void dsp_jscc_imm(void);
194: static void dsp_jsclr_aa(void);
195: static void dsp_jsclr_ea(void);
196: static void dsp_jsclr_pp(void);
197: static void dsp_jsclr_reg(void);
198: static void dsp_jset_aa(void);
199: static void dsp_jset_ea(void);
200: static void dsp_jset_pp(void);
201: static void dsp_jset_reg(void);
202: static void dsp_jsr_ea(void);
203: static void dsp_jsr_imm(void);
204: static void dsp_jsset_aa(void);
205: static void dsp_jsset_ea(void);
206: static void dsp_jsset_pp(void);
207: static void dsp_jsset_reg(void);
1.1 root 208: static void dsp_lua(void);
1.1.1.4 root 209: static void dsp_movem_ea(void);
210: static void dsp_movem_aa(void);
1.1 root 211: static void dsp_nop(void);
212: static void dsp_norm(void);
213: static void dsp_ori(void);
214: static void dsp_reset(void);
215: static void dsp_rti(void);
216: static void dsp_rts(void);
217: static void dsp_stop(void);
218: static void dsp_swi(void);
219: static void dsp_tcc(void);
220: static void dsp_wait(void);
221:
1.1.1.3 root 222: static void dsp_do_ea(void);
223: static void dsp_do_aa(void);
224: static void dsp_do_imm(void);
225: static void dsp_do_reg(void);
226: static void dsp_rep_aa(void);
227: static void dsp_rep_ea(void);
228: static void dsp_rep_imm(void);
229: static void dsp_rep_reg(void);
230: static void dsp_movec_aa(void);
231: static void dsp_movec_ea(void);
232: static void dsp_movec_imm(void);
233: static void dsp_movec_reg(void);
1.1 root 234: static void dsp_movep_0(void);
235: static void dsp_movep_1(void);
1.1.1.4 root 236: static void dsp_movep_23(void);
1.1 root 237:
238: /* Parallel move analyzer */
1.1.1.2 root 239: static int dsp_pm_read_accu24(int numreg, Uint32 *dest);
1.1 root 240: static void dsp_pm_0(void);
241: static void dsp_pm_1(void);
242: static void dsp_pm_2(void);
243: static void dsp_pm_2_2(void);
244: static void dsp_pm_3(void);
245: static void dsp_pm_4(void);
1.1.1.4 root 246: static void dsp_pm_4x(void);
1.1 root 247: static void dsp_pm_5(void);
248: static void dsp_pm_8(void);
249:
250: /* 56bits arithmetic */
1.1.1.2 root 251: static Uint16 dsp_abs56(Uint32 *dest);
252: static Uint16 dsp_asl56(Uint32 *dest);
253: static Uint16 dsp_asr56(Uint32 *dest);
254: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest);
255: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest);
1.1.1.5 root 256: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe);
1.1.1.2 root 257: static void dsp_rnd56(Uint32 *dest);
1.1 root 258:
259: /* Instructions with parallel moves */
1.1.1.6 root 260: static void dsp_abs_a(void);
261: static void dsp_abs_b(void);
262: static void dsp_adc_x_a(void);
263: static void dsp_adc_x_b(void);
264: static void dsp_adc_y_a(void);
265: static void dsp_adc_y_b(void);
266: static void dsp_add_b_a(void);
267: static void dsp_add_a_b(void);
268: static void dsp_add_x_a(void);
269: static void dsp_add_x_b(void);
270: static void dsp_add_y_a(void);
271: static void dsp_add_y_b(void);
272: static void dsp_add_x0_a(void);
273: static void dsp_add_x0_b(void);
274: static void dsp_add_y0_a(void);
275: static void dsp_add_y0_b(void);
276: static void dsp_add_x1_a(void);
277: static void dsp_add_x1_b(void);
278: static void dsp_add_y1_a(void);
279: static void dsp_add_y1_b(void);
280: static void dsp_addl_b_a(void);
281: static void dsp_addl_b_a(void);
282: static void dsp_addl_a_b(void);
283: static void dsp_addr_b_a(void);
284: static void dsp_addr_a_b(void);
285: static void dsp_and_x0_a(void);
286: static void dsp_and_x0_b(void);
287: static void dsp_and_y0_a(void);
288: static void dsp_and_y0_b(void);
289: static void dsp_and_x1_a(void);
290: static void dsp_and_x1_b(void);
291: static void dsp_and_y1_a(void);
292: static void dsp_and_y1_b(void);
1.1.1.7 root 293: static void dsp_asl_a(void);
294: static void dsp_asl_b(void);
295: static void dsp_asr_a(void);
296: static void dsp_asr_b(void);
1.1.1.6 root 297: static void dsp_clr_a(void);
298: static void dsp_clr_b(void);
299: static void dsp_cmp_b_a(void);
300: static void dsp_cmp_a_b(void);
301: static void dsp_cmp_x0_a(void);
302: static void dsp_cmp_x0_b(void);
303: static void dsp_cmp_y0_a(void);
304: static void dsp_cmp_y0_b(void);
305: static void dsp_cmp_x1_a(void);
306: static void dsp_cmp_x1_b(void);
307: static void dsp_cmp_y1_a(void);
308: static void dsp_cmp_y1_b(void);
309: static void dsp_cmpm_b_a(void);
310: static void dsp_cmpm_a_b(void);
311: static void dsp_cmpm_x0_a(void);
312: static void dsp_cmpm_x0_b(void);
313: static void dsp_cmpm_y0_a(void);
314: static void dsp_cmpm_y0_b(void);
315: static void dsp_cmpm_x1_a(void);
316: static void dsp_cmpm_x1_b(void);
317: static void dsp_cmpm_y1_a(void);
318: static void dsp_cmpm_y1_b(void);
319: static void dsp_eor_x0_a(void);
320: static void dsp_eor_x0_b(void);
321: static void dsp_eor_y0_a(void);
322: static void dsp_eor_y0_b(void);
323: static void dsp_eor_x1_a(void);
324: static void dsp_eor_x1_b(void);
325: static void dsp_eor_y1_a(void);
326: static void dsp_eor_y1_b(void);
327: static void dsp_lsl_a(void);
328: static void dsp_lsl_b(void);
329: static void dsp_lsr_a(void);
330: static void dsp_lsr_b(void);
331: static void dsp_mac_p_x0_x0_a(void);
332: static void dsp_mac_m_x0_x0_a(void);
333: static void dsp_mac_p_x0_x0_b(void);
334: static void dsp_mac_m_x0_x0_b(void);
335: static void dsp_mac_p_y0_y0_a(void);
336: static void dsp_mac_m_y0_y0_a(void);
337: static void dsp_mac_p_y0_y0_b(void);
338: static void dsp_mac_m_y0_y0_b(void);
339: static void dsp_mac_p_x1_x0_a(void);
340: static void dsp_mac_m_x1_x0_a(void);
341: static void dsp_mac_p_x1_x0_b(void);
342: static void dsp_mac_m_x1_x0_b(void);
343: static void dsp_mac_p_y1_y0_a(void);
344: static void dsp_mac_m_y1_y0_a(void);
345: static void dsp_mac_p_y1_y0_b(void);
346: static void dsp_mac_m_y1_y0_b(void);
347: static void dsp_mac_p_x0_y1_a(void);
348: static void dsp_mac_m_x0_y1_a(void);
349: static void dsp_mac_p_x0_y1_b(void);
350: static void dsp_mac_m_x0_y1_b(void);
351: static void dsp_mac_p_y0_x0_a(void);
352: static void dsp_mac_m_y0_x0_a(void);
353: static void dsp_mac_p_y0_x0_b(void);
354: static void dsp_mac_m_y0_x0_b(void);
355: static void dsp_mac_p_x1_y0_a(void);
356: static void dsp_mac_m_x1_y0_a(void);
357: static void dsp_mac_p_x1_y0_b(void);
358: static void dsp_mac_m_x1_y0_b(void);
359: static void dsp_mac_p_y1_x1_a(void);
360: static void dsp_mac_m_y1_x1_a(void);
361: static void dsp_mac_p_y1_x1_b(void);
362: static void dsp_mac_m_y1_x1_b(void);
363: static void dsp_macr_p_x0_x0_a(void);
364: static void dsp_macr_m_x0_x0_a(void);
365: static void dsp_macr_p_x0_x0_b(void);
366: static void dsp_macr_m_x0_x0_b(void);
367: static void dsp_macr_p_y0_y0_a(void);
368: static void dsp_macr_m_y0_y0_a(void);
369: static void dsp_macr_p_y0_y0_b(void);
370: static void dsp_macr_m_y0_y0_b(void);
371: static void dsp_macr_p_x1_x0_a(void);
372: static void dsp_macr_m_x1_x0_a(void);
373: static void dsp_macr_p_x1_x0_b(void);
374: static void dsp_macr_m_x1_x0_b(void);
375: static void dsp_macr_p_y1_y0_a(void);
376: static void dsp_macr_m_y1_y0_a(void);
377: static void dsp_macr_p_y1_y0_b(void);
378: static void dsp_macr_m_y1_y0_b(void);
379: static void dsp_macr_p_x0_y1_a(void);
380: static void dsp_macr_m_x0_y1_a(void);
381: static void dsp_macr_p_x0_y1_b(void);
382: static void dsp_macr_m_x0_y1_b(void);
383: static void dsp_macr_p_y0_x0_a(void);
384: static void dsp_macr_m_y0_x0_a(void);
385: static void dsp_macr_p_y0_x0_b(void);
386: static void dsp_macr_m_y0_x0_b(void);
387: static void dsp_macr_p_x1_y0_a(void);
388: static void dsp_macr_m_x1_y0_a(void);
389: static void dsp_macr_p_x1_y0_b(void);
390: static void dsp_macr_m_x1_y0_b(void);
391: static void dsp_macr_p_y1_x1_a(void);
392: static void dsp_macr_m_y1_x1_a(void);
393: static void dsp_macr_p_y1_x1_b(void);
394: static void dsp_macr_m_y1_x1_b(void);
1.1 root 395: static void dsp_move(void);
1.1.1.6 root 396: static void dsp_mpy_p_x0_x0_a(void);
397: static void dsp_mpy_m_x0_x0_a(void);
398: static void dsp_mpy_p_x0_x0_b(void);
399: static void dsp_mpy_m_x0_x0_b(void);
400: static void dsp_mpy_p_y0_y0_a(void);
401: static void dsp_mpy_m_y0_y0_a(void);
402: static void dsp_mpy_p_y0_y0_b(void);
403: static void dsp_mpy_m_y0_y0_b(void);
404: static void dsp_mpy_p_x1_x0_a(void);
405: static void dsp_mpy_m_x1_x0_a(void);
406: static void dsp_mpy_p_x1_x0_b(void);
407: static void dsp_mpy_m_x1_x0_b(void);
408: static void dsp_mpy_p_y1_y0_a(void);
409: static void dsp_mpy_m_y1_y0_a(void);
410: static void dsp_mpy_p_y1_y0_b(void);
411: static void dsp_mpy_m_y1_y0_b(void);
412: static void dsp_mpy_p_x0_y1_a(void);
413: static void dsp_mpy_m_x0_y1_a(void);
414: static void dsp_mpy_p_x0_y1_b(void);
415: static void dsp_mpy_m_x0_y1_b(void);
416: static void dsp_mpy_p_y0_x0_a(void);
417: static void dsp_mpy_m_y0_x0_a(void);
418: static void dsp_mpy_p_y0_x0_b(void);
419: static void dsp_mpy_m_y0_x0_b(void);
420: static void dsp_mpy_p_x1_y0_a(void);
421: static void dsp_mpy_m_x1_y0_a(void);
422: static void dsp_mpy_p_x1_y0_b(void);
423: static void dsp_mpy_m_x1_y0_b(void);
424: static void dsp_mpy_p_y1_x1_a(void);
425: static void dsp_mpy_m_y1_x1_a(void);
426: static void dsp_mpy_p_y1_x1_b(void);
427: static void dsp_mpy_m_y1_x1_b(void);
428: static void dsp_mpyr_p_x0_x0_a(void);
429: static void dsp_mpyr_m_x0_x0_a(void);
430: static void dsp_mpyr_p_x0_x0_b(void);
431: static void dsp_mpyr_m_x0_x0_b(void);
432: static void dsp_mpyr_p_y0_y0_a(void);
433: static void dsp_mpyr_m_y0_y0_a(void);
434: static void dsp_mpyr_p_y0_y0_b(void);
435: static void dsp_mpyr_m_y0_y0_b(void);
436: static void dsp_mpyr_p_x1_x0_a(void);
437: static void dsp_mpyr_m_x1_x0_a(void);
438: static void dsp_mpyr_p_x1_x0_b(void);
439: static void dsp_mpyr_m_x1_x0_b(void);
440: static void dsp_mpyr_p_y1_y0_a(void);
441: static void dsp_mpyr_m_y1_y0_a(void);
442: static void dsp_mpyr_p_y1_y0_b(void);
443: static void dsp_mpyr_m_y1_y0_b(void);
444: static void dsp_mpyr_p_x0_y1_a(void);
445: static void dsp_mpyr_m_x0_y1_a(void);
446: static void dsp_mpyr_p_x0_y1_b(void);
447: static void dsp_mpyr_m_x0_y1_b(void);
448: static void dsp_mpyr_p_y0_x0_a(void);
449: static void dsp_mpyr_m_y0_x0_a(void);
450: static void dsp_mpyr_p_y0_x0_b(void);
451: static void dsp_mpyr_m_y0_x0_b(void);
452: static void dsp_mpyr_p_x1_y0_a(void);
453: static void dsp_mpyr_m_x1_y0_a(void);
454: static void dsp_mpyr_p_x1_y0_b(void);
455: static void dsp_mpyr_m_x1_y0_b(void);
456: static void dsp_mpyr_p_y1_x1_a(void);
457: static void dsp_mpyr_m_y1_x1_a(void);
458: static void dsp_mpyr_p_y1_x1_b(void);
459: static void dsp_mpyr_m_y1_x1_b(void);
460: static void dsp_neg_a(void);
461: static void dsp_neg_b(void);
462: static void dsp_not_a(void);
463: static void dsp_not_b(void);
464: static void dsp_or_x0_a(void);
465: static void dsp_or_x0_b(void);
466: static void dsp_or_y0_a(void);
467: static void dsp_or_y0_b(void);
468: static void dsp_or_x1_a(void);
469: static void dsp_or_x1_b(void);
470: static void dsp_or_y1_a(void);
471: static void dsp_or_y1_b(void);
472: static void dsp_rnd_a(void);
473: static void dsp_rnd_b(void);
474: static void dsp_rol_a(void);
475: static void dsp_rol_b(void);
476: static void dsp_ror_a(void);
477: static void dsp_ror_b(void);
478: static void dsp_sbc_x_a(void);
479: static void dsp_sbc_x_b(void);
480: static void dsp_sbc_y_a(void);
481: static void dsp_sbc_y_b(void);
482: static void dsp_sub_b_a(void);
483: static void dsp_sub_a_b(void);
484: static void dsp_sub_x_a(void);
485: static void dsp_sub_x_b(void);
486: static void dsp_sub_y_a(void);
487: static void dsp_sub_y_b(void);
488: static void dsp_sub_x0_a(void);
489: static void dsp_sub_x0_b(void);
490: static void dsp_sub_y0_a(void);
491: static void dsp_sub_y0_b(void);
492: static void dsp_sub_x1_a(void);
493: static void dsp_sub_x1_b(void);
494: static void dsp_sub_y1_a(void);
495: static void dsp_sub_y1_b(void);
496: static void dsp_subl_a(void);
497: static void dsp_subl_b(void);
498: static void dsp_subr_a(void);
499: static void dsp_subr_b(void);
500: static void dsp_tfr_b_a(void);
501: static void dsp_tfr_a_b(void);
502: static void dsp_tfr_x0_a(void);
503: static void dsp_tfr_x0_b(void);
504: static void dsp_tfr_y0_a(void);
505: static void dsp_tfr_y0_b(void);
506: static void dsp_tfr_x1_a(void);
507: static void dsp_tfr_x1_b(void);
508: static void dsp_tfr_y1_a(void);
509: static void dsp_tfr_y1_b(void);
510: static void dsp_tst_a(void);
511: static void dsp_tst_b(void);
1.1 root 512:
1.1.1.6 root 513: static const dsp_emul_t opcodes8h[512] = {
1.1.1.4 root 514: /* 0x00 - 0x3f */
515: opcode8h_0, dsp_undefined, dsp_undefined, dsp_undefined, opcode8h_0, dsp_andi, dsp_undefined, dsp_ori,
516: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
517: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
518: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
519: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
520: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
521: dsp_undefined, dsp_undefined, dsp_div, dsp_div, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
522: dsp_norm, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
523:
524: /* 0x40 - 0x7f */
525: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
526: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
527: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
528: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
529: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
530: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
531: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
532: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
533:
534: /* 0x80 - 0xbf */
535: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
536: dsp_lua, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
537: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
538: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
539: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
540: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
541: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
542: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
543:
544: /* 0xc0 - 0xff */
545: dsp_do_aa, dsp_rep_aa, dsp_do_aa, dsp_rep_aa, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
546: dsp_do_ea, dsp_rep_ea, dsp_do_ea, dsp_rep_ea, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
547: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
548: dsp_do_reg, dsp_rep_reg, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
549: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
550: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
551: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
552: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
553:
554: /* 0x100 - 0x13f */
1.1.1.6 root 555: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 556: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 557: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 558: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 559: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 560: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 561: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 562: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
563:
564: /* 0x140 - 0x17f */
565: dsp_bclr_aa, dsp_bset_aa, dsp_bclr_aa, dsp_bset_aa, dsp_jclr_aa, dsp_jset_aa, dsp_jclr_aa, dsp_jset_aa,
566: dsp_bclr_ea, dsp_bset_ea, dsp_bclr_ea, dsp_bset_ea, dsp_jclr_ea, dsp_jset_ea, dsp_jclr_ea, dsp_jset_ea,
567: dsp_bclr_pp, dsp_bset_pp, dsp_bclr_pp, dsp_bset_pp, dsp_jclr_pp, dsp_jset_pp, dsp_jclr_pp, dsp_jset_pp,
568: dsp_jclr_reg, dsp_jset_reg, dsp_bclr_reg, dsp_bset_reg, dsp_jmp_ea, dsp_jcc_ea, dsp_undefined, dsp_undefined,
569: dsp_bchg_aa, dsp_btst_aa, dsp_bchg_aa, dsp_btst_aa, dsp_jsclr_aa, dsp_jsset_aa, dsp_jsclr_aa, dsp_jsset_aa,
570: dsp_bchg_ea, dsp_btst_ea, dsp_bchg_ea, dsp_btst_ea, dsp_jsclr_ea, dsp_jsset_ea, dsp_jsclr_ea, dsp_jsset_ea,
571: dsp_bchg_pp, dsp_btst_pp, dsp_bchg_pp, dsp_btst_pp, dsp_jsclr_pp, dsp_jsset_pp, dsp_jsclr_pp, dsp_jsset_pp,
572: dsp_jsclr_reg, dsp_jsset_reg, dsp_bchg_reg, dsp_btst_reg, dsp_jsr_ea, dsp_jscc_ea, dsp_undefined, dsp_undefined,
573:
574: /* 0x180 - 0x1bf */
575: dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm,
576: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
577: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
578: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
579: dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm,
580: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
581: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
582: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
583:
584: /* 0x1c0 - 0x1ff */
585: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
586: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
587: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
588: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
589: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
590: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
591: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
592: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
1.1 root 593: };
594:
1.1.1.6 root 595: static const dsp_emul_t opcodes_parmove[16] = {
596: dsp_pm_0, dsp_pm_1, dsp_pm_2, dsp_pm_3, dsp_pm_4, dsp_pm_5, dsp_pm_5, dsp_pm_5,
597: dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8
1.1 root 598: };
599:
1.1.1.6 root 600: static const dsp_emul_t opcodes_alu[256] = {
1.1.1.4 root 601: /* 0x00 - 0x3f */
1.1.1.6 root 602: dsp_move , dsp_tfr_b_a, dsp_addr_b_a, dsp_tst_a, dsp_undefined, dsp_cmp_b_a, dsp_subr_a, dsp_cmpm_b_a,
603: dsp_undefined, dsp_tfr_a_b, dsp_addr_a_b, dsp_tst_b, dsp_undefined, dsp_cmp_a_b, dsp_subr_b, dsp_cmpm_a_b,
604: dsp_add_b_a, dsp_rnd_a, dsp_addl_b_a, dsp_clr_a, dsp_sub_b_a, dsp_undefined, dsp_subl_a, dsp_not_a,
605: dsp_add_a_b, dsp_rnd_b, dsp_addl_a_b, dsp_clr_b, dsp_sub_a_b, dsp_undefined, dsp_subl_b, dsp_not_b,
1.1.1.7 root 606: dsp_add_x_a, dsp_adc_x_a, dsp_asr_a, dsp_lsr_a, dsp_sub_x_a, dsp_sbc_x_a, dsp_abs_a, dsp_ror_a,
607: dsp_add_x_b, dsp_adc_x_b, dsp_asr_b, dsp_lsr_b, dsp_sub_x_b, dsp_sbc_x_b, dsp_abs_b, dsp_ror_b,
608: dsp_add_y_a, dsp_adc_y_a, dsp_asl_a, dsp_lsl_a, dsp_sub_y_a, dsp_sbc_y_a, dsp_neg_a, dsp_rol_a,
609: dsp_add_y_b, dsp_adc_y_b, dsp_asl_b, dsp_lsl_b, dsp_sub_y_b, dsp_sbc_y_b, dsp_neg_b, dsp_rol_b,
1.1.1.4 root 610:
611: /* 0x40 - 0x7f */
1.1.1.6 root 612: dsp_add_x0_a, dsp_tfr_x0_a, dsp_or_x0_a, dsp_eor_x0_a, dsp_sub_x0_a, dsp_cmp_x0_a, dsp_and_x0_a, dsp_cmpm_x0_a,
613: dsp_add_x0_b, dsp_tfr_x0_b, dsp_or_x0_b, dsp_eor_x0_b, dsp_sub_x0_b, dsp_cmp_x0_b, dsp_and_x0_b, dsp_cmpm_x0_b,
614: dsp_add_y0_a, dsp_tfr_y0_a, dsp_or_y0_a, dsp_eor_y0_a, dsp_sub_y0_a, dsp_cmp_y0_a, dsp_and_y0_a, dsp_cmpm_y0_a,
615: dsp_add_y0_b, dsp_tfr_y0_b, dsp_or_y0_b, dsp_eor_y0_b, dsp_sub_y0_b, dsp_cmp_y0_b, dsp_and_y0_b, dsp_cmpm_y0_b,
616: dsp_add_x1_a, dsp_tfr_x1_a, dsp_or_x1_a, dsp_eor_x1_a, dsp_sub_x1_a, dsp_cmp_x1_a, dsp_and_x1_a, dsp_cmpm_x1_a,
617: dsp_add_x1_b, dsp_tfr_x1_b, dsp_or_x1_b, dsp_eor_x1_b, dsp_sub_x1_b, dsp_cmp_x1_b, dsp_and_x1_b, dsp_cmpm_x1_b,
618: dsp_add_y1_a, dsp_tfr_y1_a, dsp_or_y1_a, dsp_eor_y1_a, dsp_sub_y1_a, dsp_cmp_y1_a, dsp_and_y1_a, dsp_cmpm_y1_a,
619: dsp_add_y1_b, dsp_tfr_y1_b, dsp_or_y1_b, dsp_eor_y1_b, dsp_sub_y1_b, dsp_cmp_y1_b, dsp_and_y1_b, dsp_cmpm_y1_b,
1.1.1.4 root 620:
621: /* 0x80 - 0xbf */
1.1.1.6 root 622: dsp_mpy_p_x0_x0_a, dsp_mpyr_p_x0_x0_a, dsp_mac_p_x0_x0_a, dsp_macr_p_x0_x0_a, dsp_mpy_m_x0_x0_a, dsp_mpyr_m_x0_x0_a, dsp_mac_m_x0_x0_a, dsp_macr_m_x0_x0_a,
623: dsp_mpy_p_x0_x0_b, dsp_mpyr_p_x0_x0_b, dsp_mac_p_x0_x0_b, dsp_macr_p_x0_x0_b, dsp_mpy_m_x0_x0_b, dsp_mpyr_m_x0_x0_b, dsp_mac_m_x0_x0_b, dsp_macr_m_x0_x0_b,
624: dsp_mpy_p_y0_y0_a, dsp_mpyr_p_y0_y0_a, dsp_mac_p_y0_y0_a, dsp_macr_p_y0_y0_a, dsp_mpy_m_y0_y0_a, dsp_mpyr_m_y0_y0_a, dsp_mac_m_y0_y0_a, dsp_macr_m_y0_y0_a,
625: dsp_mpy_p_y0_y0_b, dsp_mpyr_p_y0_y0_b, dsp_mac_p_y0_y0_b, dsp_macr_p_y0_y0_b, dsp_mpy_m_y0_y0_b, dsp_mpyr_m_y0_y0_b, dsp_mac_m_y0_y0_b, dsp_macr_m_y0_y0_b,
626: dsp_mpy_p_x1_x0_a, dsp_mpyr_p_x1_x0_a, dsp_mac_p_x1_x0_a, dsp_macr_p_x1_x0_a, dsp_mpy_m_x1_x0_a, dsp_mpyr_m_x1_x0_a, dsp_mac_m_x1_x0_a, dsp_macr_m_x1_x0_a,
627: dsp_mpy_p_x1_x0_b, dsp_mpyr_p_x1_x0_b, dsp_mac_p_x1_x0_b, dsp_macr_p_x1_x0_b, dsp_mpy_m_x1_x0_b, dsp_mpyr_m_x1_x0_b, dsp_mac_m_x1_x0_b, dsp_macr_m_x1_x0_b,
628: dsp_mpy_p_y1_y0_a, dsp_mpyr_p_y1_y0_a, dsp_mac_p_y1_y0_a, dsp_macr_p_y1_y0_a, dsp_mpy_m_y1_y0_a, dsp_mpyr_m_y1_y0_a, dsp_mac_m_y1_y0_a, dsp_macr_m_y1_y0_a,
629: dsp_mpy_p_y1_y0_b, dsp_mpyr_p_y1_y0_b, dsp_mac_p_y1_y0_b, dsp_macr_p_y1_y0_b, dsp_mpy_m_y1_y0_b, dsp_mpyr_m_y1_y0_b, dsp_mac_m_y1_y0_b, dsp_macr_m_y1_y0_b,
630:
631: /* 0xc0_m_ 0xff */
632: dsp_mpy_p_x0_y1_a, dsp_mpyr_p_x0_y1_a, dsp_mac_p_x0_y1_a, dsp_macr_p_x0_y1_a, dsp_mpy_m_x0_y1_a, dsp_mpyr_m_x0_y1_a, dsp_mac_m_x0_y1_a, dsp_macr_m_x0_y1_a,
633: dsp_mpy_p_x0_y1_b, dsp_mpyr_p_x0_y1_b, dsp_mac_p_x0_y1_b, dsp_macr_p_x0_y1_b, dsp_mpy_m_x0_y1_b, dsp_mpyr_m_x0_y1_b, dsp_mac_m_x0_y1_b, dsp_macr_m_x0_y1_b,
634: dsp_mpy_p_y0_x0_a, dsp_mpyr_p_y0_x0_a, dsp_mac_p_y0_x0_a, dsp_macr_p_y0_x0_a, dsp_mpy_m_y0_x0_a, dsp_mpyr_m_y0_x0_a, dsp_mac_m_y0_x0_a, dsp_macr_m_y0_x0_a,
635: dsp_mpy_p_y0_x0_b, dsp_mpyr_p_y0_x0_b, dsp_mac_p_y0_x0_b, dsp_macr_p_y0_x0_b, dsp_mpy_m_y0_x0_b, dsp_mpyr_m_y0_x0_b, dsp_mac_m_y0_x0_b, dsp_macr_m_y0_x0_b,
636: dsp_mpy_p_x1_y0_a, dsp_mpyr_p_x1_y0_a, dsp_mac_p_x1_y0_a, dsp_macr_p_x1_y0_a, dsp_mpy_m_x1_y0_a, dsp_mpyr_m_x1_y0_a, dsp_mac_m_x1_y0_a, dsp_macr_m_x1_y0_a,
637: dsp_mpy_p_x1_y0_b, dsp_mpyr_p_x1_y0_b, dsp_mac_p_x1_y0_b, dsp_macr_p_x1_y0_b, dsp_mpy_m_x1_y0_b, dsp_mpyr_m_x1_y0_b, dsp_mac_m_x1_y0_b, dsp_macr_m_x1_y0_b,
638: dsp_mpy_p_y1_x1_a, dsp_mpyr_p_y1_x1_a, dsp_mac_p_y1_x1_a, dsp_macr_p_y1_x1_a, dsp_mpy_m_y1_x1_a, dsp_mpyr_m_y1_x1_a, dsp_mac_m_y1_x1_a, dsp_macr_m_y1_x1_a,
639: dsp_mpy_p_y1_x1_b, dsp_mpyr_p_y1_x1_b, dsp_mac_p_y1_x1_b, dsp_macr_p_y1_x1_b, dsp_mpy_m_y1_x1_b, dsp_mpyr_m_y1_x1_b, dsp_mac_m_y1_x1_b, dsp_macr_m_y1_x1_b
1.1 root 640: };
641:
1.1.1.6 root 642: static const int registers_tcc[16][2] = {
1.1 root 643: {DSP_REG_B,DSP_REG_A},
644: {DSP_REG_A,DSP_REG_B},
645: {DSP_REG_NULL,DSP_REG_NULL},
646: {DSP_REG_NULL,DSP_REG_NULL},
647:
648: {DSP_REG_NULL,DSP_REG_NULL},
649: {DSP_REG_NULL,DSP_REG_NULL},
650: {DSP_REG_NULL,DSP_REG_NULL},
651: {DSP_REG_NULL,DSP_REG_NULL},
652:
653: {DSP_REG_X0,DSP_REG_A},
654: {DSP_REG_X0,DSP_REG_B},
655: {DSP_REG_Y0,DSP_REG_A},
656: {DSP_REG_Y0,DSP_REG_B},
1.1.1.2 root 657:
658: {DSP_REG_X1,DSP_REG_A},
659: {DSP_REG_X1,DSP_REG_B},
1.1 root 660: {DSP_REG_Y1,DSP_REG_A},
661: {DSP_REG_Y1,DSP_REG_B}
662: };
663:
1.1.1.6 root 664: static const int registers_mask[64] = {
1.1 root 665: 0, 0, 0, 0,
666: 24, 24, 24, 24,
667: 24, 24, 8, 8,
668: 24, 24, 24, 24,
669:
670: 16, 16, 16, 16,
671: 16, 16, 16, 16,
672: 16, 16, 16, 16,
673: 16, 16, 16, 16,
674:
675: 16, 16, 16, 16,
676: 16, 16, 16, 16,
677: 0, 0, 0, 0,
678: 0, 0, 0, 0,
679:
680: 0, 0, 0, 0,
681: 0, 0, 0, 0,
682: 0, 16, 8, 6,
1.1.1.4 root 683: 16, 16, 16, 16
684: };
685:
1.1.1.6 root 686: static const dsp_interrupt_t dsp_interrupt[12] = {
1.1.1.5 root 687: {DSP_INTER_RESET , 0x00, 0, "Reset"},
688: {DSP_INTER_ILLEGAL , 0x3e, 0, "Illegal"},
689: {DSP_INTER_STACK_ERROR , 0x02, 0, "Stack Error"},
690: {DSP_INTER_TRACE , 0x04, 0, "Trace"},
691: {DSP_INTER_SWI , 0x06, 0, "Swi"},
692: {DSP_INTER_HOST_COMMAND , 0xff, 1, "Host Command"},
693: {DSP_INTER_HOST_RCV_DATA, 0x20, 1, "Host receive"},
694: {DSP_INTER_HOST_TRX_DATA, 0x22, 1, "Host transmit"},
695: {DSP_INTER_SSI_RCV_DATA_E, 0x0e, 2, "SSI receive with exception"},
696: {DSP_INTER_SSI_RCV_DATA , 0x0c, 2, "SSI receive"},
697: {DSP_INTER_SSI_TRX_DATA_E, 0x12, 2, "SSI transmit with exception"},
698: {DSP_INTER_SSI_TRX_DATA , 0x10, 2, "SSI tramsmit"}
1.1.1.4 root 699: };
700:
1.1 root 701:
702: /**********************************
703: * Emulator kernel
704: **********************************/
705:
1.1.1.6 root 706: void dsp56k_init_cpu(void)
1.1 root 707: {
1.1.1.6 root 708: dsp56k_disasm_init();
709: isDsp_in_disasm_mode = false;
1.1.1.2 root 710: start_time = SDL_GetTicks();
711: num_inst = 0;
1.1 root 712: }
713:
1.1.1.6 root 714: /**
715: * Execute one instruction in trace mode at a given PC address.
716: * */
1.1.1.9 root 717: Uint16 dsp56k_execute_one_disasm_instruction(FILE *out, Uint16 pc)
1.1.1.6 root 718: {
719: dsp_core_t *ptr1, *ptr2;
720: static dsp_core_t dsp_core_save;
1.1.1.8 root 721: Uint16 instruction_length;
1.1.1.6 root 722:
723: ptr1 = &dsp_core;
724: ptr2 = &dsp_core_save;
725:
726: /* Set DSP in disasm mode */
727: isDsp_in_disasm_mode = true;
728:
729: /* Save DSP context before executing instruction */
730: memcpy(ptr2, ptr1, sizeof(dsp_core));
731:
732: /* execute and disasm instruction */
733: dsp_core.pc = pc;
734:
735: /* Disasm instruction */
736: instruction_length = dsp56k_disasm(DSP_DISASM_MODE) - 1;
737:
738: /* Execute instruction at address given in parameter to get the number of cycles it takes */
739: dsp56k_execute_instruction();
740:
1.1.1.9 root 741: fprintf(out, "%s", dsp56k_getInstructionText());
1.1.1.6 root 742:
743: /* Restore DSP context after executing instruction */
744: memcpy(ptr1, ptr2, sizeof(dsp_core));
745:
746: /* Unset DSP in disasm mode */
747: isDsp_in_disasm_mode = false;
748:
749: return instruction_length;
750: }
751:
1.1.1.4 root 752: void dsp56k_execute_instruction(void)
1.1 root 753: {
1.1.1.2 root 754: Uint32 value;
1.1.1.6 root 755: Uint32 disasm_return = 0;
1.1.1.5 root 756: disasm_memory_ptr = 0;
757:
1.1.1.7 root 758: /* Initialise the number of access to the external memory for this instruction */
1.1.1.9 root 759: access_to_ext_memory = 0;
1.1.1.7 root 760:
1.1 root 761: /* Decode and execute current instruction */
1.1.1.6 root 762: cur_inst = read_memory_p(dsp_core.pc);
1.1.1.4 root 763:
1.1.1.7 root 764: /* Initialize instruction size and cycle counter */
765: cur_inst_len = 1;
1.1.1.6 root 766: dsp_core.instr_cycle = 2;
1.1 root 767:
1.1.1.6 root 768: /* Disasm current instruction ? (trace mode only) */
769: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
770: /* Call dsp56k_disasm only when DSP is called in trace mode */
771: if (isDsp_in_disasm_mode == false) {
772: disasm_return = dsp56k_disasm(DSP_TRACE_MODE);
773:
774: if (disasm_return != 0 && LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG)) {
775: /* DSP regs trace enabled only if DSP DISASM is enabled */
776: dsp56k_disasm_reg_save();
777: }
778: }
779: }
780:
1.1.1.4 root 781: if (cur_inst < 0x100000) {
782: value = (cur_inst >> 11) & (BITMASK(6) << 3);
783: value += (cur_inst >> 5) & BITMASK(3);
1.1 root 784: opcodes8h[value]();
785: } else {
1.1.1.6 root 786: /* Do parallel move read */
787: opcodes_parmove[(cur_inst>>20) & BITMASK(4)]();
788: }
789:
1.1.1.7 root 790: /* Add the waitstate due to external memory access */
1.1.1.9 root 791: /* (2 extra cycles per extra access to the external memory after the first one */
792: if (access_to_ext_memory != 0) {
793: value = access_to_ext_memory & 1;
794: value += (access_to_ext_memory & 2) >> 1;
795: value += (access_to_ext_memory & 4) >> 2;
796:
797: if (value > 1)
798: dsp_core.instr_cycle += (value - 1) * 2;
799: }
800:
1.1.1.6 root 801: /* Disasm current instruction ? (trace mode only) */
802: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
803: /* Display only when DSP is called in trace mode */
804: if (isDsp_in_disasm_mode == false) {
805: if (disasm_return != 0) {
806: fprintf(stderr, "%s", dsp56k_getInstructionText());
807:
808: /* DSP regs trace enabled only if DSP DISASM is enabled */
809: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG))
810: dsp56k_disasm_reg_compare();
811:
812: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM)) {
813: /* 1 memory change to display ? */
814: if (disasm_memory_ptr == 1)
815: fprintf(stderr, "\t%s\n", str_disasm_memory[0]);
816: /* 2 memory changes to display ? */
817: else if (disasm_memory_ptr == 2) {
818: fprintf(stderr, "\t%s\n", str_disasm_memory[0]);
819: fprintf(stderr, "\t%s\n", str_disasm_memory[1]);
820: }
821: }
822: }
823: }
1.1 root 824: }
825:
1.1.1.4 root 826: /* Process the PC */
827: dsp_postexecute_update_pc();
1.1 root 828:
1.1.1.4 root 829: /* Process Interrupts */
1.1 root 830: dsp_postexecute_interrupts();
831:
1.1.1.4 root 832: #if DSP_COUNT_IPS
833: ++num_inst;
834: if ((num_inst & 63) == 0) {
835: /* Evaluate time after <N> instructions have been executed to avoid asking too frequently */
836: Uint32 cur_time = SDL_GetTicks();
837: if (cur_time-start_time>1000) {
838: fprintf(stderr, "Dsp: %d i/s\n", (num_inst*1000)/(cur_time-start_time));
839: start_time=cur_time;
840: num_inst=0;
841: }
842: }
843: #endif
1.1 root 844: }
845:
846: /**********************************
847: * Update the PC
848: **********************************/
849:
850: static void dsp_postexecute_update_pc(void)
851: {
852: /* When running a REP, PC must stay on the current instruction */
1.1.1.6 root 853: if (dsp_core.loop_rep) {
1.1 root 854: /* Is PC on the instruction to repeat ? */
1.1.1.6 root 855: if (dsp_core.pc_on_rep==0) {
856: --dsp_core.registers[DSP_REG_LC];
857: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1 root 858:
1.1.1.6 root 859: if (dsp_core.registers[DSP_REG_LC] > 0) {
1.1.1.7 root 860: cur_inst_len = 0; /* Stay on this instruction */
1.1 root 861: } else {
1.1.1.6 root 862: dsp_core.loop_rep = 0;
863: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[DSP_REG_LCSAVE];
1.1 root 864: }
865: } else {
866: /* Init LC at right value */
1.1.1.6 root 867: if (dsp_core.registers[DSP_REG_LC] == 0) {
868: dsp_core.registers[DSP_REG_LC] = 0x010000;
1.1 root 869: }
1.1.1.6 root 870: dsp_core.pc_on_rep = 0;
1.1 root 871: }
872: }
873:
874: /* Normal execution, go to next instruction */
1.1.1.6 root 875: dsp_core.pc += cur_inst_len;
1.1 root 876:
877: /* When running a DO loop, we test the end of loop with the */
878: /* updated PC, pointing to last instruction of the loop */
1.1.1.6 root 879: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_LF)) {
1.1 root 880:
881: /* Did we execute the last instruction in loop ? */
1.1.1.7 root 882: if (dsp_core.pc == dsp_core.registers[DSP_REG_LA] + 1) {
1.1.1.6 root 883: --dsp_core.registers[DSP_REG_LC];
884: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1 root 885:
1.1.1.7 root 886: if (dsp_core.registers[DSP_REG_LC] == 0) {
1.1 root 887: /* end of loop */
1.1.1.4 root 888: Uint32 saved_pc, saved_sr;
889:
890: dsp_stack_pop(&saved_pc, &saved_sr);
1.1.1.10! root 891: dsp_core.registers[DSP_REG_SR] &= 0x7fff;
1.1.1.6 root 892: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
893: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
1.1 root 894: } else {
895: /* Loop one more time */
1.1.1.6 root 896: dsp_core.pc = dsp_core.registers[DSP_REG_SSH];
1.1 root 897: }
898: }
899: }
900: }
901:
902: /**********************************
903: * Interrupts
904: **********************************/
905:
1.1.1.5 root 906: /* Post a new interrupt to the interrupt table */
907: void dsp_add_interrupt(Uint16 inter)
908: {
909: /* detect if this interrupt is used or not */
1.1.1.6 root 910: if (dsp_core.interrupt_ipl[inter] == -1)
1.1.1.5 root 911: return;
912:
913: /* add this interrupt to the pending interrupts table */
1.1.1.6 root 914: if (dsp_core.interrupt_isPending[inter] == 0) {
915: dsp_core.interrupt_isPending[inter] = 1;
916: dsp_core.interrupt_counter ++;
1.1.1.5 root 917: }
918: }
919:
920: static void dsp_setInterruptIPL(Uint32 value)
921: {
922: Uint32 ipl_ssi, ipl_hi, i;
923:
924: ipl_ssi = ((value >> 12) & 3) - 1;
925: ipl_hi = ((value >> 10) & 3) - 1;
926:
927: /* set IPL_HI */
1.1.1.7 root 928: for (i=5; i<8; i++) {
1.1.1.6 root 929: dsp_core.interrupt_ipl[i] = ipl_hi;
1.1.1.5 root 930: }
931:
932: /* set IPL_SSI */
1.1.1.7 root 933: for (i=8; i<12; i++) {
1.1.1.6 root 934: dsp_core.interrupt_ipl[i] = ipl_ssi;
1.1.1.5 root 935: }
936: }
937:
1.1 root 938: static void dsp_postexecute_interrupts(void)
939: {
1.1.1.5 root 940: Uint32 index, instr, i;
941: Sint32 ipl_to_raise, ipl_sr;
1.1.1.4 root 942:
943: /* REP is not interruptible */
1.1.1.6 root 944: if (dsp_core.loop_rep) {
1.1.1.4 root 945: return;
946: }
947:
948: /* A fast interrupt can not be interrupted. */
1.1.1.6 root 949: if (dsp_core.interrupt_state == DSP_INTERRUPT_DISABLED) {
1.1.1.5 root 950:
1.1.1.6 root 951: switch (dsp_core.interrupt_pipeline_count) {
1.1.1.5 root 952: case 5:
1.1.1.6 root 953: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 954: return;
955: case 4:
956: /* Prefetch interrupt instruction 1 */
1.1.1.6 root 957: dsp_core.interrupt_save_pc = dsp_core.pc;
958: dsp_core.pc = dsp_core.interrupt_instr_fetch;
1.1.1.5 root 959:
960: /* is it a LONG interrupt ? */
1.1.1.6 root 961: instr = read_memory_p(dsp_core.interrupt_instr_fetch);
1.1.1.5 root 962: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1.1.1.6 root 963: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
964: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
965: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1.1.1.5 root 966: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
967: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1.1.1.6 root 968: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1.1.1.5 root 969: }
1.1.1.6 root 970: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 971: return;
972: case 3:
973: /* Prefetch interrupt instruction 2 */
1.1.1.6 root 974: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+1) {
975: instr = read_memory_p(dsp_core.pc);
1.1.1.5 root 976: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1.1.1.6 root 977: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
978: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
979: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1.1.1.5 root 980: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
981: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1.1.1.6 root 982: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1.1.1.5 root 983: }
984: }
1.1.1.6 root 985: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 986: return;
987: case 2:
988: /* 1 instruction executed after interrupt */
989: /* before re enable interrupts */
990: /* Was it a FAST interrupt ? */
1.1.1.6 root 991: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+2) {
992: dsp_core.pc = dsp_core.interrupt_save_pc;
1.1.1.5 root 993: }
1.1.1.6 root 994: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 995: return;
996: case 1:
997: /* Last instruction executed after interrupt */
998: /* before re enable interrupts */
1.1.1.6 root 999: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 1000: return;
1001: case 0:
1002: /* Re enable interrupts */
1.1.1.6 root 1003: /* All 6 instruction are done, Interrupts can be enabled again */
1004: dsp_core.interrupt_save_pc = -1;
1005: dsp_core.interrupt_instr_fetch = -1;
1006: dsp_core.interrupt_state = DSP_INTERRUPT_NONE;
1007: break;
1.1.1.4 root 1008: }
1009: }
1.1 root 1010:
1.1.1.4 root 1011: /* Trace Interrupt ? */
1.1.1.6 root 1012: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_T)) {
1.1.1.5 root 1013: dsp_add_interrupt(DSP_INTER_TRACE);
1.1.1.4 root 1014: }
1015:
1016: /* No interrupt to execute */
1.1.1.6 root 1017: if (dsp_core.interrupt_counter == 0) {
1.1.1.4 root 1018: return;
1.1 root 1019: }
1020:
1.1.1.5 root 1021: /* search for an interrupt */
1.1.1.6 root 1022: ipl_sr = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_I0) & BITMASK(2);
1.1.1.5 root 1023: index = 0xffff;
1024: ipl_to_raise = -1;
1025:
1026: /* Arbitrate between all pending interrupts */
1027: for (i=0; i<12; i++) {
1.1.1.6 root 1028: if (dsp_core.interrupt_isPending[i] == 1) {
1.1.1.5 root 1029:
1030: /* level 3 interrupt ? */
1.1.1.6 root 1031: if (dsp_core.interrupt_ipl[i] == 3) {
1.1.1.5 root 1032: index = i;
1033: break;
1034: }
1.1 root 1035:
1.1.1.5 root 1036: /* level 0, 1 ,2 interrupt ? */
1037: /* if interrupt is masked in SR, don't process it */
1.1.1.6 root 1038: if (dsp_core.interrupt_ipl[i] < ipl_sr)
1.1.1.5 root 1039: continue;
1.1 root 1040:
1.1.1.5 root 1041: /* if interrupt is lower or equal than current arbitrated interrupt */
1.1.1.6 root 1042: if (dsp_core.interrupt_ipl[i] <= ipl_to_raise)
1.1.1.5 root 1043: continue;
1044:
1045: /* save current arbitrated interrupt */
1046: index = i;
1.1.1.6 root 1047: ipl_to_raise = dsp_core.interrupt_ipl[i];
1.1 root 1048: }
1049: }
1.1.1.4 root 1050:
1.1.1.5 root 1051: /* If there's no interrupt to process, return */
1052: if (index == 0xffff) {
1.1.1.4 root 1053: return;
1054: }
1055:
1.1.1.5 root 1056: /* remove this interrupt from the pending interrupts table */
1.1.1.6 root 1057: dsp_core.interrupt_isPending[index] = 0;
1058: dsp_core.interrupt_counter --;
1.1.1.5 root 1059:
1060: /* process arbritrated interrupt */
1.1.1.6 root 1061: ipl_to_raise = dsp_core.interrupt_ipl[index] + 1;
1.1.1.5 root 1062: if (ipl_to_raise > 3) {
1063: ipl_to_raise = 3;
1064: }
1065:
1.1.1.6 root 1066: dsp_core.interrupt_instr_fetch = dsp_interrupt[index].vectorAddr;
1067: dsp_core.interrupt_pipeline_count = 5;
1068: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1069: dsp_core.interrupt_IplToRaise = ipl_to_raise;
1070:
1071: LOG_TRACE(TRACE_DSP_INTERRUPT, "Dsp interrupt: %s\n", dsp_interrupt[index].name);
1.1.1.5 root 1072:
1073: /* SSI receive data with exception ? */
1.1.1.6 root 1074: if (dsp_core.interrupt_instr_fetch == 0xe) {
1075: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_ROE);
1.1.1.4 root 1076: }
1077:
1.1.1.5 root 1078: /* SSI transmit data with exception ? */
1.1.1.6 root 1079: else if (dsp_core.interrupt_instr_fetch == 0x12) {
1080: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_TUE);
1.1.1.4 root 1081: }
1082:
1083: /* host command ? */
1.1.1.6 root 1084: else if (dsp_core.interrupt_instr_fetch == 0xff) {
1.1.1.4 root 1085: /* Clear HC and HCP interrupt */
1.1.1.6 root 1086: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] &= 0xff - (1<<DSP_HOST_HSR_HCP);
1087: dsp_core.hostport[CPU_HOST_CVR] &= 0xff - (1<<CPU_HOST_CVR_HC);
1.1.1.4 root 1088:
1.1.1.6 root 1089: dsp_core.interrupt_instr_fetch = dsp_core.hostport[CPU_HOST_CVR] & BITMASK(5);
1090: dsp_core.interrupt_instr_fetch *= 2;
1.1.1.4 root 1091: }
1.1 root 1092: }
1093:
1094: /**********************************
1095: * Set/clear ccr bits
1096: **********************************/
1097:
1098: /* reg0 has bits 55..48 */
1099: /* reg1 has bits 47..24 */
1100: /* reg2 has bits 23..0 */
1101:
1.1.1.6 root 1102: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2)
1103: {
1104: Uint32 scaling, value_e, value_u;
1.1.1.4 root 1105:
1.1.1.6 root 1106: /* Initialize SR register */
1107: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E) | (1<<DSP_SR_U) | (1<<DSP_SR_N) | (1<<DSP_SR_Z));
1.1.1.4 root 1108:
1.1.1.6 root 1109: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
1.1 root 1110: switch(scaling) {
1111: case 0:
1.1.1.6 root 1112: /* Extension Bit (E) */
1113: value_e = (reg0<<1) + (reg1>>23);
1114: if ((value_e != 0) && (value_e != BITMASK(9)))
1115: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1116:
1117: /* Unnormalized bit (U) */
1118: if ((reg1 & 0xc00000) == 0 || (reg1 & 0xc00000) == 0xc00000)
1119: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1120: break;
1121: case 1:
1.1.1.6 root 1122: /* Extension Bit (E) */
1123: if ((reg0 != 0) && (reg0 != BITMASK(8)))
1124: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1125:
1126: /* Unnormalized bit (U) */
1127: value_u = ((reg0<<1) + (reg1>>23)) & 3;
1128: if (value_u == 0 || value_u == 3)
1129: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1130: break;
1131: case 2:
1.1.1.6 root 1132: /* Extension Bit (E) */
1133: value_e = (reg0<<2) + (reg1>>22);
1134: if ((value_e != 0) && (value_e != BITMASK(10)))
1135: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1136:
1137: /* Unnormalized bit (U) */
1138: if ((reg1 & 0x600000) == 0 || (reg1 & 0x600000) == 0x600000)
1139: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1140: break;
1141: default:
1142: return;
1143: break;
1144: }
1145:
1.1.1.6 root 1146: /* Zero Flag (Z) */
1147: if ((reg1 == 0) && (reg2 == 0) && (reg0 == 0))
1148: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_Z;
1.1.1.4 root 1149:
1.1.1.6 root 1150: /* Negative Flag (N) */
1151: dsp_core.registers[DSP_REG_SR] |= (reg0>>4) & 0x8;
1.1 root 1152: }
1153:
1154: /**********************************
1155: * Read/Write memory functions
1156: **********************************/
1157:
1.1.1.2 root 1158: static Uint32 read_memory_disasm(int space, Uint16 address)
1.1 root 1159: {
1.1.1.4 root 1160: /* Internal RAM ? */
1161: if (address<0x100) {
1.1.1.6 root 1162: return dsp_core.ramint[space][address] & BITMASK(24);
1.1.1.4 root 1163: }
1.1 root 1164:
1.1.1.4 root 1165: if (space==DSP_SPACE_P) {
1166: return read_memory_p(address);
1.1 root 1167: }
1168:
1.1.1.4 root 1169: /* Internal ROM? */
1.1.1.6 root 1170: if ((dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) &&
1.1.1.4 root 1171: (address<0x200)) {
1.1.1.6 root 1172: return dsp_core.rom[space][address] & BITMASK(24);
1.1.1.4 root 1173: }
1174:
1175: /* Peripheral address ? */
1176: if (address >= 0xffc0) {
1.1.1.6 root 1177: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_HOST_HTX)) {
1178: return dsp_core.dsp_host_htx;
1.1.1.4 root 1179: }
1180: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_SSI_TX)) {
1.1.1.6 root 1181: return dsp_core.ssi.transmit_value;
1.1.1.4 root 1182: }
1.1.1.6 root 1183: return dsp_core.periph[space][address-0xffc0] & BITMASK(24);
1.1.1.4 root 1184: }
1185:
1186: /* Falcon: External RAM, map X to upper 16K of matching space in Y,P */
1187: address &= (DSP_RAMSIZE>>1) - 1;
1188: if (space == DSP_SPACE_X) {
1189: address += DSP_RAMSIZE>>1;
1190: }
1191:
1192: /* Falcon: External RAM, finally map X,Y to P */
1.1.1.6 root 1193: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1.1 root 1194: }
1195:
1.1.1.4 root 1196: static inline Uint32 read_memory_p(Uint16 address)
1197: {
1198: /* Internal RAM ? */
1.1.1.7 root 1199: if (address < 0x200) {
1.1.1.6 root 1200: return dsp_core.ramint[DSP_SPACE_P][address] & BITMASK(24);
1.1.1.4 root 1201: }
1202:
1.1.1.9 root 1203: /* Access to the external P memory */
1204: access_to_ext_memory |= 1 << EXT_P_MEMORY;
1.1.1.7 root 1205:
1.1.1.4 root 1206: /* External RAM, mask address to available ram size */
1.1.1.6 root 1207: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1.1.1.4 root 1208: }
1209:
1.1.1.2 root 1210: static Uint32 read_memory(int space, Uint16 address)
1.1 root 1211: {
1.1.1.4 root 1212: Uint32 value;
1.1 root 1213:
1.1.1.4 root 1214: /* Internal RAM ? */
1215: if (address < 0x100) {
1.1.1.6 root 1216: return dsp_core.ramint[space][address] & BITMASK(24);
1.1.1.4 root 1217: }
1.1 root 1218:
1.1.1.4 root 1219: if (space == DSP_SPACE_P) {
1220: return read_memory_p(address);
1221: }
1222:
1223: /* Internal ROM ? */
1224: if (address < 0x200) {
1.1.1.6 root 1225: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1226: return dsp_core.rom[space][address] & BITMASK(24);
1.1.1.4 root 1227: }
1228: }
1229:
1230: /* Peripheral address ? */
1231: if (address >= 0xffc0) {
1.1.1.6 root 1232: value = dsp_core.periph[space][address-0xffc0] & BITMASK(24);
1.1.1.4 root 1233: if (space == DSP_SPACE_X) {
1234: if (address == 0xffc0+DSP_HOST_HRX) {
1.1.1.6 root 1235: value = dsp_core.dsp_host_rtx;
1236: dsp_core_hostport_dspread();
1.1.1.4 root 1237: }
1238: else if (address == 0xffc0+DSP_SSI_RX) {
1.1.1.6 root 1239: value = dsp_core_ssi_readRX();
1.1 root 1240: }
1.1.1.4 root 1241: }
1242: return value;
1.1 root 1243: }
1244:
1.1.1.9 root 1245: /* Falcon: External X or Y RAM access */
1.1.1.4 root 1246: address &= (DSP_RAMSIZE>>1) - 1;
1247:
1248: if (space == DSP_SPACE_X) {
1.1.1.9 root 1249: /* Map X to upper 16K of matching space in Y,P */
1.1.1.4 root 1250: address += DSP_RAMSIZE>>1;
1.1.1.9 root 1251:
1252: /* Set one access to the X external memory */
1253: access_to_ext_memory |= 1 << EXT_X_MEMORY;
1254: }
1255: else {
1256: /* Access to the Y external memory */
1257: access_to_ext_memory |= 1 << EXT_Y_MEMORY;
1.1.1.4 root 1258: }
1259:
1.1.1.9 root 1260:
1.1.1.4 root 1261: /* Falcon: External RAM, finally map X,Y to P */
1.1.1.6 root 1262: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1263: }
1264:
1265: static inline void write_memory(int space, Uint16 address, Uint32 value)
1266: {
1.1.1.7 root 1267: if (unlikely(LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM)))
1.1.1.6 root 1268: write_memory_disasm(space, address, value);
1269: else
1270: write_memory_raw(space, address, value);
1.1 root 1271: }
1272:
1.1.1.4 root 1273: static void write_memory_raw(int space, Uint16 address, Uint32 value)
1.1 root 1274: {
1275: value &= BITMASK(24);
1276:
1.1.1.4 root 1277: /* Peripheral address ? */
1278: if (address >= 0xffc0) {
1279: if (space == DSP_SPACE_X) {
1280: switch(address-0xffc0) {
1281: case DSP_HOST_HTX:
1.1.1.6 root 1282: dsp_core.dsp_host_htx = value;
1283: dsp_core_hostport_dspwrite();
1.1.1.4 root 1284: break;
1285: case DSP_HOST_HCR:
1.1.1.6 root 1286: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] = value;
1.1.1.4 root 1287: /* Set HF3 and HF2 accordingly on the host side */
1.1.1.6 root 1288: dsp_core.hostport[CPU_HOST_ISR] &=
1.1.1.4 root 1289: BITMASK(8)-((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1.1.1.6 root 1290: dsp_core.hostport[CPU_HOST_ISR] |=
1291: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] & ((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1.1.1.4 root 1292: break;
1293: case DSP_HOST_HSR:
1294: /* Read only */
1295: break;
1296: case DSP_SSI_CRA:
1297: case DSP_SSI_CRB:
1.1.1.6 root 1298: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1299: dsp_core_ssi_configure(address-0xffc0, value);
1.1.1.4 root 1300: break;
1301: case DSP_SSI_TSR:
1.1.1.6 root 1302: dsp_core_ssi_writeTSR();
1.1.1.4 root 1303: break;
1304: case DSP_SSI_TX:
1.1.1.6 root 1305: dsp_core_ssi_writeTX(value);
1.1.1.4 root 1306: break;
1.1.1.5 root 1307: case DSP_IPR:
1.1.1.6 root 1308: dsp_core.periph[DSP_SPACE_X][DSP_IPR] = value;
1.1.1.5 root 1309: dsp_setInterruptIPL(value);
1310: break;
1311: case DSP_PCD:
1.1.1.6 root 1312: dsp_core.periph[DSP_SPACE_X][DSP_PCD] = value;
1313: dsp_core_setPortCDataRegister(value);
1.1.1.5 root 1314: break;
1.1.1.4 root 1315: default:
1.1.1.6 root 1316: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1.1.1.4 root 1317: break;
1.1 root 1318: }
1.1.1.4 root 1319: return;
1320: }
1321: else if (space == DSP_SPACE_Y) {
1.1.1.6 root 1322: dsp_core.periph[DSP_SPACE_Y][address-0xffc0] = value;
1.1.1.4 root 1323: return;
1324: }
1325: }
1326:
1327: /* Internal RAM ? */
1328: if (address < 0x100) {
1.1.1.6 root 1329: dsp_core.ramint[space][address] = value;
1.1.1.4 root 1330: return;
1331: }
1.1.1.2 root 1332:
1.1.1.4 root 1333: /* Internal ROM ? */
1334: if (address < 0x200) {
1335: if (space != DSP_SPACE_P) {
1.1.1.6 root 1336: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1.1.1.2 root 1337: /* Can not write to ROM space */
1.1 root 1338: return;
1339: }
1.1.1.4 root 1340: }
1341: else {
1342: /* Space P RAM */
1.1.1.6 root 1343: dsp_core.ramint[DSP_SPACE_P][address] = value;
1.1.1.4 root 1344: return;
1345: }
1.1 root 1346: }
1347:
1.1.1.9 root 1348: /* Access to X, Y or P external RAM */
1.1.1.4 root 1349:
1.1.1.9 root 1350: if (space == DSP_SPACE_P) {
1351: /* Access to the P external RAM */
1352: access_to_ext_memory |= 1 << EXT_P_MEMORY;
1353: }
1354: else {
1.1.1.4 root 1355: address &= (DSP_RAMSIZE>>1) - 1;
1356:
1.1.1.9 root 1357: if (space == DSP_SPACE_X) {
1358: /* Access to the X external RAM */
1359: /* map X to upper 16K of matching space in Y,P */
1360: address += DSP_RAMSIZE>>1;
1361: access_to_ext_memory |= 1;
1362: }
1363: else {
1364: /* Access to the Y external RAM */
1365: access_to_ext_memory |= 1 << EXT_Y_MEMORY;
1366: }
1.1.1.4 root 1367: }
1368:
1369: /* Falcon: External RAM, map X,Y to P */
1.1.1.6 root 1370: dsp_core.ramext[address & (DSP_RAMSIZE-1)] = value;
1.1.1.2 root 1371: }
1372:
1.1.1.4 root 1373: static void write_memory_disasm(int space, Uint16 address, Uint32 value)
1.1.1.2 root 1374: {
1.1.1.4 root 1375: Uint32 oldvalue, curvalue;
1376: Uint8 space_c = 'p';
1377:
1.1.1.2 root 1378: value &= BITMASK(24);
1.1.1.6 root 1379: oldvalue = read_memory_disasm(space, address);
1.1.1.2 root 1380:
1381: write_memory_raw(space,address,value);
1382:
1.1 root 1383: switch(space) {
1384: case DSP_SPACE_X:
1.1.1.4 root 1385: space_c = 'x';
1.1 root 1386: break;
1387: case DSP_SPACE_Y:
1.1.1.4 root 1388: space_c = 'y';
1389: break;
1390: default:
1.1 root 1391: break;
1392: }
1.1.1.4 root 1393:
1.1.1.6 root 1394: curvalue = read_memory_disasm(space, address);
1.1.1.5 root 1395: sprintf(str_disasm_memory[disasm_memory_ptr],"Mem: %c:0x%04x 0x%06x -> 0x%06x", space_c, address, oldvalue, curvalue);
1396: disasm_memory_ptr ++;
1.1 root 1397: }
1398:
1.1.1.4 root 1399: static void dsp_write_reg(Uint32 numreg, Uint32 value)
1400: {
1.1.1.5 root 1401: Uint32 stack_error;
1.1.1.4 root 1402:
1.1.1.7 root 1403: switch (numreg) {
1404: case DSP_REG_A:
1405: dsp_core.registers[DSP_REG_A0] = 0;
1406: dsp_core.registers[DSP_REG_A1] = value;
1407: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
1408: break;
1409: case DSP_REG_B:
1410: dsp_core.registers[DSP_REG_B0] = 0;
1411: dsp_core.registers[DSP_REG_B1] = value;
1412: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
1413: break;
1414: case DSP_REG_OMR:
1415: dsp_core.registers[DSP_REG_OMR] = value & 0xc7;
1416: break;
1417: case DSP_REG_SR:
1418: dsp_core.registers[DSP_REG_SR] = value & 0xaf7f;
1419: break;
1420: case DSP_REG_SP:
1.1.1.8 root 1421: stack_error = dsp_core.registers[DSP_REG_SP] & (3<<DSP_SP_SE);
1422: if ((stack_error==0) && (value & (3<<DSP_SP_SE))) {
1423: /* Stack underflow or overflow detected, raise interrupt */
1.1.1.7 root 1424: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.9 root 1425: dsp_core.registers[DSP_REG_SP] = value & (3<<DSP_SP_SE);
1.1.1.7 root 1426: if (!isDsp_in_disasm_mode)
1.1.1.8 root 1427: fprintf(stderr,"Dsp: Stack Overflow or Underflow\n");
1.1.1.10! root 1428: if (ExceptionDebugMask & EXCEPT_DSP)
1.1.1.9 root 1429: DebugUI(REASON_DSP_EXCEPTION);
1.1.1.7 root 1430: }
1.1.1.8 root 1431: else
1432: dsp_core.registers[DSP_REG_SP] = value & BITMASK(6);
1.1.1.7 root 1433: dsp_compute_ssh_ssl();
1434: break;
1435: case DSP_REG_SSH:
1436: dsp_stack_push(value, 0, 1);
1437: break;
1438: case DSP_REG_SSL:
1439: numreg = dsp_core.registers[DSP_REG_SP] & BITMASK(4);
1440: if (numreg == 0) {
1441: value = 0;
1442: }
1443: dsp_core.stack[1][numreg] = value & BITMASK(16);
1444: dsp_core.registers[DSP_REG_SSL] = value & BITMASK(16);
1445: break;
1446: default:
1447: dsp_core.registers[numreg] = value;
1448: dsp_core.registers[numreg] &= BITMASK(registers_mask[numreg]);
1449: break;
1.1.1.4 root 1450: }
1451: }
1452:
1.1 root 1453: /**********************************
1454: * Stack push/pop
1455: **********************************/
1456:
1.1.1.4 root 1457: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly)
1.1 root 1458: {
1.1.1.4 root 1459: Uint32 stack_error, underflow, stack;
1460:
1.1.1.6 root 1461: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1462: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1463: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) + 1;
1.1.1.4 root 1464:
1465:
1466: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1.1 root 1467: /* Stack full, raise interrupt */
1.1.1.5 root 1468: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.6 root 1469: if (!isDsp_in_disasm_mode)
1470: fprintf(stderr,"Dsp: Stack Overflow\n");
1.1.1.10! root 1471: if (ExceptionDebugMask & EXCEPT_DSP)
1.1.1.9 root 1472: DebugUI(REASON_DSP_EXCEPTION);
1.1 root 1473: }
1.1.1.4 root 1474:
1.1.1.6 root 1475: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1.1.1.4 root 1476: stack &= BITMASK(4);
1.1 root 1477:
1.1.1.4 root 1478: if (stack) {
1479: /* SSH part */
1.1.1.6 root 1480: dsp_core.stack[0][stack] = curpc & BITMASK(16);
1.1.1.4 root 1481: /* SSL part, if instruction is not like "MOVEC xx, SSH" */
1482: if (sshOnly == 0) {
1.1.1.6 root 1483: dsp_core.stack[1][stack] = cursr & BITMASK(16);
1.1.1.4 root 1484: }
1485: } else {
1.1.1.6 root 1486: dsp_core.stack[0][0] = 0;
1487: dsp_core.stack[1][0] = 0;
1.1.1.4 root 1488: }
1.1 root 1489:
1.1.1.4 root 1490: /* Update SSH and SSL registers */
1.1.1.6 root 1491: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1492: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1 root 1493: }
1494:
1.1.1.2 root 1495: static void dsp_stack_pop(Uint32 *newpc, Uint32 *newsr)
1.1 root 1496: {
1.1.1.4 root 1497: Uint32 stack_error, underflow, stack;
1498:
1.1.1.6 root 1499: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1500: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1501: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) - 1;
1.1.1.4 root 1502:
1503: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1504: /* Stack empty*/
1.1.1.5 root 1505: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.6 root 1506: if (!isDsp_in_disasm_mode)
1507: fprintf(stderr,"Dsp: Stack underflow\n");
1.1.1.10! root 1508: if (ExceptionDebugMask & EXCEPT_DSP)
1.1.1.9 root 1509: DebugUI(REASON_DSP_EXCEPTION);
1.1 root 1510: }
1511:
1.1.1.6 root 1512: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1.1.1.4 root 1513: stack &= BITMASK(4);
1.1.1.6 root 1514: *newpc = dsp_core.registers[DSP_REG_SSH];
1515: *newsr = dsp_core.registers[DSP_REG_SSL];
1.1.1.4 root 1516:
1.1.1.6 root 1517: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1518: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1.1.4 root 1519: }
1520:
1521: static void dsp_compute_ssh_ssl(void)
1522: {
1523: Uint32 stack;
1.1 root 1524:
1.1.1.6 root 1525: stack = dsp_core.registers[DSP_REG_SP];
1.1.1.4 root 1526: stack &= BITMASK(4);
1.1.1.6 root 1527: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1528: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1 root 1529: }
1530:
1531: /**********************************
1532: * Effective address calculation
1533: **********************************/
1534:
1.1.1.2 root 1535: static void dsp_update_rn(Uint32 numreg, Sint16 modifier)
1.1 root 1536: {
1.1.1.2 root 1537: Sint16 value;
1538: Uint16 m_reg;
1.1 root 1539:
1.1.1.6 root 1540: m_reg = (Uint16) dsp_core.registers[DSP_REG_M0+numreg];
1.1.1.7 root 1541: if (m_reg == 65535) {
1542: /* Linear addressing mode */
1543: value = (Sint16) dsp_core.registers[DSP_REG_R0+numreg];
1544: value += modifier;
1545: dsp_core.registers[DSP_REG_R0+numreg] = ((Uint32) value) & BITMASK(16);
1546: } else if (m_reg == 0) {
1.1 root 1547: /* Bit reversed carry update */
1548: dsp_update_rn_bitreverse(numreg);
1.1.1.4 root 1549: } else if (m_reg<=32767) {
1.1 root 1550: /* Modulo update */
1551: dsp_update_rn_modulo(numreg, modifier);
1552: } else {
1553: /* Undefined */
1554: }
1555: }
1556:
1.1.1.2 root 1557: static void dsp_update_rn_bitreverse(Uint32 numreg)
1.1 root 1558: {
1559: int revbits, i;
1.1.1.2 root 1560: Uint32 value, r_reg;
1.1 root 1561:
1562: /* Check how many bits to reverse */
1.1.1.6 root 1563: value = dsp_core.registers[DSP_REG_N0+numreg];
1.1 root 1564: for (revbits=0;revbits<16;revbits++) {
1565: if (value & (1<<revbits)) {
1566: break;
1567: }
1568: }
1569: revbits++;
1570:
1571: /* Reverse Rn bits */
1.1.1.6 root 1572: r_reg = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1573: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1574: for (i=0;i<revbits;i++) {
1575: if (r_reg & (1<<i)) {
1576: value |= 1<<(revbits-i-1);
1577: }
1578: }
1579:
1580: /* Increment */
1581: value++;
1582: value &= BITMASK(revbits);
1583:
1584: /* Reverse Rn bits */
1585: r_reg &= (BITMASK(16)-BITMASK(revbits));
1586: r_reg |= value;
1587:
1588: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1589: for (i=0;i<revbits;i++) {
1590: if (r_reg & (1<<i)) {
1591: value |= 1<<(revbits-i-1);
1592: }
1593: }
1594:
1.1.1.6 root 1595: dsp_core.registers[DSP_REG_R0+numreg] = value;
1.1 root 1596: }
1597:
1.1.1.2 root 1598: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier)
1.1 root 1599: {
1.1.1.2 root 1600: Uint16 bufsize, modulo, lobound, hibound, bufmask;
1.1.1.4 root 1601: Sint16 r_reg, orig_modifier=modifier;
1.1 root 1602:
1.1.1.6 root 1603: modulo = dsp_core.registers[DSP_REG_M0+numreg]+1;
1.1 root 1604: bufsize = 1;
1.1.1.2 root 1605: bufmask = BITMASK(16);
1.1 root 1606: while (bufsize < modulo) {
1607: bufsize <<= 1;
1.1.1.2 root 1608: bufmask <<= 1;
1.1 root 1609: }
1610:
1.1.1.6 root 1611: lobound = dsp_core.registers[DSP_REG_R0+numreg] & bufmask;
1.1.1.2 root 1612: hibound = lobound + modulo - 1;
1.1 root 1613:
1.1.1.6 root 1614: r_reg = (Sint16) dsp_core.registers[DSP_REG_R0+numreg];
1.1.1.4 root 1615:
1616: if (orig_modifier>modulo) {
1617: while (modifier>bufsize) {
1618: r_reg += bufsize;
1619: modifier -= bufsize;
1620: }
1621: while (modifier<-bufsize) {
1622: r_reg -= bufsize;
1623: modifier += bufsize;
1624: }
1.1.1.2 root 1625: }
1.1.1.4 root 1626:
1.1 root 1627: r_reg += modifier;
1.1.1.4 root 1628:
1629: if (orig_modifier!=modulo) {
1630: if (r_reg>hibound) {
1631: r_reg -= modulo;
1632: } else if (r_reg<lobound) {
1633: r_reg += modulo;
1634: }
1.1 root 1635: }
1636:
1.1.1.6 root 1637: dsp_core.registers[DSP_REG_R0+numreg] = ((Uint32) r_reg) & BITMASK(16);
1.1 root 1638: }
1639:
1.1.1.2 root 1640: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr)
1.1 root 1641: {
1.1.1.2 root 1642: Uint32 value, numreg, curreg;
1.1 root 1643:
1644: value = (ea_mode >> 3) & BITMASK(3);
1645: numreg = ea_mode & BITMASK(3);
1646: switch (value) {
1647: case 0:
1648: /* (Rx)-Nx */
1.1.1.6 root 1649: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1650: dsp_update_rn(numreg, -dsp_core.registers[DSP_REG_N0+numreg]);
1.1 root 1651: break;
1652: case 1:
1653: /* (Rx)+Nx */
1.1.1.6 root 1654: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1655: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1.1 root 1656: break;
1657: case 2:
1658: /* (Rx)- */
1.1.1.6 root 1659: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1660: dsp_update_rn(numreg, -1);
1661: break;
1662: case 3:
1663: /* (Rx)+ */
1.1.1.6 root 1664: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1665: dsp_update_rn(numreg, +1);
1666: break;
1667: case 4:
1668: /* (Rx) */
1.1.1.6 root 1669: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1670: break;
1671: case 5:
1672: /* (Rx+Nx) */
1.1.1.6 root 1673: dsp_core.instr_cycle += 2;
1674: curreg = dsp_core.registers[DSP_REG_R0+numreg];
1675: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1676: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1677: dsp_core.registers[DSP_REG_R0+numreg] = curreg;
1.1 root 1678: break;
1679: case 6:
1680: /* aa */
1.1.1.6 root 1681: dsp_core.instr_cycle += 2;
1682: *dst_addr = read_memory_p(dsp_core.pc+1);
1.1 root 1683: cur_inst_len++;
1684: if (numreg != 0) {
1685: return 1; /* immediate value */
1686: }
1687: break;
1688: case 7:
1689: /* -(Rx) */
1.1.1.6 root 1690: dsp_core.instr_cycle += 2;
1.1 root 1691: dsp_update_rn(numreg, -1);
1.1.1.6 root 1692: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1693: break;
1694: }
1695: /* address */
1696: return 0;
1697: }
1698:
1699: /**********************************
1700: * Condition code test
1701: **********************************/
1702:
1.1.1.2 root 1703: static int dsp_calc_cc(Uint32 cc_code)
1.1 root 1704: {
1.1.1.4 root 1705: Uint16 value1, value2, value3;
1.1 root 1706:
1.1.1.4 root 1707: switch (cc_code) {
1708: case 0: /* CC (HS) */
1.1.1.6 root 1709: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1.1.1.4 root 1710: return (value1==0);
1711: case 1: /* GE */
1.1.1.6 root 1712: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1713: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1.1.1.4 root 1714: return ((value1 ^ value2) == 0);
1715: case 2: /* NE */
1.1.1.6 root 1716: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_Z);
1.1.1.4 root 1717: return (value1==0);
1718: case 3: /* PL */
1.1.1.6 root 1719: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_N);
1.1.1.4 root 1720: return (value1==0);
1721: case 4: /* NN */
1.1.1.6 root 1722: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1723: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1724: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1.1.1.4 root 1725: return ((value1 | (value2 & value3)) == 0);
1726: case 5: /* EC */
1.1.1.6 root 1727: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_E);
1.1.1.4 root 1728: return (value1==0);
1729: case 6: /* LC */
1.1.1.6 root 1730: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_L);
1.1.1.4 root 1731: return (value1==0);
1732: case 7: /* GT */
1.1.1.6 root 1733: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1734: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1735: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1736: return ((value3 | (value1 ^ value2)) == 0);
1737: case 8: /* CS (LO) */
1.1.1.6 root 1738: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1.1.1.4 root 1739: return (value1==1);
1740: case 9: /* LT */
1.1.1.6 root 1741: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1742: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1.1.1.4 root 1743: return ((value1 ^ value2) == 1);
1744: case 10: /* EQ */
1.1.1.6 root 1745: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1746: return (value1==1);
1747: case 11: /* MI */
1.1.1.6 root 1748: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1.1.1.4 root 1749: return (value1==1);
1750: case 12: /* NR */
1.1.1.6 root 1751: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1752: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1753: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1.1.1.4 root 1754: return ((value1 | (value2 & value3)) == 1);
1755: case 13: /* ES */
1.1.1.6 root 1756: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_E) & 1;
1.1.1.4 root 1757: return (value1==1);
1758: case 14: /* LS */
1.1.1.6 root 1759: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_L) & 1;
1.1.1.4 root 1760: return (value1==1);
1761: case 15: /* LE */
1.1.1.6 root 1762: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1763: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1764: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1765: return ((value3 | (value1 ^ value2)) == 1);
1766: }
1767: return 0;
1.1 root 1768: }
1769:
1770: /**********************************
1771: * Highbyte opcodes dispatchers
1772: **********************************/
1773:
1774: static void opcode8h_0(void)
1775: {
1.1.1.4 root 1776: switch(cur_inst) {
1777: case 0x000000:
1778: dsp_nop();
1.1 root 1779: break;
1.1.1.4 root 1780: case 0x000004:
1781: dsp_rti();
1.1 root 1782: break;
1.1.1.4 root 1783: case 0x000005:
1784: dsp_illegal();
1.1 root 1785: break;
1.1.1.4 root 1786: case 0x000006:
1787: dsp_swi();
1788: break;
1789: case 0x00000c:
1790: dsp_rts();
1791: break;
1792: case 0x000084:
1793: dsp_reset();
1794: break;
1795: case 0x000086:
1796: dsp_wait();
1797: break;
1798: case 0x000087:
1799: dsp_stop();
1800: break;
1801: case 0x00008c:
1802: dsp_enddo();
1.1 root 1803: break;
1.1.1.10! root 1804: default:
! 1805: dsp_undefined();
! 1806: break;
1.1 root 1807: }
1808: }
1809:
1810: /**********************************
1811: * Non-parallel moves instructions
1812: **********************************/
1813:
1814: static void dsp_undefined(void)
1815: {
1.1.1.6 root 1816: if (isDsp_in_disasm_mode == false) {
1817: cur_inst_len = 0;
1818: fprintf(stderr, "Dsp: 0x%04x: 0x%06x Illegal instruction\n",dsp_core.pc, cur_inst);
1.1.1.7 root 1819: /* Add some artificial CPU cycles to avoid being stuck in an infinite loop */
1.1.1.6 root 1820: dsp_core.instr_cycle += 100;
1821: }
1822: else {
1823: cur_inst_len = 1;
1824: dsp_core.instr_cycle = 0;
1825: }
1.1.1.10! root 1826: if (ExceptionDebugMask & EXCEPT_DSP) {
1.1.1.9 root 1827: DebugUI(REASON_DSP_EXCEPTION);
1828: }
1.1 root 1829: }
1830:
1831: static void dsp_andi(void)
1832: {
1.1.1.2 root 1833: Uint32 regnum, value;
1.1 root 1834:
1835: value = (cur_inst >> 8) & BITMASK(8);
1836: regnum = cur_inst & BITMASK(2);
1837: switch(regnum) {
1838: case 0:
1839: /* mr */
1.1.1.6 root 1840: dsp_core.registers[DSP_REG_SR] &= (value<<8)|BITMASK(8);
1.1 root 1841: break;
1842: case 1:
1843: /* ccr */
1.1.1.6 root 1844: dsp_core.registers[DSP_REG_SR] &= (BITMASK(8)<<8)|value;
1.1 root 1845: break;
1846: case 2:
1847: /* omr */
1.1.1.6 root 1848: dsp_core.registers[DSP_REG_OMR] &= value;
1.1 root 1849: break;
1850: }
1851: }
1852:
1.1.1.4 root 1853: static void dsp_bchg_aa(void)
1.1 root 1854: {
1.1.1.4 root 1855: Uint32 memspace, addr, value, newcarry, numbit;
1.1 root 1856:
1857: memspace = (cur_inst>>6) & 1;
1858: value = (cur_inst>>8) & BITMASK(6);
1859: numbit = cur_inst & BITMASK(5);
1860:
1.1.1.4 root 1861: addr = value;
1862: value = read_memory(memspace, addr);
1863: newcarry = (value>>numbit) & 1;
1864: if (newcarry) {
1865: value -= (1<<numbit);
1866: } else {
1867: value += (1<<numbit);
1.1 root 1868: }
1.1.1.4 root 1869: write_memory(memspace, addr, value);
1.1 root 1870:
1871: /* Set carry */
1.1.1.6 root 1872: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1873: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1874:
1.1.1.6 root 1875: dsp_core.instr_cycle += 2;
1.1 root 1876: }
1877:
1.1.1.4 root 1878: static void dsp_bchg_ea(void)
1.1 root 1879: {
1.1.1.4 root 1880: Uint32 memspace, addr, value, newcarry, numbit;
1.1 root 1881:
1882: memspace = (cur_inst>>6) & 1;
1883: value = (cur_inst>>8) & BITMASK(6);
1884: numbit = cur_inst & BITMASK(5);
1885:
1.1.1.4 root 1886: dsp_calc_ea(value, &addr);
1887: value = read_memory(memspace, addr);
1888: newcarry = (value>>numbit) & 1;
1889: if (newcarry) {
1890: value -= (1<<numbit);
1891: } else {
1892: value += (1<<numbit);
1.1 root 1893: }
1.1.1.4 root 1894: write_memory(memspace, addr, value);
1.1 root 1895:
1896: /* Set carry */
1.1.1.6 root 1897: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1898: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1899:
1.1.1.6 root 1900: dsp_core.instr_cycle += 2;
1.1 root 1901: }
1902:
1.1.1.4 root 1903: static void dsp_bchg_pp(void)
1.1 root 1904: {
1.1.1.4 root 1905: Uint32 memspace, addr, value, newcarry, numbit;
1.1 root 1906:
1907: memspace = (cur_inst>>6) & 1;
1908: value = (cur_inst>>8) & BITMASK(6);
1909: numbit = cur_inst & BITMASK(5);
1910:
1.1.1.4 root 1911: addr = 0xffc0 + value;
1912: value = read_memory(memspace, addr);
1913: newcarry = (value>>numbit) & 1;
1914: if (newcarry) {
1915: value -= (1<<numbit);
1916: } else {
1917: value += (1<<numbit);
1.1 root 1918: }
1.1.1.4 root 1919: write_memory(memspace, addr, value);
1.1 root 1920:
1921: /* Set carry */
1.1.1.6 root 1922: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1923: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1924:
1.1.1.6 root 1925: dsp_core.instr_cycle += 2;
1.1 root 1926: }
1927:
1.1.1.4 root 1928: static void dsp_bchg_reg(void)
1.1 root 1929: {
1.1.1.4 root 1930: Uint32 value, numreg, newcarry, numbit;
1.1 root 1931:
1.1.1.4 root 1932: numreg = (cur_inst>>8) & BITMASK(6);
1.1 root 1933: numbit = cur_inst & BITMASK(5);
1934:
1.1.1.4 root 1935: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
1936: dsp_pm_read_accu24(numreg, &value);
1937: } else {
1.1.1.6 root 1938: value = dsp_core.registers[numreg];
1.1 root 1939: }
1940:
1.1.1.4 root 1941: newcarry = (value>>numbit) & 1;
1942: if (newcarry) {
1943: value -= (1<<numbit);
1944: } else {
1945: value += (1<<numbit);
1946: }
1947:
1948: dsp_write_reg(numreg, value);
1949:
1.1 root 1950: /* Set carry */
1.1.1.6 root 1951: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1952: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1953:
1.1.1.6 root 1954: dsp_core.instr_cycle += 2;
1.1 root 1955: }
1956:
1.1.1.4 root 1957: static void dsp_bclr_aa(void)
1.1 root 1958: {
1.1.1.4 root 1959: Uint32 memspace, addr, value, newcarry, numbit;
1960:
1961: memspace = (cur_inst>>6) & 1;
1962: addr = (cur_inst>>8) & BITMASK(6);
1963: numbit = cur_inst & BITMASK(5);
1.1 root 1964:
1.1.1.4 root 1965: value = read_memory(memspace, addr);
1966: newcarry = (value>>numbit) & 1;
1967: value &= 0xffffffff-(1<<numbit);
1968: write_memory(memspace, addr, value);
1.1.1.2 root 1969:
1.1.1.4 root 1970: /* Set carry */
1.1.1.6 root 1971: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1972: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 1973:
1.1.1.6 root 1974: dsp_core.instr_cycle += 2;
1.1.1.4 root 1975: }
1.1 root 1976:
1.1.1.4 root 1977: static void dsp_bclr_ea(void)
1978: {
1979: Uint32 memspace, addr, value, newcarry, numbit;
1980:
1981: memspace = (cur_inst>>6) & 1;
1982: value = (cur_inst>>8) & BITMASK(6);
1983: numbit = cur_inst & BITMASK(5);
1.1 root 1984:
1.1.1.4 root 1985: dsp_calc_ea(value, &addr);
1986: value = read_memory(memspace, addr);
1987: newcarry = (value>>numbit) & 1;
1988: value &= 0xffffffff-(1<<numbit);
1989: write_memory(memspace, addr, value);
1.1.1.2 root 1990:
1.1.1.4 root 1991: /* Set carry */
1.1.1.6 root 1992: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1993: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1994:
1.1.1.6 root 1995: dsp_core.instr_cycle += 2;
1.1 root 1996: }
1997:
1.1.1.4 root 1998: static void dsp_bclr_pp(void)
1999: {
2000: Uint32 memspace, addr, value, newcarry, numbit;
2001:
2002: memspace = (cur_inst>>6) & 1;
2003: value = (cur_inst>>8) & BITMASK(6);
2004: numbit = cur_inst & BITMASK(5);
1.1.1.3 root 2005:
1.1.1.4 root 2006: addr = 0xffc0 + value;
2007: value = read_memory(memspace, addr);
2008: newcarry = (value>>numbit) & 1;
2009: value &= 0xffffffff-(1<<numbit);
2010: write_memory(memspace, addr, value);
1.1.1.3 root 2011:
1.1.1.4 root 2012: /* Set carry */
1.1.1.6 root 2013: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2014: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 2015:
1.1.1.6 root 2016: dsp_core.instr_cycle += 2;
1.1.1.4 root 2017: }
1.1 root 2018:
1.1.1.4 root 2019: static void dsp_bclr_reg(void)
2020: {
2021: Uint32 value, numreg, newcarry, numbit;
2022:
2023: numreg = (cur_inst>>8) & BITMASK(6);
2024: numbit = cur_inst & BITMASK(5);
1.1 root 2025:
1.1.1.4 root 2026: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2027: dsp_pm_read_accu24(numreg, &value);
2028: } else {
1.1.1.6 root 2029: value = dsp_core.registers[numreg];
1.1.1.4 root 2030: }
1.1 root 2031:
1.1.1.4 root 2032: newcarry = (value>>numbit) & 1;
2033: value &= 0xffffffff-(1<<numbit);
1.1 root 2034:
1.1.1.4 root 2035: dsp_write_reg(numreg, value);
2036:
2037: /* Set carry */
1.1.1.6 root 2038: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2039: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 2040:
1.1.1.6 root 2041: dsp_core.instr_cycle += 2;
1.1 root 2042: }
2043:
1.1.1.4 root 2044: static void dsp_bset_aa(void)
1.1 root 2045: {
1.1.1.4 root 2046: Uint32 memspace, addr, value, newcarry, numbit;
2047:
2048: memspace = (cur_inst>>6) & 1;
2049: value = (cur_inst>>8) & BITMASK(6);
2050: numbit = cur_inst & BITMASK(5);
1.1 root 2051:
1.1.1.4 root 2052: addr = value;
2053: value = read_memory(memspace, addr);
2054: newcarry = (value>>numbit) & 1;
2055: value |= (1<<numbit);
2056: write_memory(memspace, addr, value);
2057:
2058: /* Set carry */
1.1.1.6 root 2059: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2060: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2061:
1.1.1.6 root 2062: dsp_core.instr_cycle += 2;
1.1.1.4 root 2063: }
2064:
2065: static void dsp_bset_ea(void)
2066: {
2067: Uint32 memspace, addr, value, newcarry, numbit;
2068:
2069: memspace = (cur_inst>>6) & 1;
2070: value = (cur_inst>>8) & BITMASK(6);
2071: numbit = cur_inst & BITMASK(5);
2072:
2073: dsp_calc_ea(value, &addr);
2074: value = read_memory(memspace, addr);
2075: newcarry = (value>>numbit) & 1;
2076: value |= (1<<numbit);
2077: write_memory(memspace, addr, value);
2078:
2079: /* Set carry */
1.1.1.6 root 2080: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2081: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2082:
1.1.1.6 root 2083: dsp_core.instr_cycle += 2;
1.1.1.4 root 2084: }
2085:
2086: static void dsp_bset_pp(void)
2087: {
2088: Uint32 memspace, addr, value, newcarry, numbit;
2089:
2090: memspace = (cur_inst>>6) & 1;
2091: value = (cur_inst>>8) & BITMASK(6);
2092: numbit = cur_inst & BITMASK(5);
2093: addr = 0xffc0 + value;
2094: value = read_memory(memspace, addr);
2095: newcarry = (value>>numbit) & 1;
2096: value |= (1<<numbit);
2097: write_memory(memspace, addr, value);
2098:
2099: /* Set carry */
1.1.1.6 root 2100: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2101: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2102:
1.1.1.6 root 2103: dsp_core.instr_cycle += 2;
1.1.1.4 root 2104: }
2105:
2106: static void dsp_bset_reg(void)
2107: {
2108: Uint32 value, numreg, newcarry, numbit;
2109:
2110: numreg = (cur_inst>>8) & BITMASK(6);
2111: numbit = cur_inst & BITMASK(5);
2112:
2113: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2114: dsp_pm_read_accu24(numreg, &value);
2115: } else {
1.1.1.6 root 2116: value = dsp_core.registers[numreg];
1.1.1.4 root 2117: }
2118:
2119: newcarry = (value>>numbit) & 1;
2120: value |= (1<<numbit);
2121:
2122: dsp_write_reg(numreg, value);
2123:
2124: /* Set carry */
1.1.1.6 root 2125: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2126: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2127:
1.1.1.6 root 2128: dsp_core.instr_cycle += 2;
1.1.1.4 root 2129: }
2130:
2131: static void dsp_btst_aa(void)
2132: {
2133: Uint32 memspace, addr, value, newcarry, numbit;
2134:
2135: memspace = (cur_inst>>6) & 1;
2136: value = (cur_inst>>8) & BITMASK(6);
2137: numbit = cur_inst & BITMASK(5);
2138:
2139: addr = value;
2140: value = read_memory(memspace, addr);
2141: newcarry = (value>>numbit) & 1;
2142:
2143: /* Set carry */
1.1.1.6 root 2144: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2145: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2146:
1.1.1.6 root 2147: dsp_core.instr_cycle += 2;
1.1.1.4 root 2148: }
2149:
2150: static void dsp_btst_ea(void)
2151: {
2152: Uint32 memspace, addr, value, newcarry, numbit;
2153:
2154: memspace = (cur_inst>>6) & 1;
2155: value = (cur_inst>>8) & BITMASK(6);
2156: numbit = cur_inst & BITMASK(5);
2157:
2158: dsp_calc_ea(value, &addr);
2159: value = read_memory(memspace, addr);
2160: newcarry = (value>>numbit) & 1;
2161:
2162: /* Set carry */
1.1.1.6 root 2163: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2164: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2165:
1.1.1.6 root 2166: dsp_core.instr_cycle += 2;
1.1.1.4 root 2167: }
2168:
2169: static void dsp_btst_pp(void)
2170: {
2171: Uint32 memspace, addr, value, newcarry, numbit;
2172:
2173: memspace = (cur_inst>>6) & 1;
2174: value = (cur_inst>>8) & BITMASK(6);
2175: numbit = cur_inst & BITMASK(5);
2176:
2177: addr = 0xffc0 + value;
2178: value = read_memory(memspace, addr);
2179: newcarry = (value>>numbit) & 1;
2180:
2181: /* Set carry */
1.1.1.6 root 2182: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2183: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2184:
1.1.1.6 root 2185: dsp_core.instr_cycle += 2;
1.1.1.4 root 2186: }
2187:
2188: static void dsp_btst_reg(void)
2189: {
2190: Uint32 value, numreg, newcarry, numbit;
2191:
2192: numreg = (cur_inst>>8) & BITMASK(6);
2193: numbit = cur_inst & BITMASK(5);
2194:
2195: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2196: dsp_pm_read_accu24(numreg, &value);
2197: } else {
1.1.1.6 root 2198: value = dsp_core.registers[numreg];
1.1.1.4 root 2199: }
2200:
2201: newcarry = (value>>numbit) & 1;
2202:
2203: /* Set carry */
1.1.1.6 root 2204: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2205: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2206:
1.1.1.6 root 2207: dsp_core.instr_cycle += 2;
1.1.1.4 root 2208: }
2209:
2210: static void dsp_div(void)
2211: {
2212: Uint32 srcreg, destreg, source[3], dest[3];
2213: Uint16 newsr;
2214:
2215: srcreg = DSP_REG_NULL;
2216: switch((cur_inst>>4) & BITMASK(2)) {
2217: case 0: srcreg = DSP_REG_X0; break;
2218: case 1: srcreg = DSP_REG_Y0; break;
2219: case 2: srcreg = DSP_REG_X1; break;
2220: case 3: srcreg = DSP_REG_Y1; break;
2221: }
1.1.1.7 root 2222: source[2] = 0;
2223: source[1] = dsp_core.registers[srcreg];
2224: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.4 root 2225:
1.1.1.7 root 2226: destreg = DSP_REG_A + ((cur_inst>>3) & 1);
2227: if (destreg == DSP_REG_A) {
2228: dest[0] = dsp_core.registers[DSP_REG_A2];
2229: dest[1] = dsp_core.registers[DSP_REG_A1];
2230: dest[2] = dsp_core.registers[DSP_REG_A0];
2231: }
2232: else {
2233: dest[0] = dsp_core.registers[DSP_REG_B2];
2234: dest[1] = dsp_core.registers[DSP_REG_B1];
2235: dest[2] = dsp_core.registers[DSP_REG_B0];
2236: }
1.1.1.4 root 2237:
2238: if (((dest[0]>>7) & 1) ^ ((source[1]>>23) & 1)) {
2239: /* D += S */
2240: newsr = dsp_asl56(dest);
2241: dsp_add56(source, dest);
2242: } else {
2243: /* D -= S */
2244: newsr = dsp_asl56(dest);
2245: dsp_sub56(source, dest);
2246: }
2247:
1.1.1.6 root 2248: dest[2] |= (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1.1.4 root 2249:
1.1.1.7 root 2250: if (destreg == DSP_REG_A) {
2251: dsp_core.registers[DSP_REG_A2] = dest[0];
2252: dsp_core.registers[DSP_REG_A1] = dest[1];
2253: dsp_core.registers[DSP_REG_A0] = dest[2];
2254: }
2255: else {
2256: dsp_core.registers[DSP_REG_B2] = dest[0];
2257: dsp_core.registers[DSP_REG_B1] = dest[1];
2258: dsp_core.registers[DSP_REG_B0] = dest[2];
2259: }
2260:
1.1.1.6 root 2261: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
2262: dsp_core.registers[DSP_REG_SR] |= (1-((dest[0]>>7) & 1))<<DSP_SR_C;
2263: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_L);
2264: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_V);
1.1.1.4 root 2265: }
2266:
2267: /*
2268: DO instruction parameter encoding
2269:
2270: xxxxxxxx 00xxxxxx 0xxxxxxx aa
2271: xxxxxxxx 01xxxxxx 0xxxxxxx ea
2272: xxxxxxxx YYxxxxxx 1xxxxxxx imm
2273: xxxxxxxx 11xxxxxx 0xxxxxxx reg
2274: */
2275:
2276: static void dsp_do_aa(void)
2277: {
2278: Uint32 memspace, addr;
2279:
2280: /* x:aa */
2281: /* y:aa */
2282:
1.1.1.6 root 2283: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2284: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2285: cur_inst_len++;
1.1.1.6 root 2286: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2287: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1 root 2288:
2289: memspace = (cur_inst>>6) & 1;
2290: addr = (cur_inst>>8) & BITMASK(6);
1.1.1.6 root 2291: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
1.1.1.4 root 2292:
1.1.1.6 root 2293: dsp_core.instr_cycle += 4;
1.1 root 2294: }
2295:
1.1.1.3 root 2296: static void dsp_do_imm(void)
1.1 root 2297: {
2298: /* #xx */
1.1.1.3 root 2299:
1.1.1.6 root 2300: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2301: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2302: cur_inst_len++;
1.1.1.6 root 2303: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2304: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2305:
1.1.1.6 root 2306: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
1.1.1.3 root 2307: + ((cur_inst & BITMASK(4))<<8);
1.1.1.4 root 2308:
1.1.1.6 root 2309: dsp_core.instr_cycle += 4;
1.1 root 2310: }
2311:
1.1.1.3 root 2312: static void dsp_do_ea(void)
1.1 root 2313: {
1.1.1.2 root 2314: Uint32 memspace, ea_mode, addr;
1.1 root 2315:
2316: /* x:ea */
2317: /* y:ea */
2318:
1.1.1.6 root 2319: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2320: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2321: cur_inst_len++;
1.1.1.6 root 2322: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2323: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2324:
1.1 root 2325: memspace = (cur_inst>>6) & 1;
2326: ea_mode = (cur_inst>>8) & BITMASK(6);
2327: dsp_calc_ea(ea_mode, &addr);
1.1.1.6 root 2328: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
1.1.1.4 root 2329:
1.1.1.6 root 2330: dsp_core.instr_cycle += 4;
1.1 root 2331: }
2332:
1.1.1.3 root 2333: static void dsp_do_reg(void)
1.1 root 2334: {
1.1.1.2 root 2335: Uint32 numreg;
1.1 root 2336:
2337: /* S */
2338:
1.1.1.6 root 2339: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2340: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2341: cur_inst_len++;
2342:
1.1 root 2343: numreg = (cur_inst>>8) & BITMASK(6);
2344: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.6 root 2345: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
1.1 root 2346: } else {
1.1.1.6 root 2347: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
1.1 root 2348: }
1.1.1.6 root 2349: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.4 root 2350:
1.1.1.6 root 2351: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2352: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2353:
1.1.1.6 root 2354: dsp_core.instr_cycle += 4;
1.1 root 2355: }
2356:
2357: static void dsp_enddo(void)
2358: {
1.1.1.4 root 2359: Uint32 saved_pc, saved_sr;
1.1 root 2360:
1.1.1.4 root 2361: dsp_stack_pop(&saved_pc, &saved_sr);
1.1.1.6 root 2362: dsp_core.registers[DSP_REG_SR] &= 0x7f;
2363: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
2364: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
1.1 root 2365: }
2366:
2367: static void dsp_illegal(void)
2368: {
2369: /* Raise interrupt p:0x003e */
1.1.1.5 root 2370: dsp_add_interrupt(DSP_INTER_ILLEGAL);
1.1.1.10! root 2371: if (ExceptionDebugMask & EXCEPT_DSP) {
1.1.1.9 root 2372: DebugUI(REASON_DSP_EXCEPTION);
2373: }
1.1 root 2374: }
2375:
1.1.1.4 root 2376: static void dsp_jcc_imm(void)
1.1 root 2377: {
1.1.1.4 root 2378: Uint32 cc_code, newpc;
1.1 root 2379:
1.1.1.4 root 2380: newpc = cur_inst & BITMASK(12);
2381: cc_code=(cur_inst>>12) & BITMASK(4);
2382: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2383: dsp_core.pc = newpc;
1.1.1.4 root 2384: cur_inst_len = 0;
2385: }
2386:
1.1.1.6 root 2387: dsp_core.instr_cycle += 2;
1.1.1.4 root 2388: }
2389:
2390: static void dsp_jcc_ea(void)
2391: {
2392: Uint32 newpc, cc_code;
2393:
2394: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2395: cc_code=cur_inst & BITMASK(4);
1.1 root 2396:
2397: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2398: dsp_core.pc = newpc;
1.1 root 2399: cur_inst_len = 0;
2400: }
1.1.1.4 root 2401:
1.1.1.6 root 2402: dsp_core.instr_cycle += 2;
1.1 root 2403: }
2404:
1.1.1.4 root 2405: static void dsp_jclr_aa(void)
1.1 root 2406: {
1.1.1.4 root 2407: Uint32 memspace, addr, value, numbit, newaddr;
1.1 root 2408:
2409: memspace = (cur_inst>>6) & 1;
1.1.1.4 root 2410: addr = (cur_inst>>8) & BITMASK(6);
1.1 root 2411: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2412: value = read_memory(memspace, addr);
1.1.1.6 root 2413: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2414:
1.1.1.6 root 2415: dsp_core.instr_cycle += 4;
1.1 root 2416:
1.1.1.4 root 2417: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2418: dsp_core.pc = newaddr;
1.1.1.4 root 2419: cur_inst_len = 0;
2420: return;
2421: }
1.1.1.2 root 2422: ++cur_inst_len;
1.1.1.4 root 2423: }
2424:
2425: static void dsp_jclr_ea(void)
2426: {
2427: Uint32 memspace, addr, value, numbit, newaddr;
2428:
2429: memspace = (cur_inst>>6) & 1;
2430: value = (cur_inst>>8) & BITMASK(6);
2431: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2432: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2433:
2434: dsp_calc_ea(value, &addr);
2435: value = read_memory(memspace, addr);
2436:
1.1.1.6 root 2437: dsp_core.instr_cycle += 4;
1.1 root 2438:
2439: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2440: dsp_core.pc = newaddr;
1.1.1.4 root 2441: cur_inst_len = 0;
2442: return;
2443: }
2444: ++cur_inst_len;
2445: }
1.1 root 2446:
1.1.1.4 root 2447: static void dsp_jclr_pp(void)
2448: {
2449: Uint32 memspace, addr, value, numbit, newaddr;
2450:
2451: memspace = (cur_inst>>6) & 1;
2452: value = (cur_inst>>8) & BITMASK(6);
2453: numbit = cur_inst & BITMASK(5);
2454: addr = 0xffc0 + value;
2455: value = read_memory(memspace, addr);
1.1.1.6 root 2456: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2457:
1.1.1.6 root 2458: dsp_core.instr_cycle += 4;
1.1 root 2459:
1.1.1.4 root 2460: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2461: dsp_core.pc = newaddr;
1.1.1.4 root 2462: cur_inst_len = 0;
2463: return;
2464: }
2465: ++cur_inst_len;
2466: }
1.1.1.2 root 2467:
1.1.1.4 root 2468: static void dsp_jclr_reg(void)
2469: {
2470: Uint32 value, numreg, numbit, newaddr;
2471:
2472: numreg = (cur_inst>>8) & BITMASK(6);
2473: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2474: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2475:
1.1.1.4 root 2476: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2477: dsp_pm_read_accu24(numreg, &value);
2478: } else {
1.1.1.6 root 2479: value = dsp_core.registers[numreg];
1.1.1.4 root 2480: }
1.1 root 2481:
1.1.1.6 root 2482: dsp_core.instr_cycle += 4;
1.1.1.4 root 2483:
2484: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2485: dsp_core.pc = newaddr;
1.1 root 2486: cur_inst_len = 0;
2487: return;
2488: }
1.1.1.4 root 2489: ++cur_inst_len;
1.1 root 2490: }
2491:
1.1.1.4 root 2492: static void dsp_jmp_ea(void)
1.1 root 2493: {
1.1.1.2 root 2494: Uint32 newpc;
1.1 root 2495:
1.1.1.4 root 2496: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &newpc);
1.1 root 2497: cur_inst_len = 0;
1.1.1.6 root 2498: dsp_core.pc = newpc;
1.1 root 2499:
1.1.1.6 root 2500: dsp_core.instr_cycle += 2;
1.1.1.4 root 2501: }
2502:
2503: static void dsp_jmp_imm(void)
2504: {
2505: Uint32 newpc;
1.1 root 2506:
1.1.1.4 root 2507: newpc = cur_inst & BITMASK(12);
2508: cur_inst_len = 0;
1.1.1.6 root 2509: dsp_core.pc = newpc;
1.1.1.4 root 2510:
1.1.1.6 root 2511: dsp_core.instr_cycle += 2;
1.1 root 2512: }
2513:
1.1.1.4 root 2514: static void dsp_jscc_ea(void)
1.1 root 2515: {
1.1.1.2 root 2516: Uint32 newpc, cc_code;
1.1 root 2517:
1.1.1.4 root 2518: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2519: cc_code=cur_inst & BITMASK(4);
2520:
2521: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2522: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2523: dsp_core.pc = newpc;
1.1.1.4 root 2524: cur_inst_len = 0;
2525: }
2526:
1.1.1.6 root 2527: dsp_core.instr_cycle += 2;
1.1.1.4 root 2528: }
1.1 root 2529:
1.1.1.4 root 2530: static void dsp_jscc_imm(void)
2531: {
2532: Uint32 cc_code, newpc;
2533:
2534: newpc = cur_inst & BITMASK(12);
2535: cc_code=(cur_inst>>12) & BITMASK(4);
1.1 root 2536: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2537: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2538: dsp_core.pc = newpc;
1.1.1.4 root 2539: cur_inst_len = 0;
2540: }
2541:
1.1.1.6 root 2542: dsp_core.instr_cycle += 2;
1.1.1.4 root 2543: }
1.1 root 2544:
1.1.1.4 root 2545: static void dsp_jsclr_aa(void)
2546: {
2547: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2548:
2549: memspace = (cur_inst>>6) & 1;
2550: addr = (cur_inst>>8) & BITMASK(6);
2551: numbit = cur_inst & BITMASK(5);
2552: value = read_memory(memspace, addr);
1.1.1.6 root 2553: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2554:
1.1.1.6 root 2555: dsp_core.instr_cycle += 4;
1.1.1.4 root 2556:
2557: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2558: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2559: newpc = newaddr;
1.1.1.6 root 2560: dsp_core.pc = newpc;
1.1 root 2561: cur_inst_len = 0;
1.1.1.4 root 2562: return;
1.1 root 2563: }
1.1.1.4 root 2564: ++cur_inst_len;
1.1 root 2565: }
2566:
1.1.1.4 root 2567: static void dsp_jsclr_ea(void)
1.1 root 2568: {
1.1.1.4 root 2569: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1 root 2570:
2571: memspace = (cur_inst>>6) & 1;
2572: value = (cur_inst>>8) & BITMASK(6);
2573: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2574: dsp_calc_ea(value, &addr);
2575: value = read_memory(memspace, addr);
1.1.1.6 root 2576: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2577:
1.1.1.6 root 2578: dsp_core.instr_cycle += 4;
1.1.1.4 root 2579:
2580: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2581: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2582: newpc = newaddr;
1.1.1.6 root 2583: dsp_core.pc = newpc;
1.1.1.4 root 2584: cur_inst_len = 0;
2585: return;
2586: }
1.1.1.2 root 2587: ++cur_inst_len;
1.1.1.4 root 2588: }
2589:
2590: static void dsp_jsclr_pp(void)
2591: {
2592: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2593:
2594: memspace = (cur_inst>>6) & 1;
2595: value = (cur_inst>>8) & BITMASK(6);
2596: numbit = cur_inst & BITMASK(5);
2597: addr = 0xffc0 + value;
2598: value = read_memory(memspace, addr);
1.1.1.6 root 2599: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2600:
1.1.1.6 root 2601: dsp_core.instr_cycle += 4;
1.1.1.4 root 2602:
1.1 root 2603: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2604: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2605: newpc = newaddr;
1.1.1.6 root 2606: dsp_core.pc = newpc;
1.1.1.4 root 2607: cur_inst_len = 0;
2608: return;
2609: }
2610: ++cur_inst_len;
2611: }
2612:
2613: static void dsp_jsclr_reg(void)
2614: {
2615: Uint32 value, numreg, newpc, numbit, newaddr;
2616:
2617: numreg = (cur_inst>>8) & BITMASK(6);
2618: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2619: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2620:
1.1.1.4 root 2621: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2622: dsp_pm_read_accu24(numreg, &value);
2623: } else {
1.1.1.6 root 2624: value = dsp_core.registers[numreg];
1.1.1.4 root 2625: }
2626:
1.1.1.6 root 2627: dsp_core.instr_cycle += 4;
1.1.1.4 root 2628:
2629: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2630: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2631: newpc = newaddr;
1.1.1.6 root 2632: dsp_core.pc = newpc;
1.1 root 2633: cur_inst_len = 0;
1.1.1.4 root 2634: return;
1.1 root 2635: }
1.1.1.4 root 2636: ++cur_inst_len;
1.1 root 2637: }
2638:
1.1.1.4 root 2639: static void dsp_jset_aa(void)
1.1 root 2640: {
1.1.1.4 root 2641: Uint32 memspace, addr, value, numbit, newpc, newaddr;
2642:
2643: memspace = (cur_inst>>6) & 1;
2644: addr = (cur_inst>>8) & BITMASK(6);
2645: numbit = cur_inst & BITMASK(5);
2646: value = read_memory(memspace, addr);
1.1.1.6 root 2647: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2648:
1.1.1.6 root 2649: dsp_core.instr_cycle += 4;
1.1.1.4 root 2650:
2651: if (value & (1<<numbit)) {
2652: newpc = newaddr;
1.1.1.6 root 2653: dsp_core.pc = newpc;
1.1.1.4 root 2654: cur_inst_len=0;
2655: return;
2656: }
2657: ++cur_inst_len;
2658: }
2659:
2660: static void dsp_jset_ea(void)
2661: {
2662: Uint32 memspace, addr, value, numbit, newpc, newaddr;
1.1 root 2663:
2664: memspace = (cur_inst>>6) & 1;
2665: value = (cur_inst>>8) & BITMASK(6);
2666: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2667: dsp_calc_ea(value, &addr);
2668: value = read_memory(memspace, addr);
1.1.1.6 root 2669: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2670:
1.1.1.6 root 2671: dsp_core.instr_cycle += 4;
1.1.1.7 root 2672:
1.1.1.4 root 2673: if (value & (1<<numbit)) {
2674: newpc = newaddr;
1.1.1.6 root 2675: dsp_core.pc = newpc;
1.1.1.4 root 2676: cur_inst_len=0;
2677: return;
2678: }
2679: ++cur_inst_len;
2680: }
1.1 root 2681:
1.1.1.4 root 2682: static void dsp_jset_pp(void)
2683: {
2684: Uint32 memspace, addr, value, numbit, newpc, newaddr;
2685:
2686: memspace = (cur_inst>>6) & 1;
2687: value = (cur_inst>>8) & BITMASK(6);
2688: numbit = cur_inst & BITMASK(5);
2689: addr = 0xffc0 + value;
2690: value = read_memory(memspace, addr);
1.1.1.6 root 2691: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2692:
1.1.1.6 root 2693: dsp_core.instr_cycle += 4;
1.1.1.4 root 2694:
2695: if (value & (1<<numbit)) {
2696: newpc = newaddr;
1.1.1.6 root 2697: dsp_core.pc = newpc;
1.1.1.4 root 2698: cur_inst_len=0;
2699: return;
2700: }
2701: ++cur_inst_len;
2702: }
2703:
2704: static void dsp_jset_reg(void)
2705: {
2706: Uint32 value, numreg, numbit, newpc, newaddr;
2707:
2708: numreg = (cur_inst>>8) & BITMASK(6);
2709: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2710: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2711:
2712: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2713: dsp_pm_read_accu24(numreg, &value);
2714: } else {
1.1.1.6 root 2715: value = dsp_core.registers[numreg];
1.1.1.4 root 2716: }
2717:
1.1.1.6 root 2718: dsp_core.instr_cycle += 4;
1.1.1.4 root 2719:
2720: if (value & (1<<numbit)) {
2721: newpc = newaddr;
1.1.1.6 root 2722: dsp_core.pc = newpc;
1.1.1.4 root 2723: cur_inst_len=0;
2724: return;
2725: }
2726: ++cur_inst_len;
2727: }
2728:
2729: static void dsp_jsr_imm(void)
2730: {
2731: Uint32 newpc;
2732:
2733: newpc = cur_inst & BITMASK(12);
2734:
1.1.1.6 root 2735: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2736: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2737: }
2738: else {
1.1.1.6 root 2739: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1.1.1.4 root 2740: }
2741:
1.1.1.6 root 2742: dsp_core.pc = newpc;
1.1.1.4 root 2743: cur_inst_len = 0;
2744:
1.1.1.6 root 2745: dsp_core.instr_cycle += 2;
1.1.1.4 root 2746: }
2747:
2748: static void dsp_jsr_ea(void)
2749: {
2750: Uint32 newpc;
2751:
2752: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&newpc);
2753:
1.1.1.6 root 2754: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2755: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2756: }
2757: else {
1.1.1.6 root 2758: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1.1.1.4 root 2759: }
2760:
1.1.1.6 root 2761: dsp_core.pc = newpc;
1.1.1.4 root 2762: cur_inst_len = 0;
2763:
1.1.1.6 root 2764: dsp_core.instr_cycle += 2;
1.1.1.4 root 2765: }
2766:
2767: static void dsp_jsset_aa(void)
2768: {
2769: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2770:
2771: memspace = (cur_inst>>6) & 1;
2772: addr = (cur_inst>>8) & BITMASK(6);
2773: numbit = cur_inst & BITMASK(5);
2774: value = read_memory(memspace, addr);
1.1.1.6 root 2775: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2776:
1.1.1.6 root 2777: dsp_core.instr_cycle += 4;
1.1.1.4 root 2778:
2779: if (value & (1<<numbit)) {
1.1.1.6 root 2780: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2781: newpc = newaddr;
1.1.1.6 root 2782: dsp_core.pc = newpc;
1.1.1.4 root 2783: cur_inst_len = 0;
2784: return;
2785: }
2786: ++cur_inst_len;
2787: }
2788:
2789: static void dsp_jsset_ea(void)
2790: {
2791: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2792:
2793: memspace = (cur_inst>>6) & 1;
2794: value = (cur_inst>>8) & BITMASK(6);
2795: numbit = cur_inst & BITMASK(5);
2796: dsp_calc_ea(value, &addr);
2797: value = read_memory(memspace, addr);
1.1.1.6 root 2798: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2799:
1.1.1.6 root 2800: dsp_core.instr_cycle += 4;
1.1 root 2801:
2802: if (value & (1<<numbit)) {
1.1.1.6 root 2803: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2804: newpc = newaddr;
1.1.1.6 root 2805: dsp_core.pc = newpc;
1.1.1.4 root 2806: cur_inst_len = 0;
2807: return;
1.1 root 2808: }
1.1.1.4 root 2809: ++cur_inst_len;
1.1 root 2810: }
2811:
1.1.1.4 root 2812: static void dsp_jsset_pp(void)
1.1 root 2813: {
1.1.1.4 root 2814: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2815:
2816: memspace = (cur_inst>>6) & 1;
2817: value = (cur_inst>>8) & BITMASK(6);
2818: numbit = cur_inst & BITMASK(5);
2819: addr = 0xffc0 + value;
2820: value = read_memory(memspace, addr);
1.1.1.6 root 2821: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2822:
1.1.1.6 root 2823: dsp_core.instr_cycle += 4;
1.1 root 2824:
1.1.1.4 root 2825: if (value & (1<<numbit)) {
1.1.1.6 root 2826: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2827: newpc = newaddr;
1.1.1.6 root 2828: dsp_core.pc = newpc;
1.1.1.4 root 2829: cur_inst_len = 0;
2830: return;
2831: }
2832: ++cur_inst_len;
1.1 root 2833: }
2834:
1.1.1.4 root 2835: static void dsp_jsset_reg(void)
1.1 root 2836: {
1.1.1.4 root 2837: Uint32 value, numreg, newpc, numbit, newaddr;
1.1 root 2838:
1.1.1.4 root 2839: numreg = (cur_inst>>8) & BITMASK(6);
1.1 root 2840: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2841: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2842:
2843: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2844: dsp_pm_read_accu24(numreg, &value);
2845: } else {
1.1.1.6 root 2846: value = dsp_core.registers[numreg];
1.1.1.4 root 2847: }
1.1 root 2848:
1.1.1.6 root 2849: dsp_core.instr_cycle += 4;
1.1 root 2850:
2851: if (value & (1<<numbit)) {
1.1.1.6 root 2852: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2853: newpc = newaddr;
1.1.1.6 root 2854: dsp_core.pc = newpc;
1.1 root 2855: cur_inst_len = 0;
1.1.1.4 root 2856: return;
1.1 root 2857: }
1.1.1.4 root 2858: ++cur_inst_len;
1.1 root 2859: }
2860:
2861: static void dsp_lua(void)
2862: {
1.1.1.2 root 2863: Uint32 value, srcreg, dstreg, srcsave, srcnew;
2864:
1.1 root 2865: srcreg = (cur_inst>>8) & BITMASK(3);
1.1.1.2 root 2866:
1.1.1.6 root 2867: srcsave = dsp_core.registers[DSP_REG_R0+srcreg];
1.1.1.2 root 2868: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &value);
1.1.1.6 root 2869: srcnew = dsp_core.registers[DSP_REG_R0+srcreg];
2870: dsp_core.registers[DSP_REG_R0+srcreg] = srcsave;
1.1.1.2 root 2871:
1.1 root 2872: dstreg = cur_inst & BITMASK(3);
2873:
2874: if (cur_inst & (1<<3)) {
1.1.1.6 root 2875: dsp_core.registers[DSP_REG_N0+dstreg] = srcnew;
1.1 root 2876: } else {
1.1.1.6 root 2877: dsp_core.registers[DSP_REG_R0+dstreg] = srcnew;
1.1 root 2878: }
2879:
1.1.1.6 root 2880: dsp_core.instr_cycle += 2;
1.1 root 2881: }
2882:
1.1.1.3 root 2883: static void dsp_movec_reg(void)
1.1 root 2884: {
1.1.1.4 root 2885: Uint32 numreg1, numreg2, value, dummy;
1.1 root 2886:
2887: /* S1,D2 */
2888: /* S2,D1 */
2889:
2890: numreg2 = (cur_inst>>8) & BITMASK(6);
1.1.1.4 root 2891: numreg1 = cur_inst & BITMASK(6);
1.1 root 2892:
2893: if (cur_inst & (1<<15)) {
2894: /* Write D1 */
2895:
2896: if ((numreg2 == DSP_REG_A) || (numreg2 == DSP_REG_B)) {
1.1.1.4 root 2897: dsp_pm_read_accu24(numreg2, &value);
1.1 root 2898: } else {
1.1.1.6 root 2899: value = dsp_core.registers[numreg2];
1.1 root 2900: }
1.1.1.4 root 2901: value &= BITMASK(registers_mask[numreg1]);
2902: dsp_write_reg(numreg1, value);
1.1 root 2903: } else {
2904: /* Read S1 */
1.1.1.4 root 2905: if (numreg1 == DSP_REG_SSH) {
2906: dsp_stack_pop(&value, &dummy);
2907: }
2908: else {
1.1.1.6 root 2909: value = dsp_core.registers[numreg1];
1.1.1.4 root 2910: }
1.1 root 2911:
1.1.1.7 root 2912: if (numreg2 == DSP_REG_A) {
2913: dsp_core.registers[DSP_REG_A0] = 0;
2914: dsp_core.registers[DSP_REG_A1] = value & BITMASK(24);
2915: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
2916: }
2917: else if (numreg2 == DSP_REG_B) {
2918: dsp_core.registers[DSP_REG_B0] = 0;
2919: dsp_core.registers[DSP_REG_B1] = value & BITMASK(24);
2920: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
2921: }
2922: else {
1.1.1.6 root 2923: dsp_core.registers[numreg2] = value & BITMASK(registers_mask[numreg2]);
1.1 root 2924: }
2925: }
2926: }
2927:
1.1.1.3 root 2928: static void dsp_movec_aa(void)
1.1 root 2929: {
1.1.1.4 root 2930: Uint32 numreg, addr, memspace, value, dummy;
1.1 root 2931:
2932: /* x:aa,D1 */
2933: /* S1,x:aa */
2934: /* y:aa,D1 */
2935: /* S1,y:aa */
2936:
1.1.1.4 root 2937: numreg = cur_inst & BITMASK(6);
1.1 root 2938: addr = (cur_inst>>8) & BITMASK(6);
2939: memspace = (cur_inst>>6) & 1;
2940:
2941: if (cur_inst & (1<<15)) {
2942: /* Write D1 */
1.1.1.4 root 2943: value = read_memory(memspace, addr);
2944: value &= BITMASK(registers_mask[numreg]);
2945: dsp_write_reg(numreg, value);
1.1 root 2946: } else {
2947: /* Read S1 */
1.1.1.4 root 2948: if (numreg == DSP_REG_SSH) {
2949: dsp_stack_pop(&value, &dummy);
2950: }
2951: else {
1.1.1.6 root 2952: value = dsp_core.registers[numreg];
1.1.1.4 root 2953: }
2954: write_memory(memspace, addr, value);
1.1 root 2955: }
2956: }
2957:
1.1.1.3 root 2958: static void dsp_movec_imm(void)
1.1 root 2959: {
1.1.1.4 root 2960: Uint32 numreg, value;
1.1 root 2961:
2962: /* #xx,D1 */
1.1.1.4 root 2963: numreg = cur_inst & BITMASK(6);
2964: value = (cur_inst>>8) & BITMASK(8);
2965: value &= BITMASK(registers_mask[numreg]);
2966: dsp_write_reg(numreg, value);
1.1 root 2967: }
2968:
1.1.1.3 root 2969: static void dsp_movec_ea(void)
1.1 root 2970: {
1.1.1.4 root 2971: Uint32 numreg, addr, memspace, ea_mode, value, dummy;
1.1 root 2972: int retour;
2973:
2974: /* x:ea,D1 */
2975: /* S1,x:ea */
2976: /* y:ea,D1 */
2977: /* S1,y:ea */
2978: /* #xxxx,D1 */
2979:
1.1.1.4 root 2980: numreg = cur_inst & BITMASK(6);
1.1 root 2981: ea_mode = (cur_inst>>8) & BITMASK(6);
2982: memspace = (cur_inst>>6) & 1;
2983:
2984: if (cur_inst & (1<<15)) {
2985: /* Write D1 */
2986: retour = dsp_calc_ea(ea_mode, &addr);
2987: if (retour) {
1.1.1.4 root 2988: value = addr;
1.1 root 2989: } else {
1.1.1.4 root 2990: value = read_memory(memspace, addr);
1.1 root 2991: }
1.1.1.4 root 2992: value &= BITMASK(registers_mask[numreg]);
2993: dsp_write_reg(numreg, value);
1.1 root 2994: } else {
2995: /* Read S1 */
1.1.1.4 root 2996: dsp_calc_ea(ea_mode, &addr);
2997: if (numreg == DSP_REG_SSH) {
2998: dsp_stack_pop(&value, &dummy);
2999: }
3000: else {
1.1.1.6 root 3001: value = dsp_core.registers[numreg];
1.1.1.4 root 3002: }
3003: write_memory(memspace, addr, value);
1.1 root 3004: }
3005: }
3006:
1.1.1.4 root 3007: static void dsp_movem_aa(void)
1.1 root 3008: {
1.1.1.4 root 3009: Uint32 numreg, addr, value, dummy;
1.1 root 3010:
3011: numreg = cur_inst & BITMASK(6);
1.1.1.4 root 3012: addr = (cur_inst>>8) & BITMASK(6);
1.1 root 3013:
1.1.1.4 root 3014: if (cur_inst & (1<<15)) {
3015: /* Write D */
3016: value = read_memory_p(addr);
3017: value &= BITMASK(registers_mask[numreg]);
3018: dsp_write_reg(numreg, value);
1.1 root 3019: } else {
1.1.1.4 root 3020: /* Read S */
3021: if (numreg == DSP_REG_SSH) {
3022: dsp_stack_pop(&value, &dummy);
3023: }
3024: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
3025: dsp_pm_read_accu24(numreg, &value);
3026: }
3027: else {
1.1.1.6 root 3028: value = dsp_core.registers[numreg];
1.1.1.4 root 3029: }
3030: write_memory(DSP_SPACE_P, addr, value);
3031: }
1.1 root 3032:
1.1.1.6 root 3033: dsp_core.instr_cycle += 4;
1.1.1.4 root 3034: }
3035:
3036: static void dsp_movem_ea(void)
3037: {
3038: Uint32 numreg, addr, ea_mode, value, dummy;
3039:
3040: numreg = cur_inst & BITMASK(6);
3041: ea_mode = (cur_inst>>8) & BITMASK(6);
3042: dsp_calc_ea(ea_mode, &addr);
1.1 root 3043:
3044: if (cur_inst & (1<<15)) {
3045: /* Write D */
1.1.1.4 root 3046: value = read_memory_p(addr);
3047: value &= BITMASK(registers_mask[numreg]);
3048: dsp_write_reg(numreg, value);
1.1 root 3049: } else {
3050: /* Read S */
1.1.1.4 root 3051: if (numreg == DSP_REG_SSH) {
3052: dsp_stack_pop(&value, &dummy);
3053: }
3054: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1 root 3055: dsp_pm_read_accu24(numreg, &value);
1.1.1.4 root 3056: }
3057: else {
1.1.1.6 root 3058: value = dsp_core.registers[numreg];
1.1 root 3059: }
3060: write_memory(DSP_SPACE_P, addr, value);
3061: }
3062:
1.1.1.6 root 3063: dsp_core.instr_cycle += 4;
1.1 root 3064: }
3065:
3066: static void dsp_movep_0(void)
3067: {
3068: /* S,x:pp */
3069: /* x:pp,D */
3070: /* S,y:pp */
3071: /* y:pp,D */
3072:
1.1.1.4 root 3073: Uint32 addr, memspace, numreg, value, dummy;
1.1 root 3074:
3075: addr = 0xffc0 + (cur_inst & BITMASK(6));
3076: memspace = (cur_inst>>16) & 1;
3077: numreg = (cur_inst>>8) & BITMASK(6);
3078:
3079: if (cur_inst & (1<<15)) {
3080: /* Write pp */
3081: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
3082: dsp_pm_read_accu24(numreg, &value);
1.1.1.4 root 3083: }
3084: else if (numreg == DSP_REG_SSH) {
3085: dsp_stack_pop(&value, &dummy);
3086: }
3087: else {
1.1.1.6 root 3088: value = dsp_core.registers[numreg];
1.1 root 3089: }
3090: write_memory(memspace, addr, value);
3091: } else {
3092: /* Read pp */
3093: value = read_memory(memspace, addr);
1.1.1.4 root 3094: value &= BITMASK(registers_mask[numreg]);
3095: dsp_write_reg(numreg, value);
1.1 root 3096: }
1.1.1.4 root 3097:
1.1.1.6 root 3098: dsp_core.instr_cycle += 2;
1.1 root 3099: }
3100:
3101: static void dsp_movep_1(void)
3102: {
3103: /* p:ea,x:pp */
3104: /* x:pp,p:ea */
3105: /* p:ea,y:pp */
3106: /* y:pp,p:ea */
3107:
1.1.1.2 root 3108: Uint32 xyaddr, memspace, paddr;
1.1 root 3109:
3110: xyaddr = 0xffc0 + (cur_inst & BITMASK(6));
3111: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &paddr);
3112: memspace = (cur_inst>>16) & 1;
3113:
3114: if (cur_inst & (1<<15)) {
3115: /* Write pp */
1.1.1.4 root 3116: write_memory(memspace, xyaddr, read_memory_p(paddr));
1.1 root 3117: } else {
3118: /* Read pp */
3119: write_memory(DSP_SPACE_P, paddr, read_memory(memspace, xyaddr));
3120: }
1.1.1.4 root 3121:
1.1.1.7 root 3122: /* Movep is 4 cycles, but according to the motorola doc, */
3123: /* movep from p memory to x or y peripheral memory takes */
3124: /* 2 more cycles, so +4 cycles at total */
3125: dsp_core.instr_cycle += 4;
1.1 root 3126: }
3127:
1.1.1.4 root 3128: static void dsp_movep_23(void)
1.1 root 3129: {
3130: /* x:ea,x:pp */
3131: /* y:ea,x:pp */
3132: /* #xxxxxx,x:pp */
3133: /* x:pp,x:ea */
3134: /* x:pp,y:pp */
3135: /* x:ea,y:pp */
3136: /* y:ea,y:pp */
3137: /* #xxxxxx,y:pp */
3138: /* y:pp,y:ea */
3139: /* y:pp,x:ea */
3140:
1.1.1.2 root 3141: Uint32 addr, peraddr, easpace, perspace, ea_mode;
1.1 root 3142: int retour;
3143:
3144: peraddr = 0xffc0 + (cur_inst & BITMASK(6));
3145: perspace = (cur_inst>>16) & 1;
3146:
3147: ea_mode = (cur_inst>>8) & BITMASK(6);
3148: easpace = (cur_inst>>6) & 1;
3149: retour = dsp_calc_ea(ea_mode, &addr);
3150:
3151: if (cur_inst & (1<<15)) {
3152: /* Write pp */
3153:
3154: if (retour) {
3155: write_memory(perspace, peraddr, addr);
3156: } else {
3157: write_memory(perspace, peraddr, read_memory(easpace, addr));
3158: }
3159: } else {
3160: /* Read pp */
3161: write_memory(easpace, addr, read_memory(perspace, peraddr));
3162: }
1.1.1.4 root 3163:
1.1.1.6 root 3164: dsp_core.instr_cycle += 2;
1.1 root 3165: }
3166:
3167: static void dsp_norm(void)
3168: {
1.1.1.2 root 3169: Uint32 cursr,cur_e, cur_euz, dest[3], numreg, rreg;
3170: Uint16 newsr;
1.1 root 3171:
1.1.1.6 root 3172: cursr = dsp_core.registers[DSP_REG_SR];
1.1 root 3173: cur_e = (cursr>>DSP_SR_E) & 1; /* E */
3174: cur_euz = ~cur_e; /* (not E) and U and (not Z) */
3175: cur_euz &= (cursr>>DSP_SR_U) & 1;
3176: cur_euz &= ~((cursr>>DSP_SR_Z) & 1);
3177: cur_euz &= 1;
3178:
3179: numreg = (cur_inst>>3) & 1;
1.1.1.6 root 3180: dest[0] = dsp_core.registers[DSP_REG_A2+numreg];
3181: dest[1] = dsp_core.registers[DSP_REG_A1+numreg];
3182: dest[2] = dsp_core.registers[DSP_REG_A0+numreg];
1.1 root 3183: rreg = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3184:
3185: if (cur_euz) {
3186: newsr = dsp_asl56(dest);
1.1.1.6 root 3187: --dsp_core.registers[rreg];
3188: dsp_core.registers[rreg] &= BITMASK(16);
1.1 root 3189: } else if (cur_e) {
3190: newsr = dsp_asr56(dest);
1.1.1.6 root 3191: ++dsp_core.registers[rreg];
3192: dsp_core.registers[rreg] &= BITMASK(16);
1.1 root 3193: } else {
3194: newsr = 0;
3195: }
3196:
1.1.1.6 root 3197: dsp_core.registers[DSP_REG_A2+numreg] = dest[0];
3198: dsp_core.registers[DSP_REG_A1+numreg] = dest[1];
3199: dsp_core.registers[DSP_REG_A0+numreg] = dest[2];
1.1.1.2 root 3200:
1.1.1.6 root 3201: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 3202:
1.1.1.6 root 3203: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
3204: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 3205: }
3206:
3207: static void dsp_ori(void)
3208: {
1.1.1.2 root 3209: Uint32 regnum, value;
1.1 root 3210:
3211: value = (cur_inst >> 8) & BITMASK(8);
3212: regnum = cur_inst & BITMASK(2);
3213: switch(regnum) {
3214: case 0:
3215: /* mr */
1.1.1.6 root 3216: dsp_core.registers[DSP_REG_SR] |= value<<8;
1.1 root 3217: break;
3218: case 1:
3219: /* ccr */
1.1.1.6 root 3220: dsp_core.registers[DSP_REG_SR] |= value;
1.1 root 3221: break;
3222: case 2:
3223: /* omr */
1.1.1.6 root 3224: dsp_core.registers[DSP_REG_OMR] |= value;
1.1 root 3225: break;
3226: }
3227: }
3228:
1.1.1.3 root 3229: /*
3230: REP instruction parameter encoding
3231:
3232: xxxxxxxx 00xxxxxx 0xxxxxxx aa
3233: xxxxxxxx 01xxxxxx 0xxxxxxx ea
3234: xxxxxxxx YYxxxxxx 1xxxxxxx imm
3235: xxxxxxxx 11xxxxxx 0xxxxxxx reg
3236: */
3237:
3238: static void dsp_rep_aa(void)
1.1 root 3239: {
3240: /* x:aa */
3241: /* y:aa */
1.1.1.6 root 3242: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3243: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3244: dsp_core.loop_rep = 1; /* We are now running rep */
1.1 root 3245:
1.1.1.6 root 3246: dsp_core.registers[DSP_REG_LC]=read_memory((cur_inst>>6) & 1,(cur_inst>>8) & BITMASK(6));
1.1.1.4 root 3247:
1.1.1.6 root 3248: dsp_core.instr_cycle += 2;
1.1 root 3249: }
3250:
1.1.1.3 root 3251: static void dsp_rep_imm(void)
1.1 root 3252: {
3253: /* #xxx */
3254:
1.1.1.6 root 3255: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3256: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3257: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3258:
1.1.1.6 root 3259: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
1.1.1.3 root 3260: + ((cur_inst & BITMASK(4))<<8);
1.1.1.4 root 3261:
1.1.1.6 root 3262: dsp_core.instr_cycle += 2;
1.1 root 3263: }
3264:
1.1.1.3 root 3265: static void dsp_rep_ea(void)
1.1 root 3266: {
1.1.1.2 root 3267: Uint32 value;
1.1 root 3268:
3269: /* x:ea */
3270: /* y:ea */
3271:
1.1.1.6 root 3272: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3273: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3274: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3275:
1.1 root 3276: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&value);
1.1.1.6 root 3277: dsp_core.registers[DSP_REG_LC]= read_memory((cur_inst>>6) & 1, value);
1.1.1.4 root 3278:
1.1.1.6 root 3279: dsp_core.instr_cycle += 2;
1.1 root 3280: }
3281:
1.1.1.3 root 3282: static void dsp_rep_reg(void)
1.1 root 3283: {
1.1.1.2 root 3284: Uint32 numreg;
1.1 root 3285:
3286: /* R */
3287:
1.1.1.6 root 3288: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3289: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3290: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3291:
1.1 root 3292: numreg = (cur_inst>>8) & BITMASK(6);
3293: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.6 root 3294: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
1.1 root 3295: } else {
1.1.1.6 root 3296: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
1.1 root 3297: }
1.1.1.6 root 3298: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.4 root 3299:
1.1.1.6 root 3300: dsp_core.instr_cycle += 2;
1.1 root 3301: }
3302:
3303: static void dsp_reset(void)
3304: {
3305: /* Reset external peripherals */
1.1.1.6 root 3306: dsp_core.instr_cycle += 2;
1.1 root 3307: }
3308:
3309: static void dsp_rti(void)
3310: {
1.1.1.2 root 3311: Uint32 newpc = 0, newsr = 0;
1.1 root 3312:
3313: dsp_stack_pop(&newpc, &newsr);
1.1.1.6 root 3314: dsp_core.pc = newpc;
3315: dsp_core.registers[DSP_REG_SR] = newsr;
1.1 root 3316: cur_inst_len = 0;
1.1.1.4 root 3317:
1.1.1.6 root 3318: dsp_core.instr_cycle += 2;
1.1 root 3319: }
3320:
3321: static void dsp_rts(void)
3322: {
1.1.1.2 root 3323: Uint32 newpc = 0, newsr;
1.1 root 3324:
3325: dsp_stack_pop(&newpc, &newsr);
1.1.1.6 root 3326: dsp_core.pc = newpc;
1.1 root 3327: cur_inst_len = 0;
1.1.1.4 root 3328:
1.1.1.6 root 3329: dsp_core.instr_cycle += 2;
1.1 root 3330: }
3331:
3332: static void dsp_stop(void)
3333: {
1.1.1.6 root 3334: LOG_TRACE(TRACE_DSP_STATE, "Dsp: STOP instruction\n");
1.1 root 3335: }
3336:
3337: static void dsp_swi(void)
3338: {
3339: /* Raise interrupt p:0x0006 */
1.1.1.6 root 3340: dsp_core.instr_cycle += 6;
1.1 root 3341: }
3342:
3343: static void dsp_tcc(void)
3344: {
1.1.1.6 root 3345: Uint32 cc_code, regsrc1, regdest1;
1.1.1.2 root 3346: Uint32 regsrc2, regdest2;
1.1.1.6 root 3347: Uint32 val0, val1, val2;
3348:
1.1 root 3349: cc_code = (cur_inst>>12) & BITMASK(4);
3350:
3351: if (dsp_calc_cc(cc_code)) {
3352: regsrc1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][0];
1.1.1.2 root 3353: regdest1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][1];
1.1 root 3354:
3355: /* Read S1 */
1.1.1.7 root 3356: if (regsrc1 == DSP_REG_A) {
3357: val0 = dsp_core.registers[DSP_REG_A0];
3358: val1 = dsp_core.registers[DSP_REG_A1];
3359: val2 = dsp_core.registers[DSP_REG_A2];
3360: }
3361: else if (regsrc1 == DSP_REG_B) {
3362: val0 = dsp_core.registers[DSP_REG_B0];
3363: val1 = dsp_core.registers[DSP_REG_B1];
3364: val2 = dsp_core.registers[DSP_REG_B2];
3365: }
3366: else {
1.1.1.6 root 3367: val0 = 0;
3368: val1 = dsp_core.registers[regsrc1];
1.1.1.7 root 3369: val2 = val1 & (1<<23) ? 0xff : 0x0;
1.1 root 3370: }
3371:
3372: /* Write D1 */
1.1.1.7 root 3373: if (regdest1 == DSP_REG_A) {
3374: dsp_core.registers[DSP_REG_A2] = val2;
3375: dsp_core.registers[DSP_REG_A1] = val1;
3376: dsp_core.registers[DSP_REG_A0] = val0;
3377: }
3378: else {
3379: dsp_core.registers[DSP_REG_B2] = val2;
3380: dsp_core.registers[DSP_REG_B1] = val1;
3381: dsp_core.registers[DSP_REG_B0] = val0;
3382: }
1.1 root 3383:
3384: /* S2,D2 transfer */
3385: if (cur_inst & (1<<16)) {
1.1.1.2 root 3386: regsrc2 = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3387: regdest2 = DSP_REG_R0+(cur_inst & BITMASK(3));
1.1 root 3388:
1.1.1.6 root 3389: dsp_core.registers[regdest2] = dsp_core.registers[regsrc2];
1.1 root 3390: }
3391: }
3392: }
3393:
3394: static void dsp_wait(void)
3395: {
1.1.1.6 root 3396: LOG_TRACE(TRACE_DSP_STATE, "Dsp: WAIT instruction\n");
1.1 root 3397: }
3398:
1.1.1.2 root 3399: static int dsp_pm_read_accu24(int numreg, Uint32 *dest)
1.1 root 3400: {
1.1.1.4 root 3401: Uint32 scaling, value, reg;
1.1.1.7 root 3402: int got_limited = 0;
1.1 root 3403:
3404: /* Read an accumulator, stores it limited */
3405:
1.1.1.6 root 3406: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
1.1.1.4 root 3407: reg = numreg & 1;
1.1 root 3408:
1.1.1.6 root 3409: value = (dsp_core.registers[DSP_REG_A2+reg]) << 24;
3410: value += dsp_core.registers[DSP_REG_A1+reg];
1.1 root 3411:
3412: switch(scaling) {
3413: case 0:
1.1.1.4 root 3414: /* No scaling */
3415: break;
3416: case 1:
3417: /* scaling down */
3418: value >>= 1;
1.1 root 3419: break;
3420: case 2:
1.1.1.4 root 3421: /* scaling up */
3422: value <<= 1;
1.1.1.6 root 3423: value |= (dsp_core.registers[DSP_REG_A0+reg]>>23) & 1;
1.1 root 3424: break;
1.1.1.4 root 3425: /* indeterminate */
3426: case 3:
3427: break;
3428: }
3429:
3430: /* limiting ? */
3431: value &= BITMASK(24);
3432:
1.1.1.6 root 3433: if (dsp_core.registers[DSP_REG_A2+reg] == 0) {
1.1.1.4 root 3434: if (value <= 0x007fffff) {
3435: /* No limiting */
3436: *dest=value;
3437: return 0;
3438: }
3439: }
3440:
1.1.1.6 root 3441: if (dsp_core.registers[DSP_REG_A2+reg] == 0xff) {
1.1.1.4 root 3442: if (value >= 0x00800000) {
3443: /* No limiting */
3444: *dest=value;
3445: return 0;
3446: }
1.1 root 3447: }
3448:
1.1.1.6 root 3449: if (dsp_core.registers[DSP_REG_A2+reg] & (1<<7)) {
1.1 root 3450: /* Limited to maximum negative value */
3451: *dest=0x00800000;
1.1.1.6 root 3452: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
1.1.1.2 root 3453: got_limited=1;
1.1 root 3454: } else {
3455: /* Limited to maximal positive value */
3456: *dest=0x007fffff;
1.1.1.6 root 3457: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
1.1.1.2 root 3458: got_limited=1;
1.1 root 3459: }
1.1.1.2 root 3460:
3461: return got_limited;
1.1 root 3462: }
3463:
3464: static void dsp_pm_0(void)
3465: {
1.1.1.6 root 3466: Uint32 memspace, numreg, addr, save_accu, save_xy0;
1.1 root 3467: /*
3468: 0000 100d 00mm mrrr S,x:ea x0,D
3469: 0000 100d 10mm mrrr S,y:ea y0,D
3470: */
3471: memspace = (cur_inst>>15) & 1;
3472: numreg = (cur_inst>>16) & 1;
1.1.1.6 root 3473: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &addr);
3474:
3475: /* Save A or B */
3476: dsp_pm_read_accu24(numreg, &save_accu);
1.1 root 3477:
1.1.1.6 root 3478: /* Save X0 or Y0 */
3479: save_xy0 = dsp_core.registers[DSP_REG_X0+(memspace<<1)];
3480:
3481: /* Execute parallel instruction */
3482: opcodes_alu[cur_inst & BITMASK(8)]();
3483:
3484: /* Move [A|B] to [x|y]:ea */
3485: write_memory(memspace, addr, save_accu);
3486:
3487: /* Move [x|y]0 to [A|B] */
3488: dsp_core.registers[DSP_REG_A0+numreg] = 0;
3489: dsp_core.registers[DSP_REG_A1+numreg] = save_xy0;
1.1.1.7 root 3490: dsp_core.registers[DSP_REG_A2+numreg] = save_xy0 & (1<<23) ? 0xff : 0x0;
1.1 root 3491: }
3492:
3493: static void dsp_pm_1(void)
3494: {
1.1.1.6 root 3495: Uint32 memspace, numreg1, numreg2, value, xy_addr, retour, save_1, save_2;
1.1 root 3496: /*
3497: 0001 ffdf w0mm mrrr x:ea,D1 S2,D2
3498: S1,x:ea S2,D2
3499: #xxxxxx,D1 S2,D2
3500: 0001 deff w1mm mrrr S1,D1 y:ea,D2
3501: S1,D1 S2,y:ea
3502: S1,D1 #xxxxxx,D2
3503: */
3504: value = (cur_inst>>8) & BITMASK(6);
3505: retour = dsp_calc_ea(value, &xy_addr);
3506: memspace = (cur_inst>>14) & 1;
1.1.1.6 root 3507: numreg1 = numreg2 = DSP_REG_NULL;
1.1 root 3508:
3509: if (memspace) {
3510: /* Y: */
3511: switch((cur_inst>>16) & BITMASK(2)) {
1.1.1.6 root 3512: case 0: numreg1 = DSP_REG_Y0; break;
3513: case 1: numreg1 = DSP_REG_Y1; break;
3514: case 2: numreg1 = DSP_REG_A; break;
3515: case 3: numreg1 = DSP_REG_B; break;
1.1 root 3516: }
3517: } else {
3518: /* X: */
3519: switch((cur_inst>>18) & BITMASK(2)) {
1.1.1.6 root 3520: case 0: numreg1 = DSP_REG_X0; break;
3521: case 1: numreg1 = DSP_REG_X1; break;
3522: case 2: numreg1 = DSP_REG_A; break;
3523: case 3: numreg1 = DSP_REG_B; break;
1.1 root 3524: }
3525: }
3526:
3527: if (cur_inst & (1<<15)) {
3528: /* Write D1 */
1.1.1.6 root 3529: if (retour)
3530: save_1 = xy_addr;
3531: else
3532: save_1 = read_memory(memspace, xy_addr);
1.1 root 3533: } else {
3534: /* Read S1 */
1.1.1.6 root 3535: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
3536: dsp_pm_read_accu24(numreg1, &save_1);
3537: else
3538: save_1 = dsp_core.registers[numreg1];
1.1 root 3539: }
1.1.1.6 root 3540:
1.1 root 3541: /* S2 */
3542: if (memspace) {
3543: /* Y: */
1.1.1.6 root 3544: numreg2 = DSP_REG_A + ((cur_inst>>19) & 1);
1.1 root 3545: } else {
3546: /* X: */
1.1.1.6 root 3547: numreg2 = DSP_REG_A + ((cur_inst>>17) & 1);
1.1 root 3548: }
1.1.1.6 root 3549: dsp_pm_read_accu24(numreg2, &save_2);
1.1 root 3550:
1.1.1.6 root 3551:
3552: /* Execute parallel instruction */
3553: opcodes_alu[cur_inst & BITMASK(8)]();
3554:
3555:
3556: /* Write parallel move values */
3557: if (cur_inst & (1<<15)) {
3558: /* Write D1 */
3559: if (numreg1 == DSP_REG_A) {
3560: dsp_core.registers[DSP_REG_A0] = 0x0;
3561: dsp_core.registers[DSP_REG_A1] = save_1;
3562: dsp_core.registers[DSP_REG_A2] = save_1 & (1<<23) ? 0xff : 0x0;
3563: }
3564: else if (numreg1 == DSP_REG_B) {
3565: dsp_core.registers[DSP_REG_B0] = 0x0;
3566: dsp_core.registers[DSP_REG_B1] = save_1;
3567: dsp_core.registers[DSP_REG_B2] = save_1 & (1<<23) ? 0xff : 0x0;
3568: }
3569: else {
3570: } dsp_core.registers[numreg1] = save_1;
3571: } else {
3572: /* Read S1 */
3573: write_memory(memspace, xy_addr, save_1);
3574: }
3575:
3576: /* S2 -> D2 */
1.1 root 3577: if (memspace) {
3578: /* Y: */
1.1.1.6 root 3579: numreg2 = DSP_REG_X0 + ((cur_inst>>18) & 1);
1.1 root 3580: } else {
3581: /* X: */
1.1.1.6 root 3582: numreg2 = DSP_REG_Y0 + ((cur_inst>>16) & 1);
1.1 root 3583: }
1.1.1.6 root 3584: dsp_core.registers[numreg2] = save_2;
1.1 root 3585: }
3586:
3587: static void dsp_pm_2(void)
3588: {
1.1.1.2 root 3589: Uint32 dummy;
1.1 root 3590: /*
3591: 0010 0000 0000 0000 nop
3592: 0010 0000 010m mrrr R update
3593: 0010 00ee eeed dddd S,D
3594: 001d dddd iiii iiii #xx,D
3595: */
1.1.1.4 root 3596: if ((cur_inst & 0xffff00) == 0x200000) {
1.1.1.6 root 3597: /* Execute parallel instruction */
3598: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3599: return;
3600: }
3601:
1.1.1.4 root 3602: if ((cur_inst & 0xffe000) == 0x204000) {
1.1 root 3603: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &dummy);
1.1.1.6 root 3604: /* Execute parallel instruction */
3605: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3606: return;
3607: }
3608:
1.1.1.4 root 3609: if ((cur_inst & 0xfc0000) == 0x200000) {
1.1 root 3610: dsp_pm_2_2();
3611: return;
3612: }
3613:
3614: dsp_pm_3();
3615: }
3616:
3617: static void dsp_pm_2_2(void)
3618: {
3619: /*
3620: 0010 00ee eeed dddd S,D
3621: */
1.1.1.6 root 3622: Uint32 srcreg, dstreg, save_reg;
1.1 root 3623:
3624: srcreg = (cur_inst >> 13) & BITMASK(5);
3625: dstreg = (cur_inst >> 8) & BITMASK(5);
3626:
1.1.1.6 root 3627: if ((srcreg == DSP_REG_A) || (srcreg == DSP_REG_B))
3628: /* Accu to register: limited 24 bits */
3629: dsp_pm_read_accu24(srcreg, &save_reg);
3630: else
3631: save_reg = dsp_core.registers[srcreg];
3632:
3633: /* Execute parallel instruction */
3634: opcodes_alu[cur_inst & BITMASK(8)]();
3635:
3636: /* Write reg */
3637: if (dstreg == DSP_REG_A) {
3638: dsp_core.registers[DSP_REG_A0] = 0x0;
3639: dsp_core.registers[DSP_REG_A1] = save_reg;
3640: dsp_core.registers[DSP_REG_A2] = save_reg & (1<<23) ? 0xff : 0x0;
3641: }
3642: else if (dstreg == DSP_REG_B) {
3643: dsp_core.registers[DSP_REG_B0] = 0x0;
3644: dsp_core.registers[DSP_REG_B1] = save_reg;
3645: dsp_core.registers[DSP_REG_B2] = save_reg & (1<<23) ? 0xff : 0x0;
3646: }
3647: else {
3648: dsp_core.registers[dstreg] = save_reg & BITMASK(registers_mask[dstreg]);
1.1 root 3649: }
3650: }
3651:
3652: static void dsp_pm_3(void)
3653: {
1.1.1.6 root 3654: Uint32 dstreg, srcvalue;
1.1 root 3655: /*
3656: 001d dddd iiii iiii #xx,R
3657: */
1.1.1.6 root 3658:
3659: /* Execute parallel instruction */
3660: opcodes_alu[cur_inst & BITMASK(8)]();
3661:
3662: /* Write reg */
3663: dstreg = (cur_inst >> 16) & BITMASK(5);
1.1 root 3664: srcvalue = (cur_inst >> 8) & BITMASK(8);
3665:
1.1.1.6 root 3666: switch(dstreg) {
1.1 root 3667: case DSP_REG_X0:
3668: case DSP_REG_X1:
3669: case DSP_REG_Y0:
3670: case DSP_REG_Y1:
3671: case DSP_REG_A:
3672: case DSP_REG_B:
3673: srcvalue <<= 16;
3674: break;
3675: }
3676:
1.1.1.6 root 3677: if (dstreg == DSP_REG_A) {
3678: dsp_core.registers[DSP_REG_A0] = 0x0;
3679: dsp_core.registers[DSP_REG_A1] = srcvalue;
3680: dsp_core.registers[DSP_REG_A2] = srcvalue & (1<<23) ? 0xff : 0x0;
3681: }
3682: else if (dstreg == DSP_REG_B) {
3683: dsp_core.registers[DSP_REG_B0] = 0x0;
3684: dsp_core.registers[DSP_REG_B1] = srcvalue;
3685: dsp_core.registers[DSP_REG_B2] = srcvalue & (1<<23) ? 0xff : 0x0;
3686: }
3687: else {
3688: dsp_core.registers[dstreg] = srcvalue & BITMASK(registers_mask[dstreg]);
1.1 root 3689: }
3690: }
3691:
3692: static void dsp_pm_4(void)
3693: {
3694: /*
1.1.1.4 root 3695: 0100 l0ll w0aa aaaa l:aa,D
1.1 root 3696: S,l:aa
1.1.1.4 root 3697: 0100 l0ll w1mm mrrr l:ea,D
1.1 root 3698: S,l:ea
1.1.1.4 root 3699: 01dd 0ddd w0aa aaaa x:aa,D
1.1 root 3700: S,x:aa
1.1.1.4 root 3701: 01dd 0ddd w1mm mrrr x:ea,D
1.1 root 3702: S,x:ea
3703: #xxxxxx,D
1.1.1.4 root 3704: 01dd 1ddd w0aa aaaa y:aa,D
1.1 root 3705: S,y:aa
1.1.1.4 root 3706: 01dd 1ddd w1mm mrrr y:ea,D
1.1 root 3707: S,y:ea
3708: #xxxxxx,D
3709: */
1.1.1.4 root 3710: if ((cur_inst & 0xf40000)==0x400000) {
3711: dsp_pm_4x();
1.1 root 3712: return;
3713: }
3714:
3715: dsp_pm_5();
3716: }
3717:
1.1.1.4 root 3718: static void dsp_pm_4x(void)
1.1 root 3719: {
1.1.1.6 root 3720: Uint32 value, numreg, l_addr, save_lx, save_ly;
1.1 root 3721: /*
1.1.1.4 root 3722: 0100 l0ll w0aa aaaa l:aa,D
3723: S,l:aa
3724: 0100 l0ll w1mm mrrr l:ea,D
3725: S,l:ea
1.1 root 3726: */
1.1.1.4 root 3727: value = (cur_inst>>8) & BITMASK(6);
3728: if (cur_inst & (1<<14)) {
3729: dsp_calc_ea(value, &l_addr);
3730: } else {
3731: l_addr = value;
3732: }
3733:
1.1 root 3734: numreg = (cur_inst>>16) & BITMASK(2);
3735: numreg |= (cur_inst>>17) & (1<<2);
3736:
3737: if (cur_inst & (1<<15)) {
3738: /* Write D */
1.1.1.6 root 3739: save_lx = read_memory(DSP_SPACE_X,l_addr);
3740: save_ly = read_memory(DSP_SPACE_Y,l_addr);
3741: }
3742: else {
3743: /* Read S */
1.1.1.4 root 3744: switch(numreg) {
3745: case 0:
3746: /* A10 */
1.1.1.6 root 3747: save_lx = dsp_core.registers[DSP_REG_A1];
3748: save_ly = dsp_core.registers[DSP_REG_A0];
1.1.1.4 root 3749: break;
3750: case 1:
3751: /* B10 */
1.1.1.6 root 3752: save_lx = dsp_core.registers[DSP_REG_B1];
3753: save_ly = dsp_core.registers[DSP_REG_B0];
1.1.1.4 root 3754: break;
3755: case 2:
3756: /* X */
1.1.1.6 root 3757: save_lx = dsp_core.registers[DSP_REG_X1];
3758: save_ly = dsp_core.registers[DSP_REG_X0];
1.1.1.4 root 3759: break;
3760: case 3:
3761: /* Y */
1.1.1.6 root 3762: save_lx = dsp_core.registers[DSP_REG_Y1];
3763: save_ly = dsp_core.registers[DSP_REG_Y0];
1.1.1.4 root 3764: break;
3765: case 4:
3766: /* A */
1.1.1.6 root 3767: if (dsp_pm_read_accu24(DSP_REG_A, &save_lx)) {
3768: /* Was limited, set lower part */
3769: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3770: } else {
3771: /* Not limited */
3772: save_ly = dsp_core.registers[DSP_REG_A0];
3773: }
1.1.1.4 root 3774: break;
3775: case 5:
3776: /* B */
1.1.1.6 root 3777: if (dsp_pm_read_accu24(DSP_REG_B, &save_lx)) {
3778: /* Was limited, set lower part */
3779: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3780: } else {
3781: /* Not limited */
3782: save_ly = dsp_core.registers[DSP_REG_B0];
3783: }
1.1.1.4 root 3784: break;
3785: case 6:
3786: /* AB */
1.1.1.6 root 3787: dsp_pm_read_accu24(DSP_REG_A, &save_lx);
3788: dsp_pm_read_accu24(DSP_REG_B, &save_ly);
1.1.1.4 root 3789: break;
3790: case 7:
3791: /* BA */
1.1.1.6 root 3792: dsp_pm_read_accu24(DSP_REG_B, &save_lx);
3793: dsp_pm_read_accu24(DSP_REG_A, &save_ly);
1.1.1.4 root 3794: break;
1.1 root 3795: }
1.1.1.6 root 3796: }
1.1 root 3797:
1.1.1.6 root 3798: /* Execute parallel instruction */
3799: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3800:
1.1.1.6 root 3801:
3802: if (cur_inst & (1<<15)) {
3803: /* Write D */
1.1.1.4 root 3804: switch(numreg) {
1.1.1.6 root 3805: case 0: /* A10 */
3806: dsp_core.registers[DSP_REG_A1] = save_lx;
3807: dsp_core.registers[DSP_REG_A0] = save_ly;
1.1.1.4 root 3808: break;
1.1.1.6 root 3809: case 1: /* B10 */
3810: dsp_core.registers[DSP_REG_B1] = save_lx;
3811: dsp_core.registers[DSP_REG_B0] = save_ly;
1.1.1.4 root 3812: break;
1.1.1.6 root 3813: case 2: /* X */
3814: dsp_core.registers[DSP_REG_X1] = save_lx;
3815: dsp_core.registers[DSP_REG_X0] = save_ly;
1.1.1.4 root 3816: break;
1.1.1.6 root 3817: case 3: /* Y */
3818: dsp_core.registers[DSP_REG_Y1] = save_lx;
3819: dsp_core.registers[DSP_REG_Y0] = save_ly;
1.1.1.4 root 3820: break;
1.1.1.6 root 3821: case 4: /* A */
3822: dsp_core.registers[DSP_REG_A0] = save_ly;
3823: dsp_core.registers[DSP_REG_A1] = save_lx;
3824: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
1.1.1.4 root 3825: break;
1.1.1.6 root 3826: case 5: /* B */
3827: dsp_core.registers[DSP_REG_B0] = save_ly;
3828: dsp_core.registers[DSP_REG_B1] = save_lx;
3829: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
1.1.1.4 root 3830: break;
1.1.1.6 root 3831: case 6: /* AB */
3832: dsp_core.registers[DSP_REG_A0] = 0;
3833: dsp_core.registers[DSP_REG_A1] = save_lx;
3834: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
3835: dsp_core.registers[DSP_REG_B0] = 0;
3836: dsp_core.registers[DSP_REG_B1] = save_ly;
3837: dsp_core.registers[DSP_REG_B2] = save_ly & (1<<23) ? 0xff : 0;
1.1.1.4 root 3838: break;
1.1.1.6 root 3839: case 7: /* BA */
3840: dsp_core.registers[DSP_REG_B0] = 0;
3841: dsp_core.registers[DSP_REG_B1] = save_lx;
3842: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
3843: dsp_core.registers[DSP_REG_A0] = 0;
3844: dsp_core.registers[DSP_REG_A1] = save_ly;
3845: dsp_core.registers[DSP_REG_A2] = save_ly & (1<<23) ? 0xff : 0;
1.1.1.4 root 3846: break;
1.1 root 3847: }
1.1.1.6 root 3848: }
3849: else {
3850: /* Read S */
3851: write_memory(DSP_SPACE_X, l_addr, save_lx);
3852: write_memory(DSP_SPACE_Y, l_addr, save_ly);
1.1 root 3853: }
3854: }
3855:
3856: static void dsp_pm_5(void)
3857: {
1.1.1.2 root 3858: Uint32 memspace, numreg, value, xy_addr, retour;
1.1 root 3859: /*
1.1.1.4 root 3860: 01dd 0ddd w0aa aaaa x:aa,D
1.1 root 3861: S,x:aa
1.1.1.4 root 3862: 01dd 0ddd w1mm mrrr x:ea,D
1.1 root 3863: S,x:ea
3864: #xxxxxx,D
1.1.1.4 root 3865: 01dd 1ddd w0aa aaaa y:aa,D
1.1 root 3866: S,y:aa
1.1.1.4 root 3867: 01dd 1ddd w1mm mrrr y:ea,D
1.1 root 3868: S,y:ea
3869: #xxxxxx,D
3870: */
3871:
3872: value = (cur_inst>>8) & BITMASK(6);
3873:
3874: if (cur_inst & (1<<14)) {
3875: retour = dsp_calc_ea(value, &xy_addr);
3876: } else {
3877: xy_addr = value;
3878: retour = 0;
3879: }
3880:
3881: memspace = (cur_inst>>19) & 1;
3882: numreg = (cur_inst>>16) & BITMASK(3);
3883: numreg |= (cur_inst>>17) & (BITMASK(2)<<3);
3884:
3885: if (cur_inst & (1<<15)) {
3886: /* Write D */
1.1.1.6 root 3887: if (retour)
1.1 root 3888: value = xy_addr;
1.1.1.6 root 3889: else
1.1 root 3890: value = read_memory(memspace, xy_addr);
1.1.1.6 root 3891: }
3892: else {
1.1 root 3893: /* Read S */
1.1.1.6 root 3894: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B))
3895: dsp_pm_read_accu24(numreg, &value);
3896: else
3897: value = dsp_core.registers[numreg];
3898: }
1.1 root 3899:
3900:
1.1.1.6 root 3901: /* Execute parallel instruction */
3902: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3903:
1.1.1.6 root 3904: if (cur_inst & (1<<15)) {
3905: /* Write D */
3906: if (numreg == DSP_REG_A) {
3907: dsp_core.registers[DSP_REG_A0] = 0x0;
3908: dsp_core.registers[DSP_REG_A1] = value;
3909: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
3910: }
3911: else if (numreg == DSP_REG_B) {
3912: dsp_core.registers[DSP_REG_B0] = 0x0;
3913: dsp_core.registers[DSP_REG_B1] = value;
3914: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
3915: }
3916: else {
3917: dsp_core.registers[numreg] = value & BITMASK(registers_mask[numreg]);
3918: }
3919: }
3920: else {
1.1.1.7 root 3921: /* Read S */
1.1.1.6 root 3922: write_memory(memspace, xy_addr, value);
1.1 root 3923: }
3924: }
3925:
3926: static void dsp_pm_8(void)
3927: {
1.1.1.2 root 3928: Uint32 ea1, ea2;
3929: Uint32 numreg1, numreg2;
1.1.1.6 root 3930: Uint32 save_reg1, save_reg2, x_addr, y_addr;
1.1 root 3931: /*
1.1.1.4 root 3932: 1wmm eeff WrrM MRRR x:ea,D1 y:ea,D2
1.1 root 3933: x:ea,D1 S2,y:ea
3934: S1,x:ea y:ea,D2
3935: S1,x:ea S2,y:ea
3936: */
3937: numreg1 = numreg2 = DSP_REG_NULL;
3938:
3939: ea1 = (cur_inst>>8) & BITMASK(5);
3940: if ((ea1>>3) == 0) {
3941: ea1 |= (1<<5);
3942: }
3943: ea2 = (cur_inst>>13) & BITMASK(2);
3944: ea2 |= (cur_inst>>17) & (BITMASK(2)<<3);
3945: if ((ea1 & (1<<2))==0) {
3946: ea2 |= 1<<2;
3947: }
3948: if ((ea2>>3) == 0) {
3949: ea2 |= (1<<5);
3950: }
3951:
1.1.1.4 root 3952: dsp_calc_ea(ea1, &x_addr);
3953: dsp_calc_ea(ea2, &y_addr);
3954:
1.1 root 3955: switch((cur_inst>>18) & BITMASK(2)) {
3956: case 0: numreg1=DSP_REG_X0; break;
3957: case 1: numreg1=DSP_REG_X1; break;
3958: case 2: numreg1=DSP_REG_A; break;
3959: case 3: numreg1=DSP_REG_B; break;
3960: }
3961: switch((cur_inst>>16) & BITMASK(2)) {
3962: case 0: numreg2=DSP_REG_Y0; break;
3963: case 1: numreg2=DSP_REG_Y1; break;
3964: case 2: numreg2=DSP_REG_A; break;
3965: case 3: numreg2=DSP_REG_B; break;
3966: }
3967:
3968: if (cur_inst & (1<<15)) {
3969: /* Write D1 */
1.1.1.6 root 3970: save_reg1 = read_memory(DSP_SPACE_X, x_addr);
1.1 root 3971: } else {
3972: /* Read S1 */
1.1.1.6 root 3973: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
3974: dsp_pm_read_accu24(numreg1, &save_reg1);
3975: else
3976: save_reg1 = dsp_core.registers[numreg1];
1.1 root 3977: }
3978:
3979: if (cur_inst & (1<<22)) {
3980: /* Write D2 */
1.1.1.6 root 3981: save_reg2 = read_memory(DSP_SPACE_Y, y_addr);
1.1 root 3982: } else {
3983: /* Read S2 */
1.1.1.6 root 3984: if ((numreg2==DSP_REG_A) || (numreg2==DSP_REG_B))
3985: dsp_pm_read_accu24(numreg2, &save_reg2);
3986: else
3987: save_reg2 = dsp_core.registers[numreg2];
1.1 root 3988: }
3989:
3990:
1.1.1.6 root 3991: /* Execute parallel instruction */
3992: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3993:
1.1.1.6 root 3994: /* Write first parallel move */
3995: if (cur_inst & (1<<15)) {
3996: /* Write D1 */
3997: if (numreg1 == DSP_REG_A) {
3998: dsp_core.registers[DSP_REG_A0] = 0x0;
3999: dsp_core.registers[DSP_REG_A1] = save_reg1;
4000: dsp_core.registers[DSP_REG_A2] = save_reg1 & (1<<23) ? 0xff : 0x0;
4001: }
4002: else if (numreg1 == DSP_REG_B) {
4003: dsp_core.registers[DSP_REG_B0] = 0x0;
4004: dsp_core.registers[DSP_REG_B1] = save_reg1;
4005: dsp_core.registers[DSP_REG_B2] = save_reg1 & (1<<23) ? 0xff : 0x0;
4006: }
4007: else {
4008: dsp_core.registers[numreg1] = save_reg1;
4009: }
4010: } else {
4011: /* Read S1 */
4012: write_memory(DSP_SPACE_X, x_addr, save_reg1);
4013: }
4014:
4015: /* Write second parallel move */
4016: if (cur_inst & (1<<22)) {
4017: /* Write D2 */
4018: if (numreg2 == DSP_REG_A) {
4019: dsp_core.registers[DSP_REG_A0] = 0x0;
4020: dsp_core.registers[DSP_REG_A1] = save_reg2;
4021: dsp_core.registers[DSP_REG_A2] = save_reg2 & (1<<23) ? 0xff : 0x0;
4022: }
4023: else if (numreg2 == DSP_REG_B) {
4024: dsp_core.registers[DSP_REG_B0] = 0x0;
4025: dsp_core.registers[DSP_REG_B1] = save_reg2;
4026: dsp_core.registers[DSP_REG_B2] = save_reg2 & (1<<23) ? 0xff : 0x0;
4027: }
4028: else {
4029: dsp_core.registers[numreg2] = save_reg2;
4030: }
4031: } else {
4032: /* Read S2 */
4033: write_memory(DSP_SPACE_Y, y_addr, save_reg2);
4034: }
4035: }
4036:
4037: /**********************************
4038: * 56bit arithmetic
4039: **********************************/
4040:
4041: /* source,dest[0] is 55:48 */
4042: /* source,dest[1] is 47:24 */
4043: /* source,dest[2] is 23:00 */
4044:
4045: static Uint16 dsp_abs56(Uint32 *dest)
1.1 root 4046: {
1.1.1.2 root 4047: Uint32 zerodest[3];
4048: Uint16 newsr;
1.1 root 4049:
4050: /* D=|D| */
4051:
4052: if (dest[0] & (1<<7)) {
4053: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4054:
4055: newsr = dsp_sub56(dest, zerodest);
4056:
4057: dest[0] = zerodest[0];
4058: dest[1] = zerodest[1];
4059: dest[2] = zerodest[2];
4060: } else {
4061: newsr = 0;
4062: }
4063:
4064: return newsr;
4065: }
4066:
1.1.1.2 root 4067: static Uint16 dsp_asl56(Uint32 *dest)
1.1 root 4068: {
1.1.1.2 root 4069: Uint16 overflow, carry;
1.1 root 4070:
4071: /* Shift left dest 1 bit: D<<=1 */
4072:
4073: carry = (dest[0]>>7) & 1;
4074:
4075: dest[0] <<= 1;
4076: dest[0] |= (dest[1]>>23) & 1;
4077: dest[0] &= BITMASK(8);
4078:
4079: dest[1] <<= 1;
4080: dest[1] |= (dest[2]>>23) & 1;
4081: dest[1] &= BITMASK(24);
4082:
4083: dest[2] <<= 1;
4084: dest[2] &= BITMASK(24);
4085:
4086: overflow = (carry != ((dest[0]>>7) & 1));
4087:
4088: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4089: }
4090:
1.1.1.2 root 4091: static Uint16 dsp_asr56(Uint32 *dest)
1.1 root 4092: {
1.1.1.2 root 4093: Uint16 carry;
1.1 root 4094:
4095: /* Shift right dest 1 bit: D>>=1 */
4096:
4097: carry = dest[2] & 1;
4098:
4099: dest[2] >>= 1;
4100: dest[2] |= (dest[1] & 1)<<23;
4101:
4102: dest[1] >>= 1;
4103: dest[1] |= (dest[0] & 1)<<23;
4104:
4105: dest[0] >>= 1;
4106: dest[0] |= (dest[0] & (1<<6))<<1;
4107:
4108: return (carry<<DSP_SR_C);
4109: }
4110:
1.1.1.2 root 4111: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest)
1.1 root 4112: {
1.1.1.4 root 4113: Uint16 overflow, carry, flg_s, flg_d, flg_r;
4114:
4115: flg_s = (source[0]>>7) & 1;
4116: flg_d = (dest[0]>>7) & 1;
4117:
1.1 root 4118: /* Add source to dest: D = D+S */
1.1.1.2 root 4119: dest[2] += source[2];
4120: dest[1] += source[1]+((dest[2]>>24) & 1);
4121: dest[0] += source[0]+((dest[1]>>24) & 1);
1.1 root 4122:
1.1.1.5 root 4123: carry = (dest[0]>>8) & 1;
4124:
1.1 root 4125: dest[2] &= BITMASK(24);
4126: dest[1] &= BITMASK(24);
4127: dest[0] &= BITMASK(8);
4128:
1.1.1.4 root 4129: flg_r = (dest[0]>>7) & 1;
4130:
4131: /*set overflow*/
4132: overflow = (flg_s ^ flg_r) & (flg_d ^ flg_r);
4133:
1.1 root 4134: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4135: }
4136:
1.1.1.2 root 4137: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest)
1.1 root 4138: {
1.1.1.5 root 4139: Uint16 overflow, carry, flg_s, flg_d, flg_r, dest_save;
1.1.1.4 root 4140:
1.1.1.5 root 4141: dest_save = dest[0];
1.1 root 4142:
1.1.1.9 root 4143: /* Subtract source from dest: D = D-S */
1.1.1.2 root 4144: dest[2] -= source[2];
4145: dest[1] -= source[1]+((dest[2]>>24) & 1);
4146: dest[0] -= source[0]+((dest[1]>>24) & 1);
1.1 root 4147:
1.1.1.5 root 4148: carry = (dest[0]>>8) & 1;
4149:
1.1 root 4150: dest[2] &= BITMASK(24);
4151: dest[1] &= BITMASK(24);
4152: dest[0] &= BITMASK(8);
4153:
1.1.1.4 root 4154: flg_s = (source[0]>>7) & 1;
1.1.1.5 root 4155: flg_d = (dest_save>>7) & 1;
1.1.1.4 root 4156: flg_r = (dest[0]>>7) & 1;
4157:
4158: /* set overflow */
4159: overflow = (flg_s ^ flg_d) & (flg_r ^ flg_d);
4160:
1.1 root 4161: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4162: }
4163:
1.1.1.5 root 4164: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe)
1.1 root 4165: {
1.1.1.2 root 4166: Uint32 part[4], zerodest[3], value;
1.1 root 4167:
4168: /* Multiply: D = S1*S2 */
4169: if (source1 & (1<<23)) {
1.1.1.5 root 4170: signe ^= 1;
1.1.1.6 root 4171: source1 = (1<<24) - source1;
1.1 root 4172: }
4173: if (source2 & (1<<23)) {
1.1.1.5 root 4174: signe ^= 1;
1.1.1.6 root 4175: source2 = (1<<24) - source2;
1.1 root 4176: }
4177:
4178: /* bits 0-11 * bits 0-11 */
4179: part[0]=(source1 & BITMASK(12))*(source2 & BITMASK(12));
4180: /* bits 12-23 * bits 0-11 */
4181: part[1]=((source1>>12) & BITMASK(12))*(source2 & BITMASK(12));
4182: /* bits 0-11 * bits 12-23 */
4183: part[2]=(source1 & BITMASK(12))*((source2>>12) & BITMASK(12));
4184: /* bits 12-23 * bits 12-23 */
4185: part[3]=((source1>>12) & BITMASK(12))*((source2>>12) & BITMASK(12));
4186:
4187: /* Calc dest 2 */
4188: dest[2] = part[0];
4189: dest[2] += (part[1] & BITMASK(12)) << 12;
4190: dest[2] += (part[2] & BITMASK(12)) << 12;
4191:
4192: /* Calc dest 1 */
4193: dest[1] = (part[1]>>12) & BITMASK(12);
4194: dest[1] += (part[2]>>12) & BITMASK(12);
4195: dest[1] += part[3];
4196:
4197: /* Calc dest 0 */
4198: dest[0] = 0;
4199:
4200: /* Add carries */
4201: value = (dest[2]>>24) & BITMASK(8);
4202: if (value) {
4203: dest[1] += value;
4204: dest[2] &= BITMASK(24);
4205: }
4206: value = (dest[1]>>24) & BITMASK(8);
4207: if (value) {
4208: dest[0] += value;
4209: dest[1] &= BITMASK(24);
4210: }
4211:
4212: /* Get rid of extra sign bit */
4213: dsp_asl56(dest);
4214:
1.1.1.5 root 4215: if (signe) {
1.1 root 4216: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4217:
4218: dsp_sub56(dest, zerodest);
4219:
4220: dest[0] = zerodest[0];
4221: dest[1] = zerodest[1];
4222: dest[2] = zerodest[2];
4223: }
4224: }
4225:
1.1.1.2 root 4226: static void dsp_rnd56(Uint32 *dest)
1.1 root 4227: {
1.1.1.4 root 4228: Uint32 rnd_const[3];
1.1 root 4229:
1.1.1.4 root 4230: rnd_const[0] = 0;
1.1 root 4231:
1.1.1.4 root 4232: /* Scaling mode S0 */
1.1.1.6 root 4233: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S0)) {
1.1.1.4 root 4234: rnd_const[1] = 1;
4235: rnd_const[2] = 0;
4236: dsp_add56(rnd_const, dest);
4237:
4238: if ((dest[2]==0) && ((dest[1] & 1) == 0)) {
4239: dest[1] &= (0xffffff - 0x3);
4240: }
4241: dest[1] &= 0xfffffe;
4242: dest[2]=0;
4243: }
4244: /* Scaling mode S1 */
1.1.1.6 root 4245: else if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S1)) {
1.1.1.4 root 4246: rnd_const[1] = 0;
4247: rnd_const[2] = (1<<22);
4248: dsp_add56(rnd_const, dest);
4249:
4250: if ((dest[2] & 0x7fffff) == 0){
4251: dest[2] = 0;
4252: }
4253: dest[2] &= 0x800000;
4254: }
4255: /* No Scaling */
4256: else {
4257: rnd_const[1] = 0;
4258: rnd_const[2] = (1<<23);
4259: dsp_add56(rnd_const, dest);
4260:
4261: if (dest[2] == 0) {
4262: dest[1] &= 0xfffffe;
1.1 root 4263: }
1.1.1.4 root 4264: dest[2]=0;
1.1 root 4265: }
4266: }
4267:
4268: /**********************************
4269: * Parallel moves instructions
4270: **********************************/
4271:
1.1.1.6 root 4272: static void dsp_abs_a(void)
1.1 root 4273: {
1.1.1.6 root 4274: Uint32 dest[3], overflowed;
1.1 root 4275:
1.1.1.6 root 4276: dest[0] = dsp_core.registers[DSP_REG_A2];
4277: dest[1] = dsp_core.registers[DSP_REG_A1];
4278: dest[2] = dsp_core.registers[DSP_REG_A0];
4279:
4280: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4281:
4282: dsp_abs56(dest);
4283:
4284: dsp_core.registers[DSP_REG_A2] = dest[0];
4285: dsp_core.registers[DSP_REG_A1] = dest[1];
4286: dsp_core.registers[DSP_REG_A0] = dest[2];
4287:
4288: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4289: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
4290:
4291: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4292: }
4293:
4294: static void dsp_abs_b(void)
4295: {
4296: Uint32 dest[3], overflowed;
1.1 root 4297:
1.1.1.6 root 4298: dest[0] = dsp_core.registers[DSP_REG_B2];
4299: dest[1] = dsp_core.registers[DSP_REG_B1];
4300: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 4301:
4302: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4303:
4304: dsp_abs56(dest);
4305:
1.1.1.6 root 4306: dsp_core.registers[DSP_REG_B2] = dest[0];
4307: dsp_core.registers[DSP_REG_B1] = dest[1];
4308: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4309:
1.1.1.6 root 4310: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4311: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
1.1.1.2 root 4312:
1.1.1.6 root 4313: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4314: }
4315:
1.1.1.6 root 4316: static void dsp_adc_x_a(void)
1.1 root 4317: {
1.1.1.6 root 4318: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4319: Uint16 newsr;
1.1 root 4320:
1.1.1.6 root 4321: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4322:
1.1.1.6 root 4323: dest[0] = dsp_core.registers[DSP_REG_A2];
4324: dest[1] = dsp_core.registers[DSP_REG_A1];
4325: dest[2] = dsp_core.registers[DSP_REG_A0];
4326:
4327: source[2] = dsp_core.registers[DSP_REG_X0];
4328: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4329: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4330:
4331: newsr = dsp_add56(source, dest);
4332:
4333: if (curcarry) {
1.1.1.6 root 4334: source[0]=0; source[1]=0; source[2]=1;
1.1 root 4335: newsr |= dsp_add56(source, dest);
4336: }
4337:
1.1.1.6 root 4338: dsp_core.registers[DSP_REG_A2] = dest[0];
4339: dsp_core.registers[DSP_REG_A1] = dest[1];
4340: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4341:
1.1.1.6 root 4342: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4343:
1.1.1.6 root 4344: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4345: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4346: }
4347:
1.1.1.6 root 4348: static void dsp_adc_x_b(void)
1.1 root 4349: {
1.1.1.6 root 4350: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4351: Uint16 newsr;
1.1 root 4352:
1.1.1.6 root 4353: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
4354:
4355: dest[0] = dsp_core.registers[DSP_REG_B2];
4356: dest[1] = dsp_core.registers[DSP_REG_B1];
4357: dest[2] = dsp_core.registers[DSP_REG_B0];
4358:
4359: source[2] = dsp_core.registers[DSP_REG_X0];
4360: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4361: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4362:
4363: newsr = dsp_add56(source, dest);
1.1.1.6 root 4364:
4365: if (curcarry) {
4366: source[0]=0; source[1]=0; source[2]=1;
4367: newsr |= dsp_add56(source, dest);
4368: }
1.1 root 4369:
1.1.1.6 root 4370: dsp_core.registers[DSP_REG_B2] = dest[0];
4371: dsp_core.registers[DSP_REG_B1] = dest[1];
4372: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4373:
1.1.1.6 root 4374: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4375:
1.1.1.6 root 4376: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4377: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4378: }
4379:
1.1.1.6 root 4380: static void dsp_adc_y_a(void)
1.1 root 4381: {
1.1.1.6 root 4382: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4383: Uint16 newsr;
1.1 root 4384:
1.1.1.6 root 4385: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4386:
1.1.1.6 root 4387: dest[0] = dsp_core.registers[DSP_REG_A2];
4388: dest[1] = dsp_core.registers[DSP_REG_A1];
4389: dest[2] = dsp_core.registers[DSP_REG_A0];
4390:
4391: source[2] = dsp_core.registers[DSP_REG_Y0];
4392: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4393: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4394:
1.1.1.6 root 4395: newsr = dsp_add56(source, dest);
4396:
4397: if (curcarry) {
4398: source[0]=0; source[1]=0; source[2]=1;
4399: newsr |= dsp_add56(source, dest);
4400: }
1.1 root 4401:
1.1.1.6 root 4402: dsp_core.registers[DSP_REG_A2] = dest[0];
4403: dsp_core.registers[DSP_REG_A1] = dest[1];
4404: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4405:
1.1.1.6 root 4406: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4407:
1.1.1.6 root 4408: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4409: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4410: }
4411:
1.1.1.6 root 4412: static void dsp_adc_y_b(void)
1.1 root 4413: {
1.1.1.6 root 4414: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4415: Uint16 newsr;
1.1 root 4416:
1.1.1.6 root 4417: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4418:
1.1.1.6 root 4419: dest[0] = dsp_core.registers[DSP_REG_B2];
4420: dest[1] = dsp_core.registers[DSP_REG_B1];
4421: dest[2] = dsp_core.registers[DSP_REG_B0];
4422:
4423: source[2] = dsp_core.registers[DSP_REG_Y0];
4424: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4425: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4426:
1.1.1.6 root 4427: newsr = dsp_add56(source, dest);
4428:
4429: if (curcarry) {
4430: source[0]=0; source[1]=0; source[2]=1;
4431: newsr |= dsp_add56(source, dest);
4432: }
1.1 root 4433:
1.1.1.6 root 4434: dsp_core.registers[DSP_REG_B2] = dest[0];
4435: dsp_core.registers[DSP_REG_B1] = dest[1];
4436: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4437:
1.1.1.6 root 4438: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4439:
1.1.1.6 root 4440: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4441: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4442: }
4443:
1.1.1.6 root 4444: static void dsp_add_b_a(void)
1.1 root 4445: {
1.1.1.6 root 4446: Uint32 source[3], dest[3];
4447: Uint16 newsr;
1.1 root 4448:
1.1.1.6 root 4449: dest[0] = dsp_core.registers[DSP_REG_A2];
4450: dest[1] = dsp_core.registers[DSP_REG_A1];
4451: dest[2] = dsp_core.registers[DSP_REG_A0];
4452:
4453: source[0] = dsp_core.registers[DSP_REG_B2];
4454: source[1] = dsp_core.registers[DSP_REG_B1];
4455: source[2] = dsp_core.registers[DSP_REG_B0];
4456:
4457: newsr = dsp_add56(source, dest);
4458:
4459: dsp_core.registers[DSP_REG_A2] = dest[0];
4460: dsp_core.registers[DSP_REG_A1] = dest[1];
4461: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4462:
1.1.1.6 root 4463: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4464:
1.1.1.6 root 4465: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4466: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4467: }
4468:
1.1.1.6 root 4469: static void dsp_add_a_b(void)
1.1 root 4470: {
1.1.1.6 root 4471: Uint32 source[3], dest[3];
1.1.1.2 root 4472: Uint16 newsr;
1.1 root 4473:
1.1.1.6 root 4474: dest[0] = dsp_core.registers[DSP_REG_B2];
4475: dest[1] = dsp_core.registers[DSP_REG_B1];
4476: dest[2] = dsp_core.registers[DSP_REG_B0];
4477:
4478: source[0] = dsp_core.registers[DSP_REG_A2];
4479: source[1] = dsp_core.registers[DSP_REG_A1];
4480: source[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 4481:
1.1.1.6 root 4482: newsr = dsp_add56(source, dest);
1.1 root 4483:
1.1.1.6 root 4484: dsp_core.registers[DSP_REG_B2] = dest[0];
4485: dsp_core.registers[DSP_REG_B1] = dest[1];
4486: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4487:
1.1.1.6 root 4488: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4489:
1.1.1.6 root 4490: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4491: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4492: }
4493:
1.1.1.6 root 4494: static void dsp_add_x_a(void)
1.1 root 4495: {
1.1.1.6 root 4496: Uint32 source[3], dest[3];
4497: Uint16 newsr;
1.1 root 4498:
1.1.1.6 root 4499: dest[0] = dsp_core.registers[DSP_REG_A2];
4500: dest[1] = dsp_core.registers[DSP_REG_A1];
4501: dest[2] = dsp_core.registers[DSP_REG_A0];
4502:
4503: source[1] = dsp_core.registers[DSP_REG_X1];
4504: source[2] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4505: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4506:
1.1.1.6 root 4507: newsr = dsp_add56(source, dest);
1.1 root 4508:
1.1.1.6 root 4509: dsp_core.registers[DSP_REG_A2] = dest[0];
4510: dsp_core.registers[DSP_REG_A1] = dest[1];
4511: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4512:
1.1.1.6 root 4513: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4514:
1.1.1.6 root 4515: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4516: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4517: }
4518:
1.1.1.6 root 4519: static void dsp_add_x_b(void)
1.1 root 4520: {
1.1.1.6 root 4521: Uint32 source[3], dest[3];
4522: Uint16 newsr;
1.1 root 4523:
1.1.1.6 root 4524: dest[0] = dsp_core.registers[DSP_REG_B2];
4525: dest[1] = dsp_core.registers[DSP_REG_B1];
4526: dest[2] = dsp_core.registers[DSP_REG_B0];
4527:
4528: source[1] = dsp_core.registers[DSP_REG_X1];
4529: source[2] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4530: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4531:
4532: newsr = dsp_add56(source, dest);
1.1 root 4533:
1.1.1.6 root 4534: dsp_core.registers[DSP_REG_B2] = dest[0];
4535: dsp_core.registers[DSP_REG_B1] = dest[1];
4536: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4537:
1.1.1.6 root 4538: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4539:
4540: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4541: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4542: }
4543:
1.1.1.6 root 4544: static void dsp_add_y_a(void)
1.1 root 4545: {
1.1.1.6 root 4546: Uint32 source[3], dest[3];
1.1.1.2 root 4547: Uint16 newsr;
1.1 root 4548:
1.1.1.6 root 4549: dest[0] = dsp_core.registers[DSP_REG_A2];
4550: dest[1] = dsp_core.registers[DSP_REG_A1];
4551: dest[2] = dsp_core.registers[DSP_REG_A0];
4552:
4553: source[1] = dsp_core.registers[DSP_REG_Y1];
4554: source[2] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4555: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4556:
1.1.1.6 root 4557: newsr = dsp_add56(source, dest);
1.1 root 4558:
1.1.1.6 root 4559: dsp_core.registers[DSP_REG_A2] = dest[0];
4560: dsp_core.registers[DSP_REG_A1] = dest[1];
4561: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4562:
1.1.1.6 root 4563: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4564:
4565: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4566: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4567: }
4568:
1.1.1.6 root 4569: static void dsp_add_y_b(void)
1.1 root 4570: {
1.1.1.6 root 4571: Uint32 source[3], dest[3];
1.1.1.2 root 4572: Uint16 newsr;
1.1 root 4573:
1.1.1.6 root 4574: dest[0] = dsp_core.registers[DSP_REG_B2];
4575: dest[1] = dsp_core.registers[DSP_REG_B1];
4576: dest[2] = dsp_core.registers[DSP_REG_B0];
4577:
4578: source[1] = dsp_core.registers[DSP_REG_Y1];
4579: source[2] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4580: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4581:
1.1.1.6 root 4582: newsr = dsp_add56(source, dest);
1.1 root 4583:
1.1.1.6 root 4584: dsp_core.registers[DSP_REG_B2] = dest[0];
4585: dsp_core.registers[DSP_REG_B1] = dest[1];
4586: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4587:
1.1.1.6 root 4588: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4589:
1.1.1.6 root 4590: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4591: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4592: }
4593:
1.1.1.6 root 4594: static void dsp_add_x0_a(void)
1.1 root 4595: {
1.1.1.6 root 4596: Uint32 source[3], dest[3];
4597: Uint16 newsr;
1.1 root 4598:
1.1.1.6 root 4599: dest[0] = dsp_core.registers[DSP_REG_A2];
4600: dest[1] = dsp_core.registers[DSP_REG_A1];
4601: dest[2] = dsp_core.registers[DSP_REG_A0];
4602:
4603: source[2] = 0;
4604: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4605: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4606:
4607: newsr = dsp_add56(source, dest);
4608:
4609: dsp_core.registers[DSP_REG_A2] = dest[0];
4610: dsp_core.registers[DSP_REG_A1] = dest[1];
4611: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4612:
1.1.1.6 root 4613: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4614:
1.1.1.6 root 4615: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4616: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4617: }
4618:
1.1.1.6 root 4619: static void dsp_add_x0_b(void)
1.1 root 4620: {
1.1.1.6 root 4621: Uint32 source[3], dest[3];
4622: Uint16 newsr;
4623:
4624: dest[0] = dsp_core.registers[DSP_REG_B2];
4625: dest[1] = dsp_core.registers[DSP_REG_B1];
4626: dest[2] = dsp_core.registers[DSP_REG_B0];
4627:
4628: source[2] = 0;
4629: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4630: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4631:
1.1.1.6 root 4632: newsr = dsp_add56(source, dest);
1.1 root 4633:
1.1.1.6 root 4634: dsp_core.registers[DSP_REG_B2] = dest[0];
4635: dsp_core.registers[DSP_REG_B1] = dest[1];
4636: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4637:
1.1.1.6 root 4638: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4639:
1.1.1.6 root 4640: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4641: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4642: }
4643:
1.1.1.6 root 4644: static void dsp_add_y0_a(void)
1.1 root 4645: {
1.1.1.6 root 4646: Uint32 source[3], dest[3];
4647: Uint16 newsr;
1.1 root 4648:
1.1.1.6 root 4649: dest[0] = dsp_core.registers[DSP_REG_A2];
4650: dest[1] = dsp_core.registers[DSP_REG_A1];
4651: dest[2] = dsp_core.registers[DSP_REG_A0];
4652:
4653: source[2] = 0;
4654: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4655: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4656:
1.1.1.6 root 4657: newsr = dsp_add56(source, dest);
4658:
4659: dsp_core.registers[DSP_REG_A2] = dest[0];
4660: dsp_core.registers[DSP_REG_A1] = dest[1];
4661: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4662:
1.1.1.6 root 4663: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4664:
1.1.1.6 root 4665: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4666: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4667: }
4668:
1.1.1.6 root 4669: static void dsp_add_y0_b(void)
1.1 root 4670: {
1.1.1.6 root 4671: Uint32 source[3], dest[3];
1.1.1.2 root 4672: Uint16 newsr;
1.1 root 4673:
1.1.1.6 root 4674: dest[0] = dsp_core.registers[DSP_REG_B2];
4675: dest[1] = dsp_core.registers[DSP_REG_B1];
4676: dest[2] = dsp_core.registers[DSP_REG_B0];
4677:
4678: source[2] = 0;
4679: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4680: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4681:
4682: newsr = dsp_add56(source, dest);
4683:
1.1.1.6 root 4684: dsp_core.registers[DSP_REG_B2] = dest[0];
4685: dsp_core.registers[DSP_REG_B1] = dest[1];
4686: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4687:
1.1.1.6 root 4688: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4689:
1.1.1.6 root 4690: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4691: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4692: }
4693:
1.1.1.6 root 4694: static void dsp_add_x1_a(void)
1.1 root 4695: {
1.1.1.6 root 4696: Uint32 source[3], dest[3];
1.1.1.2 root 4697: Uint16 newsr;
1.1 root 4698:
1.1.1.6 root 4699: dest[0] = dsp_core.registers[DSP_REG_A2];
4700: dest[1] = dsp_core.registers[DSP_REG_A1];
4701: dest[2] = dsp_core.registers[DSP_REG_A0];
4702:
4703: source[2] = 0;
4704: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4705: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4706:
4707: newsr = dsp_add56(source, dest);
4708:
1.1.1.6 root 4709: dsp_core.registers[DSP_REG_A2] = dest[0];
4710: dsp_core.registers[DSP_REG_A1] = dest[1];
4711: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4712:
1.1.1.6 root 4713: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4714:
1.1.1.6 root 4715: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4716: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4717: }
4718:
1.1.1.6 root 4719: static void dsp_add_x1_b(void)
1.1 root 4720: {
1.1.1.6 root 4721: Uint32 source[3], dest[3];
4722: Uint16 newsr;
4723:
4724: dest[0] = dsp_core.registers[DSP_REG_B2];
4725: dest[1] = dsp_core.registers[DSP_REG_B1];
4726: dest[2] = dsp_core.registers[DSP_REG_B0];
4727:
4728: source[2] = 0;
4729: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4730: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4731:
4732: newsr = dsp_add56(source, dest);
4733:
4734: dsp_core.registers[DSP_REG_B2] = dest[0];
4735: dsp_core.registers[DSP_REG_B1] = dest[1];
4736: dsp_core.registers[DSP_REG_B0] = dest[2];
4737:
4738: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4739:
4740: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4741: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4742: }
4743:
1.1.1.6 root 4744: static void dsp_add_y1_a(void)
1.1 root 4745: {
1.1.1.6 root 4746: Uint32 source[3], dest[3];
4747: Uint16 newsr;
1.1 root 4748:
1.1.1.6 root 4749: dest[0] = dsp_core.registers[DSP_REG_A2];
4750: dest[1] = dsp_core.registers[DSP_REG_A1];
4751: dest[2] = dsp_core.registers[DSP_REG_A0];
4752:
4753: source[2] = 0;
4754: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4755: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4756:
1.1.1.6 root 4757: newsr = dsp_add56(source, dest);
1.1 root 4758:
1.1.1.6 root 4759: dsp_core.registers[DSP_REG_A2] = dest[0];
4760: dsp_core.registers[DSP_REG_A1] = dest[1];
4761: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4762:
1.1.1.6 root 4763: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4764:
1.1.1.6 root 4765: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4766: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4767: }
4768:
1.1.1.6 root 4769: static void dsp_add_y1_b(void)
1.1 root 4770: {
1.1.1.6 root 4771: Uint32 source[3], dest[3];
4772: Uint16 newsr;
1.1 root 4773:
1.1.1.6 root 4774: dest[0] = dsp_core.registers[DSP_REG_B2];
4775: dest[1] = dsp_core.registers[DSP_REG_B1];
4776: dest[2] = dsp_core.registers[DSP_REG_B0];
4777:
4778: source[2] = 0;
4779: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4780: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4781:
1.1.1.6 root 4782: newsr = dsp_add56(source, dest);
1.1 root 4783:
1.1.1.6 root 4784: dsp_core.registers[DSP_REG_B2] = dest[0];
4785: dsp_core.registers[DSP_REG_B1] = dest[1];
4786: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4787:
1.1.1.6 root 4788: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4789:
1.1.1.6 root 4790: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4791: dsp_core.registers[DSP_REG_SR] |= newsr;
4792: }
1.1 root 4793:
1.1.1.6 root 4794: static void dsp_addl_b_a(void)
4795: {
4796: Uint32 source[3], dest[3];
4797: Uint16 newsr;
1.1.1.2 root 4798:
1.1.1.6 root 4799: dest[0] = dsp_core.registers[DSP_REG_A2];
4800: dest[1] = dsp_core.registers[DSP_REG_A1];
4801: dest[2] = dsp_core.registers[DSP_REG_A0];
4802: newsr = dsp_asl56(dest);
1.1 root 4803:
1.1.1.6 root 4804: source[0] = dsp_core.registers[DSP_REG_B2];
4805: source[1] = dsp_core.registers[DSP_REG_B1];
4806: source[2] = dsp_core.registers[DSP_REG_B0];
4807: newsr |= dsp_add56(source, dest);
1.1 root 4808:
1.1.1.6 root 4809: dsp_core.registers[DSP_REG_A2] = dest[0];
4810: dsp_core.registers[DSP_REG_A1] = dest[1];
4811: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4812:
1.1.1.6 root 4813: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4814:
1.1.1.6 root 4815: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4816: dsp_core.registers[DSP_REG_SR] |= newsr;
4817: }
1.1 root 4818:
1.1.1.6 root 4819: static void dsp_addl_a_b(void)
4820: {
4821: Uint32 source[3], dest[3];
4822: Uint16 newsr;
1.1 root 4823:
1.1.1.6 root 4824: dest[0] = dsp_core.registers[DSP_REG_B2];
4825: dest[1] = dsp_core.registers[DSP_REG_B1];
4826: dest[2] = dsp_core.registers[DSP_REG_B0];
4827: newsr = dsp_asl56(dest);
1.1 root 4828:
1.1.1.6 root 4829: source[0] = dsp_core.registers[DSP_REG_A2];
4830: source[1] = dsp_core.registers[DSP_REG_A1];
4831: source[2] = dsp_core.registers[DSP_REG_A0];
4832: newsr |= dsp_add56(source, dest);
4833:
4834: dsp_core.registers[DSP_REG_B2] = dest[0];
4835: dsp_core.registers[DSP_REG_B1] = dest[1];
4836: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4837:
1.1.1.6 root 4838: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4839:
1.1.1.6 root 4840: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4841: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4842: }
4843:
1.1.1.6 root 4844: static void dsp_addr_b_a(void)
1.1 root 4845: {
1.1.1.6 root 4846: Uint32 source[3], dest[3];
4847: Uint16 newsr;
4848:
4849: dest[0] = dsp_core.registers[DSP_REG_A2];
4850: dest[1] = dsp_core.registers[DSP_REG_A1];
4851: dest[2] = dsp_core.registers[DSP_REG_A0];
4852: newsr = dsp_asr56(dest);
4853:
4854: source[0] = dsp_core.registers[DSP_REG_B2];
4855: source[1] = dsp_core.registers[DSP_REG_B1];
4856: source[2] = dsp_core.registers[DSP_REG_B0];
4857: newsr |= dsp_add56(source, dest);
4858:
4859: dsp_core.registers[DSP_REG_A2] = dest[0];
4860: dsp_core.registers[DSP_REG_A1] = dest[1];
4861: dsp_core.registers[DSP_REG_A0] = dest[2];
4862:
4863: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4864:
4865: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4866: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4867: }
4868:
1.1.1.6 root 4869: static void dsp_addr_a_b(void)
1.1 root 4870: {
1.1.1.6 root 4871: Uint32 source[3], dest[3];
4872: Uint16 newsr;
4873:
4874: dest[0] = dsp_core.registers[DSP_REG_B2];
4875: dest[1] = dsp_core.registers[DSP_REG_B1];
4876: dest[2] = dsp_core.registers[DSP_REG_B0];
4877: newsr = dsp_asr56(dest);
4878:
4879: source[0] = dsp_core.registers[DSP_REG_A2];
4880: source[1] = dsp_core.registers[DSP_REG_A1];
4881: source[2] = dsp_core.registers[DSP_REG_A0];
4882: newsr |= dsp_add56(source, dest);
1.1 root 4883:
1.1.1.6 root 4884: dsp_core.registers[DSP_REG_B2] = dest[0];
4885: dsp_core.registers[DSP_REG_B1] = dest[1];
4886: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4887:
1.1.1.6 root 4888: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4889:
1.1.1.6 root 4890: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4891: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4892: }
4893:
1.1.1.6 root 4894: static void dsp_and_x0_a(void)
1.1 root 4895: {
1.1.1.6 root 4896: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X0];
1.1 root 4897:
1.1.1.6 root 4898: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4899: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4900: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4901: }
1.1 root 4902:
1.1.1.6 root 4903: static void dsp_and_x0_b(void)
4904: {
4905: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X0];
1.1 root 4906:
1.1.1.6 root 4907: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4908: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4909: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
1.1 root 4910: }
4911:
1.1.1.6 root 4912: static void dsp_and_y0_a(void)
1.1 root 4913: {
1.1.1.6 root 4914: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y0];
1.1 root 4915:
1.1.1.6 root 4916: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4917: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4918: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4919: }
1.1 root 4920:
1.1.1.6 root 4921: static void dsp_and_y0_b(void)
4922: {
4923: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y0];
1.1 root 4924:
1.1.1.6 root 4925: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4926: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4927: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
4928: }
1.1 root 4929:
1.1.1.6 root 4930: static void dsp_and_x1_a(void)
4931: {
4932: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X1];
1.1.1.2 root 4933:
1.1.1.6 root 4934: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4935: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4936: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
1.1 root 4937: }
4938:
1.1.1.6 root 4939: static void dsp_and_x1_b(void)
1.1 root 4940: {
1.1.1.6 root 4941: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X1];
4942:
4943: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4944: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4945: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
4946: }
1.1 root 4947:
1.1.1.6 root 4948: static void dsp_and_y1_a(void)
4949: {
4950: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y1];
1.1 root 4951:
1.1.1.6 root 4952: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4953: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4954: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4955: }
1.1 root 4956:
1.1.1.6 root 4957: static void dsp_and_y1_b(void)
4958: {
4959: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y1];
1.1.1.2 root 4960:
1.1.1.6 root 4961: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4962: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4963: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
1.1 root 4964: }
4965:
1.1.1.7 root 4966: static void dsp_asl_a(void)
1.1 root 4967: {
1.1.1.6 root 4968: Uint32 dest[3];
4969: Uint16 newsr;
1.1 root 4970:
1.1.1.6 root 4971: dest[0] = dsp_core.registers[DSP_REG_A2];
4972: dest[1] = dsp_core.registers[DSP_REG_A1];
4973: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 4974:
1.1.1.6 root 4975: newsr = dsp_asl56(dest);
4976:
4977: dsp_core.registers[DSP_REG_A2] = dest[0];
4978: dsp_core.registers[DSP_REG_A1] = dest[1];
4979: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4980:
1.1.1.6 root 4981: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
4982: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1.1.2 root 4983:
1.1.1.6 root 4984: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4985: }
4986:
1.1.1.7 root 4987: static void dsp_asl_b(void)
1.1 root 4988: {
1.1.1.6 root 4989: Uint32 dest[3];
1.1.1.2 root 4990: Uint16 newsr;
1.1 root 4991:
1.1.1.6 root 4992: dest[0] = dsp_core.registers[DSP_REG_B2];
4993: dest[1] = dsp_core.registers[DSP_REG_B1];
4994: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 4995:
1.1.1.6 root 4996: newsr = dsp_asl56(dest);
1.1 root 4997:
1.1.1.6 root 4998: dsp_core.registers[DSP_REG_B2] = dest[0];
4999: dsp_core.registers[DSP_REG_B1] = dest[1];
5000: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 5001:
1.1.1.6 root 5002: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5003: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 5004:
1.1.1.6 root 5005: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 5006: }
5007:
1.1.1.7 root 5008: static void dsp_asr_a(void)
1.1 root 5009: {
1.1.1.6 root 5010: Uint32 dest[3];
5011: Uint16 newsr;
5012:
5013: dest[0] = dsp_core.registers[DSP_REG_A2];
5014: dest[1] = dsp_core.registers[DSP_REG_A1];
5015: dest[2] = dsp_core.registers[DSP_REG_A0];
5016:
5017: newsr = dsp_asr56(dest);
5018:
5019: dsp_core.registers[DSP_REG_A2] = dest[0];
5020: dsp_core.registers[DSP_REG_A1] = dest[1];
5021: dsp_core.registers[DSP_REG_A0] = dest[2];
5022:
5023: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5024: dsp_core.registers[DSP_REG_SR] |= newsr;
5025:
5026: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5027: }
5028:
1.1.1.7 root 5029: static void dsp_asr_b(void)
1.1.1.6 root 5030: {
5031: Uint32 dest[3];
5032: Uint16 newsr;
5033:
5034: dest[0] = dsp_core.registers[DSP_REG_B2];
5035: dest[1] = dsp_core.registers[DSP_REG_B1];
5036: dest[2] = dsp_core.registers[DSP_REG_B0];
5037:
5038: newsr = dsp_asr56(dest);
5039:
5040: dsp_core.registers[DSP_REG_B2] = dest[0];
5041: dsp_core.registers[DSP_REG_B1] = dest[1];
5042: dsp_core.registers[DSP_REG_B0] = dest[2];
5043:
5044: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5045: dsp_core.registers[DSP_REG_SR] |= newsr;
5046:
5047: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5048: }
5049:
5050: static void dsp_clr_a(void)
5051: {
1.1.1.7 root 5052: dsp_core.registers[DSP_REG_A2] = 0;
5053: dsp_core.registers[DSP_REG_A1] = 0;
5054: dsp_core.registers[DSP_REG_A0] = 0;
1.1.1.6 root 5055:
5056: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5057: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5058: }
5059:
5060: static void dsp_clr_b(void)
5061: {
1.1.1.7 root 5062: dsp_core.registers[DSP_REG_B2] = 0;
5063: dsp_core.registers[DSP_REG_B1] = 0;
5064: dsp_core.registers[DSP_REG_B0] = 0;
1.1.1.6 root 5065:
5066: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5067: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5068: }
5069:
5070: static void dsp_cmp_b_a(void)
5071: {
5072: Uint32 source[3], dest[3];
5073: Uint16 newsr;
5074:
5075: dest[0] = dsp_core.registers[DSP_REG_A2];
5076: dest[1] = dsp_core.registers[DSP_REG_A1];
5077: dest[2] = dsp_core.registers[DSP_REG_A0];
5078:
5079: source[0] = dsp_core.registers[DSP_REG_B2];
5080: source[1] = dsp_core.registers[DSP_REG_B1];
5081: source[2] = dsp_core.registers[DSP_REG_B0];
5082:
5083: newsr = dsp_sub56(source, dest);
5084:
5085: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5086:
5087: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5088: dsp_core.registers[DSP_REG_SR] |= newsr;
5089: }
5090:
5091: static void dsp_cmp_a_b(void)
5092: {
5093: Uint32 source[3], dest[3];
5094: Uint16 newsr;
5095:
5096: dest[0] = dsp_core.registers[DSP_REG_B2];
5097: dest[1] = dsp_core.registers[DSP_REG_B1];
5098: dest[2] = dsp_core.registers[DSP_REG_B0];
5099:
5100: source[0] = dsp_core.registers[DSP_REG_A2];
5101: source[1] = dsp_core.registers[DSP_REG_A1];
5102: source[2] = dsp_core.registers[DSP_REG_A0];
5103:
5104: newsr = dsp_sub56(source, dest);
5105:
5106: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5107:
5108: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5109: dsp_core.registers[DSP_REG_SR] |= newsr;
5110: }
5111:
5112: static void dsp_cmp_x0_a(void)
5113: {
5114: Uint32 source[3], dest[3];
5115: Uint16 newsr;
5116:
5117: dest[2] = dsp_core.registers[DSP_REG_A0];
5118: dest[1] = dsp_core.registers[DSP_REG_A1];
5119: dest[0] = dsp_core.registers[DSP_REG_A2];
5120:
5121: source[2] = 0;
5122: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5123: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5124:
5125: newsr = dsp_sub56(source, dest);
5126:
5127: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5128:
5129: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5130: dsp_core.registers[DSP_REG_SR] |= newsr;
5131: }
5132:
5133: static void dsp_cmp_x0_b(void)
5134: {
5135: Uint32 source[3], dest[3];
5136: Uint16 newsr;
5137:
5138: dest[0] = dsp_core.registers[DSP_REG_B2];
5139: dest[1] = dsp_core.registers[DSP_REG_B1];
5140: dest[2] = dsp_core.registers[DSP_REG_B0];
5141:
5142: source[2] = 0;
5143: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5144: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5145:
5146: newsr = dsp_sub56(source, dest);
5147:
5148: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5149:
5150: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5151: dsp_core.registers[DSP_REG_SR] |= newsr;
5152: }
5153:
5154: static void dsp_cmp_y0_a(void)
5155: {
5156: Uint32 source[3], dest[3];
5157: Uint16 newsr;
5158:
5159: dest[2] = dsp_core.registers[DSP_REG_A0];
5160: dest[1] = dsp_core.registers[DSP_REG_A1];
5161: dest[0] = dsp_core.registers[DSP_REG_A2];
5162:
5163: source[2] = 0;
5164: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5165: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5166:
5167: newsr = dsp_sub56(source, dest);
5168:
5169: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5170:
5171: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5172: dsp_core.registers[DSP_REG_SR] |= newsr;
5173: }
5174:
5175: static void dsp_cmp_y0_b(void)
5176: {
5177: Uint32 source[3], dest[3];
5178: Uint16 newsr;
5179:
5180: dest[0] = dsp_core.registers[DSP_REG_B2];
5181: dest[1] = dsp_core.registers[DSP_REG_B1];
5182: dest[2] = dsp_core.registers[DSP_REG_B0];
5183:
5184: source[2] = 0;
5185: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5186: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5187:
5188: newsr = dsp_sub56(source, dest);
5189:
5190: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5191:
5192: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5193: dsp_core.registers[DSP_REG_SR] |= newsr;
5194: }
5195: static void dsp_cmp_x1_a(void)
5196: {
5197: Uint32 source[3], dest[3];
5198: Uint16 newsr;
5199:
5200: dest[2] = dsp_core.registers[DSP_REG_A0];
5201: dest[1] = dsp_core.registers[DSP_REG_A1];
5202: dest[0] = dsp_core.registers[DSP_REG_A2];
5203:
5204: source[2] = 0;
5205: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5206: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5207:
5208: newsr = dsp_sub56(source, dest);
5209:
5210: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5211:
5212: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5213: dsp_core.registers[DSP_REG_SR] |= newsr;
5214: }
5215:
5216: static void dsp_cmp_x1_b(void)
5217: {
5218: Uint32 source[3], dest[3];
5219: Uint16 newsr;
5220:
5221: dest[0] = dsp_core.registers[DSP_REG_B2];
5222: dest[1] = dsp_core.registers[DSP_REG_B1];
5223: dest[2] = dsp_core.registers[DSP_REG_B0];
5224:
5225: source[2] = 0;
5226: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5227: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5228:
5229: newsr = dsp_sub56(source, dest);
5230:
5231: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5232:
5233: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5234: dsp_core.registers[DSP_REG_SR] |= newsr;
5235: }
5236:
5237: static void dsp_cmp_y1_a(void)
5238: {
5239: Uint32 source[3], dest[3];
5240: Uint16 newsr;
5241:
5242: dest[2] = dsp_core.registers[DSP_REG_A0];
5243: dest[1] = dsp_core.registers[DSP_REG_A1];
5244: dest[0] = dsp_core.registers[DSP_REG_A2];
5245:
5246: source[2] = 0;
5247: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5248: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5249:
5250: newsr = dsp_sub56(source, dest);
5251:
5252: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5253:
5254: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5255: dsp_core.registers[DSP_REG_SR] |= newsr;
5256: }
5257:
5258: static void dsp_cmp_y1_b(void)
5259: {
5260: Uint32 source[3], dest[3];
5261: Uint16 newsr;
5262:
5263: dest[0] = dsp_core.registers[DSP_REG_B2];
5264: dest[1] = dsp_core.registers[DSP_REG_B1];
5265: dest[2] = dsp_core.registers[DSP_REG_B0];
5266:
5267: source[2] = 0;
5268: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5269: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5270:
5271: newsr = dsp_sub56(source, dest);
5272:
5273: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5274:
5275: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5276: dsp_core.registers[DSP_REG_SR] |= newsr;
5277: }
5278:
5279: static void dsp_cmpm_b_a(void)
5280: {
5281: Uint32 source[3], dest[3];
5282: Uint16 newsr;
5283:
5284: dest[0] = dsp_core.registers[DSP_REG_A2];
5285: dest[1] = dsp_core.registers[DSP_REG_A1];
5286: dest[2] = dsp_core.registers[DSP_REG_A0];
5287: dsp_abs56(dest);
5288:
5289: source[0] = dsp_core.registers[DSP_REG_B2];
5290: source[1] = dsp_core.registers[DSP_REG_B1];
5291: source[2] = dsp_core.registers[DSP_REG_B0];
5292: dsp_abs56(source);
5293:
5294: newsr = dsp_sub56(source, dest);
5295:
5296: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5297:
5298: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5299: dsp_core.registers[DSP_REG_SR] |= newsr;
5300: }
5301:
5302: static void dsp_cmpm_a_b(void)
5303: {
5304: Uint32 source[3], dest[3];
5305: Uint16 newsr;
5306:
5307: dest[0] = dsp_core.registers[DSP_REG_B2];
5308: dest[1] = dsp_core.registers[DSP_REG_B1];
5309: dest[2] = dsp_core.registers[DSP_REG_B0];
5310: dsp_abs56(dest);
5311:
5312: source[0] = dsp_core.registers[DSP_REG_A2];
5313: source[1] = dsp_core.registers[DSP_REG_A1];
5314: source[2] = dsp_core.registers[DSP_REG_A0];
5315: dsp_abs56(source);
5316:
5317: newsr = dsp_sub56(source, dest);
5318:
5319: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5320:
5321: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5322: dsp_core.registers[DSP_REG_SR] |= newsr;
5323: }
5324:
5325: static void dsp_cmpm_x0_a(void)
5326: {
5327: Uint32 source[3], dest[3];
5328: Uint16 newsr;
5329:
5330: dest[2] = dsp_core.registers[DSP_REG_A0];
5331: dest[1] = dsp_core.registers[DSP_REG_A1];
5332: dest[0] = dsp_core.registers[DSP_REG_A2];
5333: dsp_abs56(dest);
5334:
5335: source[2] = 0;
5336: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5337: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5338: dsp_abs56(source);
5339:
5340: newsr = dsp_sub56(source, dest);
5341:
5342: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5343:
5344: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5345: dsp_core.registers[DSP_REG_SR] |= newsr;
5346: }
5347:
5348: static void dsp_cmpm_x0_b(void)
5349: {
5350: Uint32 source[3], dest[3];
5351: Uint16 newsr;
5352:
5353: dest[0] = dsp_core.registers[DSP_REG_B2];
5354: dest[1] = dsp_core.registers[DSP_REG_B1];
5355: dest[2] = dsp_core.registers[DSP_REG_B0];
5356: dsp_abs56(dest);
5357:
5358: source[2] = 0;
5359: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5360: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5361: dsp_abs56(source);
5362:
5363: newsr = dsp_sub56(source, dest);
5364:
5365: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5366:
5367: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5368: dsp_core.registers[DSP_REG_SR] |= newsr;
5369: }
5370:
5371: static void dsp_cmpm_y0_a(void)
5372: {
5373: Uint32 source[3], dest[3];
5374: Uint16 newsr;
5375:
5376: dest[2] = dsp_core.registers[DSP_REG_A0];
5377: dest[1] = dsp_core.registers[DSP_REG_A1];
5378: dest[0] = dsp_core.registers[DSP_REG_A2];
5379: dsp_abs56(dest);
5380:
5381: source[2] = 0;
5382: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5383: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5384: dsp_abs56(source);
5385:
5386: newsr = dsp_sub56(source, dest);
5387:
5388: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5389:
5390: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5391: dsp_core.registers[DSP_REG_SR] |= newsr;
5392: }
5393:
5394: static void dsp_cmpm_y0_b(void)
5395: {
5396: Uint32 source[3], dest[3];
5397: Uint16 newsr;
5398:
5399: dest[0] = dsp_core.registers[DSP_REG_B2];
5400: dest[1] = dsp_core.registers[DSP_REG_B1];
5401: dest[2] = dsp_core.registers[DSP_REG_B0];
5402: dsp_abs56(dest);
5403:
5404: source[2] = 0;
5405: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5406: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5407: dsp_abs56(source);
5408:
5409: newsr = dsp_sub56(source, dest);
5410:
5411: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5412:
5413: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5414: dsp_core.registers[DSP_REG_SR] |= newsr;
5415: }
5416:
5417: static void dsp_cmpm_x1_a(void)
5418: {
5419: Uint32 source[3], dest[3];
5420: Uint16 newsr;
5421:
5422: dest[2] = dsp_core.registers[DSP_REG_A0];
5423: dest[1] = dsp_core.registers[DSP_REG_A1];
5424: dest[0] = dsp_core.registers[DSP_REG_A2];
5425: dsp_abs56(dest);
5426:
5427: source[2] = 0;
5428: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5429: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5430: dsp_abs56(source);
5431:
5432: newsr = dsp_sub56(source, dest);
5433:
5434: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5435:
5436: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5437: dsp_core.registers[DSP_REG_SR] |= newsr;
5438: }
5439:
5440: static void dsp_cmpm_x1_b(void)
5441: {
5442: Uint32 source[3], dest[3];
5443: Uint16 newsr;
5444:
5445: dest[0] = dsp_core.registers[DSP_REG_B2];
5446: dest[1] = dsp_core.registers[DSP_REG_B1];
5447: dest[2] = dsp_core.registers[DSP_REG_B0];
5448: dsp_abs56(dest);
5449:
5450: source[2] = 0;
5451: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5452: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5453: dsp_abs56(source);
5454:
5455: newsr = dsp_sub56(source, dest);
5456:
5457: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5458:
5459: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5460: dsp_core.registers[DSP_REG_SR] |= newsr;
5461: }
5462:
5463: static void dsp_cmpm_y1_a(void)
5464: {
5465: Uint32 source[3], dest[3];
5466: Uint16 newsr;
5467:
5468: dest[2] = dsp_core.registers[DSP_REG_A0];
5469: dest[1] = dsp_core.registers[DSP_REG_A1];
5470: dest[0] = dsp_core.registers[DSP_REG_A2];
5471: dsp_abs56(dest);
5472:
5473: source[2] = 0;
5474: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5475: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5476: dsp_abs56(source);
5477:
5478: newsr = dsp_sub56(source, dest);
5479:
5480: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5481:
5482: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5483: dsp_core.registers[DSP_REG_SR] |= newsr;
5484: }
5485:
5486: static void dsp_cmpm_y1_b(void)
5487: {
5488: Uint32 source[3], dest[3];
5489: Uint16 newsr;
5490:
5491: dest[0] = dsp_core.registers[DSP_REG_B2];
5492: dest[1] = dsp_core.registers[DSP_REG_B1];
5493: dest[2] = dsp_core.registers[DSP_REG_B0];
5494: dsp_abs56(dest);
5495:
5496: source[2] = 0;
5497: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5498: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5499: dsp_abs56(source);
5500:
5501: newsr = dsp_sub56(source, dest);
5502:
5503: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5504:
5505: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5506: dsp_core.registers[DSP_REG_SR] |= newsr;
5507: }
5508:
5509: static void dsp_eor_x0_a(void)
5510: {
5511: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X0];
5512: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5513:
5514: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5515: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5516: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5517: }
5518:
5519: static void dsp_eor_x0_b(void)
5520: {
5521: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X0];
5522: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5523:
5524: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5525: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5526: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5527: }
5528:
5529: static void dsp_eor_y0_a(void)
5530: {
5531: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y0];
5532: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5533:
5534: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5535: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5536: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5537: }
5538:
5539: static void dsp_eor_y0_b(void)
5540: {
5541: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y0];
5542: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5543:
5544: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5545: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5546: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5547: }
5548:
5549: static void dsp_eor_x1_a(void)
5550: {
5551: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X1];
5552: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5553:
5554: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5555: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5556: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5557: }
5558:
5559: static void dsp_eor_x1_b(void)
5560: {
5561: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X1];
5562: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5563:
5564: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5565: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5566: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5567: }
5568:
5569: static void dsp_eor_y1_a(void)
5570: {
5571: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y1];
5572: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5573:
5574: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5575: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5576: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5577: }
5578:
5579: static void dsp_eor_y1_b(void)
5580: {
5581: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y1];
5582: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5583:
5584: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5585: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5586: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5587: }
5588:
5589: static void dsp_lsl_a(void)
5590: {
5591: Uint32 newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
5592:
5593: dsp_core.registers[DSP_REG_A1] <<= 1;
5594: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
5595:
5596: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5597: dsp_core.registers[DSP_REG_SR] |= newcarry;
5598: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5599: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5600: }
5601:
5602: static void dsp_lsl_b(void)
5603: {
5604: Uint32 newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
5605:
5606: dsp_core.registers[DSP_REG_B1] <<= 1;
5607: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
5608:
5609: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5610: dsp_core.registers[DSP_REG_SR] |= newcarry;
5611: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5612: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5613: }
5614:
5615: static void dsp_lsr_a(void)
5616: {
5617: Uint32 newcarry = dsp_core.registers[DSP_REG_A1] & 1;
5618: dsp_core.registers[DSP_REG_A1] >>= 1;
5619:
5620: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5621: dsp_core.registers[DSP_REG_SR] |= newcarry;
5622: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5623: }
5624:
5625: static void dsp_lsr_b(void)
5626: {
5627: Uint32 newcarry = dsp_core.registers[DSP_REG_B1] & 1;
5628: dsp_core.registers[DSP_REG_B1] >>= 1;
5629:
5630: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5631: dsp_core.registers[DSP_REG_SR] |= newcarry;
5632: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5633: }
5634:
5635: static void dsp_mac_p_x0_x0_a(void)
5636: {
5637: Uint32 source[3], dest[3];
5638: Uint16 newsr;
5639:
5640: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5641:
5642: dest[0] = dsp_core.registers[DSP_REG_A2];
5643: dest[1] = dsp_core.registers[DSP_REG_A1];
5644: dest[2] = dsp_core.registers[DSP_REG_A0];
5645: newsr = dsp_add56(source, dest);
5646:
5647: dsp_core.registers[DSP_REG_A2] = dest[0];
5648: dsp_core.registers[DSP_REG_A1] = dest[1];
5649: dsp_core.registers[DSP_REG_A0] = dest[2];
5650:
5651: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5652:
5653: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5654: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5655: }
5656:
5657: static void dsp_mac_m_x0_x0_a(void)
5658: {
5659: Uint32 source[3], dest[3];
5660: Uint16 newsr;
5661:
5662: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5663:
5664: dest[0] = dsp_core.registers[DSP_REG_A2];
5665: dest[1] = dsp_core.registers[DSP_REG_A1];
5666: dest[2] = dsp_core.registers[DSP_REG_A0];
5667: newsr = dsp_add56(source, dest);
5668:
5669: dsp_core.registers[DSP_REG_A2] = dest[0];
5670: dsp_core.registers[DSP_REG_A1] = dest[1];
5671: dsp_core.registers[DSP_REG_A0] = dest[2];
5672:
5673: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5674:
5675: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5676: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5677: }
5678: static void dsp_mac_p_x0_x0_b(void)
5679: {
5680: Uint32 source[3], dest[3];
5681: Uint16 newsr;
5682:
5683: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5684:
5685: dest[0] = dsp_core.registers[DSP_REG_B2];
5686: dest[1] = dsp_core.registers[DSP_REG_B1];
5687: dest[2] = dsp_core.registers[DSP_REG_B0];
5688: newsr = dsp_add56(source, dest);
5689:
5690: dsp_core.registers[DSP_REG_B2] = dest[0];
5691: dsp_core.registers[DSP_REG_B1] = dest[1];
5692: dsp_core.registers[DSP_REG_B0] = dest[2];
5693:
5694: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5695:
5696: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5697: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5698: }
5699:
5700: static void dsp_mac_m_x0_x0_b(void)
5701: {
5702: Uint32 source[3], dest[3];
5703: Uint16 newsr;
5704:
5705: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5706:
5707: dest[0] = dsp_core.registers[DSP_REG_B2];
5708: dest[1] = dsp_core.registers[DSP_REG_B1];
5709: dest[2] = dsp_core.registers[DSP_REG_B0];
5710: newsr = dsp_add56(source, dest);
5711:
5712: dsp_core.registers[DSP_REG_B2] = dest[0];
5713: dsp_core.registers[DSP_REG_B1] = dest[1];
5714: dsp_core.registers[DSP_REG_B0] = dest[2];
5715:
5716: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5717:
5718: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5719: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5720: }
5721:
5722: static void dsp_mac_p_y0_y0_a(void)
5723: {
5724: Uint32 source[3], dest[3];
5725: Uint16 newsr;
5726:
5727: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5728:
5729: dest[0] = dsp_core.registers[DSP_REG_A2];
5730: dest[1] = dsp_core.registers[DSP_REG_A1];
5731: dest[2] = dsp_core.registers[DSP_REG_A0];
5732: newsr = dsp_add56(source, dest);
5733:
5734: dsp_core.registers[DSP_REG_A2] = dest[0];
5735: dsp_core.registers[DSP_REG_A1] = dest[1];
5736: dsp_core.registers[DSP_REG_A0] = dest[2];
5737:
5738: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5739:
5740: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5741: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5742: }
5743:
5744: static void dsp_mac_m_y0_y0_a(void)
5745: {
5746: Uint32 source[3], dest[3];
5747: Uint16 newsr;
5748:
5749: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5750:
5751: dest[0] = dsp_core.registers[DSP_REG_A2];
5752: dest[1] = dsp_core.registers[DSP_REG_A1];
5753: dest[2] = dsp_core.registers[DSP_REG_A0];
5754: newsr = dsp_add56(source, dest);
5755:
5756: dsp_core.registers[DSP_REG_A2] = dest[0];
5757: dsp_core.registers[DSP_REG_A1] = dest[1];
5758: dsp_core.registers[DSP_REG_A0] = dest[2];
5759:
5760: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5761:
5762: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5763: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5764: }
5765: static void dsp_mac_p_y0_y0_b(void)
5766: {
5767: Uint32 source[3], dest[3];
5768: Uint16 newsr;
5769:
5770: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5771:
5772: dest[0] = dsp_core.registers[DSP_REG_B2];
5773: dest[1] = dsp_core.registers[DSP_REG_B1];
5774: dest[2] = dsp_core.registers[DSP_REG_B0];
5775: newsr = dsp_add56(source, dest);
5776:
5777: dsp_core.registers[DSP_REG_B2] = dest[0];
5778: dsp_core.registers[DSP_REG_B1] = dest[1];
5779: dsp_core.registers[DSP_REG_B0] = dest[2];
5780:
5781: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5782:
5783: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5784: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5785: }
5786:
5787: static void dsp_mac_m_y0_y0_b(void)
5788: {
5789: Uint32 source[3], dest[3];
5790: Uint16 newsr;
5791:
5792: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5793:
5794: dest[0] = dsp_core.registers[DSP_REG_B2];
5795: dest[1] = dsp_core.registers[DSP_REG_B1];
5796: dest[2] = dsp_core.registers[DSP_REG_B0];
5797: newsr = dsp_add56(source, dest);
5798:
5799: dsp_core.registers[DSP_REG_B2] = dest[0];
5800: dsp_core.registers[DSP_REG_B1] = dest[1];
5801: dsp_core.registers[DSP_REG_B0] = dest[2];
5802:
5803: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5804:
5805: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5806: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5807: }
5808:
5809: static void dsp_mac_p_x1_x0_a(void)
5810: {
5811: Uint32 source[3], dest[3];
5812: Uint16 newsr;
5813:
5814: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5815:
5816: dest[0] = dsp_core.registers[DSP_REG_A2];
5817: dest[1] = dsp_core.registers[DSP_REG_A1];
5818: dest[2] = dsp_core.registers[DSP_REG_A0];
5819: newsr = dsp_add56(source, dest);
5820:
5821: dsp_core.registers[DSP_REG_A2] = dest[0];
5822: dsp_core.registers[DSP_REG_A1] = dest[1];
5823: dsp_core.registers[DSP_REG_A0] = dest[2];
5824:
5825: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5826:
5827: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5828: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5829: }
5830:
5831: static void dsp_mac_m_x1_x0_a(void)
5832: {
5833: Uint32 source[3], dest[3];
5834: Uint16 newsr;
5835:
5836: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5837:
5838: dest[0] = dsp_core.registers[DSP_REG_A2];
5839: dest[1] = dsp_core.registers[DSP_REG_A1];
5840: dest[2] = dsp_core.registers[DSP_REG_A0];
5841: newsr = dsp_add56(source, dest);
5842:
5843: dsp_core.registers[DSP_REG_A2] = dest[0];
5844: dsp_core.registers[DSP_REG_A1] = dest[1];
5845: dsp_core.registers[DSP_REG_A0] = dest[2];
5846:
5847: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5848:
5849: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5850: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5851: }
5852:
5853: static void dsp_mac_p_x1_x0_b(void)
5854: {
5855: Uint32 source[3], dest[3];
5856: Uint16 newsr;
5857:
5858: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5859:
5860: dest[0] = dsp_core.registers[DSP_REG_B2];
5861: dest[1] = dsp_core.registers[DSP_REG_B1];
5862: dest[2] = dsp_core.registers[DSP_REG_B0];
5863: newsr = dsp_add56(source, dest);
5864:
5865: dsp_core.registers[DSP_REG_B2] = dest[0];
5866: dsp_core.registers[DSP_REG_B1] = dest[1];
5867: dsp_core.registers[DSP_REG_B0] = dest[2];
5868:
5869: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5870:
5871: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5872: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5873: }
5874:
5875: static void dsp_mac_m_x1_x0_b(void)
5876: {
5877: Uint32 source[3], dest[3];
5878: Uint16 newsr;
5879:
5880: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5881:
5882: dest[0] = dsp_core.registers[DSP_REG_B2];
5883: dest[1] = dsp_core.registers[DSP_REG_B1];
5884: dest[2] = dsp_core.registers[DSP_REG_B0];
5885: newsr = dsp_add56(source, dest);
5886:
5887: dsp_core.registers[DSP_REG_B2] = dest[0];
5888: dsp_core.registers[DSP_REG_B1] = dest[1];
5889: dsp_core.registers[DSP_REG_B0] = dest[2];
5890:
5891: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5892:
5893: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5894: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5895: }
5896:
5897: static void dsp_mac_p_y1_y0_a(void)
5898: {
5899: Uint32 source[3], dest[3];
5900: Uint16 newsr;
5901:
5902: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5903:
5904: dest[0] = dsp_core.registers[DSP_REG_A2];
5905: dest[1] = dsp_core.registers[DSP_REG_A1];
5906: dest[2] = dsp_core.registers[DSP_REG_A0];
5907: newsr = dsp_add56(source, dest);
5908:
5909: dsp_core.registers[DSP_REG_A2] = dest[0];
5910: dsp_core.registers[DSP_REG_A1] = dest[1];
5911: dsp_core.registers[DSP_REG_A0] = dest[2];
5912:
5913: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5914:
5915: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5916: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5917: }
5918:
5919: static void dsp_mac_m_y1_y0_a(void)
5920: {
5921: Uint32 source[3], dest[3];
5922: Uint16 newsr;
5923:
5924: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5925:
5926: dest[0] = dsp_core.registers[DSP_REG_A2];
5927: dest[1] = dsp_core.registers[DSP_REG_A1];
5928: dest[2] = dsp_core.registers[DSP_REG_A0];
5929: newsr = dsp_add56(source, dest);
5930:
5931: dsp_core.registers[DSP_REG_A2] = dest[0];
5932: dsp_core.registers[DSP_REG_A1] = dest[1];
5933: dsp_core.registers[DSP_REG_A0] = dest[2];
5934:
5935: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5936:
5937: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5938: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5939: }
5940:
5941: static void dsp_mac_p_y1_y0_b(void)
5942: {
5943: Uint32 source[3], dest[3];
5944: Uint16 newsr;
5945:
5946: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5947:
5948: dest[0] = dsp_core.registers[DSP_REG_B2];
5949: dest[1] = dsp_core.registers[DSP_REG_B1];
5950: dest[2] = dsp_core.registers[DSP_REG_B0];
5951: newsr = dsp_add56(source, dest);
5952:
5953: dsp_core.registers[DSP_REG_B2] = dest[0];
5954: dsp_core.registers[DSP_REG_B1] = dest[1];
5955: dsp_core.registers[DSP_REG_B0] = dest[2];
5956:
5957: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5958:
5959: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5960: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5961: }
5962:
5963: static void dsp_mac_m_y1_y0_b(void)
5964: {
5965: Uint32 source[3], dest[3];
5966: Uint16 newsr;
5967:
5968: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5969:
5970: dest[0] = dsp_core.registers[DSP_REG_B2];
5971: dest[1] = dsp_core.registers[DSP_REG_B1];
5972: dest[2] = dsp_core.registers[DSP_REG_B0];
5973: newsr = dsp_add56(source, dest);
5974:
5975: dsp_core.registers[DSP_REG_B2] = dest[0];
5976: dsp_core.registers[DSP_REG_B1] = dest[1];
5977: dsp_core.registers[DSP_REG_B0] = dest[2];
5978:
5979: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5980:
5981: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5982: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5983: }
5984:
5985: static void dsp_mac_p_x0_y1_a(void)
5986: {
5987: Uint32 source[3], dest[3];
5988: Uint16 newsr;
5989:
5990: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
5991:
5992: dest[0] = dsp_core.registers[DSP_REG_A2];
5993: dest[1] = dsp_core.registers[DSP_REG_A1];
5994: dest[2] = dsp_core.registers[DSP_REG_A0];
5995: newsr = dsp_add56(source, dest);
5996:
5997: dsp_core.registers[DSP_REG_A2] = dest[0];
5998: dsp_core.registers[DSP_REG_A1] = dest[1];
5999: dsp_core.registers[DSP_REG_A0] = dest[2];
6000:
6001: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6002:
6003: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6004: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6005: }
6006:
6007: static void dsp_mac_m_x0_y1_a(void)
6008: {
6009: Uint32 source[3], dest[3];
6010: Uint16 newsr;
6011:
6012: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6013:
6014: dest[0] = dsp_core.registers[DSP_REG_A2];
6015: dest[1] = dsp_core.registers[DSP_REG_A1];
6016: dest[2] = dsp_core.registers[DSP_REG_A0];
6017: newsr = dsp_add56(source, dest);
6018:
6019: dsp_core.registers[DSP_REG_A2] = dest[0];
6020: dsp_core.registers[DSP_REG_A1] = dest[1];
6021: dsp_core.registers[DSP_REG_A0] = dest[2];
6022:
6023: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6024:
6025: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6026: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6027: }
6028:
6029: static void dsp_mac_p_x0_y1_b(void)
6030: {
6031: Uint32 source[3], dest[3];
6032: Uint16 newsr;
6033:
6034: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6035:
6036: dest[0] = dsp_core.registers[DSP_REG_B2];
6037: dest[1] = dsp_core.registers[DSP_REG_B1];
6038: dest[2] = dsp_core.registers[DSP_REG_B0];
6039: newsr = dsp_add56(source, dest);
6040:
6041: dsp_core.registers[DSP_REG_B2] = dest[0];
6042: dsp_core.registers[DSP_REG_B1] = dest[1];
6043: dsp_core.registers[DSP_REG_B0] = dest[2];
6044:
6045: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6046:
6047: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6048: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6049: }
6050:
6051: static void dsp_mac_m_x0_y1_b(void)
6052: {
6053: Uint32 source[3], dest[3];
6054: Uint16 newsr;
6055:
6056: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6057:
6058: dest[0] = dsp_core.registers[DSP_REG_B2];
6059: dest[1] = dsp_core.registers[DSP_REG_B1];
6060: dest[2] = dsp_core.registers[DSP_REG_B0];
6061: newsr = dsp_add56(source, dest);
6062:
6063: dsp_core.registers[DSP_REG_B2] = dest[0];
6064: dsp_core.registers[DSP_REG_B1] = dest[1];
6065: dsp_core.registers[DSP_REG_B0] = dest[2];
6066:
6067: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6068:
6069: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6070: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6071: }
6072:
6073: static void dsp_mac_p_y0_x0_a(void)
6074: {
6075: Uint32 source[3], dest[3];
6076: Uint16 newsr;
6077:
6078: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6079:
6080: dest[0] = dsp_core.registers[DSP_REG_A2];
6081: dest[1] = dsp_core.registers[DSP_REG_A1];
6082: dest[2] = dsp_core.registers[DSP_REG_A0];
6083: newsr = dsp_add56(source, dest);
6084:
6085: dsp_core.registers[DSP_REG_A2] = dest[0];
6086: dsp_core.registers[DSP_REG_A1] = dest[1];
6087: dsp_core.registers[DSP_REG_A0] = dest[2];
6088:
6089: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6090:
6091: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6092: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6093: }
6094:
6095: static void dsp_mac_m_y0_x0_a(void)
6096: {
6097: Uint32 source[3], dest[3];
6098: Uint16 newsr;
6099:
6100: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6101:
6102: dest[0] = dsp_core.registers[DSP_REG_A2];
6103: dest[1] = dsp_core.registers[DSP_REG_A1];
6104: dest[2] = dsp_core.registers[DSP_REG_A0];
6105: newsr = dsp_add56(source, dest);
6106:
6107: dsp_core.registers[DSP_REG_A2] = dest[0];
6108: dsp_core.registers[DSP_REG_A1] = dest[1];
6109: dsp_core.registers[DSP_REG_A0] = dest[2];
6110:
6111: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6112:
6113: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6114: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6115: }
6116:
6117: static void dsp_mac_p_y0_x0_b(void)
6118: {
6119: Uint32 source[3], dest[3];
6120: Uint16 newsr;
6121:
6122: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6123:
6124: dest[0] = dsp_core.registers[DSP_REG_B2];
6125: dest[1] = dsp_core.registers[DSP_REG_B1];
6126: dest[2] = dsp_core.registers[DSP_REG_B0];
6127: newsr = dsp_add56(source, dest);
6128:
6129: dsp_core.registers[DSP_REG_B2] = dest[0];
6130: dsp_core.registers[DSP_REG_B1] = dest[1];
6131: dsp_core.registers[DSP_REG_B0] = dest[2];
6132:
6133: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6134:
6135: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6136: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6137: }
6138:
6139: static void dsp_mac_m_y0_x0_b(void)
6140: {
6141: Uint32 source[3], dest[3];
6142: Uint16 newsr;
6143:
6144: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6145:
6146: dest[0] = dsp_core.registers[DSP_REG_B2];
6147: dest[1] = dsp_core.registers[DSP_REG_B1];
6148: dest[2] = dsp_core.registers[DSP_REG_B0];
6149: newsr = dsp_add56(source, dest);
6150:
6151: dsp_core.registers[DSP_REG_B2] = dest[0];
6152: dsp_core.registers[DSP_REG_B1] = dest[1];
6153: dsp_core.registers[DSP_REG_B0] = dest[2];
6154:
6155: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6156:
6157: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6158: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6159: }
6160:
6161: static void dsp_mac_p_x1_y0_a(void)
6162: {
6163: Uint32 source[3], dest[3];
6164: Uint16 newsr;
6165:
6166: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6167:
6168: dest[0] = dsp_core.registers[DSP_REG_A2];
6169: dest[1] = dsp_core.registers[DSP_REG_A1];
6170: dest[2] = dsp_core.registers[DSP_REG_A0];
6171: newsr = dsp_add56(source, dest);
6172:
6173: dsp_core.registers[DSP_REG_A2] = dest[0];
6174: dsp_core.registers[DSP_REG_A1] = dest[1];
6175: dsp_core.registers[DSP_REG_A0] = dest[2];
6176:
6177: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6178:
6179: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6180: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6181: }
6182:
6183: static void dsp_mac_m_x1_y0_a(void)
6184: {
6185: Uint32 source[3], dest[3];
6186: Uint16 newsr;
6187:
6188: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6189:
6190: dest[0] = dsp_core.registers[DSP_REG_A2];
6191: dest[1] = dsp_core.registers[DSP_REG_A1];
6192: dest[2] = dsp_core.registers[DSP_REG_A0];
6193: newsr = dsp_add56(source, dest);
6194:
6195: dsp_core.registers[DSP_REG_A2] = dest[0];
6196: dsp_core.registers[DSP_REG_A1] = dest[1];
6197: dsp_core.registers[DSP_REG_A0] = dest[2];
6198:
6199: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6200:
6201: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6202: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6203: }
6204:
6205: static void dsp_mac_p_x1_y0_b(void)
6206: {
6207: Uint32 source[3], dest[3];
6208: Uint16 newsr;
6209:
6210: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6211:
6212: dest[0] = dsp_core.registers[DSP_REG_B2];
6213: dest[1] = dsp_core.registers[DSP_REG_B1];
6214: dest[2] = dsp_core.registers[DSP_REG_B0];
6215: newsr = dsp_add56(source, dest);
6216:
6217: dsp_core.registers[DSP_REG_B2] = dest[0];
6218: dsp_core.registers[DSP_REG_B1] = dest[1];
6219: dsp_core.registers[DSP_REG_B0] = dest[2];
6220:
6221: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6222:
6223: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6224: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6225: }
6226:
6227: static void dsp_mac_m_x1_y0_b(void)
6228: {
6229: Uint32 source[3], dest[3];
6230: Uint16 newsr;
6231:
6232: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6233:
6234: dest[0] = dsp_core.registers[DSP_REG_B2];
6235: dest[1] = dsp_core.registers[DSP_REG_B1];
6236: dest[2] = dsp_core.registers[DSP_REG_B0];
6237: newsr = dsp_add56(source, dest);
6238:
6239: dsp_core.registers[DSP_REG_B2] = dest[0];
6240: dsp_core.registers[DSP_REG_B1] = dest[1];
6241: dsp_core.registers[DSP_REG_B0] = dest[2];
6242:
6243: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6244:
6245: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6246: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6247: }
6248:
6249: static void dsp_mac_p_y1_x1_a(void)
6250: {
6251: Uint32 source[3], dest[3];
6252: Uint16 newsr;
6253:
6254: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6255:
6256: dest[0] = dsp_core.registers[DSP_REG_A2];
6257: dest[1] = dsp_core.registers[DSP_REG_A1];
6258: dest[2] = dsp_core.registers[DSP_REG_A0];
6259: newsr = dsp_add56(source, dest);
6260:
6261: dsp_core.registers[DSP_REG_A2] = dest[0];
6262: dsp_core.registers[DSP_REG_A1] = dest[1];
6263: dsp_core.registers[DSP_REG_A0] = dest[2];
6264:
6265: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6266:
6267: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6268: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6269: }
6270:
6271: static void dsp_mac_m_y1_x1_a(void)
6272: {
6273: Uint32 source[3], dest[3];
6274: Uint16 newsr;
6275:
6276: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6277:
6278: dest[0] = dsp_core.registers[DSP_REG_A2];
6279: dest[1] = dsp_core.registers[DSP_REG_A1];
6280: dest[2] = dsp_core.registers[DSP_REG_A0];
6281: newsr = dsp_add56(source, dest);
6282:
6283: dsp_core.registers[DSP_REG_A2] = dest[0];
6284: dsp_core.registers[DSP_REG_A1] = dest[1];
6285: dsp_core.registers[DSP_REG_A0] = dest[2];
6286:
6287: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6288:
6289: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6290: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6291: }
6292:
6293: static void dsp_mac_p_y1_x1_b(void)
6294: {
6295: Uint32 source[3], dest[3];
6296: Uint16 newsr;
6297:
6298: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6299:
6300: dest[0] = dsp_core.registers[DSP_REG_B2];
6301: dest[1] = dsp_core.registers[DSP_REG_B1];
6302: dest[2] = dsp_core.registers[DSP_REG_B0];
6303: newsr = dsp_add56(source, dest);
6304:
6305: dsp_core.registers[DSP_REG_B2] = dest[0];
6306: dsp_core.registers[DSP_REG_B1] = dest[1];
6307: dsp_core.registers[DSP_REG_B0] = dest[2];
6308:
6309: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6310:
6311: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6312: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6313: }
6314:
6315: static void dsp_mac_m_y1_x1_b(void)
6316: {
6317: Uint32 source[3], dest[3];
6318: Uint16 newsr;
6319:
6320: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6321:
6322: dest[0] = dsp_core.registers[DSP_REG_B2];
6323: dest[1] = dsp_core.registers[DSP_REG_B1];
6324: dest[2] = dsp_core.registers[DSP_REG_B0];
6325: newsr = dsp_add56(source, dest);
6326:
6327: dsp_core.registers[DSP_REG_B2] = dest[0];
6328: dsp_core.registers[DSP_REG_B1] = dest[1];
6329: dsp_core.registers[DSP_REG_B0] = dest[2];
6330:
6331: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6332:
6333: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6334: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6335: }
6336:
6337: static void dsp_macr_p_x0_x0_a(void)
6338: {
6339: Uint32 source[3], dest[3];
6340: Uint16 newsr;
6341:
6342: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6343:
6344: dest[0] = dsp_core.registers[DSP_REG_A2];
6345: dest[1] = dsp_core.registers[DSP_REG_A1];
6346: dest[2] = dsp_core.registers[DSP_REG_A0];
6347: newsr = dsp_add56(source, dest);
6348:
6349: dsp_rnd56(dest);
6350:
6351: dsp_core.registers[DSP_REG_A2] = dest[0];
6352: dsp_core.registers[DSP_REG_A1] = dest[1];
6353: dsp_core.registers[DSP_REG_A0] = dest[2];
6354:
6355: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6356:
6357: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6358: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6359: }
6360:
6361: static void dsp_macr_m_x0_x0_a(void)
6362: {
6363: Uint32 source[3], dest[3];
6364: Uint16 newsr;
6365:
6366: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6367:
6368: dest[0] = dsp_core.registers[DSP_REG_A2];
6369: dest[1] = dsp_core.registers[DSP_REG_A1];
6370: dest[2] = dsp_core.registers[DSP_REG_A0];
6371: newsr = dsp_add56(source, dest);
6372:
6373: dsp_rnd56(dest);
6374:
6375: dsp_core.registers[DSP_REG_A2] = dest[0];
6376: dsp_core.registers[DSP_REG_A1] = dest[1];
6377: dsp_core.registers[DSP_REG_A0] = dest[2];
6378:
6379: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6380:
6381: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6382: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6383: }
6384: static void dsp_macr_p_x0_x0_b(void)
6385: {
6386: Uint32 source[3], dest[3];
6387: Uint16 newsr;
6388:
6389: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6390:
6391: dest[0] = dsp_core.registers[DSP_REG_B2];
6392: dest[1] = dsp_core.registers[DSP_REG_B1];
6393: dest[2] = dsp_core.registers[DSP_REG_B0];
6394: newsr = dsp_add56(source, dest);
6395:
6396: dsp_rnd56(dest);
6397:
6398: dsp_core.registers[DSP_REG_B2] = dest[0];
6399: dsp_core.registers[DSP_REG_B1] = dest[1];
6400: dsp_core.registers[DSP_REG_B0] = dest[2];
6401:
6402: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6403:
6404: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6405: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6406: }
6407:
6408: static void dsp_macr_m_x0_x0_b(void)
6409: {
6410: Uint32 source[3], dest[3];
6411: Uint16 newsr;
6412:
6413: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6414:
6415: dest[0] = dsp_core.registers[DSP_REG_B2];
6416: dest[1] = dsp_core.registers[DSP_REG_B1];
6417: dest[2] = dsp_core.registers[DSP_REG_B0];
6418: newsr = dsp_add56(source, dest);
6419:
6420: dsp_rnd56(dest);
6421:
6422: dsp_core.registers[DSP_REG_B2] = dest[0];
6423: dsp_core.registers[DSP_REG_B1] = dest[1];
6424: dsp_core.registers[DSP_REG_B0] = dest[2];
6425:
6426: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6427:
6428: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6429: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6430: }
6431:
6432: static void dsp_macr_p_y0_y0_a(void)
6433: {
6434: Uint32 source[3], dest[3];
6435: Uint16 newsr;
6436:
6437: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6438:
6439: dest[0] = dsp_core.registers[DSP_REG_A2];
6440: dest[1] = dsp_core.registers[DSP_REG_A1];
6441: dest[2] = dsp_core.registers[DSP_REG_A0];
6442: newsr = dsp_add56(source, dest);
6443:
6444: dsp_rnd56(dest);
6445:
6446: dsp_core.registers[DSP_REG_A2] = dest[0];
6447: dsp_core.registers[DSP_REG_A1] = dest[1];
6448: dsp_core.registers[DSP_REG_A0] = dest[2];
6449:
6450: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6451:
6452: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6453: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6454: }
6455:
6456: static void dsp_macr_m_y0_y0_a(void)
6457: {
6458: Uint32 source[3], dest[3];
6459: Uint16 newsr;
6460:
6461: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6462:
6463: dest[0] = dsp_core.registers[DSP_REG_A2];
6464: dest[1] = dsp_core.registers[DSP_REG_A1];
6465: dest[2] = dsp_core.registers[DSP_REG_A0];
6466: newsr = dsp_add56(source, dest);
6467:
6468: dsp_rnd56(dest);
6469:
6470: dsp_core.registers[DSP_REG_A2] = dest[0];
6471: dsp_core.registers[DSP_REG_A1] = dest[1];
6472: dsp_core.registers[DSP_REG_A0] = dest[2];
6473:
6474: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6475:
6476: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6477: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6478: }
6479: static void dsp_macr_p_y0_y0_b(void)
6480: {
6481: Uint32 source[3], dest[3];
6482: Uint16 newsr;
6483:
6484: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6485:
6486: dest[0] = dsp_core.registers[DSP_REG_B2];
6487: dest[1] = dsp_core.registers[DSP_REG_B1];
6488: dest[2] = dsp_core.registers[DSP_REG_B0];
6489: newsr = dsp_add56(source, dest);
6490:
6491: dsp_rnd56(dest);
6492:
6493: dsp_core.registers[DSP_REG_B2] = dest[0];
6494: dsp_core.registers[DSP_REG_B1] = dest[1];
6495: dsp_core.registers[DSP_REG_B0] = dest[2];
6496:
6497: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6498:
6499: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6500: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6501: }
6502:
6503: static void dsp_macr_m_y0_y0_b(void)
6504: {
6505: Uint32 source[3], dest[3];
6506: Uint16 newsr;
6507:
6508: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6509:
6510: dest[0] = dsp_core.registers[DSP_REG_B2];
6511: dest[1] = dsp_core.registers[DSP_REG_B1];
6512: dest[2] = dsp_core.registers[DSP_REG_B0];
6513: newsr = dsp_add56(source, dest);
6514:
6515: dsp_rnd56(dest);
6516:
6517: dsp_core.registers[DSP_REG_B2] = dest[0];
6518: dsp_core.registers[DSP_REG_B1] = dest[1];
6519: dsp_core.registers[DSP_REG_B0] = dest[2];
6520:
6521: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6522:
6523: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6524: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6525: }
6526:
6527: static void dsp_macr_p_x1_x0_a(void)
6528: {
6529: Uint32 source[3], dest[3];
6530: Uint16 newsr;
6531:
6532: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6533:
6534: dest[0] = dsp_core.registers[DSP_REG_A2];
6535: dest[1] = dsp_core.registers[DSP_REG_A1];
6536: dest[2] = dsp_core.registers[DSP_REG_A0];
6537: newsr = dsp_add56(source, dest);
6538:
6539: dsp_rnd56(dest);
6540:
6541: dsp_core.registers[DSP_REG_A2] = dest[0];
6542: dsp_core.registers[DSP_REG_A1] = dest[1];
6543: dsp_core.registers[DSP_REG_A0] = dest[2];
6544:
6545: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6546:
6547: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6548: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6549: }
6550:
6551: static void dsp_macr_m_x1_x0_a(void)
6552: {
6553: Uint32 source[3], dest[3];
6554: Uint16 newsr;
6555:
6556: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6557:
6558: dest[0] = dsp_core.registers[DSP_REG_A2];
6559: dest[1] = dsp_core.registers[DSP_REG_A1];
6560: dest[2] = dsp_core.registers[DSP_REG_A0];
6561: newsr = dsp_add56(source, dest);
6562:
6563: dsp_rnd56(dest);
6564:
6565: dsp_core.registers[DSP_REG_A2] = dest[0];
6566: dsp_core.registers[DSP_REG_A1] = dest[1];
6567: dsp_core.registers[DSP_REG_A0] = dest[2];
6568:
6569: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6570:
6571: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6572: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6573: }
6574:
6575: static void dsp_macr_p_x1_x0_b(void)
6576: {
6577: Uint32 source[3], dest[3];
6578: Uint16 newsr;
6579:
6580: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6581:
6582: dest[0] = dsp_core.registers[DSP_REG_B2];
6583: dest[1] = dsp_core.registers[DSP_REG_B1];
6584: dest[2] = dsp_core.registers[DSP_REG_B0];
6585: newsr = dsp_add56(source, dest);
6586:
6587: dsp_rnd56(dest);
6588:
6589: dsp_core.registers[DSP_REG_B2] = dest[0];
6590: dsp_core.registers[DSP_REG_B1] = dest[1];
6591: dsp_core.registers[DSP_REG_B0] = dest[2];
6592:
6593: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6594:
6595: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6596: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6597: }
6598:
6599: static void dsp_macr_m_x1_x0_b(void)
6600: {
6601: Uint32 source[3], dest[3];
6602: Uint16 newsr;
6603:
6604: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6605:
6606: dest[0] = dsp_core.registers[DSP_REG_B2];
6607: dest[1] = dsp_core.registers[DSP_REG_B1];
6608: dest[2] = dsp_core.registers[DSP_REG_B0];
6609: newsr = dsp_add56(source, dest);
6610:
6611: dsp_rnd56(dest);
6612:
6613: dsp_core.registers[DSP_REG_B2] = dest[0];
6614: dsp_core.registers[DSP_REG_B1] = dest[1];
6615: dsp_core.registers[DSP_REG_B0] = dest[2];
6616:
6617: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6618:
6619: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6620: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6621: }
6622:
6623: static void dsp_macr_p_y1_y0_a(void)
6624: {
6625: Uint32 source[3], dest[3];
6626: Uint16 newsr;
6627:
6628: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6629:
6630: dest[0] = dsp_core.registers[DSP_REG_A2];
6631: dest[1] = dsp_core.registers[DSP_REG_A1];
6632: dest[2] = dsp_core.registers[DSP_REG_A0];
6633: newsr = dsp_add56(source, dest);
6634:
6635: dsp_rnd56(dest);
6636:
6637: dsp_core.registers[DSP_REG_A2] = dest[0];
6638: dsp_core.registers[DSP_REG_A1] = dest[1];
6639: dsp_core.registers[DSP_REG_A0] = dest[2];
6640:
6641: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6642:
6643: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6644: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6645: }
6646:
6647: static void dsp_macr_m_y1_y0_a(void)
6648: {
6649: Uint32 source[3], dest[3];
6650: Uint16 newsr;
6651:
6652: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6653:
6654: dest[0] = dsp_core.registers[DSP_REG_A2];
6655: dest[1] = dsp_core.registers[DSP_REG_A1];
6656: dest[2] = dsp_core.registers[DSP_REG_A0];
6657: newsr = dsp_add56(source, dest);
6658:
6659: dsp_rnd56(dest);
6660:
6661: dsp_core.registers[DSP_REG_A2] = dest[0];
6662: dsp_core.registers[DSP_REG_A1] = dest[1];
6663: dsp_core.registers[DSP_REG_A0] = dest[2];
6664:
6665: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6666:
6667: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6668: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6669: }
6670:
6671: static void dsp_macr_p_y1_y0_b(void)
6672: {
6673: Uint32 source[3], dest[3];
6674: Uint16 newsr;
6675:
6676: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6677:
6678: dest[0] = dsp_core.registers[DSP_REG_B2];
6679: dest[1] = dsp_core.registers[DSP_REG_B1];
6680: dest[2] = dsp_core.registers[DSP_REG_B0];
6681: newsr = dsp_add56(source, dest);
6682:
6683: dsp_rnd56(dest);
6684:
6685: dsp_core.registers[DSP_REG_B2] = dest[0];
6686: dsp_core.registers[DSP_REG_B1] = dest[1];
6687: dsp_core.registers[DSP_REG_B0] = dest[2];
6688:
6689: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6690:
6691: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6692: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6693: }
6694:
6695: static void dsp_macr_m_y1_y0_b(void)
6696: {
6697: Uint32 source[3], dest[3];
6698: Uint16 newsr;
6699:
6700: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6701:
6702: dest[0] = dsp_core.registers[DSP_REG_B2];
6703: dest[1] = dsp_core.registers[DSP_REG_B1];
6704: dest[2] = dsp_core.registers[DSP_REG_B0];
6705: newsr = dsp_add56(source, dest);
6706:
6707: dsp_rnd56(dest);
6708:
6709: dsp_core.registers[DSP_REG_B2] = dest[0];
6710: dsp_core.registers[DSP_REG_B1] = dest[1];
6711: dsp_core.registers[DSP_REG_B0] = dest[2];
6712:
6713: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6714:
6715: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6716: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6717: }
6718:
6719: static void dsp_macr_p_x0_y1_a(void)
6720: {
6721: Uint32 source[3], dest[3];
6722: Uint16 newsr;
6723:
6724: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6725:
6726: dest[0] = dsp_core.registers[DSP_REG_A2];
6727: dest[1] = dsp_core.registers[DSP_REG_A1];
6728: dest[2] = dsp_core.registers[DSP_REG_A0];
6729: newsr = dsp_add56(source, dest);
6730:
6731: dsp_rnd56(dest);
6732:
6733: dsp_core.registers[DSP_REG_A2] = dest[0];
6734: dsp_core.registers[DSP_REG_A1] = dest[1];
6735: dsp_core.registers[DSP_REG_A0] = dest[2];
6736:
6737: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6738:
6739: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6740: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6741: }
6742:
6743: static void dsp_macr_m_x0_y1_a(void)
6744: {
6745: Uint32 source[3], dest[3];
6746: Uint16 newsr;
6747:
6748: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6749:
6750: dest[0] = dsp_core.registers[DSP_REG_A2];
6751: dest[1] = dsp_core.registers[DSP_REG_A1];
6752: dest[2] = dsp_core.registers[DSP_REG_A0];
6753: newsr = dsp_add56(source, dest);
6754:
6755: dsp_rnd56(dest);
6756:
6757: dsp_core.registers[DSP_REG_A2] = dest[0];
6758: dsp_core.registers[DSP_REG_A1] = dest[1];
6759: dsp_core.registers[DSP_REG_A0] = dest[2];
6760:
6761: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6762:
6763: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6764: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6765: }
6766:
6767: static void dsp_macr_p_x0_y1_b(void)
6768: {
6769: Uint32 source[3], dest[3];
6770: Uint16 newsr;
6771:
6772: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6773:
6774: dest[0] = dsp_core.registers[DSP_REG_B2];
6775: dest[1] = dsp_core.registers[DSP_REG_B1];
6776: dest[2] = dsp_core.registers[DSP_REG_B0];
6777: newsr = dsp_add56(source, dest);
6778:
6779: dsp_rnd56(dest);
6780:
6781: dsp_core.registers[DSP_REG_B2] = dest[0];
6782: dsp_core.registers[DSP_REG_B1] = dest[1];
6783: dsp_core.registers[DSP_REG_B0] = dest[2];
6784:
6785: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6786:
6787: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6788: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6789: }
6790:
6791: static void dsp_macr_m_x0_y1_b(void)
6792: {
6793: Uint32 source[3], dest[3];
6794: Uint16 newsr;
6795:
6796: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6797:
6798: dest[0] = dsp_core.registers[DSP_REG_B2];
6799: dest[1] = dsp_core.registers[DSP_REG_B1];
6800: dest[2] = dsp_core.registers[DSP_REG_B0];
6801: newsr = dsp_add56(source, dest);
6802:
6803: dsp_rnd56(dest);
6804:
6805: dsp_core.registers[DSP_REG_B2] = dest[0];
6806: dsp_core.registers[DSP_REG_B1] = dest[1];
6807: dsp_core.registers[DSP_REG_B0] = dest[2];
6808:
6809: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6810:
6811: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6812: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6813: }
6814:
6815: static void dsp_macr_p_y0_x0_a(void)
6816: {
6817: Uint32 source[3], dest[3];
6818: Uint16 newsr;
6819:
6820: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6821:
6822: dest[0] = dsp_core.registers[DSP_REG_A2];
6823: dest[1] = dsp_core.registers[DSP_REG_A1];
6824: dest[2] = dsp_core.registers[DSP_REG_A0];
6825: newsr = dsp_add56(source, dest);
6826:
6827: dsp_rnd56(dest);
6828:
6829: dsp_core.registers[DSP_REG_A2] = dest[0];
6830: dsp_core.registers[DSP_REG_A1] = dest[1];
6831: dsp_core.registers[DSP_REG_A0] = dest[2];
6832:
6833: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6834:
6835: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6836: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6837: }
6838:
6839: static void dsp_macr_m_y0_x0_a(void)
6840: {
6841: Uint32 source[3], dest[3];
6842: Uint16 newsr;
6843:
6844: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6845:
6846: dest[0] = dsp_core.registers[DSP_REG_A2];
6847: dest[1] = dsp_core.registers[DSP_REG_A1];
6848: dest[2] = dsp_core.registers[DSP_REG_A0];
6849: newsr = dsp_add56(source, dest);
6850:
6851: dsp_rnd56(dest);
6852:
6853: dsp_core.registers[DSP_REG_A2] = dest[0];
6854: dsp_core.registers[DSP_REG_A1] = dest[1];
6855: dsp_core.registers[DSP_REG_A0] = dest[2];
6856:
6857: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6858:
6859: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6860: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6861: }
6862:
6863: static void dsp_macr_p_y0_x0_b(void)
6864: {
6865: Uint32 source[3], dest[3];
6866: Uint16 newsr;
6867:
6868: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6869:
6870: dest[0] = dsp_core.registers[DSP_REG_B2];
6871: dest[1] = dsp_core.registers[DSP_REG_B1];
6872: dest[2] = dsp_core.registers[DSP_REG_B0];
6873: newsr = dsp_add56(source, dest);
6874:
6875: dsp_rnd56(dest);
6876:
6877: dsp_core.registers[DSP_REG_B2] = dest[0];
6878: dsp_core.registers[DSP_REG_B1] = dest[1];
6879: dsp_core.registers[DSP_REG_B0] = dest[2];
6880:
6881: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6882:
6883: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6884: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6885: }
6886:
6887: static void dsp_macr_m_y0_x0_b(void)
6888: {
6889: Uint32 source[3], dest[3];
6890: Uint16 newsr;
6891:
6892: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6893:
6894: dest[0] = dsp_core.registers[DSP_REG_B2];
6895: dest[1] = dsp_core.registers[DSP_REG_B1];
6896: dest[2] = dsp_core.registers[DSP_REG_B0];
6897: newsr = dsp_add56(source, dest);
6898:
6899: dsp_rnd56(dest);
6900:
6901: dsp_core.registers[DSP_REG_B2] = dest[0];
6902: dsp_core.registers[DSP_REG_B1] = dest[1];
6903: dsp_core.registers[DSP_REG_B0] = dest[2];
6904:
6905: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6906:
6907: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6908: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6909: }
6910:
6911: static void dsp_macr_p_x1_y0_a(void)
6912: {
6913: Uint32 source[3], dest[3];
6914: Uint16 newsr;
6915:
6916: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6917:
6918: dest[0] = dsp_core.registers[DSP_REG_A2];
6919: dest[1] = dsp_core.registers[DSP_REG_A1];
6920: dest[2] = dsp_core.registers[DSP_REG_A0];
6921: newsr = dsp_add56(source, dest);
6922:
6923: dsp_rnd56(dest);
6924:
6925: dsp_core.registers[DSP_REG_A2] = dest[0];
6926: dsp_core.registers[DSP_REG_A1] = dest[1];
6927: dsp_core.registers[DSP_REG_A0] = dest[2];
6928:
6929: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6930:
6931: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6932: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6933: }
6934:
6935: static void dsp_macr_m_x1_y0_a(void)
6936: {
6937: Uint32 source[3], dest[3];
6938: Uint16 newsr;
6939:
6940: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6941:
6942: dest[0] = dsp_core.registers[DSP_REG_A2];
6943: dest[1] = dsp_core.registers[DSP_REG_A1];
6944: dest[2] = dsp_core.registers[DSP_REG_A0];
6945: newsr = dsp_add56(source, dest);
6946:
6947: dsp_rnd56(dest);
6948:
6949: dsp_core.registers[DSP_REG_A2] = dest[0];
6950: dsp_core.registers[DSP_REG_A1] = dest[1];
6951: dsp_core.registers[DSP_REG_A0] = dest[2];
6952:
6953: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6954:
6955: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6956: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6957: }
6958:
6959: static void dsp_macr_p_x1_y0_b(void)
6960: {
6961: Uint32 source[3], dest[3];
6962: Uint16 newsr;
6963:
6964: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6965:
6966: dest[0] = dsp_core.registers[DSP_REG_B2];
6967: dest[1] = dsp_core.registers[DSP_REG_B1];
6968: dest[2] = dsp_core.registers[DSP_REG_B0];
6969: newsr = dsp_add56(source, dest);
6970:
1.1.1.10! root 6971: dsp_rnd56(dest);
! 6972:
1.1.1.6 root 6973: dsp_core.registers[DSP_REG_B2] = dest[0];
6974: dsp_core.registers[DSP_REG_B1] = dest[1];
6975: dsp_core.registers[DSP_REG_B0] = dest[2];
6976:
6977: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6978:
6979: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6980: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6981: }
6982:
6983: static void dsp_macr_m_x1_y0_b(void)
6984: {
6985: Uint32 source[3], dest[3];
6986: Uint16 newsr;
6987:
6988: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6989:
6990: dest[0] = dsp_core.registers[DSP_REG_B2];
6991: dest[1] = dsp_core.registers[DSP_REG_B1];
6992: dest[2] = dsp_core.registers[DSP_REG_B0];
6993: newsr = dsp_add56(source, dest);
6994:
6995: dsp_rnd56(dest);
6996:
6997: dsp_core.registers[DSP_REG_B2] = dest[0];
6998: dsp_core.registers[DSP_REG_B1] = dest[1];
6999: dsp_core.registers[DSP_REG_B0] = dest[2];
7000:
7001: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7002:
7003: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7004: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7005: }
7006:
7007: static void dsp_macr_p_y1_x1_a(void)
7008: {
7009: Uint32 source[3], dest[3];
7010: Uint16 newsr;
7011:
7012: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7013:
7014: dest[0] = dsp_core.registers[DSP_REG_A2];
7015: dest[1] = dsp_core.registers[DSP_REG_A1];
7016: dest[2] = dsp_core.registers[DSP_REG_A0];
7017: newsr = dsp_add56(source, dest);
7018:
7019: dsp_rnd56(dest);
7020:
7021: dsp_core.registers[DSP_REG_A2] = dest[0];
7022: dsp_core.registers[DSP_REG_A1] = dest[1];
7023: dsp_core.registers[DSP_REG_A0] = dest[2];
7024:
7025: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7026:
7027: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7028: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7029: }
7030:
7031: static void dsp_macr_m_y1_x1_a(void)
7032: {
7033: Uint32 source[3], dest[3];
7034: Uint16 newsr;
7035:
7036: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7037:
7038: dest[0] = dsp_core.registers[DSP_REG_A2];
7039: dest[1] = dsp_core.registers[DSP_REG_A1];
7040: dest[2] = dsp_core.registers[DSP_REG_A0];
7041: newsr = dsp_add56(source, dest);
7042:
7043: dsp_rnd56(dest);
7044:
7045: dsp_core.registers[DSP_REG_A2] = dest[0];
7046: dsp_core.registers[DSP_REG_A1] = dest[1];
7047: dsp_core.registers[DSP_REG_A0] = dest[2];
7048:
7049: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7050:
7051: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7052: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7053: }
7054:
7055: static void dsp_macr_p_y1_x1_b(void)
7056: {
7057: Uint32 source[3], dest[3];
7058: Uint16 newsr;
7059:
7060: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7061:
7062: dest[0] = dsp_core.registers[DSP_REG_B2];
7063: dest[1] = dsp_core.registers[DSP_REG_B1];
7064: dest[2] = dsp_core.registers[DSP_REG_B0];
7065: newsr = dsp_add56(source, dest);
7066:
7067: dsp_rnd56(dest);
7068:
7069: dsp_core.registers[DSP_REG_B2] = dest[0];
7070: dsp_core.registers[DSP_REG_B1] = dest[1];
7071: dsp_core.registers[DSP_REG_B0] = dest[2];
7072:
7073: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7074:
7075: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7076: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7077: }
7078:
7079: static void dsp_macr_m_y1_x1_b(void)
7080: {
7081: Uint32 source[3], dest[3];
7082: Uint16 newsr;
7083:
7084: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7085:
7086: dest[0] = dsp_core.registers[DSP_REG_B2];
7087: dest[1] = dsp_core.registers[DSP_REG_B1];
7088: dest[2] = dsp_core.registers[DSP_REG_B0];
7089: newsr = dsp_add56(source, dest);
7090:
7091: dsp_rnd56(dest);
7092:
7093: dsp_core.registers[DSP_REG_B2] = dest[0];
7094: dsp_core.registers[DSP_REG_B1] = dest[1];
7095: dsp_core.registers[DSP_REG_B0] = dest[2];
7096:
7097: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7098:
7099: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7100: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7101: }
7102:
7103:
7104: static void dsp_move(void)
7105: {
7106: /* move instruction inside alu opcodes
7107: taken care of by parallel move dispatcher */
7108: }
7109:
7110: static void dsp_mpy_p_x0_x0_a(void)
7111: {
7112: Uint32 source[3];
7113:
7114: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7115:
7116: dsp_core.registers[DSP_REG_A2] = source[0];
7117: dsp_core.registers[DSP_REG_A1] = source[1];
7118: dsp_core.registers[DSP_REG_A0] = source[2];
7119:
7120: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7121: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7122: }
7123:
7124: static void dsp_mpy_m_x0_x0_a(void)
7125: {
7126: Uint32 source[3];
7127:
7128: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7129:
7130: dsp_core.registers[DSP_REG_A2] = source[0];
7131: dsp_core.registers[DSP_REG_A1] = source[1];
7132: dsp_core.registers[DSP_REG_A0] = source[2];
7133:
7134: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7135: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7136: }
7137:
7138: static void dsp_mpy_p_x0_x0_b(void)
7139: {
7140: Uint32 source[3];
7141:
7142: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7143:
7144: dsp_core.registers[DSP_REG_B2] = source[0];
7145: dsp_core.registers[DSP_REG_B1] = source[1];
7146: dsp_core.registers[DSP_REG_B0] = source[2];
7147:
7148: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7149: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7150: }
7151:
7152: static void dsp_mpy_m_x0_x0_b(void)
7153: {
7154: Uint32 source[3];
7155:
7156:
7157: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7158:
7159: dsp_core.registers[DSP_REG_B2] = source[0];
7160: dsp_core.registers[DSP_REG_B1] = source[1];
7161: dsp_core.registers[DSP_REG_B0] = source[2];
7162:
7163: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7164: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7165: }
7166:
7167: static void dsp_mpy_p_y0_y0_a(void)
7168: {
7169: Uint32 source[3];
7170:
7171: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7172:
7173: dsp_core.registers[DSP_REG_A2] = source[0];
7174: dsp_core.registers[DSP_REG_A1] = source[1];
7175: dsp_core.registers[DSP_REG_A0] = source[2];
7176:
7177: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7178: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7179: }
7180:
7181: static void dsp_mpy_m_y0_y0_a(void)
7182: {
7183: Uint32 source[3];
7184:
7185: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7186:
7187: dsp_core.registers[DSP_REG_A2] = source[0];
7188: dsp_core.registers[DSP_REG_A1] = source[1];
7189: dsp_core.registers[DSP_REG_A0] = source[2];
7190:
7191: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7192: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7193: }
7194:
7195: static void dsp_mpy_p_y0_y0_b(void)
7196: {
7197: Uint32 source[3];
7198:
7199: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7200:
7201: dsp_core.registers[DSP_REG_B2] = source[0];
7202: dsp_core.registers[DSP_REG_B1] = source[1];
7203: dsp_core.registers[DSP_REG_B0] = source[2];
7204:
7205: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7206: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7207: }
7208:
7209: static void dsp_mpy_m_y0_y0_b(void)
7210: {
7211: Uint32 source[3];
7212:
7213: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7214:
7215: dsp_core.registers[DSP_REG_B2] = source[0];
7216: dsp_core.registers[DSP_REG_B1] = source[1];
7217: dsp_core.registers[DSP_REG_B0] = source[2];
7218:
7219: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7220: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7221: }
7222:
7223: static void dsp_mpy_p_x1_x0_a(void)
7224: {
7225: Uint32 source[3];
7226:
7227: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7228:
7229: dsp_core.registers[DSP_REG_A2] = source[0];
7230: dsp_core.registers[DSP_REG_A1] = source[1];
7231: dsp_core.registers[DSP_REG_A0] = source[2];
7232:
7233: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7234: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7235: }
7236:
7237: static void dsp_mpy_m_x1_x0_a(void)
7238: {
7239: Uint32 source[3];
7240:
7241: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7242:
7243: dsp_core.registers[DSP_REG_A2] = source[0];
7244: dsp_core.registers[DSP_REG_A1] = source[1];
7245: dsp_core.registers[DSP_REG_A0] = source[2];
7246:
7247: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7248: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7249: }
7250:
7251: static void dsp_mpy_p_x1_x0_b(void)
7252: {
7253: Uint32 source[3];
7254:
7255: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7256:
7257: dsp_core.registers[DSP_REG_B2] = source[0];
7258: dsp_core.registers[DSP_REG_B1] = source[1];
7259: dsp_core.registers[DSP_REG_B0] = source[2];
7260:
7261: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7262: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7263: }
7264:
7265: static void dsp_mpy_m_x1_x0_b(void)
7266: {
7267: Uint32 source[3];
7268:
7269: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7270:
7271: dsp_core.registers[DSP_REG_B2] = source[0];
7272: dsp_core.registers[DSP_REG_B1] = source[1];
7273: dsp_core.registers[DSP_REG_B0] = source[2];
7274:
7275: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7276: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7277: }
7278:
7279: static void dsp_mpy_p_y1_y0_a(void)
7280: {
7281: Uint32 source[3];
7282:
7283: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7284:
7285: dsp_core.registers[DSP_REG_A2] = source[0];
7286: dsp_core.registers[DSP_REG_A1] = source[1];
7287: dsp_core.registers[DSP_REG_A0] = source[2];
7288:
7289: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7290: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7291: }
7292:
7293: static void dsp_mpy_m_y1_y0_a(void)
7294: {
7295: Uint32 source[3];
7296:
7297: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7298:
7299: dsp_core.registers[DSP_REG_A2] = source[0];
7300: dsp_core.registers[DSP_REG_A1] = source[1];
7301: dsp_core.registers[DSP_REG_A0] = source[2];
7302:
7303: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7304: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7305: }
7306:
7307: static void dsp_mpy_p_y1_y0_b(void)
7308: {
7309: Uint32 source[3];
7310:
7311: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7312:
7313: dsp_core.registers[DSP_REG_B2] = source[0];
7314: dsp_core.registers[DSP_REG_B1] = source[1];
7315: dsp_core.registers[DSP_REG_B0] = source[2];
7316:
7317: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7318: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7319: }
7320:
7321: static void dsp_mpy_m_y1_y0_b(void)
7322: {
7323: Uint32 source[3];
7324:
7325: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7326:
7327: dsp_core.registers[DSP_REG_B2] = source[0];
7328: dsp_core.registers[DSP_REG_B1] = source[1];
7329: dsp_core.registers[DSP_REG_B0] = source[2];
7330:
7331: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7332: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7333: }
7334:
7335: static void dsp_mpy_p_x0_y1_a(void)
7336: {
7337: Uint32 source[3];
7338:
7339: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7340:
7341: dsp_core.registers[DSP_REG_A2] = source[0];
7342: dsp_core.registers[DSP_REG_A1] = source[1];
7343: dsp_core.registers[DSP_REG_A0] = source[2];
7344:
7345: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7346: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7347: }
7348:
7349: static void dsp_mpy_m_x0_y1_a(void)
7350: {
7351: Uint32 source[3];
7352:
7353: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7354:
7355: dsp_core.registers[DSP_REG_A2] = source[0];
7356: dsp_core.registers[DSP_REG_A1] = source[1];
7357: dsp_core.registers[DSP_REG_A0] = source[2];
7358:
7359: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7360: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7361: }
7362:
7363: static void dsp_mpy_p_x0_y1_b(void)
7364: {
7365: Uint32 source[3];
7366:
7367: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7368:
7369: dsp_core.registers[DSP_REG_B2] = source[0];
7370: dsp_core.registers[DSP_REG_B1] = source[1];
7371: dsp_core.registers[DSP_REG_B0] = source[2];
7372:
7373: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7374: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7375: }
7376:
7377: static void dsp_mpy_m_x0_y1_b(void)
7378: {
7379: Uint32 source[3];
7380:
7381: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7382:
7383: dsp_core.registers[DSP_REG_B2] = source[0];
7384: dsp_core.registers[DSP_REG_B1] = source[1];
7385: dsp_core.registers[DSP_REG_B0] = source[2];
7386:
7387: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7388: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7389: }
7390:
7391: static void dsp_mpy_p_y0_x0_a(void)
7392: {
7393: Uint32 source[3];
7394:
7395: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7396:
7397: dsp_core.registers[DSP_REG_A2] = source[0];
7398: dsp_core.registers[DSP_REG_A1] = source[1];
7399: dsp_core.registers[DSP_REG_A0] = source[2];
7400:
7401: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7402: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7403: }
7404:
7405: static void dsp_mpy_m_y0_x0_a(void)
7406: {
7407: Uint32 source[3];
7408:
7409: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7410:
7411: dsp_core.registers[DSP_REG_A2] = source[0];
7412: dsp_core.registers[DSP_REG_A1] = source[1];
7413: dsp_core.registers[DSP_REG_A0] = source[2];
7414:
7415: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7416: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7417: }
7418:
7419: static void dsp_mpy_p_y0_x0_b(void)
7420: {
7421: Uint32 source[3];
7422:
7423: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7424:
7425: dsp_core.registers[DSP_REG_B2] = source[0];
7426: dsp_core.registers[DSP_REG_B1] = source[1];
7427: dsp_core.registers[DSP_REG_B0] = source[2];
7428:
7429: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7430: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7431: }
7432:
7433: static void dsp_mpy_m_y0_x0_b(void)
7434: {
7435: Uint32 source[3];
7436:
7437: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7438:
7439: dsp_core.registers[DSP_REG_B2] = source[0];
7440: dsp_core.registers[DSP_REG_B1] = source[1];
7441: dsp_core.registers[DSP_REG_B0] = source[2];
7442:
7443: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7444: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7445: }
7446:
7447: static void dsp_mpy_p_x1_y0_a(void)
7448: {
7449: Uint32 source[3];
7450:
7451: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7452:
7453: dsp_core.registers[DSP_REG_A2] = source[0];
7454: dsp_core.registers[DSP_REG_A1] = source[1];
7455: dsp_core.registers[DSP_REG_A0] = source[2];
7456:
7457: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7458: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7459: }
7460:
7461: static void dsp_mpy_m_x1_y0_a(void)
7462: {
7463: Uint32 source[3];
7464:
7465: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7466:
7467: dsp_core.registers[DSP_REG_A2] = source[0];
7468: dsp_core.registers[DSP_REG_A1] = source[1];
7469: dsp_core.registers[DSP_REG_A0] = source[2];
7470:
7471: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7472: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7473: }
7474:
7475: static void dsp_mpy_p_x1_y0_b(void)
7476: {
7477: Uint32 source[3];
7478:
7479: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7480:
7481: dsp_core.registers[DSP_REG_B2] = source[0];
7482: dsp_core.registers[DSP_REG_B1] = source[1];
7483: dsp_core.registers[DSP_REG_B0] = source[2];
7484:
7485: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7486: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7487: }
7488:
7489: static void dsp_mpy_m_x1_y0_b(void)
7490: {
7491: Uint32 source[3];
7492:
7493: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7494:
7495: dsp_core.registers[DSP_REG_B2] = source[0];
7496: dsp_core.registers[DSP_REG_B1] = source[1];
7497: dsp_core.registers[DSP_REG_B0] = source[2];
7498:
7499: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7500: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7501: }
7502:
7503: static void dsp_mpy_p_y1_x1_a(void)
7504: {
7505: Uint32 source[3];
7506:
7507: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7508:
7509: dsp_core.registers[DSP_REG_A2] = source[0];
7510: dsp_core.registers[DSP_REG_A1] = source[1];
7511: dsp_core.registers[DSP_REG_A0] = source[2];
7512:
7513: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7514: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7515: }
7516:
7517: static void dsp_mpy_m_y1_x1_a(void)
7518: {
7519: Uint32 source[3];
7520:
7521: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7522:
7523: dsp_core.registers[DSP_REG_A2] = source[0];
7524: dsp_core.registers[DSP_REG_A1] = source[1];
7525: dsp_core.registers[DSP_REG_A0] = source[2];
7526:
7527: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7528: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7529: }
7530:
7531: static void dsp_mpy_p_y1_x1_b(void)
7532: {
7533: Uint32 source[3];
7534:
7535: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7536:
7537: dsp_core.registers[DSP_REG_B2] = source[0];
7538: dsp_core.registers[DSP_REG_B1] = source[1];
7539: dsp_core.registers[DSP_REG_B0] = source[2];
7540:
7541: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7542: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7543: }
7544:
7545: static void dsp_mpy_m_y1_x1_b(void)
7546: {
7547: Uint32 source[3];
7548:
7549: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7550:
7551: dsp_core.registers[DSP_REG_B2] = source[0];
7552: dsp_core.registers[DSP_REG_B1] = source[1];
7553: dsp_core.registers[DSP_REG_B0] = source[2];
7554:
7555: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7556: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7557: }
7558:
7559: static void dsp_mpyr_p_x0_x0_a(void)
7560: {
7561: Uint32 source[3];
7562:
7563: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7564: dsp_rnd56(source);
7565:
7566: dsp_core.registers[DSP_REG_A2] = source[0];
7567: dsp_core.registers[DSP_REG_A1] = source[1];
7568: dsp_core.registers[DSP_REG_A0] = source[2];
7569:
7570: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7571: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7572: }
7573:
7574: static void dsp_mpyr_m_x0_x0_a(void)
7575: {
7576: Uint32 source[3];
7577:
7578: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7579: dsp_rnd56(source);
7580:
7581: dsp_core.registers[DSP_REG_A2] = source[0];
7582: dsp_core.registers[DSP_REG_A1] = source[1];
7583: dsp_core.registers[DSP_REG_A0] = source[2];
7584:
7585: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7586: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7587: }
7588:
7589: static void dsp_mpyr_p_x0_x0_b(void)
7590: {
7591: Uint32 source[3];
7592:
7593: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7594: dsp_rnd56(source);
7595:
7596: dsp_core.registers[DSP_REG_B2] = source[0];
7597: dsp_core.registers[DSP_REG_B1] = source[1];
7598: dsp_core.registers[DSP_REG_B0] = source[2];
7599:
7600: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7601: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7602: }
7603:
7604: static void dsp_mpyr_m_x0_x0_b(void)
7605: {
7606: Uint32 source[3];
7607:
7608:
7609: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7610: dsp_rnd56(source);
7611:
7612: dsp_core.registers[DSP_REG_B2] = source[0];
7613: dsp_core.registers[DSP_REG_B1] = source[1];
7614: dsp_core.registers[DSP_REG_B0] = source[2];
7615:
7616: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7617: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7618: }
7619:
7620: static void dsp_mpyr_p_y0_y0_a(void)
7621: {
7622: Uint32 source[3];
7623:
7624: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7625: dsp_rnd56(source);
7626:
7627: dsp_core.registers[DSP_REG_A2] = source[0];
7628: dsp_core.registers[DSP_REG_A1] = source[1];
7629: dsp_core.registers[DSP_REG_A0] = source[2];
7630:
7631: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7632: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7633: }
7634:
7635: static void dsp_mpyr_m_y0_y0_a(void)
7636: {
7637: Uint32 source[3];
7638:
7639: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7640: dsp_rnd56(source);
7641:
7642: dsp_core.registers[DSP_REG_A2] = source[0];
7643: dsp_core.registers[DSP_REG_A1] = source[1];
7644: dsp_core.registers[DSP_REG_A0] = source[2];
7645:
7646: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7647: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7648: }
7649:
7650: static void dsp_mpyr_p_y0_y0_b(void)
7651: {
7652: Uint32 source[3];
7653:
7654: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7655: dsp_rnd56(source);
7656:
7657: dsp_core.registers[DSP_REG_B2] = source[0];
7658: dsp_core.registers[DSP_REG_B1] = source[1];
7659: dsp_core.registers[DSP_REG_B0] = source[2];
7660:
7661: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7662: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7663: }
7664:
7665: static void dsp_mpyr_m_y0_y0_b(void)
7666: {
7667: Uint32 source[3];
7668:
7669: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7670: dsp_rnd56(source);
7671:
7672: dsp_core.registers[DSP_REG_B2] = source[0];
7673: dsp_core.registers[DSP_REG_B1] = source[1];
7674: dsp_core.registers[DSP_REG_B0] = source[2];
7675:
7676: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7677: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7678: }
7679:
7680: static void dsp_mpyr_p_x1_x0_a(void)
7681: {
7682: Uint32 source[3];
7683:
7684: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7685: dsp_rnd56(source);
7686:
7687: dsp_core.registers[DSP_REG_A2] = source[0];
7688: dsp_core.registers[DSP_REG_A1] = source[1];
7689: dsp_core.registers[DSP_REG_A0] = source[2];
7690:
7691: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7692: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7693: }
7694:
7695: static void dsp_mpyr_m_x1_x0_a(void)
7696: {
7697: Uint32 source[3];
7698:
7699: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7700: dsp_rnd56(source);
7701:
7702: dsp_core.registers[DSP_REG_A2] = source[0];
7703: dsp_core.registers[DSP_REG_A1] = source[1];
7704: dsp_core.registers[DSP_REG_A0] = source[2];
7705:
7706: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7707: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7708: }
7709:
7710: static void dsp_mpyr_p_x1_x0_b(void)
7711: {
7712: Uint32 source[3];
7713:
7714: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7715: dsp_rnd56(source);
7716:
7717: dsp_core.registers[DSP_REG_B2] = source[0];
7718: dsp_core.registers[DSP_REG_B1] = source[1];
7719: dsp_core.registers[DSP_REG_B0] = source[2];
7720:
7721: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7722: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7723: }
7724:
7725: static void dsp_mpyr_m_x1_x0_b(void)
7726: {
7727: Uint32 source[3];
7728:
7729: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7730: dsp_rnd56(source);
7731:
7732: dsp_core.registers[DSP_REG_B2] = source[0];
7733: dsp_core.registers[DSP_REG_B1] = source[1];
7734: dsp_core.registers[DSP_REG_B0] = source[2];
7735:
7736: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7737: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7738: }
7739:
7740: static void dsp_mpyr_p_y1_y0_a(void)
7741: {
7742: Uint32 source[3];
7743:
7744: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7745: dsp_rnd56(source);
7746:
7747: dsp_core.registers[DSP_REG_A2] = source[0];
7748: dsp_core.registers[DSP_REG_A1] = source[1];
7749: dsp_core.registers[DSP_REG_A0] = source[2];
7750:
7751: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7752: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7753: }
7754:
7755: static void dsp_mpyr_m_y1_y0_a(void)
7756: {
7757: Uint32 source[3];
7758:
7759: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7760: dsp_rnd56(source);
7761:
7762: dsp_core.registers[DSP_REG_A2] = source[0];
7763: dsp_core.registers[DSP_REG_A1] = source[1];
7764: dsp_core.registers[DSP_REG_A0] = source[2];
7765:
7766: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7767: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7768: }
7769:
7770: static void dsp_mpyr_p_y1_y0_b(void)
7771: {
7772: Uint32 source[3];
7773:
7774: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7775: dsp_rnd56(source);
7776:
7777: dsp_core.registers[DSP_REG_B2] = source[0];
7778: dsp_core.registers[DSP_REG_B1] = source[1];
7779: dsp_core.registers[DSP_REG_B0] = source[2];
7780:
7781: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7782: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7783: }
7784:
7785: static void dsp_mpyr_m_y1_y0_b(void)
7786: {
7787: Uint32 source[3];
7788:
7789: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7790: dsp_rnd56(source);
7791:
7792: dsp_core.registers[DSP_REG_B2] = source[0];
7793: dsp_core.registers[DSP_REG_B1] = source[1];
7794: dsp_core.registers[DSP_REG_B0] = source[2];
7795:
7796: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7797: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7798: }
7799:
7800: static void dsp_mpyr_p_x0_y1_a(void)
7801: {
7802: Uint32 source[3];
7803:
7804: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7805: dsp_rnd56(source);
7806:
7807: dsp_core.registers[DSP_REG_A2] = source[0];
7808: dsp_core.registers[DSP_REG_A1] = source[1];
7809: dsp_core.registers[DSP_REG_A0] = source[2];
7810:
7811: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7812: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7813: }
7814:
7815: static void dsp_mpyr_m_x0_y1_a(void)
7816: {
7817: Uint32 source[3];
7818:
7819: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7820: dsp_rnd56(source);
7821:
7822: dsp_core.registers[DSP_REG_A2] = source[0];
7823: dsp_core.registers[DSP_REG_A1] = source[1];
7824: dsp_core.registers[DSP_REG_A0] = source[2];
7825:
7826: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7827: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7828: }
7829:
7830: static void dsp_mpyr_p_x0_y1_b(void)
7831: {
7832: Uint32 source[3];
7833:
7834: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7835: dsp_rnd56(source);
7836:
7837: dsp_core.registers[DSP_REG_B2] = source[0];
7838: dsp_core.registers[DSP_REG_B1] = source[1];
7839: dsp_core.registers[DSP_REG_B0] = source[2];
7840:
7841: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7842: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7843: }
7844:
7845: static void dsp_mpyr_m_x0_y1_b(void)
7846: {
7847: Uint32 source[3];
7848:
7849: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7850: dsp_rnd56(source);
7851:
7852: dsp_core.registers[DSP_REG_B2] = source[0];
7853: dsp_core.registers[DSP_REG_B1] = source[1];
7854: dsp_core.registers[DSP_REG_B0] = source[2];
7855:
7856: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7857: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7858: }
7859:
7860: static void dsp_mpyr_p_y0_x0_a(void)
7861: {
7862: Uint32 source[3];
7863:
7864: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7865: dsp_rnd56(source);
7866:
7867: dsp_core.registers[DSP_REG_A2] = source[0];
7868: dsp_core.registers[DSP_REG_A1] = source[1];
7869: dsp_core.registers[DSP_REG_A0] = source[2];
7870:
7871: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7872: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7873: }
7874:
7875: static void dsp_mpyr_m_y0_x0_a(void)
7876: {
7877: Uint32 source[3];
7878:
7879: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7880: dsp_rnd56(source);
7881:
7882: dsp_core.registers[DSP_REG_A2] = source[0];
7883: dsp_core.registers[DSP_REG_A1] = source[1];
7884: dsp_core.registers[DSP_REG_A0] = source[2];
7885:
7886: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7887: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7888: }
7889:
7890: static void dsp_mpyr_p_y0_x0_b(void)
7891: {
7892: Uint32 source[3];
7893:
7894: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7895: dsp_rnd56(source);
7896:
7897: dsp_core.registers[DSP_REG_B2] = source[0];
7898: dsp_core.registers[DSP_REG_B1] = source[1];
7899: dsp_core.registers[DSP_REG_B0] = source[2];
7900:
7901: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7902: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7903: }
7904:
7905: static void dsp_mpyr_m_y0_x0_b(void)
7906: {
7907: Uint32 source[3];
7908:
7909: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7910: dsp_rnd56(source);
7911:
7912: dsp_core.registers[DSP_REG_B2] = source[0];
7913: dsp_core.registers[DSP_REG_B1] = source[1];
7914: dsp_core.registers[DSP_REG_B0] = source[2];
7915:
7916: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7917: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7918: }
7919:
7920: static void dsp_mpyr_p_x1_y0_a(void)
7921: {
7922: Uint32 source[3];
7923:
7924: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7925: dsp_rnd56(source);
7926:
7927: dsp_core.registers[DSP_REG_A2] = source[0];
7928: dsp_core.registers[DSP_REG_A1] = source[1];
7929: dsp_core.registers[DSP_REG_A0] = source[2];
7930:
7931: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7932: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7933: }
7934:
7935: static void dsp_mpyr_m_x1_y0_a(void)
7936: {
7937: Uint32 source[3];
7938:
7939: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7940: dsp_rnd56(source);
7941:
7942: dsp_core.registers[DSP_REG_A2] = source[0];
7943: dsp_core.registers[DSP_REG_A1] = source[1];
7944: dsp_core.registers[DSP_REG_A0] = source[2];
7945:
7946: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7947: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7948: }
7949:
7950: static void dsp_mpyr_p_x1_y0_b(void)
7951: {
7952: Uint32 source[3];
7953:
7954: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7955: dsp_rnd56(source);
7956:
7957: dsp_core.registers[DSP_REG_B2] = source[0];
7958: dsp_core.registers[DSP_REG_B1] = source[1];
7959: dsp_core.registers[DSP_REG_B0] = source[2];
7960:
7961: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7962: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7963: }
7964:
7965: static void dsp_mpyr_m_x1_y0_b(void)
7966: {
7967: Uint32 source[3];
7968:
7969: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7970: dsp_rnd56(source);
7971:
7972: dsp_core.registers[DSP_REG_B2] = source[0];
7973: dsp_core.registers[DSP_REG_B1] = source[1];
7974: dsp_core.registers[DSP_REG_B0] = source[2];
7975:
7976: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7977: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7978: }
7979:
7980: static void dsp_mpyr_p_y1_x1_a(void)
7981: {
7982: Uint32 source[3];
7983:
7984: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7985: dsp_rnd56(source);
7986:
7987: dsp_core.registers[DSP_REG_A2] = source[0];
7988: dsp_core.registers[DSP_REG_A1] = source[1];
7989: dsp_core.registers[DSP_REG_A0] = source[2];
7990:
7991: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7992: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7993: }
7994:
7995: static void dsp_mpyr_m_y1_x1_a(void)
7996: {
7997: Uint32 source[3];
7998:
7999: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
8000: dsp_rnd56(source);
8001:
8002: dsp_core.registers[DSP_REG_A2] = source[0];
8003: dsp_core.registers[DSP_REG_A1] = source[1];
8004: dsp_core.registers[DSP_REG_A0] = source[2];
8005:
8006: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8007: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8008: }
8009:
8010: static void dsp_mpyr_p_y1_x1_b(void)
8011: {
8012: Uint32 source[3];
8013:
8014: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
8015: dsp_rnd56(source);
8016:
8017: dsp_core.registers[DSP_REG_B2] = source[0];
8018: dsp_core.registers[DSP_REG_B1] = source[1];
8019: dsp_core.registers[DSP_REG_B0] = source[2];
8020:
8021: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8022: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8023: }
8024:
8025: static void dsp_mpyr_m_y1_x1_b(void)
8026: {
8027: Uint32 source[3];
8028:
8029: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
8030: dsp_rnd56(source);
8031:
8032: dsp_core.registers[DSP_REG_B2] = source[0];
8033: dsp_core.registers[DSP_REG_B1] = source[1];
8034: dsp_core.registers[DSP_REG_B0] = source[2];
8035:
8036: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8037: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8038: }
8039:
8040: static void dsp_neg_a(void)
8041: {
8042: Uint32 source[3], dest[3], overflowed;
8043:
8044: source[0] = dsp_core.registers[DSP_REG_A2];
8045: source[1] = dsp_core.registers[DSP_REG_A1];
8046: source[2] = dsp_core.registers[DSP_REG_A0];
8047:
8048: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8049:
8050: dest[0] = dest[1] = dest[2] = 0;
8051:
8052: dsp_sub56(source, dest);
8053:
8054: dsp_core.registers[DSP_REG_A2] = dest[0];
8055: dsp_core.registers[DSP_REG_A1] = dest[1];
8056: dsp_core.registers[DSP_REG_A0] = dest[2];
8057:
8058: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8059: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8060:
8061: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8062: }
8063:
8064: static void dsp_neg_b(void)
8065: {
8066: Uint32 source[3], dest[3], overflowed;
8067:
8068: source[0] = dsp_core.registers[DSP_REG_B2];
8069: source[1] = dsp_core.registers[DSP_REG_B1];
8070: source[2] = dsp_core.registers[DSP_REG_B0];
8071:
8072: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8073:
8074: dest[0] = dest[1] = dest[2] = 0;
8075:
8076: dsp_sub56(source, dest);
8077:
8078: dsp_core.registers[DSP_REG_B2] = dest[0];
8079: dsp_core.registers[DSP_REG_B1] = dest[1];
8080: dsp_core.registers[DSP_REG_B0] = dest[2];
8081:
8082: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8083: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8084:
8085: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8086: }
8087:
8088: static void dsp_nop(void)
8089: {
8090: }
8091:
8092: static void dsp_not_a(void)
8093: {
8094: dsp_core.registers[DSP_REG_A1] = ~dsp_core.registers[DSP_REG_A1];
8095: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8096:
8097: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8098: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8099: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8100: }
8101:
8102: static void dsp_not_b(void)
8103: {
8104: dsp_core.registers[DSP_REG_B1] = ~dsp_core.registers[DSP_REG_B1];
8105: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8106:
8107: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8108: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8109: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8110: }
8111:
8112: static void dsp_or_x0_a(void)
8113: {
8114: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X0];
8115: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8116:
8117: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8118: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8119: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8120: }
8121:
8122: static void dsp_or_x0_b(void)
8123: {
8124: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X0];
8125: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8126:
8127: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8128: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8129: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8130: }
8131:
8132: static void dsp_or_y0_a(void)
8133: {
8134: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y0];
8135: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8136:
8137: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8138: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8139: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8140: }
8141:
8142: static void dsp_or_y0_b(void)
8143: {
8144: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y0];
8145: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8146:
8147: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8148: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8149: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8150: }
8151:
8152: static void dsp_or_x1_a(void)
8153: {
8154: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X1];
8155: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8156:
8157: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8158: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8159: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8160: }
8161:
8162: static void dsp_or_x1_b(void)
8163: {
8164: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X1];
8165: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8166:
8167: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8168: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8169: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8170: }
8171:
8172: static void dsp_or_y1_a(void)
8173: {
8174: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y1];
8175: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8176:
8177: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8178: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8179: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8180: }
8181:
8182: static void dsp_or_y1_b(void)
8183: {
8184: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y1];
8185: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8186:
8187: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8188: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8189: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8190: }
8191:
8192: static void dsp_rnd_a(void)
8193: {
8194: Uint32 dest[3];
8195:
8196: dest[0] = dsp_core.registers[DSP_REG_A2];
8197: dest[1] = dsp_core.registers[DSP_REG_A1];
8198: dest[2] = dsp_core.registers[DSP_REG_A0];
8199:
8200: dsp_rnd56(dest);
8201:
8202: dsp_core.registers[DSP_REG_A2] = dest[0];
8203: dsp_core.registers[DSP_REG_A1] = dest[1];
8204: dsp_core.registers[DSP_REG_A0] = dest[2];
8205:
8206: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8207: }
8208:
8209: static void dsp_rnd_b(void)
8210: {
8211: Uint32 dest[3];
8212:
8213: dest[0] = dsp_core.registers[DSP_REG_B2];
8214: dest[1] = dsp_core.registers[DSP_REG_B1];
8215: dest[2] = dsp_core.registers[DSP_REG_B0];
8216:
8217: dsp_rnd56(dest);
8218:
8219: dsp_core.registers[DSP_REG_B2] = dest[0];
8220: dsp_core.registers[DSP_REG_B1] = dest[1];
8221: dsp_core.registers[DSP_REG_B0] = dest[2];
8222:
8223: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8224: }
8225:
8226: static void dsp_rol_a(void)
8227: {
8228: Uint32 newcarry;
8229:
8230: newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
8231:
8232: dsp_core.registers[DSP_REG_A1] <<= 1;
8233: dsp_core.registers[DSP_REG_A1] |= newcarry;
8234: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
8235:
8236: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8237: dsp_core.registers[DSP_REG_SR] |= newcarry;
8238: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8239: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8240: }
8241:
8242: static void dsp_rol_b(void)
8243: {
8244: Uint32 newcarry;
8245:
8246: newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
8247:
8248: dsp_core.registers[DSP_REG_B1] <<= 1;
8249: dsp_core.registers[DSP_REG_B1] |= newcarry;
8250: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
8251:
8252: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8253: dsp_core.registers[DSP_REG_SR] |= newcarry;
8254: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8255: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8256: }
8257:
8258: static void dsp_ror_a(void)
8259: {
8260: Uint32 newcarry;
8261:
8262: newcarry = dsp_core.registers[DSP_REG_A1] & 1;
8263:
8264: dsp_core.registers[DSP_REG_A1] >>= 1;
8265: dsp_core.registers[DSP_REG_A1] |= newcarry<<23;
8266:
8267: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8268: dsp_core.registers[DSP_REG_SR] |= newcarry;
8269: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8270: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8271: }
8272:
8273: static void dsp_ror_b(void)
8274: {
8275: Uint32 newcarry;
8276:
8277: newcarry = dsp_core.registers[DSP_REG_B1] & 1;
8278:
8279: dsp_core.registers[DSP_REG_B1] >>= 1;
8280: dsp_core.registers[DSP_REG_B1] |= newcarry<<23;
8281:
8282: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8283: dsp_core.registers[DSP_REG_SR] |= newcarry;
8284: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8285: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8286: }
8287:
8288: static void dsp_sbc_x_a(void)
8289: {
8290: Uint32 source[3], dest[3], curcarry;
8291: Uint16 newsr;
8292:
8293: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8294:
8295: dest[2] = dsp_core.registers[DSP_REG_A0];
8296: dest[1] = dsp_core.registers[DSP_REG_A1];
8297: dest[0] = dsp_core.registers[DSP_REG_A2];
8298:
8299: source[2] = dsp_core.registers[DSP_REG_X0];
8300: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8301: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8302:
8303: newsr = dsp_sub56(source, dest);
8304:
8305: if (curcarry) {
8306: source[0]=0; source[1]=0; source[2]=1;
8307: newsr |= dsp_sub56(source, dest);
8308: }
8309:
8310: dsp_core.registers[DSP_REG_A2] = dest[0];
8311: dsp_core.registers[DSP_REG_A1] = dest[1];
8312: dsp_core.registers[DSP_REG_A0] = dest[2];
8313:
8314: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8315:
8316: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8317: dsp_core.registers[DSP_REG_SR] |= newsr;
8318: }
8319:
8320: static void dsp_sbc_x_b(void)
8321: {
8322: Uint32 source[3], dest[3], curcarry;
8323: Uint16 newsr;
8324:
8325: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8326:
8327: dest[2] = dsp_core.registers[DSP_REG_B0];
8328: dest[1] = dsp_core.registers[DSP_REG_B1];
8329: dest[0] = dsp_core.registers[DSP_REG_B2];
8330:
8331: source[2] = dsp_core.registers[DSP_REG_X0];
8332: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8333: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8334:
8335: newsr = dsp_sub56(source, dest);
8336:
8337: if (curcarry) {
8338: source[0]=0; source[1]=0; source[2]=1;
8339: newsr |= dsp_sub56(source, dest);
8340: }
8341:
8342: dsp_core.registers[DSP_REG_B2] = dest[0];
8343: dsp_core.registers[DSP_REG_B1] = dest[1];
8344: dsp_core.registers[DSP_REG_B0] = dest[2];
8345:
8346: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8347:
8348: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8349: dsp_core.registers[DSP_REG_SR] |= newsr;
8350: }
8351:
8352: static void dsp_sbc_y_a(void)
8353: {
8354: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 8355: Uint16 newsr;
1.1 root 8356:
1.1.1.6 root 8357: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8358:
8359: dest[2] = dsp_core.registers[DSP_REG_A0];
8360: dest[1] = dsp_core.registers[DSP_REG_A1];
8361: dest[0] = dsp_core.registers[DSP_REG_A2];
8362:
8363: source[2] = dsp_core.registers[DSP_REG_Y0];
8364: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8365: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8366:
8367: newsr = dsp_sub56(source, dest);
8368:
8369: if (curcarry) {
8370: source[0]=0; source[1]=0; source[2]=1;
8371: newsr |= dsp_sub56(source, dest);
8372: }
8373:
8374: dsp_core.registers[DSP_REG_A2] = dest[0];
8375: dsp_core.registers[DSP_REG_A1] = dest[1];
8376: dsp_core.registers[DSP_REG_A0] = dest[2];
8377:
8378: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8379:
8380: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8381: dsp_core.registers[DSP_REG_SR] |= newsr;
8382: }
8383:
8384: static void dsp_sbc_y_b(void)
8385: {
8386: Uint32 source[3], dest[3], curcarry;
8387: Uint16 newsr;
8388:
8389: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8390:
8391: dest[2] = dsp_core.registers[DSP_REG_B0];
8392: dest[1] = dsp_core.registers[DSP_REG_B1];
8393: dest[0] = dsp_core.registers[DSP_REG_B2];
8394:
8395: source[2] = dsp_core.registers[DSP_REG_Y0];
8396: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8397: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8398:
8399: newsr = dsp_sub56(source, dest);
8400:
8401: if (curcarry) {
8402: source[0]=0; source[1]=0; source[2]=1;
8403: newsr |= dsp_sub56(source, dest);
1.1 root 8404: }
8405:
1.1.1.6 root 8406: dsp_core.registers[DSP_REG_B2] = dest[0];
8407: dsp_core.registers[DSP_REG_B1] = dest[1];
8408: dsp_core.registers[DSP_REG_B0] = dest[2];
8409:
8410: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8411:
8412: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8413: dsp_core.registers[DSP_REG_SR] |= newsr;
8414: }
8415:
8416: static void dsp_sub_b_a(void)
8417: {
8418: Uint32 source[3], dest[3];
8419: Uint16 newsr;
8420:
8421: dest[2] = dsp_core.registers[DSP_REG_A0];
8422: dest[1] = dsp_core.registers[DSP_REG_A1];
8423: dest[0] = dsp_core.registers[DSP_REG_A2];
8424:
8425: source[2] = dsp_core.registers[DSP_REG_B0];
8426: source[1] = dsp_core.registers[DSP_REG_B1];
8427: source[0] = dsp_core.registers[DSP_REG_B2];
8428:
1.1 root 8429: newsr = dsp_sub56(source, dest);
8430:
1.1.1.6 root 8431: dsp_core.registers[DSP_REG_A2] = dest[0];
8432: dsp_core.registers[DSP_REG_A1] = dest[1];
8433: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8434:
1.1.1.6 root 8435: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8436:
1.1.1.6 root 8437: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8438: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8439: }
8440:
1.1.1.6 root 8441: static void dsp_sub_a_b(void)
1.1 root 8442: {
1.1.1.6 root 8443: Uint32 source[3], dest[3];
1.1.1.2 root 8444: Uint16 newsr;
1.1 root 8445:
1.1.1.6 root 8446: dest[2] = dsp_core.registers[DSP_REG_B0];
8447: dest[1] = dsp_core.registers[DSP_REG_B1];
8448: dest[0] = dsp_core.registers[DSP_REG_B2];
8449:
8450: source[2] = dsp_core.registers[DSP_REG_A0];
8451: source[1] = dsp_core.registers[DSP_REG_A1];
8452: source[0] = dsp_core.registers[DSP_REG_A2];
8453:
8454: newsr = dsp_sub56(source, dest);
8455:
8456: dsp_core.registers[DSP_REG_B2] = dest[0];
8457: dsp_core.registers[DSP_REG_B1] = dest[1];
8458: dsp_core.registers[DSP_REG_B0] = dest[2];
8459:
8460: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8461:
8462: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8463: dsp_core.registers[DSP_REG_SR] |= newsr;
8464: }
8465:
8466: static void dsp_sub_x_a(void)
8467: {
8468: Uint32 source[3], dest[3];
8469: Uint16 newsr;
8470:
8471: dest[2] = dsp_core.registers[DSP_REG_A0];
8472: dest[1] = dsp_core.registers[DSP_REG_A1];
8473: dest[0] = dsp_core.registers[DSP_REG_A2];
8474:
8475: source[2] = dsp_core.registers[DSP_REG_X0];
8476: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8477: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8478:
8479: newsr = dsp_sub56(source, dest);
8480:
8481: dsp_core.registers[DSP_REG_A2] = dest[0];
8482: dsp_core.registers[DSP_REG_A1] = dest[1];
8483: dsp_core.registers[DSP_REG_A0] = dest[2];
8484:
8485: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8486:
8487: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8488: dsp_core.registers[DSP_REG_SR] |= newsr;
8489: }
8490:
8491: static void dsp_sub_x_b(void)
8492: {
8493: Uint32 source[3], dest[3];
8494: Uint16 newsr;
8495:
8496: dest[2] = dsp_core.registers[DSP_REG_B0];
8497: dest[1] = dsp_core.registers[DSP_REG_B1];
8498: dest[0] = dsp_core.registers[DSP_REG_B2];
8499:
8500: source[2] = dsp_core.registers[DSP_REG_X0];
8501: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8502: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8503:
8504: newsr = dsp_sub56(source, dest);
8505:
8506: dsp_core.registers[DSP_REG_B2] = dest[0];
8507: dsp_core.registers[DSP_REG_B1] = dest[1];
8508: dsp_core.registers[DSP_REG_B0] = dest[2];
8509:
8510: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8511:
8512: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8513: dsp_core.registers[DSP_REG_SR] |= newsr;
8514: }
8515:
8516: static void dsp_sub_y_a(void)
8517: {
8518: Uint32 source[3], dest[3];
8519: Uint16 newsr;
8520:
8521: dest[2] = dsp_core.registers[DSP_REG_A0];
8522: dest[1] = dsp_core.registers[DSP_REG_A1];
8523: dest[0] = dsp_core.registers[DSP_REG_A2];
8524:
8525: source[2] = dsp_core.registers[DSP_REG_Y0];
8526: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8527: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8528:
8529: newsr = dsp_sub56(source, dest);
8530:
8531: dsp_core.registers[DSP_REG_A2] = dest[0];
8532: dsp_core.registers[DSP_REG_A1] = dest[1];
8533: dsp_core.registers[DSP_REG_A0] = dest[2];
8534:
8535: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8536:
8537: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8538: dsp_core.registers[DSP_REG_SR] |= newsr;
8539: }
8540:
8541: static void dsp_sub_y_b(void)
8542: {
8543: Uint32 source[3], dest[3];
8544: Uint16 newsr;
8545:
8546: dest[2] = dsp_core.registers[DSP_REG_B0];
8547: dest[1] = dsp_core.registers[DSP_REG_B1];
8548: dest[0] = dsp_core.registers[DSP_REG_B2];
8549:
8550: source[2] = dsp_core.registers[DSP_REG_Y0];
8551: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8552: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8553:
8554: newsr = dsp_sub56(source, dest);
8555:
8556: dsp_core.registers[DSP_REG_B2] = dest[0];
8557: dsp_core.registers[DSP_REG_B1] = dest[1];
8558: dsp_core.registers[DSP_REG_B0] = dest[2];
8559:
8560: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8561:
8562: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8563: dsp_core.registers[DSP_REG_SR] |= newsr;
8564: }
8565:
8566: static void dsp_sub_x0_a(void)
8567: {
8568: Uint32 source[3], dest[3];
8569: Uint16 newsr;
8570:
8571: dest[2] = dsp_core.registers[DSP_REG_A0];
8572: dest[1] = dsp_core.registers[DSP_REG_A1];
8573: dest[0] = dsp_core.registers[DSP_REG_A2];
8574:
8575: source[2] = 0;
8576: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 8577: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8578:
8579: newsr = dsp_sub56(source, dest);
8580:
8581: dsp_core.registers[DSP_REG_A2] = dest[0];
8582: dsp_core.registers[DSP_REG_A1] = dest[1];
8583: dsp_core.registers[DSP_REG_A0] = dest[2];
8584:
8585: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8586:
8587: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8588: dsp_core.registers[DSP_REG_SR] |= newsr;
8589: }
8590:
8591: static void dsp_sub_x0_b(void)
8592: {
8593: Uint32 source[3], dest[3];
8594: Uint16 newsr;
8595:
8596: dest[2] = dsp_core.registers[DSP_REG_B0];
8597: dest[1] = dsp_core.registers[DSP_REG_B1];
8598: dest[0] = dsp_core.registers[DSP_REG_B2];
8599:
8600: source[2] = 0;
8601: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 8602: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8603:
8604: newsr = dsp_sub56(source, dest);
8605:
8606: dsp_core.registers[DSP_REG_B2] = dest[0];
8607: dsp_core.registers[DSP_REG_B1] = dest[1];
8608: dsp_core.registers[DSP_REG_B0] = dest[2];
8609:
8610: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8611:
8612: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8613: dsp_core.registers[DSP_REG_SR] |= newsr;
8614: }
8615:
8616: static void dsp_sub_y0_a(void)
8617: {
8618: Uint32 source[3], dest[3];
8619: Uint16 newsr;
8620:
8621: dest[2] = dsp_core.registers[DSP_REG_A0];
8622: dest[1] = dsp_core.registers[DSP_REG_A1];
8623: dest[0] = dsp_core.registers[DSP_REG_A2];
8624:
8625: source[2] = 0;
8626: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 8627: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8628:
8629: newsr = dsp_sub56(source, dest);
1.1 root 8630:
1.1.1.6 root 8631: dsp_core.registers[DSP_REG_A2] = dest[0];
8632: dsp_core.registers[DSP_REG_A1] = dest[1];
8633: dsp_core.registers[DSP_REG_A0] = dest[2];
8634:
8635: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8636:
8637: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8638: dsp_core.registers[DSP_REG_SR] |= newsr;
8639: }
8640:
8641: static void dsp_sub_y0_b(void)
8642: {
8643: Uint32 source[3], dest[3];
8644: Uint16 newsr;
8645:
8646: dest[2] = dsp_core.registers[DSP_REG_B0];
8647: dest[1] = dsp_core.registers[DSP_REG_B1];
8648: dest[0] = dsp_core.registers[DSP_REG_B2];
8649:
8650: source[2] = 0;
8651: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 8652: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8653:
8654: newsr = dsp_sub56(source, dest);
8655:
8656: dsp_core.registers[DSP_REG_B2] = dest[0];
8657: dsp_core.registers[DSP_REG_B1] = dest[1];
8658: dsp_core.registers[DSP_REG_B0] = dest[2];
8659:
8660: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8661:
8662: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8663: dsp_core.registers[DSP_REG_SR] |= newsr;
8664: }
8665:
8666: static void dsp_sub_x1_a(void)
8667: {
8668: Uint32 source[3], dest[3];
8669: Uint16 newsr;
8670:
8671: dest[2] = dsp_core.registers[DSP_REG_A0];
8672: dest[1] = dsp_core.registers[DSP_REG_A1];
8673: dest[0] = dsp_core.registers[DSP_REG_A2];
8674:
8675: source[2] = 0;
8676: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8677: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8678:
8679: newsr = dsp_sub56(source, dest);
8680:
8681: dsp_core.registers[DSP_REG_A2] = dest[0];
8682: dsp_core.registers[DSP_REG_A1] = dest[1];
8683: dsp_core.registers[DSP_REG_A0] = dest[2];
8684:
8685: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8686:
8687: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8688: dsp_core.registers[DSP_REG_SR] |= newsr;
8689: }
8690:
8691: static void dsp_sub_x1_b(void)
8692: {
8693: Uint32 source[3], dest[3];
8694: Uint16 newsr;
8695:
8696: dest[2] = dsp_core.registers[DSP_REG_B0];
8697: dest[1] = dsp_core.registers[DSP_REG_B1];
8698: dest[0] = dsp_core.registers[DSP_REG_B2];
8699:
8700: source[2] = 0;
8701: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8702: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8703:
8704: newsr = dsp_sub56(source, dest);
8705:
8706: dsp_core.registers[DSP_REG_B2] = dest[0];
8707: dsp_core.registers[DSP_REG_B1] = dest[1];
8708: dsp_core.registers[DSP_REG_B0] = dest[2];
8709:
8710: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8711:
8712: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8713: dsp_core.registers[DSP_REG_SR] |= newsr;
8714: }
8715:
8716: static void dsp_sub_y1_a(void)
8717: {
8718: Uint32 source[3], dest[3];
8719: Uint16 newsr;
8720:
8721: dest[2] = dsp_core.registers[DSP_REG_A0];
8722: dest[1] = dsp_core.registers[DSP_REG_A1];
8723: dest[0] = dsp_core.registers[DSP_REG_A2];
8724:
8725: source[2] = 0;
8726: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8727: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8728:
8729: newsr = dsp_sub56(source, dest);
8730:
8731: dsp_core.registers[DSP_REG_A2] = dest[0];
8732: dsp_core.registers[DSP_REG_A1] = dest[1];
8733: dsp_core.registers[DSP_REG_A0] = dest[2];
8734:
8735: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8736:
8737: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8738: dsp_core.registers[DSP_REG_SR] |= newsr;
8739: }
8740:
8741: static void dsp_sub_y1_b(void)
8742: {
8743: Uint32 source[3], dest[3];
8744: Uint16 newsr;
8745:
8746: dest[2] = dsp_core.registers[DSP_REG_B0];
8747: dest[1] = dsp_core.registers[DSP_REG_B1];
8748: dest[0] = dsp_core.registers[DSP_REG_B2];
8749:
8750: source[2] = 0;
8751: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8752: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8753:
8754: newsr = dsp_sub56(source, dest);
8755:
8756: dsp_core.registers[DSP_REG_B2] = dest[0];
8757: dsp_core.registers[DSP_REG_B1] = dest[1];
8758: dsp_core.registers[DSP_REG_B0] = dest[2];
8759:
8760: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8761:
8762: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8763: dsp_core.registers[DSP_REG_SR] |= newsr;
8764: }
8765:
8766: static void dsp_subl_a(void)
8767: {
8768: Uint32 source[3], dest[3];
8769: Uint16 newsr;
8770:
8771: dest[0] = dsp_core.registers[DSP_REG_A2];
8772: dest[1] = dsp_core.registers[DSP_REG_A1];
8773: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 8774: newsr = dsp_asl56(dest);
8775:
1.1.1.6 root 8776: source[0] = dsp_core.registers[DSP_REG_B2];
8777: source[1] = dsp_core.registers[DSP_REG_B1];
8778: source[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 8779: newsr |= dsp_sub56(source, dest);
8780:
1.1.1.6 root 8781: dsp_core.registers[DSP_REG_A2] = dest[0];
8782: dsp_core.registers[DSP_REG_A1] = dest[1];
8783: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8784:
1.1.1.6 root 8785: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8786:
1.1.1.6 root 8787: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8788: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8789: }
8790:
1.1.1.6 root 8791: static void dsp_subl_b(void)
1.1 root 8792: {
1.1.1.6 root 8793: Uint32 source[3], dest[3];
1.1.1.2 root 8794: Uint16 newsr;
1.1 root 8795:
1.1.1.6 root 8796: dest[0] = dsp_core.registers[DSP_REG_B2];
8797: dest[1] = dsp_core.registers[DSP_REG_B1];
8798: dest[2] = dsp_core.registers[DSP_REG_B0];
8799: newsr = dsp_asl56(dest);
1.1 root 8800:
1.1.1.6 root 8801: source[0] = dsp_core.registers[DSP_REG_A2];
8802: source[1] = dsp_core.registers[DSP_REG_A1];
8803: source[2] = dsp_core.registers[DSP_REG_A0];
8804: newsr |= dsp_sub56(source, dest);
8805:
8806: dsp_core.registers[DSP_REG_B2] = dest[0];
8807: dsp_core.registers[DSP_REG_B1] = dest[1];
8808: dsp_core.registers[DSP_REG_B0] = dest[2];
8809:
8810: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8811:
8812: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8813: dsp_core.registers[DSP_REG_SR] |= newsr;
8814: }
8815:
8816: static void dsp_subr_a(void)
8817: {
8818: Uint32 source[3], dest[3];
8819: Uint16 newsr;
8820:
8821: dest[0] = dsp_core.registers[DSP_REG_A2];
8822: dest[1] = dsp_core.registers[DSP_REG_A1];
8823: dest[2] = dsp_core.registers[DSP_REG_A0];
8824:
1.1 root 8825: newsr = dsp_asr56(dest);
8826:
1.1.1.6 root 8827: source[0] = dsp_core.registers[DSP_REG_B2];
8828: source[1] = dsp_core.registers[DSP_REG_B1];
8829: source[2] = dsp_core.registers[DSP_REG_B0];
8830:
1.1 root 8831: newsr |= dsp_sub56(source, dest);
8832:
1.1.1.6 root 8833: dsp_core.registers[DSP_REG_A2] = dest[0];
8834: dsp_core.registers[DSP_REG_A1] = dest[1];
8835: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8836:
1.1.1.6 root 8837: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8838:
1.1.1.6 root 8839: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8840: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8841: }
8842:
1.1.1.6 root 8843: static void dsp_subr_b(void)
1.1 root 8844: {
1.1.1.6 root 8845: Uint32 source[3], dest[3];
8846: Uint16 newsr;
1.1 root 8847:
1.1.1.6 root 8848: dest[0] = dsp_core.registers[DSP_REG_B2];
8849: dest[1] = dsp_core.registers[DSP_REG_B1];
8850: dest[2] = dsp_core.registers[DSP_REG_B0];
8851:
8852: newsr = dsp_asr56(dest);
1.1 root 8853:
1.1.1.6 root 8854: source[0] = dsp_core.registers[DSP_REG_A2];
8855: source[1] = dsp_core.registers[DSP_REG_A1];
8856: source[2] = dsp_core.registers[DSP_REG_A0];
8857:
8858: newsr |= dsp_sub56(source, dest);
1.1 root 8859:
1.1.1.6 root 8860: dsp_core.registers[DSP_REG_B2] = dest[0];
8861: dsp_core.registers[DSP_REG_B1] = dest[1];
8862: dsp_core.registers[DSP_REG_B0] = dest[2];
8863:
8864: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8865:
8866: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8867: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8868: }
8869:
1.1.1.6 root 8870: static void dsp_tfr_b_a(void)
1.1 root 8871: {
1.1.1.6 root 8872: dsp_core.registers[DSP_REG_A0] = dsp_core.registers[DSP_REG_B0];
8873: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_B1];
8874: dsp_core.registers[DSP_REG_A2] = dsp_core.registers[DSP_REG_B2];
8875: }
1.1 root 8876:
1.1.1.6 root 8877: static void dsp_tfr_a_b(void)
8878: {
8879: dsp_core.registers[DSP_REG_B0] = dsp_core.registers[DSP_REG_A0];
8880: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_A1];
8881: dsp_core.registers[DSP_REG_B2] = dsp_core.registers[DSP_REG_A2];
8882: }
8883:
8884: static void dsp_tfr_x0_a(void)
8885: {
8886: dsp_core.registers[DSP_REG_A0] = 0;
8887: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_X0];
8888: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
8889: dsp_core.registers[DSP_REG_A2] = 0xff;
8890: else
8891: dsp_core.registers[DSP_REG_A2] = 0x0;
8892: }
8893:
8894: static void dsp_tfr_x0_b(void)
8895: {
8896: dsp_core.registers[DSP_REG_B0] = 0;
8897: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_X0];
8898: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
8899: dsp_core.registers[DSP_REG_B2] = 0xff;
8900: else
8901: dsp_core.registers[DSP_REG_B2] = 0x0;
8902: }
8903:
8904: static void dsp_tfr_y0_a(void)
8905: {
8906: dsp_core.registers[DSP_REG_A0] = 0;
8907: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_Y0];
8908: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
8909: dsp_core.registers[DSP_REG_A2] = 0xff;
8910: else
8911: dsp_core.registers[DSP_REG_A2] = 0x0;
8912: }
8913:
8914: static void dsp_tfr_y0_b(void)
8915: {
8916: dsp_core.registers[DSP_REG_B0] = 0;
8917: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_Y0];
8918: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
8919: dsp_core.registers[DSP_REG_B2] = 0xff;
8920: else
8921: dsp_core.registers[DSP_REG_B2] = 0x0;
8922: }
8923:
8924: static void dsp_tfr_x1_a(void)
8925: {
8926: dsp_core.registers[DSP_REG_A0] = 0;
8927: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_X1];
8928: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
8929: dsp_core.registers[DSP_REG_A2] = 0xff;
8930: else
8931: dsp_core.registers[DSP_REG_A2] = 0x0;
8932: }
8933:
8934: static void dsp_tfr_x1_b(void)
8935: {
8936: dsp_core.registers[DSP_REG_B0] = 0;
8937: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_X1];
8938: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
8939: dsp_core.registers[DSP_REG_B2] = 0xff;
8940: else
8941: dsp_core.registers[DSP_REG_B2] = 0x0;
8942: }
8943:
8944: static void dsp_tfr_y1_a(void)
8945: {
8946: dsp_core.registers[DSP_REG_A0] = 0;
8947: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_Y1];
8948: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
8949: dsp_core.registers[DSP_REG_A2] = 0xff;
8950: else
8951: dsp_core.registers[DSP_REG_A2] = 0x0;
8952: }
8953:
8954: static void dsp_tfr_y1_b(void)
8955: {
8956: dsp_core.registers[DSP_REG_B0] = 0;
8957: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_Y1];
8958: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
8959: dsp_core.registers[DSP_REG_B2] = 0xff;
8960: else
8961: dsp_core.registers[DSP_REG_B2] = 0x0;
8962: }
8963:
8964: static void dsp_tst_a(void)
8965: {
8966: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_A2],
1.1.1.7 root 8967: dsp_core.registers[DSP_REG_A1],
8968: dsp_core.registers[DSP_REG_A0]);
1.1.1.6 root 8969:
8970: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8971: }
8972:
8973: static void dsp_tst_b(void)
8974: {
8975: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_B2],
1.1.1.7 root 8976: dsp_core.registers[DSP_REG_B1],
8977: dsp_core.registers[DSP_REG_B0]);
1.1 root 8978:
1.1.1.6 root 8979: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
1.1 root 8980: }
8981:
1.1.1.2 root 8982: /*
8983: vim:ts=4:sw=4:
8984: */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.