![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to dsp_cpu.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [HATARI the Atari ST Emulator] / hatari / src / falcon|
Return to dsp_cpu.c CVS log | Up to [HATARI the Atari ST Emulator] / hatari / src / falcon |
1.1 root 1: /*
1.1.1.2 root 2: DSP M56001 emulation
1.1.1.4 root 3: Instructions interpreter
1.1.1.2 root 4:
5: (C) 2003-2008 ARAnyM developer team
6:
7: This program is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2 of the License, or
10: (at your option) any later version.
11:
12: This program is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
18: along with this program; if not, write to the Free Software
19: Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20: */
21:
1.1.1.7 root 22: /*
23: DSP memory mapping
24: ------------------
1.1.1.11! root 25:
1.1.1.7 root 26: The memory map is configured as follows :
27: Program space P is one contiguous block of 32K dsp Words
1.1.1.11! root 28: X and Y data space are each separate 16K dsp Word blocks.
1.1.1.7 root 29: Both X and Y can be accessed as blocks starting at 0 or 16K.
30: Program space physically overlaps both X and Y data spaces.
31: Y: memory is mapped at address $0 in P memory
1.1.1.11! root 32: X: memory is mapped at address $4000 in P memory
1.1.1.7 root 33:
34: The DSP external RAM is zero waitstate, but there is a penalty for
1.1.1.11! root 35: accessing it twice or more in a single instruction, because there is only
1.1.1.9 root 36: one external data bus. The extra access costs 2 cycles penalty.
37:
1.1.1.7 root 38: The internal buses are all separate (0 waitstate)
39:
40:
41: X: Y: P:
42: $ffff |--------------+--------------+--------------|
43: | Int. I/O | Ext. I/O | |
44: $ffc0 |--------------+--------------+ |
45: | | | |
46: | Reserved | Reserved | Reserved |
47: | | | |
48: | | | |
49: | | | |
50: $8000 |--------------+--------------+--------------|
51: | | | |
52: | 16k Shadow | 16k Shadow | |
53: | | | 32K |
54: $4000 |--------------+--------------| Program |
55: | 16K | 16K | RAM |
56: | External | External | |
57: | RAM | RAM | |
58: $0200 |--------------+--------------+--------------|
59: | Log table or | Sin table or | |
60: | external mem | external mem | Internal |
61: $0100 |--------------+--------------+ program |
62: | Internal X | Internal Y | memory |
63: | memory | memory | |
64: $0000 |--------------+--------------+--------------|
65:
66:
67: Special Note : As the Falcon DSP is a 0 waitstate access memory, I've simplified a little the cycle counting.
68: If this DSP emulator code is used in another project, one should take into account the bus control register (BCR) waitstates.
69: */
70:
1.1.1.2 root 71: #ifdef HAVE_CONFIG_H
72: #include "config.h"
73: #endif
74:
1.1.1.6 root 75: #include <stdbool.h>
76:
1.1.1.10 root 77: #include "main.h"
1.1.1.2 root 78: #include "dsp_core.h"
1.1 root 79: #include "dsp_cpu.h"
80: #include "dsp_disasm.h"
1.1.1.6 root 81: #include "log.h"
1.1.1.9 root 82: #include "debugui.h"
1.1 root 83:
1.1.1.2 root 84: #define DSP_COUNT_IPS 0 /* Count instruction per seconds */
85:
1.1 root 86:
87: /**********************************
88: * Defines
89: **********************************/
90:
1.1.1.6 root 91: #define SIGN_PLUS 0
92: #define SIGN_MINUS 1
1.1.1.4 root 93:
1.1.1.9 root 94: /* Defines some bits values for access to external memory (X, Y, P) */
95: /* These values will set/unset the corresponding bits in the variable access_to_ext_memory */
96: /* to detect how many access to the external memory were done for a single instruction */
97: #define EXT_X_MEMORY 0
98: #define EXT_Y_MEMORY 1
99: #define EXT_P_MEMORY 2
100:
101:
1.1 root 102: /**********************************
103: * Variables
104: **********************************/
105:
1.1.1.4 root 106: /* Instructions per second */
107: static Uint32 start_time;
108: static Uint32 num_inst;
109:
1.1 root 110: /* Length of current instruction */
1.1.1.2 root 111: static Uint32 cur_inst_len; /* =0:jump, >0:increment */
1.1 root 112:
113: /* Current instruction */
1.1.1.4 root 114: static Uint32 cur_inst;
1.1 root 115:
1.1.1.7 root 116: /* Counts the number of access to the external memory for one instruction */
1.1.1.9 root 117: static Uint16 access_to_ext_memory;
1.1.1.7 root 118:
1.1.1.6 root 119: /* DSP is in disasm mode ? */
120: /* If yes, stack overflow, underflow and illegal instructions messages are not displayed */
121: static bool isDsp_in_disasm_mode;
1.1 root 122:
1.1.1.7 root 123: static char str_disasm_memory[2][50]; /* Buffer for memory change text in disasm mode */
1.1.1.5 root 124: static Uint16 disasm_memory_ptr; /* Pointer for memory change in disasm mode */
1.1 root 125:
126: /**********************************
127: * Functions
128: **********************************/
129:
130: typedef void (*dsp_emul_t)(void);
131:
132: static void dsp_postexecute_update_pc(void);
133: static void dsp_postexecute_interrupts(void);
134:
1.1.1.5 root 135: static void dsp_setInterruptIPL(Uint32 value);
136:
1.1.1.6 root 137: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2);
1.1.1.2 root 138:
139: static Uint32 read_memory(int space, Uint16 address);
1.1.1.6 root 140: static inline Uint32 read_memory_p(Uint16 address);
1.1.1.2 root 141: static Uint32 read_memory_disasm(int space, Uint16 address);
1.1.1.6 root 142:
143: static inline void write_memory(int space, Uint16 address, Uint32 value);
144: static void write_memory_raw(int space, Uint16 address, Uint32 value);
1.1.1.4 root 145: static void write_memory_disasm(int space, Uint16 address, Uint32 value);
1.1.1.6 root 146:
1.1.1.11! root 147: static void dsp_write_reg(Uint32 numreg, Uint32 value);
1.1 root 148:
1.1.1.4 root 149: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly);
1.1.1.2 root 150: static void dsp_stack_pop(Uint32 *curpc, Uint32 *cursr);
1.1.1.4 root 151: static void dsp_compute_ssh_ssl(void);
1.1 root 152:
153: static void opcode8h_0(void);
154:
1.1.1.2 root 155: static void dsp_update_rn(Uint32 numreg, Sint16 modifier);
156: static void dsp_update_rn_bitreverse(Uint32 numreg);
157: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier);
158: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr);
159: static int dsp_calc_cc(Uint32 cc_code);
1.1 root 160:
161: static void dsp_undefined(void);
162:
163: /* Instructions without parallel moves */
164: static void dsp_andi(void);
1.1.1.4 root 165: static void dsp_bchg_aa(void);
166: static void dsp_bchg_ea(void);
167: static void dsp_bchg_pp(void);
168: static void dsp_bchg_reg(void);
169: static void dsp_bclr_aa(void);
170: static void dsp_bclr_ea(void);
171: static void dsp_bclr_pp(void);
172: static void dsp_bclr_reg(void);
173: static void dsp_bset_aa(void);
174: static void dsp_bset_ea(void);
175: static void dsp_bset_pp(void);
176: static void dsp_bset_reg(void);
177: static void dsp_btst_aa(void);
178: static void dsp_btst_ea(void);
179: static void dsp_btst_pp(void);
180: static void dsp_btst_reg(void);
1.1 root 181: static void dsp_div(void);
182: static void dsp_enddo(void);
183: static void dsp_illegal(void);
1.1.1.4 root 184: static void dsp_jcc_imm(void);
185: static void dsp_jcc_ea(void);
186: static void dsp_jclr_aa(void);
187: static void dsp_jclr_ea(void);
188: static void dsp_jclr_pp(void);
189: static void dsp_jclr_reg(void);
190: static void dsp_jmp_ea(void);
191: static void dsp_jmp_imm(void);
192: static void dsp_jscc_ea(void);
193: static void dsp_jscc_imm(void);
194: static void dsp_jsclr_aa(void);
195: static void dsp_jsclr_ea(void);
196: static void dsp_jsclr_pp(void);
197: static void dsp_jsclr_reg(void);
198: static void dsp_jset_aa(void);
199: static void dsp_jset_ea(void);
200: static void dsp_jset_pp(void);
201: static void dsp_jset_reg(void);
202: static void dsp_jsr_ea(void);
203: static void dsp_jsr_imm(void);
204: static void dsp_jsset_aa(void);
205: static void dsp_jsset_ea(void);
206: static void dsp_jsset_pp(void);
207: static void dsp_jsset_reg(void);
1.1 root 208: static void dsp_lua(void);
1.1.1.4 root 209: static void dsp_movem_ea(void);
210: static void dsp_movem_aa(void);
1.1 root 211: static void dsp_nop(void);
212: static void dsp_norm(void);
213: static void dsp_ori(void);
214: static void dsp_reset(void);
215: static void dsp_rti(void);
216: static void dsp_rts(void);
217: static void dsp_stop(void);
218: static void dsp_swi(void);
219: static void dsp_tcc(void);
220: static void dsp_wait(void);
221:
1.1.1.3 root 222: static void dsp_do_ea(void);
223: static void dsp_do_aa(void);
224: static void dsp_do_imm(void);
225: static void dsp_do_reg(void);
226: static void dsp_rep_aa(void);
227: static void dsp_rep_ea(void);
228: static void dsp_rep_imm(void);
229: static void dsp_rep_reg(void);
230: static void dsp_movec_aa(void);
231: static void dsp_movec_ea(void);
232: static void dsp_movec_imm(void);
233: static void dsp_movec_reg(void);
1.1 root 234: static void dsp_movep_0(void);
235: static void dsp_movep_1(void);
1.1.1.4 root 236: static void dsp_movep_23(void);
1.1 root 237:
238: /* Parallel move analyzer */
1.1.1.2 root 239: static int dsp_pm_read_accu24(int numreg, Uint32 *dest);
1.1 root 240: static void dsp_pm_0(void);
241: static void dsp_pm_1(void);
242: static void dsp_pm_2(void);
243: static void dsp_pm_2_2(void);
244: static void dsp_pm_3(void);
245: static void dsp_pm_4(void);
1.1.1.4 root 246: static void dsp_pm_4x(void);
1.1 root 247: static void dsp_pm_5(void);
248: static void dsp_pm_8(void);
249:
250: /* 56bits arithmetic */
1.1.1.2 root 251: static Uint16 dsp_abs56(Uint32 *dest);
252: static Uint16 dsp_asl56(Uint32 *dest);
253: static Uint16 dsp_asr56(Uint32 *dest);
254: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest);
255: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest);
1.1.1.5 root 256: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe);
1.1.1.2 root 257: static void dsp_rnd56(Uint32 *dest);
1.1 root 258:
259: /* Instructions with parallel moves */
1.1.1.6 root 260: static void dsp_abs_a(void);
261: static void dsp_abs_b(void);
262: static void dsp_adc_x_a(void);
263: static void dsp_adc_x_b(void);
264: static void dsp_adc_y_a(void);
265: static void dsp_adc_y_b(void);
266: static void dsp_add_b_a(void);
267: static void dsp_add_a_b(void);
268: static void dsp_add_x_a(void);
269: static void dsp_add_x_b(void);
270: static void dsp_add_y_a(void);
271: static void dsp_add_y_b(void);
272: static void dsp_add_x0_a(void);
273: static void dsp_add_x0_b(void);
274: static void dsp_add_y0_a(void);
275: static void dsp_add_y0_b(void);
276: static void dsp_add_x1_a(void);
277: static void dsp_add_x1_b(void);
278: static void dsp_add_y1_a(void);
279: static void dsp_add_y1_b(void);
280: static void dsp_addl_b_a(void);
281: static void dsp_addl_b_a(void);
282: static void dsp_addl_a_b(void);
283: static void dsp_addr_b_a(void);
284: static void dsp_addr_a_b(void);
285: static void dsp_and_x0_a(void);
286: static void dsp_and_x0_b(void);
287: static void dsp_and_y0_a(void);
288: static void dsp_and_y0_b(void);
289: static void dsp_and_x1_a(void);
290: static void dsp_and_x1_b(void);
291: static void dsp_and_y1_a(void);
292: static void dsp_and_y1_b(void);
1.1.1.7 root 293: static void dsp_asl_a(void);
294: static void dsp_asl_b(void);
295: static void dsp_asr_a(void);
296: static void dsp_asr_b(void);
1.1.1.6 root 297: static void dsp_clr_a(void);
298: static void dsp_clr_b(void);
299: static void dsp_cmp_b_a(void);
300: static void dsp_cmp_a_b(void);
301: static void dsp_cmp_x0_a(void);
302: static void dsp_cmp_x0_b(void);
303: static void dsp_cmp_y0_a(void);
304: static void dsp_cmp_y0_b(void);
305: static void dsp_cmp_x1_a(void);
306: static void dsp_cmp_x1_b(void);
307: static void dsp_cmp_y1_a(void);
308: static void dsp_cmp_y1_b(void);
309: static void dsp_cmpm_b_a(void);
310: static void dsp_cmpm_a_b(void);
311: static void dsp_cmpm_x0_a(void);
312: static void dsp_cmpm_x0_b(void);
313: static void dsp_cmpm_y0_a(void);
314: static void dsp_cmpm_y0_b(void);
315: static void dsp_cmpm_x1_a(void);
316: static void dsp_cmpm_x1_b(void);
317: static void dsp_cmpm_y1_a(void);
318: static void dsp_cmpm_y1_b(void);
319: static void dsp_eor_x0_a(void);
320: static void dsp_eor_x0_b(void);
321: static void dsp_eor_y0_a(void);
322: static void dsp_eor_y0_b(void);
323: static void dsp_eor_x1_a(void);
324: static void dsp_eor_x1_b(void);
325: static void dsp_eor_y1_a(void);
326: static void dsp_eor_y1_b(void);
327: static void dsp_lsl_a(void);
328: static void dsp_lsl_b(void);
329: static void dsp_lsr_a(void);
330: static void dsp_lsr_b(void);
331: static void dsp_mac_p_x0_x0_a(void);
332: static void dsp_mac_m_x0_x0_a(void);
333: static void dsp_mac_p_x0_x0_b(void);
334: static void dsp_mac_m_x0_x0_b(void);
335: static void dsp_mac_p_y0_y0_a(void);
336: static void dsp_mac_m_y0_y0_a(void);
337: static void dsp_mac_p_y0_y0_b(void);
338: static void dsp_mac_m_y0_y0_b(void);
339: static void dsp_mac_p_x1_x0_a(void);
340: static void dsp_mac_m_x1_x0_a(void);
341: static void dsp_mac_p_x1_x0_b(void);
342: static void dsp_mac_m_x1_x0_b(void);
343: static void dsp_mac_p_y1_y0_a(void);
344: static void dsp_mac_m_y1_y0_a(void);
345: static void dsp_mac_p_y1_y0_b(void);
346: static void dsp_mac_m_y1_y0_b(void);
347: static void dsp_mac_p_x0_y1_a(void);
348: static void dsp_mac_m_x0_y1_a(void);
349: static void dsp_mac_p_x0_y1_b(void);
350: static void dsp_mac_m_x0_y1_b(void);
351: static void dsp_mac_p_y0_x0_a(void);
352: static void dsp_mac_m_y0_x0_a(void);
353: static void dsp_mac_p_y0_x0_b(void);
354: static void dsp_mac_m_y0_x0_b(void);
355: static void dsp_mac_p_x1_y0_a(void);
356: static void dsp_mac_m_x1_y0_a(void);
357: static void dsp_mac_p_x1_y0_b(void);
358: static void dsp_mac_m_x1_y0_b(void);
359: static void dsp_mac_p_y1_x1_a(void);
360: static void dsp_mac_m_y1_x1_a(void);
361: static void dsp_mac_p_y1_x1_b(void);
362: static void dsp_mac_m_y1_x1_b(void);
363: static void dsp_macr_p_x0_x0_a(void);
364: static void dsp_macr_m_x0_x0_a(void);
365: static void dsp_macr_p_x0_x0_b(void);
366: static void dsp_macr_m_x0_x0_b(void);
367: static void dsp_macr_p_y0_y0_a(void);
368: static void dsp_macr_m_y0_y0_a(void);
369: static void dsp_macr_p_y0_y0_b(void);
370: static void dsp_macr_m_y0_y0_b(void);
371: static void dsp_macr_p_x1_x0_a(void);
372: static void dsp_macr_m_x1_x0_a(void);
373: static void dsp_macr_p_x1_x0_b(void);
374: static void dsp_macr_m_x1_x0_b(void);
375: static void dsp_macr_p_y1_y0_a(void);
376: static void dsp_macr_m_y1_y0_a(void);
377: static void dsp_macr_p_y1_y0_b(void);
378: static void dsp_macr_m_y1_y0_b(void);
379: static void dsp_macr_p_x0_y1_a(void);
380: static void dsp_macr_m_x0_y1_a(void);
381: static void dsp_macr_p_x0_y1_b(void);
382: static void dsp_macr_m_x0_y1_b(void);
383: static void dsp_macr_p_y0_x0_a(void);
384: static void dsp_macr_m_y0_x0_a(void);
385: static void dsp_macr_p_y0_x0_b(void);
386: static void dsp_macr_m_y0_x0_b(void);
387: static void dsp_macr_p_x1_y0_a(void);
388: static void dsp_macr_m_x1_y0_a(void);
389: static void dsp_macr_p_x1_y0_b(void);
390: static void dsp_macr_m_x1_y0_b(void);
391: static void dsp_macr_p_y1_x1_a(void);
392: static void dsp_macr_m_y1_x1_a(void);
393: static void dsp_macr_p_y1_x1_b(void);
394: static void dsp_macr_m_y1_x1_b(void);
1.1 root 395: static void dsp_move(void);
1.1.1.6 root 396: static void dsp_mpy_p_x0_x0_a(void);
397: static void dsp_mpy_m_x0_x0_a(void);
398: static void dsp_mpy_p_x0_x0_b(void);
399: static void dsp_mpy_m_x0_x0_b(void);
400: static void dsp_mpy_p_y0_y0_a(void);
401: static void dsp_mpy_m_y0_y0_a(void);
402: static void dsp_mpy_p_y0_y0_b(void);
403: static void dsp_mpy_m_y0_y0_b(void);
404: static void dsp_mpy_p_x1_x0_a(void);
405: static void dsp_mpy_m_x1_x0_a(void);
406: static void dsp_mpy_p_x1_x0_b(void);
407: static void dsp_mpy_m_x1_x0_b(void);
408: static void dsp_mpy_p_y1_y0_a(void);
409: static void dsp_mpy_m_y1_y0_a(void);
410: static void dsp_mpy_p_y1_y0_b(void);
411: static void dsp_mpy_m_y1_y0_b(void);
412: static void dsp_mpy_p_x0_y1_a(void);
413: static void dsp_mpy_m_x0_y1_a(void);
414: static void dsp_mpy_p_x0_y1_b(void);
415: static void dsp_mpy_m_x0_y1_b(void);
416: static void dsp_mpy_p_y0_x0_a(void);
417: static void dsp_mpy_m_y0_x0_a(void);
418: static void dsp_mpy_p_y0_x0_b(void);
419: static void dsp_mpy_m_y0_x0_b(void);
420: static void dsp_mpy_p_x1_y0_a(void);
421: static void dsp_mpy_m_x1_y0_a(void);
422: static void dsp_mpy_p_x1_y0_b(void);
423: static void dsp_mpy_m_x1_y0_b(void);
424: static void dsp_mpy_p_y1_x1_a(void);
425: static void dsp_mpy_m_y1_x1_a(void);
426: static void dsp_mpy_p_y1_x1_b(void);
427: static void dsp_mpy_m_y1_x1_b(void);
428: static void dsp_mpyr_p_x0_x0_a(void);
429: static void dsp_mpyr_m_x0_x0_a(void);
430: static void dsp_mpyr_p_x0_x0_b(void);
431: static void dsp_mpyr_m_x0_x0_b(void);
432: static void dsp_mpyr_p_y0_y0_a(void);
433: static void dsp_mpyr_m_y0_y0_a(void);
434: static void dsp_mpyr_p_y0_y0_b(void);
435: static void dsp_mpyr_m_y0_y0_b(void);
436: static void dsp_mpyr_p_x1_x0_a(void);
437: static void dsp_mpyr_m_x1_x0_a(void);
438: static void dsp_mpyr_p_x1_x0_b(void);
439: static void dsp_mpyr_m_x1_x0_b(void);
440: static void dsp_mpyr_p_y1_y0_a(void);
441: static void dsp_mpyr_m_y1_y0_a(void);
442: static void dsp_mpyr_p_y1_y0_b(void);
443: static void dsp_mpyr_m_y1_y0_b(void);
444: static void dsp_mpyr_p_x0_y1_a(void);
445: static void dsp_mpyr_m_x0_y1_a(void);
446: static void dsp_mpyr_p_x0_y1_b(void);
447: static void dsp_mpyr_m_x0_y1_b(void);
448: static void dsp_mpyr_p_y0_x0_a(void);
449: static void dsp_mpyr_m_y0_x0_a(void);
450: static void dsp_mpyr_p_y0_x0_b(void);
451: static void dsp_mpyr_m_y0_x0_b(void);
452: static void dsp_mpyr_p_x1_y0_a(void);
453: static void dsp_mpyr_m_x1_y0_a(void);
454: static void dsp_mpyr_p_x1_y0_b(void);
455: static void dsp_mpyr_m_x1_y0_b(void);
456: static void dsp_mpyr_p_y1_x1_a(void);
457: static void dsp_mpyr_m_y1_x1_a(void);
458: static void dsp_mpyr_p_y1_x1_b(void);
459: static void dsp_mpyr_m_y1_x1_b(void);
460: static void dsp_neg_a(void);
461: static void dsp_neg_b(void);
462: static void dsp_not_a(void);
463: static void dsp_not_b(void);
464: static void dsp_or_x0_a(void);
465: static void dsp_or_x0_b(void);
466: static void dsp_or_y0_a(void);
467: static void dsp_or_y0_b(void);
468: static void dsp_or_x1_a(void);
469: static void dsp_or_x1_b(void);
470: static void dsp_or_y1_a(void);
471: static void dsp_or_y1_b(void);
472: static void dsp_rnd_a(void);
473: static void dsp_rnd_b(void);
474: static void dsp_rol_a(void);
475: static void dsp_rol_b(void);
476: static void dsp_ror_a(void);
477: static void dsp_ror_b(void);
478: static void dsp_sbc_x_a(void);
479: static void dsp_sbc_x_b(void);
480: static void dsp_sbc_y_a(void);
481: static void dsp_sbc_y_b(void);
482: static void dsp_sub_b_a(void);
483: static void dsp_sub_a_b(void);
484: static void dsp_sub_x_a(void);
485: static void dsp_sub_x_b(void);
486: static void dsp_sub_y_a(void);
487: static void dsp_sub_y_b(void);
488: static void dsp_sub_x0_a(void);
489: static void dsp_sub_x0_b(void);
490: static void dsp_sub_y0_a(void);
491: static void dsp_sub_y0_b(void);
492: static void dsp_sub_x1_a(void);
493: static void dsp_sub_x1_b(void);
494: static void dsp_sub_y1_a(void);
495: static void dsp_sub_y1_b(void);
496: static void dsp_subl_a(void);
497: static void dsp_subl_b(void);
498: static void dsp_subr_a(void);
499: static void dsp_subr_b(void);
500: static void dsp_tfr_b_a(void);
501: static void dsp_tfr_a_b(void);
502: static void dsp_tfr_x0_a(void);
503: static void dsp_tfr_x0_b(void);
504: static void dsp_tfr_y0_a(void);
505: static void dsp_tfr_y0_b(void);
506: static void dsp_tfr_x1_a(void);
507: static void dsp_tfr_x1_b(void);
508: static void dsp_tfr_y1_a(void);
509: static void dsp_tfr_y1_b(void);
510: static void dsp_tst_a(void);
511: static void dsp_tst_b(void);
1.1 root 512:
1.1.1.6 root 513: static const dsp_emul_t opcodes8h[512] = {
1.1.1.4 root 514: /* 0x00 - 0x3f */
515: opcode8h_0, dsp_undefined, dsp_undefined, dsp_undefined, opcode8h_0, dsp_andi, dsp_undefined, dsp_ori,
516: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
517: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
518: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
519: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
520: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
521: dsp_undefined, dsp_undefined, dsp_div, dsp_div, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
522: dsp_norm, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
1.1.1.11! root 523:
1.1.1.4 root 524: /* 0x40 - 0x7f */
525: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
526: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
527: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
528: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
529: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
530: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
531: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
532: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
533:
534: /* 0x80 - 0xbf */
535: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
1.1.1.11! root 536: dsp_lua, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
1.1.1.4 root 537: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
1.1.1.11! root 538: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
1.1.1.4 root 539: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
540: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
541: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
542: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
1.1.1.11! root 543:
1.1.1.4 root 544: /* 0xc0 - 0xff */
1.1.1.11! root 545: dsp_do_aa, dsp_rep_aa, dsp_do_aa, dsp_rep_aa, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
! 546: dsp_do_ea, dsp_rep_ea, dsp_do_ea, dsp_rep_ea, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
! 547: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
! 548: dsp_do_reg, dsp_rep_reg, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
! 549: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
! 550: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
! 551: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
! 552: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
1.1.1.4 root 553:
554: /* 0x100 - 0x13f */
1.1.1.6 root 555: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 556: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 557: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 558: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 559: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 560: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 561: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 562: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
563:
564: /* 0x140 - 0x17f */
565: dsp_bclr_aa, dsp_bset_aa, dsp_bclr_aa, dsp_bset_aa, dsp_jclr_aa, dsp_jset_aa, dsp_jclr_aa, dsp_jset_aa,
566: dsp_bclr_ea, dsp_bset_ea, dsp_bclr_ea, dsp_bset_ea, dsp_jclr_ea, dsp_jset_ea, dsp_jclr_ea, dsp_jset_ea,
567: dsp_bclr_pp, dsp_bset_pp, dsp_bclr_pp, dsp_bset_pp, dsp_jclr_pp, dsp_jset_pp, dsp_jclr_pp, dsp_jset_pp,
568: dsp_jclr_reg, dsp_jset_reg, dsp_bclr_reg, dsp_bset_reg, dsp_jmp_ea, dsp_jcc_ea, dsp_undefined, dsp_undefined,
569: dsp_bchg_aa, dsp_btst_aa, dsp_bchg_aa, dsp_btst_aa, dsp_jsclr_aa, dsp_jsset_aa, dsp_jsclr_aa, dsp_jsset_aa,
570: dsp_bchg_ea, dsp_btst_ea, dsp_bchg_ea, dsp_btst_ea, dsp_jsclr_ea, dsp_jsset_ea, dsp_jsclr_ea, dsp_jsset_ea,
571: dsp_bchg_pp, dsp_btst_pp, dsp_bchg_pp, dsp_btst_pp, dsp_jsclr_pp, dsp_jsset_pp, dsp_jsclr_pp, dsp_jsset_pp,
572: dsp_jsclr_reg, dsp_jsset_reg, dsp_bchg_reg, dsp_btst_reg, dsp_jsr_ea, dsp_jscc_ea, dsp_undefined, dsp_undefined,
573:
574: /* 0x180 - 0x1bf */
575: dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm,
1.1.1.11! root 576: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
! 577: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
! 578: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
! 579: dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm,
! 580: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
! 581: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
! 582: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
1.1.1.4 root 583:
584: /* 0x1c0 - 0x1ff */
1.1.1.11! root 585: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
! 586: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
! 587: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
! 588: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
! 589: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
! 590: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
! 591: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
! 592: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
1.1 root 593: };
594:
1.1.1.6 root 595: static const dsp_emul_t opcodes_parmove[16] = {
596: dsp_pm_0, dsp_pm_1, dsp_pm_2, dsp_pm_3, dsp_pm_4, dsp_pm_5, dsp_pm_5, dsp_pm_5,
597: dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8
1.1 root 598: };
599:
1.1.1.6 root 600: static const dsp_emul_t opcodes_alu[256] = {
1.1.1.4 root 601: /* 0x00 - 0x3f */
1.1.1.6 root 602: dsp_move , dsp_tfr_b_a, dsp_addr_b_a, dsp_tst_a, dsp_undefined, dsp_cmp_b_a, dsp_subr_a, dsp_cmpm_b_a,
603: dsp_undefined, dsp_tfr_a_b, dsp_addr_a_b, dsp_tst_b, dsp_undefined, dsp_cmp_a_b, dsp_subr_b, dsp_cmpm_a_b,
604: dsp_add_b_a, dsp_rnd_a, dsp_addl_b_a, dsp_clr_a, dsp_sub_b_a, dsp_undefined, dsp_subl_a, dsp_not_a,
605: dsp_add_a_b, dsp_rnd_b, dsp_addl_a_b, dsp_clr_b, dsp_sub_a_b, dsp_undefined, dsp_subl_b, dsp_not_b,
1.1.1.7 root 606: dsp_add_x_a, dsp_adc_x_a, dsp_asr_a, dsp_lsr_a, dsp_sub_x_a, dsp_sbc_x_a, dsp_abs_a, dsp_ror_a,
607: dsp_add_x_b, dsp_adc_x_b, dsp_asr_b, dsp_lsr_b, dsp_sub_x_b, dsp_sbc_x_b, dsp_abs_b, dsp_ror_b,
608: dsp_add_y_a, dsp_adc_y_a, dsp_asl_a, dsp_lsl_a, dsp_sub_y_a, dsp_sbc_y_a, dsp_neg_a, dsp_rol_a,
609: dsp_add_y_b, dsp_adc_y_b, dsp_asl_b, dsp_lsl_b, dsp_sub_y_b, dsp_sbc_y_b, dsp_neg_b, dsp_rol_b,
1.1.1.11! root 610:
1.1.1.4 root 611: /* 0x40 - 0x7f */
1.1.1.6 root 612: dsp_add_x0_a, dsp_tfr_x0_a, dsp_or_x0_a, dsp_eor_x0_a, dsp_sub_x0_a, dsp_cmp_x0_a, dsp_and_x0_a, dsp_cmpm_x0_a,
613: dsp_add_x0_b, dsp_tfr_x0_b, dsp_or_x0_b, dsp_eor_x0_b, dsp_sub_x0_b, dsp_cmp_x0_b, dsp_and_x0_b, dsp_cmpm_x0_b,
614: dsp_add_y0_a, dsp_tfr_y0_a, dsp_or_y0_a, dsp_eor_y0_a, dsp_sub_y0_a, dsp_cmp_y0_a, dsp_and_y0_a, dsp_cmpm_y0_a,
615: dsp_add_y0_b, dsp_tfr_y0_b, dsp_or_y0_b, dsp_eor_y0_b, dsp_sub_y0_b, dsp_cmp_y0_b, dsp_and_y0_b, dsp_cmpm_y0_b,
616: dsp_add_x1_a, dsp_tfr_x1_a, dsp_or_x1_a, dsp_eor_x1_a, dsp_sub_x1_a, dsp_cmp_x1_a, dsp_and_x1_a, dsp_cmpm_x1_a,
617: dsp_add_x1_b, dsp_tfr_x1_b, dsp_or_x1_b, dsp_eor_x1_b, dsp_sub_x1_b, dsp_cmp_x1_b, dsp_and_x1_b, dsp_cmpm_x1_b,
618: dsp_add_y1_a, dsp_tfr_y1_a, dsp_or_y1_a, dsp_eor_y1_a, dsp_sub_y1_a, dsp_cmp_y1_a, dsp_and_y1_a, dsp_cmpm_y1_a,
619: dsp_add_y1_b, dsp_tfr_y1_b, dsp_or_y1_b, dsp_eor_y1_b, dsp_sub_y1_b, dsp_cmp_y1_b, dsp_and_y1_b, dsp_cmpm_y1_b,
1.1.1.4 root 620:
621: /* 0x80 - 0xbf */
1.1.1.6 root 622: dsp_mpy_p_x0_x0_a, dsp_mpyr_p_x0_x0_a, dsp_mac_p_x0_x0_a, dsp_macr_p_x0_x0_a, dsp_mpy_m_x0_x0_a, dsp_mpyr_m_x0_x0_a, dsp_mac_m_x0_x0_a, dsp_macr_m_x0_x0_a,
623: dsp_mpy_p_x0_x0_b, dsp_mpyr_p_x0_x0_b, dsp_mac_p_x0_x0_b, dsp_macr_p_x0_x0_b, dsp_mpy_m_x0_x0_b, dsp_mpyr_m_x0_x0_b, dsp_mac_m_x0_x0_b, dsp_macr_m_x0_x0_b,
624: dsp_mpy_p_y0_y0_a, dsp_mpyr_p_y0_y0_a, dsp_mac_p_y0_y0_a, dsp_macr_p_y0_y0_a, dsp_mpy_m_y0_y0_a, dsp_mpyr_m_y0_y0_a, dsp_mac_m_y0_y0_a, dsp_macr_m_y0_y0_a,
625: dsp_mpy_p_y0_y0_b, dsp_mpyr_p_y0_y0_b, dsp_mac_p_y0_y0_b, dsp_macr_p_y0_y0_b, dsp_mpy_m_y0_y0_b, dsp_mpyr_m_y0_y0_b, dsp_mac_m_y0_y0_b, dsp_macr_m_y0_y0_b,
626: dsp_mpy_p_x1_x0_a, dsp_mpyr_p_x1_x0_a, dsp_mac_p_x1_x0_a, dsp_macr_p_x1_x0_a, dsp_mpy_m_x1_x0_a, dsp_mpyr_m_x1_x0_a, dsp_mac_m_x1_x0_a, dsp_macr_m_x1_x0_a,
627: dsp_mpy_p_x1_x0_b, dsp_mpyr_p_x1_x0_b, dsp_mac_p_x1_x0_b, dsp_macr_p_x1_x0_b, dsp_mpy_m_x1_x0_b, dsp_mpyr_m_x1_x0_b, dsp_mac_m_x1_x0_b, dsp_macr_m_x1_x0_b,
628: dsp_mpy_p_y1_y0_a, dsp_mpyr_p_y1_y0_a, dsp_mac_p_y1_y0_a, dsp_macr_p_y1_y0_a, dsp_mpy_m_y1_y0_a, dsp_mpyr_m_y1_y0_a, dsp_mac_m_y1_y0_a, dsp_macr_m_y1_y0_a,
629: dsp_mpy_p_y1_y0_b, dsp_mpyr_p_y1_y0_b, dsp_mac_p_y1_y0_b, dsp_macr_p_y1_y0_b, dsp_mpy_m_y1_y0_b, dsp_mpyr_m_y1_y0_b, dsp_mac_m_y1_y0_b, dsp_macr_m_y1_y0_b,
630:
631: /* 0xc0_m_ 0xff */
632: dsp_mpy_p_x0_y1_a, dsp_mpyr_p_x0_y1_a, dsp_mac_p_x0_y1_a, dsp_macr_p_x0_y1_a, dsp_mpy_m_x0_y1_a, dsp_mpyr_m_x0_y1_a, dsp_mac_m_x0_y1_a, dsp_macr_m_x0_y1_a,
633: dsp_mpy_p_x0_y1_b, dsp_mpyr_p_x0_y1_b, dsp_mac_p_x0_y1_b, dsp_macr_p_x0_y1_b, dsp_mpy_m_x0_y1_b, dsp_mpyr_m_x0_y1_b, dsp_mac_m_x0_y1_b, dsp_macr_m_x0_y1_b,
634: dsp_mpy_p_y0_x0_a, dsp_mpyr_p_y0_x0_a, dsp_mac_p_y0_x0_a, dsp_macr_p_y0_x0_a, dsp_mpy_m_y0_x0_a, dsp_mpyr_m_y0_x0_a, dsp_mac_m_y0_x0_a, dsp_macr_m_y0_x0_a,
635: dsp_mpy_p_y0_x0_b, dsp_mpyr_p_y0_x0_b, dsp_mac_p_y0_x0_b, dsp_macr_p_y0_x0_b, dsp_mpy_m_y0_x0_b, dsp_mpyr_m_y0_x0_b, dsp_mac_m_y0_x0_b, dsp_macr_m_y0_x0_b,
636: dsp_mpy_p_x1_y0_a, dsp_mpyr_p_x1_y0_a, dsp_mac_p_x1_y0_a, dsp_macr_p_x1_y0_a, dsp_mpy_m_x1_y0_a, dsp_mpyr_m_x1_y0_a, dsp_mac_m_x1_y0_a, dsp_macr_m_x1_y0_a,
637: dsp_mpy_p_x1_y0_b, dsp_mpyr_p_x1_y0_b, dsp_mac_p_x1_y0_b, dsp_macr_p_x1_y0_b, dsp_mpy_m_x1_y0_b, dsp_mpyr_m_x1_y0_b, dsp_mac_m_x1_y0_b, dsp_macr_m_x1_y0_b,
638: dsp_mpy_p_y1_x1_a, dsp_mpyr_p_y1_x1_a, dsp_mac_p_y1_x1_a, dsp_macr_p_y1_x1_a, dsp_mpy_m_y1_x1_a, dsp_mpyr_m_y1_x1_a, dsp_mac_m_y1_x1_a, dsp_macr_m_y1_x1_a,
639: dsp_mpy_p_y1_x1_b, dsp_mpyr_p_y1_x1_b, dsp_mac_p_y1_x1_b, dsp_macr_p_y1_x1_b, dsp_mpy_m_y1_x1_b, dsp_mpyr_m_y1_x1_b, dsp_mac_m_y1_x1_b, dsp_macr_m_y1_x1_b
1.1 root 640: };
641:
1.1.1.6 root 642: static const int registers_tcc[16][2] = {
1.1 root 643: {DSP_REG_B,DSP_REG_A},
644: {DSP_REG_A,DSP_REG_B},
645: {DSP_REG_NULL,DSP_REG_NULL},
646: {DSP_REG_NULL,DSP_REG_NULL},
647:
648: {DSP_REG_NULL,DSP_REG_NULL},
649: {DSP_REG_NULL,DSP_REG_NULL},
650: {DSP_REG_NULL,DSP_REG_NULL},
651: {DSP_REG_NULL,DSP_REG_NULL},
652:
653: {DSP_REG_X0,DSP_REG_A},
654: {DSP_REG_X0,DSP_REG_B},
655: {DSP_REG_Y0,DSP_REG_A},
656: {DSP_REG_Y0,DSP_REG_B},
1.1.1.2 root 657:
658: {DSP_REG_X1,DSP_REG_A},
659: {DSP_REG_X1,DSP_REG_B},
1.1 root 660: {DSP_REG_Y1,DSP_REG_A},
661: {DSP_REG_Y1,DSP_REG_B}
662: };
663:
1.1.1.6 root 664: static const int registers_mask[64] = {
1.1 root 665: 0, 0, 0, 0,
666: 24, 24, 24, 24,
667: 24, 24, 8, 8,
668: 24, 24, 24, 24,
1.1.1.11! root 669:
1.1 root 670: 16, 16, 16, 16,
671: 16, 16, 16, 16,
672: 16, 16, 16, 16,
673: 16, 16, 16, 16,
1.1.1.11! root 674:
1.1 root 675: 16, 16, 16, 16,
676: 16, 16, 16, 16,
677: 0, 0, 0, 0,
678: 0, 0, 0, 0,
679:
680: 0, 0, 0, 0,
681: 0, 0, 0, 0,
682: 0, 16, 8, 6,
1.1.1.4 root 683: 16, 16, 16, 16
684: };
685:
1.1.1.6 root 686: static const dsp_interrupt_t dsp_interrupt[12] = {
1.1.1.5 root 687: {DSP_INTER_RESET , 0x00, 0, "Reset"},
688: {DSP_INTER_ILLEGAL , 0x3e, 0, "Illegal"},
689: {DSP_INTER_STACK_ERROR , 0x02, 0, "Stack Error"},
690: {DSP_INTER_TRACE , 0x04, 0, "Trace"},
691: {DSP_INTER_SWI , 0x06, 0, "Swi"},
692: {DSP_INTER_HOST_COMMAND , 0xff, 1, "Host Command"},
693: {DSP_INTER_HOST_RCV_DATA, 0x20, 1, "Host receive"},
694: {DSP_INTER_HOST_TRX_DATA, 0x22, 1, "Host transmit"},
695: {DSP_INTER_SSI_RCV_DATA_E, 0x0e, 2, "SSI receive with exception"},
696: {DSP_INTER_SSI_RCV_DATA , 0x0c, 2, "SSI receive"},
697: {DSP_INTER_SSI_TRX_DATA_E, 0x12, 2, "SSI transmit with exception"},
698: {DSP_INTER_SSI_TRX_DATA , 0x10, 2, "SSI tramsmit"}
1.1.1.4 root 699: };
700:
1.1 root 701:
702: /**********************************
703: * Emulator kernel
704: **********************************/
705:
1.1.1.6 root 706: void dsp56k_init_cpu(void)
1.1 root 707: {
1.1.1.6 root 708: dsp56k_disasm_init();
709: isDsp_in_disasm_mode = false;
1.1.1.2 root 710: start_time = SDL_GetTicks();
711: num_inst = 0;
1.1 root 712: }
713:
1.1.1.6 root 714: /**
715: * Execute one instruction in trace mode at a given PC address.
716: * */
1.1.1.9 root 717: Uint16 dsp56k_execute_one_disasm_instruction(FILE *out, Uint16 pc)
1.1.1.6 root 718: {
719: dsp_core_t *ptr1, *ptr2;
720: static dsp_core_t dsp_core_save;
1.1.1.8 root 721: Uint16 instruction_length;
1.1.1.6 root 722:
723: ptr1 = &dsp_core;
724: ptr2 = &dsp_core_save;
725:
726: /* Set DSP in disasm mode */
727: isDsp_in_disasm_mode = true;
728:
729: /* Save DSP context before executing instruction */
730: memcpy(ptr2, ptr1, sizeof(dsp_core));
731:
732: /* execute and disasm instruction */
733: dsp_core.pc = pc;
734:
735: /* Disasm instruction */
736: instruction_length = dsp56k_disasm(DSP_DISASM_MODE) - 1;
737:
738: /* Execute instruction at address given in parameter to get the number of cycles it takes */
739: dsp56k_execute_instruction();
740:
1.1.1.9 root 741: fprintf(out, "%s", dsp56k_getInstructionText());
1.1.1.6 root 742:
743: /* Restore DSP context after executing instruction */
744: memcpy(ptr1, ptr2, sizeof(dsp_core));
1.1.1.11! root 745:
1.1.1.6 root 746: /* Unset DSP in disasm mode */
747: isDsp_in_disasm_mode = false;
748:
749: return instruction_length;
750: }
751:
1.1.1.4 root 752: void dsp56k_execute_instruction(void)
1.1 root 753: {
1.1.1.2 root 754: Uint32 value;
1.1.1.6 root 755: Uint32 disasm_return = 0;
1.1.1.5 root 756: disasm_memory_ptr = 0;
757:
1.1.1.7 root 758: /* Initialise the number of access to the external memory for this instruction */
1.1.1.9 root 759: access_to_ext_memory = 0;
1.1.1.11! root 760:
! 761: /* Init the indirect AGU move instruction flag */
! 762: dsp_core.agu_move_indirect_instr = 0;
! 763:
1.1 root 764: /* Decode and execute current instruction */
1.1.1.6 root 765: cur_inst = read_memory_p(dsp_core.pc);
1.1.1.11! root 766:
1.1.1.7 root 767: /* Initialize instruction size and cycle counter */
768: cur_inst_len = 1;
1.1.1.6 root 769: dsp_core.instr_cycle = 2;
1.1 root 770:
1.1.1.6 root 771: /* Disasm current instruction ? (trace mode only) */
1.1.1.11! root 772: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
1.1.1.6 root 773: /* Call dsp56k_disasm only when DSP is called in trace mode */
774: if (isDsp_in_disasm_mode == false) {
775: disasm_return = dsp56k_disasm(DSP_TRACE_MODE);
1.1.1.11! root 776:
1.1.1.6 root 777: if (disasm_return != 0 && LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG)) {
778: /* DSP regs trace enabled only if DSP DISASM is enabled */
779: dsp56k_disasm_reg_save();
780: }
781: }
782: }
1.1.1.11! root 783:
1.1.1.4 root 784: if (cur_inst < 0x100000) {
785: value = (cur_inst >> 11) & (BITMASK(6) << 3);
786: value += (cur_inst >> 5) & BITMASK(3);
1.1 root 787: opcodes8h[value]();
788: } else {
1.1.1.6 root 789: /* Do parallel move read */
790: opcodes_parmove[(cur_inst>>20) & BITMASK(4)]();
791: }
792:
1.1.1.7 root 793: /* Add the waitstate due to external memory access */
1.1.1.9 root 794: /* (2 extra cycles per extra access to the external memory after the first one */
795: if (access_to_ext_memory != 0) {
796: value = access_to_ext_memory & 1;
797: value += (access_to_ext_memory & 2) >> 1;
798: value += (access_to_ext_memory & 4) >> 2;
1.1.1.11! root 799:
1.1.1.9 root 800: if (value > 1)
801: dsp_core.instr_cycle += (value - 1) * 2;
802: }
803:
1.1.1.6 root 804: /* Disasm current instruction ? (trace mode only) */
805: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
806: /* Display only when DSP is called in trace mode */
807: if (isDsp_in_disasm_mode == false) {
808: if (disasm_return != 0) {
809: fprintf(stderr, "%s", dsp56k_getInstructionText());
1.1.1.11! root 810:
1.1.1.6 root 811: /* DSP regs trace enabled only if DSP DISASM is enabled */
812: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG))
813: dsp56k_disasm_reg_compare();
814:
815: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM)) {
816: /* 1 memory change to display ? */
817: if (disasm_memory_ptr == 1)
818: fprintf(stderr, "\t%s\n", str_disasm_memory[0]);
819: /* 2 memory changes to display ? */
820: else if (disasm_memory_ptr == 2) {
821: fprintf(stderr, "\t%s\n", str_disasm_memory[0]);
822: fprintf(stderr, "\t%s\n", str_disasm_memory[1]);
823: }
824: }
825: }
826: }
1.1 root 827: }
828:
1.1.1.4 root 829: /* Process the PC */
830: dsp_postexecute_update_pc();
1.1 root 831:
1.1.1.4 root 832: /* Process Interrupts */
1.1 root 833: dsp_postexecute_interrupts();
834:
1.1.1.4 root 835: #if DSP_COUNT_IPS
836: ++num_inst;
837: if ((num_inst & 63) == 0) {
838: /* Evaluate time after <N> instructions have been executed to avoid asking too frequently */
839: Uint32 cur_time = SDL_GetTicks();
840: if (cur_time-start_time>1000) {
841: fprintf(stderr, "Dsp: %d i/s\n", (num_inst*1000)/(cur_time-start_time));
842: start_time=cur_time;
843: num_inst=0;
844: }
845: }
846: #endif
1.1 root 847: }
848:
849: /**********************************
850: * Update the PC
851: **********************************/
852:
853: static void dsp_postexecute_update_pc(void)
854: {
855: /* When running a REP, PC must stay on the current instruction */
1.1.1.6 root 856: if (dsp_core.loop_rep) {
1.1.1.11! root 857: /* Is PC on the instruction to repeat ? */
1.1.1.6 root 858: if (dsp_core.pc_on_rep==0) {
859: --dsp_core.registers[DSP_REG_LC];
860: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1 root 861:
1.1.1.6 root 862: if (dsp_core.registers[DSP_REG_LC] > 0) {
1.1.1.7 root 863: cur_inst_len = 0; /* Stay on this instruction */
1.1 root 864: } else {
1.1.1.6 root 865: dsp_core.loop_rep = 0;
866: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[DSP_REG_LCSAVE];
1.1 root 867: }
868: } else {
869: /* Init LC at right value */
1.1.1.6 root 870: if (dsp_core.registers[DSP_REG_LC] == 0) {
871: dsp_core.registers[DSP_REG_LC] = 0x010000;
1.1 root 872: }
1.1.1.6 root 873: dsp_core.pc_on_rep = 0;
1.1 root 874: }
875: }
876:
877: /* Normal execution, go to next instruction */
1.1.1.6 root 878: dsp_core.pc += cur_inst_len;
1.1 root 879:
880: /* When running a DO loop, we test the end of loop with the */
881: /* updated PC, pointing to last instruction of the loop */
1.1.1.6 root 882: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_LF)) {
1.1 root 883:
884: /* Did we execute the last instruction in loop ? */
1.1.1.11! root 885: if (dsp_core.pc == dsp_core.registers[DSP_REG_LA] + 1) {
! 886: if (dsp_core.registers[DSP_REG_LC] == 1) {
! 887: /* end of the loop */
1.1.1.4 root 888: Uint32 saved_pc, saved_sr;
889:
890: dsp_stack_pop(&saved_pc, &saved_sr);
1.1.1.10 root 891: dsp_core.registers[DSP_REG_SR] &= 0x7fff;
1.1.1.6 root 892: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
893: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
1.1 root 894: } else {
895: /* Loop one more time */
1.1.1.11! root 896: --dsp_core.registers[DSP_REG_LC];
! 897: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.6 root 898: dsp_core.pc = dsp_core.registers[DSP_REG_SSH];
1.1 root 899: }
900: }
901: }
902: }
903:
904: /**********************************
905: * Interrupts
906: **********************************/
907:
1.1.1.5 root 908: /* Post a new interrupt to the interrupt table */
909: void dsp_add_interrupt(Uint16 inter)
910: {
911: /* detect if this interrupt is used or not */
1.1.1.6 root 912: if (dsp_core.interrupt_ipl[inter] == -1)
1.1.1.5 root 913: return;
914:
915: /* add this interrupt to the pending interrupts table */
1.1.1.11! root 916: if (dsp_core.interrupt_isPending[inter] == 0) {
1.1.1.6 root 917: dsp_core.interrupt_isPending[inter] = 1;
918: dsp_core.interrupt_counter ++;
1.1.1.5 root 919: }
920: }
921:
922: static void dsp_setInterruptIPL(Uint32 value)
923: {
924: Uint32 ipl_ssi, ipl_hi, i;
925:
926: ipl_ssi = ((value >> 12) & 3) - 1;
927: ipl_hi = ((value >> 10) & 3) - 1;
928:
929: /* set IPL_HI */
1.1.1.7 root 930: for (i=5; i<8; i++) {
1.1.1.6 root 931: dsp_core.interrupt_ipl[i] = ipl_hi;
1.1.1.5 root 932: }
933:
934: /* set IPL_SSI */
1.1.1.7 root 935: for (i=8; i<12; i++) {
1.1.1.6 root 936: dsp_core.interrupt_ipl[i] = ipl_ssi;
1.1.1.5 root 937: }
938: }
939:
1.1 root 940: static void dsp_postexecute_interrupts(void)
941: {
1.1.1.5 root 942: Uint32 index, instr, i;
943: Sint32 ipl_to_raise, ipl_sr;
1.1.1.4 root 944:
945: /* REP is not interruptible */
1.1.1.6 root 946: if (dsp_core.loop_rep) {
1.1.1.4 root 947: return;
948: }
949:
950: /* A fast interrupt can not be interrupted. */
1.1.1.6 root 951: if (dsp_core.interrupt_state == DSP_INTERRUPT_DISABLED) {
1.1.1.5 root 952:
1.1.1.6 root 953: switch (dsp_core.interrupt_pipeline_count) {
1.1.1.5 root 954: case 5:
1.1.1.6 root 955: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 956: return;
957: case 4:
958: /* Prefetch interrupt instruction 1 */
1.1.1.6 root 959: dsp_core.interrupt_save_pc = dsp_core.pc;
960: dsp_core.pc = dsp_core.interrupt_instr_fetch;
1.1.1.5 root 961:
962: /* is it a LONG interrupt ? */
1.1.1.6 root 963: instr = read_memory_p(dsp_core.interrupt_instr_fetch);
1.1.1.5 root 964: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1.1.1.6 root 965: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
1.1.1.11! root 966: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.6 root 967: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1.1.1.5 root 968: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
969: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1.1.1.6 root 970: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1.1.1.5 root 971: }
1.1.1.6 root 972: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 973: return;
974: case 3:
1.1.1.11! root 975: /* Prefetch interrupt instruction 2, if first one was single word */
1.1.1.6 root 976: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+1) {
977: instr = read_memory_p(dsp_core.pc);
1.1.1.5 root 978: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1.1.1.6 root 979: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
1.1.1.11! root 980: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.6 root 981: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1.1.1.5 root 982: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
983: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1.1.1.6 root 984: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1.1.1.5 root 985: }
1.1.1.11! root 986: dsp_core.interrupt_pipeline_count --;
! 987: return;
! 988: }
! 989: dsp_core.interrupt_pipeline_count --;
! 990: /* First instruction was 2 word. Fall through */
1.1.1.5 root 991: case 2:
992: /* 1 instruction executed after interrupt */
993: /* before re enable interrupts */
994: /* Was it a FAST interrupt ? */
1.1.1.6 root 995: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+2) {
996: dsp_core.pc = dsp_core.interrupt_save_pc;
1.1.1.5 root 997: }
1.1.1.6 root 998: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 999: return;
1000: case 1:
1001: /* Last instruction executed after interrupt */
1002: /* before re enable interrupts */
1.1.1.6 root 1003: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 1004: return;
1005: case 0:
1006: /* Re enable interrupts */
1.1.1.6 root 1007: /* All 6 instruction are done, Interrupts can be enabled again */
1008: dsp_core.interrupt_save_pc = -1;
1009: dsp_core.interrupt_instr_fetch = -1;
1010: dsp_core.interrupt_state = DSP_INTERRUPT_NONE;
1011: break;
1.1.1.4 root 1012: }
1013: }
1.1 root 1014:
1.1.1.4 root 1015: /* Trace Interrupt ? */
1.1.1.6 root 1016: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_T)) {
1.1.1.5 root 1017: dsp_add_interrupt(DSP_INTER_TRACE);
1.1.1.4 root 1018: }
1019:
1020: /* No interrupt to execute */
1.1.1.6 root 1021: if (dsp_core.interrupt_counter == 0) {
1.1.1.4 root 1022: return;
1.1 root 1023: }
1024:
1.1.1.5 root 1025: /* search for an interrupt */
1.1.1.6 root 1026: ipl_sr = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_I0) & BITMASK(2);
1.1.1.5 root 1027: index = 0xffff;
1028: ipl_to_raise = -1;
1029:
1030: /* Arbitrate between all pending interrupts */
1031: for (i=0; i<12; i++) {
1.1.1.6 root 1032: if (dsp_core.interrupt_isPending[i] == 1) {
1.1.1.5 root 1033:
1034: /* level 3 interrupt ? */
1.1.1.6 root 1035: if (dsp_core.interrupt_ipl[i] == 3) {
1.1.1.5 root 1036: index = i;
1037: break;
1038: }
1.1 root 1039:
1.1.1.5 root 1040: /* level 0, 1 ,2 interrupt ? */
1041: /* if interrupt is masked in SR, don't process it */
1.1.1.6 root 1042: if (dsp_core.interrupt_ipl[i] < ipl_sr)
1.1.1.5 root 1043: continue;
1.1 root 1044:
1.1.1.5 root 1045: /* if interrupt is lower or equal than current arbitrated interrupt */
1.1.1.6 root 1046: if (dsp_core.interrupt_ipl[i] <= ipl_to_raise)
1.1.1.5 root 1047: continue;
1048:
1049: /* save current arbitrated interrupt */
1050: index = i;
1.1.1.6 root 1051: ipl_to_raise = dsp_core.interrupt_ipl[i];
1.1 root 1052: }
1053: }
1.1.1.4 root 1054:
1.1.1.5 root 1055: /* If there's no interrupt to process, return */
1056: if (index == 0xffff) {
1.1.1.4 root 1057: return;
1058: }
1059:
1.1.1.5 root 1060: /* remove this interrupt from the pending interrupts table */
1.1.1.6 root 1061: dsp_core.interrupt_isPending[index] = 0;
1062: dsp_core.interrupt_counter --;
1.1.1.5 root 1063:
1064: /* process arbritrated interrupt */
1.1.1.6 root 1065: ipl_to_raise = dsp_core.interrupt_ipl[index] + 1;
1.1.1.5 root 1066: if (ipl_to_raise > 3) {
1067: ipl_to_raise = 3;
1068: }
1069:
1.1.1.6 root 1070: dsp_core.interrupt_instr_fetch = dsp_interrupt[index].vectorAddr;
1071: dsp_core.interrupt_pipeline_count = 5;
1072: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1073: dsp_core.interrupt_IplToRaise = ipl_to_raise;
1074:
1075: LOG_TRACE(TRACE_DSP_INTERRUPT, "Dsp interrupt: %s\n", dsp_interrupt[index].name);
1.1.1.5 root 1076:
1077: /* SSI receive data with exception ? */
1.1.1.6 root 1078: if (dsp_core.interrupt_instr_fetch == 0xe) {
1079: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_ROE);
1.1.1.4 root 1080: }
1081:
1.1.1.5 root 1082: /* SSI transmit data with exception ? */
1.1.1.6 root 1083: else if (dsp_core.interrupt_instr_fetch == 0x12) {
1084: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_TUE);
1.1.1.4 root 1085: }
1086:
1087: /* host command ? */
1.1.1.6 root 1088: else if (dsp_core.interrupt_instr_fetch == 0xff) {
1.1.1.4 root 1089: /* Clear HC and HCP interrupt */
1.1.1.6 root 1090: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] &= 0xff - (1<<DSP_HOST_HSR_HCP);
1.1.1.11! root 1091: dsp_core.hostport[CPU_HOST_CVR] &= 0xff - (1<<CPU_HOST_CVR_HC);
1.1.1.4 root 1092:
1.1.1.6 root 1093: dsp_core.interrupt_instr_fetch = dsp_core.hostport[CPU_HOST_CVR] & BITMASK(5);
1.1.1.11! root 1094: dsp_core.interrupt_instr_fetch *= 2;
1.1.1.4 root 1095: }
1.1 root 1096: }
1097:
1098: /**********************************
1099: * Set/clear ccr bits
1100: **********************************/
1101:
1102: /* reg0 has bits 55..48 */
1103: /* reg1 has bits 47..24 */
1104: /* reg2 has bits 23..0 */
1105:
1.1.1.11! root 1106: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2)
1.1.1.6 root 1107: {
1108: Uint32 scaling, value_e, value_u;
1.1.1.4 root 1109:
1.1.1.6 root 1110: /* Initialize SR register */
1111: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E) | (1<<DSP_SR_U) | (1<<DSP_SR_N) | (1<<DSP_SR_Z));
1.1.1.4 root 1112:
1.1.1.6 root 1113: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
1.1 root 1114: switch(scaling) {
1115: case 0:
1.1.1.6 root 1116: /* Extension Bit (E) */
1117: value_e = (reg0<<1) + (reg1>>23);
1118: if ((value_e != 0) && (value_e != BITMASK(9)))
1119: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1120:
1121: /* Unnormalized bit (U) */
1.1.1.11! root 1122: if ((reg1 & 0xc00000) == 0 || (reg1 & 0xc00000) == 0xc00000)
1.1.1.6 root 1123: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1124: break;
1125: case 1:
1.1.1.6 root 1126: /* Extension Bit (E) */
1127: if ((reg0 != 0) && (reg0 != BITMASK(8)))
1128: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1129:
1130: /* Unnormalized bit (U) */
1131: value_u = ((reg0<<1) + (reg1>>23)) & 3;
1.1.1.11! root 1132: if (value_u == 0 || value_u == 3)
1.1.1.6 root 1133: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1134: break;
1135: case 2:
1.1.1.6 root 1136: /* Extension Bit (E) */
1137: value_e = (reg0<<2) + (reg1>>22);
1138: if ((value_e != 0) && (value_e != BITMASK(10)))
1139: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1140:
1141: /* Unnormalized bit (U) */
1.1.1.11! root 1142: if ((reg1 & 0x600000) == 0 || (reg1 & 0x600000) == 0x600000)
1.1.1.6 root 1143: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1144: break;
1145: default:
1146: return;
1147: break;
1148: }
1149:
1.1.1.6 root 1150: /* Zero Flag (Z) */
1151: if ((reg1 == 0) && (reg2 == 0) && (reg0 == 0))
1152: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_Z;
1.1.1.4 root 1153:
1.1.1.6 root 1154: /* Negative Flag (N) */
1155: dsp_core.registers[DSP_REG_SR] |= (reg0>>4) & 0x8;
1.1 root 1156: }
1157:
1158: /**********************************
1159: * Read/Write memory functions
1160: **********************************/
1161:
1.1.1.2 root 1162: static Uint32 read_memory_disasm(int space, Uint16 address)
1.1 root 1163: {
1.1.1.4 root 1164: /* Internal RAM ? */
1165: if (address<0x100) {
1.1.1.6 root 1166: return dsp_core.ramint[space][address] & BITMASK(24);
1.1.1.4 root 1167: }
1.1 root 1168:
1.1.1.4 root 1169: if (space==DSP_SPACE_P) {
1170: return read_memory_p(address);
1.1 root 1171: }
1172:
1.1.1.4 root 1173: /* Internal ROM? */
1.1.1.6 root 1174: if ((dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) &&
1.1.1.4 root 1175: (address<0x200)) {
1.1.1.6 root 1176: return dsp_core.rom[space][address] & BITMASK(24);
1.1.1.4 root 1177: }
1178:
1179: /* Peripheral address ? */
1180: if (address >= 0xffc0) {
1.1.1.6 root 1181: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_HOST_HTX)) {
1182: return dsp_core.dsp_host_htx;
1.1.1.4 root 1183: }
1184: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_SSI_TX)) {
1.1.1.6 root 1185: return dsp_core.ssi.transmit_value;
1.1.1.4 root 1186: }
1.1.1.6 root 1187: return dsp_core.periph[space][address-0xffc0] & BITMASK(24);
1.1.1.4 root 1188: }
1189:
1190: /* Falcon: External RAM, map X to upper 16K of matching space in Y,P */
1191: address &= (DSP_RAMSIZE>>1) - 1;
1192: if (space == DSP_SPACE_X) {
1193: address += DSP_RAMSIZE>>1;
1194: }
1195:
1196: /* Falcon: External RAM, finally map X,Y to P */
1.1.1.6 root 1197: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1.1 root 1198: }
1199:
1.1.1.4 root 1200: static inline Uint32 read_memory_p(Uint16 address)
1201: {
1202: /* Internal RAM ? */
1.1.1.7 root 1203: if (address < 0x200) {
1.1.1.6 root 1204: return dsp_core.ramint[DSP_SPACE_P][address] & BITMASK(24);
1.1.1.4 root 1205: }
1206:
1.1.1.9 root 1207: /* Access to the external P memory */
1208: access_to_ext_memory |= 1 << EXT_P_MEMORY;
1.1.1.7 root 1209:
1.1.1.4 root 1210: /* External RAM, mask address to available ram size */
1.1.1.6 root 1211: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1.1.1.4 root 1212: }
1213:
1.1.1.2 root 1214: static Uint32 read_memory(int space, Uint16 address)
1.1 root 1215: {
1.1.1.4 root 1216: Uint32 value;
1.1 root 1217:
1.1.1.4 root 1218: /* Internal RAM ? */
1219: if (address < 0x100) {
1.1.1.6 root 1220: return dsp_core.ramint[space][address] & BITMASK(24);
1.1.1.4 root 1221: }
1.1 root 1222:
1.1.1.4 root 1223: if (space == DSP_SPACE_P) {
1224: return read_memory_p(address);
1225: }
1226:
1227: /* Internal ROM ? */
1228: if (address < 0x200) {
1.1.1.6 root 1229: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1230: return dsp_core.rom[space][address] & BITMASK(24);
1.1.1.4 root 1231: }
1232: }
1233:
1234: /* Peripheral address ? */
1235: if (address >= 0xffc0) {
1.1.1.6 root 1236: value = dsp_core.periph[space][address-0xffc0] & BITMASK(24);
1.1.1.4 root 1237: if (space == DSP_SPACE_X) {
1238: if (address == 0xffc0+DSP_HOST_HRX) {
1.1.1.6 root 1239: value = dsp_core.dsp_host_rtx;
1240: dsp_core_hostport_dspread();
1.1.1.11! root 1241: }
1.1.1.4 root 1242: else if (address == 0xffc0+DSP_SSI_RX) {
1.1.1.6 root 1243: value = dsp_core_ssi_readRX();
1.1 root 1244: }
1.1.1.4 root 1245: }
1246: return value;
1.1 root 1247: }
1248:
1.1.1.9 root 1249: /* Falcon: External X or Y RAM access */
1.1.1.4 root 1250: address &= (DSP_RAMSIZE>>1) - 1;
1251:
1252: if (space == DSP_SPACE_X) {
1.1.1.9 root 1253: /* Map X to upper 16K of matching space in Y,P */
1.1.1.4 root 1254: address += DSP_RAMSIZE>>1;
1.1.1.9 root 1255:
1256: /* Set one access to the X external memory */
1257: access_to_ext_memory |= 1 << EXT_X_MEMORY;
1258: }
1259: else {
1260: /* Access to the Y external memory */
1261: access_to_ext_memory |= 1 << EXT_Y_MEMORY;
1.1.1.4 root 1262: }
1263:
1.1.1.9 root 1264:
1.1.1.4 root 1265: /* Falcon: External RAM, finally map X,Y to P */
1.1.1.6 root 1266: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1267: }
1268:
1269: static inline void write_memory(int space, Uint16 address, Uint32 value)
1270: {
1.1.1.7 root 1271: if (unlikely(LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM)))
1.1.1.6 root 1272: write_memory_disasm(space, address, value);
1.1.1.11! root 1273: else
1.1.1.6 root 1274: write_memory_raw(space, address, value);
1.1 root 1275: }
1276:
1.1.1.4 root 1277: static void write_memory_raw(int space, Uint16 address, Uint32 value)
1.1 root 1278: {
1279: value &= BITMASK(24);
1280:
1.1.1.4 root 1281: /* Peripheral address ? */
1282: if (address >= 0xffc0) {
1283: if (space == DSP_SPACE_X) {
1284: switch(address-0xffc0) {
1285: case DSP_HOST_HTX:
1.1.1.6 root 1286: dsp_core.dsp_host_htx = value;
1287: dsp_core_hostport_dspwrite();
1.1.1.4 root 1288: break;
1289: case DSP_HOST_HCR:
1.1.1.6 root 1290: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] = value;
1.1.1.4 root 1291: /* Set HF3 and HF2 accordingly on the host side */
1.1.1.6 root 1292: dsp_core.hostport[CPU_HOST_ISR] &=
1.1.1.4 root 1293: BITMASK(8)-((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1.1.1.6 root 1294: dsp_core.hostport[CPU_HOST_ISR] |=
1295: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] & ((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1.1.1.4 root 1296: break;
1297: case DSP_HOST_HSR:
1298: /* Read only */
1299: break;
1300: case DSP_SSI_CRA:
1301: case DSP_SSI_CRB:
1.1.1.6 root 1302: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1303: dsp_core_ssi_configure(address-0xffc0, value);
1.1.1.4 root 1304: break;
1305: case DSP_SSI_TSR:
1.1.1.6 root 1306: dsp_core_ssi_writeTSR();
1.1.1.4 root 1307: break;
1308: case DSP_SSI_TX:
1.1.1.6 root 1309: dsp_core_ssi_writeTX(value);
1.1.1.4 root 1310: break;
1.1.1.5 root 1311: case DSP_IPR:
1.1.1.6 root 1312: dsp_core.periph[DSP_SPACE_X][DSP_IPR] = value;
1.1.1.5 root 1313: dsp_setInterruptIPL(value);
1314: break;
1315: case DSP_PCD:
1.1.1.6 root 1316: dsp_core.periph[DSP_SPACE_X][DSP_PCD] = value;
1317: dsp_core_setPortCDataRegister(value);
1.1.1.5 root 1318: break;
1.1.1.4 root 1319: default:
1.1.1.6 root 1320: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1.1.1.4 root 1321: break;
1.1 root 1322: }
1.1.1.4 root 1323: return;
1.1.1.11! root 1324: }
1.1.1.4 root 1325: else if (space == DSP_SPACE_Y) {
1.1.1.6 root 1326: dsp_core.periph[DSP_SPACE_Y][address-0xffc0] = value;
1.1.1.4 root 1327: return;
1328: }
1329: }
1.1.1.11! root 1330:
1.1.1.4 root 1331: /* Internal RAM ? */
1332: if (address < 0x100) {
1.1.1.6 root 1333: dsp_core.ramint[space][address] = value;
1.1.1.4 root 1334: return;
1335: }
1.1.1.2 root 1336:
1.1.1.4 root 1337: /* Internal ROM ? */
1338: if (address < 0x200) {
1339: if (space != DSP_SPACE_P) {
1.1.1.6 root 1340: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1.1.1.2 root 1341: /* Can not write to ROM space */
1.1 root 1342: return;
1343: }
1.1.1.4 root 1344: }
1345: else {
1346: /* Space P RAM */
1.1.1.6 root 1347: dsp_core.ramint[DSP_SPACE_P][address] = value;
1.1.1.4 root 1348: return;
1349: }
1.1 root 1350: }
1351:
1.1.1.9 root 1352: /* Access to X, Y or P external RAM */
1.1.1.4 root 1353:
1.1.1.9 root 1354: if (space == DSP_SPACE_P) {
1355: /* Access to the P external RAM */
1356: access_to_ext_memory |= 1 << EXT_P_MEMORY;
1357: }
1358: else {
1.1.1.4 root 1359: address &= (DSP_RAMSIZE>>1) - 1;
1360:
1.1.1.9 root 1361: if (space == DSP_SPACE_X) {
1362: /* Access to the X external RAM */
1363: /* map X to upper 16K of matching space in Y,P */
1364: address += DSP_RAMSIZE>>1;
1365: access_to_ext_memory |= 1;
1366: }
1367: else {
1368: /* Access to the Y external RAM */
1369: access_to_ext_memory |= 1 << EXT_Y_MEMORY;
1370: }
1.1.1.4 root 1371: }
1372:
1373: /* Falcon: External RAM, map X,Y to P */
1.1.1.6 root 1374: dsp_core.ramext[address & (DSP_RAMSIZE-1)] = value;
1.1.1.2 root 1375: }
1376:
1.1.1.4 root 1377: static void write_memory_disasm(int space, Uint16 address, Uint32 value)
1.1.1.2 root 1378: {
1.1.1.4 root 1379: Uint32 oldvalue, curvalue;
1380: Uint8 space_c = 'p';
1381:
1.1.1.2 root 1382: value &= BITMASK(24);
1.1.1.6 root 1383: oldvalue = read_memory_disasm(space, address);
1.1.1.2 root 1384:
1385: write_memory_raw(space,address,value);
1386:
1.1 root 1387: switch(space) {
1388: case DSP_SPACE_X:
1.1.1.4 root 1389: space_c = 'x';
1.1 root 1390: break;
1391: case DSP_SPACE_Y:
1.1.1.4 root 1392: space_c = 'y';
1393: break;
1394: default:
1.1 root 1395: break;
1396: }
1.1.1.4 root 1397:
1.1.1.6 root 1398: curvalue = read_memory_disasm(space, address);
1.1.1.5 root 1399: sprintf(str_disasm_memory[disasm_memory_ptr],"Mem: %c:0x%04x 0x%06x -> 0x%06x", space_c, address, oldvalue, curvalue);
1400: disasm_memory_ptr ++;
1.1 root 1401: }
1402:
1.1.1.4 root 1403: static void dsp_write_reg(Uint32 numreg, Uint32 value)
1404: {
1.1.1.5 root 1405: Uint32 stack_error;
1.1.1.4 root 1406:
1.1.1.7 root 1407: switch (numreg) {
1408: case DSP_REG_A:
1409: dsp_core.registers[DSP_REG_A0] = 0;
1.1.1.11! root 1410: dsp_core.registers[DSP_REG_A1] = value & BITMASK(24);
1.1.1.7 root 1411: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
1412: break;
1413: case DSP_REG_B:
1414: dsp_core.registers[DSP_REG_B0] = 0;
1.1.1.11! root 1415: dsp_core.registers[DSP_REG_B1] = value & BITMASK(24);
1.1.1.7 root 1416: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
1417: break;
1.1.1.11! root 1418: case DSP_REG_R0:
! 1419: case DSP_REG_R1:
! 1420: case DSP_REG_R2:
! 1421: case DSP_REG_R3:
! 1422: case DSP_REG_R4:
! 1423: case DSP_REG_R5:
! 1424: case DSP_REG_R6:
! 1425: case DSP_REG_R7:
! 1426: case DSP_REG_N0:
! 1427: case DSP_REG_N1:
! 1428: case DSP_REG_N2:
! 1429: case DSP_REG_N3:
! 1430: case DSP_REG_N4:
! 1431: case DSP_REG_N5:
! 1432: case DSP_REG_N6:
! 1433: case DSP_REG_N7:
! 1434: case DSP_REG_M0:
! 1435: case DSP_REG_M1:
! 1436: case DSP_REG_M2:
! 1437: case DSP_REG_M3:
! 1438: case DSP_REG_M4:
! 1439: case DSP_REG_M5:
! 1440: case DSP_REG_M6:
! 1441: case DSP_REG_M7:
! 1442: dsp_core.registers[numreg] = value & BITMASK(16);
! 1443: break;
1.1.1.7 root 1444: case DSP_REG_OMR:
1445: dsp_core.registers[DSP_REG_OMR] = value & 0xc7;
1446: break;
1447: case DSP_REG_SR:
1448: dsp_core.registers[DSP_REG_SR] = value & 0xaf7f;
1449: break;
1450: case DSP_REG_SP:
1.1.1.8 root 1451: stack_error = dsp_core.registers[DSP_REG_SP] & (3<<DSP_SP_SE);
1452: if ((stack_error==0) && (value & (3<<DSP_SP_SE))) {
1453: /* Stack underflow or overflow detected, raise interrupt */
1.1.1.7 root 1454: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.9 root 1455: dsp_core.registers[DSP_REG_SP] = value & (3<<DSP_SP_SE);
1.1.1.7 root 1456: if (!isDsp_in_disasm_mode)
1.1.1.8 root 1457: fprintf(stderr,"Dsp: Stack Overflow or Underflow\n");
1.1.1.10 root 1458: if (ExceptionDebugMask & EXCEPT_DSP)
1.1.1.9 root 1459: DebugUI(REASON_DSP_EXCEPTION);
1.1.1.7 root 1460: }
1.1.1.8 root 1461: else
1.1.1.11! root 1462: dsp_core.registers[DSP_REG_SP] = value & BITMASK(6);
1.1.1.7 root 1463: dsp_compute_ssh_ssl();
1464: break;
1465: case DSP_REG_SSH:
1466: dsp_stack_push(value, 0, 1);
1467: break;
1468: case DSP_REG_SSL:
1469: numreg = dsp_core.registers[DSP_REG_SP] & BITMASK(4);
1470: if (numreg == 0) {
1471: value = 0;
1472: }
1473: dsp_core.stack[1][numreg] = value & BITMASK(16);
1474: dsp_core.registers[DSP_REG_SSL] = value & BITMASK(16);
1475: break;
1476: default:
1.1.1.11! root 1477: dsp_core.registers[numreg] = value;
1.1.1.7 root 1478: dsp_core.registers[numreg] &= BITMASK(registers_mask[numreg]);
1479: break;
1.1.1.4 root 1480: }
1481: }
1482:
1.1 root 1483: /**********************************
1484: * Stack push/pop
1485: **********************************/
1486:
1.1.1.4 root 1487: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly)
1.1 root 1488: {
1.1.1.4 root 1489: Uint32 stack_error, underflow, stack;
1490:
1.1.1.6 root 1491: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1492: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1493: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) + 1;
1.1.1.4 root 1494:
1495:
1496: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1.1 root 1497: /* Stack full, raise interrupt */
1.1.1.5 root 1498: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.6 root 1499: if (!isDsp_in_disasm_mode)
1500: fprintf(stderr,"Dsp: Stack Overflow\n");
1.1.1.10 root 1501: if (ExceptionDebugMask & EXCEPT_DSP)
1.1.1.9 root 1502: DebugUI(REASON_DSP_EXCEPTION);
1.1 root 1503: }
1.1.1.11! root 1504:
1.1.1.6 root 1505: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1.1.1.4 root 1506: stack &= BITMASK(4);
1.1 root 1507:
1.1.1.4 root 1508: if (stack) {
1509: /* SSH part */
1.1.1.6 root 1510: dsp_core.stack[0][stack] = curpc & BITMASK(16);
1.1.1.4 root 1511: /* SSL part, if instruction is not like "MOVEC xx, SSH" */
1512: if (sshOnly == 0) {
1.1.1.6 root 1513: dsp_core.stack[1][stack] = cursr & BITMASK(16);
1.1.1.4 root 1514: }
1515: } else {
1.1.1.6 root 1516: dsp_core.stack[0][0] = 0;
1517: dsp_core.stack[1][0] = 0;
1.1.1.4 root 1518: }
1.1 root 1519:
1.1.1.4 root 1520: /* Update SSH and SSL registers */
1.1.1.6 root 1521: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1522: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1 root 1523: }
1524:
1.1.1.2 root 1525: static void dsp_stack_pop(Uint32 *newpc, Uint32 *newsr)
1.1 root 1526: {
1.1.1.4 root 1527: Uint32 stack_error, underflow, stack;
1528:
1.1.1.6 root 1529: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1530: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1531: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) - 1;
1.1.1.4 root 1532:
1533: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1534: /* Stack empty*/
1.1.1.5 root 1535: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.6 root 1536: if (!isDsp_in_disasm_mode)
1537: fprintf(stderr,"Dsp: Stack underflow\n");
1.1.1.10 root 1538: if (ExceptionDebugMask & EXCEPT_DSP)
1.1.1.9 root 1539: DebugUI(REASON_DSP_EXCEPTION);
1.1 root 1540: }
1541:
1.1.1.6 root 1542: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1.1.1.4 root 1543: stack &= BITMASK(4);
1.1.1.6 root 1544: *newpc = dsp_core.registers[DSP_REG_SSH];
1545: *newsr = dsp_core.registers[DSP_REG_SSL];
1.1.1.4 root 1546:
1.1.1.6 root 1547: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1548: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1.1.4 root 1549: }
1550:
1551: static void dsp_compute_ssh_ssl(void)
1552: {
1553: Uint32 stack;
1.1 root 1554:
1.1.1.6 root 1555: stack = dsp_core.registers[DSP_REG_SP];
1.1.1.4 root 1556: stack &= BITMASK(4);
1.1.1.6 root 1557: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1558: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1 root 1559: }
1560:
1561: /**********************************
1562: * Effective address calculation
1563: **********************************/
1564:
1.1.1.2 root 1565: static void dsp_update_rn(Uint32 numreg, Sint16 modifier)
1.1 root 1566: {
1.1.1.2 root 1567: Sint16 value;
1568: Uint16 m_reg;
1.1 root 1569:
1.1.1.6 root 1570: m_reg = (Uint16) dsp_core.registers[DSP_REG_M0+numreg];
1.1.1.7 root 1571: if (m_reg == 65535) {
1572: /* Linear addressing mode */
1573: value = (Sint16) dsp_core.registers[DSP_REG_R0+numreg];
1574: value += modifier;
1575: dsp_core.registers[DSP_REG_R0+numreg] = ((Uint32) value) & BITMASK(16);
1576: } else if (m_reg == 0) {
1.1 root 1577: /* Bit reversed carry update */
1578: dsp_update_rn_bitreverse(numreg);
1.1.1.4 root 1579: } else if (m_reg<=32767) {
1.1 root 1580: /* Modulo update */
1581: dsp_update_rn_modulo(numreg, modifier);
1582: } else {
1583: /* Undefined */
1584: }
1585: }
1586:
1.1.1.2 root 1587: static void dsp_update_rn_bitreverse(Uint32 numreg)
1.1 root 1588: {
1589: int revbits, i;
1.1.1.2 root 1590: Uint32 value, r_reg;
1.1 root 1591:
1592: /* Check how many bits to reverse */
1.1.1.6 root 1593: value = dsp_core.registers[DSP_REG_N0+numreg];
1.1 root 1594: for (revbits=0;revbits<16;revbits++) {
1595: if (value & (1<<revbits)) {
1596: break;
1597: }
1.1.1.11! root 1598: }
1.1 root 1599: revbits++;
1.1.1.11! root 1600:
1.1 root 1601: /* Reverse Rn bits */
1.1.1.6 root 1602: r_reg = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1603: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1604: for (i=0;i<revbits;i++) {
1605: if (r_reg & (1<<i)) {
1606: value |= 1<<(revbits-i-1);
1607: }
1608: }
1609:
1610: /* Increment */
1611: value++;
1612: value &= BITMASK(revbits);
1613:
1614: /* Reverse Rn bits */
1615: r_reg &= (BITMASK(16)-BITMASK(revbits));
1616: r_reg |= value;
1617:
1618: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1619: for (i=0;i<revbits;i++) {
1620: if (r_reg & (1<<i)) {
1621: value |= 1<<(revbits-i-1);
1622: }
1623: }
1624:
1.1.1.6 root 1625: dsp_core.registers[DSP_REG_R0+numreg] = value;
1.1 root 1626: }
1627:
1.1.1.2 root 1628: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier)
1.1 root 1629: {
1.1.1.2 root 1630: Uint16 bufsize, modulo, lobound, hibound, bufmask;
1.1.1.4 root 1631: Sint16 r_reg, orig_modifier=modifier;
1.1 root 1632:
1.1.1.6 root 1633: modulo = dsp_core.registers[DSP_REG_M0+numreg]+1;
1.1 root 1634: bufsize = 1;
1.1.1.2 root 1635: bufmask = BITMASK(16);
1.1 root 1636: while (bufsize < modulo) {
1637: bufsize <<= 1;
1.1.1.2 root 1638: bufmask <<= 1;
1.1 root 1639: }
1.1.1.11! root 1640:
1.1.1.6 root 1641: lobound = dsp_core.registers[DSP_REG_R0+numreg] & bufmask;
1.1.1.2 root 1642: hibound = lobound + modulo - 1;
1.1 root 1643:
1.1.1.6 root 1644: r_reg = (Sint16) dsp_core.registers[DSP_REG_R0+numreg];
1.1.1.4 root 1645:
1646: if (orig_modifier>modulo) {
1647: while (modifier>bufsize) {
1648: r_reg += bufsize;
1649: modifier -= bufsize;
1650: }
1651: while (modifier<-bufsize) {
1652: r_reg -= bufsize;
1653: modifier += bufsize;
1654: }
1.1.1.2 root 1655: }
1.1.1.4 root 1656:
1.1 root 1657: r_reg += modifier;
1.1.1.4 root 1658:
1659: if (orig_modifier!=modulo) {
1660: if (r_reg>hibound) {
1661: r_reg -= modulo;
1662: } else if (r_reg<lobound) {
1663: r_reg += modulo;
1.1.1.11! root 1664: }
1.1 root 1665: }
1666:
1.1.1.6 root 1667: dsp_core.registers[DSP_REG_R0+numreg] = ((Uint32) r_reg) & BITMASK(16);
1.1 root 1668: }
1669:
1.1.1.2 root 1670: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr)
1.1 root 1671: {
1.1.1.2 root 1672: Uint32 value, numreg, curreg;
1.1 root 1673:
1674: value = (ea_mode >> 3) & BITMASK(3);
1675: numreg = ea_mode & BITMASK(3);
1676: switch (value) {
1677: case 0:
1678: /* (Rx)-Nx */
1.1.1.6 root 1679: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1680: dsp_update_rn(numreg, -dsp_core.registers[DSP_REG_N0+numreg]);
1.1 root 1681: break;
1682: case 1:
1683: /* (Rx)+Nx */
1.1.1.6 root 1684: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1685: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1.1 root 1686: break;
1687: case 2:
1688: /* (Rx)- */
1.1.1.6 root 1689: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1690: dsp_update_rn(numreg, -1);
1691: break;
1692: case 3:
1693: /* (Rx)+ */
1.1.1.6 root 1694: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1695: dsp_update_rn(numreg, +1);
1696: break;
1697: case 4:
1698: /* (Rx) */
1.1.1.6 root 1699: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1700: break;
1701: case 5:
1702: /* (Rx+Nx) */
1.1.1.6 root 1703: dsp_core.instr_cycle += 2;
1704: curreg = dsp_core.registers[DSP_REG_R0+numreg];
1705: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1706: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1707: dsp_core.registers[DSP_REG_R0+numreg] = curreg;
1.1 root 1708: break;
1709: case 6:
1710: /* aa */
1.1.1.6 root 1711: dsp_core.instr_cycle += 2;
1712: *dst_addr = read_memory_p(dsp_core.pc+1);
1.1 root 1713: cur_inst_len++;
1714: if (numreg != 0) {
1715: return 1; /* immediate value */
1716: }
1717: break;
1718: case 7:
1719: /* -(Rx) */
1.1.1.6 root 1720: dsp_core.instr_cycle += 2;
1.1 root 1721: dsp_update_rn(numreg, -1);
1.1.1.6 root 1722: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1723: break;
1724: }
1725: /* address */
1726: return 0;
1727: }
1728:
1729: /**********************************
1730: * Condition code test
1731: **********************************/
1732:
1.1.1.2 root 1733: static int dsp_calc_cc(Uint32 cc_code)
1.1 root 1734: {
1.1.1.4 root 1735: Uint16 value1, value2, value3;
1.1 root 1736:
1.1.1.4 root 1737: switch (cc_code) {
1738: case 0: /* CC (HS) */
1.1.1.6 root 1739: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1.1.1.4 root 1740: return (value1==0);
1741: case 1: /* GE */
1.1.1.6 root 1742: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1743: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1.1.1.4 root 1744: return ((value1 ^ value2) == 0);
1745: case 2: /* NE */
1.1.1.6 root 1746: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_Z);
1.1.1.4 root 1747: return (value1==0);
1748: case 3: /* PL */
1.1.1.6 root 1749: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_N);
1.1.1.4 root 1750: return (value1==0);
1751: case 4: /* NN */
1.1.1.6 root 1752: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1753: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1754: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1.1.1.4 root 1755: return ((value1 | (value2 & value3)) == 0);
1756: case 5: /* EC */
1.1.1.6 root 1757: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_E);
1.1.1.4 root 1758: return (value1==0);
1759: case 6: /* LC */
1.1.1.6 root 1760: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_L);
1.1.1.4 root 1761: return (value1==0);
1.1.1.11! root 1762: case 7: /* GT */
1.1.1.6 root 1763: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1764: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1765: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1766: return ((value3 | (value1 ^ value2)) == 0);
1767: case 8: /* CS (LO) */
1.1.1.6 root 1768: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1.1.1.4 root 1769: return (value1==1);
1770: case 9: /* LT */
1.1.1.6 root 1771: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1772: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1.1.1.4 root 1773: return ((value1 ^ value2) == 1);
1774: case 10: /* EQ */
1.1.1.6 root 1775: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1776: return (value1==1);
1777: case 11: /* MI */
1.1.1.6 root 1778: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1.1.1.4 root 1779: return (value1==1);
1780: case 12: /* NR */
1.1.1.6 root 1781: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1782: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1783: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1.1.1.4 root 1784: return ((value1 | (value2 & value3)) == 1);
1785: case 13: /* ES */
1.1.1.6 root 1786: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_E) & 1;
1.1.1.4 root 1787: return (value1==1);
1788: case 14: /* LS */
1.1.1.6 root 1789: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_L) & 1;
1.1.1.4 root 1790: return (value1==1);
1791: case 15: /* LE */
1.1.1.6 root 1792: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1793: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1794: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1795: return ((value3 | (value1 ^ value2)) == 1);
1796: }
1797: return 0;
1.1 root 1798: }
1799:
1800: /**********************************
1801: * Highbyte opcodes dispatchers
1802: **********************************/
1803:
1804: static void opcode8h_0(void)
1805: {
1.1.1.4 root 1806: switch(cur_inst) {
1807: case 0x000000:
1808: dsp_nop();
1.1 root 1809: break;
1.1.1.4 root 1810: case 0x000004:
1811: dsp_rti();
1.1 root 1812: break;
1.1.1.4 root 1813: case 0x000005:
1814: dsp_illegal();
1.1 root 1815: break;
1.1.1.4 root 1816: case 0x000006:
1817: dsp_swi();
1818: break;
1819: case 0x00000c:
1820: dsp_rts();
1821: break;
1822: case 0x000084:
1823: dsp_reset();
1824: break;
1825: case 0x000086:
1826: dsp_wait();
1827: break;
1828: case 0x000087:
1829: dsp_stop();
1830: break;
1831: case 0x00008c:
1832: dsp_enddo();
1.1 root 1833: break;
1.1.1.10 root 1834: default:
1835: dsp_undefined();
1836: break;
1.1 root 1837: }
1838: }
1839:
1840: /**********************************
1841: * Non-parallel moves instructions
1842: **********************************/
1843:
1844: static void dsp_undefined(void)
1845: {
1.1.1.6 root 1846: if (isDsp_in_disasm_mode == false) {
1847: cur_inst_len = 0;
1848: fprintf(stderr, "Dsp: 0x%04x: 0x%06x Illegal instruction\n",dsp_core.pc, cur_inst);
1.1.1.7 root 1849: /* Add some artificial CPU cycles to avoid being stuck in an infinite loop */
1.1.1.6 root 1850: dsp_core.instr_cycle += 100;
1851: }
1852: else {
1853: cur_inst_len = 1;
1854: dsp_core.instr_cycle = 0;
1855: }
1.1.1.10 root 1856: if (ExceptionDebugMask & EXCEPT_DSP) {
1.1.1.9 root 1857: DebugUI(REASON_DSP_EXCEPTION);
1858: }
1.1 root 1859: }
1860:
1861: static void dsp_andi(void)
1862: {
1.1.1.2 root 1863: Uint32 regnum, value;
1.1 root 1864:
1865: value = (cur_inst >> 8) & BITMASK(8);
1866: regnum = cur_inst & BITMASK(2);
1867: switch(regnum) {
1868: case 0:
1869: /* mr */
1.1.1.6 root 1870: dsp_core.registers[DSP_REG_SR] &= (value<<8)|BITMASK(8);
1.1 root 1871: break;
1872: case 1:
1873: /* ccr */
1.1.1.6 root 1874: dsp_core.registers[DSP_REG_SR] &= (BITMASK(8)<<8)|value;
1.1 root 1875: break;
1876: case 2:
1877: /* omr */
1.1.1.6 root 1878: dsp_core.registers[DSP_REG_OMR] &= value;
1.1 root 1879: break;
1880: }
1881: }
1882:
1.1.1.4 root 1883: static void dsp_bchg_aa(void)
1.1 root 1884: {
1.1.1.4 root 1885: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11! root 1886:
1.1 root 1887: memspace = (cur_inst>>6) & 1;
1888: value = (cur_inst>>8) & BITMASK(6);
1889: numbit = cur_inst & BITMASK(5);
1890:
1.1.1.4 root 1891: addr = value;
1892: value = read_memory(memspace, addr);
1893: newcarry = (value>>numbit) & 1;
1894: if (newcarry) {
1895: value -= (1<<numbit);
1896: } else {
1897: value += (1<<numbit);
1.1 root 1898: }
1.1.1.4 root 1899: write_memory(memspace, addr, value);
1.1 root 1900:
1901: /* Set carry */
1.1.1.6 root 1902: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1903: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1904:
1.1.1.6 root 1905: dsp_core.instr_cycle += 2;
1.1 root 1906: }
1907:
1.1.1.4 root 1908: static void dsp_bchg_ea(void)
1.1 root 1909: {
1.1.1.4 root 1910: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11! root 1911:
1.1 root 1912: memspace = (cur_inst>>6) & 1;
1913: value = (cur_inst>>8) & BITMASK(6);
1914: numbit = cur_inst & BITMASK(5);
1915:
1.1.1.4 root 1916: dsp_calc_ea(value, &addr);
1917: value = read_memory(memspace, addr);
1918: newcarry = (value>>numbit) & 1;
1919: if (newcarry) {
1920: value -= (1<<numbit);
1921: } else {
1922: value += (1<<numbit);
1.1 root 1923: }
1.1.1.4 root 1924: write_memory(memspace, addr, value);
1.1 root 1925:
1926: /* Set carry */
1.1.1.6 root 1927: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1928: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1929:
1.1.1.6 root 1930: dsp_core.instr_cycle += 2;
1.1 root 1931: }
1932:
1.1.1.4 root 1933: static void dsp_bchg_pp(void)
1.1 root 1934: {
1.1.1.4 root 1935: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11! root 1936:
1.1 root 1937: memspace = (cur_inst>>6) & 1;
1938: value = (cur_inst>>8) & BITMASK(6);
1939: numbit = cur_inst & BITMASK(5);
1940:
1.1.1.4 root 1941: addr = 0xffc0 + value;
1942: value = read_memory(memspace, addr);
1943: newcarry = (value>>numbit) & 1;
1944: if (newcarry) {
1945: value -= (1<<numbit);
1946: } else {
1947: value += (1<<numbit);
1.1 root 1948: }
1.1.1.4 root 1949: write_memory(memspace, addr, value);
1.1 root 1950:
1951: /* Set carry */
1.1.1.6 root 1952: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1953: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1954:
1.1.1.6 root 1955: dsp_core.instr_cycle += 2;
1.1 root 1956: }
1957:
1.1.1.4 root 1958: static void dsp_bchg_reg(void)
1.1 root 1959: {
1.1.1.4 root 1960: Uint32 value, numreg, newcarry, numbit;
1.1.1.11! root 1961:
1.1.1.4 root 1962: numreg = (cur_inst>>8) & BITMASK(6);
1.1 root 1963: numbit = cur_inst & BITMASK(5);
1964:
1.1.1.4 root 1965: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
1966: dsp_pm_read_accu24(numreg, &value);
1967: } else {
1.1.1.6 root 1968: value = dsp_core.registers[numreg];
1.1 root 1969: }
1970:
1.1.1.4 root 1971: newcarry = (value>>numbit) & 1;
1972: if (newcarry) {
1973: value -= (1<<numbit);
1974: } else {
1975: value += (1<<numbit);
1976: }
1977:
1978: dsp_write_reg(numreg, value);
1979:
1.1 root 1980: /* Set carry */
1.1.1.6 root 1981: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1982: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1983:
1.1.1.6 root 1984: dsp_core.instr_cycle += 2;
1.1 root 1985: }
1986:
1.1.1.4 root 1987: static void dsp_bclr_aa(void)
1.1 root 1988: {
1.1.1.4 root 1989: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11! root 1990:
1.1.1.4 root 1991: memspace = (cur_inst>>6) & 1;
1992: addr = (cur_inst>>8) & BITMASK(6);
1993: numbit = cur_inst & BITMASK(5);
1.1 root 1994:
1.1.1.4 root 1995: value = read_memory(memspace, addr);
1996: newcarry = (value>>numbit) & 1;
1997: value &= 0xffffffff-(1<<numbit);
1998: write_memory(memspace, addr, value);
1.1.1.2 root 1999:
1.1.1.4 root 2000: /* Set carry */
1.1.1.6 root 2001: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2002: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 2003:
1.1.1.6 root 2004: dsp_core.instr_cycle += 2;
1.1.1.4 root 2005: }
1.1 root 2006:
1.1.1.4 root 2007: static void dsp_bclr_ea(void)
2008: {
2009: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11! root 2010:
1.1.1.4 root 2011: memspace = (cur_inst>>6) & 1;
2012: value = (cur_inst>>8) & BITMASK(6);
2013: numbit = cur_inst & BITMASK(5);
1.1 root 2014:
1.1.1.4 root 2015: dsp_calc_ea(value, &addr);
2016: value = read_memory(memspace, addr);
2017: newcarry = (value>>numbit) & 1;
2018: value &= 0xffffffff-(1<<numbit);
2019: write_memory(memspace, addr, value);
1.1.1.2 root 2020:
1.1.1.4 root 2021: /* Set carry */
1.1.1.6 root 2022: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2023: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2024:
1.1.1.6 root 2025: dsp_core.instr_cycle += 2;
1.1 root 2026: }
2027:
1.1.1.4 root 2028: static void dsp_bclr_pp(void)
2029: {
2030: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11! root 2031:
1.1.1.4 root 2032: memspace = (cur_inst>>6) & 1;
2033: value = (cur_inst>>8) & BITMASK(6);
2034: numbit = cur_inst & BITMASK(5);
1.1.1.3 root 2035:
1.1.1.4 root 2036: addr = 0xffc0 + value;
2037: value = read_memory(memspace, addr);
2038: newcarry = (value>>numbit) & 1;
2039: value &= 0xffffffff-(1<<numbit);
2040: write_memory(memspace, addr, value);
1.1.1.3 root 2041:
1.1.1.4 root 2042: /* Set carry */
1.1.1.6 root 2043: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2044: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 2045:
1.1.1.6 root 2046: dsp_core.instr_cycle += 2;
1.1.1.4 root 2047: }
1.1 root 2048:
1.1.1.4 root 2049: static void dsp_bclr_reg(void)
2050: {
2051: Uint32 value, numreg, newcarry, numbit;
1.1.1.11! root 2052:
1.1.1.4 root 2053: numreg = (cur_inst>>8) & BITMASK(6);
2054: numbit = cur_inst & BITMASK(5);
1.1 root 2055:
1.1.1.4 root 2056: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2057: dsp_pm_read_accu24(numreg, &value);
2058: } else {
1.1.1.6 root 2059: value = dsp_core.registers[numreg];
1.1.1.4 root 2060: }
1.1 root 2061:
1.1.1.4 root 2062: newcarry = (value>>numbit) & 1;
2063: value &= 0xffffffff-(1<<numbit);
1.1 root 2064:
1.1.1.4 root 2065: dsp_write_reg(numreg, value);
2066:
2067: /* Set carry */
1.1.1.6 root 2068: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2069: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 2070:
1.1.1.6 root 2071: dsp_core.instr_cycle += 2;
1.1 root 2072: }
2073:
1.1.1.4 root 2074: static void dsp_bset_aa(void)
1.1 root 2075: {
1.1.1.4 root 2076: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11! root 2077:
1.1.1.4 root 2078: memspace = (cur_inst>>6) & 1;
2079: value = (cur_inst>>8) & BITMASK(6);
2080: numbit = cur_inst & BITMASK(5);
1.1 root 2081:
1.1.1.4 root 2082: addr = value;
2083: value = read_memory(memspace, addr);
2084: newcarry = (value>>numbit) & 1;
2085: value |= (1<<numbit);
2086: write_memory(memspace, addr, value);
2087:
2088: /* Set carry */
1.1.1.6 root 2089: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2090: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2091:
1.1.1.6 root 2092: dsp_core.instr_cycle += 2;
1.1.1.4 root 2093: }
2094:
2095: static void dsp_bset_ea(void)
2096: {
2097: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11! root 2098:
1.1.1.4 root 2099: memspace = (cur_inst>>6) & 1;
2100: value = (cur_inst>>8) & BITMASK(6);
2101: numbit = cur_inst & BITMASK(5);
2102:
2103: dsp_calc_ea(value, &addr);
2104: value = read_memory(memspace, addr);
2105: newcarry = (value>>numbit) & 1;
2106: value |= (1<<numbit);
2107: write_memory(memspace, addr, value);
2108:
2109: /* Set carry */
1.1.1.6 root 2110: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2111: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2112:
1.1.1.6 root 2113: dsp_core.instr_cycle += 2;
1.1.1.4 root 2114: }
2115:
2116: static void dsp_bset_pp(void)
2117: {
2118: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11! root 2119:
1.1.1.4 root 2120: memspace = (cur_inst>>6) & 1;
2121: value = (cur_inst>>8) & BITMASK(6);
2122: numbit = cur_inst & BITMASK(5);
2123: addr = 0xffc0 + value;
2124: value = read_memory(memspace, addr);
2125: newcarry = (value>>numbit) & 1;
2126: value |= (1<<numbit);
2127: write_memory(memspace, addr, value);
2128:
2129: /* Set carry */
1.1.1.6 root 2130: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2131: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2132:
1.1.1.6 root 2133: dsp_core.instr_cycle += 2;
1.1.1.4 root 2134: }
2135:
2136: static void dsp_bset_reg(void)
2137: {
2138: Uint32 value, numreg, newcarry, numbit;
1.1.1.11! root 2139:
1.1.1.4 root 2140: numreg = (cur_inst>>8) & BITMASK(6);
2141: numbit = cur_inst & BITMASK(5);
2142:
2143: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2144: dsp_pm_read_accu24(numreg, &value);
2145: } else {
1.1.1.6 root 2146: value = dsp_core.registers[numreg];
1.1.1.4 root 2147: }
2148:
2149: newcarry = (value>>numbit) & 1;
2150: value |= (1<<numbit);
2151:
2152: dsp_write_reg(numreg, value);
2153:
2154: /* Set carry */
1.1.1.6 root 2155: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2156: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2157:
1.1.1.6 root 2158: dsp_core.instr_cycle += 2;
1.1.1.4 root 2159: }
2160:
2161: static void dsp_btst_aa(void)
2162: {
2163: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11! root 2164:
1.1.1.4 root 2165: memspace = (cur_inst>>6) & 1;
2166: value = (cur_inst>>8) & BITMASK(6);
2167: numbit = cur_inst & BITMASK(5);
2168:
2169: addr = value;
2170: value = read_memory(memspace, addr);
2171: newcarry = (value>>numbit) & 1;
2172:
2173: /* Set carry */
1.1.1.6 root 2174: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2175: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2176:
1.1.1.6 root 2177: dsp_core.instr_cycle += 2;
1.1.1.4 root 2178: }
2179:
2180: static void dsp_btst_ea(void)
2181: {
2182: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11! root 2183:
1.1.1.4 root 2184: memspace = (cur_inst>>6) & 1;
2185: value = (cur_inst>>8) & BITMASK(6);
2186: numbit = cur_inst & BITMASK(5);
2187:
2188: dsp_calc_ea(value, &addr);
2189: value = read_memory(memspace, addr);
2190: newcarry = (value>>numbit) & 1;
2191:
2192: /* Set carry */
1.1.1.6 root 2193: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2194: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2195:
1.1.1.6 root 2196: dsp_core.instr_cycle += 2;
1.1.1.4 root 2197: }
2198:
2199: static void dsp_btst_pp(void)
2200: {
2201: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11! root 2202:
1.1.1.4 root 2203: memspace = (cur_inst>>6) & 1;
2204: value = (cur_inst>>8) & BITMASK(6);
2205: numbit = cur_inst & BITMASK(5);
2206:
2207: addr = 0xffc0 + value;
2208: value = read_memory(memspace, addr);
2209: newcarry = (value>>numbit) & 1;
2210:
2211: /* Set carry */
1.1.1.6 root 2212: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2213: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2214:
1.1.1.6 root 2215: dsp_core.instr_cycle += 2;
1.1.1.4 root 2216: }
2217:
2218: static void dsp_btst_reg(void)
2219: {
2220: Uint32 value, numreg, newcarry, numbit;
1.1.1.11! root 2221:
1.1.1.4 root 2222: numreg = (cur_inst>>8) & BITMASK(6);
2223: numbit = cur_inst & BITMASK(5);
2224:
2225: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2226: dsp_pm_read_accu24(numreg, &value);
2227: } else {
1.1.1.6 root 2228: value = dsp_core.registers[numreg];
1.1.1.4 root 2229: }
2230:
2231: newcarry = (value>>numbit) & 1;
2232:
2233: /* Set carry */
1.1.1.6 root 2234: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2235: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2236:
1.1.1.6 root 2237: dsp_core.instr_cycle += 2;
1.1.1.4 root 2238: }
2239:
2240: static void dsp_div(void)
2241: {
2242: Uint32 srcreg, destreg, source[3], dest[3];
2243: Uint16 newsr;
2244:
2245: srcreg = DSP_REG_NULL;
2246: switch((cur_inst>>4) & BITMASK(2)) {
2247: case 0: srcreg = DSP_REG_X0; break;
2248: case 1: srcreg = DSP_REG_Y0; break;
2249: case 2: srcreg = DSP_REG_X1; break;
2250: case 3: srcreg = DSP_REG_Y1; break;
2251: }
1.1.1.7 root 2252: source[2] = 0;
2253: source[1] = dsp_core.registers[srcreg];
2254: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.4 root 2255:
1.1.1.7 root 2256: destreg = DSP_REG_A + ((cur_inst>>3) & 1);
2257: if (destreg == DSP_REG_A) {
2258: dest[0] = dsp_core.registers[DSP_REG_A2];
2259: dest[1] = dsp_core.registers[DSP_REG_A1];
2260: dest[2] = dsp_core.registers[DSP_REG_A0];
2261: }
2262: else {
2263: dest[0] = dsp_core.registers[DSP_REG_B2];
2264: dest[1] = dsp_core.registers[DSP_REG_B1];
2265: dest[2] = dsp_core.registers[DSP_REG_B0];
2266: }
1.1.1.4 root 2267:
2268: if (((dest[0]>>7) & 1) ^ ((source[1]>>23) & 1)) {
2269: /* D += S */
2270: newsr = dsp_asl56(dest);
2271: dsp_add56(source, dest);
2272: } else {
2273: /* D -= S */
2274: newsr = dsp_asl56(dest);
2275: dsp_sub56(source, dest);
2276: }
2277:
1.1.1.6 root 2278: dest[2] |= (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1.1.4 root 2279:
1.1.1.7 root 2280: if (destreg == DSP_REG_A) {
2281: dsp_core.registers[DSP_REG_A2] = dest[0];
2282: dsp_core.registers[DSP_REG_A1] = dest[1];
2283: dsp_core.registers[DSP_REG_A0] = dest[2];
2284: }
2285: else {
2286: dsp_core.registers[DSP_REG_B2] = dest[0];
2287: dsp_core.registers[DSP_REG_B1] = dest[1];
2288: dsp_core.registers[DSP_REG_B0] = dest[2];
2289: }
1.1.1.11! root 2290:
1.1.1.6 root 2291: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
2292: dsp_core.registers[DSP_REG_SR] |= (1-((dest[0]>>7) & 1))<<DSP_SR_C;
2293: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_L);
2294: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_V);
1.1.1.4 root 2295: }
2296:
2297: /*
2298: DO instruction parameter encoding
2299:
2300: xxxxxxxx 00xxxxxx 0xxxxxxx aa
2301: xxxxxxxx 01xxxxxx 0xxxxxxx ea
2302: xxxxxxxx YYxxxxxx 1xxxxxxx imm
2303: xxxxxxxx 11xxxxxx 0xxxxxxx reg
2304: */
2305:
2306: static void dsp_do_aa(void)
2307: {
2308: Uint32 memspace, addr;
2309:
2310: /* x:aa */
2311: /* y:aa */
2312:
1.1.1.6 root 2313: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2314: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2315: cur_inst_len++;
1.1.1.6 root 2316: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2317: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1 root 2318:
2319: memspace = (cur_inst>>6) & 1;
2320: addr = (cur_inst>>8) & BITMASK(6);
1.1.1.6 root 2321: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
1.1.1.4 root 2322:
1.1.1.6 root 2323: dsp_core.instr_cycle += 4;
1.1 root 2324: }
2325:
1.1.1.3 root 2326: static void dsp_do_imm(void)
1.1 root 2327: {
2328: /* #xx */
1.1.1.3 root 2329:
1.1.1.6 root 2330: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2331: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2332: cur_inst_len++;
1.1.1.6 root 2333: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2334: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2335:
1.1.1.6 root 2336: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
1.1.1.3 root 2337: + ((cur_inst & BITMASK(4))<<8);
1.1.1.4 root 2338:
1.1.1.6 root 2339: dsp_core.instr_cycle += 4;
1.1 root 2340: }
2341:
1.1.1.3 root 2342: static void dsp_do_ea(void)
1.1 root 2343: {
1.1.1.2 root 2344: Uint32 memspace, ea_mode, addr;
1.1 root 2345:
2346: /* x:ea */
2347: /* y:ea */
2348:
1.1.1.6 root 2349: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2350: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2351: cur_inst_len++;
1.1.1.6 root 2352: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2353: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2354:
1.1 root 2355: memspace = (cur_inst>>6) & 1;
2356: ea_mode = (cur_inst>>8) & BITMASK(6);
2357: dsp_calc_ea(ea_mode, &addr);
1.1.1.6 root 2358: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
1.1.1.4 root 2359:
1.1.1.6 root 2360: dsp_core.instr_cycle += 4;
1.1 root 2361: }
2362:
1.1.1.3 root 2363: static void dsp_do_reg(void)
1.1 root 2364: {
1.1.1.2 root 2365: Uint32 numreg;
1.1 root 2366:
2367: /* S */
2368:
1.1.1.6 root 2369: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2370: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2371: cur_inst_len++;
2372:
1.1 root 2373: numreg = (cur_inst>>8) & BITMASK(6);
2374: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11! root 2375: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
1.1 root 2376: } else {
1.1.1.6 root 2377: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
1.1 root 2378: }
1.1.1.6 root 2379: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.4 root 2380:
1.1.1.6 root 2381: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2382: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2383:
1.1.1.6 root 2384: dsp_core.instr_cycle += 4;
1.1 root 2385: }
2386:
2387: static void dsp_enddo(void)
2388: {
1.1.1.4 root 2389: Uint32 saved_pc, saved_sr;
1.1 root 2390:
1.1.1.4 root 2391: dsp_stack_pop(&saved_pc, &saved_sr);
1.1.1.6 root 2392: dsp_core.registers[DSP_REG_SR] &= 0x7f;
2393: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
2394: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
1.1 root 2395: }
2396:
2397: static void dsp_illegal(void)
2398: {
2399: /* Raise interrupt p:0x003e */
1.1.1.5 root 2400: dsp_add_interrupt(DSP_INTER_ILLEGAL);
1.1.1.10 root 2401: if (ExceptionDebugMask & EXCEPT_DSP) {
1.1.1.9 root 2402: DebugUI(REASON_DSP_EXCEPTION);
2403: }
1.1 root 2404: }
2405:
1.1.1.4 root 2406: static void dsp_jcc_imm(void)
1.1 root 2407: {
1.1.1.4 root 2408: Uint32 cc_code, newpc;
1.1 root 2409:
1.1.1.4 root 2410: newpc = cur_inst & BITMASK(12);
2411: cc_code=(cur_inst>>12) & BITMASK(4);
2412: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2413: dsp_core.pc = newpc;
1.1.1.4 root 2414: cur_inst_len = 0;
2415: }
2416:
1.1.1.6 root 2417: dsp_core.instr_cycle += 2;
1.1.1.4 root 2418: }
2419:
2420: static void dsp_jcc_ea(void)
2421: {
2422: Uint32 newpc, cc_code;
2423:
2424: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2425: cc_code=cur_inst & BITMASK(4);
1.1 root 2426:
2427: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2428: dsp_core.pc = newpc;
1.1 root 2429: cur_inst_len = 0;
2430: }
1.1.1.4 root 2431:
1.1.1.6 root 2432: dsp_core.instr_cycle += 2;
1.1 root 2433: }
2434:
1.1.1.4 root 2435: static void dsp_jclr_aa(void)
1.1 root 2436: {
1.1.1.4 root 2437: Uint32 memspace, addr, value, numbit, newaddr;
1.1.1.11! root 2438:
1.1 root 2439: memspace = (cur_inst>>6) & 1;
1.1.1.4 root 2440: addr = (cur_inst>>8) & BITMASK(6);
1.1 root 2441: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2442: value = read_memory(memspace, addr);
1.1.1.6 root 2443: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2444:
1.1.1.6 root 2445: dsp_core.instr_cycle += 4;
1.1 root 2446:
1.1.1.4 root 2447: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2448: dsp_core.pc = newaddr;
1.1.1.4 root 2449: cur_inst_len = 0;
2450: return;
1.1.1.11! root 2451: }
1.1.1.2 root 2452: ++cur_inst_len;
1.1.1.4 root 2453: }
2454:
2455: static void dsp_jclr_ea(void)
2456: {
2457: Uint32 memspace, addr, value, numbit, newaddr;
1.1.1.11! root 2458:
1.1.1.4 root 2459: memspace = (cur_inst>>6) & 1;
2460: value = (cur_inst>>8) & BITMASK(6);
2461: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2462: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11! root 2463:
1.1.1.4 root 2464: dsp_calc_ea(value, &addr);
2465: value = read_memory(memspace, addr);
2466:
1.1.1.6 root 2467: dsp_core.instr_cycle += 4;
1.1 root 2468:
2469: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2470: dsp_core.pc = newaddr;
1.1.1.4 root 2471: cur_inst_len = 0;
2472: return;
1.1.1.11! root 2473: }
1.1.1.4 root 2474: ++cur_inst_len;
2475: }
1.1 root 2476:
1.1.1.4 root 2477: static void dsp_jclr_pp(void)
2478: {
2479: Uint32 memspace, addr, value, numbit, newaddr;
1.1.1.11! root 2480:
1.1.1.4 root 2481: memspace = (cur_inst>>6) & 1;
2482: value = (cur_inst>>8) & BITMASK(6);
2483: numbit = cur_inst & BITMASK(5);
2484: addr = 0xffc0 + value;
2485: value = read_memory(memspace, addr);
1.1.1.6 root 2486: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2487:
1.1.1.6 root 2488: dsp_core.instr_cycle += 4;
1.1 root 2489:
1.1.1.4 root 2490: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2491: dsp_core.pc = newaddr;
1.1.1.4 root 2492: cur_inst_len = 0;
2493: return;
1.1.1.11! root 2494: }
1.1.1.4 root 2495: ++cur_inst_len;
2496: }
1.1.1.2 root 2497:
1.1.1.4 root 2498: static void dsp_jclr_reg(void)
2499: {
2500: Uint32 value, numreg, numbit, newaddr;
1.1.1.11! root 2501:
1.1.1.4 root 2502: numreg = (cur_inst>>8) & BITMASK(6);
2503: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2504: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2505:
1.1.1.4 root 2506: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2507: dsp_pm_read_accu24(numreg, &value);
2508: } else {
1.1.1.6 root 2509: value = dsp_core.registers[numreg];
1.1.1.4 root 2510: }
1.1 root 2511:
1.1.1.6 root 2512: dsp_core.instr_cycle += 4;
1.1.1.4 root 2513:
2514: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2515: dsp_core.pc = newaddr;
1.1 root 2516: cur_inst_len = 0;
2517: return;
1.1.1.11! root 2518: }
1.1.1.4 root 2519: ++cur_inst_len;
1.1 root 2520: }
2521:
1.1.1.4 root 2522: static void dsp_jmp_ea(void)
1.1 root 2523: {
1.1.1.2 root 2524: Uint32 newpc;
1.1 root 2525:
1.1.1.4 root 2526: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &newpc);
1.1 root 2527: cur_inst_len = 0;
1.1.1.6 root 2528: dsp_core.pc = newpc;
1.1 root 2529:
1.1.1.6 root 2530: dsp_core.instr_cycle += 2;
1.1.1.4 root 2531: }
2532:
2533: static void dsp_jmp_imm(void)
2534: {
2535: Uint32 newpc;
1.1 root 2536:
1.1.1.4 root 2537: newpc = cur_inst & BITMASK(12);
2538: cur_inst_len = 0;
1.1.1.6 root 2539: dsp_core.pc = newpc;
1.1.1.4 root 2540:
1.1.1.6 root 2541: dsp_core.instr_cycle += 2;
1.1 root 2542: }
2543:
1.1.1.4 root 2544: static void dsp_jscc_ea(void)
1.1 root 2545: {
1.1.1.2 root 2546: Uint32 newpc, cc_code;
1.1 root 2547:
1.1.1.4 root 2548: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2549: cc_code=cur_inst & BITMASK(4);
2550:
2551: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2552: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2553: dsp_core.pc = newpc;
1.1.1.4 root 2554: cur_inst_len = 0;
1.1.1.11! root 2555: }
1.1.1.4 root 2556:
1.1.1.6 root 2557: dsp_core.instr_cycle += 2;
1.1.1.4 root 2558: }
1.1 root 2559:
1.1.1.4 root 2560: static void dsp_jscc_imm(void)
2561: {
2562: Uint32 cc_code, newpc;
2563:
2564: newpc = cur_inst & BITMASK(12);
2565: cc_code=(cur_inst>>12) & BITMASK(4);
1.1 root 2566: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2567: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2568: dsp_core.pc = newpc;
1.1.1.4 root 2569: cur_inst_len = 0;
1.1.1.11! root 2570: }
1.1.1.4 root 2571:
1.1.1.6 root 2572: dsp_core.instr_cycle += 2;
1.1.1.4 root 2573: }
1.1 root 2574:
1.1.1.4 root 2575: static void dsp_jsclr_aa(void)
2576: {
2577: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11! root 2578:
1.1.1.4 root 2579: memspace = (cur_inst>>6) & 1;
2580: addr = (cur_inst>>8) & BITMASK(6);
2581: numbit = cur_inst & BITMASK(5);
2582: value = read_memory(memspace, addr);
1.1.1.6 root 2583: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11! root 2584:
1.1.1.6 root 2585: dsp_core.instr_cycle += 4;
1.1.1.11! root 2586:
1.1.1.4 root 2587: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2588: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2589: newpc = newaddr;
1.1.1.6 root 2590: dsp_core.pc = newpc;
1.1 root 2591: cur_inst_len = 0;
1.1.1.4 root 2592: return;
1.1.1.11! root 2593: }
1.1.1.4 root 2594: ++cur_inst_len;
1.1 root 2595: }
2596:
1.1.1.4 root 2597: static void dsp_jsclr_ea(void)
1.1 root 2598: {
1.1.1.4 root 2599: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11! root 2600:
1.1 root 2601: memspace = (cur_inst>>6) & 1;
2602: value = (cur_inst>>8) & BITMASK(6);
2603: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2604: dsp_calc_ea(value, &addr);
2605: value = read_memory(memspace, addr);
1.1.1.6 root 2606: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2607:
1.1.1.6 root 2608: dsp_core.instr_cycle += 4;
1.1.1.11! root 2609:
1.1.1.4 root 2610: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2611: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2612: newpc = newaddr;
1.1.1.6 root 2613: dsp_core.pc = newpc;
1.1.1.4 root 2614: cur_inst_len = 0;
2615: return;
1.1.1.11! root 2616: }
1.1.1.2 root 2617: ++cur_inst_len;
1.1.1.4 root 2618: }
2619:
2620: static void dsp_jsclr_pp(void)
2621: {
2622: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11! root 2623:
1.1.1.4 root 2624: memspace = (cur_inst>>6) & 1;
2625: value = (cur_inst>>8) & BITMASK(6);
2626: numbit = cur_inst & BITMASK(5);
2627: addr = 0xffc0 + value;
2628: value = read_memory(memspace, addr);
1.1.1.6 root 2629: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2630:
1.1.1.6 root 2631: dsp_core.instr_cycle += 4;
1.1.1.11! root 2632:
1.1 root 2633: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2634: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2635: newpc = newaddr;
1.1.1.6 root 2636: dsp_core.pc = newpc;
1.1.1.4 root 2637: cur_inst_len = 0;
2638: return;
1.1.1.11! root 2639: }
1.1.1.4 root 2640: ++cur_inst_len;
2641: }
2642:
2643: static void dsp_jsclr_reg(void)
2644: {
2645: Uint32 value, numreg, newpc, numbit, newaddr;
1.1.1.11! root 2646:
1.1.1.4 root 2647: numreg = (cur_inst>>8) & BITMASK(6);
2648: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2649: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2650:
1.1.1.4 root 2651: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2652: dsp_pm_read_accu24(numreg, &value);
2653: } else {
1.1.1.6 root 2654: value = dsp_core.registers[numreg];
1.1.1.4 root 2655: }
2656:
1.1.1.6 root 2657: dsp_core.instr_cycle += 4;
1.1.1.11! root 2658:
1.1.1.4 root 2659: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2660: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2661: newpc = newaddr;
1.1.1.6 root 2662: dsp_core.pc = newpc;
1.1 root 2663: cur_inst_len = 0;
1.1.1.4 root 2664: return;
1.1.1.11! root 2665: }
1.1.1.4 root 2666: ++cur_inst_len;
1.1 root 2667: }
2668:
1.1.1.4 root 2669: static void dsp_jset_aa(void)
1.1 root 2670: {
1.1.1.4 root 2671: Uint32 memspace, addr, value, numbit, newpc, newaddr;
1.1.1.11! root 2672:
1.1.1.4 root 2673: memspace = (cur_inst>>6) & 1;
2674: addr = (cur_inst>>8) & BITMASK(6);
2675: numbit = cur_inst & BITMASK(5);
2676: value = read_memory(memspace, addr);
1.1.1.6 root 2677: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2678:
1.1.1.6 root 2679: dsp_core.instr_cycle += 4;
1.1.1.11! root 2680:
1.1.1.4 root 2681: if (value & (1<<numbit)) {
2682: newpc = newaddr;
1.1.1.6 root 2683: dsp_core.pc = newpc;
1.1.1.4 root 2684: cur_inst_len=0;
2685: return;
1.1.1.11! root 2686: }
1.1.1.4 root 2687: ++cur_inst_len;
2688: }
2689:
2690: static void dsp_jset_ea(void)
2691: {
2692: Uint32 memspace, addr, value, numbit, newpc, newaddr;
1.1.1.11! root 2693:
1.1 root 2694: memspace = (cur_inst>>6) & 1;
2695: value = (cur_inst>>8) & BITMASK(6);
2696: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2697: dsp_calc_ea(value, &addr);
2698: value = read_memory(memspace, addr);
1.1.1.6 root 2699: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2700:
1.1.1.6 root 2701: dsp_core.instr_cycle += 4;
1.1.1.7 root 2702:
1.1.1.4 root 2703: if (value & (1<<numbit)) {
2704: newpc = newaddr;
1.1.1.6 root 2705: dsp_core.pc = newpc;
1.1.1.4 root 2706: cur_inst_len=0;
2707: return;
1.1.1.11! root 2708: }
1.1.1.4 root 2709: ++cur_inst_len;
2710: }
1.1 root 2711:
1.1.1.4 root 2712: static void dsp_jset_pp(void)
2713: {
2714: Uint32 memspace, addr, value, numbit, newpc, newaddr;
1.1.1.11! root 2715:
1.1.1.4 root 2716: memspace = (cur_inst>>6) & 1;
2717: value = (cur_inst>>8) & BITMASK(6);
2718: numbit = cur_inst & BITMASK(5);
2719: addr = 0xffc0 + value;
2720: value = read_memory(memspace, addr);
1.1.1.6 root 2721: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2722:
1.1.1.6 root 2723: dsp_core.instr_cycle += 4;
1.1.1.11! root 2724:
1.1.1.4 root 2725: if (value & (1<<numbit)) {
2726: newpc = newaddr;
1.1.1.6 root 2727: dsp_core.pc = newpc;
1.1.1.4 root 2728: cur_inst_len=0;
2729: return;
1.1.1.11! root 2730: }
1.1.1.4 root 2731: ++cur_inst_len;
2732: }
2733:
2734: static void dsp_jset_reg(void)
2735: {
2736: Uint32 value, numreg, numbit, newpc, newaddr;
1.1.1.11! root 2737:
1.1.1.4 root 2738: numreg = (cur_inst>>8) & BITMASK(6);
2739: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2740: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11! root 2741:
1.1.1.4 root 2742: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2743: dsp_pm_read_accu24(numreg, &value);
2744: } else {
1.1.1.6 root 2745: value = dsp_core.registers[numreg];
1.1.1.4 root 2746: }
2747:
1.1.1.6 root 2748: dsp_core.instr_cycle += 4;
1.1.1.11! root 2749:
1.1.1.4 root 2750: if (value & (1<<numbit)) {
2751: newpc = newaddr;
1.1.1.6 root 2752: dsp_core.pc = newpc;
1.1.1.4 root 2753: cur_inst_len=0;
2754: return;
1.1.1.11! root 2755: }
1.1.1.4 root 2756: ++cur_inst_len;
2757: }
2758:
2759: static void dsp_jsr_imm(void)
2760: {
2761: Uint32 newpc;
2762:
2763: newpc = cur_inst & BITMASK(12);
2764:
1.1.1.6 root 2765: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2766: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2767: }
2768: else {
1.1.1.6 root 2769: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1.1.1.4 root 2770: }
2771:
1.1.1.6 root 2772: dsp_core.pc = newpc;
1.1.1.4 root 2773: cur_inst_len = 0;
2774:
1.1.1.6 root 2775: dsp_core.instr_cycle += 2;
1.1.1.4 root 2776: }
2777:
2778: static void dsp_jsr_ea(void)
2779: {
2780: Uint32 newpc;
2781:
2782: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&newpc);
2783:
1.1.1.6 root 2784: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2785: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2786: }
2787: else {
1.1.1.6 root 2788: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1.1.1.4 root 2789: }
2790:
1.1.1.6 root 2791: dsp_core.pc = newpc;
1.1.1.4 root 2792: cur_inst_len = 0;
2793:
1.1.1.6 root 2794: dsp_core.instr_cycle += 2;
1.1.1.4 root 2795: }
2796:
2797: static void dsp_jsset_aa(void)
2798: {
2799: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11! root 2800:
1.1.1.4 root 2801: memspace = (cur_inst>>6) & 1;
2802: addr = (cur_inst>>8) & BITMASK(6);
2803: numbit = cur_inst & BITMASK(5);
2804: value = read_memory(memspace, addr);
1.1.1.6 root 2805: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11! root 2806:
1.1.1.6 root 2807: dsp_core.instr_cycle += 4;
1.1.1.4 root 2808:
2809: if (value & (1<<numbit)) {
1.1.1.6 root 2810: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2811: newpc = newaddr;
1.1.1.6 root 2812: dsp_core.pc = newpc;
1.1.1.4 root 2813: cur_inst_len = 0;
2814: return;
1.1.1.11! root 2815: }
1.1.1.4 root 2816: ++cur_inst_len;
2817: }
2818:
2819: static void dsp_jsset_ea(void)
2820: {
2821: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11! root 2822:
1.1.1.4 root 2823: memspace = (cur_inst>>6) & 1;
2824: value = (cur_inst>>8) & BITMASK(6);
2825: numbit = cur_inst & BITMASK(5);
2826: dsp_calc_ea(value, &addr);
2827: value = read_memory(memspace, addr);
1.1.1.6 root 2828: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11! root 2829:
1.1.1.6 root 2830: dsp_core.instr_cycle += 4;
1.1 root 2831:
2832: if (value & (1<<numbit)) {
1.1.1.6 root 2833: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2834: newpc = newaddr;
1.1.1.6 root 2835: dsp_core.pc = newpc;
1.1.1.4 root 2836: cur_inst_len = 0;
2837: return;
1.1.1.11! root 2838: }
1.1.1.4 root 2839: ++cur_inst_len;
1.1 root 2840: }
2841:
1.1.1.4 root 2842: static void dsp_jsset_pp(void)
1.1 root 2843: {
1.1.1.4 root 2844: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11! root 2845:
1.1.1.4 root 2846: memspace = (cur_inst>>6) & 1;
2847: value = (cur_inst>>8) & BITMASK(6);
2848: numbit = cur_inst & BITMASK(5);
2849: addr = 0xffc0 + value;
2850: value = read_memory(memspace, addr);
1.1.1.6 root 2851: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2852:
1.1.1.6 root 2853: dsp_core.instr_cycle += 4;
1.1 root 2854:
1.1.1.4 root 2855: if (value & (1<<numbit)) {
1.1.1.6 root 2856: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2857: newpc = newaddr;
1.1.1.6 root 2858: dsp_core.pc = newpc;
1.1.1.4 root 2859: cur_inst_len = 0;
2860: return;
1.1.1.11! root 2861: }
1.1.1.4 root 2862: ++cur_inst_len;
1.1 root 2863: }
2864:
1.1.1.4 root 2865: static void dsp_jsset_reg(void)
1.1 root 2866: {
1.1.1.4 root 2867: Uint32 value, numreg, newpc, numbit, newaddr;
1.1.1.11! root 2868:
1.1.1.4 root 2869: numreg = (cur_inst>>8) & BITMASK(6);
1.1 root 2870: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2871: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11! root 2872:
1.1.1.4 root 2873: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2874: dsp_pm_read_accu24(numreg, &value);
2875: } else {
1.1.1.6 root 2876: value = dsp_core.registers[numreg];
1.1.1.4 root 2877: }
1.1 root 2878:
1.1.1.6 root 2879: dsp_core.instr_cycle += 4;
1.1 root 2880:
2881: if (value & (1<<numbit)) {
1.1.1.6 root 2882: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2883: newpc = newaddr;
1.1.1.6 root 2884: dsp_core.pc = newpc;
1.1 root 2885: cur_inst_len = 0;
1.1.1.4 root 2886: return;
1.1.1.11! root 2887: }
1.1.1.4 root 2888: ++cur_inst_len;
1.1 root 2889: }
2890:
2891: static void dsp_lua(void)
2892: {
1.1.1.2 root 2893: Uint32 value, srcreg, dstreg, srcsave, srcnew;
2894:
1.1 root 2895: srcreg = (cur_inst>>8) & BITMASK(3);
1.1.1.2 root 2896:
1.1.1.6 root 2897: srcsave = dsp_core.registers[DSP_REG_R0+srcreg];
1.1.1.2 root 2898: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &value);
1.1.1.6 root 2899: srcnew = dsp_core.registers[DSP_REG_R0+srcreg];
2900: dsp_core.registers[DSP_REG_R0+srcreg] = srcsave;
1.1.1.2 root 2901:
1.1.1.11! root 2902: if (cur_inst & (1<<3))
! 2903: dstreg = DSP_REG_N0 + (cur_inst & BITMASK(3));
! 2904: else
! 2905: dstreg = DSP_REG_R0 + (cur_inst & BITMASK(3));
1.1 root 2906:
1.1.1.11! root 2907: dsp_core.agu_move_indirect_instr = 1;
! 2908: dsp_write_reg(dstreg, srcnew);
1.1.1.6 root 2909: dsp_core.instr_cycle += 2;
1.1 root 2910: }
2911:
1.1.1.3 root 2912: static void dsp_movec_reg(void)
1.1 root 2913: {
1.1.1.4 root 2914: Uint32 numreg1, numreg2, value, dummy;
1.1 root 2915:
2916: /* S1,D2 */
2917: /* S2,D1 */
2918:
2919: numreg2 = (cur_inst>>8) & BITMASK(6);
1.1.1.4 root 2920: numreg1 = cur_inst & BITMASK(6);
1.1 root 2921:
1.1.1.11! root 2922: dsp_core.agu_move_indirect_instr = 1;
! 2923:
1.1 root 2924: if (cur_inst & (1<<15)) {
2925: /* Write D1 */
2926:
2927: if ((numreg2 == DSP_REG_A) || (numreg2 == DSP_REG_B)) {
1.1.1.11! root 2928: dsp_pm_read_accu24(numreg2, &value);
1.1 root 2929: } else {
1.1.1.6 root 2930: value = dsp_core.registers[numreg2];
1.1 root 2931: }
1.1.1.4 root 2932: dsp_write_reg(numreg1, value);
1.1 root 2933: } else {
2934: /* Read S1 */
1.1.1.4 root 2935: if (numreg1 == DSP_REG_SSH) {
2936: dsp_stack_pop(&value, &dummy);
1.1.1.11! root 2937: }
1.1.1.4 root 2938: else {
1.1.1.6 root 2939: value = dsp_core.registers[numreg1];
1.1.1.4 root 2940: }
1.1 root 2941:
1.1.1.11! root 2942: dsp_write_reg(numreg2, value);
1.1 root 2943: }
2944: }
2945:
1.1.1.3 root 2946: static void dsp_movec_aa(void)
1.1 root 2947: {
1.1.1.4 root 2948: Uint32 numreg, addr, memspace, value, dummy;
1.1 root 2949:
2950: /* x:aa,D1 */
2951: /* S1,x:aa */
2952: /* y:aa,D1 */
2953: /* S1,y:aa */
2954:
1.1.1.4 root 2955: numreg = cur_inst & BITMASK(6);
1.1 root 2956: addr = (cur_inst>>8) & BITMASK(6);
2957: memspace = (cur_inst>>6) & 1;
2958:
2959: if (cur_inst & (1<<15)) {
2960: /* Write D1 */
1.1.1.4 root 2961: value = read_memory(memspace, addr);
1.1.1.11! root 2962: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 2963: dsp_write_reg(numreg, value);
1.1 root 2964: } else {
2965: /* Read S1 */
1.1.1.4 root 2966: if (numreg == DSP_REG_SSH) {
2967: dsp_stack_pop(&value, &dummy);
1.1.1.11! root 2968: }
1.1.1.4 root 2969: else {
1.1.1.6 root 2970: value = dsp_core.registers[numreg];
1.1.1.4 root 2971: }
2972: write_memory(memspace, addr, value);
1.1 root 2973: }
2974: }
2975:
1.1.1.3 root 2976: static void dsp_movec_imm(void)
1.1 root 2977: {
1.1.1.4 root 2978: Uint32 numreg, value;
1.1 root 2979:
2980: /* #xx,D1 */
1.1.1.4 root 2981: numreg = cur_inst & BITMASK(6);
2982: value = (cur_inst>>8) & BITMASK(8);
1.1.1.11! root 2983: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 2984: dsp_write_reg(numreg, value);
1.1 root 2985: }
2986:
1.1.1.3 root 2987: static void dsp_movec_ea(void)
1.1 root 2988: {
1.1.1.4 root 2989: Uint32 numreg, addr, memspace, ea_mode, value, dummy;
1.1 root 2990: int retour;
2991:
2992: /* x:ea,D1 */
2993: /* S1,x:ea */
2994: /* y:ea,D1 */
2995: /* S1,y:ea */
2996: /* #xxxx,D1 */
2997:
1.1.1.4 root 2998: numreg = cur_inst & BITMASK(6);
1.1 root 2999: ea_mode = (cur_inst>>8) & BITMASK(6);
3000: memspace = (cur_inst>>6) & 1;
3001:
3002: if (cur_inst & (1<<15)) {
3003: /* Write D1 */
3004: retour = dsp_calc_ea(ea_mode, &addr);
3005: if (retour) {
1.1.1.4 root 3006: value = addr;
1.1 root 3007: } else {
1.1.1.4 root 3008: value = read_memory(memspace, addr);
1.1 root 3009: }
1.1.1.11! root 3010: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3011: dsp_write_reg(numreg, value);
1.1 root 3012: } else {
3013: /* Read S1 */
1.1.1.4 root 3014: dsp_calc_ea(ea_mode, &addr);
3015: if (numreg == DSP_REG_SSH) {
3016: dsp_stack_pop(&value, &dummy);
1.1.1.11! root 3017: }
1.1.1.4 root 3018: else {
1.1.1.6 root 3019: value = dsp_core.registers[numreg];
1.1.1.4 root 3020: }
3021: write_memory(memspace, addr, value);
1.1 root 3022: }
3023: }
3024:
1.1.1.4 root 3025: static void dsp_movem_aa(void)
1.1 root 3026: {
1.1.1.4 root 3027: Uint32 numreg, addr, value, dummy;
1.1 root 3028:
3029: numreg = cur_inst & BITMASK(6);
1.1.1.4 root 3030: addr = (cur_inst>>8) & BITMASK(6);
1.1 root 3031:
1.1.1.4 root 3032: if (cur_inst & (1<<15)) {
3033: /* Write D */
3034: value = read_memory_p(addr);
1.1.1.11! root 3035: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3036: dsp_write_reg(numreg, value);
1.1 root 3037: } else {
1.1.1.4 root 3038: /* Read S */
3039: if (numreg == DSP_REG_SSH) {
3040: dsp_stack_pop(&value, &dummy);
1.1.1.11! root 3041: }
1.1.1.4 root 3042: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11! root 3043: dsp_pm_read_accu24(numreg, &value);
! 3044: }
1.1.1.4 root 3045: else {
1.1.1.6 root 3046: value = dsp_core.registers[numreg];
1.1.1.4 root 3047: }
3048: write_memory(DSP_SPACE_P, addr, value);
3049: }
1.1 root 3050:
1.1.1.6 root 3051: dsp_core.instr_cycle += 4;
1.1.1.4 root 3052: }
3053:
3054: static void dsp_movem_ea(void)
3055: {
3056: Uint32 numreg, addr, ea_mode, value, dummy;
3057:
3058: numreg = cur_inst & BITMASK(6);
3059: ea_mode = (cur_inst>>8) & BITMASK(6);
3060: dsp_calc_ea(ea_mode, &addr);
1.1 root 3061:
3062: if (cur_inst & (1<<15)) {
3063: /* Write D */
1.1.1.4 root 3064: value = read_memory_p(addr);
1.1.1.11! root 3065: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3066: dsp_write_reg(numreg, value);
1.1 root 3067: } else {
3068: /* Read S */
1.1.1.4 root 3069: if (numreg == DSP_REG_SSH) {
3070: dsp_stack_pop(&value, &dummy);
1.1.1.11! root 3071: }
1.1.1.4 root 3072: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11! root 3073: dsp_pm_read_accu24(numreg, &value);
! 3074: }
1.1.1.4 root 3075: else {
1.1.1.6 root 3076: value = dsp_core.registers[numreg];
1.1 root 3077: }
3078: write_memory(DSP_SPACE_P, addr, value);
3079: }
3080:
1.1.1.6 root 3081: dsp_core.instr_cycle += 4;
1.1 root 3082: }
3083:
3084: static void dsp_movep_0(void)
3085: {
3086: /* S,x:pp */
3087: /* x:pp,D */
3088: /* S,y:pp */
3089: /* y:pp,D */
1.1.1.11! root 3090:
1.1.1.4 root 3091: Uint32 addr, memspace, numreg, value, dummy;
1.1 root 3092:
3093: addr = 0xffc0 + (cur_inst & BITMASK(6));
3094: memspace = (cur_inst>>16) & 1;
3095: numreg = (cur_inst>>8) & BITMASK(6);
3096:
3097: if (cur_inst & (1<<15)) {
3098: /* Write pp */
3099: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11! root 3100: dsp_pm_read_accu24(numreg, &value);
1.1.1.4 root 3101: }
3102: else if (numreg == DSP_REG_SSH) {
3103: dsp_stack_pop(&value, &dummy);
3104: }
3105: else {
1.1.1.6 root 3106: value = dsp_core.registers[numreg];
1.1 root 3107: }
3108: write_memory(memspace, addr, value);
3109: } else {
3110: /* Read pp */
3111: value = read_memory(memspace, addr);
1.1.1.11! root 3112: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3113: dsp_write_reg(numreg, value);
1.1 root 3114: }
1.1.1.4 root 3115:
1.1.1.6 root 3116: dsp_core.instr_cycle += 2;
1.1 root 3117: }
3118:
3119: static void dsp_movep_1(void)
3120: {
3121: /* p:ea,x:pp */
3122: /* x:pp,p:ea */
3123: /* p:ea,y:pp */
3124: /* y:pp,p:ea */
3125:
1.1.1.2 root 3126: Uint32 xyaddr, memspace, paddr;
1.1 root 3127:
3128: xyaddr = 0xffc0 + (cur_inst & BITMASK(6));
3129: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &paddr);
3130: memspace = (cur_inst>>16) & 1;
3131:
3132: if (cur_inst & (1<<15)) {
3133: /* Write pp */
1.1.1.4 root 3134: write_memory(memspace, xyaddr, read_memory_p(paddr));
1.1 root 3135: } else {
3136: /* Read pp */
3137: write_memory(DSP_SPACE_P, paddr, read_memory(memspace, xyaddr));
3138: }
1.1.1.4 root 3139:
1.1.1.7 root 3140: /* Movep is 4 cycles, but according to the motorola doc, */
3141: /* movep from p memory to x or y peripheral memory takes */
3142: /* 2 more cycles, so +4 cycles at total */
3143: dsp_core.instr_cycle += 4;
1.1 root 3144: }
3145:
1.1.1.4 root 3146: static void dsp_movep_23(void)
1.1 root 3147: {
3148: /* x:ea,x:pp */
3149: /* y:ea,x:pp */
3150: /* #xxxxxx,x:pp */
3151: /* x:pp,x:ea */
3152: /* x:pp,y:pp */
3153: /* x:ea,y:pp */
3154: /* y:ea,y:pp */
3155: /* #xxxxxx,y:pp */
3156: /* y:pp,y:ea */
3157: /* y:pp,x:ea */
3158:
1.1.1.2 root 3159: Uint32 addr, peraddr, easpace, perspace, ea_mode;
1.1 root 3160: int retour;
3161:
3162: peraddr = 0xffc0 + (cur_inst & BITMASK(6));
3163: perspace = (cur_inst>>16) & 1;
1.1.1.11! root 3164:
1.1 root 3165: ea_mode = (cur_inst>>8) & BITMASK(6);
3166: easpace = (cur_inst>>6) & 1;
3167: retour = dsp_calc_ea(ea_mode, &addr);
3168:
3169: if (cur_inst & (1<<15)) {
3170: /* Write pp */
1.1.1.11! root 3171:
1.1 root 3172: if (retour) {
3173: write_memory(perspace, peraddr, addr);
3174: } else {
3175: write_memory(perspace, peraddr, read_memory(easpace, addr));
3176: }
3177: } else {
3178: /* Read pp */
3179: write_memory(easpace, addr, read_memory(perspace, peraddr));
3180: }
1.1.1.4 root 3181:
1.1.1.6 root 3182: dsp_core.instr_cycle += 2;
1.1 root 3183: }
3184:
3185: static void dsp_norm(void)
3186: {
1.1.1.2 root 3187: Uint32 cursr,cur_e, cur_euz, dest[3], numreg, rreg;
3188: Uint16 newsr;
1.1 root 3189:
1.1.1.6 root 3190: cursr = dsp_core.registers[DSP_REG_SR];
1.1 root 3191: cur_e = (cursr>>DSP_SR_E) & 1; /* E */
3192: cur_euz = ~cur_e; /* (not E) and U and (not Z) */
3193: cur_euz &= (cursr>>DSP_SR_U) & 1;
3194: cur_euz &= ~((cursr>>DSP_SR_Z) & 1);
3195: cur_euz &= 1;
3196:
3197: numreg = (cur_inst>>3) & 1;
1.1.1.6 root 3198: dest[0] = dsp_core.registers[DSP_REG_A2+numreg];
3199: dest[1] = dsp_core.registers[DSP_REG_A1+numreg];
3200: dest[2] = dsp_core.registers[DSP_REG_A0+numreg];
1.1 root 3201: rreg = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3202:
3203: if (cur_euz) {
3204: newsr = dsp_asl56(dest);
1.1.1.6 root 3205: --dsp_core.registers[rreg];
3206: dsp_core.registers[rreg] &= BITMASK(16);
1.1 root 3207: } else if (cur_e) {
3208: newsr = dsp_asr56(dest);
1.1.1.6 root 3209: ++dsp_core.registers[rreg];
3210: dsp_core.registers[rreg] &= BITMASK(16);
1.1 root 3211: } else {
3212: newsr = 0;
3213: }
3214:
1.1.1.6 root 3215: dsp_core.registers[DSP_REG_A2+numreg] = dest[0];
3216: dsp_core.registers[DSP_REG_A1+numreg] = dest[1];
3217: dsp_core.registers[DSP_REG_A0+numreg] = dest[2];
1.1.1.2 root 3218:
1.1.1.6 root 3219: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 3220:
1.1.1.6 root 3221: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
3222: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 3223: }
3224:
3225: static void dsp_ori(void)
3226: {
1.1.1.2 root 3227: Uint32 regnum, value;
1.1 root 3228:
3229: value = (cur_inst >> 8) & BITMASK(8);
3230: regnum = cur_inst & BITMASK(2);
3231: switch(regnum) {
3232: case 0:
3233: /* mr */
1.1.1.6 root 3234: dsp_core.registers[DSP_REG_SR] |= value<<8;
1.1 root 3235: break;
3236: case 1:
3237: /* ccr */
1.1.1.6 root 3238: dsp_core.registers[DSP_REG_SR] |= value;
1.1 root 3239: break;
3240: case 2:
3241: /* omr */
1.1.1.6 root 3242: dsp_core.registers[DSP_REG_OMR] |= value;
1.1 root 3243: break;
3244: }
3245: }
3246:
1.1.1.3 root 3247: /*
3248: REP instruction parameter encoding
3249:
3250: xxxxxxxx 00xxxxxx 0xxxxxxx aa
3251: xxxxxxxx 01xxxxxx 0xxxxxxx ea
3252: xxxxxxxx YYxxxxxx 1xxxxxxx imm
3253: xxxxxxxx 11xxxxxx 0xxxxxxx reg
3254: */
3255:
3256: static void dsp_rep_aa(void)
1.1 root 3257: {
3258: /* x:aa */
3259: /* y:aa */
1.1.1.6 root 3260: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3261: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3262: dsp_core.loop_rep = 1; /* We are now running rep */
1.1 root 3263:
1.1.1.6 root 3264: dsp_core.registers[DSP_REG_LC]=read_memory((cur_inst>>6) & 1,(cur_inst>>8) & BITMASK(6));
1.1.1.4 root 3265:
1.1.1.6 root 3266: dsp_core.instr_cycle += 2;
1.1 root 3267: }
3268:
1.1.1.3 root 3269: static void dsp_rep_imm(void)
1.1 root 3270: {
3271: /* #xxx */
3272:
1.1.1.6 root 3273: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3274: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3275: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3276:
1.1.1.6 root 3277: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
1.1.1.3 root 3278: + ((cur_inst & BITMASK(4))<<8);
1.1.1.4 root 3279:
1.1.1.6 root 3280: dsp_core.instr_cycle += 2;
1.1 root 3281: }
3282:
1.1.1.3 root 3283: static void dsp_rep_ea(void)
1.1 root 3284: {
1.1.1.2 root 3285: Uint32 value;
1.1 root 3286:
3287: /* x:ea */
3288: /* y:ea */
3289:
1.1.1.6 root 3290: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3291: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3292: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3293:
1.1 root 3294: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&value);
1.1.1.6 root 3295: dsp_core.registers[DSP_REG_LC]= read_memory((cur_inst>>6) & 1, value);
1.1.1.4 root 3296:
1.1.1.6 root 3297: dsp_core.instr_cycle += 2;
1.1 root 3298: }
3299:
1.1.1.3 root 3300: static void dsp_rep_reg(void)
1.1 root 3301: {
1.1.1.2 root 3302: Uint32 numreg;
1.1 root 3303:
3304: /* R */
3305:
1.1.1.6 root 3306: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3307: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3308: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3309:
1.1 root 3310: numreg = (cur_inst>>8) & BITMASK(6);
3311: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11! root 3312: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
1.1 root 3313: } else {
1.1.1.6 root 3314: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
1.1 root 3315: }
1.1.1.6 root 3316: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.4 root 3317:
1.1.1.6 root 3318: dsp_core.instr_cycle += 2;
1.1 root 3319: }
3320:
3321: static void dsp_reset(void)
3322: {
3323: /* Reset external peripherals */
1.1.1.6 root 3324: dsp_core.instr_cycle += 2;
1.1 root 3325: }
3326:
3327: static void dsp_rti(void)
3328: {
1.1.1.2 root 3329: Uint32 newpc = 0, newsr = 0;
1.1 root 3330:
3331: dsp_stack_pop(&newpc, &newsr);
1.1.1.6 root 3332: dsp_core.pc = newpc;
3333: dsp_core.registers[DSP_REG_SR] = newsr;
1.1 root 3334: cur_inst_len = 0;
1.1.1.4 root 3335:
1.1.1.6 root 3336: dsp_core.instr_cycle += 2;
1.1 root 3337: }
3338:
3339: static void dsp_rts(void)
3340: {
1.1.1.2 root 3341: Uint32 newpc = 0, newsr;
1.1 root 3342:
3343: dsp_stack_pop(&newpc, &newsr);
1.1.1.6 root 3344: dsp_core.pc = newpc;
1.1 root 3345: cur_inst_len = 0;
1.1.1.4 root 3346:
1.1.1.6 root 3347: dsp_core.instr_cycle += 2;
1.1 root 3348: }
3349:
3350: static void dsp_stop(void)
3351: {
1.1.1.6 root 3352: LOG_TRACE(TRACE_DSP_STATE, "Dsp: STOP instruction\n");
1.1 root 3353: }
3354:
3355: static void dsp_swi(void)
3356: {
3357: /* Raise interrupt p:0x0006 */
1.1.1.6 root 3358: dsp_core.instr_cycle += 6;
1.1 root 3359: }
3360:
3361: static void dsp_tcc(void)
3362: {
1.1.1.6 root 3363: Uint32 cc_code, regsrc1, regdest1;
1.1.1.2 root 3364: Uint32 regsrc2, regdest2;
1.1.1.6 root 3365: Uint32 val0, val1, val2;
1.1.1.11! root 3366:
1.1 root 3367: cc_code = (cur_inst>>12) & BITMASK(4);
3368:
3369: if (dsp_calc_cc(cc_code)) {
3370: regsrc1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][0];
1.1.1.2 root 3371: regdest1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][1];
1.1 root 3372:
3373: /* Read S1 */
1.1.1.7 root 3374: if (regsrc1 == DSP_REG_A) {
3375: val0 = dsp_core.registers[DSP_REG_A0];
3376: val1 = dsp_core.registers[DSP_REG_A1];
3377: val2 = dsp_core.registers[DSP_REG_A2];
3378: }
3379: else if (regsrc1 == DSP_REG_B) {
3380: val0 = dsp_core.registers[DSP_REG_B0];
3381: val1 = dsp_core.registers[DSP_REG_B1];
3382: val2 = dsp_core.registers[DSP_REG_B2];
3383: }
3384: else {
1.1.1.6 root 3385: val0 = 0;
3386: val1 = dsp_core.registers[regsrc1];
1.1.1.7 root 3387: val2 = val1 & (1<<23) ? 0xff : 0x0;
1.1 root 3388: }
1.1.1.11! root 3389:
1.1 root 3390: /* Write D1 */
1.1.1.7 root 3391: if (regdest1 == DSP_REG_A) {
3392: dsp_core.registers[DSP_REG_A2] = val2;
3393: dsp_core.registers[DSP_REG_A1] = val1;
3394: dsp_core.registers[DSP_REG_A0] = val0;
3395: }
3396: else {
3397: dsp_core.registers[DSP_REG_B2] = val2;
3398: dsp_core.registers[DSP_REG_B1] = val1;
3399: dsp_core.registers[DSP_REG_B0] = val0;
3400: }
1.1 root 3401:
3402: /* S2,D2 transfer */
3403: if (cur_inst & (1<<16)) {
1.1.1.2 root 3404: regsrc2 = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3405: regdest2 = DSP_REG_R0+(cur_inst & BITMASK(3));
1.1 root 3406:
1.1.1.11! root 3407: dsp_core.agu_move_indirect_instr = 1;
! 3408: dsp_write_reg(regdest2, dsp_core.registers[regsrc2]);
1.1 root 3409: }
3410: }
3411: }
3412:
3413: static void dsp_wait(void)
3414: {
1.1.1.6 root 3415: LOG_TRACE(TRACE_DSP_STATE, "Dsp: WAIT instruction\n");
1.1 root 3416: }
3417:
1.1.1.2 root 3418: static int dsp_pm_read_accu24(int numreg, Uint32 *dest)
1.1 root 3419: {
1.1.1.4 root 3420: Uint32 scaling, value, reg;
1.1.1.7 root 3421: int got_limited = 0;
1.1 root 3422:
3423: /* Read an accumulator, stores it limited */
3424:
1.1.1.6 root 3425: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
1.1.1.4 root 3426: reg = numreg & 1;
1.1 root 3427:
1.1.1.6 root 3428: value = (dsp_core.registers[DSP_REG_A2+reg]) << 24;
3429: value += dsp_core.registers[DSP_REG_A1+reg];
1.1 root 3430:
3431: switch(scaling) {
3432: case 0:
1.1.1.4 root 3433: /* No scaling */
3434: break;
3435: case 1:
3436: /* scaling down */
3437: value >>= 1;
1.1 root 3438: break;
3439: case 2:
1.1.1.4 root 3440: /* scaling up */
3441: value <<= 1;
1.1.1.6 root 3442: value |= (dsp_core.registers[DSP_REG_A0+reg]>>23) & 1;
1.1 root 3443: break;
1.1.1.4 root 3444: /* indeterminate */
1.1.1.11! root 3445: case 3:
1.1.1.4 root 3446: break;
3447: }
3448:
3449: /* limiting ? */
3450: value &= BITMASK(24);
3451:
1.1.1.6 root 3452: if (dsp_core.registers[DSP_REG_A2+reg] == 0) {
1.1.1.4 root 3453: if (value <= 0x007fffff) {
3454: /* No limiting */
3455: *dest=value;
3456: return 0;
1.1.1.11! root 3457: }
1.1.1.4 root 3458: }
3459:
1.1.1.6 root 3460: if (dsp_core.registers[DSP_REG_A2+reg] == 0xff) {
1.1.1.4 root 3461: if (value >= 0x00800000) {
3462: /* No limiting */
3463: *dest=value;
3464: return 0;
1.1.1.11! root 3465: }
1.1 root 3466: }
3467:
1.1.1.6 root 3468: if (dsp_core.registers[DSP_REG_A2+reg] & (1<<7)) {
1.1 root 3469: /* Limited to maximum negative value */
3470: *dest=0x00800000;
1.1.1.6 root 3471: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
1.1.1.2 root 3472: got_limited=1;
1.1 root 3473: } else {
3474: /* Limited to maximal positive value */
3475: *dest=0x007fffff;
1.1.1.6 root 3476: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
1.1.1.2 root 3477: got_limited=1;
1.1.1.11! root 3478: }
1.1.1.2 root 3479:
3480: return got_limited;
1.1 root 3481: }
3482:
3483: static void dsp_pm_0(void)
3484: {
1.1.1.6 root 3485: Uint32 memspace, numreg, addr, save_accu, save_xy0;
1.1 root 3486: /*
3487: 0000 100d 00mm mrrr S,x:ea x0,D
3488: 0000 100d 10mm mrrr S,y:ea y0,D
3489: */
3490: memspace = (cur_inst>>15) & 1;
3491: numreg = (cur_inst>>16) & 1;
1.1.1.6 root 3492: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &addr);
3493:
1.1.1.11! root 3494: /* Save A or B */
1.1.1.6 root 3495: dsp_pm_read_accu24(numreg, &save_accu);
1.1 root 3496:
1.1.1.6 root 3497: /* Save X0 or Y0 */
3498: save_xy0 = dsp_core.registers[DSP_REG_X0+(memspace<<1)];
3499:
3500: /* Execute parallel instruction */
3501: opcodes_alu[cur_inst & BITMASK(8)]();
3502:
1.1.1.11! root 3503: /* Move [A|B] to [x|y]:ea */
1.1.1.6 root 3504: write_memory(memspace, addr, save_accu);
3505:
3506: /* Move [x|y]0 to [A|B] */
3507: dsp_core.registers[DSP_REG_A0+numreg] = 0;
3508: dsp_core.registers[DSP_REG_A1+numreg] = save_xy0;
1.1.1.7 root 3509: dsp_core.registers[DSP_REG_A2+numreg] = save_xy0 & (1<<23) ? 0xff : 0x0;
1.1 root 3510: }
3511:
3512: static void dsp_pm_1(void)
3513: {
1.1.1.6 root 3514: Uint32 memspace, numreg1, numreg2, value, xy_addr, retour, save_1, save_2;
1.1 root 3515: /*
1.1.1.11! root 3516: 0001 ffdf w0mm mrrr x:ea,D1 S2,D2
1.1 root 3517: S1,x:ea S2,D2
3518: #xxxxxx,D1 S2,D2
1.1.1.11! root 3519: 0001 deff w1mm mrrr S1,D1 y:ea,D2
1.1 root 3520: S1,D1 S2,y:ea
3521: S1,D1 #xxxxxx,D2
3522: */
3523: value = (cur_inst>>8) & BITMASK(6);
1.1.1.11! root 3524: retour = dsp_calc_ea(value, &xy_addr);
1.1 root 3525: memspace = (cur_inst>>14) & 1;
1.1.1.6 root 3526: numreg1 = numreg2 = DSP_REG_NULL;
1.1 root 3527:
3528: if (memspace) {
3529: /* Y: */
3530: switch((cur_inst>>16) & BITMASK(2)) {
1.1.1.6 root 3531: case 0: numreg1 = DSP_REG_Y0; break;
3532: case 1: numreg1 = DSP_REG_Y1; break;
3533: case 2: numreg1 = DSP_REG_A; break;
3534: case 3: numreg1 = DSP_REG_B; break;
1.1 root 3535: }
3536: } else {
3537: /* X: */
3538: switch((cur_inst>>18) & BITMASK(2)) {
1.1.1.6 root 3539: case 0: numreg1 = DSP_REG_X0; break;
3540: case 1: numreg1 = DSP_REG_X1; break;
3541: case 2: numreg1 = DSP_REG_A; break;
3542: case 3: numreg1 = DSP_REG_B; break;
1.1 root 3543: }
3544: }
3545:
3546: if (cur_inst & (1<<15)) {
3547: /* Write D1 */
1.1.1.6 root 3548: if (retour)
3549: save_1 = xy_addr;
3550: else
3551: save_1 = read_memory(memspace, xy_addr);
1.1 root 3552: } else {
3553: /* Read S1 */
1.1.1.6 root 3554: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
3555: dsp_pm_read_accu24(numreg1, &save_1);
3556: else
3557: save_1 = dsp_core.registers[numreg1];
1.1 root 3558: }
1.1.1.11! root 3559:
1.1 root 3560: /* S2 */
3561: if (memspace) {
3562: /* Y: */
1.1.1.6 root 3563: numreg2 = DSP_REG_A + ((cur_inst>>19) & 1);
1.1 root 3564: } else {
3565: /* X: */
1.1.1.6 root 3566: numreg2 = DSP_REG_A + ((cur_inst>>17) & 1);
1.1.1.11! root 3567: }
1.1.1.6 root 3568: dsp_pm_read_accu24(numreg2, &save_2);
1.1.1.11! root 3569:
1.1.1.6 root 3570:
3571: /* Execute parallel instruction */
3572: opcodes_alu[cur_inst & BITMASK(8)]();
3573:
3574:
3575: /* Write parallel move values */
3576: if (cur_inst & (1<<15)) {
3577: /* Write D1 */
1.1.1.11! root 3578: dsp_write_reg(numreg1, save_1);
1.1.1.6 root 3579: } else {
3580: /* Read S1 */
3581: write_memory(memspace, xy_addr, save_1);
3582: }
3583:
3584: /* S2 -> D2 */
1.1 root 3585: if (memspace) {
3586: /* Y: */
1.1.1.6 root 3587: numreg2 = DSP_REG_X0 + ((cur_inst>>18) & 1);
1.1 root 3588: } else {
3589: /* X: */
1.1.1.6 root 3590: numreg2 = DSP_REG_Y0 + ((cur_inst>>16) & 1);
1.1.1.11! root 3591: }
1.1.1.6 root 3592: dsp_core.registers[numreg2] = save_2;
1.1 root 3593: }
3594:
3595: static void dsp_pm_2(void)
3596: {
1.1.1.2 root 3597: Uint32 dummy;
1.1 root 3598: /*
3599: 0010 0000 0000 0000 nop
3600: 0010 0000 010m mrrr R update
3601: 0010 00ee eeed dddd S,D
3602: 001d dddd iiii iiii #xx,D
3603: */
1.1.1.4 root 3604: if ((cur_inst & 0xffff00) == 0x200000) {
1.1.1.6 root 3605: /* Execute parallel instruction */
3606: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3607: return;
3608: }
3609:
1.1.1.4 root 3610: if ((cur_inst & 0xffe000) == 0x204000) {
1.1 root 3611: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &dummy);
1.1.1.6 root 3612: /* Execute parallel instruction */
3613: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3614: return;
3615: }
3616:
1.1.1.4 root 3617: if ((cur_inst & 0xfc0000) == 0x200000) {
1.1 root 3618: dsp_pm_2_2();
3619: return;
3620: }
3621:
3622: dsp_pm_3();
3623: }
3624:
3625: static void dsp_pm_2_2(void)
3626: {
3627: /*
3628: 0010 00ee eeed dddd S,D
3629: */
1.1.1.6 root 3630: Uint32 srcreg, dstreg, save_reg;
1.1.1.11! root 3631:
1.1 root 3632: srcreg = (cur_inst >> 13) & BITMASK(5);
3633: dstreg = (cur_inst >> 8) & BITMASK(5);
3634:
1.1.1.6 root 3635: if ((srcreg == DSP_REG_A) || (srcreg == DSP_REG_B))
3636: /* Accu to register: limited 24 bits */
3637: dsp_pm_read_accu24(srcreg, &save_reg);
3638: else
3639: save_reg = dsp_core.registers[srcreg];
3640:
3641: /* Execute parallel instruction */
3642: opcodes_alu[cur_inst & BITMASK(8)]();
3643:
3644: /* Write reg */
1.1.1.11! root 3645: dsp_core.agu_move_indirect_instr = 1;
! 3646: dsp_write_reg(dstreg, save_reg);
1.1 root 3647: }
3648:
3649: static void dsp_pm_3(void)
3650: {
1.1.1.6 root 3651: Uint32 dstreg, srcvalue;
1.1 root 3652: /*
3653: 001d dddd iiii iiii #xx,R
3654: */
1.1.1.6 root 3655:
3656: /* Execute parallel instruction */
3657: opcodes_alu[cur_inst & BITMASK(8)]();
3658:
3659: /* Write reg */
3660: dstreg = (cur_inst >> 16) & BITMASK(5);
1.1 root 3661: srcvalue = (cur_inst >> 8) & BITMASK(8);
3662:
1.1.1.6 root 3663: switch(dstreg) {
1.1 root 3664: case DSP_REG_X0:
3665: case DSP_REG_X1:
3666: case DSP_REG_Y0:
3667: case DSP_REG_Y1:
3668: case DSP_REG_A:
3669: case DSP_REG_B:
3670: srcvalue <<= 16;
3671: break;
3672: }
3673:
1.1.1.11! root 3674: dsp_core.agu_move_indirect_instr = 1;
! 3675: dsp_write_reg(dstreg, srcvalue);
1.1 root 3676: }
3677:
3678: static void dsp_pm_4(void)
3679: {
3680: /*
1.1.1.4 root 3681: 0100 l0ll w0aa aaaa l:aa,D
1.1 root 3682: S,l:aa
1.1.1.4 root 3683: 0100 l0ll w1mm mrrr l:ea,D
1.1 root 3684: S,l:ea
1.1.1.4 root 3685: 01dd 0ddd w0aa aaaa x:aa,D
1.1 root 3686: S,x:aa
1.1.1.4 root 3687: 01dd 0ddd w1mm mrrr x:ea,D
1.1 root 3688: S,x:ea
3689: #xxxxxx,D
1.1.1.4 root 3690: 01dd 1ddd w0aa aaaa y:aa,D
1.1 root 3691: S,y:aa
1.1.1.4 root 3692: 01dd 1ddd w1mm mrrr y:ea,D
1.1 root 3693: S,y:ea
3694: #xxxxxx,D
3695: */
1.1.1.4 root 3696: if ((cur_inst & 0xf40000)==0x400000) {
3697: dsp_pm_4x();
1.1 root 3698: return;
3699: }
3700:
3701: dsp_pm_5();
3702: }
3703:
1.1.1.4 root 3704: static void dsp_pm_4x(void)
1.1 root 3705: {
1.1.1.6 root 3706: Uint32 value, numreg, l_addr, save_lx, save_ly;
1.1 root 3707: /*
1.1.1.4 root 3708: 0100 l0ll w0aa aaaa l:aa,D
3709: S,l:aa
3710: 0100 l0ll w1mm mrrr l:ea,D
3711: S,l:ea
1.1 root 3712: */
1.1.1.4 root 3713: value = (cur_inst>>8) & BITMASK(6);
3714: if (cur_inst & (1<<14)) {
1.1.1.11! root 3715: dsp_calc_ea(value, &l_addr);
1.1.1.4 root 3716: } else {
3717: l_addr = value;
3718: }
3719:
1.1 root 3720: numreg = (cur_inst>>16) & BITMASK(2);
3721: numreg |= (cur_inst>>17) & (1<<2);
3722:
3723: if (cur_inst & (1<<15)) {
3724: /* Write D */
1.1.1.6 root 3725: save_lx = read_memory(DSP_SPACE_X,l_addr);
3726: save_ly = read_memory(DSP_SPACE_Y,l_addr);
3727: }
3728: else {
3729: /* Read S */
1.1.1.4 root 3730: switch(numreg) {
3731: case 0:
3732: /* A10 */
1.1.1.6 root 3733: save_lx = dsp_core.registers[DSP_REG_A1];
3734: save_ly = dsp_core.registers[DSP_REG_A0];
1.1.1.4 root 3735: break;
3736: case 1:
3737: /* B10 */
1.1.1.6 root 3738: save_lx = dsp_core.registers[DSP_REG_B1];
3739: save_ly = dsp_core.registers[DSP_REG_B0];
1.1.1.4 root 3740: break;
3741: case 2:
3742: /* X */
1.1.1.6 root 3743: save_lx = dsp_core.registers[DSP_REG_X1];
3744: save_ly = dsp_core.registers[DSP_REG_X0];
1.1.1.4 root 3745: break;
3746: case 3:
3747: /* Y */
1.1.1.6 root 3748: save_lx = dsp_core.registers[DSP_REG_Y1];
3749: save_ly = dsp_core.registers[DSP_REG_Y0];
1.1.1.4 root 3750: break;
3751: case 4:
3752: /* A */
1.1.1.6 root 3753: if (dsp_pm_read_accu24(DSP_REG_A, &save_lx)) {
3754: /* Was limited, set lower part */
3755: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3756: } else {
3757: /* Not limited */
3758: save_ly = dsp_core.registers[DSP_REG_A0];
3759: }
1.1.1.4 root 3760: break;
3761: case 5:
3762: /* B */
1.1.1.6 root 3763: if (dsp_pm_read_accu24(DSP_REG_B, &save_lx)) {
3764: /* Was limited, set lower part */
3765: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3766: } else {
3767: /* Not limited */
3768: save_ly = dsp_core.registers[DSP_REG_B0];
3769: }
1.1.1.4 root 3770: break;
3771: case 6:
3772: /* AB */
1.1.1.11! root 3773: dsp_pm_read_accu24(DSP_REG_A, &save_lx);
! 3774: dsp_pm_read_accu24(DSP_REG_B, &save_ly);
1.1.1.4 root 3775: break;
3776: case 7:
3777: /* BA */
1.1.1.11! root 3778: dsp_pm_read_accu24(DSP_REG_B, &save_lx);
! 3779: dsp_pm_read_accu24(DSP_REG_A, &save_ly);
1.1.1.4 root 3780: break;
1.1 root 3781: }
1.1.1.6 root 3782: }
1.1 root 3783:
1.1.1.6 root 3784: /* Execute parallel instruction */
3785: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3786:
1.1.1.6 root 3787:
3788: if (cur_inst & (1<<15)) {
3789: /* Write D */
1.1.1.4 root 3790: switch(numreg) {
1.1.1.6 root 3791: case 0: /* A10 */
3792: dsp_core.registers[DSP_REG_A1] = save_lx;
3793: dsp_core.registers[DSP_REG_A0] = save_ly;
1.1.1.4 root 3794: break;
1.1.1.6 root 3795: case 1: /* B10 */
3796: dsp_core.registers[DSP_REG_B1] = save_lx;
3797: dsp_core.registers[DSP_REG_B0] = save_ly;
1.1.1.4 root 3798: break;
1.1.1.6 root 3799: case 2: /* X */
3800: dsp_core.registers[DSP_REG_X1] = save_lx;
3801: dsp_core.registers[DSP_REG_X0] = save_ly;
1.1.1.4 root 3802: break;
1.1.1.6 root 3803: case 3: /* Y */
3804: dsp_core.registers[DSP_REG_Y1] = save_lx;
3805: dsp_core.registers[DSP_REG_Y0] = save_ly;
1.1.1.4 root 3806: break;
1.1.1.6 root 3807: case 4: /* A */
3808: dsp_core.registers[DSP_REG_A0] = save_ly;
3809: dsp_core.registers[DSP_REG_A1] = save_lx;
3810: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
1.1.1.4 root 3811: break;
1.1.1.6 root 3812: case 5: /* B */
3813: dsp_core.registers[DSP_REG_B0] = save_ly;
3814: dsp_core.registers[DSP_REG_B1] = save_lx;
3815: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
1.1.1.4 root 3816: break;
1.1.1.6 root 3817: case 6: /* AB */
3818: dsp_core.registers[DSP_REG_A0] = 0;
3819: dsp_core.registers[DSP_REG_A1] = save_lx;
3820: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
3821: dsp_core.registers[DSP_REG_B0] = 0;
3822: dsp_core.registers[DSP_REG_B1] = save_ly;
3823: dsp_core.registers[DSP_REG_B2] = save_ly & (1<<23) ? 0xff : 0;
1.1.1.4 root 3824: break;
1.1.1.6 root 3825: case 7: /* BA */
3826: dsp_core.registers[DSP_REG_B0] = 0;
3827: dsp_core.registers[DSP_REG_B1] = save_lx;
3828: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
3829: dsp_core.registers[DSP_REG_A0] = 0;
3830: dsp_core.registers[DSP_REG_A1] = save_ly;
3831: dsp_core.registers[DSP_REG_A2] = save_ly & (1<<23) ? 0xff : 0;
1.1.1.4 root 3832: break;
1.1 root 3833: }
1.1.1.6 root 3834: }
3835: else {
3836: /* Read S */
3837: write_memory(DSP_SPACE_X, l_addr, save_lx);
3838: write_memory(DSP_SPACE_Y, l_addr, save_ly);
1.1 root 3839: }
3840: }
3841:
3842: static void dsp_pm_5(void)
3843: {
1.1.1.2 root 3844: Uint32 memspace, numreg, value, xy_addr, retour;
1.1 root 3845: /*
1.1.1.4 root 3846: 01dd 0ddd w0aa aaaa x:aa,D
1.1 root 3847: S,x:aa
1.1.1.4 root 3848: 01dd 0ddd w1mm mrrr x:ea,D
1.1 root 3849: S,x:ea
3850: #xxxxxx,D
1.1.1.4 root 3851: 01dd 1ddd w0aa aaaa y:aa,D
1.1 root 3852: S,y:aa
1.1.1.4 root 3853: 01dd 1ddd w1mm mrrr y:ea,D
1.1 root 3854: S,y:ea
3855: #xxxxxx,D
3856: */
3857:
3858: value = (cur_inst>>8) & BITMASK(6);
3859:
3860: if (cur_inst & (1<<14)) {
1.1.1.11! root 3861: retour = dsp_calc_ea(value, &xy_addr);
1.1 root 3862: } else {
3863: xy_addr = value;
3864: retour = 0;
3865: }
3866:
3867: memspace = (cur_inst>>19) & 1;
3868: numreg = (cur_inst>>16) & BITMASK(3);
3869: numreg |= (cur_inst>>17) & (BITMASK(2)<<3);
3870:
3871: if (cur_inst & (1<<15)) {
3872: /* Write D */
1.1.1.6 root 3873: if (retour)
1.1 root 3874: value = xy_addr;
1.1.1.6 root 3875: else
1.1 root 3876: value = read_memory(memspace, xy_addr);
1.1.1.6 root 3877: }
3878: else {
1.1 root 3879: /* Read S */
1.1.1.6 root 3880: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B))
3881: dsp_pm_read_accu24(numreg, &value);
3882: else
3883: value = dsp_core.registers[numreg];
3884: }
1.1 root 3885:
3886:
1.1.1.6 root 3887: /* Execute parallel instruction */
3888: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3889:
1.1.1.6 root 3890: if (cur_inst & (1<<15)) {
3891: /* Write D */
1.1.1.11! root 3892: dsp_core.agu_move_indirect_instr = 1;
! 3893: dsp_write_reg(numreg, value);
1.1.1.6 root 3894: }
3895: else {
1.1.1.7 root 3896: /* Read S */
1.1.1.6 root 3897: write_memory(memspace, xy_addr, value);
1.1 root 3898: }
3899: }
3900:
3901: static void dsp_pm_8(void)
3902: {
1.1.1.2 root 3903: Uint32 ea1, ea2;
3904: Uint32 numreg1, numreg2;
1.1.1.6 root 3905: Uint32 save_reg1, save_reg2, x_addr, y_addr;
1.1 root 3906: /*
1.1.1.11! root 3907: 1wmm eeff WrrM MRRR x:ea,D1 y:ea,D2
1.1 root 3908: x:ea,D1 S2,y:ea
3909: S1,x:ea y:ea,D2
3910: S1,x:ea S2,y:ea
3911: */
3912: numreg1 = numreg2 = DSP_REG_NULL;
3913:
3914: ea1 = (cur_inst>>8) & BITMASK(5);
3915: if ((ea1>>3) == 0) {
3916: ea1 |= (1<<5);
3917: }
3918: ea2 = (cur_inst>>13) & BITMASK(2);
3919: ea2 |= (cur_inst>>17) & (BITMASK(2)<<3);
3920: if ((ea1 & (1<<2))==0) {
3921: ea2 |= 1<<2;
3922: }
3923: if ((ea2>>3) == 0) {
3924: ea2 |= (1<<5);
3925: }
3926:
1.1.1.4 root 3927: dsp_calc_ea(ea1, &x_addr);
3928: dsp_calc_ea(ea2, &y_addr);
3929:
1.1 root 3930: switch((cur_inst>>18) & BITMASK(2)) {
3931: case 0: numreg1=DSP_REG_X0; break;
3932: case 1: numreg1=DSP_REG_X1; break;
3933: case 2: numreg1=DSP_REG_A; break;
3934: case 3: numreg1=DSP_REG_B; break;
3935: }
3936: switch((cur_inst>>16) & BITMASK(2)) {
3937: case 0: numreg2=DSP_REG_Y0; break;
3938: case 1: numreg2=DSP_REG_Y1; break;
3939: case 2: numreg2=DSP_REG_A; break;
3940: case 3: numreg2=DSP_REG_B; break;
3941: }
1.1.1.11! root 3942:
1.1 root 3943: if (cur_inst & (1<<15)) {
3944: /* Write D1 */
1.1.1.6 root 3945: save_reg1 = read_memory(DSP_SPACE_X, x_addr);
1.1 root 3946: } else {
3947: /* Read S1 */
1.1.1.6 root 3948: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
3949: dsp_pm_read_accu24(numreg1, &save_reg1);
3950: else
3951: save_reg1 = dsp_core.registers[numreg1];
1.1 root 3952: }
3953:
3954: if (cur_inst & (1<<22)) {
3955: /* Write D2 */
1.1.1.6 root 3956: save_reg2 = read_memory(DSP_SPACE_Y, y_addr);
1.1 root 3957: } else {
3958: /* Read S2 */
1.1.1.6 root 3959: if ((numreg2==DSP_REG_A) || (numreg2==DSP_REG_B))
3960: dsp_pm_read_accu24(numreg2, &save_reg2);
3961: else
3962: save_reg2 = dsp_core.registers[numreg2];
1.1 root 3963: }
3964:
3965:
1.1.1.6 root 3966: /* Execute parallel instruction */
3967: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3968:
1.1.1.6 root 3969: /* Write first parallel move */
3970: if (cur_inst & (1<<15)) {
3971: /* Write D1 */
3972: if (numreg1 == DSP_REG_A) {
3973: dsp_core.registers[DSP_REG_A0] = 0x0;
3974: dsp_core.registers[DSP_REG_A1] = save_reg1;
3975: dsp_core.registers[DSP_REG_A2] = save_reg1 & (1<<23) ? 0xff : 0x0;
3976: }
3977: else if (numreg1 == DSP_REG_B) {
3978: dsp_core.registers[DSP_REG_B0] = 0x0;
3979: dsp_core.registers[DSP_REG_B1] = save_reg1;
3980: dsp_core.registers[DSP_REG_B2] = save_reg1 & (1<<23) ? 0xff : 0x0;
3981: }
3982: else {
3983: dsp_core.registers[numreg1] = save_reg1;
3984: }
3985: } else {
3986: /* Read S1 */
3987: write_memory(DSP_SPACE_X, x_addr, save_reg1);
3988: }
3989:
3990: /* Write second parallel move */
3991: if (cur_inst & (1<<22)) {
3992: /* Write D2 */
3993: if (numreg2 == DSP_REG_A) {
3994: dsp_core.registers[DSP_REG_A0] = 0x0;
3995: dsp_core.registers[DSP_REG_A1] = save_reg2;
3996: dsp_core.registers[DSP_REG_A2] = save_reg2 & (1<<23) ? 0xff : 0x0;
3997: }
3998: else if (numreg2 == DSP_REG_B) {
3999: dsp_core.registers[DSP_REG_B0] = 0x0;
4000: dsp_core.registers[DSP_REG_B1] = save_reg2;
4001: dsp_core.registers[DSP_REG_B2] = save_reg2 & (1<<23) ? 0xff : 0x0;
4002: }
4003: else {
4004: dsp_core.registers[numreg2] = save_reg2;
4005: }
4006: } else {
4007: /* Read S2 */
4008: write_memory(DSP_SPACE_Y, y_addr, save_reg2);
4009: }
4010: }
4011:
4012: /**********************************
4013: * 56bit arithmetic
4014: **********************************/
4015:
4016: /* source,dest[0] is 55:48 */
4017: /* source,dest[1] is 47:24 */
4018: /* source,dest[2] is 23:00 */
4019:
4020: static Uint16 dsp_abs56(Uint32 *dest)
1.1 root 4021: {
1.1.1.2 root 4022: Uint32 zerodest[3];
4023: Uint16 newsr;
1.1 root 4024:
4025: /* D=|D| */
4026:
4027: if (dest[0] & (1<<7)) {
4028: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4029:
4030: newsr = dsp_sub56(dest, zerodest);
4031:
4032: dest[0] = zerodest[0];
4033: dest[1] = zerodest[1];
4034: dest[2] = zerodest[2];
4035: } else {
4036: newsr = 0;
4037: }
4038:
4039: return newsr;
4040: }
4041:
1.1.1.2 root 4042: static Uint16 dsp_asl56(Uint32 *dest)
1.1 root 4043: {
1.1.1.2 root 4044: Uint16 overflow, carry;
1.1 root 4045:
4046: /* Shift left dest 1 bit: D<<=1 */
4047:
4048: carry = (dest[0]>>7) & 1;
4049:
4050: dest[0] <<= 1;
4051: dest[0] |= (dest[1]>>23) & 1;
4052: dest[0] &= BITMASK(8);
4053:
4054: dest[1] <<= 1;
4055: dest[1] |= (dest[2]>>23) & 1;
4056: dest[1] &= BITMASK(24);
1.1.1.11! root 4057:
1.1 root 4058: dest[2] <<= 1;
4059: dest[2] &= BITMASK(24);
4060:
4061: overflow = (carry != ((dest[0]>>7) & 1));
4062:
4063: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4064: }
4065:
1.1.1.2 root 4066: static Uint16 dsp_asr56(Uint32 *dest)
1.1 root 4067: {
1.1.1.2 root 4068: Uint16 carry;
1.1 root 4069:
4070: /* Shift right dest 1 bit: D>>=1 */
4071:
4072: carry = dest[2] & 1;
4073:
4074: dest[2] >>= 1;
4075: dest[2] |= (dest[1] & 1)<<23;
4076:
4077: dest[1] >>= 1;
4078: dest[1] |= (dest[0] & 1)<<23;
4079:
4080: dest[0] >>= 1;
4081: dest[0] |= (dest[0] & (1<<6))<<1;
4082:
4083: return (carry<<DSP_SR_C);
4084: }
4085:
1.1.1.2 root 4086: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest)
1.1 root 4087: {
1.1.1.4 root 4088: Uint16 overflow, carry, flg_s, flg_d, flg_r;
4089:
4090: flg_s = (source[0]>>7) & 1;
4091: flg_d = (dest[0]>>7) & 1;
4092:
1.1 root 4093: /* Add source to dest: D = D+S */
1.1.1.2 root 4094: dest[2] += source[2];
4095: dest[1] += source[1]+((dest[2]>>24) & 1);
4096: dest[0] += source[0]+((dest[1]>>24) & 1);
1.1 root 4097:
1.1.1.5 root 4098: carry = (dest[0]>>8) & 1;
4099:
1.1 root 4100: dest[2] &= BITMASK(24);
4101: dest[1] &= BITMASK(24);
4102: dest[0] &= BITMASK(8);
4103:
1.1.1.4 root 4104: flg_r = (dest[0]>>7) & 1;
4105:
4106: /*set overflow*/
4107: overflow = (flg_s ^ flg_r) & (flg_d ^ flg_r);
4108:
1.1 root 4109: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4110: }
4111:
1.1.1.2 root 4112: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest)
1.1 root 4113: {
1.1.1.5 root 4114: Uint16 overflow, carry, flg_s, flg_d, flg_r, dest_save;
1.1.1.4 root 4115:
1.1.1.5 root 4116: dest_save = dest[0];
1.1 root 4117:
1.1.1.9 root 4118: /* Subtract source from dest: D = D-S */
1.1.1.2 root 4119: dest[2] -= source[2];
4120: dest[1] -= source[1]+((dest[2]>>24) & 1);
4121: dest[0] -= source[0]+((dest[1]>>24) & 1);
1.1 root 4122:
1.1.1.5 root 4123: carry = (dest[0]>>8) & 1;
4124:
1.1 root 4125: dest[2] &= BITMASK(24);
4126: dest[1] &= BITMASK(24);
4127: dest[0] &= BITMASK(8);
4128:
1.1.1.4 root 4129: flg_s = (source[0]>>7) & 1;
1.1.1.5 root 4130: flg_d = (dest_save>>7) & 1;
1.1.1.4 root 4131: flg_r = (dest[0]>>7) & 1;
4132:
4133: /* set overflow */
4134: overflow = (flg_s ^ flg_d) & (flg_r ^ flg_d);
4135:
1.1 root 4136: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4137: }
4138:
1.1.1.5 root 4139: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe)
1.1 root 4140: {
1.1.1.2 root 4141: Uint32 part[4], zerodest[3], value;
1.1 root 4142:
4143: /* Multiply: D = S1*S2 */
4144: if (source1 & (1<<23)) {
1.1.1.5 root 4145: signe ^= 1;
1.1.1.6 root 4146: source1 = (1<<24) - source1;
1.1 root 4147: }
4148: if (source2 & (1<<23)) {
1.1.1.5 root 4149: signe ^= 1;
1.1.1.6 root 4150: source2 = (1<<24) - source2;
1.1 root 4151: }
4152:
4153: /* bits 0-11 * bits 0-11 */
4154: part[0]=(source1 & BITMASK(12))*(source2 & BITMASK(12));
4155: /* bits 12-23 * bits 0-11 */
4156: part[1]=((source1>>12) & BITMASK(12))*(source2 & BITMASK(12));
4157: /* bits 0-11 * bits 12-23 */
4158: part[2]=(source1 & BITMASK(12))*((source2>>12) & BITMASK(12));
4159: /* bits 12-23 * bits 12-23 */
4160: part[3]=((source1>>12) & BITMASK(12))*((source2>>12) & BITMASK(12));
4161:
4162: /* Calc dest 2 */
4163: dest[2] = part[0];
4164: dest[2] += (part[1] & BITMASK(12)) << 12;
4165: dest[2] += (part[2] & BITMASK(12)) << 12;
4166:
4167: /* Calc dest 1 */
4168: dest[1] = (part[1]>>12) & BITMASK(12);
4169: dest[1] += (part[2]>>12) & BITMASK(12);
4170: dest[1] += part[3];
4171:
4172: /* Calc dest 0 */
4173: dest[0] = 0;
4174:
4175: /* Add carries */
4176: value = (dest[2]>>24) & BITMASK(8);
4177: if (value) {
4178: dest[1] += value;
4179: dest[2] &= BITMASK(24);
4180: }
4181: value = (dest[1]>>24) & BITMASK(8);
4182: if (value) {
4183: dest[0] += value;
4184: dest[1] &= BITMASK(24);
4185: }
4186:
4187: /* Get rid of extra sign bit */
4188: dsp_asl56(dest);
4189:
1.1.1.5 root 4190: if (signe) {
1.1 root 4191: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4192:
4193: dsp_sub56(dest, zerodest);
4194:
4195: dest[0] = zerodest[0];
4196: dest[1] = zerodest[1];
4197: dest[2] = zerodest[2];
4198: }
4199: }
4200:
1.1.1.2 root 4201: static void dsp_rnd56(Uint32 *dest)
1.1 root 4202: {
1.1.1.4 root 4203: Uint32 rnd_const[3];
1.1 root 4204:
1.1.1.4 root 4205: rnd_const[0] = 0;
1.1 root 4206:
1.1.1.4 root 4207: /* Scaling mode S0 */
1.1.1.6 root 4208: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S0)) {
1.1.1.4 root 4209: rnd_const[1] = 1;
4210: rnd_const[2] = 0;
4211: dsp_add56(rnd_const, dest);
4212:
4213: if ((dest[2]==0) && ((dest[1] & 1) == 0)) {
4214: dest[1] &= (0xffffff - 0x3);
4215: }
4216: dest[1] &= 0xfffffe;
4217: dest[2]=0;
4218: }
4219: /* Scaling mode S1 */
1.1.1.6 root 4220: else if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S1)) {
1.1.1.4 root 4221: rnd_const[1] = 0;
4222: rnd_const[2] = (1<<22);
4223: dsp_add56(rnd_const, dest);
1.1.1.11! root 4224:
1.1.1.4 root 4225: if ((dest[2] & 0x7fffff) == 0){
4226: dest[2] = 0;
4227: }
4228: dest[2] &= 0x800000;
4229: }
4230: /* No Scaling */
4231: else {
4232: rnd_const[1] = 0;
4233: rnd_const[2] = (1<<23);
4234: dsp_add56(rnd_const, dest);
4235:
4236: if (dest[2] == 0) {
4237: dest[1] &= 0xfffffe;
1.1 root 4238: }
1.1.1.4 root 4239: dest[2]=0;
1.1 root 4240: }
4241: }
4242:
4243: /**********************************
4244: * Parallel moves instructions
4245: **********************************/
4246:
1.1.1.6 root 4247: static void dsp_abs_a(void)
1.1 root 4248: {
1.1.1.6 root 4249: Uint32 dest[3], overflowed;
1.1 root 4250:
1.1.1.6 root 4251: dest[0] = dsp_core.registers[DSP_REG_A2];
4252: dest[1] = dsp_core.registers[DSP_REG_A1];
4253: dest[2] = dsp_core.registers[DSP_REG_A0];
4254:
4255: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4256:
4257: dsp_abs56(dest);
4258:
4259: dsp_core.registers[DSP_REG_A2] = dest[0];
4260: dsp_core.registers[DSP_REG_A1] = dest[1];
4261: dsp_core.registers[DSP_REG_A0] = dest[2];
4262:
4263: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4264: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
4265:
4266: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4267: }
4268:
4269: static void dsp_abs_b(void)
4270: {
4271: Uint32 dest[3], overflowed;
1.1 root 4272:
1.1.1.6 root 4273: dest[0] = dsp_core.registers[DSP_REG_B2];
4274: dest[1] = dsp_core.registers[DSP_REG_B1];
4275: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 4276:
4277: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4278:
4279: dsp_abs56(dest);
4280:
1.1.1.6 root 4281: dsp_core.registers[DSP_REG_B2] = dest[0];
4282: dsp_core.registers[DSP_REG_B1] = dest[1];
4283: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4284:
1.1.1.6 root 4285: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4286: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
1.1.1.2 root 4287:
1.1.1.6 root 4288: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4289: }
4290:
1.1.1.6 root 4291: static void dsp_adc_x_a(void)
1.1 root 4292: {
1.1.1.6 root 4293: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4294: Uint16 newsr;
1.1 root 4295:
1.1.1.6 root 4296: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4297:
1.1.1.6 root 4298: dest[0] = dsp_core.registers[DSP_REG_A2];
4299: dest[1] = dsp_core.registers[DSP_REG_A1];
4300: dest[2] = dsp_core.registers[DSP_REG_A0];
4301:
4302: source[2] = dsp_core.registers[DSP_REG_X0];
4303: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4304: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4305:
4306: newsr = dsp_add56(source, dest);
1.1.1.11! root 4307:
1.1 root 4308: if (curcarry) {
1.1.1.6 root 4309: source[0]=0; source[1]=0; source[2]=1;
1.1 root 4310: newsr |= dsp_add56(source, dest);
4311: }
4312:
1.1.1.6 root 4313: dsp_core.registers[DSP_REG_A2] = dest[0];
4314: dsp_core.registers[DSP_REG_A1] = dest[1];
4315: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4316:
1.1.1.6 root 4317: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4318:
1.1.1.6 root 4319: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4320: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4321: }
4322:
1.1.1.6 root 4323: static void dsp_adc_x_b(void)
1.1 root 4324: {
1.1.1.6 root 4325: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4326: Uint16 newsr;
1.1 root 4327:
1.1.1.6 root 4328: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
4329:
4330: dest[0] = dsp_core.registers[DSP_REG_B2];
4331: dest[1] = dsp_core.registers[DSP_REG_B1];
4332: dest[2] = dsp_core.registers[DSP_REG_B0];
4333:
4334: source[2] = dsp_core.registers[DSP_REG_X0];
4335: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4336: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4337:
4338: newsr = dsp_add56(source, dest);
1.1.1.11! root 4339:
1.1.1.6 root 4340: if (curcarry) {
4341: source[0]=0; source[1]=0; source[2]=1;
4342: newsr |= dsp_add56(source, dest);
4343: }
1.1 root 4344:
1.1.1.6 root 4345: dsp_core.registers[DSP_REG_B2] = dest[0];
4346: dsp_core.registers[DSP_REG_B1] = dest[1];
4347: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4348:
1.1.1.6 root 4349: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4350:
1.1.1.6 root 4351: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4352: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4353: }
4354:
1.1.1.6 root 4355: static void dsp_adc_y_a(void)
1.1 root 4356: {
1.1.1.6 root 4357: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4358: Uint16 newsr;
1.1 root 4359:
1.1.1.6 root 4360: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4361:
1.1.1.6 root 4362: dest[0] = dsp_core.registers[DSP_REG_A2];
4363: dest[1] = dsp_core.registers[DSP_REG_A1];
4364: dest[2] = dsp_core.registers[DSP_REG_A0];
4365:
4366: source[2] = dsp_core.registers[DSP_REG_Y0];
4367: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4368: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4369:
1.1.1.6 root 4370: newsr = dsp_add56(source, dest);
1.1.1.11! root 4371:
1.1.1.6 root 4372: if (curcarry) {
4373: source[0]=0; source[1]=0; source[2]=1;
4374: newsr |= dsp_add56(source, dest);
4375: }
1.1 root 4376:
1.1.1.6 root 4377: dsp_core.registers[DSP_REG_A2] = dest[0];
4378: dsp_core.registers[DSP_REG_A1] = dest[1];
4379: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4380:
1.1.1.6 root 4381: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4382:
1.1.1.6 root 4383: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4384: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4385: }
4386:
1.1.1.6 root 4387: static void dsp_adc_y_b(void)
1.1 root 4388: {
1.1.1.6 root 4389: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4390: Uint16 newsr;
1.1 root 4391:
1.1.1.6 root 4392: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4393:
1.1.1.6 root 4394: dest[0] = dsp_core.registers[DSP_REG_B2];
4395: dest[1] = dsp_core.registers[DSP_REG_B1];
4396: dest[2] = dsp_core.registers[DSP_REG_B0];
4397:
4398: source[2] = dsp_core.registers[DSP_REG_Y0];
4399: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4400: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4401:
1.1.1.6 root 4402: newsr = dsp_add56(source, dest);
1.1.1.11! root 4403:
1.1.1.6 root 4404: if (curcarry) {
4405: source[0]=0; source[1]=0; source[2]=1;
4406: newsr |= dsp_add56(source, dest);
4407: }
1.1 root 4408:
1.1.1.6 root 4409: dsp_core.registers[DSP_REG_B2] = dest[0];
4410: dsp_core.registers[DSP_REG_B1] = dest[1];
4411: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4412:
1.1.1.6 root 4413: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4414:
1.1.1.6 root 4415: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4416: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4417: }
4418:
1.1.1.6 root 4419: static void dsp_add_b_a(void)
1.1 root 4420: {
1.1.1.6 root 4421: Uint32 source[3], dest[3];
4422: Uint16 newsr;
1.1 root 4423:
1.1.1.6 root 4424: dest[0] = dsp_core.registers[DSP_REG_A2];
4425: dest[1] = dsp_core.registers[DSP_REG_A1];
4426: dest[2] = dsp_core.registers[DSP_REG_A0];
4427:
4428: source[0] = dsp_core.registers[DSP_REG_B2];
4429: source[1] = dsp_core.registers[DSP_REG_B1];
4430: source[2] = dsp_core.registers[DSP_REG_B0];
4431:
4432: newsr = dsp_add56(source, dest);
4433:
4434: dsp_core.registers[DSP_REG_A2] = dest[0];
4435: dsp_core.registers[DSP_REG_A1] = dest[1];
4436: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4437:
1.1.1.6 root 4438: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4439:
1.1.1.6 root 4440: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4441: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4442: }
4443:
1.1.1.6 root 4444: static void dsp_add_a_b(void)
1.1 root 4445: {
1.1.1.6 root 4446: Uint32 source[3], dest[3];
1.1.1.2 root 4447: Uint16 newsr;
1.1 root 4448:
1.1.1.6 root 4449: dest[0] = dsp_core.registers[DSP_REG_B2];
4450: dest[1] = dsp_core.registers[DSP_REG_B1];
4451: dest[2] = dsp_core.registers[DSP_REG_B0];
4452:
4453: source[0] = dsp_core.registers[DSP_REG_A2];
4454: source[1] = dsp_core.registers[DSP_REG_A1];
4455: source[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 4456:
1.1.1.6 root 4457: newsr = dsp_add56(source, dest);
1.1 root 4458:
1.1.1.6 root 4459: dsp_core.registers[DSP_REG_B2] = dest[0];
4460: dsp_core.registers[DSP_REG_B1] = dest[1];
4461: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4462:
1.1.1.6 root 4463: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4464:
1.1.1.6 root 4465: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4466: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4467: }
4468:
1.1.1.6 root 4469: static void dsp_add_x_a(void)
1.1 root 4470: {
1.1.1.6 root 4471: Uint32 source[3], dest[3];
4472: Uint16 newsr;
1.1 root 4473:
1.1.1.6 root 4474: dest[0] = dsp_core.registers[DSP_REG_A2];
4475: dest[1] = dsp_core.registers[DSP_REG_A1];
4476: dest[2] = dsp_core.registers[DSP_REG_A0];
4477:
4478: source[1] = dsp_core.registers[DSP_REG_X1];
4479: source[2] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4480: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4481:
1.1.1.6 root 4482: newsr = dsp_add56(source, dest);
1.1 root 4483:
1.1.1.6 root 4484: dsp_core.registers[DSP_REG_A2] = dest[0];
4485: dsp_core.registers[DSP_REG_A1] = dest[1];
4486: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4487:
1.1.1.6 root 4488: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4489:
1.1.1.6 root 4490: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4491: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4492: }
4493:
1.1.1.6 root 4494: static void dsp_add_x_b(void)
1.1 root 4495: {
1.1.1.6 root 4496: Uint32 source[3], dest[3];
4497: Uint16 newsr;
1.1 root 4498:
1.1.1.6 root 4499: dest[0] = dsp_core.registers[DSP_REG_B2];
4500: dest[1] = dsp_core.registers[DSP_REG_B1];
4501: dest[2] = dsp_core.registers[DSP_REG_B0];
4502:
4503: source[1] = dsp_core.registers[DSP_REG_X1];
4504: source[2] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4505: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4506:
4507: newsr = dsp_add56(source, dest);
1.1 root 4508:
1.1.1.6 root 4509: dsp_core.registers[DSP_REG_B2] = dest[0];
4510: dsp_core.registers[DSP_REG_B1] = dest[1];
4511: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4512:
1.1.1.6 root 4513: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4514:
4515: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4516: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4517: }
4518:
1.1.1.6 root 4519: static void dsp_add_y_a(void)
1.1 root 4520: {
1.1.1.6 root 4521: Uint32 source[3], dest[3];
1.1.1.2 root 4522: Uint16 newsr;
1.1 root 4523:
1.1.1.6 root 4524: dest[0] = dsp_core.registers[DSP_REG_A2];
4525: dest[1] = dsp_core.registers[DSP_REG_A1];
4526: dest[2] = dsp_core.registers[DSP_REG_A0];
4527:
4528: source[1] = dsp_core.registers[DSP_REG_Y1];
4529: source[2] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4530: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4531:
1.1.1.6 root 4532: newsr = dsp_add56(source, dest);
1.1 root 4533:
1.1.1.6 root 4534: dsp_core.registers[DSP_REG_A2] = dest[0];
4535: dsp_core.registers[DSP_REG_A1] = dest[1];
4536: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4537:
1.1.1.6 root 4538: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4539:
4540: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4541: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4542: }
4543:
1.1.1.6 root 4544: static void dsp_add_y_b(void)
1.1 root 4545: {
1.1.1.6 root 4546: Uint32 source[3], dest[3];
1.1.1.2 root 4547: Uint16 newsr;
1.1 root 4548:
1.1.1.6 root 4549: dest[0] = dsp_core.registers[DSP_REG_B2];
4550: dest[1] = dsp_core.registers[DSP_REG_B1];
4551: dest[2] = dsp_core.registers[DSP_REG_B0];
4552:
4553: source[1] = dsp_core.registers[DSP_REG_Y1];
4554: source[2] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4555: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4556:
1.1.1.6 root 4557: newsr = dsp_add56(source, dest);
1.1 root 4558:
1.1.1.6 root 4559: dsp_core.registers[DSP_REG_B2] = dest[0];
4560: dsp_core.registers[DSP_REG_B1] = dest[1];
4561: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4562:
1.1.1.6 root 4563: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4564:
1.1.1.6 root 4565: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4566: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4567: }
4568:
1.1.1.6 root 4569: static void dsp_add_x0_a(void)
1.1 root 4570: {
1.1.1.6 root 4571: Uint32 source[3], dest[3];
4572: Uint16 newsr;
1.1 root 4573:
1.1.1.6 root 4574: dest[0] = dsp_core.registers[DSP_REG_A2];
4575: dest[1] = dsp_core.registers[DSP_REG_A1];
4576: dest[2] = dsp_core.registers[DSP_REG_A0];
4577:
4578: source[2] = 0;
4579: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4580: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4581:
4582: newsr = dsp_add56(source, dest);
4583:
4584: dsp_core.registers[DSP_REG_A2] = dest[0];
4585: dsp_core.registers[DSP_REG_A1] = dest[1];
4586: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4587:
1.1.1.6 root 4588: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4589:
1.1.1.6 root 4590: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4591: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4592: }
4593:
1.1.1.6 root 4594: static void dsp_add_x0_b(void)
1.1 root 4595: {
1.1.1.6 root 4596: Uint32 source[3], dest[3];
4597: Uint16 newsr;
4598:
4599: dest[0] = dsp_core.registers[DSP_REG_B2];
4600: dest[1] = dsp_core.registers[DSP_REG_B1];
4601: dest[2] = dsp_core.registers[DSP_REG_B0];
4602:
4603: source[2] = 0;
4604: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4605: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4606:
1.1.1.6 root 4607: newsr = dsp_add56(source, dest);
1.1 root 4608:
1.1.1.6 root 4609: dsp_core.registers[DSP_REG_B2] = dest[0];
4610: dsp_core.registers[DSP_REG_B1] = dest[1];
4611: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4612:
1.1.1.6 root 4613: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4614:
1.1.1.6 root 4615: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4616: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4617: }
4618:
1.1.1.6 root 4619: static void dsp_add_y0_a(void)
1.1 root 4620: {
1.1.1.6 root 4621: Uint32 source[3], dest[3];
4622: Uint16 newsr;
1.1 root 4623:
1.1.1.6 root 4624: dest[0] = dsp_core.registers[DSP_REG_A2];
4625: dest[1] = dsp_core.registers[DSP_REG_A1];
4626: dest[2] = dsp_core.registers[DSP_REG_A0];
4627:
4628: source[2] = 0;
4629: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4630: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4631:
1.1.1.6 root 4632: newsr = dsp_add56(source, dest);
4633:
4634: dsp_core.registers[DSP_REG_A2] = dest[0];
4635: dsp_core.registers[DSP_REG_A1] = dest[1];
4636: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4637:
1.1.1.6 root 4638: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4639:
1.1.1.6 root 4640: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4641: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4642: }
4643:
1.1.1.6 root 4644: static void dsp_add_y0_b(void)
1.1 root 4645: {
1.1.1.6 root 4646: Uint32 source[3], dest[3];
1.1.1.2 root 4647: Uint16 newsr;
1.1 root 4648:
1.1.1.6 root 4649: dest[0] = dsp_core.registers[DSP_REG_B2];
4650: dest[1] = dsp_core.registers[DSP_REG_B1];
4651: dest[2] = dsp_core.registers[DSP_REG_B0];
4652:
4653: source[2] = 0;
4654: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4655: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4656:
4657: newsr = dsp_add56(source, dest);
4658:
1.1.1.6 root 4659: dsp_core.registers[DSP_REG_B2] = dest[0];
4660: dsp_core.registers[DSP_REG_B1] = dest[1];
4661: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4662:
1.1.1.6 root 4663: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4664:
1.1.1.6 root 4665: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4666: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4667: }
4668:
1.1.1.6 root 4669: static void dsp_add_x1_a(void)
1.1 root 4670: {
1.1.1.6 root 4671: Uint32 source[3], dest[3];
1.1.1.2 root 4672: Uint16 newsr;
1.1 root 4673:
1.1.1.6 root 4674: dest[0] = dsp_core.registers[DSP_REG_A2];
4675: dest[1] = dsp_core.registers[DSP_REG_A1];
4676: dest[2] = dsp_core.registers[DSP_REG_A0];
4677:
4678: source[2] = 0;
4679: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4680: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4681:
4682: newsr = dsp_add56(source, dest);
4683:
1.1.1.6 root 4684: dsp_core.registers[DSP_REG_A2] = dest[0];
4685: dsp_core.registers[DSP_REG_A1] = dest[1];
4686: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4687:
1.1.1.6 root 4688: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4689:
1.1.1.6 root 4690: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4691: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4692: }
4693:
1.1.1.6 root 4694: static void dsp_add_x1_b(void)
1.1 root 4695: {
1.1.1.6 root 4696: Uint32 source[3], dest[3];
4697: Uint16 newsr;
4698:
4699: dest[0] = dsp_core.registers[DSP_REG_B2];
4700: dest[1] = dsp_core.registers[DSP_REG_B1];
4701: dest[2] = dsp_core.registers[DSP_REG_B0];
4702:
4703: source[2] = 0;
4704: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4705: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4706:
4707: newsr = dsp_add56(source, dest);
4708:
4709: dsp_core.registers[DSP_REG_B2] = dest[0];
4710: dsp_core.registers[DSP_REG_B1] = dest[1];
4711: dsp_core.registers[DSP_REG_B0] = dest[2];
4712:
4713: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4714:
4715: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4716: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4717: }
4718:
1.1.1.6 root 4719: static void dsp_add_y1_a(void)
1.1 root 4720: {
1.1.1.6 root 4721: Uint32 source[3], dest[3];
4722: Uint16 newsr;
1.1 root 4723:
1.1.1.6 root 4724: dest[0] = dsp_core.registers[DSP_REG_A2];
4725: dest[1] = dsp_core.registers[DSP_REG_A1];
4726: dest[2] = dsp_core.registers[DSP_REG_A0];
4727:
4728: source[2] = 0;
4729: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4730: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4731:
1.1.1.6 root 4732: newsr = dsp_add56(source, dest);
1.1 root 4733:
1.1.1.6 root 4734: dsp_core.registers[DSP_REG_A2] = dest[0];
4735: dsp_core.registers[DSP_REG_A1] = dest[1];
4736: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4737:
1.1.1.6 root 4738: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4739:
1.1.1.6 root 4740: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4741: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4742: }
4743:
1.1.1.6 root 4744: static void dsp_add_y1_b(void)
1.1 root 4745: {
1.1.1.6 root 4746: Uint32 source[3], dest[3];
4747: Uint16 newsr;
1.1 root 4748:
1.1.1.6 root 4749: dest[0] = dsp_core.registers[DSP_REG_B2];
4750: dest[1] = dsp_core.registers[DSP_REG_B1];
4751: dest[2] = dsp_core.registers[DSP_REG_B0];
4752:
4753: source[2] = 0;
4754: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4755: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4756:
1.1.1.6 root 4757: newsr = dsp_add56(source, dest);
1.1 root 4758:
1.1.1.6 root 4759: dsp_core.registers[DSP_REG_B2] = dest[0];
4760: dsp_core.registers[DSP_REG_B1] = dest[1];
4761: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4762:
1.1.1.6 root 4763: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4764:
1.1.1.6 root 4765: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4766: dsp_core.registers[DSP_REG_SR] |= newsr;
4767: }
1.1 root 4768:
1.1.1.6 root 4769: static void dsp_addl_b_a(void)
4770: {
4771: Uint32 source[3], dest[3];
4772: Uint16 newsr;
1.1.1.2 root 4773:
1.1.1.6 root 4774: dest[0] = dsp_core.registers[DSP_REG_A2];
4775: dest[1] = dsp_core.registers[DSP_REG_A1];
4776: dest[2] = dsp_core.registers[DSP_REG_A0];
4777: newsr = dsp_asl56(dest);
1.1 root 4778:
1.1.1.6 root 4779: source[0] = dsp_core.registers[DSP_REG_B2];
4780: source[1] = dsp_core.registers[DSP_REG_B1];
4781: source[2] = dsp_core.registers[DSP_REG_B0];
4782: newsr |= dsp_add56(source, dest);
1.1 root 4783:
1.1.1.6 root 4784: dsp_core.registers[DSP_REG_A2] = dest[0];
4785: dsp_core.registers[DSP_REG_A1] = dest[1];
4786: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4787:
1.1.1.6 root 4788: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4789:
1.1.1.6 root 4790: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4791: dsp_core.registers[DSP_REG_SR] |= newsr;
4792: }
1.1 root 4793:
1.1.1.6 root 4794: static void dsp_addl_a_b(void)
4795: {
4796: Uint32 source[3], dest[3];
4797: Uint16 newsr;
1.1 root 4798:
1.1.1.6 root 4799: dest[0] = dsp_core.registers[DSP_REG_B2];
4800: dest[1] = dsp_core.registers[DSP_REG_B1];
4801: dest[2] = dsp_core.registers[DSP_REG_B0];
4802: newsr = dsp_asl56(dest);
1.1 root 4803:
1.1.1.6 root 4804: source[0] = dsp_core.registers[DSP_REG_A2];
4805: source[1] = dsp_core.registers[DSP_REG_A1];
4806: source[2] = dsp_core.registers[DSP_REG_A0];
4807: newsr |= dsp_add56(source, dest);
4808:
4809: dsp_core.registers[DSP_REG_B2] = dest[0];
4810: dsp_core.registers[DSP_REG_B1] = dest[1];
4811: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4812:
1.1.1.6 root 4813: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4814:
1.1.1.6 root 4815: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4816: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4817: }
4818:
1.1.1.6 root 4819: static void dsp_addr_b_a(void)
1.1 root 4820: {
1.1.1.6 root 4821: Uint32 source[3], dest[3];
4822: Uint16 newsr;
4823:
4824: dest[0] = dsp_core.registers[DSP_REG_A2];
4825: dest[1] = dsp_core.registers[DSP_REG_A1];
4826: dest[2] = dsp_core.registers[DSP_REG_A0];
4827: newsr = dsp_asr56(dest);
4828:
4829: source[0] = dsp_core.registers[DSP_REG_B2];
4830: source[1] = dsp_core.registers[DSP_REG_B1];
4831: source[2] = dsp_core.registers[DSP_REG_B0];
4832: newsr |= dsp_add56(source, dest);
4833:
4834: dsp_core.registers[DSP_REG_A2] = dest[0];
4835: dsp_core.registers[DSP_REG_A1] = dest[1];
4836: dsp_core.registers[DSP_REG_A0] = dest[2];
4837:
4838: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4839:
4840: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4841: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4842: }
4843:
1.1.1.6 root 4844: static void dsp_addr_a_b(void)
1.1 root 4845: {
1.1.1.6 root 4846: Uint32 source[3], dest[3];
4847: Uint16 newsr;
4848:
4849: dest[0] = dsp_core.registers[DSP_REG_B2];
4850: dest[1] = dsp_core.registers[DSP_REG_B1];
4851: dest[2] = dsp_core.registers[DSP_REG_B0];
4852: newsr = dsp_asr56(dest);
4853:
4854: source[0] = dsp_core.registers[DSP_REG_A2];
4855: source[1] = dsp_core.registers[DSP_REG_A1];
4856: source[2] = dsp_core.registers[DSP_REG_A0];
4857: newsr |= dsp_add56(source, dest);
1.1 root 4858:
1.1.1.6 root 4859: dsp_core.registers[DSP_REG_B2] = dest[0];
4860: dsp_core.registers[DSP_REG_B1] = dest[1];
4861: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4862:
1.1.1.6 root 4863: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4864:
1.1.1.6 root 4865: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4866: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4867: }
4868:
1.1.1.6 root 4869: static void dsp_and_x0_a(void)
1.1 root 4870: {
1.1.1.6 root 4871: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X0];
1.1 root 4872:
1.1.1.6 root 4873: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4874: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4875: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4876: }
1.1 root 4877:
1.1.1.6 root 4878: static void dsp_and_x0_b(void)
4879: {
4880: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X0];
1.1 root 4881:
1.1.1.6 root 4882: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4883: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4884: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
1.1 root 4885: }
4886:
1.1.1.6 root 4887: static void dsp_and_y0_a(void)
1.1 root 4888: {
1.1.1.6 root 4889: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y0];
1.1 root 4890:
1.1.1.6 root 4891: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4892: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4893: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4894: }
1.1 root 4895:
1.1.1.6 root 4896: static void dsp_and_y0_b(void)
4897: {
4898: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y0];
1.1 root 4899:
1.1.1.6 root 4900: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4901: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4902: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
4903: }
1.1 root 4904:
1.1.1.6 root 4905: static void dsp_and_x1_a(void)
4906: {
4907: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X1];
1.1.1.2 root 4908:
1.1.1.6 root 4909: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4910: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4911: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
1.1 root 4912: }
4913:
1.1.1.6 root 4914: static void dsp_and_x1_b(void)
1.1 root 4915: {
1.1.1.6 root 4916: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X1];
4917:
4918: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4919: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4920: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
4921: }
1.1 root 4922:
1.1.1.6 root 4923: static void dsp_and_y1_a(void)
4924: {
4925: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y1];
1.1 root 4926:
1.1.1.6 root 4927: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4928: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4929: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4930: }
1.1 root 4931:
1.1.1.6 root 4932: static void dsp_and_y1_b(void)
4933: {
4934: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y1];
1.1.1.2 root 4935:
1.1.1.6 root 4936: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4937: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4938: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
1.1 root 4939: }
4940:
1.1.1.7 root 4941: static void dsp_asl_a(void)
1.1 root 4942: {
1.1.1.6 root 4943: Uint32 dest[3];
4944: Uint16 newsr;
1.1 root 4945:
1.1.1.6 root 4946: dest[0] = dsp_core.registers[DSP_REG_A2];
4947: dest[1] = dsp_core.registers[DSP_REG_A1];
4948: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 4949:
1.1.1.6 root 4950: newsr = dsp_asl56(dest);
4951:
4952: dsp_core.registers[DSP_REG_A2] = dest[0];
4953: dsp_core.registers[DSP_REG_A1] = dest[1];
4954: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4955:
1.1.1.6 root 4956: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
4957: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1.1.2 root 4958:
1.1.1.6 root 4959: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4960: }
4961:
1.1.1.7 root 4962: static void dsp_asl_b(void)
1.1 root 4963: {
1.1.1.6 root 4964: Uint32 dest[3];
1.1.1.2 root 4965: Uint16 newsr;
1.1 root 4966:
1.1.1.6 root 4967: dest[0] = dsp_core.registers[DSP_REG_B2];
4968: dest[1] = dsp_core.registers[DSP_REG_B1];
4969: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 4970:
1.1.1.6 root 4971: newsr = dsp_asl56(dest);
1.1 root 4972:
1.1.1.6 root 4973: dsp_core.registers[DSP_REG_B2] = dest[0];
4974: dsp_core.registers[DSP_REG_B1] = dest[1];
4975: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4976:
1.1.1.6 root 4977: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
4978: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4979:
1.1.1.6 root 4980: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4981: }
4982:
1.1.1.7 root 4983: static void dsp_asr_a(void)
1.1 root 4984: {
1.1.1.6 root 4985: Uint32 dest[3];
4986: Uint16 newsr;
4987:
4988: dest[0] = dsp_core.registers[DSP_REG_A2];
4989: dest[1] = dsp_core.registers[DSP_REG_A1];
4990: dest[2] = dsp_core.registers[DSP_REG_A0];
4991:
4992: newsr = dsp_asr56(dest);
4993:
4994: dsp_core.registers[DSP_REG_A2] = dest[0];
4995: dsp_core.registers[DSP_REG_A1] = dest[1];
4996: dsp_core.registers[DSP_REG_A0] = dest[2];
4997:
4998: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
4999: dsp_core.registers[DSP_REG_SR] |= newsr;
5000:
5001: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5002: }
5003:
1.1.1.7 root 5004: static void dsp_asr_b(void)
1.1.1.6 root 5005: {
5006: Uint32 dest[3];
5007: Uint16 newsr;
5008:
5009: dest[0] = dsp_core.registers[DSP_REG_B2];
5010: dest[1] = dsp_core.registers[DSP_REG_B1];
5011: dest[2] = dsp_core.registers[DSP_REG_B0];
5012:
5013: newsr = dsp_asr56(dest);
5014:
5015: dsp_core.registers[DSP_REG_B2] = dest[0];
5016: dsp_core.registers[DSP_REG_B1] = dest[1];
5017: dsp_core.registers[DSP_REG_B0] = dest[2];
5018:
5019: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5020: dsp_core.registers[DSP_REG_SR] |= newsr;
5021:
5022: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5023: }
5024:
5025: static void dsp_clr_a(void)
5026: {
1.1.1.7 root 5027: dsp_core.registers[DSP_REG_A2] = 0;
5028: dsp_core.registers[DSP_REG_A1] = 0;
5029: dsp_core.registers[DSP_REG_A0] = 0;
1.1.1.6 root 5030:
5031: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5032: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5033: }
5034:
5035: static void dsp_clr_b(void)
5036: {
1.1.1.7 root 5037: dsp_core.registers[DSP_REG_B2] = 0;
5038: dsp_core.registers[DSP_REG_B1] = 0;
5039: dsp_core.registers[DSP_REG_B0] = 0;
1.1.1.6 root 5040:
5041: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5042: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5043: }
5044:
5045: static void dsp_cmp_b_a(void)
5046: {
5047: Uint32 source[3], dest[3];
5048: Uint16 newsr;
5049:
5050: dest[0] = dsp_core.registers[DSP_REG_A2];
5051: dest[1] = dsp_core.registers[DSP_REG_A1];
5052: dest[2] = dsp_core.registers[DSP_REG_A0];
5053:
5054: source[0] = dsp_core.registers[DSP_REG_B2];
5055: source[1] = dsp_core.registers[DSP_REG_B1];
5056: source[2] = dsp_core.registers[DSP_REG_B0];
5057:
5058: newsr = dsp_sub56(source, dest);
5059:
5060: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5061:
5062: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5063: dsp_core.registers[DSP_REG_SR] |= newsr;
5064: }
5065:
5066: static void dsp_cmp_a_b(void)
5067: {
5068: Uint32 source[3], dest[3];
5069: Uint16 newsr;
5070:
5071: dest[0] = dsp_core.registers[DSP_REG_B2];
5072: dest[1] = dsp_core.registers[DSP_REG_B1];
5073: dest[2] = dsp_core.registers[DSP_REG_B0];
5074:
5075: source[0] = dsp_core.registers[DSP_REG_A2];
5076: source[1] = dsp_core.registers[DSP_REG_A1];
5077: source[2] = dsp_core.registers[DSP_REG_A0];
5078:
5079: newsr = dsp_sub56(source, dest);
5080:
5081: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5082:
5083: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5084: dsp_core.registers[DSP_REG_SR] |= newsr;
5085: }
5086:
5087: static void dsp_cmp_x0_a(void)
5088: {
5089: Uint32 source[3], dest[3];
5090: Uint16 newsr;
5091:
5092: dest[2] = dsp_core.registers[DSP_REG_A0];
5093: dest[1] = dsp_core.registers[DSP_REG_A1];
5094: dest[0] = dsp_core.registers[DSP_REG_A2];
5095:
5096: source[2] = 0;
5097: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5098: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5099:
5100: newsr = dsp_sub56(source, dest);
5101:
5102: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5103:
5104: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5105: dsp_core.registers[DSP_REG_SR] |= newsr;
5106: }
5107:
5108: static void dsp_cmp_x0_b(void)
5109: {
5110: Uint32 source[3], dest[3];
5111: Uint16 newsr;
5112:
5113: dest[0] = dsp_core.registers[DSP_REG_B2];
5114: dest[1] = dsp_core.registers[DSP_REG_B1];
5115: dest[2] = dsp_core.registers[DSP_REG_B0];
5116:
5117: source[2] = 0;
5118: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5119: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5120:
5121: newsr = dsp_sub56(source, dest);
5122:
5123: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5124:
5125: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5126: dsp_core.registers[DSP_REG_SR] |= newsr;
5127: }
5128:
5129: static void dsp_cmp_y0_a(void)
5130: {
5131: Uint32 source[3], dest[3];
5132: Uint16 newsr;
5133:
5134: dest[2] = dsp_core.registers[DSP_REG_A0];
5135: dest[1] = dsp_core.registers[DSP_REG_A1];
5136: dest[0] = dsp_core.registers[DSP_REG_A2];
5137:
5138: source[2] = 0;
5139: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5140: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5141:
5142: newsr = dsp_sub56(source, dest);
5143:
5144: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5145:
5146: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5147: dsp_core.registers[DSP_REG_SR] |= newsr;
5148: }
5149:
5150: static void dsp_cmp_y0_b(void)
5151: {
5152: Uint32 source[3], dest[3];
5153: Uint16 newsr;
5154:
5155: dest[0] = dsp_core.registers[DSP_REG_B2];
5156: dest[1] = dsp_core.registers[DSP_REG_B1];
5157: dest[2] = dsp_core.registers[DSP_REG_B0];
5158:
5159: source[2] = 0;
5160: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5161: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5162:
5163: newsr = dsp_sub56(source, dest);
5164:
5165: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5166:
5167: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5168: dsp_core.registers[DSP_REG_SR] |= newsr;
5169: }
5170: static void dsp_cmp_x1_a(void)
5171: {
5172: Uint32 source[3], dest[3];
5173: Uint16 newsr;
5174:
5175: dest[2] = dsp_core.registers[DSP_REG_A0];
5176: dest[1] = dsp_core.registers[DSP_REG_A1];
5177: dest[0] = dsp_core.registers[DSP_REG_A2];
5178:
5179: source[2] = 0;
5180: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5181: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5182:
5183: newsr = dsp_sub56(source, dest);
5184:
5185: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5186:
5187: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5188: dsp_core.registers[DSP_REG_SR] |= newsr;
5189: }
5190:
5191: static void dsp_cmp_x1_b(void)
5192: {
5193: Uint32 source[3], dest[3];
5194: Uint16 newsr;
5195:
5196: dest[0] = dsp_core.registers[DSP_REG_B2];
5197: dest[1] = dsp_core.registers[DSP_REG_B1];
5198: dest[2] = dsp_core.registers[DSP_REG_B0];
5199:
5200: source[2] = 0;
5201: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5202: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5203:
5204: newsr = dsp_sub56(source, dest);
5205:
5206: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5207:
5208: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5209: dsp_core.registers[DSP_REG_SR] |= newsr;
5210: }
5211:
5212: static void dsp_cmp_y1_a(void)
5213: {
5214: Uint32 source[3], dest[3];
5215: Uint16 newsr;
5216:
5217: dest[2] = dsp_core.registers[DSP_REG_A0];
5218: dest[1] = dsp_core.registers[DSP_REG_A1];
5219: dest[0] = dsp_core.registers[DSP_REG_A2];
5220:
5221: source[2] = 0;
5222: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5223: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5224:
5225: newsr = dsp_sub56(source, dest);
5226:
5227: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5228:
5229: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5230: dsp_core.registers[DSP_REG_SR] |= newsr;
5231: }
5232:
5233: static void dsp_cmp_y1_b(void)
5234: {
5235: Uint32 source[3], dest[3];
5236: Uint16 newsr;
5237:
5238: dest[0] = dsp_core.registers[DSP_REG_B2];
5239: dest[1] = dsp_core.registers[DSP_REG_B1];
5240: dest[2] = dsp_core.registers[DSP_REG_B0];
5241:
5242: source[2] = 0;
5243: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5244: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5245:
5246: newsr = dsp_sub56(source, dest);
5247:
5248: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5249:
5250: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5251: dsp_core.registers[DSP_REG_SR] |= newsr;
5252: }
5253:
5254: static void dsp_cmpm_b_a(void)
5255: {
5256: Uint32 source[3], dest[3];
5257: Uint16 newsr;
5258:
5259: dest[0] = dsp_core.registers[DSP_REG_A2];
5260: dest[1] = dsp_core.registers[DSP_REG_A1];
5261: dest[2] = dsp_core.registers[DSP_REG_A0];
5262: dsp_abs56(dest);
5263:
5264: source[0] = dsp_core.registers[DSP_REG_B2];
5265: source[1] = dsp_core.registers[DSP_REG_B1];
5266: source[2] = dsp_core.registers[DSP_REG_B0];
5267: dsp_abs56(source);
5268:
5269: newsr = dsp_sub56(source, dest);
5270:
5271: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5272:
5273: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5274: dsp_core.registers[DSP_REG_SR] |= newsr;
5275: }
5276:
5277: static void dsp_cmpm_a_b(void)
5278: {
5279: Uint32 source[3], dest[3];
5280: Uint16 newsr;
5281:
5282: dest[0] = dsp_core.registers[DSP_REG_B2];
5283: dest[1] = dsp_core.registers[DSP_REG_B1];
5284: dest[2] = dsp_core.registers[DSP_REG_B0];
5285: dsp_abs56(dest);
5286:
5287: source[0] = dsp_core.registers[DSP_REG_A2];
5288: source[1] = dsp_core.registers[DSP_REG_A1];
5289: source[2] = dsp_core.registers[DSP_REG_A0];
5290: dsp_abs56(source);
5291:
5292: newsr = dsp_sub56(source, dest);
5293:
5294: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5295:
5296: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5297: dsp_core.registers[DSP_REG_SR] |= newsr;
5298: }
5299:
5300: static void dsp_cmpm_x0_a(void)
5301: {
5302: Uint32 source[3], dest[3];
5303: Uint16 newsr;
5304:
5305: dest[2] = dsp_core.registers[DSP_REG_A0];
5306: dest[1] = dsp_core.registers[DSP_REG_A1];
5307: dest[0] = dsp_core.registers[DSP_REG_A2];
5308: dsp_abs56(dest);
5309:
5310: source[2] = 0;
5311: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5312: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5313: dsp_abs56(source);
5314:
5315: newsr = dsp_sub56(source, dest);
5316:
5317: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5318:
5319: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5320: dsp_core.registers[DSP_REG_SR] |= newsr;
5321: }
5322:
5323: static void dsp_cmpm_x0_b(void)
5324: {
5325: Uint32 source[3], dest[3];
5326: Uint16 newsr;
5327:
5328: dest[0] = dsp_core.registers[DSP_REG_B2];
5329: dest[1] = dsp_core.registers[DSP_REG_B1];
5330: dest[2] = dsp_core.registers[DSP_REG_B0];
5331: dsp_abs56(dest);
5332:
5333: source[2] = 0;
5334: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5335: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5336: dsp_abs56(source);
5337:
5338: newsr = dsp_sub56(source, dest);
5339:
5340: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5341:
5342: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5343: dsp_core.registers[DSP_REG_SR] |= newsr;
5344: }
5345:
5346: static void dsp_cmpm_y0_a(void)
5347: {
5348: Uint32 source[3], dest[3];
5349: Uint16 newsr;
5350:
5351: dest[2] = dsp_core.registers[DSP_REG_A0];
5352: dest[1] = dsp_core.registers[DSP_REG_A1];
5353: dest[0] = dsp_core.registers[DSP_REG_A2];
5354: dsp_abs56(dest);
5355:
5356: source[2] = 0;
5357: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5358: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5359: dsp_abs56(source);
5360:
5361: newsr = dsp_sub56(source, dest);
5362:
5363: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5364:
5365: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5366: dsp_core.registers[DSP_REG_SR] |= newsr;
5367: }
5368:
5369: static void dsp_cmpm_y0_b(void)
5370: {
5371: Uint32 source[3], dest[3];
5372: Uint16 newsr;
5373:
5374: dest[0] = dsp_core.registers[DSP_REG_B2];
5375: dest[1] = dsp_core.registers[DSP_REG_B1];
5376: dest[2] = dsp_core.registers[DSP_REG_B0];
5377: dsp_abs56(dest);
5378:
5379: source[2] = 0;
5380: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5381: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5382: dsp_abs56(source);
5383:
5384: newsr = dsp_sub56(source, dest);
5385:
5386: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5387:
5388: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5389: dsp_core.registers[DSP_REG_SR] |= newsr;
5390: }
5391:
5392: static void dsp_cmpm_x1_a(void)
5393: {
5394: Uint32 source[3], dest[3];
5395: Uint16 newsr;
5396:
5397: dest[2] = dsp_core.registers[DSP_REG_A0];
5398: dest[1] = dsp_core.registers[DSP_REG_A1];
5399: dest[0] = dsp_core.registers[DSP_REG_A2];
5400: dsp_abs56(dest);
5401:
5402: source[2] = 0;
5403: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5404: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5405: dsp_abs56(source);
5406:
5407: newsr = dsp_sub56(source, dest);
5408:
5409: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5410:
5411: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5412: dsp_core.registers[DSP_REG_SR] |= newsr;
5413: }
5414:
5415: static void dsp_cmpm_x1_b(void)
5416: {
5417: Uint32 source[3], dest[3];
5418: Uint16 newsr;
5419:
5420: dest[0] = dsp_core.registers[DSP_REG_B2];
5421: dest[1] = dsp_core.registers[DSP_REG_B1];
5422: dest[2] = dsp_core.registers[DSP_REG_B0];
5423: dsp_abs56(dest);
5424:
5425: source[2] = 0;
5426: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5427: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5428: dsp_abs56(source);
5429:
5430: newsr = dsp_sub56(source, dest);
5431:
5432: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5433:
5434: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5435: dsp_core.registers[DSP_REG_SR] |= newsr;
5436: }
5437:
5438: static void dsp_cmpm_y1_a(void)
5439: {
5440: Uint32 source[3], dest[3];
5441: Uint16 newsr;
5442:
5443: dest[2] = dsp_core.registers[DSP_REG_A0];
5444: dest[1] = dsp_core.registers[DSP_REG_A1];
5445: dest[0] = dsp_core.registers[DSP_REG_A2];
5446: dsp_abs56(dest);
5447:
5448: source[2] = 0;
5449: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5450: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5451: dsp_abs56(source);
5452:
5453: newsr = dsp_sub56(source, dest);
5454:
5455: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5456:
5457: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5458: dsp_core.registers[DSP_REG_SR] |= newsr;
5459: }
5460:
5461: static void dsp_cmpm_y1_b(void)
5462: {
5463: Uint32 source[3], dest[3];
5464: Uint16 newsr;
5465:
5466: dest[0] = dsp_core.registers[DSP_REG_B2];
5467: dest[1] = dsp_core.registers[DSP_REG_B1];
5468: dest[2] = dsp_core.registers[DSP_REG_B0];
5469: dsp_abs56(dest);
5470:
5471: source[2] = 0;
5472: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5473: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5474: dsp_abs56(source);
5475:
5476: newsr = dsp_sub56(source, dest);
5477:
5478: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5479:
5480: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5481: dsp_core.registers[DSP_REG_SR] |= newsr;
5482: }
5483:
5484: static void dsp_eor_x0_a(void)
5485: {
5486: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X0];
5487: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5488:
5489: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5490: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5491: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5492: }
5493:
5494: static void dsp_eor_x0_b(void)
5495: {
5496: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X0];
5497: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5498:
5499: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5500: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5501: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5502: }
5503:
5504: static void dsp_eor_y0_a(void)
5505: {
5506: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y0];
5507: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5508:
5509: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5510: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5511: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5512: }
5513:
5514: static void dsp_eor_y0_b(void)
5515: {
5516: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y0];
5517: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5518:
5519: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5520: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5521: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5522: }
5523:
5524: static void dsp_eor_x1_a(void)
5525: {
5526: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X1];
5527: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5528:
5529: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5530: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5531: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5532: }
5533:
5534: static void dsp_eor_x1_b(void)
5535: {
5536: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X1];
5537: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5538:
5539: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5540: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5541: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5542: }
5543:
5544: static void dsp_eor_y1_a(void)
5545: {
5546: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y1];
5547: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5548:
5549: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5550: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5551: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5552: }
5553:
5554: static void dsp_eor_y1_b(void)
5555: {
5556: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y1];
5557: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5558:
5559: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5560: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5561: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5562: }
5563:
5564: static void dsp_lsl_a(void)
5565: {
5566: Uint32 newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
5567:
5568: dsp_core.registers[DSP_REG_A1] <<= 1;
5569: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
5570:
5571: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5572: dsp_core.registers[DSP_REG_SR] |= newcarry;
5573: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5574: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5575: }
5576:
5577: static void dsp_lsl_b(void)
5578: {
5579: Uint32 newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
5580:
5581: dsp_core.registers[DSP_REG_B1] <<= 1;
5582: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
5583:
5584: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5585: dsp_core.registers[DSP_REG_SR] |= newcarry;
5586: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5587: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5588: }
5589:
5590: static void dsp_lsr_a(void)
5591: {
5592: Uint32 newcarry = dsp_core.registers[DSP_REG_A1] & 1;
5593: dsp_core.registers[DSP_REG_A1] >>= 1;
5594:
5595: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5596: dsp_core.registers[DSP_REG_SR] |= newcarry;
5597: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5598: }
5599:
5600: static void dsp_lsr_b(void)
5601: {
5602: Uint32 newcarry = dsp_core.registers[DSP_REG_B1] & 1;
5603: dsp_core.registers[DSP_REG_B1] >>= 1;
5604:
5605: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5606: dsp_core.registers[DSP_REG_SR] |= newcarry;
5607: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5608: }
5609:
5610: static void dsp_mac_p_x0_x0_a(void)
5611: {
5612: Uint32 source[3], dest[3];
5613: Uint16 newsr;
5614:
5615: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5616:
5617: dest[0] = dsp_core.registers[DSP_REG_A2];
5618: dest[1] = dsp_core.registers[DSP_REG_A1];
5619: dest[2] = dsp_core.registers[DSP_REG_A0];
5620: newsr = dsp_add56(source, dest);
5621:
5622: dsp_core.registers[DSP_REG_A2] = dest[0];
5623: dsp_core.registers[DSP_REG_A1] = dest[1];
5624: dsp_core.registers[DSP_REG_A0] = dest[2];
5625:
5626: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5627:
5628: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5629: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5630: }
5631:
5632: static void dsp_mac_m_x0_x0_a(void)
5633: {
5634: Uint32 source[3], dest[3];
5635: Uint16 newsr;
5636:
5637: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5638:
5639: dest[0] = dsp_core.registers[DSP_REG_A2];
5640: dest[1] = dsp_core.registers[DSP_REG_A1];
5641: dest[2] = dsp_core.registers[DSP_REG_A0];
5642: newsr = dsp_add56(source, dest);
5643:
5644: dsp_core.registers[DSP_REG_A2] = dest[0];
5645: dsp_core.registers[DSP_REG_A1] = dest[1];
5646: dsp_core.registers[DSP_REG_A0] = dest[2];
5647:
5648: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5649:
5650: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5651: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5652: }
5653: static void dsp_mac_p_x0_x0_b(void)
5654: {
5655: Uint32 source[3], dest[3];
5656: Uint16 newsr;
5657:
5658: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5659:
5660: dest[0] = dsp_core.registers[DSP_REG_B2];
5661: dest[1] = dsp_core.registers[DSP_REG_B1];
5662: dest[2] = dsp_core.registers[DSP_REG_B0];
5663: newsr = dsp_add56(source, dest);
5664:
5665: dsp_core.registers[DSP_REG_B2] = dest[0];
5666: dsp_core.registers[DSP_REG_B1] = dest[1];
5667: dsp_core.registers[DSP_REG_B0] = dest[2];
5668:
5669: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5670:
5671: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5672: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5673: }
5674:
5675: static void dsp_mac_m_x0_x0_b(void)
5676: {
5677: Uint32 source[3], dest[3];
5678: Uint16 newsr;
5679:
5680: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5681:
5682: dest[0] = dsp_core.registers[DSP_REG_B2];
5683: dest[1] = dsp_core.registers[DSP_REG_B1];
5684: dest[2] = dsp_core.registers[DSP_REG_B0];
5685: newsr = dsp_add56(source, dest);
5686:
5687: dsp_core.registers[DSP_REG_B2] = dest[0];
5688: dsp_core.registers[DSP_REG_B1] = dest[1];
5689: dsp_core.registers[DSP_REG_B0] = dest[2];
5690:
5691: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5692:
5693: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5694: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5695: }
5696:
5697: static void dsp_mac_p_y0_y0_a(void)
5698: {
5699: Uint32 source[3], dest[3];
5700: Uint16 newsr;
5701:
5702: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5703:
5704: dest[0] = dsp_core.registers[DSP_REG_A2];
5705: dest[1] = dsp_core.registers[DSP_REG_A1];
5706: dest[2] = dsp_core.registers[DSP_REG_A0];
5707: newsr = dsp_add56(source, dest);
5708:
5709: dsp_core.registers[DSP_REG_A2] = dest[0];
5710: dsp_core.registers[DSP_REG_A1] = dest[1];
5711: dsp_core.registers[DSP_REG_A0] = dest[2];
5712:
5713: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5714:
5715: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5716: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5717: }
5718:
5719: static void dsp_mac_m_y0_y0_a(void)
5720: {
5721: Uint32 source[3], dest[3];
5722: Uint16 newsr;
5723:
5724: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5725:
5726: dest[0] = dsp_core.registers[DSP_REG_A2];
5727: dest[1] = dsp_core.registers[DSP_REG_A1];
5728: dest[2] = dsp_core.registers[DSP_REG_A0];
5729: newsr = dsp_add56(source, dest);
5730:
5731: dsp_core.registers[DSP_REG_A2] = dest[0];
5732: dsp_core.registers[DSP_REG_A1] = dest[1];
5733: dsp_core.registers[DSP_REG_A0] = dest[2];
5734:
5735: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5736:
5737: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5738: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5739: }
5740: static void dsp_mac_p_y0_y0_b(void)
5741: {
5742: Uint32 source[3], dest[3];
5743: Uint16 newsr;
5744:
5745: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5746:
5747: dest[0] = dsp_core.registers[DSP_REG_B2];
5748: dest[1] = dsp_core.registers[DSP_REG_B1];
5749: dest[2] = dsp_core.registers[DSP_REG_B0];
5750: newsr = dsp_add56(source, dest);
5751:
5752: dsp_core.registers[DSP_REG_B2] = dest[0];
5753: dsp_core.registers[DSP_REG_B1] = dest[1];
5754: dsp_core.registers[DSP_REG_B0] = dest[2];
5755:
5756: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5757:
5758: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5759: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5760: }
5761:
5762: static void dsp_mac_m_y0_y0_b(void)
5763: {
5764: Uint32 source[3], dest[3];
5765: Uint16 newsr;
5766:
5767: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5768:
5769: dest[0] = dsp_core.registers[DSP_REG_B2];
5770: dest[1] = dsp_core.registers[DSP_REG_B1];
5771: dest[2] = dsp_core.registers[DSP_REG_B0];
5772: newsr = dsp_add56(source, dest);
5773:
5774: dsp_core.registers[DSP_REG_B2] = dest[0];
5775: dsp_core.registers[DSP_REG_B1] = dest[1];
5776: dsp_core.registers[DSP_REG_B0] = dest[2];
5777:
5778: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5779:
5780: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5781: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5782: }
5783:
5784: static void dsp_mac_p_x1_x0_a(void)
5785: {
5786: Uint32 source[3], dest[3];
5787: Uint16 newsr;
5788:
5789: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5790:
5791: dest[0] = dsp_core.registers[DSP_REG_A2];
5792: dest[1] = dsp_core.registers[DSP_REG_A1];
5793: dest[2] = dsp_core.registers[DSP_REG_A0];
5794: newsr = dsp_add56(source, dest);
5795:
5796: dsp_core.registers[DSP_REG_A2] = dest[0];
5797: dsp_core.registers[DSP_REG_A1] = dest[1];
5798: dsp_core.registers[DSP_REG_A0] = dest[2];
5799:
5800: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5801:
5802: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5803: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5804: }
5805:
5806: static void dsp_mac_m_x1_x0_a(void)
5807: {
5808: Uint32 source[3], dest[3];
5809: Uint16 newsr;
5810:
5811: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5812:
5813: dest[0] = dsp_core.registers[DSP_REG_A2];
5814: dest[1] = dsp_core.registers[DSP_REG_A1];
5815: dest[2] = dsp_core.registers[DSP_REG_A0];
5816: newsr = dsp_add56(source, dest);
5817:
5818: dsp_core.registers[DSP_REG_A2] = dest[0];
5819: dsp_core.registers[DSP_REG_A1] = dest[1];
5820: dsp_core.registers[DSP_REG_A0] = dest[2];
5821:
5822: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5823:
5824: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5825: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5826: }
5827:
5828: static void dsp_mac_p_x1_x0_b(void)
5829: {
5830: Uint32 source[3], dest[3];
5831: Uint16 newsr;
5832:
5833: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5834:
5835: dest[0] = dsp_core.registers[DSP_REG_B2];
5836: dest[1] = dsp_core.registers[DSP_REG_B1];
5837: dest[2] = dsp_core.registers[DSP_REG_B0];
5838: newsr = dsp_add56(source, dest);
5839:
5840: dsp_core.registers[DSP_REG_B2] = dest[0];
5841: dsp_core.registers[DSP_REG_B1] = dest[1];
5842: dsp_core.registers[DSP_REG_B0] = dest[2];
5843:
5844: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5845:
5846: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5847: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5848: }
5849:
5850: static void dsp_mac_m_x1_x0_b(void)
5851: {
5852: Uint32 source[3], dest[3];
5853: Uint16 newsr;
5854:
5855: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5856:
5857: dest[0] = dsp_core.registers[DSP_REG_B2];
5858: dest[1] = dsp_core.registers[DSP_REG_B1];
5859: dest[2] = dsp_core.registers[DSP_REG_B0];
5860: newsr = dsp_add56(source, dest);
5861:
5862: dsp_core.registers[DSP_REG_B2] = dest[0];
5863: dsp_core.registers[DSP_REG_B1] = dest[1];
5864: dsp_core.registers[DSP_REG_B0] = dest[2];
5865:
5866: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5867:
5868: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5869: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5870: }
5871:
5872: static void dsp_mac_p_y1_y0_a(void)
5873: {
5874: Uint32 source[3], dest[3];
5875: Uint16 newsr;
5876:
5877: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5878:
5879: dest[0] = dsp_core.registers[DSP_REG_A2];
5880: dest[1] = dsp_core.registers[DSP_REG_A1];
5881: dest[2] = dsp_core.registers[DSP_REG_A0];
5882: newsr = dsp_add56(source, dest);
5883:
5884: dsp_core.registers[DSP_REG_A2] = dest[0];
5885: dsp_core.registers[DSP_REG_A1] = dest[1];
5886: dsp_core.registers[DSP_REG_A0] = dest[2];
5887:
5888: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5889:
5890: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5891: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5892: }
5893:
5894: static void dsp_mac_m_y1_y0_a(void)
5895: {
5896: Uint32 source[3], dest[3];
5897: Uint16 newsr;
5898:
5899: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5900:
5901: dest[0] = dsp_core.registers[DSP_REG_A2];
5902: dest[1] = dsp_core.registers[DSP_REG_A1];
5903: dest[2] = dsp_core.registers[DSP_REG_A0];
5904: newsr = dsp_add56(source, dest);
5905:
5906: dsp_core.registers[DSP_REG_A2] = dest[0];
5907: dsp_core.registers[DSP_REG_A1] = dest[1];
5908: dsp_core.registers[DSP_REG_A0] = dest[2];
5909:
5910: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5911:
5912: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5913: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5914: }
5915:
5916: static void dsp_mac_p_y1_y0_b(void)
5917: {
5918: Uint32 source[3], dest[3];
5919: Uint16 newsr;
5920:
5921: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5922:
5923: dest[0] = dsp_core.registers[DSP_REG_B2];
5924: dest[1] = dsp_core.registers[DSP_REG_B1];
5925: dest[2] = dsp_core.registers[DSP_REG_B0];
5926: newsr = dsp_add56(source, dest);
5927:
5928: dsp_core.registers[DSP_REG_B2] = dest[0];
5929: dsp_core.registers[DSP_REG_B1] = dest[1];
5930: dsp_core.registers[DSP_REG_B0] = dest[2];
5931:
5932: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5933:
5934: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5935: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5936: }
5937:
5938: static void dsp_mac_m_y1_y0_b(void)
5939: {
5940: Uint32 source[3], dest[3];
5941: Uint16 newsr;
5942:
5943: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5944:
5945: dest[0] = dsp_core.registers[DSP_REG_B2];
5946: dest[1] = dsp_core.registers[DSP_REG_B1];
5947: dest[2] = dsp_core.registers[DSP_REG_B0];
5948: newsr = dsp_add56(source, dest);
5949:
5950: dsp_core.registers[DSP_REG_B2] = dest[0];
5951: dsp_core.registers[DSP_REG_B1] = dest[1];
5952: dsp_core.registers[DSP_REG_B0] = dest[2];
5953:
5954: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5955:
5956: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5957: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5958: }
5959:
5960: static void dsp_mac_p_x0_y1_a(void)
5961: {
5962: Uint32 source[3], dest[3];
5963: Uint16 newsr;
5964:
5965: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
5966:
5967: dest[0] = dsp_core.registers[DSP_REG_A2];
5968: dest[1] = dsp_core.registers[DSP_REG_A1];
5969: dest[2] = dsp_core.registers[DSP_REG_A0];
5970: newsr = dsp_add56(source, dest);
5971:
5972: dsp_core.registers[DSP_REG_A2] = dest[0];
5973: dsp_core.registers[DSP_REG_A1] = dest[1];
5974: dsp_core.registers[DSP_REG_A0] = dest[2];
5975:
5976: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5977:
5978: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5979: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5980: }
5981:
5982: static void dsp_mac_m_x0_y1_a(void)
5983: {
5984: Uint32 source[3], dest[3];
5985: Uint16 newsr;
5986:
5987: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
5988:
5989: dest[0] = dsp_core.registers[DSP_REG_A2];
5990: dest[1] = dsp_core.registers[DSP_REG_A1];
5991: dest[2] = dsp_core.registers[DSP_REG_A0];
5992: newsr = dsp_add56(source, dest);
5993:
5994: dsp_core.registers[DSP_REG_A2] = dest[0];
5995: dsp_core.registers[DSP_REG_A1] = dest[1];
5996: dsp_core.registers[DSP_REG_A0] = dest[2];
5997:
5998: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5999:
6000: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6001: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6002: }
6003:
6004: static void dsp_mac_p_x0_y1_b(void)
6005: {
6006: Uint32 source[3], dest[3];
6007: Uint16 newsr;
6008:
6009: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6010:
6011: dest[0] = dsp_core.registers[DSP_REG_B2];
6012: dest[1] = dsp_core.registers[DSP_REG_B1];
6013: dest[2] = dsp_core.registers[DSP_REG_B0];
6014: newsr = dsp_add56(source, dest);
6015:
6016: dsp_core.registers[DSP_REG_B2] = dest[0];
6017: dsp_core.registers[DSP_REG_B1] = dest[1];
6018: dsp_core.registers[DSP_REG_B0] = dest[2];
6019:
6020: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6021:
6022: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6023: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6024: }
6025:
6026: static void dsp_mac_m_x0_y1_b(void)
6027: {
6028: Uint32 source[3], dest[3];
6029: Uint16 newsr;
6030:
6031: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6032:
6033: dest[0] = dsp_core.registers[DSP_REG_B2];
6034: dest[1] = dsp_core.registers[DSP_REG_B1];
6035: dest[2] = dsp_core.registers[DSP_REG_B0];
6036: newsr = dsp_add56(source, dest);
6037:
6038: dsp_core.registers[DSP_REG_B2] = dest[0];
6039: dsp_core.registers[DSP_REG_B1] = dest[1];
6040: dsp_core.registers[DSP_REG_B0] = dest[2];
6041:
6042: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6043:
6044: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6045: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6046: }
6047:
6048: static void dsp_mac_p_y0_x0_a(void)
6049: {
6050: Uint32 source[3], dest[3];
6051: Uint16 newsr;
6052:
6053: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6054:
6055: dest[0] = dsp_core.registers[DSP_REG_A2];
6056: dest[1] = dsp_core.registers[DSP_REG_A1];
6057: dest[2] = dsp_core.registers[DSP_REG_A0];
6058: newsr = dsp_add56(source, dest);
6059:
6060: dsp_core.registers[DSP_REG_A2] = dest[0];
6061: dsp_core.registers[DSP_REG_A1] = dest[1];
6062: dsp_core.registers[DSP_REG_A0] = dest[2];
6063:
6064: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6065:
6066: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6067: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6068: }
6069:
6070: static void dsp_mac_m_y0_x0_a(void)
6071: {
6072: Uint32 source[3], dest[3];
6073: Uint16 newsr;
6074:
6075: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6076:
6077: dest[0] = dsp_core.registers[DSP_REG_A2];
6078: dest[1] = dsp_core.registers[DSP_REG_A1];
6079: dest[2] = dsp_core.registers[DSP_REG_A0];
6080: newsr = dsp_add56(source, dest);
6081:
6082: dsp_core.registers[DSP_REG_A2] = dest[0];
6083: dsp_core.registers[DSP_REG_A1] = dest[1];
6084: dsp_core.registers[DSP_REG_A0] = dest[2];
6085:
6086: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6087:
6088: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6089: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6090: }
6091:
6092: static void dsp_mac_p_y0_x0_b(void)
6093: {
6094: Uint32 source[3], dest[3];
6095: Uint16 newsr;
6096:
6097: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6098:
6099: dest[0] = dsp_core.registers[DSP_REG_B2];
6100: dest[1] = dsp_core.registers[DSP_REG_B1];
6101: dest[2] = dsp_core.registers[DSP_REG_B0];
6102: newsr = dsp_add56(source, dest);
6103:
6104: dsp_core.registers[DSP_REG_B2] = dest[0];
6105: dsp_core.registers[DSP_REG_B1] = dest[1];
6106: dsp_core.registers[DSP_REG_B0] = dest[2];
6107:
6108: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6109:
6110: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6111: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6112: }
6113:
6114: static void dsp_mac_m_y0_x0_b(void)
6115: {
6116: Uint32 source[3], dest[3];
6117: Uint16 newsr;
6118:
6119: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6120:
6121: dest[0] = dsp_core.registers[DSP_REG_B2];
6122: dest[1] = dsp_core.registers[DSP_REG_B1];
6123: dest[2] = dsp_core.registers[DSP_REG_B0];
6124: newsr = dsp_add56(source, dest);
6125:
6126: dsp_core.registers[DSP_REG_B2] = dest[0];
6127: dsp_core.registers[DSP_REG_B1] = dest[1];
6128: dsp_core.registers[DSP_REG_B0] = dest[2];
6129:
6130: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6131:
6132: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6133: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6134: }
6135:
6136: static void dsp_mac_p_x1_y0_a(void)
6137: {
6138: Uint32 source[3], dest[3];
6139: Uint16 newsr;
6140:
6141: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6142:
6143: dest[0] = dsp_core.registers[DSP_REG_A2];
6144: dest[1] = dsp_core.registers[DSP_REG_A1];
6145: dest[2] = dsp_core.registers[DSP_REG_A0];
6146: newsr = dsp_add56(source, dest);
6147:
6148: dsp_core.registers[DSP_REG_A2] = dest[0];
6149: dsp_core.registers[DSP_REG_A1] = dest[1];
6150: dsp_core.registers[DSP_REG_A0] = dest[2];
6151:
6152: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6153:
6154: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6155: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6156: }
6157:
6158: static void dsp_mac_m_x1_y0_a(void)
6159: {
6160: Uint32 source[3], dest[3];
6161: Uint16 newsr;
6162:
6163: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6164:
6165: dest[0] = dsp_core.registers[DSP_REG_A2];
6166: dest[1] = dsp_core.registers[DSP_REG_A1];
6167: dest[2] = dsp_core.registers[DSP_REG_A0];
6168: newsr = dsp_add56(source, dest);
6169:
6170: dsp_core.registers[DSP_REG_A2] = dest[0];
6171: dsp_core.registers[DSP_REG_A1] = dest[1];
6172: dsp_core.registers[DSP_REG_A0] = dest[2];
6173:
6174: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6175:
6176: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6177: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6178: }
6179:
6180: static void dsp_mac_p_x1_y0_b(void)
6181: {
6182: Uint32 source[3], dest[3];
6183: Uint16 newsr;
6184:
6185: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6186:
6187: dest[0] = dsp_core.registers[DSP_REG_B2];
6188: dest[1] = dsp_core.registers[DSP_REG_B1];
6189: dest[2] = dsp_core.registers[DSP_REG_B0];
6190: newsr = dsp_add56(source, dest);
6191:
6192: dsp_core.registers[DSP_REG_B2] = dest[0];
6193: dsp_core.registers[DSP_REG_B1] = dest[1];
6194: dsp_core.registers[DSP_REG_B0] = dest[2];
6195:
6196: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6197:
6198: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6199: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6200: }
6201:
6202: static void dsp_mac_m_x1_y0_b(void)
6203: {
6204: Uint32 source[3], dest[3];
6205: Uint16 newsr;
6206:
6207: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6208:
6209: dest[0] = dsp_core.registers[DSP_REG_B2];
6210: dest[1] = dsp_core.registers[DSP_REG_B1];
6211: dest[2] = dsp_core.registers[DSP_REG_B0];
6212: newsr = dsp_add56(source, dest);
6213:
6214: dsp_core.registers[DSP_REG_B2] = dest[0];
6215: dsp_core.registers[DSP_REG_B1] = dest[1];
6216: dsp_core.registers[DSP_REG_B0] = dest[2];
6217:
6218: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6219:
6220: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6221: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6222: }
6223:
6224: static void dsp_mac_p_y1_x1_a(void)
6225: {
6226: Uint32 source[3], dest[3];
6227: Uint16 newsr;
6228:
6229: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6230:
6231: dest[0] = dsp_core.registers[DSP_REG_A2];
6232: dest[1] = dsp_core.registers[DSP_REG_A1];
6233: dest[2] = dsp_core.registers[DSP_REG_A0];
6234: newsr = dsp_add56(source, dest);
6235:
6236: dsp_core.registers[DSP_REG_A2] = dest[0];
6237: dsp_core.registers[DSP_REG_A1] = dest[1];
6238: dsp_core.registers[DSP_REG_A0] = dest[2];
6239:
6240: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6241:
6242: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6243: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6244: }
6245:
6246: static void dsp_mac_m_y1_x1_a(void)
6247: {
6248: Uint32 source[3], dest[3];
6249: Uint16 newsr;
6250:
6251: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6252:
6253: dest[0] = dsp_core.registers[DSP_REG_A2];
6254: dest[1] = dsp_core.registers[DSP_REG_A1];
6255: dest[2] = dsp_core.registers[DSP_REG_A0];
6256: newsr = dsp_add56(source, dest);
6257:
6258: dsp_core.registers[DSP_REG_A2] = dest[0];
6259: dsp_core.registers[DSP_REG_A1] = dest[1];
6260: dsp_core.registers[DSP_REG_A0] = dest[2];
6261:
6262: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6263:
6264: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6265: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6266: }
6267:
6268: static void dsp_mac_p_y1_x1_b(void)
6269: {
6270: Uint32 source[3], dest[3];
6271: Uint16 newsr;
6272:
6273: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6274:
6275: dest[0] = dsp_core.registers[DSP_REG_B2];
6276: dest[1] = dsp_core.registers[DSP_REG_B1];
6277: dest[2] = dsp_core.registers[DSP_REG_B0];
6278: newsr = dsp_add56(source, dest);
6279:
6280: dsp_core.registers[DSP_REG_B2] = dest[0];
6281: dsp_core.registers[DSP_REG_B1] = dest[1];
6282: dsp_core.registers[DSP_REG_B0] = dest[2];
6283:
6284: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6285:
6286: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6287: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6288: }
6289:
6290: static void dsp_mac_m_y1_x1_b(void)
6291: {
6292: Uint32 source[3], dest[3];
6293: Uint16 newsr;
6294:
6295: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6296:
6297: dest[0] = dsp_core.registers[DSP_REG_B2];
6298: dest[1] = dsp_core.registers[DSP_REG_B1];
6299: dest[2] = dsp_core.registers[DSP_REG_B0];
6300: newsr = dsp_add56(source, dest);
6301:
6302: dsp_core.registers[DSP_REG_B2] = dest[0];
6303: dsp_core.registers[DSP_REG_B1] = dest[1];
6304: dsp_core.registers[DSP_REG_B0] = dest[2];
6305:
6306: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6307:
6308: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6309: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6310: }
6311:
6312: static void dsp_macr_p_x0_x0_a(void)
6313: {
6314: Uint32 source[3], dest[3];
6315: Uint16 newsr;
6316:
6317: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6318:
6319: dest[0] = dsp_core.registers[DSP_REG_A2];
6320: dest[1] = dsp_core.registers[DSP_REG_A1];
6321: dest[2] = dsp_core.registers[DSP_REG_A0];
6322: newsr = dsp_add56(source, dest);
6323:
6324: dsp_rnd56(dest);
6325:
6326: dsp_core.registers[DSP_REG_A2] = dest[0];
6327: dsp_core.registers[DSP_REG_A1] = dest[1];
6328: dsp_core.registers[DSP_REG_A0] = dest[2];
6329:
6330: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6331:
6332: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6333: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6334: }
6335:
6336: static void dsp_macr_m_x0_x0_a(void)
6337: {
6338: Uint32 source[3], dest[3];
6339: Uint16 newsr;
6340:
6341: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6342:
6343: dest[0] = dsp_core.registers[DSP_REG_A2];
6344: dest[1] = dsp_core.registers[DSP_REG_A1];
6345: dest[2] = dsp_core.registers[DSP_REG_A0];
6346: newsr = dsp_add56(source, dest);
6347:
6348: dsp_rnd56(dest);
6349:
6350: dsp_core.registers[DSP_REG_A2] = dest[0];
6351: dsp_core.registers[DSP_REG_A1] = dest[1];
6352: dsp_core.registers[DSP_REG_A0] = dest[2];
6353:
6354: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6355:
6356: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6357: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6358: }
6359: static void dsp_macr_p_x0_x0_b(void)
6360: {
6361: Uint32 source[3], dest[3];
6362: Uint16 newsr;
6363:
6364: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6365:
6366: dest[0] = dsp_core.registers[DSP_REG_B2];
6367: dest[1] = dsp_core.registers[DSP_REG_B1];
6368: dest[2] = dsp_core.registers[DSP_REG_B0];
6369: newsr = dsp_add56(source, dest);
6370:
6371: dsp_rnd56(dest);
6372:
6373: dsp_core.registers[DSP_REG_B2] = dest[0];
6374: dsp_core.registers[DSP_REG_B1] = dest[1];
6375: dsp_core.registers[DSP_REG_B0] = dest[2];
6376:
6377: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6378:
6379: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6380: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6381: }
6382:
6383: static void dsp_macr_m_x0_x0_b(void)
6384: {
6385: Uint32 source[3], dest[3];
6386: Uint16 newsr;
6387:
6388: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6389:
6390: dest[0] = dsp_core.registers[DSP_REG_B2];
6391: dest[1] = dsp_core.registers[DSP_REG_B1];
6392: dest[2] = dsp_core.registers[DSP_REG_B0];
6393: newsr = dsp_add56(source, dest);
6394:
6395: dsp_rnd56(dest);
6396:
6397: dsp_core.registers[DSP_REG_B2] = dest[0];
6398: dsp_core.registers[DSP_REG_B1] = dest[1];
6399: dsp_core.registers[DSP_REG_B0] = dest[2];
6400:
6401: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6402:
6403: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6404: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6405: }
6406:
6407: static void dsp_macr_p_y0_y0_a(void)
6408: {
6409: Uint32 source[3], dest[3];
6410: Uint16 newsr;
6411:
6412: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6413:
6414: dest[0] = dsp_core.registers[DSP_REG_A2];
6415: dest[1] = dsp_core.registers[DSP_REG_A1];
6416: dest[2] = dsp_core.registers[DSP_REG_A0];
6417: newsr = dsp_add56(source, dest);
6418:
6419: dsp_rnd56(dest);
6420:
6421: dsp_core.registers[DSP_REG_A2] = dest[0];
6422: dsp_core.registers[DSP_REG_A1] = dest[1];
6423: dsp_core.registers[DSP_REG_A0] = dest[2];
6424:
6425: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6426:
6427: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6428: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6429: }
6430:
6431: static void dsp_macr_m_y0_y0_a(void)
6432: {
6433: Uint32 source[3], dest[3];
6434: Uint16 newsr;
6435:
6436: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6437:
6438: dest[0] = dsp_core.registers[DSP_REG_A2];
6439: dest[1] = dsp_core.registers[DSP_REG_A1];
6440: dest[2] = dsp_core.registers[DSP_REG_A0];
6441: newsr = dsp_add56(source, dest);
6442:
6443: dsp_rnd56(dest);
6444:
6445: dsp_core.registers[DSP_REG_A2] = dest[0];
6446: dsp_core.registers[DSP_REG_A1] = dest[1];
6447: dsp_core.registers[DSP_REG_A0] = dest[2];
6448:
6449: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6450:
6451: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6452: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6453: }
6454: static void dsp_macr_p_y0_y0_b(void)
6455: {
6456: Uint32 source[3], dest[3];
6457: Uint16 newsr;
6458:
6459: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6460:
6461: dest[0] = dsp_core.registers[DSP_REG_B2];
6462: dest[1] = dsp_core.registers[DSP_REG_B1];
6463: dest[2] = dsp_core.registers[DSP_REG_B0];
6464: newsr = dsp_add56(source, dest);
6465:
6466: dsp_rnd56(dest);
6467:
6468: dsp_core.registers[DSP_REG_B2] = dest[0];
6469: dsp_core.registers[DSP_REG_B1] = dest[1];
6470: dsp_core.registers[DSP_REG_B0] = dest[2];
6471:
6472: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6473:
6474: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6475: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6476: }
6477:
6478: static void dsp_macr_m_y0_y0_b(void)
6479: {
6480: Uint32 source[3], dest[3];
6481: Uint16 newsr;
6482:
6483: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6484:
6485: dest[0] = dsp_core.registers[DSP_REG_B2];
6486: dest[1] = dsp_core.registers[DSP_REG_B1];
6487: dest[2] = dsp_core.registers[DSP_REG_B0];
6488: newsr = dsp_add56(source, dest);
6489:
6490: dsp_rnd56(dest);
6491:
6492: dsp_core.registers[DSP_REG_B2] = dest[0];
6493: dsp_core.registers[DSP_REG_B1] = dest[1];
6494: dsp_core.registers[DSP_REG_B0] = dest[2];
6495:
6496: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6497:
6498: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6499: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6500: }
6501:
6502: static void dsp_macr_p_x1_x0_a(void)
6503: {
6504: Uint32 source[3], dest[3];
6505: Uint16 newsr;
6506:
6507: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6508:
6509: dest[0] = dsp_core.registers[DSP_REG_A2];
6510: dest[1] = dsp_core.registers[DSP_REG_A1];
6511: dest[2] = dsp_core.registers[DSP_REG_A0];
6512: newsr = dsp_add56(source, dest);
6513:
6514: dsp_rnd56(dest);
6515:
6516: dsp_core.registers[DSP_REG_A2] = dest[0];
6517: dsp_core.registers[DSP_REG_A1] = dest[1];
6518: dsp_core.registers[DSP_REG_A0] = dest[2];
6519:
6520: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6521:
6522: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6523: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6524: }
6525:
6526: static void dsp_macr_m_x1_x0_a(void)
6527: {
6528: Uint32 source[3], dest[3];
6529: Uint16 newsr;
6530:
6531: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6532:
6533: dest[0] = dsp_core.registers[DSP_REG_A2];
6534: dest[1] = dsp_core.registers[DSP_REG_A1];
6535: dest[2] = dsp_core.registers[DSP_REG_A0];
6536: newsr = dsp_add56(source, dest);
6537:
6538: dsp_rnd56(dest);
6539:
6540: dsp_core.registers[DSP_REG_A2] = dest[0];
6541: dsp_core.registers[DSP_REG_A1] = dest[1];
6542: dsp_core.registers[DSP_REG_A0] = dest[2];
6543:
6544: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6545:
6546: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6547: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6548: }
6549:
6550: static void dsp_macr_p_x1_x0_b(void)
6551: {
6552: Uint32 source[3], dest[3];
6553: Uint16 newsr;
6554:
6555: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6556:
6557: dest[0] = dsp_core.registers[DSP_REG_B2];
6558: dest[1] = dsp_core.registers[DSP_REG_B1];
6559: dest[2] = dsp_core.registers[DSP_REG_B0];
6560: newsr = dsp_add56(source, dest);
6561:
6562: dsp_rnd56(dest);
6563:
6564: dsp_core.registers[DSP_REG_B2] = dest[0];
6565: dsp_core.registers[DSP_REG_B1] = dest[1];
6566: dsp_core.registers[DSP_REG_B0] = dest[2];
6567:
6568: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6569:
6570: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6571: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6572: }
6573:
6574: static void dsp_macr_m_x1_x0_b(void)
6575: {
6576: Uint32 source[3], dest[3];
6577: Uint16 newsr;
6578:
6579: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6580:
6581: dest[0] = dsp_core.registers[DSP_REG_B2];
6582: dest[1] = dsp_core.registers[DSP_REG_B1];
6583: dest[2] = dsp_core.registers[DSP_REG_B0];
6584: newsr = dsp_add56(source, dest);
6585:
6586: dsp_rnd56(dest);
6587:
6588: dsp_core.registers[DSP_REG_B2] = dest[0];
6589: dsp_core.registers[DSP_REG_B1] = dest[1];
6590: dsp_core.registers[DSP_REG_B0] = dest[2];
6591:
6592: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6593:
6594: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6595: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6596: }
6597:
6598: static void dsp_macr_p_y1_y0_a(void)
6599: {
6600: Uint32 source[3], dest[3];
6601: Uint16 newsr;
6602:
6603: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6604:
6605: dest[0] = dsp_core.registers[DSP_REG_A2];
6606: dest[1] = dsp_core.registers[DSP_REG_A1];
6607: dest[2] = dsp_core.registers[DSP_REG_A0];
6608: newsr = dsp_add56(source, dest);
6609:
6610: dsp_rnd56(dest);
6611:
6612: dsp_core.registers[DSP_REG_A2] = dest[0];
6613: dsp_core.registers[DSP_REG_A1] = dest[1];
6614: dsp_core.registers[DSP_REG_A0] = dest[2];
6615:
6616: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6617:
6618: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6619: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6620: }
6621:
6622: static void dsp_macr_m_y1_y0_a(void)
6623: {
6624: Uint32 source[3], dest[3];
6625: Uint16 newsr;
6626:
6627: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6628:
6629: dest[0] = dsp_core.registers[DSP_REG_A2];
6630: dest[1] = dsp_core.registers[DSP_REG_A1];
6631: dest[2] = dsp_core.registers[DSP_REG_A0];
6632: newsr = dsp_add56(source, dest);
6633:
6634: dsp_rnd56(dest);
6635:
6636: dsp_core.registers[DSP_REG_A2] = dest[0];
6637: dsp_core.registers[DSP_REG_A1] = dest[1];
6638: dsp_core.registers[DSP_REG_A0] = dest[2];
6639:
6640: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6641:
6642: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6643: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6644: }
6645:
6646: static void dsp_macr_p_y1_y0_b(void)
6647: {
6648: Uint32 source[3], dest[3];
6649: Uint16 newsr;
6650:
6651: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6652:
6653: dest[0] = dsp_core.registers[DSP_REG_B2];
6654: dest[1] = dsp_core.registers[DSP_REG_B1];
6655: dest[2] = dsp_core.registers[DSP_REG_B0];
6656: newsr = dsp_add56(source, dest);
6657:
6658: dsp_rnd56(dest);
6659:
6660: dsp_core.registers[DSP_REG_B2] = dest[0];
6661: dsp_core.registers[DSP_REG_B1] = dest[1];
6662: dsp_core.registers[DSP_REG_B0] = dest[2];
6663:
6664: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6665:
6666: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6667: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6668: }
6669:
6670: static void dsp_macr_m_y1_y0_b(void)
6671: {
6672: Uint32 source[3], dest[3];
6673: Uint16 newsr;
6674:
6675: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6676:
6677: dest[0] = dsp_core.registers[DSP_REG_B2];
6678: dest[1] = dsp_core.registers[DSP_REG_B1];
6679: dest[2] = dsp_core.registers[DSP_REG_B0];
6680: newsr = dsp_add56(source, dest);
6681:
6682: dsp_rnd56(dest);
6683:
6684: dsp_core.registers[DSP_REG_B2] = dest[0];
6685: dsp_core.registers[DSP_REG_B1] = dest[1];
6686: dsp_core.registers[DSP_REG_B0] = dest[2];
6687:
6688: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6689:
6690: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6691: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6692: }
6693:
6694: static void dsp_macr_p_x0_y1_a(void)
6695: {
6696: Uint32 source[3], dest[3];
6697: Uint16 newsr;
6698:
6699: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6700:
6701: dest[0] = dsp_core.registers[DSP_REG_A2];
6702: dest[1] = dsp_core.registers[DSP_REG_A1];
6703: dest[2] = dsp_core.registers[DSP_REG_A0];
6704: newsr = dsp_add56(source, dest);
6705:
6706: dsp_rnd56(dest);
6707:
6708: dsp_core.registers[DSP_REG_A2] = dest[0];
6709: dsp_core.registers[DSP_REG_A1] = dest[1];
6710: dsp_core.registers[DSP_REG_A0] = dest[2];
6711:
6712: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6713:
6714: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6715: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6716: }
6717:
6718: static void dsp_macr_m_x0_y1_a(void)
6719: {
6720: Uint32 source[3], dest[3];
6721: Uint16 newsr;
6722:
6723: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6724:
6725: dest[0] = dsp_core.registers[DSP_REG_A2];
6726: dest[1] = dsp_core.registers[DSP_REG_A1];
6727: dest[2] = dsp_core.registers[DSP_REG_A0];
6728: newsr = dsp_add56(source, dest);
6729:
6730: dsp_rnd56(dest);
6731:
6732: dsp_core.registers[DSP_REG_A2] = dest[0];
6733: dsp_core.registers[DSP_REG_A1] = dest[1];
6734: dsp_core.registers[DSP_REG_A0] = dest[2];
6735:
6736: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6737:
6738: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6739: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6740: }
6741:
6742: static void dsp_macr_p_x0_y1_b(void)
6743: {
6744: Uint32 source[3], dest[3];
6745: Uint16 newsr;
6746:
6747: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6748:
6749: dest[0] = dsp_core.registers[DSP_REG_B2];
6750: dest[1] = dsp_core.registers[DSP_REG_B1];
6751: dest[2] = dsp_core.registers[DSP_REG_B0];
6752: newsr = dsp_add56(source, dest);
6753:
6754: dsp_rnd56(dest);
6755:
6756: dsp_core.registers[DSP_REG_B2] = dest[0];
6757: dsp_core.registers[DSP_REG_B1] = dest[1];
6758: dsp_core.registers[DSP_REG_B0] = dest[2];
6759:
6760: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6761:
6762: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6763: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6764: }
6765:
6766: static void dsp_macr_m_x0_y1_b(void)
6767: {
6768: Uint32 source[3], dest[3];
6769: Uint16 newsr;
6770:
6771: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6772:
6773: dest[0] = dsp_core.registers[DSP_REG_B2];
6774: dest[1] = dsp_core.registers[DSP_REG_B1];
6775: dest[2] = dsp_core.registers[DSP_REG_B0];
6776: newsr = dsp_add56(source, dest);
6777:
6778: dsp_rnd56(dest);
6779:
6780: dsp_core.registers[DSP_REG_B2] = dest[0];
6781: dsp_core.registers[DSP_REG_B1] = dest[1];
6782: dsp_core.registers[DSP_REG_B0] = dest[2];
6783:
6784: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6785:
6786: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6787: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6788: }
6789:
6790: static void dsp_macr_p_y0_x0_a(void)
6791: {
6792: Uint32 source[3], dest[3];
6793: Uint16 newsr;
6794:
6795: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6796:
6797: dest[0] = dsp_core.registers[DSP_REG_A2];
6798: dest[1] = dsp_core.registers[DSP_REG_A1];
6799: dest[2] = dsp_core.registers[DSP_REG_A0];
6800: newsr = dsp_add56(source, dest);
6801:
6802: dsp_rnd56(dest);
6803:
6804: dsp_core.registers[DSP_REG_A2] = dest[0];
6805: dsp_core.registers[DSP_REG_A1] = dest[1];
6806: dsp_core.registers[DSP_REG_A0] = dest[2];
6807:
6808: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6809:
6810: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6811: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6812: }
6813:
6814: static void dsp_macr_m_y0_x0_a(void)
6815: {
6816: Uint32 source[3], dest[3];
6817: Uint16 newsr;
6818:
6819: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6820:
6821: dest[0] = dsp_core.registers[DSP_REG_A2];
6822: dest[1] = dsp_core.registers[DSP_REG_A1];
6823: dest[2] = dsp_core.registers[DSP_REG_A0];
6824: newsr = dsp_add56(source, dest);
6825:
6826: dsp_rnd56(dest);
6827:
6828: dsp_core.registers[DSP_REG_A2] = dest[0];
6829: dsp_core.registers[DSP_REG_A1] = dest[1];
6830: dsp_core.registers[DSP_REG_A0] = dest[2];
6831:
6832: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6833:
6834: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6835: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6836: }
6837:
6838: static void dsp_macr_p_y0_x0_b(void)
6839: {
6840: Uint32 source[3], dest[3];
6841: Uint16 newsr;
6842:
6843: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6844:
6845: dest[0] = dsp_core.registers[DSP_REG_B2];
6846: dest[1] = dsp_core.registers[DSP_REG_B1];
6847: dest[2] = dsp_core.registers[DSP_REG_B0];
6848: newsr = dsp_add56(source, dest);
6849:
6850: dsp_rnd56(dest);
6851:
6852: dsp_core.registers[DSP_REG_B2] = dest[0];
6853: dsp_core.registers[DSP_REG_B1] = dest[1];
6854: dsp_core.registers[DSP_REG_B0] = dest[2];
6855:
6856: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6857:
6858: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6859: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6860: }
6861:
6862: static void dsp_macr_m_y0_x0_b(void)
6863: {
6864: Uint32 source[3], dest[3];
6865: Uint16 newsr;
6866:
6867: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6868:
6869: dest[0] = dsp_core.registers[DSP_REG_B2];
6870: dest[1] = dsp_core.registers[DSP_REG_B1];
6871: dest[2] = dsp_core.registers[DSP_REG_B0];
6872: newsr = dsp_add56(source, dest);
6873:
6874: dsp_rnd56(dest);
6875:
6876: dsp_core.registers[DSP_REG_B2] = dest[0];
6877: dsp_core.registers[DSP_REG_B1] = dest[1];
6878: dsp_core.registers[DSP_REG_B0] = dest[2];
6879:
6880: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6881:
6882: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6883: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6884: }
6885:
6886: static void dsp_macr_p_x1_y0_a(void)
6887: {
6888: Uint32 source[3], dest[3];
6889: Uint16 newsr;
6890:
6891: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6892:
6893: dest[0] = dsp_core.registers[DSP_REG_A2];
6894: dest[1] = dsp_core.registers[DSP_REG_A1];
6895: dest[2] = dsp_core.registers[DSP_REG_A0];
6896: newsr = dsp_add56(source, dest);
6897:
6898: dsp_rnd56(dest);
6899:
6900: dsp_core.registers[DSP_REG_A2] = dest[0];
6901: dsp_core.registers[DSP_REG_A1] = dest[1];
6902: dsp_core.registers[DSP_REG_A0] = dest[2];
6903:
6904: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6905:
6906: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6907: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6908: }
6909:
6910: static void dsp_macr_m_x1_y0_a(void)
6911: {
6912: Uint32 source[3], dest[3];
6913: Uint16 newsr;
6914:
6915: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6916:
6917: dest[0] = dsp_core.registers[DSP_REG_A2];
6918: dest[1] = dsp_core.registers[DSP_REG_A1];
6919: dest[2] = dsp_core.registers[DSP_REG_A0];
6920: newsr = dsp_add56(source, dest);
6921:
6922: dsp_rnd56(dest);
6923:
6924: dsp_core.registers[DSP_REG_A2] = dest[0];
6925: dsp_core.registers[DSP_REG_A1] = dest[1];
6926: dsp_core.registers[DSP_REG_A0] = dest[2];
6927:
6928: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6929:
6930: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6931: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6932: }
6933:
6934: static void dsp_macr_p_x1_y0_b(void)
6935: {
6936: Uint32 source[3], dest[3];
6937: Uint16 newsr;
6938:
6939: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6940:
6941: dest[0] = dsp_core.registers[DSP_REG_B2];
6942: dest[1] = dsp_core.registers[DSP_REG_B1];
6943: dest[2] = dsp_core.registers[DSP_REG_B0];
6944: newsr = dsp_add56(source, dest);
6945:
1.1.1.10 root 6946: dsp_rnd56(dest);
6947:
1.1.1.6 root 6948: dsp_core.registers[DSP_REG_B2] = dest[0];
6949: dsp_core.registers[DSP_REG_B1] = dest[1];
6950: dsp_core.registers[DSP_REG_B0] = dest[2];
6951:
6952: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6953:
6954: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6955: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6956: }
6957:
6958: static void dsp_macr_m_x1_y0_b(void)
6959: {
6960: Uint32 source[3], dest[3];
6961: Uint16 newsr;
6962:
6963: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6964:
6965: dest[0] = dsp_core.registers[DSP_REG_B2];
6966: dest[1] = dsp_core.registers[DSP_REG_B1];
6967: dest[2] = dsp_core.registers[DSP_REG_B0];
6968: newsr = dsp_add56(source, dest);
6969:
6970: dsp_rnd56(dest);
6971:
6972: dsp_core.registers[DSP_REG_B2] = dest[0];
6973: dsp_core.registers[DSP_REG_B1] = dest[1];
6974: dsp_core.registers[DSP_REG_B0] = dest[2];
6975:
6976: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6977:
6978: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6979: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6980: }
6981:
6982: static void dsp_macr_p_y1_x1_a(void)
6983: {
6984: Uint32 source[3], dest[3];
6985: Uint16 newsr;
6986:
6987: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6988:
6989: dest[0] = dsp_core.registers[DSP_REG_A2];
6990: dest[1] = dsp_core.registers[DSP_REG_A1];
6991: dest[2] = dsp_core.registers[DSP_REG_A0];
6992: newsr = dsp_add56(source, dest);
6993:
6994: dsp_rnd56(dest);
6995:
6996: dsp_core.registers[DSP_REG_A2] = dest[0];
6997: dsp_core.registers[DSP_REG_A1] = dest[1];
6998: dsp_core.registers[DSP_REG_A0] = dest[2];
6999:
7000: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7001:
7002: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7003: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7004: }
7005:
7006: static void dsp_macr_m_y1_x1_a(void)
7007: {
7008: Uint32 source[3], dest[3];
7009: Uint16 newsr;
7010:
7011: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7012:
7013: dest[0] = dsp_core.registers[DSP_REG_A2];
7014: dest[1] = dsp_core.registers[DSP_REG_A1];
7015: dest[2] = dsp_core.registers[DSP_REG_A0];
7016: newsr = dsp_add56(source, dest);
7017:
7018: dsp_rnd56(dest);
7019:
7020: dsp_core.registers[DSP_REG_A2] = dest[0];
7021: dsp_core.registers[DSP_REG_A1] = dest[1];
7022: dsp_core.registers[DSP_REG_A0] = dest[2];
7023:
7024: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7025:
7026: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7027: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7028: }
7029:
7030: static void dsp_macr_p_y1_x1_b(void)
7031: {
7032: Uint32 source[3], dest[3];
7033: Uint16 newsr;
7034:
7035: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7036:
7037: dest[0] = dsp_core.registers[DSP_REG_B2];
7038: dest[1] = dsp_core.registers[DSP_REG_B1];
7039: dest[2] = dsp_core.registers[DSP_REG_B0];
7040: newsr = dsp_add56(source, dest);
7041:
7042: dsp_rnd56(dest);
7043:
7044: dsp_core.registers[DSP_REG_B2] = dest[0];
7045: dsp_core.registers[DSP_REG_B1] = dest[1];
7046: dsp_core.registers[DSP_REG_B0] = dest[2];
7047:
7048: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7049:
7050: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7051: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7052: }
7053:
7054: static void dsp_macr_m_y1_x1_b(void)
7055: {
7056: Uint32 source[3], dest[3];
7057: Uint16 newsr;
7058:
7059: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7060:
7061: dest[0] = dsp_core.registers[DSP_REG_B2];
7062: dest[1] = dsp_core.registers[DSP_REG_B1];
7063: dest[2] = dsp_core.registers[DSP_REG_B0];
7064: newsr = dsp_add56(source, dest);
7065:
7066: dsp_rnd56(dest);
7067:
7068: dsp_core.registers[DSP_REG_B2] = dest[0];
7069: dsp_core.registers[DSP_REG_B1] = dest[1];
7070: dsp_core.registers[DSP_REG_B0] = dest[2];
7071:
7072: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7073:
7074: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7075: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7076: }
7077:
7078:
7079: static void dsp_move(void)
7080: {
7081: /* move instruction inside alu opcodes
7082: taken care of by parallel move dispatcher */
7083: }
7084:
7085: static void dsp_mpy_p_x0_x0_a(void)
7086: {
7087: Uint32 source[3];
7088:
7089: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7090:
7091: dsp_core.registers[DSP_REG_A2] = source[0];
7092: dsp_core.registers[DSP_REG_A1] = source[1];
7093: dsp_core.registers[DSP_REG_A0] = source[2];
7094:
7095: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7096: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7097: }
7098:
7099: static void dsp_mpy_m_x0_x0_a(void)
7100: {
7101: Uint32 source[3];
7102:
7103: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7104:
7105: dsp_core.registers[DSP_REG_A2] = source[0];
7106: dsp_core.registers[DSP_REG_A1] = source[1];
7107: dsp_core.registers[DSP_REG_A0] = source[2];
7108:
7109: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7110: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7111: }
7112:
7113: static void dsp_mpy_p_x0_x0_b(void)
7114: {
7115: Uint32 source[3];
7116:
7117: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7118:
7119: dsp_core.registers[DSP_REG_B2] = source[0];
7120: dsp_core.registers[DSP_REG_B1] = source[1];
7121: dsp_core.registers[DSP_REG_B0] = source[2];
7122:
7123: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7124: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7125: }
7126:
7127: static void dsp_mpy_m_x0_x0_b(void)
7128: {
7129: Uint32 source[3];
7130:
7131:
7132: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7133:
7134: dsp_core.registers[DSP_REG_B2] = source[0];
7135: dsp_core.registers[DSP_REG_B1] = source[1];
7136: dsp_core.registers[DSP_REG_B0] = source[2];
7137:
7138: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7139: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7140: }
7141:
7142: static void dsp_mpy_p_y0_y0_a(void)
7143: {
7144: Uint32 source[3];
7145:
7146: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7147:
7148: dsp_core.registers[DSP_REG_A2] = source[0];
7149: dsp_core.registers[DSP_REG_A1] = source[1];
7150: dsp_core.registers[DSP_REG_A0] = source[2];
7151:
7152: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7153: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7154: }
7155:
7156: static void dsp_mpy_m_y0_y0_a(void)
7157: {
7158: Uint32 source[3];
7159:
7160: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7161:
7162: dsp_core.registers[DSP_REG_A2] = source[0];
7163: dsp_core.registers[DSP_REG_A1] = source[1];
7164: dsp_core.registers[DSP_REG_A0] = source[2];
7165:
7166: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7167: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7168: }
7169:
7170: static void dsp_mpy_p_y0_y0_b(void)
7171: {
7172: Uint32 source[3];
7173:
7174: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7175:
7176: dsp_core.registers[DSP_REG_B2] = source[0];
7177: dsp_core.registers[DSP_REG_B1] = source[1];
7178: dsp_core.registers[DSP_REG_B0] = source[2];
7179:
7180: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7181: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7182: }
7183:
7184: static void dsp_mpy_m_y0_y0_b(void)
7185: {
7186: Uint32 source[3];
7187:
7188: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7189:
7190: dsp_core.registers[DSP_REG_B2] = source[0];
7191: dsp_core.registers[DSP_REG_B1] = source[1];
7192: dsp_core.registers[DSP_REG_B0] = source[2];
7193:
7194: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7195: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7196: }
7197:
7198: static void dsp_mpy_p_x1_x0_a(void)
7199: {
7200: Uint32 source[3];
7201:
7202: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7203:
7204: dsp_core.registers[DSP_REG_A2] = source[0];
7205: dsp_core.registers[DSP_REG_A1] = source[1];
7206: dsp_core.registers[DSP_REG_A0] = source[2];
7207:
7208: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7209: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7210: }
7211:
7212: static void dsp_mpy_m_x1_x0_a(void)
7213: {
7214: Uint32 source[3];
7215:
7216: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7217:
7218: dsp_core.registers[DSP_REG_A2] = source[0];
7219: dsp_core.registers[DSP_REG_A1] = source[1];
7220: dsp_core.registers[DSP_REG_A0] = source[2];
7221:
7222: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7223: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7224: }
7225:
7226: static void dsp_mpy_p_x1_x0_b(void)
7227: {
7228: Uint32 source[3];
7229:
7230: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7231:
7232: dsp_core.registers[DSP_REG_B2] = source[0];
7233: dsp_core.registers[DSP_REG_B1] = source[1];
7234: dsp_core.registers[DSP_REG_B0] = source[2];
7235:
7236: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7237: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7238: }
7239:
7240: static void dsp_mpy_m_x1_x0_b(void)
7241: {
7242: Uint32 source[3];
7243:
7244: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7245:
7246: dsp_core.registers[DSP_REG_B2] = source[0];
7247: dsp_core.registers[DSP_REG_B1] = source[1];
7248: dsp_core.registers[DSP_REG_B0] = source[2];
7249:
7250: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7251: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7252: }
7253:
7254: static void dsp_mpy_p_y1_y0_a(void)
7255: {
7256: Uint32 source[3];
7257:
7258: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7259:
7260: dsp_core.registers[DSP_REG_A2] = source[0];
7261: dsp_core.registers[DSP_REG_A1] = source[1];
7262: dsp_core.registers[DSP_REG_A0] = source[2];
7263:
7264: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7265: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7266: }
7267:
7268: static void dsp_mpy_m_y1_y0_a(void)
7269: {
7270: Uint32 source[3];
7271:
7272: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7273:
7274: dsp_core.registers[DSP_REG_A2] = source[0];
7275: dsp_core.registers[DSP_REG_A1] = source[1];
7276: dsp_core.registers[DSP_REG_A0] = source[2];
7277:
7278: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7279: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7280: }
7281:
7282: static void dsp_mpy_p_y1_y0_b(void)
7283: {
7284: Uint32 source[3];
7285:
7286: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7287:
7288: dsp_core.registers[DSP_REG_B2] = source[0];
7289: dsp_core.registers[DSP_REG_B1] = source[1];
7290: dsp_core.registers[DSP_REG_B0] = source[2];
7291:
7292: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7293: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7294: }
7295:
7296: static void dsp_mpy_m_y1_y0_b(void)
7297: {
7298: Uint32 source[3];
7299:
7300: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7301:
7302: dsp_core.registers[DSP_REG_B2] = source[0];
7303: dsp_core.registers[DSP_REG_B1] = source[1];
7304: dsp_core.registers[DSP_REG_B0] = source[2];
7305:
7306: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7307: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7308: }
7309:
7310: static void dsp_mpy_p_x0_y1_a(void)
7311: {
7312: Uint32 source[3];
7313:
7314: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7315:
7316: dsp_core.registers[DSP_REG_A2] = source[0];
7317: dsp_core.registers[DSP_REG_A1] = source[1];
7318: dsp_core.registers[DSP_REG_A0] = source[2];
7319:
7320: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7321: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7322: }
7323:
7324: static void dsp_mpy_m_x0_y1_a(void)
7325: {
7326: Uint32 source[3];
7327:
7328: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7329:
7330: dsp_core.registers[DSP_REG_A2] = source[0];
7331: dsp_core.registers[DSP_REG_A1] = source[1];
7332: dsp_core.registers[DSP_REG_A0] = source[2];
7333:
7334: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7335: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7336: }
7337:
7338: static void dsp_mpy_p_x0_y1_b(void)
7339: {
7340: Uint32 source[3];
7341:
7342: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7343:
7344: dsp_core.registers[DSP_REG_B2] = source[0];
7345: dsp_core.registers[DSP_REG_B1] = source[1];
7346: dsp_core.registers[DSP_REG_B0] = source[2];
7347:
7348: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7349: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7350: }
7351:
7352: static void dsp_mpy_m_x0_y1_b(void)
7353: {
7354: Uint32 source[3];
7355:
7356: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7357:
7358: dsp_core.registers[DSP_REG_B2] = source[0];
7359: dsp_core.registers[DSP_REG_B1] = source[1];
7360: dsp_core.registers[DSP_REG_B0] = source[2];
7361:
7362: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7363: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7364: }
7365:
7366: static void dsp_mpy_p_y0_x0_a(void)
7367: {
7368: Uint32 source[3];
7369:
7370: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7371:
7372: dsp_core.registers[DSP_REG_A2] = source[0];
7373: dsp_core.registers[DSP_REG_A1] = source[1];
7374: dsp_core.registers[DSP_REG_A0] = source[2];
7375:
7376: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7377: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7378: }
7379:
7380: static void dsp_mpy_m_y0_x0_a(void)
7381: {
7382: Uint32 source[3];
7383:
7384: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7385:
7386: dsp_core.registers[DSP_REG_A2] = source[0];
7387: dsp_core.registers[DSP_REG_A1] = source[1];
7388: dsp_core.registers[DSP_REG_A0] = source[2];
7389:
7390: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7391: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7392: }
7393:
7394: static void dsp_mpy_p_y0_x0_b(void)
7395: {
7396: Uint32 source[3];
7397:
7398: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7399:
7400: dsp_core.registers[DSP_REG_B2] = source[0];
7401: dsp_core.registers[DSP_REG_B1] = source[1];
7402: dsp_core.registers[DSP_REG_B0] = source[2];
7403:
7404: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7405: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7406: }
7407:
7408: static void dsp_mpy_m_y0_x0_b(void)
7409: {
7410: Uint32 source[3];
7411:
7412: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7413:
7414: dsp_core.registers[DSP_REG_B2] = source[0];
7415: dsp_core.registers[DSP_REG_B1] = source[1];
7416: dsp_core.registers[DSP_REG_B0] = source[2];
7417:
7418: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7419: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7420: }
7421:
7422: static void dsp_mpy_p_x1_y0_a(void)
7423: {
7424: Uint32 source[3];
7425:
7426: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7427:
7428: dsp_core.registers[DSP_REG_A2] = source[0];
7429: dsp_core.registers[DSP_REG_A1] = source[1];
7430: dsp_core.registers[DSP_REG_A0] = source[2];
7431:
7432: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7433: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7434: }
7435:
7436: static void dsp_mpy_m_x1_y0_a(void)
7437: {
7438: Uint32 source[3];
7439:
7440: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7441:
7442: dsp_core.registers[DSP_REG_A2] = source[0];
7443: dsp_core.registers[DSP_REG_A1] = source[1];
7444: dsp_core.registers[DSP_REG_A0] = source[2];
7445:
7446: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7447: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7448: }
7449:
7450: static void dsp_mpy_p_x1_y0_b(void)
7451: {
7452: Uint32 source[3];
7453:
7454: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7455:
7456: dsp_core.registers[DSP_REG_B2] = source[0];
7457: dsp_core.registers[DSP_REG_B1] = source[1];
7458: dsp_core.registers[DSP_REG_B0] = source[2];
7459:
7460: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7461: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7462: }
7463:
7464: static void dsp_mpy_m_x1_y0_b(void)
7465: {
7466: Uint32 source[3];
7467:
7468: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7469:
7470: dsp_core.registers[DSP_REG_B2] = source[0];
7471: dsp_core.registers[DSP_REG_B1] = source[1];
7472: dsp_core.registers[DSP_REG_B0] = source[2];
7473:
7474: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7475: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7476: }
7477:
7478: static void dsp_mpy_p_y1_x1_a(void)
7479: {
7480: Uint32 source[3];
7481:
7482: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7483:
7484: dsp_core.registers[DSP_REG_A2] = source[0];
7485: dsp_core.registers[DSP_REG_A1] = source[1];
7486: dsp_core.registers[DSP_REG_A0] = source[2];
7487:
7488: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7489: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7490: }
7491:
7492: static void dsp_mpy_m_y1_x1_a(void)
7493: {
7494: Uint32 source[3];
7495:
7496: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7497:
7498: dsp_core.registers[DSP_REG_A2] = source[0];
7499: dsp_core.registers[DSP_REG_A1] = source[1];
7500: dsp_core.registers[DSP_REG_A0] = source[2];
7501:
7502: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7503: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7504: }
7505:
7506: static void dsp_mpy_p_y1_x1_b(void)
7507: {
7508: Uint32 source[3];
7509:
7510: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7511:
7512: dsp_core.registers[DSP_REG_B2] = source[0];
7513: dsp_core.registers[DSP_REG_B1] = source[1];
7514: dsp_core.registers[DSP_REG_B0] = source[2];
7515:
7516: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7517: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7518: }
7519:
7520: static void dsp_mpy_m_y1_x1_b(void)
7521: {
7522: Uint32 source[3];
7523:
7524: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7525:
7526: dsp_core.registers[DSP_REG_B2] = source[0];
7527: dsp_core.registers[DSP_REG_B1] = source[1];
7528: dsp_core.registers[DSP_REG_B0] = source[2];
7529:
7530: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7531: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7532: }
7533:
7534: static void dsp_mpyr_p_x0_x0_a(void)
7535: {
7536: Uint32 source[3];
7537:
7538: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7539: dsp_rnd56(source);
7540:
7541: dsp_core.registers[DSP_REG_A2] = source[0];
7542: dsp_core.registers[DSP_REG_A1] = source[1];
7543: dsp_core.registers[DSP_REG_A0] = source[2];
7544:
7545: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7546: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7547: }
7548:
7549: static void dsp_mpyr_m_x0_x0_a(void)
7550: {
7551: Uint32 source[3];
7552:
7553: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7554: dsp_rnd56(source);
7555:
7556: dsp_core.registers[DSP_REG_A2] = source[0];
7557: dsp_core.registers[DSP_REG_A1] = source[1];
7558: dsp_core.registers[DSP_REG_A0] = source[2];
7559:
7560: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7561: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7562: }
7563:
7564: static void dsp_mpyr_p_x0_x0_b(void)
7565: {
7566: Uint32 source[3];
7567:
7568: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7569: dsp_rnd56(source);
7570:
7571: dsp_core.registers[DSP_REG_B2] = source[0];
7572: dsp_core.registers[DSP_REG_B1] = source[1];
7573: dsp_core.registers[DSP_REG_B0] = source[2];
7574:
7575: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7576: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7577: }
7578:
7579: static void dsp_mpyr_m_x0_x0_b(void)
7580: {
7581: Uint32 source[3];
7582:
7583:
7584: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7585: dsp_rnd56(source);
7586:
7587: dsp_core.registers[DSP_REG_B2] = source[0];
7588: dsp_core.registers[DSP_REG_B1] = source[1];
7589: dsp_core.registers[DSP_REG_B0] = source[2];
7590:
7591: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7592: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7593: }
7594:
7595: static void dsp_mpyr_p_y0_y0_a(void)
7596: {
7597: Uint32 source[3];
7598:
7599: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7600: dsp_rnd56(source);
7601:
7602: dsp_core.registers[DSP_REG_A2] = source[0];
7603: dsp_core.registers[DSP_REG_A1] = source[1];
7604: dsp_core.registers[DSP_REG_A0] = source[2];
7605:
7606: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7607: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7608: }
7609:
7610: static void dsp_mpyr_m_y0_y0_a(void)
7611: {
7612: Uint32 source[3];
7613:
7614: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7615: dsp_rnd56(source);
7616:
7617: dsp_core.registers[DSP_REG_A2] = source[0];
7618: dsp_core.registers[DSP_REG_A1] = source[1];
7619: dsp_core.registers[DSP_REG_A0] = source[2];
7620:
7621: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7622: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7623: }
7624:
7625: static void dsp_mpyr_p_y0_y0_b(void)
7626: {
7627: Uint32 source[3];
7628:
7629: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7630: dsp_rnd56(source);
7631:
7632: dsp_core.registers[DSP_REG_B2] = source[0];
7633: dsp_core.registers[DSP_REG_B1] = source[1];
7634: dsp_core.registers[DSP_REG_B0] = source[2];
7635:
7636: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7637: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7638: }
7639:
7640: static void dsp_mpyr_m_y0_y0_b(void)
7641: {
7642: Uint32 source[3];
7643:
7644: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7645: dsp_rnd56(source);
7646:
7647: dsp_core.registers[DSP_REG_B2] = source[0];
7648: dsp_core.registers[DSP_REG_B1] = source[1];
7649: dsp_core.registers[DSP_REG_B0] = source[2];
7650:
7651: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7652: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7653: }
7654:
7655: static void dsp_mpyr_p_x1_x0_a(void)
7656: {
7657: Uint32 source[3];
7658:
7659: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7660: dsp_rnd56(source);
7661:
7662: dsp_core.registers[DSP_REG_A2] = source[0];
7663: dsp_core.registers[DSP_REG_A1] = source[1];
7664: dsp_core.registers[DSP_REG_A0] = source[2];
7665:
7666: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7667: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7668: }
7669:
7670: static void dsp_mpyr_m_x1_x0_a(void)
7671: {
7672: Uint32 source[3];
7673:
7674: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7675: dsp_rnd56(source);
7676:
7677: dsp_core.registers[DSP_REG_A2] = source[0];
7678: dsp_core.registers[DSP_REG_A1] = source[1];
7679: dsp_core.registers[DSP_REG_A0] = source[2];
7680:
7681: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7682: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7683: }
7684:
7685: static void dsp_mpyr_p_x1_x0_b(void)
7686: {
7687: Uint32 source[3];
7688:
7689: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7690: dsp_rnd56(source);
7691:
7692: dsp_core.registers[DSP_REG_B2] = source[0];
7693: dsp_core.registers[DSP_REG_B1] = source[1];
7694: dsp_core.registers[DSP_REG_B0] = source[2];
7695:
7696: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7697: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7698: }
7699:
7700: static void dsp_mpyr_m_x1_x0_b(void)
7701: {
7702: Uint32 source[3];
7703:
7704: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7705: dsp_rnd56(source);
7706:
7707: dsp_core.registers[DSP_REG_B2] = source[0];
7708: dsp_core.registers[DSP_REG_B1] = source[1];
7709: dsp_core.registers[DSP_REG_B0] = source[2];
7710:
7711: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7712: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7713: }
7714:
7715: static void dsp_mpyr_p_y1_y0_a(void)
7716: {
7717: Uint32 source[3];
7718:
7719: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7720: dsp_rnd56(source);
7721:
7722: dsp_core.registers[DSP_REG_A2] = source[0];
7723: dsp_core.registers[DSP_REG_A1] = source[1];
7724: dsp_core.registers[DSP_REG_A0] = source[2];
7725:
7726: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7727: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7728: }
7729:
7730: static void dsp_mpyr_m_y1_y0_a(void)
7731: {
7732: Uint32 source[3];
7733:
7734: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7735: dsp_rnd56(source);
7736:
7737: dsp_core.registers[DSP_REG_A2] = source[0];
7738: dsp_core.registers[DSP_REG_A1] = source[1];
7739: dsp_core.registers[DSP_REG_A0] = source[2];
7740:
7741: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7742: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7743: }
7744:
7745: static void dsp_mpyr_p_y1_y0_b(void)
7746: {
7747: Uint32 source[3];
7748:
7749: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7750: dsp_rnd56(source);
7751:
7752: dsp_core.registers[DSP_REG_B2] = source[0];
7753: dsp_core.registers[DSP_REG_B1] = source[1];
7754: dsp_core.registers[DSP_REG_B0] = source[2];
7755:
7756: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7757: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7758: }
7759:
7760: static void dsp_mpyr_m_y1_y0_b(void)
7761: {
7762: Uint32 source[3];
7763:
7764: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7765: dsp_rnd56(source);
7766:
7767: dsp_core.registers[DSP_REG_B2] = source[0];
7768: dsp_core.registers[DSP_REG_B1] = source[1];
7769: dsp_core.registers[DSP_REG_B0] = source[2];
7770:
7771: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7772: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7773: }
7774:
7775: static void dsp_mpyr_p_x0_y1_a(void)
7776: {
7777: Uint32 source[3];
7778:
7779: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7780: dsp_rnd56(source);
7781:
7782: dsp_core.registers[DSP_REG_A2] = source[0];
7783: dsp_core.registers[DSP_REG_A1] = source[1];
7784: dsp_core.registers[DSP_REG_A0] = source[2];
7785:
7786: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7787: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7788: }
7789:
7790: static void dsp_mpyr_m_x0_y1_a(void)
7791: {
7792: Uint32 source[3];
7793:
7794: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7795: dsp_rnd56(source);
7796:
7797: dsp_core.registers[DSP_REG_A2] = source[0];
7798: dsp_core.registers[DSP_REG_A1] = source[1];
7799: dsp_core.registers[DSP_REG_A0] = source[2];
7800:
7801: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7802: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7803: }
7804:
7805: static void dsp_mpyr_p_x0_y1_b(void)
7806: {
7807: Uint32 source[3];
7808:
7809: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7810: dsp_rnd56(source);
7811:
7812: dsp_core.registers[DSP_REG_B2] = source[0];
7813: dsp_core.registers[DSP_REG_B1] = source[1];
7814: dsp_core.registers[DSP_REG_B0] = source[2];
7815:
7816: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7817: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7818: }
7819:
7820: static void dsp_mpyr_m_x0_y1_b(void)
7821: {
7822: Uint32 source[3];
7823:
7824: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7825: dsp_rnd56(source);
7826:
7827: dsp_core.registers[DSP_REG_B2] = source[0];
7828: dsp_core.registers[DSP_REG_B1] = source[1];
7829: dsp_core.registers[DSP_REG_B0] = source[2];
7830:
7831: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7832: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7833: }
7834:
7835: static void dsp_mpyr_p_y0_x0_a(void)
7836: {
7837: Uint32 source[3];
7838:
7839: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7840: dsp_rnd56(source);
7841:
7842: dsp_core.registers[DSP_REG_A2] = source[0];
7843: dsp_core.registers[DSP_REG_A1] = source[1];
7844: dsp_core.registers[DSP_REG_A0] = source[2];
7845:
7846: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7847: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7848: }
7849:
7850: static void dsp_mpyr_m_y0_x0_a(void)
7851: {
7852: Uint32 source[3];
7853:
7854: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7855: dsp_rnd56(source);
7856:
7857: dsp_core.registers[DSP_REG_A2] = source[0];
7858: dsp_core.registers[DSP_REG_A1] = source[1];
7859: dsp_core.registers[DSP_REG_A0] = source[2];
7860:
7861: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7862: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7863: }
7864:
7865: static void dsp_mpyr_p_y0_x0_b(void)
7866: {
7867: Uint32 source[3];
7868:
7869: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7870: dsp_rnd56(source);
7871:
7872: dsp_core.registers[DSP_REG_B2] = source[0];
7873: dsp_core.registers[DSP_REG_B1] = source[1];
7874: dsp_core.registers[DSP_REG_B0] = source[2];
7875:
7876: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7877: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7878: }
7879:
7880: static void dsp_mpyr_m_y0_x0_b(void)
7881: {
7882: Uint32 source[3];
7883:
7884: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7885: dsp_rnd56(source);
7886:
7887: dsp_core.registers[DSP_REG_B2] = source[0];
7888: dsp_core.registers[DSP_REG_B1] = source[1];
7889: dsp_core.registers[DSP_REG_B0] = source[2];
7890:
7891: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7892: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7893: }
7894:
7895: static void dsp_mpyr_p_x1_y0_a(void)
7896: {
7897: Uint32 source[3];
7898:
7899: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7900: dsp_rnd56(source);
7901:
7902: dsp_core.registers[DSP_REG_A2] = source[0];
7903: dsp_core.registers[DSP_REG_A1] = source[1];
7904: dsp_core.registers[DSP_REG_A0] = source[2];
7905:
7906: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7907: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7908: }
7909:
7910: static void dsp_mpyr_m_x1_y0_a(void)
7911: {
7912: Uint32 source[3];
7913:
7914: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7915: dsp_rnd56(source);
7916:
7917: dsp_core.registers[DSP_REG_A2] = source[0];
7918: dsp_core.registers[DSP_REG_A1] = source[1];
7919: dsp_core.registers[DSP_REG_A0] = source[2];
7920:
7921: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7922: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7923: }
7924:
7925: static void dsp_mpyr_p_x1_y0_b(void)
7926: {
7927: Uint32 source[3];
7928:
7929: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7930: dsp_rnd56(source);
7931:
7932: dsp_core.registers[DSP_REG_B2] = source[0];
7933: dsp_core.registers[DSP_REG_B1] = source[1];
7934: dsp_core.registers[DSP_REG_B0] = source[2];
7935:
7936: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7937: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7938: }
7939:
7940: static void dsp_mpyr_m_x1_y0_b(void)
7941: {
7942: Uint32 source[3];
7943:
7944: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7945: dsp_rnd56(source);
7946:
7947: dsp_core.registers[DSP_REG_B2] = source[0];
7948: dsp_core.registers[DSP_REG_B1] = source[1];
7949: dsp_core.registers[DSP_REG_B0] = source[2];
7950:
7951: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7952: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7953: }
7954:
7955: static void dsp_mpyr_p_y1_x1_a(void)
7956: {
7957: Uint32 source[3];
7958:
7959: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7960: dsp_rnd56(source);
7961:
7962: dsp_core.registers[DSP_REG_A2] = source[0];
7963: dsp_core.registers[DSP_REG_A1] = source[1];
7964: dsp_core.registers[DSP_REG_A0] = source[2];
7965:
7966: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7967: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7968: }
7969:
7970: static void dsp_mpyr_m_y1_x1_a(void)
7971: {
7972: Uint32 source[3];
7973:
7974: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7975: dsp_rnd56(source);
7976:
7977: dsp_core.registers[DSP_REG_A2] = source[0];
7978: dsp_core.registers[DSP_REG_A1] = source[1];
7979: dsp_core.registers[DSP_REG_A0] = source[2];
7980:
7981: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7982: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7983: }
7984:
7985: static void dsp_mpyr_p_y1_x1_b(void)
7986: {
7987: Uint32 source[3];
7988:
7989: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7990: dsp_rnd56(source);
7991:
7992: dsp_core.registers[DSP_REG_B2] = source[0];
7993: dsp_core.registers[DSP_REG_B1] = source[1];
7994: dsp_core.registers[DSP_REG_B0] = source[2];
7995:
7996: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7997: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7998: }
7999:
8000: static void dsp_mpyr_m_y1_x1_b(void)
8001: {
8002: Uint32 source[3];
8003:
8004: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
8005: dsp_rnd56(source);
8006:
8007: dsp_core.registers[DSP_REG_B2] = source[0];
8008: dsp_core.registers[DSP_REG_B1] = source[1];
8009: dsp_core.registers[DSP_REG_B0] = source[2];
8010:
8011: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8012: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8013: }
8014:
8015: static void dsp_neg_a(void)
8016: {
8017: Uint32 source[3], dest[3], overflowed;
8018:
8019: source[0] = dsp_core.registers[DSP_REG_A2];
8020: source[1] = dsp_core.registers[DSP_REG_A1];
8021: source[2] = dsp_core.registers[DSP_REG_A0];
8022:
8023: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8024:
8025: dest[0] = dest[1] = dest[2] = 0;
8026:
8027: dsp_sub56(source, dest);
8028:
8029: dsp_core.registers[DSP_REG_A2] = dest[0];
8030: dsp_core.registers[DSP_REG_A1] = dest[1];
8031: dsp_core.registers[DSP_REG_A0] = dest[2];
8032:
8033: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8034: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8035:
8036: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8037: }
8038:
8039: static void dsp_neg_b(void)
8040: {
8041: Uint32 source[3], dest[3], overflowed;
8042:
8043: source[0] = dsp_core.registers[DSP_REG_B2];
8044: source[1] = dsp_core.registers[DSP_REG_B1];
8045: source[2] = dsp_core.registers[DSP_REG_B0];
8046:
8047: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8048:
8049: dest[0] = dest[1] = dest[2] = 0;
8050:
8051: dsp_sub56(source, dest);
8052:
8053: dsp_core.registers[DSP_REG_B2] = dest[0];
8054: dsp_core.registers[DSP_REG_B1] = dest[1];
8055: dsp_core.registers[DSP_REG_B0] = dest[2];
8056:
8057: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8058: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8059:
8060: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8061: }
8062:
8063: static void dsp_nop(void)
8064: {
8065: }
8066:
8067: static void dsp_not_a(void)
8068: {
8069: dsp_core.registers[DSP_REG_A1] = ~dsp_core.registers[DSP_REG_A1];
8070: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8071:
8072: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8073: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8074: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8075: }
8076:
8077: static void dsp_not_b(void)
8078: {
8079: dsp_core.registers[DSP_REG_B1] = ~dsp_core.registers[DSP_REG_B1];
8080: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8081:
8082: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8083: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8084: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8085: }
8086:
8087: static void dsp_or_x0_a(void)
8088: {
8089: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X0];
8090: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8091:
8092: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8093: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8094: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8095: }
8096:
8097: static void dsp_or_x0_b(void)
8098: {
8099: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X0];
8100: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8101:
8102: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8103: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8104: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8105: }
8106:
8107: static void dsp_or_y0_a(void)
8108: {
8109: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y0];
8110: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8111:
8112: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8113: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8114: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8115: }
8116:
8117: static void dsp_or_y0_b(void)
8118: {
8119: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y0];
8120: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8121:
8122: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8123: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8124: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8125: }
8126:
8127: static void dsp_or_x1_a(void)
8128: {
8129: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X1];
8130: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8131:
8132: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8133: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8134: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8135: }
8136:
8137: static void dsp_or_x1_b(void)
8138: {
8139: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X1];
8140: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8141:
8142: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8143: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8144: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8145: }
8146:
8147: static void dsp_or_y1_a(void)
8148: {
8149: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y1];
8150: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8151:
8152: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8153: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8154: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8155: }
8156:
8157: static void dsp_or_y1_b(void)
8158: {
8159: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y1];
8160: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8161:
8162: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8163: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8164: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8165: }
8166:
8167: static void dsp_rnd_a(void)
8168: {
8169: Uint32 dest[3];
8170:
8171: dest[0] = dsp_core.registers[DSP_REG_A2];
8172: dest[1] = dsp_core.registers[DSP_REG_A1];
8173: dest[2] = dsp_core.registers[DSP_REG_A0];
8174:
8175: dsp_rnd56(dest);
8176:
8177: dsp_core.registers[DSP_REG_A2] = dest[0];
8178: dsp_core.registers[DSP_REG_A1] = dest[1];
8179: dsp_core.registers[DSP_REG_A0] = dest[2];
8180:
8181: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8182: }
8183:
8184: static void dsp_rnd_b(void)
8185: {
8186: Uint32 dest[3];
8187:
8188: dest[0] = dsp_core.registers[DSP_REG_B2];
8189: dest[1] = dsp_core.registers[DSP_REG_B1];
8190: dest[2] = dsp_core.registers[DSP_REG_B0];
8191:
8192: dsp_rnd56(dest);
8193:
8194: dsp_core.registers[DSP_REG_B2] = dest[0];
8195: dsp_core.registers[DSP_REG_B1] = dest[1];
8196: dsp_core.registers[DSP_REG_B0] = dest[2];
8197:
8198: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8199: }
8200:
8201: static void dsp_rol_a(void)
8202: {
8203: Uint32 newcarry;
8204:
8205: newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
8206:
8207: dsp_core.registers[DSP_REG_A1] <<= 1;
8208: dsp_core.registers[DSP_REG_A1] |= newcarry;
8209: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
8210:
8211: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8212: dsp_core.registers[DSP_REG_SR] |= newcarry;
8213: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8214: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8215: }
8216:
8217: static void dsp_rol_b(void)
8218: {
8219: Uint32 newcarry;
8220:
8221: newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
8222:
8223: dsp_core.registers[DSP_REG_B1] <<= 1;
8224: dsp_core.registers[DSP_REG_B1] |= newcarry;
8225: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
8226:
8227: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8228: dsp_core.registers[DSP_REG_SR] |= newcarry;
8229: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8230: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8231: }
8232:
8233: static void dsp_ror_a(void)
8234: {
8235: Uint32 newcarry;
8236:
8237: newcarry = dsp_core.registers[DSP_REG_A1] & 1;
8238:
8239: dsp_core.registers[DSP_REG_A1] >>= 1;
8240: dsp_core.registers[DSP_REG_A1] |= newcarry<<23;
8241:
8242: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8243: dsp_core.registers[DSP_REG_SR] |= newcarry;
8244: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8245: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8246: }
8247:
8248: static void dsp_ror_b(void)
8249: {
8250: Uint32 newcarry;
8251:
8252: newcarry = dsp_core.registers[DSP_REG_B1] & 1;
8253:
8254: dsp_core.registers[DSP_REG_B1] >>= 1;
8255: dsp_core.registers[DSP_REG_B1] |= newcarry<<23;
8256:
8257: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8258: dsp_core.registers[DSP_REG_SR] |= newcarry;
8259: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8260: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8261: }
8262:
8263: static void dsp_sbc_x_a(void)
8264: {
8265: Uint32 source[3], dest[3], curcarry;
8266: Uint16 newsr;
8267:
8268: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8269:
8270: dest[2] = dsp_core.registers[DSP_REG_A0];
8271: dest[1] = dsp_core.registers[DSP_REG_A1];
8272: dest[0] = dsp_core.registers[DSP_REG_A2];
8273:
8274: source[2] = dsp_core.registers[DSP_REG_X0];
8275: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8276: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8277:
8278: newsr = dsp_sub56(source, dest);
1.1.1.11! root 8279:
1.1.1.6 root 8280: if (curcarry) {
8281: source[0]=0; source[1]=0; source[2]=1;
8282: newsr |= dsp_sub56(source, dest);
8283: }
8284:
8285: dsp_core.registers[DSP_REG_A2] = dest[0];
8286: dsp_core.registers[DSP_REG_A1] = dest[1];
8287: dsp_core.registers[DSP_REG_A0] = dest[2];
8288:
8289: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8290:
8291: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8292: dsp_core.registers[DSP_REG_SR] |= newsr;
8293: }
8294:
8295: static void dsp_sbc_x_b(void)
8296: {
8297: Uint32 source[3], dest[3], curcarry;
8298: Uint16 newsr;
8299:
8300: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8301:
8302: dest[2] = dsp_core.registers[DSP_REG_B0];
8303: dest[1] = dsp_core.registers[DSP_REG_B1];
8304: dest[0] = dsp_core.registers[DSP_REG_B2];
8305:
8306: source[2] = dsp_core.registers[DSP_REG_X0];
8307: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8308: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8309:
8310: newsr = dsp_sub56(source, dest);
1.1.1.11! root 8311:
1.1.1.6 root 8312: if (curcarry) {
8313: source[0]=0; source[1]=0; source[2]=1;
8314: newsr |= dsp_sub56(source, dest);
8315: }
8316:
8317: dsp_core.registers[DSP_REG_B2] = dest[0];
8318: dsp_core.registers[DSP_REG_B1] = dest[1];
8319: dsp_core.registers[DSP_REG_B0] = dest[2];
8320:
8321: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8322:
8323: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8324: dsp_core.registers[DSP_REG_SR] |= newsr;
8325: }
8326:
8327: static void dsp_sbc_y_a(void)
8328: {
8329: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 8330: Uint16 newsr;
1.1 root 8331:
1.1.1.6 root 8332: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8333:
8334: dest[2] = dsp_core.registers[DSP_REG_A0];
8335: dest[1] = dsp_core.registers[DSP_REG_A1];
8336: dest[0] = dsp_core.registers[DSP_REG_A2];
8337:
8338: source[2] = dsp_core.registers[DSP_REG_Y0];
8339: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8340: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8341:
8342: newsr = dsp_sub56(source, dest);
1.1.1.11! root 8343:
1.1.1.6 root 8344: if (curcarry) {
8345: source[0]=0; source[1]=0; source[2]=1;
8346: newsr |= dsp_sub56(source, dest);
8347: }
8348:
8349: dsp_core.registers[DSP_REG_A2] = dest[0];
8350: dsp_core.registers[DSP_REG_A1] = dest[1];
8351: dsp_core.registers[DSP_REG_A0] = dest[2];
8352:
8353: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8354:
8355: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8356: dsp_core.registers[DSP_REG_SR] |= newsr;
8357: }
8358:
8359: static void dsp_sbc_y_b(void)
8360: {
8361: Uint32 source[3], dest[3], curcarry;
8362: Uint16 newsr;
8363:
8364: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8365:
8366: dest[2] = dsp_core.registers[DSP_REG_B0];
8367: dest[1] = dsp_core.registers[DSP_REG_B1];
8368: dest[0] = dsp_core.registers[DSP_REG_B2];
8369:
8370: source[2] = dsp_core.registers[DSP_REG_Y0];
8371: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8372: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8373:
8374: newsr = dsp_sub56(source, dest);
1.1.1.11! root 8375:
1.1.1.6 root 8376: if (curcarry) {
8377: source[0]=0; source[1]=0; source[2]=1;
8378: newsr |= dsp_sub56(source, dest);
1.1 root 8379: }
8380:
1.1.1.6 root 8381: dsp_core.registers[DSP_REG_B2] = dest[0];
8382: dsp_core.registers[DSP_REG_B1] = dest[1];
8383: dsp_core.registers[DSP_REG_B0] = dest[2];
8384:
8385: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8386:
8387: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8388: dsp_core.registers[DSP_REG_SR] |= newsr;
8389: }
8390:
8391: static void dsp_sub_b_a(void)
8392: {
8393: Uint32 source[3], dest[3];
8394: Uint16 newsr;
8395:
8396: dest[2] = dsp_core.registers[DSP_REG_A0];
8397: dest[1] = dsp_core.registers[DSP_REG_A1];
8398: dest[0] = dsp_core.registers[DSP_REG_A2];
8399:
8400: source[2] = dsp_core.registers[DSP_REG_B0];
8401: source[1] = dsp_core.registers[DSP_REG_B1];
8402: source[0] = dsp_core.registers[DSP_REG_B2];
8403:
1.1 root 8404: newsr = dsp_sub56(source, dest);
8405:
1.1.1.6 root 8406: dsp_core.registers[DSP_REG_A2] = dest[0];
8407: dsp_core.registers[DSP_REG_A1] = dest[1];
8408: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8409:
1.1.1.6 root 8410: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8411:
1.1.1.6 root 8412: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8413: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8414: }
8415:
1.1.1.6 root 8416: static void dsp_sub_a_b(void)
1.1 root 8417: {
1.1.1.6 root 8418: Uint32 source[3], dest[3];
1.1.1.2 root 8419: Uint16 newsr;
1.1 root 8420:
1.1.1.6 root 8421: dest[2] = dsp_core.registers[DSP_REG_B0];
8422: dest[1] = dsp_core.registers[DSP_REG_B1];
8423: dest[0] = dsp_core.registers[DSP_REG_B2];
8424:
8425: source[2] = dsp_core.registers[DSP_REG_A0];
8426: source[1] = dsp_core.registers[DSP_REG_A1];
8427: source[0] = dsp_core.registers[DSP_REG_A2];
8428:
8429: newsr = dsp_sub56(source, dest);
8430:
8431: dsp_core.registers[DSP_REG_B2] = dest[0];
8432: dsp_core.registers[DSP_REG_B1] = dest[1];
8433: dsp_core.registers[DSP_REG_B0] = dest[2];
8434:
8435: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8436:
8437: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8438: dsp_core.registers[DSP_REG_SR] |= newsr;
8439: }
8440:
8441: static void dsp_sub_x_a(void)
8442: {
8443: Uint32 source[3], dest[3];
8444: Uint16 newsr;
8445:
8446: dest[2] = dsp_core.registers[DSP_REG_A0];
8447: dest[1] = dsp_core.registers[DSP_REG_A1];
8448: dest[0] = dsp_core.registers[DSP_REG_A2];
8449:
8450: source[2] = dsp_core.registers[DSP_REG_X0];
8451: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8452: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8453:
8454: newsr = dsp_sub56(source, dest);
8455:
8456: dsp_core.registers[DSP_REG_A2] = dest[0];
8457: dsp_core.registers[DSP_REG_A1] = dest[1];
8458: dsp_core.registers[DSP_REG_A0] = dest[2];
8459:
8460: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8461:
8462: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8463: dsp_core.registers[DSP_REG_SR] |= newsr;
8464: }
8465:
8466: static void dsp_sub_x_b(void)
8467: {
8468: Uint32 source[3], dest[3];
8469: Uint16 newsr;
8470:
8471: dest[2] = dsp_core.registers[DSP_REG_B0];
8472: dest[1] = dsp_core.registers[DSP_REG_B1];
8473: dest[0] = dsp_core.registers[DSP_REG_B2];
8474:
8475: source[2] = dsp_core.registers[DSP_REG_X0];
8476: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8477: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8478:
8479: newsr = dsp_sub56(source, dest);
8480:
8481: dsp_core.registers[DSP_REG_B2] = dest[0];
8482: dsp_core.registers[DSP_REG_B1] = dest[1];
8483: dsp_core.registers[DSP_REG_B0] = dest[2];
8484:
8485: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8486:
8487: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8488: dsp_core.registers[DSP_REG_SR] |= newsr;
8489: }
8490:
8491: static void dsp_sub_y_a(void)
8492: {
8493: Uint32 source[3], dest[3];
8494: Uint16 newsr;
8495:
8496: dest[2] = dsp_core.registers[DSP_REG_A0];
8497: dest[1] = dsp_core.registers[DSP_REG_A1];
8498: dest[0] = dsp_core.registers[DSP_REG_A2];
8499:
8500: source[2] = dsp_core.registers[DSP_REG_Y0];
8501: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8502: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8503:
8504: newsr = dsp_sub56(source, dest);
8505:
8506: dsp_core.registers[DSP_REG_A2] = dest[0];
8507: dsp_core.registers[DSP_REG_A1] = dest[1];
8508: dsp_core.registers[DSP_REG_A0] = dest[2];
8509:
8510: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8511:
8512: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8513: dsp_core.registers[DSP_REG_SR] |= newsr;
8514: }
8515:
8516: static void dsp_sub_y_b(void)
8517: {
8518: Uint32 source[3], dest[3];
8519: Uint16 newsr;
8520:
8521: dest[2] = dsp_core.registers[DSP_REG_B0];
8522: dest[1] = dsp_core.registers[DSP_REG_B1];
8523: dest[0] = dsp_core.registers[DSP_REG_B2];
8524:
8525: source[2] = dsp_core.registers[DSP_REG_Y0];
8526: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8527: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8528:
8529: newsr = dsp_sub56(source, dest);
8530:
8531: dsp_core.registers[DSP_REG_B2] = dest[0];
8532: dsp_core.registers[DSP_REG_B1] = dest[1];
8533: dsp_core.registers[DSP_REG_B0] = dest[2];
8534:
8535: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8536:
8537: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8538: dsp_core.registers[DSP_REG_SR] |= newsr;
8539: }
8540:
8541: static void dsp_sub_x0_a(void)
8542: {
8543: Uint32 source[3], dest[3];
8544: Uint16 newsr;
8545:
8546: dest[2] = dsp_core.registers[DSP_REG_A0];
8547: dest[1] = dsp_core.registers[DSP_REG_A1];
8548: dest[0] = dsp_core.registers[DSP_REG_A2];
8549:
8550: source[2] = 0;
8551: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 8552: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8553:
8554: newsr = dsp_sub56(source, dest);
8555:
8556: dsp_core.registers[DSP_REG_A2] = dest[0];
8557: dsp_core.registers[DSP_REG_A1] = dest[1];
8558: dsp_core.registers[DSP_REG_A0] = dest[2];
8559:
8560: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8561:
8562: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8563: dsp_core.registers[DSP_REG_SR] |= newsr;
8564: }
8565:
8566: static void dsp_sub_x0_b(void)
8567: {
8568: Uint32 source[3], dest[3];
8569: Uint16 newsr;
8570:
8571: dest[2] = dsp_core.registers[DSP_REG_B0];
8572: dest[1] = dsp_core.registers[DSP_REG_B1];
8573: dest[0] = dsp_core.registers[DSP_REG_B2];
8574:
8575: source[2] = 0;
8576: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 8577: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8578:
8579: newsr = dsp_sub56(source, dest);
8580:
8581: dsp_core.registers[DSP_REG_B2] = dest[0];
8582: dsp_core.registers[DSP_REG_B1] = dest[1];
8583: dsp_core.registers[DSP_REG_B0] = dest[2];
8584:
8585: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8586:
8587: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8588: dsp_core.registers[DSP_REG_SR] |= newsr;
8589: }
8590:
8591: static void dsp_sub_y0_a(void)
8592: {
8593: Uint32 source[3], dest[3];
8594: Uint16 newsr;
8595:
8596: dest[2] = dsp_core.registers[DSP_REG_A0];
8597: dest[1] = dsp_core.registers[DSP_REG_A1];
8598: dest[0] = dsp_core.registers[DSP_REG_A2];
8599:
8600: source[2] = 0;
8601: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 8602: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8603:
8604: newsr = dsp_sub56(source, dest);
1.1 root 8605:
1.1.1.6 root 8606: dsp_core.registers[DSP_REG_A2] = dest[0];
8607: dsp_core.registers[DSP_REG_A1] = dest[1];
8608: dsp_core.registers[DSP_REG_A0] = dest[2];
8609:
8610: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8611:
8612: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8613: dsp_core.registers[DSP_REG_SR] |= newsr;
8614: }
8615:
8616: static void dsp_sub_y0_b(void)
8617: {
8618: Uint32 source[3], dest[3];
8619: Uint16 newsr;
8620:
8621: dest[2] = dsp_core.registers[DSP_REG_B0];
8622: dest[1] = dsp_core.registers[DSP_REG_B1];
8623: dest[0] = dsp_core.registers[DSP_REG_B2];
8624:
8625: source[2] = 0;
8626: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 8627: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8628:
8629: newsr = dsp_sub56(source, dest);
8630:
8631: dsp_core.registers[DSP_REG_B2] = dest[0];
8632: dsp_core.registers[DSP_REG_B1] = dest[1];
8633: dsp_core.registers[DSP_REG_B0] = dest[2];
8634:
8635: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8636:
8637: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8638: dsp_core.registers[DSP_REG_SR] |= newsr;
8639: }
8640:
8641: static void dsp_sub_x1_a(void)
8642: {
8643: Uint32 source[3], dest[3];
8644: Uint16 newsr;
8645:
8646: dest[2] = dsp_core.registers[DSP_REG_A0];
8647: dest[1] = dsp_core.registers[DSP_REG_A1];
8648: dest[0] = dsp_core.registers[DSP_REG_A2];
8649:
8650: source[2] = 0;
8651: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8652: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8653:
8654: newsr = dsp_sub56(source, dest);
8655:
8656: dsp_core.registers[DSP_REG_A2] = dest[0];
8657: dsp_core.registers[DSP_REG_A1] = dest[1];
8658: dsp_core.registers[DSP_REG_A0] = dest[2];
8659:
8660: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8661:
8662: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8663: dsp_core.registers[DSP_REG_SR] |= newsr;
8664: }
8665:
8666: static void dsp_sub_x1_b(void)
8667: {
8668: Uint32 source[3], dest[3];
8669: Uint16 newsr;
8670:
8671: dest[2] = dsp_core.registers[DSP_REG_B0];
8672: dest[1] = dsp_core.registers[DSP_REG_B1];
8673: dest[0] = dsp_core.registers[DSP_REG_B2];
8674:
8675: source[2] = 0;
8676: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8677: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8678:
8679: newsr = dsp_sub56(source, dest);
8680:
8681: dsp_core.registers[DSP_REG_B2] = dest[0];
8682: dsp_core.registers[DSP_REG_B1] = dest[1];
8683: dsp_core.registers[DSP_REG_B0] = dest[2];
8684:
8685: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8686:
8687: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8688: dsp_core.registers[DSP_REG_SR] |= newsr;
8689: }
8690:
8691: static void dsp_sub_y1_a(void)
8692: {
8693: Uint32 source[3], dest[3];
8694: Uint16 newsr;
8695:
8696: dest[2] = dsp_core.registers[DSP_REG_A0];
8697: dest[1] = dsp_core.registers[DSP_REG_A1];
8698: dest[0] = dsp_core.registers[DSP_REG_A2];
8699:
8700: source[2] = 0;
8701: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8702: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8703:
8704: newsr = dsp_sub56(source, dest);
8705:
8706: dsp_core.registers[DSP_REG_A2] = dest[0];
8707: dsp_core.registers[DSP_REG_A1] = dest[1];
8708: dsp_core.registers[DSP_REG_A0] = dest[2];
8709:
8710: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8711:
8712: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8713: dsp_core.registers[DSP_REG_SR] |= newsr;
8714: }
8715:
8716: static void dsp_sub_y1_b(void)
8717: {
8718: Uint32 source[3], dest[3];
8719: Uint16 newsr;
8720:
8721: dest[2] = dsp_core.registers[DSP_REG_B0];
8722: dest[1] = dsp_core.registers[DSP_REG_B1];
8723: dest[0] = dsp_core.registers[DSP_REG_B2];
8724:
8725: source[2] = 0;
8726: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8727: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8728:
8729: newsr = dsp_sub56(source, dest);
8730:
8731: dsp_core.registers[DSP_REG_B2] = dest[0];
8732: dsp_core.registers[DSP_REG_B1] = dest[1];
8733: dsp_core.registers[DSP_REG_B0] = dest[2];
8734:
8735: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8736:
8737: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8738: dsp_core.registers[DSP_REG_SR] |= newsr;
8739: }
8740:
8741: static void dsp_subl_a(void)
8742: {
8743: Uint32 source[3], dest[3];
8744: Uint16 newsr;
8745:
8746: dest[0] = dsp_core.registers[DSP_REG_A2];
8747: dest[1] = dsp_core.registers[DSP_REG_A1];
8748: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 8749: newsr = dsp_asl56(dest);
8750:
1.1.1.6 root 8751: source[0] = dsp_core.registers[DSP_REG_B2];
8752: source[1] = dsp_core.registers[DSP_REG_B1];
8753: source[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 8754: newsr |= dsp_sub56(source, dest);
8755:
1.1.1.6 root 8756: dsp_core.registers[DSP_REG_A2] = dest[0];
8757: dsp_core.registers[DSP_REG_A1] = dest[1];
8758: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8759:
1.1.1.6 root 8760: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8761:
1.1.1.6 root 8762: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8763: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8764: }
8765:
1.1.1.6 root 8766: static void dsp_subl_b(void)
1.1 root 8767: {
1.1.1.6 root 8768: Uint32 source[3], dest[3];
1.1.1.2 root 8769: Uint16 newsr;
1.1 root 8770:
1.1.1.6 root 8771: dest[0] = dsp_core.registers[DSP_REG_B2];
8772: dest[1] = dsp_core.registers[DSP_REG_B1];
8773: dest[2] = dsp_core.registers[DSP_REG_B0];
8774: newsr = dsp_asl56(dest);
1.1 root 8775:
1.1.1.6 root 8776: source[0] = dsp_core.registers[DSP_REG_A2];
8777: source[1] = dsp_core.registers[DSP_REG_A1];
8778: source[2] = dsp_core.registers[DSP_REG_A0];
8779: newsr |= dsp_sub56(source, dest);
8780:
8781: dsp_core.registers[DSP_REG_B2] = dest[0];
8782: dsp_core.registers[DSP_REG_B1] = dest[1];
8783: dsp_core.registers[DSP_REG_B0] = dest[2];
8784:
8785: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8786:
8787: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8788: dsp_core.registers[DSP_REG_SR] |= newsr;
8789: }
8790:
8791: static void dsp_subr_a(void)
8792: {
8793: Uint32 source[3], dest[3];
8794: Uint16 newsr;
8795:
8796: dest[0] = dsp_core.registers[DSP_REG_A2];
8797: dest[1] = dsp_core.registers[DSP_REG_A1];
8798: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1.1.11! root 8799:
1.1 root 8800: newsr = dsp_asr56(dest);
8801:
1.1.1.6 root 8802: source[0] = dsp_core.registers[DSP_REG_B2];
8803: source[1] = dsp_core.registers[DSP_REG_B1];
8804: source[2] = dsp_core.registers[DSP_REG_B0];
1.1.1.11! root 8805:
1.1 root 8806: newsr |= dsp_sub56(source, dest);
8807:
1.1.1.6 root 8808: dsp_core.registers[DSP_REG_A2] = dest[0];
8809: dsp_core.registers[DSP_REG_A1] = dest[1];
8810: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8811:
1.1.1.6 root 8812: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8813:
1.1.1.6 root 8814: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8815: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8816: }
8817:
1.1.1.6 root 8818: static void dsp_subr_b(void)
1.1 root 8819: {
1.1.1.6 root 8820: Uint32 source[3], dest[3];
8821: Uint16 newsr;
1.1 root 8822:
1.1.1.6 root 8823: dest[0] = dsp_core.registers[DSP_REG_B2];
8824: dest[1] = dsp_core.registers[DSP_REG_B1];
8825: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1.1.11! root 8826:
1.1.1.6 root 8827: newsr = dsp_asr56(dest);
1.1 root 8828:
1.1.1.6 root 8829: source[0] = dsp_core.registers[DSP_REG_A2];
8830: source[1] = dsp_core.registers[DSP_REG_A1];
8831: source[2] = dsp_core.registers[DSP_REG_A0];
1.1.1.11! root 8832:
1.1.1.6 root 8833: newsr |= dsp_sub56(source, dest);
1.1 root 8834:
1.1.1.6 root 8835: dsp_core.registers[DSP_REG_B2] = dest[0];
8836: dsp_core.registers[DSP_REG_B1] = dest[1];
8837: dsp_core.registers[DSP_REG_B0] = dest[2];
8838:
8839: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8840:
8841: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8842: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8843: }
8844:
1.1.1.6 root 8845: static void dsp_tfr_b_a(void)
1.1 root 8846: {
1.1.1.6 root 8847: dsp_core.registers[DSP_REG_A0] = dsp_core.registers[DSP_REG_B0];
8848: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_B1];
8849: dsp_core.registers[DSP_REG_A2] = dsp_core.registers[DSP_REG_B2];
8850: }
1.1 root 8851:
1.1.1.6 root 8852: static void dsp_tfr_a_b(void)
8853: {
8854: dsp_core.registers[DSP_REG_B0] = dsp_core.registers[DSP_REG_A0];
8855: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_A1];
8856: dsp_core.registers[DSP_REG_B2] = dsp_core.registers[DSP_REG_A2];
8857: }
8858:
8859: static void dsp_tfr_x0_a(void)
8860: {
1.1.1.11! root 8861: dsp_write_reg(DSP_REG_A, dsp_core.registers[DSP_REG_X0]);
1.1.1.6 root 8862: }
8863:
8864: static void dsp_tfr_x0_b(void)
8865: {
1.1.1.11! root 8866: dsp_write_reg(DSP_REG_B, dsp_core.registers[DSP_REG_X0]);
1.1.1.6 root 8867: }
8868:
8869: static void dsp_tfr_y0_a(void)
8870: {
1.1.1.11! root 8871: dsp_write_reg(DSP_REG_A, dsp_core.registers[DSP_REG_Y0]);
1.1.1.6 root 8872: }
8873:
8874: static void dsp_tfr_y0_b(void)
8875: {
1.1.1.11! root 8876: dsp_write_reg(DSP_REG_B, dsp_core.registers[DSP_REG_Y0]);
1.1.1.6 root 8877: }
8878:
8879: static void dsp_tfr_x1_a(void)
8880: {
1.1.1.11! root 8881: dsp_write_reg(DSP_REG_A, dsp_core.registers[DSP_REG_X1]);
1.1.1.6 root 8882: }
8883:
8884: static void dsp_tfr_x1_b(void)
8885: {
1.1.1.11! root 8886: dsp_write_reg(DSP_REG_B, dsp_core.registers[DSP_REG_X1]);
1.1.1.6 root 8887: }
8888:
8889: static void dsp_tfr_y1_a(void)
8890: {
1.1.1.11! root 8891: dsp_write_reg(DSP_REG_A, dsp_core.registers[DSP_REG_Y1]);
1.1.1.6 root 8892: }
8893:
8894: static void dsp_tfr_y1_b(void)
8895: {
1.1.1.11! root 8896: dsp_write_reg(DSP_REG_B, dsp_core.registers[DSP_REG_Y1]);
1.1.1.6 root 8897: }
8898:
8899: static void dsp_tst_a(void)
8900: {
8901: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_A2],
1.1.1.7 root 8902: dsp_core.registers[DSP_REG_A1],
8903: dsp_core.registers[DSP_REG_A0]);
1.1.1.6 root 8904:
8905: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8906: }
8907:
8908: static void dsp_tst_b(void)
8909: {
8910: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_B2],
1.1.1.7 root 8911: dsp_core.registers[DSP_REG_B1],
8912: dsp_core.registers[DSP_REG_B0]);
1.1 root 8913:
1.1.1.6 root 8914: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
1.1 root 8915: }
8916:
1.1.1.2 root 8917: /*
8918: vim:ts=4:sw=4:
8919: */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.