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1.1 root 1: /*
1.1.1.2 root 2: DSP M56001 emulation
1.1.1.4 root 3: Instructions interpreter
1.1.1.2 root 4:
5: (C) 2003-2008 ARAnyM developer team
6:
7: This program is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2 of the License, or
10: (at your option) any later version.
11:
12: This program is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
18: along with this program; if not, write to the Free Software
19: Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20: */
21:
1.1.1.7 root 22: /*
23: DSP memory mapping
24: ------------------
1.1.1.11 root 25:
1.1.1.7 root 26: The memory map is configured as follows :
27: Program space P is one contiguous block of 32K dsp Words
1.1.1.11 root 28: X and Y data space are each separate 16K dsp Word blocks.
1.1.1.7 root 29: Both X and Y can be accessed as blocks starting at 0 or 16K.
30: Program space physically overlaps both X and Y data spaces.
31: Y: memory is mapped at address $0 in P memory
1.1.1.11 root 32: X: memory is mapped at address $4000 in P memory
1.1.1.7 root 33:
34: The DSP external RAM is zero waitstate, but there is a penalty for
1.1.1.11 root 35: accessing it twice or more in a single instruction, because there is only
1.1.1.9 root 36: one external data bus. The extra access costs 2 cycles penalty.
37:
1.1.1.7 root 38: The internal buses are all separate (0 waitstate)
39:
40:
41: X: Y: P:
42: $ffff |--------------+--------------+--------------|
43: | Int. I/O | Ext. I/O | |
44: $ffc0 |--------------+--------------+ |
45: | | | |
46: | Reserved | Reserved | Reserved |
47: | | | |
48: | | | |
49: | | | |
50: $8000 |--------------+--------------+--------------|
51: | | | |
52: | 16k Shadow | 16k Shadow | |
53: | | | 32K |
54: $4000 |--------------+--------------| Program |
55: | 16K | 16K | RAM |
56: | External | External | |
57: | RAM | RAM | |
58: $0200 |--------------+--------------+--------------|
59: | Log table or | Sin table or | |
60: | external mem | external mem | Internal |
61: $0100 |--------------+--------------+ program |
62: | Internal X | Internal Y | memory |
63: | memory | memory | |
64: $0000 |--------------+--------------+--------------|
65:
66:
67: Special Note : As the Falcon DSP is a 0 waitstate access memory, I've simplified a little the cycle counting.
68: If this DSP emulator code is used in another project, one should take into account the bus control register (BCR) waitstates.
69: */
70:
1.1.1.2 root 71: #ifdef HAVE_CONFIG_H
72: #include "config.h"
73: #endif
74:
1.1.1.6 root 75: #include <stdbool.h>
76:
1.1.1.10 root 77: #include "main.h"
1.1.1.2 root 78: #include "dsp_core.h"
1.1 root 79: #include "dsp_cpu.h"
80: #include "dsp_disasm.h"
1.1.1.6 root 81: #include "log.h"
1.1.1.9 root 82: #include "debugui.h"
1.1 root 83:
1.1.1.2 root 84: #define DSP_COUNT_IPS 0 /* Count instruction per seconds */
85:
1.1 root 86:
87: /**********************************
88: * Defines
89: **********************************/
90:
1.1.1.6 root 91: #define SIGN_PLUS 0
92: #define SIGN_MINUS 1
1.1.1.4 root 93:
1.1.1.9 root 94: /* Defines some bits values for access to external memory (X, Y, P) */
95: /* These values will set/unset the corresponding bits in the variable access_to_ext_memory */
96: /* to detect how many access to the external memory were done for a single instruction */
97: #define EXT_X_MEMORY 0
98: #define EXT_Y_MEMORY 1
99: #define EXT_P_MEMORY 2
100:
101:
1.1 root 102: /**********************************
103: * Variables
104: **********************************/
105:
1.1.1.4 root 106: /* Instructions per second */
107: static Uint32 start_time;
108: static Uint32 num_inst;
109:
1.1 root 110: /* Length of current instruction */
1.1.1.2 root 111: static Uint32 cur_inst_len; /* =0:jump, >0:increment */
1.1 root 112:
113: /* Current instruction */
1.1.1.4 root 114: static Uint32 cur_inst;
1.1 root 115:
1.1.1.7 root 116: /* Counts the number of access to the external memory for one instruction */
1.1.1.9 root 117: static Uint16 access_to_ext_memory;
1.1.1.7 root 118:
1.1.1.6 root 119: /* DSP is in disasm mode ? */
120: /* If yes, stack overflow, underflow and illegal instructions messages are not displayed */
121: static bool isDsp_in_disasm_mode;
1.1 root 122:
1.1.1.7 root 123: static char str_disasm_memory[2][50]; /* Buffer for memory change text in disasm mode */
1.1.1.5 root 124: static Uint16 disasm_memory_ptr; /* Pointer for memory change in disasm mode */
1.1 root 125:
126: /**********************************
127: * Functions
128: **********************************/
129:
130: typedef void (*dsp_emul_t)(void);
131:
132: static void dsp_postexecute_update_pc(void);
133: static void dsp_postexecute_interrupts(void);
134:
1.1.1.5 root 135: static void dsp_setInterruptIPL(Uint32 value);
136:
1.1.1.6 root 137: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2);
1.1.1.2 root 138:
139: static Uint32 read_memory(int space, Uint16 address);
1.1.1.6 root 140: static inline Uint32 read_memory_p(Uint16 address);
1.1.1.2 root 141: static Uint32 read_memory_disasm(int space, Uint16 address);
1.1.1.6 root 142:
143: static inline void write_memory(int space, Uint16 address, Uint32 value);
144: static void write_memory_raw(int space, Uint16 address, Uint32 value);
1.1.1.4 root 145: static void write_memory_disasm(int space, Uint16 address, Uint32 value);
1.1.1.6 root 146:
1.1.1.11 root 147: static void dsp_write_reg(Uint32 numreg, Uint32 value);
1.1 root 148:
1.1.1.4 root 149: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly);
1.1.1.2 root 150: static void dsp_stack_pop(Uint32 *curpc, Uint32 *cursr);
1.1.1.4 root 151: static void dsp_compute_ssh_ssl(void);
1.1 root 152:
153: static void opcode8h_0(void);
154:
1.1.1.2 root 155: static void dsp_update_rn(Uint32 numreg, Sint16 modifier);
156: static void dsp_update_rn_bitreverse(Uint32 numreg);
157: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier);
158: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr);
159: static int dsp_calc_cc(Uint32 cc_code);
1.1 root 160:
161: static void dsp_undefined(void);
162:
163: /* Instructions without parallel moves */
164: static void dsp_andi(void);
1.1.1.4 root 165: static void dsp_bchg_aa(void);
166: static void dsp_bchg_ea(void);
167: static void dsp_bchg_pp(void);
168: static void dsp_bchg_reg(void);
169: static void dsp_bclr_aa(void);
170: static void dsp_bclr_ea(void);
171: static void dsp_bclr_pp(void);
172: static void dsp_bclr_reg(void);
173: static void dsp_bset_aa(void);
174: static void dsp_bset_ea(void);
175: static void dsp_bset_pp(void);
176: static void dsp_bset_reg(void);
177: static void dsp_btst_aa(void);
178: static void dsp_btst_ea(void);
179: static void dsp_btst_pp(void);
180: static void dsp_btst_reg(void);
1.1 root 181: static void dsp_div(void);
182: static void dsp_enddo(void);
183: static void dsp_illegal(void);
1.1.1.4 root 184: static void dsp_jcc_imm(void);
185: static void dsp_jcc_ea(void);
186: static void dsp_jclr_aa(void);
187: static void dsp_jclr_ea(void);
188: static void dsp_jclr_pp(void);
189: static void dsp_jclr_reg(void);
190: static void dsp_jmp_ea(void);
191: static void dsp_jmp_imm(void);
192: static void dsp_jscc_ea(void);
193: static void dsp_jscc_imm(void);
194: static void dsp_jsclr_aa(void);
195: static void dsp_jsclr_ea(void);
196: static void dsp_jsclr_pp(void);
197: static void dsp_jsclr_reg(void);
198: static void dsp_jset_aa(void);
199: static void dsp_jset_ea(void);
200: static void dsp_jset_pp(void);
201: static void dsp_jset_reg(void);
202: static void dsp_jsr_ea(void);
203: static void dsp_jsr_imm(void);
204: static void dsp_jsset_aa(void);
205: static void dsp_jsset_ea(void);
206: static void dsp_jsset_pp(void);
207: static void dsp_jsset_reg(void);
1.1 root 208: static void dsp_lua(void);
1.1.1.4 root 209: static void dsp_movem_ea(void);
210: static void dsp_movem_aa(void);
1.1 root 211: static void dsp_nop(void);
212: static void dsp_norm(void);
213: static void dsp_ori(void);
214: static void dsp_reset(void);
215: static void dsp_rti(void);
216: static void dsp_rts(void);
217: static void dsp_stop(void);
218: static void dsp_swi(void);
219: static void dsp_tcc(void);
220: static void dsp_wait(void);
221:
1.1.1.3 root 222: static void dsp_do_ea(void);
223: static void dsp_do_aa(void);
224: static void dsp_do_imm(void);
225: static void dsp_do_reg(void);
226: static void dsp_rep_aa(void);
227: static void dsp_rep_ea(void);
228: static void dsp_rep_imm(void);
229: static void dsp_rep_reg(void);
230: static void dsp_movec_aa(void);
231: static void dsp_movec_ea(void);
232: static void dsp_movec_imm(void);
233: static void dsp_movec_reg(void);
1.1 root 234: static void dsp_movep_0(void);
235: static void dsp_movep_1(void);
1.1.1.4 root 236: static void dsp_movep_23(void);
1.1 root 237:
238: /* Parallel move analyzer */
1.1.1.2 root 239: static int dsp_pm_read_accu24(int numreg, Uint32 *dest);
1.1 root 240: static void dsp_pm_0(void);
241: static void dsp_pm_1(void);
242: static void dsp_pm_2(void);
243: static void dsp_pm_2_2(void);
244: static void dsp_pm_3(void);
245: static void dsp_pm_4(void);
1.1.1.4 root 246: static void dsp_pm_4x(void);
1.1 root 247: static void dsp_pm_5(void);
248: static void dsp_pm_8(void);
249:
250: /* 56bits arithmetic */
1.1.1.2 root 251: static Uint16 dsp_abs56(Uint32 *dest);
252: static Uint16 dsp_asl56(Uint32 *dest);
253: static Uint16 dsp_asr56(Uint32 *dest);
254: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest);
255: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest);
1.1.1.5 root 256: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe);
1.1.1.2 root 257: static void dsp_rnd56(Uint32 *dest);
1.1 root 258:
259: /* Instructions with parallel moves */
1.1.1.6 root 260: static void dsp_abs_a(void);
261: static void dsp_abs_b(void);
262: static void dsp_adc_x_a(void);
263: static void dsp_adc_x_b(void);
264: static void dsp_adc_y_a(void);
265: static void dsp_adc_y_b(void);
266: static void dsp_add_b_a(void);
267: static void dsp_add_a_b(void);
268: static void dsp_add_x_a(void);
269: static void dsp_add_x_b(void);
270: static void dsp_add_y_a(void);
271: static void dsp_add_y_b(void);
272: static void dsp_add_x0_a(void);
273: static void dsp_add_x0_b(void);
274: static void dsp_add_y0_a(void);
275: static void dsp_add_y0_b(void);
276: static void dsp_add_x1_a(void);
277: static void dsp_add_x1_b(void);
278: static void dsp_add_y1_a(void);
279: static void dsp_add_y1_b(void);
280: static void dsp_addl_b_a(void);
281: static void dsp_addl_a_b(void);
282: static void dsp_addr_b_a(void);
283: static void dsp_addr_a_b(void);
284: static void dsp_and_x0_a(void);
285: static void dsp_and_x0_b(void);
286: static void dsp_and_y0_a(void);
287: static void dsp_and_y0_b(void);
288: static void dsp_and_x1_a(void);
289: static void dsp_and_x1_b(void);
290: static void dsp_and_y1_a(void);
291: static void dsp_and_y1_b(void);
1.1.1.7 root 292: static void dsp_asl_a(void);
293: static void dsp_asl_b(void);
294: static void dsp_asr_a(void);
295: static void dsp_asr_b(void);
1.1.1.6 root 296: static void dsp_clr_a(void);
297: static void dsp_clr_b(void);
298: static void dsp_cmp_b_a(void);
299: static void dsp_cmp_a_b(void);
300: static void dsp_cmp_x0_a(void);
301: static void dsp_cmp_x0_b(void);
302: static void dsp_cmp_y0_a(void);
303: static void dsp_cmp_y0_b(void);
304: static void dsp_cmp_x1_a(void);
305: static void dsp_cmp_x1_b(void);
306: static void dsp_cmp_y1_a(void);
307: static void dsp_cmp_y1_b(void);
308: static void dsp_cmpm_b_a(void);
309: static void dsp_cmpm_a_b(void);
310: static void dsp_cmpm_x0_a(void);
311: static void dsp_cmpm_x0_b(void);
312: static void dsp_cmpm_y0_a(void);
313: static void dsp_cmpm_y0_b(void);
314: static void dsp_cmpm_x1_a(void);
315: static void dsp_cmpm_x1_b(void);
316: static void dsp_cmpm_y1_a(void);
317: static void dsp_cmpm_y1_b(void);
318: static void dsp_eor_x0_a(void);
319: static void dsp_eor_x0_b(void);
320: static void dsp_eor_y0_a(void);
321: static void dsp_eor_y0_b(void);
322: static void dsp_eor_x1_a(void);
323: static void dsp_eor_x1_b(void);
324: static void dsp_eor_y1_a(void);
325: static void dsp_eor_y1_b(void);
326: static void dsp_lsl_a(void);
327: static void dsp_lsl_b(void);
328: static void dsp_lsr_a(void);
329: static void dsp_lsr_b(void);
330: static void dsp_mac_p_x0_x0_a(void);
331: static void dsp_mac_m_x0_x0_a(void);
332: static void dsp_mac_p_x0_x0_b(void);
333: static void dsp_mac_m_x0_x0_b(void);
334: static void dsp_mac_p_y0_y0_a(void);
335: static void dsp_mac_m_y0_y0_a(void);
336: static void dsp_mac_p_y0_y0_b(void);
337: static void dsp_mac_m_y0_y0_b(void);
338: static void dsp_mac_p_x1_x0_a(void);
339: static void dsp_mac_m_x1_x0_a(void);
340: static void dsp_mac_p_x1_x0_b(void);
341: static void dsp_mac_m_x1_x0_b(void);
342: static void dsp_mac_p_y1_y0_a(void);
343: static void dsp_mac_m_y1_y0_a(void);
344: static void dsp_mac_p_y1_y0_b(void);
345: static void dsp_mac_m_y1_y0_b(void);
346: static void dsp_mac_p_x0_y1_a(void);
347: static void dsp_mac_m_x0_y1_a(void);
348: static void dsp_mac_p_x0_y1_b(void);
349: static void dsp_mac_m_x0_y1_b(void);
350: static void dsp_mac_p_y0_x0_a(void);
351: static void dsp_mac_m_y0_x0_a(void);
352: static void dsp_mac_p_y0_x0_b(void);
353: static void dsp_mac_m_y0_x0_b(void);
354: static void dsp_mac_p_x1_y0_a(void);
355: static void dsp_mac_m_x1_y0_a(void);
356: static void dsp_mac_p_x1_y0_b(void);
357: static void dsp_mac_m_x1_y0_b(void);
358: static void dsp_mac_p_y1_x1_a(void);
359: static void dsp_mac_m_y1_x1_a(void);
360: static void dsp_mac_p_y1_x1_b(void);
361: static void dsp_mac_m_y1_x1_b(void);
362: static void dsp_macr_p_x0_x0_a(void);
363: static void dsp_macr_m_x0_x0_a(void);
364: static void dsp_macr_p_x0_x0_b(void);
365: static void dsp_macr_m_x0_x0_b(void);
366: static void dsp_macr_p_y0_y0_a(void);
367: static void dsp_macr_m_y0_y0_a(void);
368: static void dsp_macr_p_y0_y0_b(void);
369: static void dsp_macr_m_y0_y0_b(void);
370: static void dsp_macr_p_x1_x0_a(void);
371: static void dsp_macr_m_x1_x0_a(void);
372: static void dsp_macr_p_x1_x0_b(void);
373: static void dsp_macr_m_x1_x0_b(void);
374: static void dsp_macr_p_y1_y0_a(void);
375: static void dsp_macr_m_y1_y0_a(void);
376: static void dsp_macr_p_y1_y0_b(void);
377: static void dsp_macr_m_y1_y0_b(void);
378: static void dsp_macr_p_x0_y1_a(void);
379: static void dsp_macr_m_x0_y1_a(void);
380: static void dsp_macr_p_x0_y1_b(void);
381: static void dsp_macr_m_x0_y1_b(void);
382: static void dsp_macr_p_y0_x0_a(void);
383: static void dsp_macr_m_y0_x0_a(void);
384: static void dsp_macr_p_y0_x0_b(void);
385: static void dsp_macr_m_y0_x0_b(void);
386: static void dsp_macr_p_x1_y0_a(void);
387: static void dsp_macr_m_x1_y0_a(void);
388: static void dsp_macr_p_x1_y0_b(void);
389: static void dsp_macr_m_x1_y0_b(void);
390: static void dsp_macr_p_y1_x1_a(void);
391: static void dsp_macr_m_y1_x1_a(void);
392: static void dsp_macr_p_y1_x1_b(void);
393: static void dsp_macr_m_y1_x1_b(void);
1.1 root 394: static void dsp_move(void);
1.1.1.6 root 395: static void dsp_mpy_p_x0_x0_a(void);
396: static void dsp_mpy_m_x0_x0_a(void);
397: static void dsp_mpy_p_x0_x0_b(void);
398: static void dsp_mpy_m_x0_x0_b(void);
399: static void dsp_mpy_p_y0_y0_a(void);
400: static void dsp_mpy_m_y0_y0_a(void);
401: static void dsp_mpy_p_y0_y0_b(void);
402: static void dsp_mpy_m_y0_y0_b(void);
403: static void dsp_mpy_p_x1_x0_a(void);
404: static void dsp_mpy_m_x1_x0_a(void);
405: static void dsp_mpy_p_x1_x0_b(void);
406: static void dsp_mpy_m_x1_x0_b(void);
407: static void dsp_mpy_p_y1_y0_a(void);
408: static void dsp_mpy_m_y1_y0_a(void);
409: static void dsp_mpy_p_y1_y0_b(void);
410: static void dsp_mpy_m_y1_y0_b(void);
411: static void dsp_mpy_p_x0_y1_a(void);
412: static void dsp_mpy_m_x0_y1_a(void);
413: static void dsp_mpy_p_x0_y1_b(void);
414: static void dsp_mpy_m_x0_y1_b(void);
415: static void dsp_mpy_p_y0_x0_a(void);
416: static void dsp_mpy_m_y0_x0_a(void);
417: static void dsp_mpy_p_y0_x0_b(void);
418: static void dsp_mpy_m_y0_x0_b(void);
419: static void dsp_mpy_p_x1_y0_a(void);
420: static void dsp_mpy_m_x1_y0_a(void);
421: static void dsp_mpy_p_x1_y0_b(void);
422: static void dsp_mpy_m_x1_y0_b(void);
423: static void dsp_mpy_p_y1_x1_a(void);
424: static void dsp_mpy_m_y1_x1_a(void);
425: static void dsp_mpy_p_y1_x1_b(void);
426: static void dsp_mpy_m_y1_x1_b(void);
427: static void dsp_mpyr_p_x0_x0_a(void);
428: static void dsp_mpyr_m_x0_x0_a(void);
429: static void dsp_mpyr_p_x0_x0_b(void);
430: static void dsp_mpyr_m_x0_x0_b(void);
431: static void dsp_mpyr_p_y0_y0_a(void);
432: static void dsp_mpyr_m_y0_y0_a(void);
433: static void dsp_mpyr_p_y0_y0_b(void);
434: static void dsp_mpyr_m_y0_y0_b(void);
435: static void dsp_mpyr_p_x1_x0_a(void);
436: static void dsp_mpyr_m_x1_x0_a(void);
437: static void dsp_mpyr_p_x1_x0_b(void);
438: static void dsp_mpyr_m_x1_x0_b(void);
439: static void dsp_mpyr_p_y1_y0_a(void);
440: static void dsp_mpyr_m_y1_y0_a(void);
441: static void dsp_mpyr_p_y1_y0_b(void);
442: static void dsp_mpyr_m_y1_y0_b(void);
443: static void dsp_mpyr_p_x0_y1_a(void);
444: static void dsp_mpyr_m_x0_y1_a(void);
445: static void dsp_mpyr_p_x0_y1_b(void);
446: static void dsp_mpyr_m_x0_y1_b(void);
447: static void dsp_mpyr_p_y0_x0_a(void);
448: static void dsp_mpyr_m_y0_x0_a(void);
449: static void dsp_mpyr_p_y0_x0_b(void);
450: static void dsp_mpyr_m_y0_x0_b(void);
451: static void dsp_mpyr_p_x1_y0_a(void);
452: static void dsp_mpyr_m_x1_y0_a(void);
453: static void dsp_mpyr_p_x1_y0_b(void);
454: static void dsp_mpyr_m_x1_y0_b(void);
455: static void dsp_mpyr_p_y1_x1_a(void);
456: static void dsp_mpyr_m_y1_x1_a(void);
457: static void dsp_mpyr_p_y1_x1_b(void);
458: static void dsp_mpyr_m_y1_x1_b(void);
459: static void dsp_neg_a(void);
460: static void dsp_neg_b(void);
461: static void dsp_not_a(void);
462: static void dsp_not_b(void);
463: static void dsp_or_x0_a(void);
464: static void dsp_or_x0_b(void);
465: static void dsp_or_y0_a(void);
466: static void dsp_or_y0_b(void);
467: static void dsp_or_x1_a(void);
468: static void dsp_or_x1_b(void);
469: static void dsp_or_y1_a(void);
470: static void dsp_or_y1_b(void);
471: static void dsp_rnd_a(void);
472: static void dsp_rnd_b(void);
473: static void dsp_rol_a(void);
474: static void dsp_rol_b(void);
475: static void dsp_ror_a(void);
476: static void dsp_ror_b(void);
477: static void dsp_sbc_x_a(void);
478: static void dsp_sbc_x_b(void);
479: static void dsp_sbc_y_a(void);
480: static void dsp_sbc_y_b(void);
481: static void dsp_sub_b_a(void);
482: static void dsp_sub_a_b(void);
483: static void dsp_sub_x_a(void);
484: static void dsp_sub_x_b(void);
485: static void dsp_sub_y_a(void);
486: static void dsp_sub_y_b(void);
487: static void dsp_sub_x0_a(void);
488: static void dsp_sub_x0_b(void);
489: static void dsp_sub_y0_a(void);
490: static void dsp_sub_y0_b(void);
491: static void dsp_sub_x1_a(void);
492: static void dsp_sub_x1_b(void);
493: static void dsp_sub_y1_a(void);
494: static void dsp_sub_y1_b(void);
495: static void dsp_subl_a(void);
496: static void dsp_subl_b(void);
497: static void dsp_subr_a(void);
498: static void dsp_subr_b(void);
499: static void dsp_tfr_b_a(void);
500: static void dsp_tfr_a_b(void);
501: static void dsp_tfr_x0_a(void);
502: static void dsp_tfr_x0_b(void);
503: static void dsp_tfr_y0_a(void);
504: static void dsp_tfr_y0_b(void);
505: static void dsp_tfr_x1_a(void);
506: static void dsp_tfr_x1_b(void);
507: static void dsp_tfr_y1_a(void);
508: static void dsp_tfr_y1_b(void);
509: static void dsp_tst_a(void);
510: static void dsp_tst_b(void);
1.1 root 511:
1.1.1.6 root 512: static const dsp_emul_t opcodes8h[512] = {
1.1.1.4 root 513: /* 0x00 - 0x3f */
514: opcode8h_0, dsp_undefined, dsp_undefined, dsp_undefined, opcode8h_0, dsp_andi, dsp_undefined, dsp_ori,
515: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
516: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
517: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
518: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
519: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
520: dsp_undefined, dsp_undefined, dsp_div, dsp_div, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
521: dsp_norm, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
1.1.1.11 root 522:
1.1.1.4 root 523: /* 0x40 - 0x7f */
524: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
525: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
526: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
527: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
528: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
529: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
530: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
531: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
532:
533: /* 0x80 - 0xbf */
534: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
1.1.1.11 root 535: dsp_lua, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
1.1.1.4 root 536: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
1.1.1.11 root 537: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
1.1.1.4 root 538: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
539: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
540: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
541: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
1.1.1.11 root 542:
1.1.1.4 root 543: /* 0xc0 - 0xff */
1.1.1.11 root 544: dsp_do_aa, dsp_rep_aa, dsp_do_aa, dsp_rep_aa, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
545: dsp_do_ea, dsp_rep_ea, dsp_do_ea, dsp_rep_ea, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
546: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
547: dsp_do_reg, dsp_rep_reg, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
548: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
549: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
550: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
551: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
1.1.1.4 root 552:
553: /* 0x100 - 0x13f */
1.1.1.6 root 554: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 555: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 556: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 557: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 558: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 559: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 560: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 561: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
562:
563: /* 0x140 - 0x17f */
564: dsp_bclr_aa, dsp_bset_aa, dsp_bclr_aa, dsp_bset_aa, dsp_jclr_aa, dsp_jset_aa, dsp_jclr_aa, dsp_jset_aa,
565: dsp_bclr_ea, dsp_bset_ea, dsp_bclr_ea, dsp_bset_ea, dsp_jclr_ea, dsp_jset_ea, dsp_jclr_ea, dsp_jset_ea,
566: dsp_bclr_pp, dsp_bset_pp, dsp_bclr_pp, dsp_bset_pp, dsp_jclr_pp, dsp_jset_pp, dsp_jclr_pp, dsp_jset_pp,
567: dsp_jclr_reg, dsp_jset_reg, dsp_bclr_reg, dsp_bset_reg, dsp_jmp_ea, dsp_jcc_ea, dsp_undefined, dsp_undefined,
568: dsp_bchg_aa, dsp_btst_aa, dsp_bchg_aa, dsp_btst_aa, dsp_jsclr_aa, dsp_jsset_aa, dsp_jsclr_aa, dsp_jsset_aa,
569: dsp_bchg_ea, dsp_btst_ea, dsp_bchg_ea, dsp_btst_ea, dsp_jsclr_ea, dsp_jsset_ea, dsp_jsclr_ea, dsp_jsset_ea,
570: dsp_bchg_pp, dsp_btst_pp, dsp_bchg_pp, dsp_btst_pp, dsp_jsclr_pp, dsp_jsset_pp, dsp_jsclr_pp, dsp_jsset_pp,
571: dsp_jsclr_reg, dsp_jsset_reg, dsp_bchg_reg, dsp_btst_reg, dsp_jsr_ea, dsp_jscc_ea, dsp_undefined, dsp_undefined,
572:
573: /* 0x180 - 0x1bf */
574: dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm,
1.1.1.11 root 575: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
576: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
577: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
578: dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm,
579: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
580: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
581: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
1.1.1.4 root 582:
583: /* 0x1c0 - 0x1ff */
1.1.1.11 root 584: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
585: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
586: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
587: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
588: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
589: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
590: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
591: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
1.1 root 592: };
593:
1.1.1.6 root 594: static const dsp_emul_t opcodes_parmove[16] = {
595: dsp_pm_0, dsp_pm_1, dsp_pm_2, dsp_pm_3, dsp_pm_4, dsp_pm_5, dsp_pm_5, dsp_pm_5,
596: dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8
1.1 root 597: };
598:
1.1.1.6 root 599: static const dsp_emul_t opcodes_alu[256] = {
1.1.1.4 root 600: /* 0x00 - 0x3f */
1.1.1.6 root 601: dsp_move , dsp_tfr_b_a, dsp_addr_b_a, dsp_tst_a, dsp_undefined, dsp_cmp_b_a, dsp_subr_a, dsp_cmpm_b_a,
602: dsp_undefined, dsp_tfr_a_b, dsp_addr_a_b, dsp_tst_b, dsp_undefined, dsp_cmp_a_b, dsp_subr_b, dsp_cmpm_a_b,
603: dsp_add_b_a, dsp_rnd_a, dsp_addl_b_a, dsp_clr_a, dsp_sub_b_a, dsp_undefined, dsp_subl_a, dsp_not_a,
604: dsp_add_a_b, dsp_rnd_b, dsp_addl_a_b, dsp_clr_b, dsp_sub_a_b, dsp_undefined, dsp_subl_b, dsp_not_b,
1.1.1.7 root 605: dsp_add_x_a, dsp_adc_x_a, dsp_asr_a, dsp_lsr_a, dsp_sub_x_a, dsp_sbc_x_a, dsp_abs_a, dsp_ror_a,
606: dsp_add_x_b, dsp_adc_x_b, dsp_asr_b, dsp_lsr_b, dsp_sub_x_b, dsp_sbc_x_b, dsp_abs_b, dsp_ror_b,
607: dsp_add_y_a, dsp_adc_y_a, dsp_asl_a, dsp_lsl_a, dsp_sub_y_a, dsp_sbc_y_a, dsp_neg_a, dsp_rol_a,
608: dsp_add_y_b, dsp_adc_y_b, dsp_asl_b, dsp_lsl_b, dsp_sub_y_b, dsp_sbc_y_b, dsp_neg_b, dsp_rol_b,
1.1.1.11 root 609:
1.1.1.4 root 610: /* 0x40 - 0x7f */
1.1.1.6 root 611: dsp_add_x0_a, dsp_tfr_x0_a, dsp_or_x0_a, dsp_eor_x0_a, dsp_sub_x0_a, dsp_cmp_x0_a, dsp_and_x0_a, dsp_cmpm_x0_a,
612: dsp_add_x0_b, dsp_tfr_x0_b, dsp_or_x0_b, dsp_eor_x0_b, dsp_sub_x0_b, dsp_cmp_x0_b, dsp_and_x0_b, dsp_cmpm_x0_b,
613: dsp_add_y0_a, dsp_tfr_y0_a, dsp_or_y0_a, dsp_eor_y0_a, dsp_sub_y0_a, dsp_cmp_y0_a, dsp_and_y0_a, dsp_cmpm_y0_a,
614: dsp_add_y0_b, dsp_tfr_y0_b, dsp_or_y0_b, dsp_eor_y0_b, dsp_sub_y0_b, dsp_cmp_y0_b, dsp_and_y0_b, dsp_cmpm_y0_b,
615: dsp_add_x1_a, dsp_tfr_x1_a, dsp_or_x1_a, dsp_eor_x1_a, dsp_sub_x1_a, dsp_cmp_x1_a, dsp_and_x1_a, dsp_cmpm_x1_a,
616: dsp_add_x1_b, dsp_tfr_x1_b, dsp_or_x1_b, dsp_eor_x1_b, dsp_sub_x1_b, dsp_cmp_x1_b, dsp_and_x1_b, dsp_cmpm_x1_b,
617: dsp_add_y1_a, dsp_tfr_y1_a, dsp_or_y1_a, dsp_eor_y1_a, dsp_sub_y1_a, dsp_cmp_y1_a, dsp_and_y1_a, dsp_cmpm_y1_a,
618: dsp_add_y1_b, dsp_tfr_y1_b, dsp_or_y1_b, dsp_eor_y1_b, dsp_sub_y1_b, dsp_cmp_y1_b, dsp_and_y1_b, dsp_cmpm_y1_b,
1.1.1.4 root 619:
620: /* 0x80 - 0xbf */
1.1.1.6 root 621: dsp_mpy_p_x0_x0_a, dsp_mpyr_p_x0_x0_a, dsp_mac_p_x0_x0_a, dsp_macr_p_x0_x0_a, dsp_mpy_m_x0_x0_a, dsp_mpyr_m_x0_x0_a, dsp_mac_m_x0_x0_a, dsp_macr_m_x0_x0_a,
622: dsp_mpy_p_x0_x0_b, dsp_mpyr_p_x0_x0_b, dsp_mac_p_x0_x0_b, dsp_macr_p_x0_x0_b, dsp_mpy_m_x0_x0_b, dsp_mpyr_m_x0_x0_b, dsp_mac_m_x0_x0_b, dsp_macr_m_x0_x0_b,
623: dsp_mpy_p_y0_y0_a, dsp_mpyr_p_y0_y0_a, dsp_mac_p_y0_y0_a, dsp_macr_p_y0_y0_a, dsp_mpy_m_y0_y0_a, dsp_mpyr_m_y0_y0_a, dsp_mac_m_y0_y0_a, dsp_macr_m_y0_y0_a,
624: dsp_mpy_p_y0_y0_b, dsp_mpyr_p_y0_y0_b, dsp_mac_p_y0_y0_b, dsp_macr_p_y0_y0_b, dsp_mpy_m_y0_y0_b, dsp_mpyr_m_y0_y0_b, dsp_mac_m_y0_y0_b, dsp_macr_m_y0_y0_b,
625: dsp_mpy_p_x1_x0_a, dsp_mpyr_p_x1_x0_a, dsp_mac_p_x1_x0_a, dsp_macr_p_x1_x0_a, dsp_mpy_m_x1_x0_a, dsp_mpyr_m_x1_x0_a, dsp_mac_m_x1_x0_a, dsp_macr_m_x1_x0_a,
626: dsp_mpy_p_x1_x0_b, dsp_mpyr_p_x1_x0_b, dsp_mac_p_x1_x0_b, dsp_macr_p_x1_x0_b, dsp_mpy_m_x1_x0_b, dsp_mpyr_m_x1_x0_b, dsp_mac_m_x1_x0_b, dsp_macr_m_x1_x0_b,
627: dsp_mpy_p_y1_y0_a, dsp_mpyr_p_y1_y0_a, dsp_mac_p_y1_y0_a, dsp_macr_p_y1_y0_a, dsp_mpy_m_y1_y0_a, dsp_mpyr_m_y1_y0_a, dsp_mac_m_y1_y0_a, dsp_macr_m_y1_y0_a,
628: dsp_mpy_p_y1_y0_b, dsp_mpyr_p_y1_y0_b, dsp_mac_p_y1_y0_b, dsp_macr_p_y1_y0_b, dsp_mpy_m_y1_y0_b, dsp_mpyr_m_y1_y0_b, dsp_mac_m_y1_y0_b, dsp_macr_m_y1_y0_b,
629:
630: /* 0xc0_m_ 0xff */
631: dsp_mpy_p_x0_y1_a, dsp_mpyr_p_x0_y1_a, dsp_mac_p_x0_y1_a, dsp_macr_p_x0_y1_a, dsp_mpy_m_x0_y1_a, dsp_mpyr_m_x0_y1_a, dsp_mac_m_x0_y1_a, dsp_macr_m_x0_y1_a,
632: dsp_mpy_p_x0_y1_b, dsp_mpyr_p_x0_y1_b, dsp_mac_p_x0_y1_b, dsp_macr_p_x0_y1_b, dsp_mpy_m_x0_y1_b, dsp_mpyr_m_x0_y1_b, dsp_mac_m_x0_y1_b, dsp_macr_m_x0_y1_b,
633: dsp_mpy_p_y0_x0_a, dsp_mpyr_p_y0_x0_a, dsp_mac_p_y0_x0_a, dsp_macr_p_y0_x0_a, dsp_mpy_m_y0_x0_a, dsp_mpyr_m_y0_x0_a, dsp_mac_m_y0_x0_a, dsp_macr_m_y0_x0_a,
634: dsp_mpy_p_y0_x0_b, dsp_mpyr_p_y0_x0_b, dsp_mac_p_y0_x0_b, dsp_macr_p_y0_x0_b, dsp_mpy_m_y0_x0_b, dsp_mpyr_m_y0_x0_b, dsp_mac_m_y0_x0_b, dsp_macr_m_y0_x0_b,
635: dsp_mpy_p_x1_y0_a, dsp_mpyr_p_x1_y0_a, dsp_mac_p_x1_y0_a, dsp_macr_p_x1_y0_a, dsp_mpy_m_x1_y0_a, dsp_mpyr_m_x1_y0_a, dsp_mac_m_x1_y0_a, dsp_macr_m_x1_y0_a,
636: dsp_mpy_p_x1_y0_b, dsp_mpyr_p_x1_y0_b, dsp_mac_p_x1_y0_b, dsp_macr_p_x1_y0_b, dsp_mpy_m_x1_y0_b, dsp_mpyr_m_x1_y0_b, dsp_mac_m_x1_y0_b, dsp_macr_m_x1_y0_b,
637: dsp_mpy_p_y1_x1_a, dsp_mpyr_p_y1_x1_a, dsp_mac_p_y1_x1_a, dsp_macr_p_y1_x1_a, dsp_mpy_m_y1_x1_a, dsp_mpyr_m_y1_x1_a, dsp_mac_m_y1_x1_a, dsp_macr_m_y1_x1_a,
638: dsp_mpy_p_y1_x1_b, dsp_mpyr_p_y1_x1_b, dsp_mac_p_y1_x1_b, dsp_macr_p_y1_x1_b, dsp_mpy_m_y1_x1_b, dsp_mpyr_m_y1_x1_b, dsp_mac_m_y1_x1_b, dsp_macr_m_y1_x1_b
1.1 root 639: };
640:
1.1.1.6 root 641: static const int registers_tcc[16][2] = {
1.1 root 642: {DSP_REG_B,DSP_REG_A},
643: {DSP_REG_A,DSP_REG_B},
644: {DSP_REG_NULL,DSP_REG_NULL},
645: {DSP_REG_NULL,DSP_REG_NULL},
646:
647: {DSP_REG_NULL,DSP_REG_NULL},
648: {DSP_REG_NULL,DSP_REG_NULL},
649: {DSP_REG_NULL,DSP_REG_NULL},
650: {DSP_REG_NULL,DSP_REG_NULL},
651:
652: {DSP_REG_X0,DSP_REG_A},
653: {DSP_REG_X0,DSP_REG_B},
654: {DSP_REG_Y0,DSP_REG_A},
655: {DSP_REG_Y0,DSP_REG_B},
1.1.1.2 root 656:
657: {DSP_REG_X1,DSP_REG_A},
658: {DSP_REG_X1,DSP_REG_B},
1.1 root 659: {DSP_REG_Y1,DSP_REG_A},
660: {DSP_REG_Y1,DSP_REG_B}
661: };
662:
1.1.1.6 root 663: static const int registers_mask[64] = {
1.1 root 664: 0, 0, 0, 0,
665: 24, 24, 24, 24,
666: 24, 24, 8, 8,
667: 24, 24, 24, 24,
1.1.1.11 root 668:
1.1 root 669: 16, 16, 16, 16,
670: 16, 16, 16, 16,
671: 16, 16, 16, 16,
672: 16, 16, 16, 16,
1.1.1.11 root 673:
1.1 root 674: 16, 16, 16, 16,
675: 16, 16, 16, 16,
676: 0, 0, 0, 0,
677: 0, 0, 0, 0,
678:
679: 0, 0, 0, 0,
680: 0, 0, 0, 0,
681: 0, 16, 8, 6,
1.1.1.4 root 682: 16, 16, 16, 16
683: };
684:
1.1.1.6 root 685: static const dsp_interrupt_t dsp_interrupt[12] = {
1.1.1.5 root 686: {DSP_INTER_RESET , 0x00, 0, "Reset"},
687: {DSP_INTER_ILLEGAL , 0x3e, 0, "Illegal"},
688: {DSP_INTER_STACK_ERROR , 0x02, 0, "Stack Error"},
689: {DSP_INTER_TRACE , 0x04, 0, "Trace"},
690: {DSP_INTER_SWI , 0x06, 0, "Swi"},
691: {DSP_INTER_HOST_COMMAND , 0xff, 1, "Host Command"},
692: {DSP_INTER_HOST_RCV_DATA, 0x20, 1, "Host receive"},
693: {DSP_INTER_HOST_TRX_DATA, 0x22, 1, "Host transmit"},
694: {DSP_INTER_SSI_RCV_DATA_E, 0x0e, 2, "SSI receive with exception"},
695: {DSP_INTER_SSI_RCV_DATA , 0x0c, 2, "SSI receive"},
696: {DSP_INTER_SSI_TRX_DATA_E, 0x12, 2, "SSI transmit with exception"},
697: {DSP_INTER_SSI_TRX_DATA , 0x10, 2, "SSI tramsmit"}
1.1.1.4 root 698: };
699:
1.1 root 700:
701: /**********************************
702: * Emulator kernel
703: **********************************/
704:
1.1.1.6 root 705: void dsp56k_init_cpu(void)
1.1 root 706: {
1.1.1.6 root 707: dsp56k_disasm_init();
708: isDsp_in_disasm_mode = false;
1.1.1.2 root 709: start_time = SDL_GetTicks();
710: num_inst = 0;
1.1 root 711: }
712:
1.1.1.6 root 713: /**
714: * Execute one instruction in trace mode at a given PC address.
715: * */
1.1.1.9 root 716: Uint16 dsp56k_execute_one_disasm_instruction(FILE *out, Uint16 pc)
1.1.1.6 root 717: {
718: dsp_core_t *ptr1, *ptr2;
719: static dsp_core_t dsp_core_save;
1.1.1.8 root 720: Uint16 instruction_length;
1.1.1.6 root 721:
722: ptr1 = &dsp_core;
723: ptr2 = &dsp_core_save;
724:
725: /* Set DSP in disasm mode */
726: isDsp_in_disasm_mode = true;
727:
728: /* Save DSP context before executing instruction */
729: memcpy(ptr2, ptr1, sizeof(dsp_core));
730:
731: /* execute and disasm instruction */
732: dsp_core.pc = pc;
733:
734: /* Disasm instruction */
1.1.1.12! root 735: instruction_length = dsp56k_disasm(DSP_DISASM_MODE, out) - 1;
1.1.1.6 root 736:
737: /* Execute instruction at address given in parameter to get the number of cycles it takes */
738: dsp56k_execute_instruction();
739:
1.1.1.9 root 740: fprintf(out, "%s", dsp56k_getInstructionText());
1.1.1.6 root 741:
742: /* Restore DSP context after executing instruction */
743: memcpy(ptr1, ptr2, sizeof(dsp_core));
1.1.1.11 root 744:
1.1.1.6 root 745: /* Unset DSP in disasm mode */
746: isDsp_in_disasm_mode = false;
747:
748: return instruction_length;
749: }
750:
1.1.1.4 root 751: void dsp56k_execute_instruction(void)
1.1 root 752: {
1.1.1.2 root 753: Uint32 value;
1.1.1.6 root 754: Uint32 disasm_return = 0;
1.1.1.5 root 755: disasm_memory_ptr = 0;
756:
1.1.1.7 root 757: /* Initialise the number of access to the external memory for this instruction */
1.1.1.9 root 758: access_to_ext_memory = 0;
1.1.1.11 root 759:
760: /* Init the indirect AGU move instruction flag */
761: dsp_core.agu_move_indirect_instr = 0;
762:
1.1 root 763: /* Decode and execute current instruction */
1.1.1.6 root 764: cur_inst = read_memory_p(dsp_core.pc);
1.1.1.11 root 765:
1.1.1.7 root 766: /* Initialize instruction size and cycle counter */
767: cur_inst_len = 1;
1.1.1.6 root 768: dsp_core.instr_cycle = 2;
1.1 root 769:
1.1.1.6 root 770: /* Disasm current instruction ? (trace mode only) */
1.1.1.11 root 771: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
1.1.1.6 root 772: /* Call dsp56k_disasm only when DSP is called in trace mode */
773: if (isDsp_in_disasm_mode == false) {
1.1.1.12! root 774: disasm_return = dsp56k_disasm(DSP_TRACE_MODE, TraceFile);
1.1.1.11 root 775:
1.1.1.6 root 776: if (disasm_return != 0 && LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG)) {
777: /* DSP regs trace enabled only if DSP DISASM is enabled */
778: dsp56k_disasm_reg_save();
779: }
780: }
781: }
1.1.1.11 root 782:
1.1.1.4 root 783: if (cur_inst < 0x100000) {
784: value = (cur_inst >> 11) & (BITMASK(6) << 3);
785: value += (cur_inst >> 5) & BITMASK(3);
1.1 root 786: opcodes8h[value]();
787: } else {
1.1.1.6 root 788: /* Do parallel move read */
789: opcodes_parmove[(cur_inst>>20) & BITMASK(4)]();
790: }
791:
1.1.1.7 root 792: /* Add the waitstate due to external memory access */
1.1.1.9 root 793: /* (2 extra cycles per extra access to the external memory after the first one */
794: if (access_to_ext_memory != 0) {
795: value = access_to_ext_memory & 1;
796: value += (access_to_ext_memory & 2) >> 1;
797: value += (access_to_ext_memory & 4) >> 2;
1.1.1.11 root 798:
1.1.1.9 root 799: if (value > 1)
800: dsp_core.instr_cycle += (value - 1) * 2;
801: }
802:
1.1.1.6 root 803: /* Disasm current instruction ? (trace mode only) */
804: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
805: /* Display only when DSP is called in trace mode */
806: if (isDsp_in_disasm_mode == false) {
807: if (disasm_return != 0) {
1.1.1.12! root 808: fprintf(TraceFile, "%s", dsp56k_getInstructionText());
1.1.1.11 root 809:
1.1.1.6 root 810: /* DSP regs trace enabled only if DSP DISASM is enabled */
811: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG))
1.1.1.12! root 812: dsp56k_disasm_reg_compare(TraceFile);
1.1.1.6 root 813:
814: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM)) {
815: /* 1 memory change to display ? */
816: if (disasm_memory_ptr == 1)
1.1.1.12! root 817: fprintf(TraceFile, "\t%s\n", str_disasm_memory[0]);
1.1.1.6 root 818: /* 2 memory changes to display ? */
819: else if (disasm_memory_ptr == 2) {
1.1.1.12! root 820: fprintf(TraceFile, "\t%s\n", str_disasm_memory[0]);
! 821: fprintf(TraceFile, "\t%s\n", str_disasm_memory[1]);
1.1.1.6 root 822: }
823: }
824: }
825: }
1.1 root 826: }
827:
1.1.1.4 root 828: /* Process the PC */
829: dsp_postexecute_update_pc();
1.1 root 830:
1.1.1.4 root 831: /* Process Interrupts */
1.1 root 832: dsp_postexecute_interrupts();
833:
1.1.1.4 root 834: #if DSP_COUNT_IPS
835: ++num_inst;
836: if ((num_inst & 63) == 0) {
837: /* Evaluate time after <N> instructions have been executed to avoid asking too frequently */
838: Uint32 cur_time = SDL_GetTicks();
839: if (cur_time-start_time>1000) {
840: fprintf(stderr, "Dsp: %d i/s\n", (num_inst*1000)/(cur_time-start_time));
841: start_time=cur_time;
842: num_inst=0;
843: }
844: }
845: #endif
1.1 root 846: }
847:
848: /**********************************
849: * Update the PC
850: **********************************/
851:
852: static void dsp_postexecute_update_pc(void)
853: {
854: /* When running a REP, PC must stay on the current instruction */
1.1.1.6 root 855: if (dsp_core.loop_rep) {
1.1.1.11 root 856: /* Is PC on the instruction to repeat ? */
1.1.1.6 root 857: if (dsp_core.pc_on_rep==0) {
858: --dsp_core.registers[DSP_REG_LC];
859: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1 root 860:
1.1.1.6 root 861: if (dsp_core.registers[DSP_REG_LC] > 0) {
1.1.1.7 root 862: cur_inst_len = 0; /* Stay on this instruction */
1.1 root 863: } else {
1.1.1.6 root 864: dsp_core.loop_rep = 0;
865: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[DSP_REG_LCSAVE];
1.1 root 866: }
867: } else {
868: /* Init LC at right value */
1.1.1.6 root 869: if (dsp_core.registers[DSP_REG_LC] == 0) {
870: dsp_core.registers[DSP_REG_LC] = 0x010000;
1.1 root 871: }
1.1.1.6 root 872: dsp_core.pc_on_rep = 0;
1.1 root 873: }
874: }
875:
876: /* Normal execution, go to next instruction */
1.1.1.6 root 877: dsp_core.pc += cur_inst_len;
1.1 root 878:
879: /* When running a DO loop, we test the end of loop with the */
880: /* updated PC, pointing to last instruction of the loop */
1.1.1.6 root 881: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_LF)) {
1.1 root 882:
883: /* Did we execute the last instruction in loop ? */
1.1.1.11 root 884: if (dsp_core.pc == dsp_core.registers[DSP_REG_LA] + 1) {
885: if (dsp_core.registers[DSP_REG_LC] == 1) {
886: /* end of the loop */
1.1.1.4 root 887: Uint32 saved_pc, saved_sr;
888:
889: dsp_stack_pop(&saved_pc, &saved_sr);
1.1.1.10 root 890: dsp_core.registers[DSP_REG_SR] &= 0x7fff;
1.1.1.6 root 891: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
892: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
1.1 root 893: } else {
894: /* Loop one more time */
1.1.1.11 root 895: --dsp_core.registers[DSP_REG_LC];
896: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.6 root 897: dsp_core.pc = dsp_core.registers[DSP_REG_SSH];
1.1 root 898: }
899: }
900: }
901: }
902:
903: /**********************************
904: * Interrupts
905: **********************************/
906:
1.1.1.5 root 907: /* Post a new interrupt to the interrupt table */
908: void dsp_add_interrupt(Uint16 inter)
909: {
910: /* detect if this interrupt is used or not */
1.1.1.6 root 911: if (dsp_core.interrupt_ipl[inter] == -1)
1.1.1.5 root 912: return;
913:
914: /* add this interrupt to the pending interrupts table */
1.1.1.11 root 915: if (dsp_core.interrupt_isPending[inter] == 0) {
1.1.1.6 root 916: dsp_core.interrupt_isPending[inter] = 1;
917: dsp_core.interrupt_counter ++;
1.1.1.5 root 918: }
919: }
920:
921: static void dsp_setInterruptIPL(Uint32 value)
922: {
923: Uint32 ipl_ssi, ipl_hi, i;
924:
925: ipl_ssi = ((value >> 12) & 3) - 1;
926: ipl_hi = ((value >> 10) & 3) - 1;
927:
928: /* set IPL_HI */
1.1.1.7 root 929: for (i=5; i<8; i++) {
1.1.1.6 root 930: dsp_core.interrupt_ipl[i] = ipl_hi;
1.1.1.5 root 931: }
932:
933: /* set IPL_SSI */
1.1.1.7 root 934: for (i=8; i<12; i++) {
1.1.1.6 root 935: dsp_core.interrupt_ipl[i] = ipl_ssi;
1.1.1.5 root 936: }
937: }
938:
1.1 root 939: static void dsp_postexecute_interrupts(void)
940: {
1.1.1.5 root 941: Uint32 index, instr, i;
942: Sint32 ipl_to_raise, ipl_sr;
1.1.1.4 root 943:
944: /* REP is not interruptible */
1.1.1.6 root 945: if (dsp_core.loop_rep) {
1.1.1.4 root 946: return;
947: }
948:
949: /* A fast interrupt can not be interrupted. */
1.1.1.6 root 950: if (dsp_core.interrupt_state == DSP_INTERRUPT_DISABLED) {
1.1.1.5 root 951:
1.1.1.6 root 952: switch (dsp_core.interrupt_pipeline_count) {
1.1.1.5 root 953: case 5:
1.1.1.6 root 954: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 955: return;
956: case 4:
957: /* Prefetch interrupt instruction 1 */
1.1.1.6 root 958: dsp_core.interrupt_save_pc = dsp_core.pc;
959: dsp_core.pc = dsp_core.interrupt_instr_fetch;
1.1.1.5 root 960:
961: /* is it a LONG interrupt ? */
1.1.1.6 root 962: instr = read_memory_p(dsp_core.interrupt_instr_fetch);
1.1.1.5 root 963: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1.1.1.6 root 964: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
1.1.1.11 root 965: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.6 root 966: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1.1.1.5 root 967: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
968: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1.1.1.6 root 969: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1.1.1.5 root 970: }
1.1.1.6 root 971: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 972: return;
973: case 3:
1.1.1.11 root 974: /* Prefetch interrupt instruction 2, if first one was single word */
1.1.1.6 root 975: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+1) {
976: instr = read_memory_p(dsp_core.pc);
1.1.1.5 root 977: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1.1.1.6 root 978: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
1.1.1.11 root 979: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.6 root 980: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1.1.1.5 root 981: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
982: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1.1.1.6 root 983: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1.1.1.5 root 984: }
1.1.1.11 root 985: dsp_core.interrupt_pipeline_count --;
986: return;
987: }
988: dsp_core.interrupt_pipeline_count --;
989: /* First instruction was 2 word. Fall through */
1.1.1.5 root 990: case 2:
991: /* 1 instruction executed after interrupt */
992: /* before re enable interrupts */
993: /* Was it a FAST interrupt ? */
1.1.1.6 root 994: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+2) {
995: dsp_core.pc = dsp_core.interrupt_save_pc;
1.1.1.5 root 996: }
1.1.1.6 root 997: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 998: return;
999: case 1:
1000: /* Last instruction executed after interrupt */
1001: /* before re enable interrupts */
1.1.1.6 root 1002: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 1003: return;
1004: case 0:
1005: /* Re enable interrupts */
1.1.1.6 root 1006: /* All 6 instruction are done, Interrupts can be enabled again */
1007: dsp_core.interrupt_save_pc = -1;
1008: dsp_core.interrupt_instr_fetch = -1;
1009: dsp_core.interrupt_state = DSP_INTERRUPT_NONE;
1010: break;
1.1.1.4 root 1011: }
1012: }
1.1 root 1013:
1.1.1.4 root 1014: /* Trace Interrupt ? */
1.1.1.6 root 1015: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_T)) {
1.1.1.5 root 1016: dsp_add_interrupt(DSP_INTER_TRACE);
1.1.1.4 root 1017: }
1018:
1019: /* No interrupt to execute */
1.1.1.6 root 1020: if (dsp_core.interrupt_counter == 0) {
1.1.1.4 root 1021: return;
1.1 root 1022: }
1023:
1.1.1.5 root 1024: /* search for an interrupt */
1.1.1.6 root 1025: ipl_sr = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_I0) & BITMASK(2);
1.1.1.5 root 1026: index = 0xffff;
1027: ipl_to_raise = -1;
1028:
1029: /* Arbitrate between all pending interrupts */
1030: for (i=0; i<12; i++) {
1.1.1.6 root 1031: if (dsp_core.interrupt_isPending[i] == 1) {
1.1.1.5 root 1032:
1033: /* level 3 interrupt ? */
1.1.1.6 root 1034: if (dsp_core.interrupt_ipl[i] == 3) {
1.1.1.5 root 1035: index = i;
1036: break;
1037: }
1.1 root 1038:
1.1.1.5 root 1039: /* level 0, 1 ,2 interrupt ? */
1040: /* if interrupt is masked in SR, don't process it */
1.1.1.6 root 1041: if (dsp_core.interrupt_ipl[i] < ipl_sr)
1.1.1.5 root 1042: continue;
1.1 root 1043:
1.1.1.5 root 1044: /* if interrupt is lower or equal than current arbitrated interrupt */
1.1.1.6 root 1045: if (dsp_core.interrupt_ipl[i] <= ipl_to_raise)
1.1.1.5 root 1046: continue;
1047:
1048: /* save current arbitrated interrupt */
1049: index = i;
1.1.1.6 root 1050: ipl_to_raise = dsp_core.interrupt_ipl[i];
1.1 root 1051: }
1052: }
1.1.1.4 root 1053:
1.1.1.5 root 1054: /* If there's no interrupt to process, return */
1055: if (index == 0xffff) {
1.1.1.4 root 1056: return;
1057: }
1058:
1.1.1.5 root 1059: /* remove this interrupt from the pending interrupts table */
1.1.1.6 root 1060: dsp_core.interrupt_isPending[index] = 0;
1061: dsp_core.interrupt_counter --;
1.1.1.5 root 1062:
1063: /* process arbritrated interrupt */
1.1.1.6 root 1064: ipl_to_raise = dsp_core.interrupt_ipl[index] + 1;
1.1.1.5 root 1065: if (ipl_to_raise > 3) {
1066: ipl_to_raise = 3;
1067: }
1068:
1.1.1.6 root 1069: dsp_core.interrupt_instr_fetch = dsp_interrupt[index].vectorAddr;
1070: dsp_core.interrupt_pipeline_count = 5;
1071: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1072: dsp_core.interrupt_IplToRaise = ipl_to_raise;
1073:
1074: LOG_TRACE(TRACE_DSP_INTERRUPT, "Dsp interrupt: %s\n", dsp_interrupt[index].name);
1.1.1.5 root 1075:
1076: /* SSI receive data with exception ? */
1.1.1.6 root 1077: if (dsp_core.interrupt_instr_fetch == 0xe) {
1078: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_ROE);
1.1.1.4 root 1079: }
1080:
1.1.1.5 root 1081: /* SSI transmit data with exception ? */
1.1.1.6 root 1082: else if (dsp_core.interrupt_instr_fetch == 0x12) {
1083: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_TUE);
1.1.1.4 root 1084: }
1085:
1086: /* host command ? */
1.1.1.6 root 1087: else if (dsp_core.interrupt_instr_fetch == 0xff) {
1.1.1.4 root 1088: /* Clear HC and HCP interrupt */
1.1.1.6 root 1089: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] &= 0xff - (1<<DSP_HOST_HSR_HCP);
1.1.1.11 root 1090: dsp_core.hostport[CPU_HOST_CVR] &= 0xff - (1<<CPU_HOST_CVR_HC);
1.1.1.4 root 1091:
1.1.1.6 root 1092: dsp_core.interrupt_instr_fetch = dsp_core.hostport[CPU_HOST_CVR] & BITMASK(5);
1.1.1.11 root 1093: dsp_core.interrupt_instr_fetch *= 2;
1.1.1.4 root 1094: }
1.1 root 1095: }
1096:
1097: /**********************************
1098: * Set/clear ccr bits
1099: **********************************/
1100:
1101: /* reg0 has bits 55..48 */
1102: /* reg1 has bits 47..24 */
1103: /* reg2 has bits 23..0 */
1104:
1.1.1.11 root 1105: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2)
1.1.1.6 root 1106: {
1107: Uint32 scaling, value_e, value_u;
1.1.1.4 root 1108:
1.1.1.6 root 1109: /* Initialize SR register */
1110: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E) | (1<<DSP_SR_U) | (1<<DSP_SR_N) | (1<<DSP_SR_Z));
1.1.1.4 root 1111:
1.1.1.6 root 1112: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
1.1 root 1113: switch(scaling) {
1114: case 0:
1.1.1.6 root 1115: /* Extension Bit (E) */
1116: value_e = (reg0<<1) + (reg1>>23);
1117: if ((value_e != 0) && (value_e != BITMASK(9)))
1118: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1119:
1120: /* Unnormalized bit (U) */
1.1.1.11 root 1121: if ((reg1 & 0xc00000) == 0 || (reg1 & 0xc00000) == 0xc00000)
1.1.1.6 root 1122: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1123: break;
1124: case 1:
1.1.1.6 root 1125: /* Extension Bit (E) */
1126: if ((reg0 != 0) && (reg0 != BITMASK(8)))
1127: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1128:
1129: /* Unnormalized bit (U) */
1130: value_u = ((reg0<<1) + (reg1>>23)) & 3;
1.1.1.11 root 1131: if (value_u == 0 || value_u == 3)
1.1.1.6 root 1132: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1133: break;
1134: case 2:
1.1.1.6 root 1135: /* Extension Bit (E) */
1136: value_e = (reg0<<2) + (reg1>>22);
1137: if ((value_e != 0) && (value_e != BITMASK(10)))
1138: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1139:
1140: /* Unnormalized bit (U) */
1.1.1.11 root 1141: if ((reg1 & 0x600000) == 0 || (reg1 & 0x600000) == 0x600000)
1.1.1.6 root 1142: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1143: break;
1144: default:
1145: return;
1146: break;
1147: }
1148:
1.1.1.6 root 1149: /* Zero Flag (Z) */
1150: if ((reg1 == 0) && (reg2 == 0) && (reg0 == 0))
1151: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_Z;
1.1.1.4 root 1152:
1.1.1.6 root 1153: /* Negative Flag (N) */
1154: dsp_core.registers[DSP_REG_SR] |= (reg0>>4) & 0x8;
1.1 root 1155: }
1156:
1157: /**********************************
1158: * Read/Write memory functions
1159: **********************************/
1160:
1.1.1.2 root 1161: static Uint32 read_memory_disasm(int space, Uint16 address)
1.1 root 1162: {
1.1.1.4 root 1163: /* Internal RAM ? */
1164: if (address<0x100) {
1.1.1.6 root 1165: return dsp_core.ramint[space][address] & BITMASK(24);
1.1.1.4 root 1166: }
1.1 root 1167:
1.1.1.4 root 1168: if (space==DSP_SPACE_P) {
1169: return read_memory_p(address);
1.1 root 1170: }
1171:
1.1.1.4 root 1172: /* Internal ROM? */
1.1.1.6 root 1173: if ((dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) &&
1.1.1.4 root 1174: (address<0x200)) {
1.1.1.6 root 1175: return dsp_core.rom[space][address] & BITMASK(24);
1.1.1.4 root 1176: }
1177:
1178: /* Peripheral address ? */
1179: if (address >= 0xffc0) {
1.1.1.6 root 1180: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_HOST_HTX)) {
1181: return dsp_core.dsp_host_htx;
1.1.1.4 root 1182: }
1183: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_SSI_TX)) {
1.1.1.6 root 1184: return dsp_core.ssi.transmit_value;
1.1.1.4 root 1185: }
1.1.1.6 root 1186: return dsp_core.periph[space][address-0xffc0] & BITMASK(24);
1.1.1.4 root 1187: }
1188:
1189: /* Falcon: External RAM, map X to upper 16K of matching space in Y,P */
1190: address &= (DSP_RAMSIZE>>1) - 1;
1191: if (space == DSP_SPACE_X) {
1192: address += DSP_RAMSIZE>>1;
1193: }
1194:
1195: /* Falcon: External RAM, finally map X,Y to P */
1.1.1.6 root 1196: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1.1 root 1197: }
1198:
1.1.1.4 root 1199: static inline Uint32 read_memory_p(Uint16 address)
1200: {
1201: /* Internal RAM ? */
1.1.1.7 root 1202: if (address < 0x200) {
1.1.1.6 root 1203: return dsp_core.ramint[DSP_SPACE_P][address] & BITMASK(24);
1.1.1.4 root 1204: }
1205:
1.1.1.9 root 1206: /* Access to the external P memory */
1207: access_to_ext_memory |= 1 << EXT_P_MEMORY;
1.1.1.7 root 1208:
1.1.1.4 root 1209: /* External RAM, mask address to available ram size */
1.1.1.6 root 1210: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1.1.1.4 root 1211: }
1212:
1.1.1.2 root 1213: static Uint32 read_memory(int space, Uint16 address)
1.1 root 1214: {
1.1.1.4 root 1215: Uint32 value;
1.1 root 1216:
1.1.1.4 root 1217: /* Internal RAM ? */
1218: if (address < 0x100) {
1.1.1.6 root 1219: return dsp_core.ramint[space][address] & BITMASK(24);
1.1.1.4 root 1220: }
1.1 root 1221:
1.1.1.4 root 1222: if (space == DSP_SPACE_P) {
1223: return read_memory_p(address);
1224: }
1225:
1226: /* Internal ROM ? */
1227: if (address < 0x200) {
1.1.1.6 root 1228: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1229: return dsp_core.rom[space][address] & BITMASK(24);
1.1.1.4 root 1230: }
1231: }
1232:
1233: /* Peripheral address ? */
1234: if (address >= 0xffc0) {
1.1.1.6 root 1235: value = dsp_core.periph[space][address-0xffc0] & BITMASK(24);
1.1.1.4 root 1236: if (space == DSP_SPACE_X) {
1237: if (address == 0xffc0+DSP_HOST_HRX) {
1.1.1.6 root 1238: value = dsp_core.dsp_host_rtx;
1239: dsp_core_hostport_dspread();
1.1.1.11 root 1240: }
1.1.1.4 root 1241: else if (address == 0xffc0+DSP_SSI_RX) {
1.1.1.6 root 1242: value = dsp_core_ssi_readRX();
1.1 root 1243: }
1.1.1.4 root 1244: }
1245: return value;
1.1 root 1246: }
1247:
1.1.1.9 root 1248: /* Falcon: External X or Y RAM access */
1.1.1.4 root 1249: address &= (DSP_RAMSIZE>>1) - 1;
1250:
1251: if (space == DSP_SPACE_X) {
1.1.1.9 root 1252: /* Map X to upper 16K of matching space in Y,P */
1.1.1.4 root 1253: address += DSP_RAMSIZE>>1;
1.1.1.9 root 1254:
1255: /* Set one access to the X external memory */
1256: access_to_ext_memory |= 1 << EXT_X_MEMORY;
1257: }
1258: else {
1259: /* Access to the Y external memory */
1260: access_to_ext_memory |= 1 << EXT_Y_MEMORY;
1.1.1.4 root 1261: }
1262:
1.1.1.9 root 1263:
1.1.1.4 root 1264: /* Falcon: External RAM, finally map X,Y to P */
1.1.1.6 root 1265: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1266: }
1267:
1268: static inline void write_memory(int space, Uint16 address, Uint32 value)
1269: {
1.1.1.12! root 1270: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM))
1.1.1.6 root 1271: write_memory_disasm(space, address, value);
1.1.1.11 root 1272: else
1.1.1.6 root 1273: write_memory_raw(space, address, value);
1.1 root 1274: }
1275:
1.1.1.4 root 1276: static void write_memory_raw(int space, Uint16 address, Uint32 value)
1.1 root 1277: {
1278: value &= BITMASK(24);
1279:
1.1.1.4 root 1280: /* Peripheral address ? */
1281: if (address >= 0xffc0) {
1282: if (space == DSP_SPACE_X) {
1283: switch(address-0xffc0) {
1284: case DSP_HOST_HTX:
1.1.1.6 root 1285: dsp_core.dsp_host_htx = value;
1286: dsp_core_hostport_dspwrite();
1.1.1.4 root 1287: break;
1288: case DSP_HOST_HCR:
1.1.1.6 root 1289: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] = value;
1.1.1.4 root 1290: /* Set HF3 and HF2 accordingly on the host side */
1.1.1.6 root 1291: dsp_core.hostport[CPU_HOST_ISR] &=
1.1.1.4 root 1292: BITMASK(8)-((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1.1.1.6 root 1293: dsp_core.hostport[CPU_HOST_ISR] |=
1294: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] & ((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1.1.1.4 root 1295: break;
1296: case DSP_HOST_HSR:
1297: /* Read only */
1298: break;
1299: case DSP_SSI_CRA:
1300: case DSP_SSI_CRB:
1.1.1.6 root 1301: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1302: dsp_core_ssi_configure(address-0xffc0, value);
1.1.1.4 root 1303: break;
1304: case DSP_SSI_TSR:
1.1.1.6 root 1305: dsp_core_ssi_writeTSR();
1.1.1.4 root 1306: break;
1307: case DSP_SSI_TX:
1.1.1.6 root 1308: dsp_core_ssi_writeTX(value);
1.1.1.4 root 1309: break;
1.1.1.5 root 1310: case DSP_IPR:
1.1.1.6 root 1311: dsp_core.periph[DSP_SPACE_X][DSP_IPR] = value;
1.1.1.5 root 1312: dsp_setInterruptIPL(value);
1313: break;
1314: case DSP_PCD:
1.1.1.6 root 1315: dsp_core.periph[DSP_SPACE_X][DSP_PCD] = value;
1316: dsp_core_setPortCDataRegister(value);
1.1.1.5 root 1317: break;
1.1.1.4 root 1318: default:
1.1.1.6 root 1319: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1.1.1.4 root 1320: break;
1.1 root 1321: }
1.1.1.4 root 1322: return;
1.1.1.11 root 1323: }
1.1.1.4 root 1324: else if (space == DSP_SPACE_Y) {
1.1.1.6 root 1325: dsp_core.periph[DSP_SPACE_Y][address-0xffc0] = value;
1.1.1.4 root 1326: return;
1327: }
1328: }
1.1.1.11 root 1329:
1.1.1.4 root 1330: /* Internal RAM ? */
1331: if (address < 0x100) {
1.1.1.6 root 1332: dsp_core.ramint[space][address] = value;
1.1.1.4 root 1333: return;
1334: }
1.1.1.2 root 1335:
1.1.1.4 root 1336: /* Internal ROM ? */
1337: if (address < 0x200) {
1338: if (space != DSP_SPACE_P) {
1.1.1.6 root 1339: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1.1.1.2 root 1340: /* Can not write to ROM space */
1.1 root 1341: return;
1342: }
1.1.1.4 root 1343: }
1344: else {
1345: /* Space P RAM */
1.1.1.6 root 1346: dsp_core.ramint[DSP_SPACE_P][address] = value;
1.1.1.4 root 1347: return;
1348: }
1.1 root 1349: }
1350:
1.1.1.9 root 1351: /* Access to X, Y or P external RAM */
1.1.1.4 root 1352:
1.1.1.9 root 1353: if (space == DSP_SPACE_P) {
1354: /* Access to the P external RAM */
1355: access_to_ext_memory |= 1 << EXT_P_MEMORY;
1356: }
1357: else {
1.1.1.4 root 1358: address &= (DSP_RAMSIZE>>1) - 1;
1359:
1.1.1.9 root 1360: if (space == DSP_SPACE_X) {
1361: /* Access to the X external RAM */
1362: /* map X to upper 16K of matching space in Y,P */
1363: address += DSP_RAMSIZE>>1;
1364: access_to_ext_memory |= 1;
1365: }
1366: else {
1367: /* Access to the Y external RAM */
1368: access_to_ext_memory |= 1 << EXT_Y_MEMORY;
1369: }
1.1.1.4 root 1370: }
1371:
1372: /* Falcon: External RAM, map X,Y to P */
1.1.1.6 root 1373: dsp_core.ramext[address & (DSP_RAMSIZE-1)] = value;
1.1.1.2 root 1374: }
1375:
1.1.1.4 root 1376: static void write_memory_disasm(int space, Uint16 address, Uint32 value)
1.1.1.2 root 1377: {
1.1.1.4 root 1378: Uint32 oldvalue, curvalue;
1379: Uint8 space_c = 'p';
1380:
1.1.1.2 root 1381: value &= BITMASK(24);
1.1.1.6 root 1382: oldvalue = read_memory_disasm(space, address);
1.1.1.2 root 1383:
1384: write_memory_raw(space,address,value);
1385:
1.1 root 1386: switch(space) {
1387: case DSP_SPACE_X:
1.1.1.4 root 1388: space_c = 'x';
1.1 root 1389: break;
1390: case DSP_SPACE_Y:
1.1.1.4 root 1391: space_c = 'y';
1392: break;
1393: default:
1.1 root 1394: break;
1395: }
1.1.1.4 root 1396:
1.1.1.6 root 1397: curvalue = read_memory_disasm(space, address);
1.1.1.5 root 1398: sprintf(str_disasm_memory[disasm_memory_ptr],"Mem: %c:0x%04x 0x%06x -> 0x%06x", space_c, address, oldvalue, curvalue);
1399: disasm_memory_ptr ++;
1.1 root 1400: }
1401:
1.1.1.4 root 1402: static void dsp_write_reg(Uint32 numreg, Uint32 value)
1403: {
1.1.1.5 root 1404: Uint32 stack_error;
1.1.1.4 root 1405:
1.1.1.7 root 1406: switch (numreg) {
1407: case DSP_REG_A:
1408: dsp_core.registers[DSP_REG_A0] = 0;
1.1.1.11 root 1409: dsp_core.registers[DSP_REG_A1] = value & BITMASK(24);
1.1.1.7 root 1410: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
1411: break;
1412: case DSP_REG_B:
1413: dsp_core.registers[DSP_REG_B0] = 0;
1.1.1.11 root 1414: dsp_core.registers[DSP_REG_B1] = value & BITMASK(24);
1.1.1.7 root 1415: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
1416: break;
1.1.1.11 root 1417: case DSP_REG_R0:
1418: case DSP_REG_R1:
1419: case DSP_REG_R2:
1420: case DSP_REG_R3:
1421: case DSP_REG_R4:
1422: case DSP_REG_R5:
1423: case DSP_REG_R6:
1424: case DSP_REG_R7:
1425: case DSP_REG_N0:
1426: case DSP_REG_N1:
1427: case DSP_REG_N2:
1428: case DSP_REG_N3:
1429: case DSP_REG_N4:
1430: case DSP_REG_N5:
1431: case DSP_REG_N6:
1432: case DSP_REG_N7:
1433: case DSP_REG_M0:
1434: case DSP_REG_M1:
1435: case DSP_REG_M2:
1436: case DSP_REG_M3:
1437: case DSP_REG_M4:
1438: case DSP_REG_M5:
1439: case DSP_REG_M6:
1440: case DSP_REG_M7:
1441: dsp_core.registers[numreg] = value & BITMASK(16);
1442: break;
1.1.1.7 root 1443: case DSP_REG_OMR:
1444: dsp_core.registers[DSP_REG_OMR] = value & 0xc7;
1445: break;
1446: case DSP_REG_SR:
1447: dsp_core.registers[DSP_REG_SR] = value & 0xaf7f;
1448: break;
1449: case DSP_REG_SP:
1.1.1.8 root 1450: stack_error = dsp_core.registers[DSP_REG_SP] & (3<<DSP_SP_SE);
1451: if ((stack_error==0) && (value & (3<<DSP_SP_SE))) {
1452: /* Stack underflow or overflow detected, raise interrupt */
1.1.1.7 root 1453: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.9 root 1454: dsp_core.registers[DSP_REG_SP] = value & (3<<DSP_SP_SE);
1.1.1.7 root 1455: if (!isDsp_in_disasm_mode)
1.1.1.8 root 1456: fprintf(stderr,"Dsp: Stack Overflow or Underflow\n");
1.1.1.10 root 1457: if (ExceptionDebugMask & EXCEPT_DSP)
1.1.1.9 root 1458: DebugUI(REASON_DSP_EXCEPTION);
1.1.1.7 root 1459: }
1.1.1.8 root 1460: else
1.1.1.11 root 1461: dsp_core.registers[DSP_REG_SP] = value & BITMASK(6);
1.1.1.7 root 1462: dsp_compute_ssh_ssl();
1463: break;
1464: case DSP_REG_SSH:
1465: dsp_stack_push(value, 0, 1);
1466: break;
1467: case DSP_REG_SSL:
1468: numreg = dsp_core.registers[DSP_REG_SP] & BITMASK(4);
1469: if (numreg == 0) {
1470: value = 0;
1471: }
1472: dsp_core.stack[1][numreg] = value & BITMASK(16);
1473: dsp_core.registers[DSP_REG_SSL] = value & BITMASK(16);
1474: break;
1475: default:
1.1.1.11 root 1476: dsp_core.registers[numreg] = value;
1.1.1.7 root 1477: dsp_core.registers[numreg] &= BITMASK(registers_mask[numreg]);
1478: break;
1.1.1.4 root 1479: }
1480: }
1481:
1.1 root 1482: /**********************************
1483: * Stack push/pop
1484: **********************************/
1485:
1.1.1.4 root 1486: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly)
1.1 root 1487: {
1.1.1.4 root 1488: Uint32 stack_error, underflow, stack;
1489:
1.1.1.6 root 1490: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1491: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1492: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) + 1;
1.1.1.4 root 1493:
1494:
1495: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1.1 root 1496: /* Stack full, raise interrupt */
1.1.1.5 root 1497: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.6 root 1498: if (!isDsp_in_disasm_mode)
1499: fprintf(stderr,"Dsp: Stack Overflow\n");
1.1.1.10 root 1500: if (ExceptionDebugMask & EXCEPT_DSP)
1.1.1.9 root 1501: DebugUI(REASON_DSP_EXCEPTION);
1.1 root 1502: }
1.1.1.11 root 1503:
1.1.1.6 root 1504: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1.1.1.4 root 1505: stack &= BITMASK(4);
1.1 root 1506:
1.1.1.4 root 1507: if (stack) {
1508: /* SSH part */
1.1.1.6 root 1509: dsp_core.stack[0][stack] = curpc & BITMASK(16);
1.1.1.4 root 1510: /* SSL part, if instruction is not like "MOVEC xx, SSH" */
1511: if (sshOnly == 0) {
1.1.1.6 root 1512: dsp_core.stack[1][stack] = cursr & BITMASK(16);
1.1.1.4 root 1513: }
1514: } else {
1.1.1.6 root 1515: dsp_core.stack[0][0] = 0;
1516: dsp_core.stack[1][0] = 0;
1.1.1.4 root 1517: }
1.1 root 1518:
1.1.1.4 root 1519: /* Update SSH and SSL registers */
1.1.1.6 root 1520: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1521: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1 root 1522: }
1523:
1.1.1.2 root 1524: static void dsp_stack_pop(Uint32 *newpc, Uint32 *newsr)
1.1 root 1525: {
1.1.1.4 root 1526: Uint32 stack_error, underflow, stack;
1527:
1.1.1.6 root 1528: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1529: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1530: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) - 1;
1.1.1.4 root 1531:
1532: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1533: /* Stack empty*/
1.1.1.5 root 1534: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.6 root 1535: if (!isDsp_in_disasm_mode)
1536: fprintf(stderr,"Dsp: Stack underflow\n");
1.1.1.10 root 1537: if (ExceptionDebugMask & EXCEPT_DSP)
1.1.1.9 root 1538: DebugUI(REASON_DSP_EXCEPTION);
1.1 root 1539: }
1540:
1.1.1.6 root 1541: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1.1.1.4 root 1542: stack &= BITMASK(4);
1.1.1.6 root 1543: *newpc = dsp_core.registers[DSP_REG_SSH];
1544: *newsr = dsp_core.registers[DSP_REG_SSL];
1.1.1.4 root 1545:
1.1.1.6 root 1546: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1547: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1.1.4 root 1548: }
1549:
1550: static void dsp_compute_ssh_ssl(void)
1551: {
1552: Uint32 stack;
1.1 root 1553:
1.1.1.6 root 1554: stack = dsp_core.registers[DSP_REG_SP];
1.1.1.4 root 1555: stack &= BITMASK(4);
1.1.1.6 root 1556: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1557: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1 root 1558: }
1559:
1560: /**********************************
1561: * Effective address calculation
1562: **********************************/
1563:
1.1.1.2 root 1564: static void dsp_update_rn(Uint32 numreg, Sint16 modifier)
1.1 root 1565: {
1.1.1.12! root 1566: Uint32 value;
1.1.1.2 root 1567: Uint16 m_reg;
1.1 root 1568:
1.1.1.6 root 1569: m_reg = (Uint16) dsp_core.registers[DSP_REG_M0+numreg];
1.1.1.7 root 1570: if (m_reg == 65535) {
1571: /* Linear addressing mode */
1.1.1.12! root 1572: value = dsp_core.registers[DSP_REG_R0+numreg]|0x10000;
1.1.1.7 root 1573: value += modifier;
1.1.1.12! root 1574: dsp_core.registers[DSP_REG_R0+numreg] = value & BITMASK(16);
1.1.1.7 root 1575: } else if (m_reg == 0) {
1.1 root 1576: /* Bit reversed carry update */
1577: dsp_update_rn_bitreverse(numreg);
1.1.1.4 root 1578: } else if (m_reg<=32767) {
1.1 root 1579: /* Modulo update */
1580: dsp_update_rn_modulo(numreg, modifier);
1581: } else {
1582: /* Undefined */
1583: }
1584: }
1585:
1.1.1.2 root 1586: static void dsp_update_rn_bitreverse(Uint32 numreg)
1.1 root 1587: {
1588: int revbits, i;
1.1.1.2 root 1589: Uint32 value, r_reg;
1.1 root 1590:
1591: /* Check how many bits to reverse */
1.1.1.6 root 1592: value = dsp_core.registers[DSP_REG_N0+numreg];
1.1 root 1593: for (revbits=0;revbits<16;revbits++) {
1594: if (value & (1<<revbits)) {
1595: break;
1596: }
1.1.1.11 root 1597: }
1.1 root 1598: revbits++;
1.1.1.11 root 1599:
1.1 root 1600: /* Reverse Rn bits */
1.1.1.6 root 1601: r_reg = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1602: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1603: for (i=0;i<revbits;i++) {
1604: if (r_reg & (1<<i)) {
1605: value |= 1<<(revbits-i-1);
1606: }
1607: }
1608:
1609: /* Increment */
1610: value++;
1611: value &= BITMASK(revbits);
1612:
1613: /* Reverse Rn bits */
1614: r_reg &= (BITMASK(16)-BITMASK(revbits));
1615: r_reg |= value;
1616:
1617: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1618: for (i=0;i<revbits;i++) {
1619: if (r_reg & (1<<i)) {
1620: value |= 1<<(revbits-i-1);
1621: }
1622: }
1623:
1.1.1.6 root 1624: dsp_core.registers[DSP_REG_R0+numreg] = value;
1.1 root 1625: }
1626:
1.1.1.2 root 1627: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier)
1.1 root 1628: {
1.1.1.12! root 1629: Uint16 bufsize, bufmask, modulo, abs_modifier;
! 1630: Uint32 r_reg, lobound, hibound;
1.1 root 1631:
1.1.1.12! root 1632: r_reg = dsp_core.registers[DSP_REG_R0+numreg]|0x10000;
1.1.1.6 root 1633: modulo = dsp_core.registers[DSP_REG_M0+numreg]+1;
1.1.1.12! root 1634:
! 1635:
1.1 root 1636: bufsize = 1;
1637: while (bufsize < modulo) {
1638: bufsize <<= 1;
1639: }
1.1.1.12! root 1640: bufmask = bufsize - 1;
1.1.1.11 root 1641:
1.1.1.12! root 1642:
! 1643: lobound = r_reg - (r_reg&bufmask);
1.1.1.2 root 1644: hibound = lobound + modulo - 1;
1.1 root 1645:
1.1.1.4 root 1646:
1.1.1.12! root 1647: if (modifier<0) {
! 1648: abs_modifier = -modifier;
! 1649: } else {
! 1650: abs_modifier = modifier;
1.1.1.2 root 1651: }
1.1.1.4 root 1652:
1653:
1.1.1.12! root 1654: if (abs_modifier>modulo) {
! 1655: if (abs_modifier&bufmask) {
! 1656: fprintf(stderr,"Dsp: Modulo addressing result unpredictable\n");
! 1657: } else {
! 1658: r_reg += modifier;
! 1659: }
! 1660: } else {
! 1661: r_reg += modifier;
! 1662:
! 1663:
1.1.1.4 root 1664: if (r_reg>hibound) {
1665: r_reg -= modulo;
1666: } else if (r_reg<lobound) {
1667: r_reg += modulo;
1.1.1.11 root 1668: }
1.1 root 1669: }
1670:
1.1.1.12! root 1671: dsp_core.registers[DSP_REG_R0+numreg] = r_reg & BITMASK(16);
1.1 root 1672: }
1673:
1.1.1.2 root 1674: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr)
1.1 root 1675: {
1.1.1.2 root 1676: Uint32 value, numreg, curreg;
1.1 root 1677:
1678: value = (ea_mode >> 3) & BITMASK(3);
1679: numreg = ea_mode & BITMASK(3);
1680: switch (value) {
1681: case 0:
1682: /* (Rx)-Nx */
1.1.1.6 root 1683: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1684: dsp_update_rn(numreg, -dsp_core.registers[DSP_REG_N0+numreg]);
1.1 root 1685: break;
1686: case 1:
1687: /* (Rx)+Nx */
1.1.1.6 root 1688: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1689: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1.1 root 1690: break;
1691: case 2:
1692: /* (Rx)- */
1.1.1.6 root 1693: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1694: dsp_update_rn(numreg, -1);
1695: break;
1696: case 3:
1697: /* (Rx)+ */
1.1.1.6 root 1698: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1.1.12! root 1699: dsp_update_rn(numreg, 1);
1.1 root 1700: break;
1701: case 4:
1702: /* (Rx) */
1.1.1.6 root 1703: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1704: break;
1705: case 5:
1706: /* (Rx+Nx) */
1.1.1.6 root 1707: dsp_core.instr_cycle += 2;
1708: curreg = dsp_core.registers[DSP_REG_R0+numreg];
1709: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1710: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1711: dsp_core.registers[DSP_REG_R0+numreg] = curreg;
1.1 root 1712: break;
1713: case 6:
1714: /* aa */
1.1.1.6 root 1715: dsp_core.instr_cycle += 2;
1716: *dst_addr = read_memory_p(dsp_core.pc+1);
1.1 root 1717: cur_inst_len++;
1718: if (numreg != 0) {
1719: return 1; /* immediate value */
1720: }
1721: break;
1722: case 7:
1723: /* -(Rx) */
1.1.1.6 root 1724: dsp_core.instr_cycle += 2;
1.1 root 1725: dsp_update_rn(numreg, -1);
1.1.1.6 root 1726: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1727: break;
1728: }
1729: /* address */
1730: return 0;
1731: }
1732:
1733: /**********************************
1734: * Condition code test
1735: **********************************/
1736:
1.1.1.2 root 1737: static int dsp_calc_cc(Uint32 cc_code)
1.1 root 1738: {
1.1.1.4 root 1739: Uint16 value1, value2, value3;
1.1 root 1740:
1.1.1.4 root 1741: switch (cc_code) {
1742: case 0: /* CC (HS) */
1.1.1.6 root 1743: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1.1.1.4 root 1744: return (value1==0);
1745: case 1: /* GE */
1.1.1.6 root 1746: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1747: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1.1.1.4 root 1748: return ((value1 ^ value2) == 0);
1749: case 2: /* NE */
1.1.1.6 root 1750: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_Z);
1.1.1.4 root 1751: return (value1==0);
1752: case 3: /* PL */
1.1.1.6 root 1753: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_N);
1.1.1.4 root 1754: return (value1==0);
1755: case 4: /* NN */
1.1.1.6 root 1756: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1757: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1758: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1.1.1.4 root 1759: return ((value1 | (value2 & value3)) == 0);
1760: case 5: /* EC */
1.1.1.6 root 1761: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_E);
1.1.1.4 root 1762: return (value1==0);
1763: case 6: /* LC */
1.1.1.6 root 1764: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_L);
1.1.1.4 root 1765: return (value1==0);
1.1.1.11 root 1766: case 7: /* GT */
1.1.1.6 root 1767: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1768: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1769: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1770: return ((value3 | (value1 ^ value2)) == 0);
1771: case 8: /* CS (LO) */
1.1.1.6 root 1772: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1.1.1.4 root 1773: return (value1==1);
1774: case 9: /* LT */
1.1.1.6 root 1775: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1776: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1.1.1.4 root 1777: return ((value1 ^ value2) == 1);
1778: case 10: /* EQ */
1.1.1.6 root 1779: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1780: return (value1==1);
1781: case 11: /* MI */
1.1.1.6 root 1782: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1.1.1.4 root 1783: return (value1==1);
1784: case 12: /* NR */
1.1.1.6 root 1785: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1786: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1787: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1.1.1.4 root 1788: return ((value1 | (value2 & value3)) == 1);
1789: case 13: /* ES */
1.1.1.6 root 1790: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_E) & 1;
1.1.1.4 root 1791: return (value1==1);
1792: case 14: /* LS */
1.1.1.6 root 1793: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_L) & 1;
1.1.1.4 root 1794: return (value1==1);
1795: case 15: /* LE */
1.1.1.6 root 1796: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1797: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1798: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1799: return ((value3 | (value1 ^ value2)) == 1);
1800: }
1801: return 0;
1.1 root 1802: }
1803:
1804: /**********************************
1805: * Highbyte opcodes dispatchers
1806: **********************************/
1807:
1808: static void opcode8h_0(void)
1809: {
1.1.1.4 root 1810: switch(cur_inst) {
1811: case 0x000000:
1812: dsp_nop();
1.1 root 1813: break;
1.1.1.4 root 1814: case 0x000004:
1815: dsp_rti();
1.1 root 1816: break;
1.1.1.4 root 1817: case 0x000005:
1818: dsp_illegal();
1.1 root 1819: break;
1.1.1.4 root 1820: case 0x000006:
1821: dsp_swi();
1822: break;
1823: case 0x00000c:
1824: dsp_rts();
1825: break;
1826: case 0x000084:
1827: dsp_reset();
1828: break;
1829: case 0x000086:
1830: dsp_wait();
1831: break;
1832: case 0x000087:
1833: dsp_stop();
1834: break;
1835: case 0x00008c:
1836: dsp_enddo();
1.1 root 1837: break;
1.1.1.10 root 1838: default:
1839: dsp_undefined();
1840: break;
1.1 root 1841: }
1842: }
1843:
1844: /**********************************
1845: * Non-parallel moves instructions
1846: **********************************/
1847:
1848: static void dsp_undefined(void)
1849: {
1.1.1.6 root 1850: if (isDsp_in_disasm_mode == false) {
1851: cur_inst_len = 0;
1852: fprintf(stderr, "Dsp: 0x%04x: 0x%06x Illegal instruction\n",dsp_core.pc, cur_inst);
1.1.1.7 root 1853: /* Add some artificial CPU cycles to avoid being stuck in an infinite loop */
1.1.1.6 root 1854: dsp_core.instr_cycle += 100;
1855: }
1856: else {
1857: cur_inst_len = 1;
1858: dsp_core.instr_cycle = 0;
1859: }
1.1.1.10 root 1860: if (ExceptionDebugMask & EXCEPT_DSP) {
1.1.1.9 root 1861: DebugUI(REASON_DSP_EXCEPTION);
1862: }
1.1 root 1863: }
1864:
1865: static void dsp_andi(void)
1866: {
1.1.1.2 root 1867: Uint32 regnum, value;
1.1 root 1868:
1869: value = (cur_inst >> 8) & BITMASK(8);
1870: regnum = cur_inst & BITMASK(2);
1871: switch(regnum) {
1872: case 0:
1873: /* mr */
1.1.1.6 root 1874: dsp_core.registers[DSP_REG_SR] &= (value<<8)|BITMASK(8);
1.1 root 1875: break;
1876: case 1:
1877: /* ccr */
1.1.1.6 root 1878: dsp_core.registers[DSP_REG_SR] &= (BITMASK(8)<<8)|value;
1.1 root 1879: break;
1880: case 2:
1881: /* omr */
1.1.1.6 root 1882: dsp_core.registers[DSP_REG_OMR] &= value;
1.1 root 1883: break;
1884: }
1885: }
1886:
1.1.1.4 root 1887: static void dsp_bchg_aa(void)
1.1 root 1888: {
1.1.1.4 root 1889: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 1890:
1.1 root 1891: memspace = (cur_inst>>6) & 1;
1892: value = (cur_inst>>8) & BITMASK(6);
1893: numbit = cur_inst & BITMASK(5);
1894:
1.1.1.4 root 1895: addr = value;
1896: value = read_memory(memspace, addr);
1897: newcarry = (value>>numbit) & 1;
1898: if (newcarry) {
1899: value -= (1<<numbit);
1900: } else {
1901: value += (1<<numbit);
1.1 root 1902: }
1.1.1.4 root 1903: write_memory(memspace, addr, value);
1.1 root 1904:
1905: /* Set carry */
1.1.1.6 root 1906: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1907: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1908:
1.1.1.6 root 1909: dsp_core.instr_cycle += 2;
1.1 root 1910: }
1911:
1.1.1.4 root 1912: static void dsp_bchg_ea(void)
1.1 root 1913: {
1.1.1.4 root 1914: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 1915:
1.1 root 1916: memspace = (cur_inst>>6) & 1;
1917: value = (cur_inst>>8) & BITMASK(6);
1918: numbit = cur_inst & BITMASK(5);
1919:
1.1.1.4 root 1920: dsp_calc_ea(value, &addr);
1921: value = read_memory(memspace, addr);
1922: newcarry = (value>>numbit) & 1;
1923: if (newcarry) {
1924: value -= (1<<numbit);
1925: } else {
1926: value += (1<<numbit);
1.1 root 1927: }
1.1.1.4 root 1928: write_memory(memspace, addr, value);
1.1 root 1929:
1930: /* Set carry */
1.1.1.6 root 1931: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1932: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1933:
1.1.1.6 root 1934: dsp_core.instr_cycle += 2;
1.1 root 1935: }
1936:
1.1.1.4 root 1937: static void dsp_bchg_pp(void)
1.1 root 1938: {
1.1.1.4 root 1939: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 1940:
1.1 root 1941: memspace = (cur_inst>>6) & 1;
1942: value = (cur_inst>>8) & BITMASK(6);
1943: numbit = cur_inst & BITMASK(5);
1944:
1.1.1.4 root 1945: addr = 0xffc0 + value;
1946: value = read_memory(memspace, addr);
1947: newcarry = (value>>numbit) & 1;
1948: if (newcarry) {
1949: value -= (1<<numbit);
1950: } else {
1951: value += (1<<numbit);
1.1 root 1952: }
1.1.1.4 root 1953: write_memory(memspace, addr, value);
1.1 root 1954:
1955: /* Set carry */
1.1.1.6 root 1956: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1957: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1958:
1.1.1.6 root 1959: dsp_core.instr_cycle += 2;
1.1 root 1960: }
1961:
1.1.1.4 root 1962: static void dsp_bchg_reg(void)
1.1 root 1963: {
1.1.1.4 root 1964: Uint32 value, numreg, newcarry, numbit;
1.1.1.11 root 1965:
1.1.1.4 root 1966: numreg = (cur_inst>>8) & BITMASK(6);
1.1 root 1967: numbit = cur_inst & BITMASK(5);
1968:
1.1.1.4 root 1969: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
1970: dsp_pm_read_accu24(numreg, &value);
1971: } else {
1.1.1.6 root 1972: value = dsp_core.registers[numreg];
1.1 root 1973: }
1974:
1.1.1.4 root 1975: newcarry = (value>>numbit) & 1;
1976: if (newcarry) {
1977: value -= (1<<numbit);
1978: } else {
1979: value += (1<<numbit);
1980: }
1981:
1982: dsp_write_reg(numreg, value);
1983:
1.1 root 1984: /* Set carry */
1.1.1.6 root 1985: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1986: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1987:
1.1.1.6 root 1988: dsp_core.instr_cycle += 2;
1.1 root 1989: }
1990:
1.1.1.4 root 1991: static void dsp_bclr_aa(void)
1.1 root 1992: {
1.1.1.4 root 1993: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 1994:
1.1.1.4 root 1995: memspace = (cur_inst>>6) & 1;
1996: addr = (cur_inst>>8) & BITMASK(6);
1997: numbit = cur_inst & BITMASK(5);
1.1 root 1998:
1.1.1.4 root 1999: value = read_memory(memspace, addr);
2000: newcarry = (value>>numbit) & 1;
2001: value &= 0xffffffff-(1<<numbit);
2002: write_memory(memspace, addr, value);
1.1.1.2 root 2003:
1.1.1.4 root 2004: /* Set carry */
1.1.1.6 root 2005: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2006: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 2007:
1.1.1.6 root 2008: dsp_core.instr_cycle += 2;
1.1.1.4 root 2009: }
1.1 root 2010:
1.1.1.4 root 2011: static void dsp_bclr_ea(void)
2012: {
2013: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2014:
1.1.1.4 root 2015: memspace = (cur_inst>>6) & 1;
2016: value = (cur_inst>>8) & BITMASK(6);
2017: numbit = cur_inst & BITMASK(5);
1.1 root 2018:
1.1.1.4 root 2019: dsp_calc_ea(value, &addr);
2020: value = read_memory(memspace, addr);
2021: newcarry = (value>>numbit) & 1;
2022: value &= 0xffffffff-(1<<numbit);
2023: write_memory(memspace, addr, value);
1.1.1.2 root 2024:
1.1.1.4 root 2025: /* Set carry */
1.1.1.6 root 2026: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2027: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2028:
1.1.1.6 root 2029: dsp_core.instr_cycle += 2;
1.1 root 2030: }
2031:
1.1.1.4 root 2032: static void dsp_bclr_pp(void)
2033: {
2034: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2035:
1.1.1.4 root 2036: memspace = (cur_inst>>6) & 1;
2037: value = (cur_inst>>8) & BITMASK(6);
2038: numbit = cur_inst & BITMASK(5);
1.1.1.3 root 2039:
1.1.1.4 root 2040: addr = 0xffc0 + value;
2041: value = read_memory(memspace, addr);
2042: newcarry = (value>>numbit) & 1;
2043: value &= 0xffffffff-(1<<numbit);
2044: write_memory(memspace, addr, value);
1.1.1.3 root 2045:
1.1.1.4 root 2046: /* Set carry */
1.1.1.6 root 2047: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2048: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 2049:
1.1.1.6 root 2050: dsp_core.instr_cycle += 2;
1.1.1.4 root 2051: }
1.1 root 2052:
1.1.1.4 root 2053: static void dsp_bclr_reg(void)
2054: {
2055: Uint32 value, numreg, newcarry, numbit;
1.1.1.11 root 2056:
1.1.1.4 root 2057: numreg = (cur_inst>>8) & BITMASK(6);
2058: numbit = cur_inst & BITMASK(5);
1.1 root 2059:
1.1.1.4 root 2060: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2061: dsp_pm_read_accu24(numreg, &value);
2062: } else {
1.1.1.6 root 2063: value = dsp_core.registers[numreg];
1.1.1.4 root 2064: }
1.1 root 2065:
1.1.1.4 root 2066: newcarry = (value>>numbit) & 1;
2067: value &= 0xffffffff-(1<<numbit);
1.1 root 2068:
1.1.1.4 root 2069: dsp_write_reg(numreg, value);
2070:
2071: /* Set carry */
1.1.1.6 root 2072: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2073: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 2074:
1.1.1.6 root 2075: dsp_core.instr_cycle += 2;
1.1 root 2076: }
2077:
1.1.1.4 root 2078: static void dsp_bset_aa(void)
1.1 root 2079: {
1.1.1.4 root 2080: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2081:
1.1.1.4 root 2082: memspace = (cur_inst>>6) & 1;
2083: value = (cur_inst>>8) & BITMASK(6);
2084: numbit = cur_inst & BITMASK(5);
1.1 root 2085:
1.1.1.4 root 2086: addr = value;
2087: value = read_memory(memspace, addr);
2088: newcarry = (value>>numbit) & 1;
2089: value |= (1<<numbit);
2090: write_memory(memspace, addr, value);
2091:
2092: /* Set carry */
1.1.1.6 root 2093: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2094: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2095:
1.1.1.6 root 2096: dsp_core.instr_cycle += 2;
1.1.1.4 root 2097: }
2098:
2099: static void dsp_bset_ea(void)
2100: {
2101: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2102:
1.1.1.4 root 2103: memspace = (cur_inst>>6) & 1;
2104: value = (cur_inst>>8) & BITMASK(6);
2105: numbit = cur_inst & BITMASK(5);
2106:
2107: dsp_calc_ea(value, &addr);
2108: value = read_memory(memspace, addr);
2109: newcarry = (value>>numbit) & 1;
2110: value |= (1<<numbit);
2111: write_memory(memspace, addr, value);
2112:
2113: /* Set carry */
1.1.1.6 root 2114: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2115: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2116:
1.1.1.6 root 2117: dsp_core.instr_cycle += 2;
1.1.1.4 root 2118: }
2119:
2120: static void dsp_bset_pp(void)
2121: {
2122: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2123:
1.1.1.4 root 2124: memspace = (cur_inst>>6) & 1;
2125: value = (cur_inst>>8) & BITMASK(6);
2126: numbit = cur_inst & BITMASK(5);
2127: addr = 0xffc0 + value;
2128: value = read_memory(memspace, addr);
2129: newcarry = (value>>numbit) & 1;
2130: value |= (1<<numbit);
2131: write_memory(memspace, addr, value);
2132:
2133: /* Set carry */
1.1.1.6 root 2134: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2135: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2136:
1.1.1.6 root 2137: dsp_core.instr_cycle += 2;
1.1.1.4 root 2138: }
2139:
2140: static void dsp_bset_reg(void)
2141: {
2142: Uint32 value, numreg, newcarry, numbit;
1.1.1.11 root 2143:
1.1.1.4 root 2144: numreg = (cur_inst>>8) & BITMASK(6);
2145: numbit = cur_inst & BITMASK(5);
2146:
2147: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2148: dsp_pm_read_accu24(numreg, &value);
2149: } else {
1.1.1.6 root 2150: value = dsp_core.registers[numreg];
1.1.1.4 root 2151: }
2152:
2153: newcarry = (value>>numbit) & 1;
2154: value |= (1<<numbit);
2155:
2156: dsp_write_reg(numreg, value);
2157:
2158: /* Set carry */
1.1.1.6 root 2159: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2160: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2161:
1.1.1.6 root 2162: dsp_core.instr_cycle += 2;
1.1.1.4 root 2163: }
2164:
2165: static void dsp_btst_aa(void)
2166: {
2167: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2168:
1.1.1.4 root 2169: memspace = (cur_inst>>6) & 1;
2170: value = (cur_inst>>8) & BITMASK(6);
2171: numbit = cur_inst & BITMASK(5);
2172:
2173: addr = value;
2174: value = read_memory(memspace, addr);
2175: newcarry = (value>>numbit) & 1;
2176:
2177: /* Set carry */
1.1.1.6 root 2178: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2179: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2180:
1.1.1.6 root 2181: dsp_core.instr_cycle += 2;
1.1.1.4 root 2182: }
2183:
2184: static void dsp_btst_ea(void)
2185: {
2186: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2187:
1.1.1.4 root 2188: memspace = (cur_inst>>6) & 1;
2189: value = (cur_inst>>8) & BITMASK(6);
2190: numbit = cur_inst & BITMASK(5);
2191:
2192: dsp_calc_ea(value, &addr);
2193: value = read_memory(memspace, addr);
2194: newcarry = (value>>numbit) & 1;
2195:
2196: /* Set carry */
1.1.1.6 root 2197: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2198: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2199:
1.1.1.6 root 2200: dsp_core.instr_cycle += 2;
1.1.1.4 root 2201: }
2202:
2203: static void dsp_btst_pp(void)
2204: {
2205: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2206:
1.1.1.4 root 2207: memspace = (cur_inst>>6) & 1;
2208: value = (cur_inst>>8) & BITMASK(6);
2209: numbit = cur_inst & BITMASK(5);
2210:
2211: addr = 0xffc0 + value;
2212: value = read_memory(memspace, addr);
2213: newcarry = (value>>numbit) & 1;
2214:
2215: /* Set carry */
1.1.1.6 root 2216: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2217: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2218:
1.1.1.6 root 2219: dsp_core.instr_cycle += 2;
1.1.1.4 root 2220: }
2221:
2222: static void dsp_btst_reg(void)
2223: {
2224: Uint32 value, numreg, newcarry, numbit;
1.1.1.11 root 2225:
1.1.1.4 root 2226: numreg = (cur_inst>>8) & BITMASK(6);
2227: numbit = cur_inst & BITMASK(5);
2228:
2229: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2230: dsp_pm_read_accu24(numreg, &value);
2231: } else {
1.1.1.6 root 2232: value = dsp_core.registers[numreg];
1.1.1.4 root 2233: }
2234:
2235: newcarry = (value>>numbit) & 1;
2236:
2237: /* Set carry */
1.1.1.6 root 2238: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2239: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2240:
1.1.1.6 root 2241: dsp_core.instr_cycle += 2;
1.1.1.4 root 2242: }
2243:
2244: static void dsp_div(void)
2245: {
2246: Uint32 srcreg, destreg, source[3], dest[3];
2247: Uint16 newsr;
2248:
2249: srcreg = DSP_REG_NULL;
2250: switch((cur_inst>>4) & BITMASK(2)) {
2251: case 0: srcreg = DSP_REG_X0; break;
2252: case 1: srcreg = DSP_REG_Y0; break;
2253: case 2: srcreg = DSP_REG_X1; break;
2254: case 3: srcreg = DSP_REG_Y1; break;
2255: }
1.1.1.7 root 2256: source[2] = 0;
2257: source[1] = dsp_core.registers[srcreg];
2258: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.4 root 2259:
1.1.1.7 root 2260: destreg = DSP_REG_A + ((cur_inst>>3) & 1);
2261: if (destreg == DSP_REG_A) {
2262: dest[0] = dsp_core.registers[DSP_REG_A2];
2263: dest[1] = dsp_core.registers[DSP_REG_A1];
2264: dest[2] = dsp_core.registers[DSP_REG_A0];
2265: }
2266: else {
2267: dest[0] = dsp_core.registers[DSP_REG_B2];
2268: dest[1] = dsp_core.registers[DSP_REG_B1];
2269: dest[2] = dsp_core.registers[DSP_REG_B0];
2270: }
1.1.1.4 root 2271:
2272: if (((dest[0]>>7) & 1) ^ ((source[1]>>23) & 1)) {
2273: /* D += S */
2274: newsr = dsp_asl56(dest);
2275: dsp_add56(source, dest);
2276: } else {
2277: /* D -= S */
2278: newsr = dsp_asl56(dest);
2279: dsp_sub56(source, dest);
2280: }
2281:
1.1.1.6 root 2282: dest[2] |= (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1.1.4 root 2283:
1.1.1.7 root 2284: if (destreg == DSP_REG_A) {
2285: dsp_core.registers[DSP_REG_A2] = dest[0];
2286: dsp_core.registers[DSP_REG_A1] = dest[1];
2287: dsp_core.registers[DSP_REG_A0] = dest[2];
2288: }
2289: else {
2290: dsp_core.registers[DSP_REG_B2] = dest[0];
2291: dsp_core.registers[DSP_REG_B1] = dest[1];
2292: dsp_core.registers[DSP_REG_B0] = dest[2];
2293: }
1.1.1.11 root 2294:
1.1.1.6 root 2295: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
2296: dsp_core.registers[DSP_REG_SR] |= (1-((dest[0]>>7) & 1))<<DSP_SR_C;
2297: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_L);
2298: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_V);
1.1.1.4 root 2299: }
2300:
2301: /*
2302: DO instruction parameter encoding
2303:
2304: xxxxxxxx 00xxxxxx 0xxxxxxx aa
2305: xxxxxxxx 01xxxxxx 0xxxxxxx ea
2306: xxxxxxxx YYxxxxxx 1xxxxxxx imm
2307: xxxxxxxx 11xxxxxx 0xxxxxxx reg
2308: */
2309:
2310: static void dsp_do_aa(void)
2311: {
2312: Uint32 memspace, addr;
2313:
2314: /* x:aa */
2315: /* y:aa */
2316:
1.1.1.6 root 2317: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2318: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2319: cur_inst_len++;
1.1.1.6 root 2320: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2321: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1 root 2322:
2323: memspace = (cur_inst>>6) & 1;
2324: addr = (cur_inst>>8) & BITMASK(6);
1.1.1.6 root 2325: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
1.1.1.4 root 2326:
1.1.1.6 root 2327: dsp_core.instr_cycle += 4;
1.1 root 2328: }
2329:
1.1.1.3 root 2330: static void dsp_do_imm(void)
1.1 root 2331: {
2332: /* #xx */
1.1.1.3 root 2333:
1.1.1.6 root 2334: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2335: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2336: cur_inst_len++;
1.1.1.6 root 2337: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2338: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2339:
1.1.1.6 root 2340: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
1.1.1.3 root 2341: + ((cur_inst & BITMASK(4))<<8);
1.1.1.4 root 2342:
1.1.1.6 root 2343: dsp_core.instr_cycle += 4;
1.1 root 2344: }
2345:
1.1.1.3 root 2346: static void dsp_do_ea(void)
1.1 root 2347: {
1.1.1.2 root 2348: Uint32 memspace, ea_mode, addr;
1.1 root 2349:
2350: /* x:ea */
2351: /* y:ea */
2352:
1.1.1.6 root 2353: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2354: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2355: cur_inst_len++;
1.1.1.6 root 2356: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2357: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2358:
1.1 root 2359: memspace = (cur_inst>>6) & 1;
2360: ea_mode = (cur_inst>>8) & BITMASK(6);
2361: dsp_calc_ea(ea_mode, &addr);
1.1.1.6 root 2362: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
1.1.1.4 root 2363:
1.1.1.6 root 2364: dsp_core.instr_cycle += 4;
1.1 root 2365: }
2366:
1.1.1.3 root 2367: static void dsp_do_reg(void)
1.1 root 2368: {
1.1.1.2 root 2369: Uint32 numreg;
1.1 root 2370:
2371: /* S */
2372:
1.1.1.6 root 2373: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2374: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2375: cur_inst_len++;
2376:
1.1 root 2377: numreg = (cur_inst>>8) & BITMASK(6);
2378: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11 root 2379: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
1.1 root 2380: } else {
1.1.1.6 root 2381: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
1.1 root 2382: }
1.1.1.6 root 2383: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.4 root 2384:
1.1.1.6 root 2385: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2386: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2387:
1.1.1.6 root 2388: dsp_core.instr_cycle += 4;
1.1 root 2389: }
2390:
2391: static void dsp_enddo(void)
2392: {
1.1.1.4 root 2393: Uint32 saved_pc, saved_sr;
1.1 root 2394:
1.1.1.4 root 2395: dsp_stack_pop(&saved_pc, &saved_sr);
1.1.1.6 root 2396: dsp_core.registers[DSP_REG_SR] &= 0x7f;
2397: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
2398: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
1.1 root 2399: }
2400:
2401: static void dsp_illegal(void)
2402: {
2403: /* Raise interrupt p:0x003e */
1.1.1.5 root 2404: dsp_add_interrupt(DSP_INTER_ILLEGAL);
1.1.1.10 root 2405: if (ExceptionDebugMask & EXCEPT_DSP) {
1.1.1.9 root 2406: DebugUI(REASON_DSP_EXCEPTION);
2407: }
1.1 root 2408: }
2409:
1.1.1.4 root 2410: static void dsp_jcc_imm(void)
1.1 root 2411: {
1.1.1.4 root 2412: Uint32 cc_code, newpc;
1.1 root 2413:
1.1.1.4 root 2414: newpc = cur_inst & BITMASK(12);
2415: cc_code=(cur_inst>>12) & BITMASK(4);
2416: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2417: dsp_core.pc = newpc;
1.1.1.4 root 2418: cur_inst_len = 0;
2419: }
2420:
1.1.1.6 root 2421: dsp_core.instr_cycle += 2;
1.1.1.4 root 2422: }
2423:
2424: static void dsp_jcc_ea(void)
2425: {
2426: Uint32 newpc, cc_code;
2427:
2428: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2429: cc_code=cur_inst & BITMASK(4);
1.1 root 2430:
2431: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2432: dsp_core.pc = newpc;
1.1 root 2433: cur_inst_len = 0;
2434: }
1.1.1.4 root 2435:
1.1.1.6 root 2436: dsp_core.instr_cycle += 2;
1.1 root 2437: }
2438:
1.1.1.4 root 2439: static void dsp_jclr_aa(void)
1.1 root 2440: {
1.1.1.4 root 2441: Uint32 memspace, addr, value, numbit, newaddr;
1.1.1.11 root 2442:
1.1 root 2443: memspace = (cur_inst>>6) & 1;
1.1.1.4 root 2444: addr = (cur_inst>>8) & BITMASK(6);
1.1 root 2445: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2446: value = read_memory(memspace, addr);
1.1.1.6 root 2447: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2448:
1.1.1.6 root 2449: dsp_core.instr_cycle += 4;
1.1 root 2450:
1.1.1.4 root 2451: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2452: dsp_core.pc = newaddr;
1.1.1.4 root 2453: cur_inst_len = 0;
2454: return;
1.1.1.11 root 2455: }
1.1.1.2 root 2456: ++cur_inst_len;
1.1.1.4 root 2457: }
2458:
2459: static void dsp_jclr_ea(void)
2460: {
2461: Uint32 memspace, addr, value, numbit, newaddr;
1.1.1.11 root 2462:
1.1.1.4 root 2463: memspace = (cur_inst>>6) & 1;
2464: value = (cur_inst>>8) & BITMASK(6);
2465: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2466: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2467:
1.1.1.4 root 2468: dsp_calc_ea(value, &addr);
2469: value = read_memory(memspace, addr);
2470:
1.1.1.6 root 2471: dsp_core.instr_cycle += 4;
1.1 root 2472:
2473: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2474: dsp_core.pc = newaddr;
1.1.1.4 root 2475: cur_inst_len = 0;
2476: return;
1.1.1.11 root 2477: }
1.1.1.4 root 2478: ++cur_inst_len;
2479: }
1.1 root 2480:
1.1.1.4 root 2481: static void dsp_jclr_pp(void)
2482: {
2483: Uint32 memspace, addr, value, numbit, newaddr;
1.1.1.11 root 2484:
1.1.1.4 root 2485: memspace = (cur_inst>>6) & 1;
2486: value = (cur_inst>>8) & BITMASK(6);
2487: numbit = cur_inst & BITMASK(5);
2488: addr = 0xffc0 + value;
2489: value = read_memory(memspace, addr);
1.1.1.6 root 2490: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2491:
1.1.1.6 root 2492: dsp_core.instr_cycle += 4;
1.1 root 2493:
1.1.1.4 root 2494: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2495: dsp_core.pc = newaddr;
1.1.1.4 root 2496: cur_inst_len = 0;
2497: return;
1.1.1.11 root 2498: }
1.1.1.4 root 2499: ++cur_inst_len;
2500: }
1.1.1.2 root 2501:
1.1.1.4 root 2502: static void dsp_jclr_reg(void)
2503: {
2504: Uint32 value, numreg, numbit, newaddr;
1.1.1.11 root 2505:
1.1.1.4 root 2506: numreg = (cur_inst>>8) & BITMASK(6);
2507: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2508: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2509:
1.1.1.4 root 2510: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2511: dsp_pm_read_accu24(numreg, &value);
2512: } else {
1.1.1.6 root 2513: value = dsp_core.registers[numreg];
1.1.1.4 root 2514: }
1.1 root 2515:
1.1.1.6 root 2516: dsp_core.instr_cycle += 4;
1.1.1.4 root 2517:
2518: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2519: dsp_core.pc = newaddr;
1.1 root 2520: cur_inst_len = 0;
2521: return;
1.1.1.11 root 2522: }
1.1.1.4 root 2523: ++cur_inst_len;
1.1 root 2524: }
2525:
1.1.1.4 root 2526: static void dsp_jmp_ea(void)
1.1 root 2527: {
1.1.1.2 root 2528: Uint32 newpc;
1.1 root 2529:
1.1.1.4 root 2530: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &newpc);
1.1 root 2531: cur_inst_len = 0;
1.1.1.6 root 2532: dsp_core.pc = newpc;
1.1 root 2533:
1.1.1.6 root 2534: dsp_core.instr_cycle += 2;
1.1.1.4 root 2535: }
2536:
2537: static void dsp_jmp_imm(void)
2538: {
2539: Uint32 newpc;
1.1 root 2540:
1.1.1.4 root 2541: newpc = cur_inst & BITMASK(12);
2542: cur_inst_len = 0;
1.1.1.6 root 2543: dsp_core.pc = newpc;
1.1.1.4 root 2544:
1.1.1.6 root 2545: dsp_core.instr_cycle += 2;
1.1 root 2546: }
2547:
1.1.1.4 root 2548: static void dsp_jscc_ea(void)
1.1 root 2549: {
1.1.1.2 root 2550: Uint32 newpc, cc_code;
1.1 root 2551:
1.1.1.4 root 2552: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2553: cc_code=cur_inst & BITMASK(4);
2554:
2555: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2556: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2557: dsp_core.pc = newpc;
1.1.1.4 root 2558: cur_inst_len = 0;
1.1.1.11 root 2559: }
1.1.1.4 root 2560:
1.1.1.6 root 2561: dsp_core.instr_cycle += 2;
1.1.1.4 root 2562: }
1.1 root 2563:
1.1.1.4 root 2564: static void dsp_jscc_imm(void)
2565: {
2566: Uint32 cc_code, newpc;
2567:
2568: newpc = cur_inst & BITMASK(12);
2569: cc_code=(cur_inst>>12) & BITMASK(4);
1.1 root 2570: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2571: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2572: dsp_core.pc = newpc;
1.1.1.4 root 2573: cur_inst_len = 0;
1.1.1.11 root 2574: }
1.1.1.4 root 2575:
1.1.1.6 root 2576: dsp_core.instr_cycle += 2;
1.1.1.4 root 2577: }
1.1 root 2578:
1.1.1.4 root 2579: static void dsp_jsclr_aa(void)
2580: {
2581: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2582:
1.1.1.4 root 2583: memspace = (cur_inst>>6) & 1;
2584: addr = (cur_inst>>8) & BITMASK(6);
2585: numbit = cur_inst & BITMASK(5);
2586: value = read_memory(memspace, addr);
1.1.1.6 root 2587: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2588:
1.1.1.6 root 2589: dsp_core.instr_cycle += 4;
1.1.1.11 root 2590:
1.1.1.4 root 2591: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2592: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2593: newpc = newaddr;
1.1.1.6 root 2594: dsp_core.pc = newpc;
1.1 root 2595: cur_inst_len = 0;
1.1.1.4 root 2596: return;
1.1.1.11 root 2597: }
1.1.1.4 root 2598: ++cur_inst_len;
1.1 root 2599: }
2600:
1.1.1.4 root 2601: static void dsp_jsclr_ea(void)
1.1 root 2602: {
1.1.1.4 root 2603: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2604:
1.1 root 2605: memspace = (cur_inst>>6) & 1;
2606: value = (cur_inst>>8) & BITMASK(6);
2607: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2608: dsp_calc_ea(value, &addr);
2609: value = read_memory(memspace, addr);
1.1.1.6 root 2610: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2611:
1.1.1.6 root 2612: dsp_core.instr_cycle += 4;
1.1.1.11 root 2613:
1.1.1.4 root 2614: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2615: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2616: newpc = newaddr;
1.1.1.6 root 2617: dsp_core.pc = newpc;
1.1.1.4 root 2618: cur_inst_len = 0;
2619: return;
1.1.1.11 root 2620: }
1.1.1.2 root 2621: ++cur_inst_len;
1.1.1.4 root 2622: }
2623:
2624: static void dsp_jsclr_pp(void)
2625: {
2626: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2627:
1.1.1.4 root 2628: memspace = (cur_inst>>6) & 1;
2629: value = (cur_inst>>8) & BITMASK(6);
2630: numbit = cur_inst & BITMASK(5);
2631: addr = 0xffc0 + value;
2632: value = read_memory(memspace, addr);
1.1.1.6 root 2633: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2634:
1.1.1.6 root 2635: dsp_core.instr_cycle += 4;
1.1.1.11 root 2636:
1.1 root 2637: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2638: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2639: newpc = newaddr;
1.1.1.6 root 2640: dsp_core.pc = newpc;
1.1.1.4 root 2641: cur_inst_len = 0;
2642: return;
1.1.1.11 root 2643: }
1.1.1.4 root 2644: ++cur_inst_len;
2645: }
2646:
2647: static void dsp_jsclr_reg(void)
2648: {
2649: Uint32 value, numreg, newpc, numbit, newaddr;
1.1.1.11 root 2650:
1.1.1.4 root 2651: numreg = (cur_inst>>8) & BITMASK(6);
2652: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2653: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2654:
1.1.1.4 root 2655: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2656: dsp_pm_read_accu24(numreg, &value);
2657: } else {
1.1.1.6 root 2658: value = dsp_core.registers[numreg];
1.1.1.4 root 2659: }
2660:
1.1.1.6 root 2661: dsp_core.instr_cycle += 4;
1.1.1.11 root 2662:
1.1.1.4 root 2663: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2664: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2665: newpc = newaddr;
1.1.1.6 root 2666: dsp_core.pc = newpc;
1.1 root 2667: cur_inst_len = 0;
1.1.1.4 root 2668: return;
1.1.1.11 root 2669: }
1.1.1.4 root 2670: ++cur_inst_len;
1.1 root 2671: }
2672:
1.1.1.4 root 2673: static void dsp_jset_aa(void)
1.1 root 2674: {
1.1.1.4 root 2675: Uint32 memspace, addr, value, numbit, newpc, newaddr;
1.1.1.11 root 2676:
1.1.1.4 root 2677: memspace = (cur_inst>>6) & 1;
2678: addr = (cur_inst>>8) & BITMASK(6);
2679: numbit = cur_inst & BITMASK(5);
2680: value = read_memory(memspace, addr);
1.1.1.6 root 2681: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2682:
1.1.1.6 root 2683: dsp_core.instr_cycle += 4;
1.1.1.11 root 2684:
1.1.1.4 root 2685: if (value & (1<<numbit)) {
2686: newpc = newaddr;
1.1.1.6 root 2687: dsp_core.pc = newpc;
1.1.1.4 root 2688: cur_inst_len=0;
2689: return;
1.1.1.11 root 2690: }
1.1.1.4 root 2691: ++cur_inst_len;
2692: }
2693:
2694: static void dsp_jset_ea(void)
2695: {
2696: Uint32 memspace, addr, value, numbit, newpc, newaddr;
1.1.1.11 root 2697:
1.1 root 2698: memspace = (cur_inst>>6) & 1;
2699: value = (cur_inst>>8) & BITMASK(6);
2700: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2701: dsp_calc_ea(value, &addr);
2702: value = read_memory(memspace, addr);
1.1.1.6 root 2703: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2704:
1.1.1.6 root 2705: dsp_core.instr_cycle += 4;
1.1.1.7 root 2706:
1.1.1.4 root 2707: if (value & (1<<numbit)) {
2708: newpc = newaddr;
1.1.1.6 root 2709: dsp_core.pc = newpc;
1.1.1.4 root 2710: cur_inst_len=0;
2711: return;
1.1.1.11 root 2712: }
1.1.1.4 root 2713: ++cur_inst_len;
2714: }
1.1 root 2715:
1.1.1.4 root 2716: static void dsp_jset_pp(void)
2717: {
2718: Uint32 memspace, addr, value, numbit, newpc, newaddr;
1.1.1.11 root 2719:
1.1.1.4 root 2720: memspace = (cur_inst>>6) & 1;
2721: value = (cur_inst>>8) & BITMASK(6);
2722: numbit = cur_inst & BITMASK(5);
2723: addr = 0xffc0 + value;
2724: value = read_memory(memspace, addr);
1.1.1.6 root 2725: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2726:
1.1.1.6 root 2727: dsp_core.instr_cycle += 4;
1.1.1.11 root 2728:
1.1.1.4 root 2729: if (value & (1<<numbit)) {
2730: newpc = newaddr;
1.1.1.6 root 2731: dsp_core.pc = newpc;
1.1.1.4 root 2732: cur_inst_len=0;
2733: return;
1.1.1.11 root 2734: }
1.1.1.4 root 2735: ++cur_inst_len;
2736: }
2737:
2738: static void dsp_jset_reg(void)
2739: {
2740: Uint32 value, numreg, numbit, newpc, newaddr;
1.1.1.11 root 2741:
1.1.1.4 root 2742: numreg = (cur_inst>>8) & BITMASK(6);
2743: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2744: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2745:
1.1.1.4 root 2746: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2747: dsp_pm_read_accu24(numreg, &value);
2748: } else {
1.1.1.6 root 2749: value = dsp_core.registers[numreg];
1.1.1.4 root 2750: }
2751:
1.1.1.6 root 2752: dsp_core.instr_cycle += 4;
1.1.1.11 root 2753:
1.1.1.4 root 2754: if (value & (1<<numbit)) {
2755: newpc = newaddr;
1.1.1.6 root 2756: dsp_core.pc = newpc;
1.1.1.4 root 2757: cur_inst_len=0;
2758: return;
1.1.1.11 root 2759: }
1.1.1.4 root 2760: ++cur_inst_len;
2761: }
2762:
2763: static void dsp_jsr_imm(void)
2764: {
2765: Uint32 newpc;
2766:
2767: newpc = cur_inst & BITMASK(12);
2768:
1.1.1.6 root 2769: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2770: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2771: }
2772: else {
1.1.1.6 root 2773: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1.1.1.4 root 2774: }
2775:
1.1.1.6 root 2776: dsp_core.pc = newpc;
1.1.1.4 root 2777: cur_inst_len = 0;
2778:
1.1.1.6 root 2779: dsp_core.instr_cycle += 2;
1.1.1.4 root 2780: }
2781:
2782: static void dsp_jsr_ea(void)
2783: {
2784: Uint32 newpc;
2785:
2786: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&newpc);
2787:
1.1.1.6 root 2788: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2789: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2790: }
2791: else {
1.1.1.6 root 2792: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1.1.1.4 root 2793: }
2794:
1.1.1.6 root 2795: dsp_core.pc = newpc;
1.1.1.4 root 2796: cur_inst_len = 0;
2797:
1.1.1.6 root 2798: dsp_core.instr_cycle += 2;
1.1.1.4 root 2799: }
2800:
2801: static void dsp_jsset_aa(void)
2802: {
2803: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2804:
1.1.1.4 root 2805: memspace = (cur_inst>>6) & 1;
2806: addr = (cur_inst>>8) & BITMASK(6);
2807: numbit = cur_inst & BITMASK(5);
2808: value = read_memory(memspace, addr);
1.1.1.6 root 2809: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2810:
1.1.1.6 root 2811: dsp_core.instr_cycle += 4;
1.1.1.4 root 2812:
2813: if (value & (1<<numbit)) {
1.1.1.6 root 2814: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2815: newpc = newaddr;
1.1.1.6 root 2816: dsp_core.pc = newpc;
1.1.1.4 root 2817: cur_inst_len = 0;
2818: return;
1.1.1.11 root 2819: }
1.1.1.4 root 2820: ++cur_inst_len;
2821: }
2822:
2823: static void dsp_jsset_ea(void)
2824: {
2825: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2826:
1.1.1.4 root 2827: memspace = (cur_inst>>6) & 1;
2828: value = (cur_inst>>8) & BITMASK(6);
2829: numbit = cur_inst & BITMASK(5);
2830: dsp_calc_ea(value, &addr);
2831: value = read_memory(memspace, addr);
1.1.1.6 root 2832: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2833:
1.1.1.6 root 2834: dsp_core.instr_cycle += 4;
1.1 root 2835:
2836: if (value & (1<<numbit)) {
1.1.1.6 root 2837: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2838: newpc = newaddr;
1.1.1.6 root 2839: dsp_core.pc = newpc;
1.1.1.4 root 2840: cur_inst_len = 0;
2841: return;
1.1.1.11 root 2842: }
1.1.1.4 root 2843: ++cur_inst_len;
1.1 root 2844: }
2845:
1.1.1.4 root 2846: static void dsp_jsset_pp(void)
1.1 root 2847: {
1.1.1.4 root 2848: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2849:
1.1.1.4 root 2850: memspace = (cur_inst>>6) & 1;
2851: value = (cur_inst>>8) & BITMASK(6);
2852: numbit = cur_inst & BITMASK(5);
2853: addr = 0xffc0 + value;
2854: value = read_memory(memspace, addr);
1.1.1.6 root 2855: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2856:
1.1.1.6 root 2857: dsp_core.instr_cycle += 4;
1.1 root 2858:
1.1.1.4 root 2859: if (value & (1<<numbit)) {
1.1.1.6 root 2860: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2861: newpc = newaddr;
1.1.1.6 root 2862: dsp_core.pc = newpc;
1.1.1.4 root 2863: cur_inst_len = 0;
2864: return;
1.1.1.11 root 2865: }
1.1.1.4 root 2866: ++cur_inst_len;
1.1 root 2867: }
2868:
1.1.1.4 root 2869: static void dsp_jsset_reg(void)
1.1 root 2870: {
1.1.1.4 root 2871: Uint32 value, numreg, newpc, numbit, newaddr;
1.1.1.11 root 2872:
1.1.1.4 root 2873: numreg = (cur_inst>>8) & BITMASK(6);
1.1 root 2874: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2875: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2876:
1.1.1.4 root 2877: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2878: dsp_pm_read_accu24(numreg, &value);
2879: } else {
1.1.1.6 root 2880: value = dsp_core.registers[numreg];
1.1.1.4 root 2881: }
1.1 root 2882:
1.1.1.6 root 2883: dsp_core.instr_cycle += 4;
1.1 root 2884:
2885: if (value & (1<<numbit)) {
1.1.1.6 root 2886: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2887: newpc = newaddr;
1.1.1.6 root 2888: dsp_core.pc = newpc;
1.1 root 2889: cur_inst_len = 0;
1.1.1.4 root 2890: return;
1.1.1.11 root 2891: }
1.1.1.4 root 2892: ++cur_inst_len;
1.1 root 2893: }
2894:
2895: static void dsp_lua(void)
2896: {
1.1.1.2 root 2897: Uint32 value, srcreg, dstreg, srcsave, srcnew;
2898:
1.1 root 2899: srcreg = (cur_inst>>8) & BITMASK(3);
1.1.1.2 root 2900:
1.1.1.6 root 2901: srcsave = dsp_core.registers[DSP_REG_R0+srcreg];
1.1.1.2 root 2902: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &value);
1.1.1.6 root 2903: srcnew = dsp_core.registers[DSP_REG_R0+srcreg];
2904: dsp_core.registers[DSP_REG_R0+srcreg] = srcsave;
1.1.1.2 root 2905:
1.1.1.11 root 2906: if (cur_inst & (1<<3))
2907: dstreg = DSP_REG_N0 + (cur_inst & BITMASK(3));
2908: else
2909: dstreg = DSP_REG_R0 + (cur_inst & BITMASK(3));
1.1 root 2910:
1.1.1.11 root 2911: dsp_core.agu_move_indirect_instr = 1;
2912: dsp_write_reg(dstreg, srcnew);
1.1.1.6 root 2913: dsp_core.instr_cycle += 2;
1.1 root 2914: }
2915:
1.1.1.3 root 2916: static void dsp_movec_reg(void)
1.1 root 2917: {
1.1.1.4 root 2918: Uint32 numreg1, numreg2, value, dummy;
1.1 root 2919:
2920: /* S1,D2 */
2921: /* S2,D1 */
2922:
2923: numreg2 = (cur_inst>>8) & BITMASK(6);
1.1.1.4 root 2924: numreg1 = cur_inst & BITMASK(6);
1.1 root 2925:
1.1.1.11 root 2926: dsp_core.agu_move_indirect_instr = 1;
2927:
1.1 root 2928: if (cur_inst & (1<<15)) {
2929: /* Write D1 */
2930:
2931: if ((numreg2 == DSP_REG_A) || (numreg2 == DSP_REG_B)) {
1.1.1.11 root 2932: dsp_pm_read_accu24(numreg2, &value);
1.1 root 2933: } else {
1.1.1.6 root 2934: value = dsp_core.registers[numreg2];
1.1 root 2935: }
1.1.1.4 root 2936: dsp_write_reg(numreg1, value);
1.1 root 2937: } else {
2938: /* Read S1 */
1.1.1.4 root 2939: if (numreg1 == DSP_REG_SSH) {
2940: dsp_stack_pop(&value, &dummy);
1.1.1.11 root 2941: }
1.1.1.4 root 2942: else {
1.1.1.6 root 2943: value = dsp_core.registers[numreg1];
1.1.1.4 root 2944: }
1.1 root 2945:
1.1.1.11 root 2946: dsp_write_reg(numreg2, value);
1.1 root 2947: }
2948: }
2949:
1.1.1.3 root 2950: static void dsp_movec_aa(void)
1.1 root 2951: {
1.1.1.4 root 2952: Uint32 numreg, addr, memspace, value, dummy;
1.1 root 2953:
2954: /* x:aa,D1 */
2955: /* S1,x:aa */
2956: /* y:aa,D1 */
2957: /* S1,y:aa */
2958:
1.1.1.4 root 2959: numreg = cur_inst & BITMASK(6);
1.1 root 2960: addr = (cur_inst>>8) & BITMASK(6);
2961: memspace = (cur_inst>>6) & 1;
2962:
2963: if (cur_inst & (1<<15)) {
2964: /* Write D1 */
1.1.1.4 root 2965: value = read_memory(memspace, addr);
1.1.1.11 root 2966: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 2967: dsp_write_reg(numreg, value);
1.1 root 2968: } else {
2969: /* Read S1 */
1.1.1.4 root 2970: if (numreg == DSP_REG_SSH) {
2971: dsp_stack_pop(&value, &dummy);
1.1.1.11 root 2972: }
1.1.1.4 root 2973: else {
1.1.1.6 root 2974: value = dsp_core.registers[numreg];
1.1.1.4 root 2975: }
2976: write_memory(memspace, addr, value);
1.1 root 2977: }
2978: }
2979:
1.1.1.3 root 2980: static void dsp_movec_imm(void)
1.1 root 2981: {
1.1.1.4 root 2982: Uint32 numreg, value;
1.1 root 2983:
2984: /* #xx,D1 */
1.1.1.4 root 2985: numreg = cur_inst & BITMASK(6);
2986: value = (cur_inst>>8) & BITMASK(8);
1.1.1.11 root 2987: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 2988: dsp_write_reg(numreg, value);
1.1 root 2989: }
2990:
1.1.1.3 root 2991: static void dsp_movec_ea(void)
1.1 root 2992: {
1.1.1.4 root 2993: Uint32 numreg, addr, memspace, ea_mode, value, dummy;
1.1 root 2994: int retour;
2995:
2996: /* x:ea,D1 */
2997: /* S1,x:ea */
2998: /* y:ea,D1 */
2999: /* S1,y:ea */
3000: /* #xxxx,D1 */
3001:
1.1.1.4 root 3002: numreg = cur_inst & BITMASK(6);
1.1 root 3003: ea_mode = (cur_inst>>8) & BITMASK(6);
3004: memspace = (cur_inst>>6) & 1;
3005:
3006: if (cur_inst & (1<<15)) {
3007: /* Write D1 */
3008: retour = dsp_calc_ea(ea_mode, &addr);
3009: if (retour) {
1.1.1.4 root 3010: value = addr;
1.1 root 3011: } else {
1.1.1.4 root 3012: value = read_memory(memspace, addr);
1.1 root 3013: }
1.1.1.11 root 3014: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3015: dsp_write_reg(numreg, value);
1.1 root 3016: } else {
3017: /* Read S1 */
1.1.1.4 root 3018: dsp_calc_ea(ea_mode, &addr);
3019: if (numreg == DSP_REG_SSH) {
3020: dsp_stack_pop(&value, &dummy);
1.1.1.11 root 3021: }
1.1.1.4 root 3022: else {
1.1.1.6 root 3023: value = dsp_core.registers[numreg];
1.1.1.4 root 3024: }
3025: write_memory(memspace, addr, value);
1.1 root 3026: }
3027: }
3028:
1.1.1.4 root 3029: static void dsp_movem_aa(void)
1.1 root 3030: {
1.1.1.4 root 3031: Uint32 numreg, addr, value, dummy;
1.1 root 3032:
3033: numreg = cur_inst & BITMASK(6);
1.1.1.4 root 3034: addr = (cur_inst>>8) & BITMASK(6);
1.1 root 3035:
1.1.1.4 root 3036: if (cur_inst & (1<<15)) {
3037: /* Write D */
3038: value = read_memory_p(addr);
1.1.1.11 root 3039: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3040: dsp_write_reg(numreg, value);
1.1 root 3041: } else {
1.1.1.4 root 3042: /* Read S */
3043: if (numreg == DSP_REG_SSH) {
3044: dsp_stack_pop(&value, &dummy);
1.1.1.11 root 3045: }
1.1.1.4 root 3046: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11 root 3047: dsp_pm_read_accu24(numreg, &value);
3048: }
1.1.1.4 root 3049: else {
1.1.1.6 root 3050: value = dsp_core.registers[numreg];
1.1.1.4 root 3051: }
3052: write_memory(DSP_SPACE_P, addr, value);
3053: }
1.1 root 3054:
1.1.1.6 root 3055: dsp_core.instr_cycle += 4;
1.1.1.4 root 3056: }
3057:
3058: static void dsp_movem_ea(void)
3059: {
3060: Uint32 numreg, addr, ea_mode, value, dummy;
3061:
3062: numreg = cur_inst & BITMASK(6);
3063: ea_mode = (cur_inst>>8) & BITMASK(6);
3064: dsp_calc_ea(ea_mode, &addr);
1.1 root 3065:
3066: if (cur_inst & (1<<15)) {
3067: /* Write D */
1.1.1.4 root 3068: value = read_memory_p(addr);
1.1.1.11 root 3069: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3070: dsp_write_reg(numreg, value);
1.1 root 3071: } else {
3072: /* Read S */
1.1.1.4 root 3073: if (numreg == DSP_REG_SSH) {
3074: dsp_stack_pop(&value, &dummy);
1.1.1.11 root 3075: }
1.1.1.4 root 3076: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11 root 3077: dsp_pm_read_accu24(numreg, &value);
3078: }
1.1.1.4 root 3079: else {
1.1.1.6 root 3080: value = dsp_core.registers[numreg];
1.1 root 3081: }
3082: write_memory(DSP_SPACE_P, addr, value);
3083: }
3084:
1.1.1.6 root 3085: dsp_core.instr_cycle += 4;
1.1 root 3086: }
3087:
3088: static void dsp_movep_0(void)
3089: {
3090: /* S,x:pp */
3091: /* x:pp,D */
3092: /* S,y:pp */
3093: /* y:pp,D */
1.1.1.11 root 3094:
1.1.1.4 root 3095: Uint32 addr, memspace, numreg, value, dummy;
1.1 root 3096:
3097: addr = 0xffc0 + (cur_inst & BITMASK(6));
3098: memspace = (cur_inst>>16) & 1;
3099: numreg = (cur_inst>>8) & BITMASK(6);
3100:
3101: if (cur_inst & (1<<15)) {
3102: /* Write pp */
3103: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11 root 3104: dsp_pm_read_accu24(numreg, &value);
1.1.1.4 root 3105: }
3106: else if (numreg == DSP_REG_SSH) {
3107: dsp_stack_pop(&value, &dummy);
3108: }
3109: else {
1.1.1.6 root 3110: value = dsp_core.registers[numreg];
1.1 root 3111: }
3112: write_memory(memspace, addr, value);
3113: } else {
3114: /* Read pp */
3115: value = read_memory(memspace, addr);
1.1.1.11 root 3116: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3117: dsp_write_reg(numreg, value);
1.1 root 3118: }
1.1.1.4 root 3119:
1.1.1.6 root 3120: dsp_core.instr_cycle += 2;
1.1 root 3121: }
3122:
3123: static void dsp_movep_1(void)
3124: {
3125: /* p:ea,x:pp */
3126: /* x:pp,p:ea */
3127: /* p:ea,y:pp */
3128: /* y:pp,p:ea */
3129:
1.1.1.2 root 3130: Uint32 xyaddr, memspace, paddr;
1.1 root 3131:
3132: xyaddr = 0xffc0 + (cur_inst & BITMASK(6));
3133: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &paddr);
3134: memspace = (cur_inst>>16) & 1;
3135:
3136: if (cur_inst & (1<<15)) {
3137: /* Write pp */
1.1.1.4 root 3138: write_memory(memspace, xyaddr, read_memory_p(paddr));
1.1 root 3139: } else {
3140: /* Read pp */
3141: write_memory(DSP_SPACE_P, paddr, read_memory(memspace, xyaddr));
3142: }
1.1.1.4 root 3143:
1.1.1.7 root 3144: /* Movep is 4 cycles, but according to the motorola doc, */
3145: /* movep from p memory to x or y peripheral memory takes */
3146: /* 2 more cycles, so +4 cycles at total */
3147: dsp_core.instr_cycle += 4;
1.1 root 3148: }
3149:
1.1.1.4 root 3150: static void dsp_movep_23(void)
1.1 root 3151: {
3152: /* x:ea,x:pp */
3153: /* y:ea,x:pp */
3154: /* #xxxxxx,x:pp */
3155: /* x:pp,x:ea */
3156: /* x:pp,y:pp */
3157: /* x:ea,y:pp */
3158: /* y:ea,y:pp */
3159: /* #xxxxxx,y:pp */
3160: /* y:pp,y:ea */
3161: /* y:pp,x:ea */
3162:
1.1.1.2 root 3163: Uint32 addr, peraddr, easpace, perspace, ea_mode;
1.1 root 3164: int retour;
3165:
3166: peraddr = 0xffc0 + (cur_inst & BITMASK(6));
3167: perspace = (cur_inst>>16) & 1;
1.1.1.11 root 3168:
1.1 root 3169: ea_mode = (cur_inst>>8) & BITMASK(6);
3170: easpace = (cur_inst>>6) & 1;
3171: retour = dsp_calc_ea(ea_mode, &addr);
3172:
3173: if (cur_inst & (1<<15)) {
3174: /* Write pp */
1.1.1.11 root 3175:
1.1 root 3176: if (retour) {
3177: write_memory(perspace, peraddr, addr);
3178: } else {
3179: write_memory(perspace, peraddr, read_memory(easpace, addr));
3180: }
3181: } else {
3182: /* Read pp */
3183: write_memory(easpace, addr, read_memory(perspace, peraddr));
3184: }
1.1.1.4 root 3185:
1.1.1.6 root 3186: dsp_core.instr_cycle += 2;
1.1 root 3187: }
3188:
3189: static void dsp_norm(void)
3190: {
1.1.1.2 root 3191: Uint32 cursr,cur_e, cur_euz, dest[3], numreg, rreg;
3192: Uint16 newsr;
1.1 root 3193:
1.1.1.6 root 3194: cursr = dsp_core.registers[DSP_REG_SR];
1.1 root 3195: cur_e = (cursr>>DSP_SR_E) & 1; /* E */
3196: cur_euz = ~cur_e; /* (not E) and U and (not Z) */
3197: cur_euz &= (cursr>>DSP_SR_U) & 1;
3198: cur_euz &= ~((cursr>>DSP_SR_Z) & 1);
3199: cur_euz &= 1;
3200:
3201: numreg = (cur_inst>>3) & 1;
1.1.1.6 root 3202: dest[0] = dsp_core.registers[DSP_REG_A2+numreg];
3203: dest[1] = dsp_core.registers[DSP_REG_A1+numreg];
3204: dest[2] = dsp_core.registers[DSP_REG_A0+numreg];
1.1 root 3205: rreg = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3206:
3207: if (cur_euz) {
3208: newsr = dsp_asl56(dest);
1.1.1.6 root 3209: --dsp_core.registers[rreg];
3210: dsp_core.registers[rreg] &= BITMASK(16);
1.1 root 3211: } else if (cur_e) {
3212: newsr = dsp_asr56(dest);
1.1.1.6 root 3213: ++dsp_core.registers[rreg];
3214: dsp_core.registers[rreg] &= BITMASK(16);
1.1 root 3215: } else {
3216: newsr = 0;
3217: }
3218:
1.1.1.6 root 3219: dsp_core.registers[DSP_REG_A2+numreg] = dest[0];
3220: dsp_core.registers[DSP_REG_A1+numreg] = dest[1];
3221: dsp_core.registers[DSP_REG_A0+numreg] = dest[2];
1.1.1.2 root 3222:
1.1.1.6 root 3223: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 3224:
1.1.1.6 root 3225: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
3226: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 3227: }
3228:
3229: static void dsp_ori(void)
3230: {
1.1.1.2 root 3231: Uint32 regnum, value;
1.1 root 3232:
3233: value = (cur_inst >> 8) & BITMASK(8);
3234: regnum = cur_inst & BITMASK(2);
3235: switch(regnum) {
3236: case 0:
3237: /* mr */
1.1.1.6 root 3238: dsp_core.registers[DSP_REG_SR] |= value<<8;
1.1 root 3239: break;
3240: case 1:
3241: /* ccr */
1.1.1.6 root 3242: dsp_core.registers[DSP_REG_SR] |= value;
1.1 root 3243: break;
3244: case 2:
3245: /* omr */
1.1.1.6 root 3246: dsp_core.registers[DSP_REG_OMR] |= value;
1.1 root 3247: break;
3248: }
3249: }
3250:
1.1.1.3 root 3251: /*
3252: REP instruction parameter encoding
3253:
3254: xxxxxxxx 00xxxxxx 0xxxxxxx aa
3255: xxxxxxxx 01xxxxxx 0xxxxxxx ea
3256: xxxxxxxx YYxxxxxx 1xxxxxxx imm
3257: xxxxxxxx 11xxxxxx 0xxxxxxx reg
3258: */
3259:
3260: static void dsp_rep_aa(void)
1.1 root 3261: {
3262: /* x:aa */
3263: /* y:aa */
1.1.1.6 root 3264: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3265: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3266: dsp_core.loop_rep = 1; /* We are now running rep */
1.1 root 3267:
1.1.1.6 root 3268: dsp_core.registers[DSP_REG_LC]=read_memory((cur_inst>>6) & 1,(cur_inst>>8) & BITMASK(6));
1.1.1.4 root 3269:
1.1.1.6 root 3270: dsp_core.instr_cycle += 2;
1.1 root 3271: }
3272:
1.1.1.3 root 3273: static void dsp_rep_imm(void)
1.1 root 3274: {
3275: /* #xxx */
3276:
1.1.1.6 root 3277: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3278: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3279: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3280:
1.1.1.6 root 3281: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
1.1.1.3 root 3282: + ((cur_inst & BITMASK(4))<<8);
1.1.1.4 root 3283:
1.1.1.6 root 3284: dsp_core.instr_cycle += 2;
1.1 root 3285: }
3286:
1.1.1.3 root 3287: static void dsp_rep_ea(void)
1.1 root 3288: {
1.1.1.2 root 3289: Uint32 value;
1.1 root 3290:
3291: /* x:ea */
3292: /* y:ea */
3293:
1.1.1.6 root 3294: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3295: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3296: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3297:
1.1 root 3298: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&value);
1.1.1.6 root 3299: dsp_core.registers[DSP_REG_LC]= read_memory((cur_inst>>6) & 1, value);
1.1.1.4 root 3300:
1.1.1.6 root 3301: dsp_core.instr_cycle += 2;
1.1 root 3302: }
3303:
1.1.1.3 root 3304: static void dsp_rep_reg(void)
1.1 root 3305: {
1.1.1.2 root 3306: Uint32 numreg;
1.1 root 3307:
3308: /* R */
3309:
1.1.1.6 root 3310: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3311: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3312: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3313:
1.1 root 3314: numreg = (cur_inst>>8) & BITMASK(6);
3315: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11 root 3316: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
1.1 root 3317: } else {
1.1.1.6 root 3318: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
1.1 root 3319: }
1.1.1.6 root 3320: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.4 root 3321:
1.1.1.6 root 3322: dsp_core.instr_cycle += 2;
1.1 root 3323: }
3324:
3325: static void dsp_reset(void)
3326: {
3327: /* Reset external peripherals */
1.1.1.6 root 3328: dsp_core.instr_cycle += 2;
1.1 root 3329: }
3330:
3331: static void dsp_rti(void)
3332: {
1.1.1.2 root 3333: Uint32 newpc = 0, newsr = 0;
1.1 root 3334:
3335: dsp_stack_pop(&newpc, &newsr);
1.1.1.6 root 3336: dsp_core.pc = newpc;
3337: dsp_core.registers[DSP_REG_SR] = newsr;
1.1 root 3338: cur_inst_len = 0;
1.1.1.4 root 3339:
1.1.1.6 root 3340: dsp_core.instr_cycle += 2;
1.1 root 3341: }
3342:
3343: static void dsp_rts(void)
3344: {
1.1.1.2 root 3345: Uint32 newpc = 0, newsr;
1.1 root 3346:
3347: dsp_stack_pop(&newpc, &newsr);
1.1.1.6 root 3348: dsp_core.pc = newpc;
1.1 root 3349: cur_inst_len = 0;
1.1.1.4 root 3350:
1.1.1.6 root 3351: dsp_core.instr_cycle += 2;
1.1 root 3352: }
3353:
3354: static void dsp_stop(void)
3355: {
1.1.1.6 root 3356: LOG_TRACE(TRACE_DSP_STATE, "Dsp: STOP instruction\n");
1.1 root 3357: }
3358:
3359: static void dsp_swi(void)
3360: {
3361: /* Raise interrupt p:0x0006 */
1.1.1.6 root 3362: dsp_core.instr_cycle += 6;
1.1 root 3363: }
3364:
3365: static void dsp_tcc(void)
3366: {
1.1.1.6 root 3367: Uint32 cc_code, regsrc1, regdest1;
1.1.1.2 root 3368: Uint32 regsrc2, regdest2;
1.1.1.6 root 3369: Uint32 val0, val1, val2;
1.1.1.11 root 3370:
1.1 root 3371: cc_code = (cur_inst>>12) & BITMASK(4);
3372:
3373: if (dsp_calc_cc(cc_code)) {
3374: regsrc1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][0];
1.1.1.2 root 3375: regdest1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][1];
1.1 root 3376:
3377: /* Read S1 */
1.1.1.7 root 3378: if (regsrc1 == DSP_REG_A) {
3379: val0 = dsp_core.registers[DSP_REG_A0];
3380: val1 = dsp_core.registers[DSP_REG_A1];
3381: val2 = dsp_core.registers[DSP_REG_A2];
3382: }
3383: else if (regsrc1 == DSP_REG_B) {
3384: val0 = dsp_core.registers[DSP_REG_B0];
3385: val1 = dsp_core.registers[DSP_REG_B1];
3386: val2 = dsp_core.registers[DSP_REG_B2];
3387: }
3388: else {
1.1.1.6 root 3389: val0 = 0;
3390: val1 = dsp_core.registers[regsrc1];
1.1.1.7 root 3391: val2 = val1 & (1<<23) ? 0xff : 0x0;
1.1 root 3392: }
1.1.1.11 root 3393:
1.1 root 3394: /* Write D1 */
1.1.1.7 root 3395: if (regdest1 == DSP_REG_A) {
3396: dsp_core.registers[DSP_REG_A2] = val2;
3397: dsp_core.registers[DSP_REG_A1] = val1;
3398: dsp_core.registers[DSP_REG_A0] = val0;
3399: }
3400: else {
3401: dsp_core.registers[DSP_REG_B2] = val2;
3402: dsp_core.registers[DSP_REG_B1] = val1;
3403: dsp_core.registers[DSP_REG_B0] = val0;
3404: }
1.1 root 3405:
3406: /* S2,D2 transfer */
3407: if (cur_inst & (1<<16)) {
1.1.1.2 root 3408: regsrc2 = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3409: regdest2 = DSP_REG_R0+(cur_inst & BITMASK(3));
1.1 root 3410:
1.1.1.11 root 3411: dsp_core.agu_move_indirect_instr = 1;
3412: dsp_write_reg(regdest2, dsp_core.registers[regsrc2]);
1.1 root 3413: }
3414: }
3415: }
3416:
3417: static void dsp_wait(void)
3418: {
1.1.1.6 root 3419: LOG_TRACE(TRACE_DSP_STATE, "Dsp: WAIT instruction\n");
1.1 root 3420: }
3421:
1.1.1.2 root 3422: static int dsp_pm_read_accu24(int numreg, Uint32 *dest)
1.1 root 3423: {
1.1.1.4 root 3424: Uint32 scaling, value, reg;
1.1.1.7 root 3425: int got_limited = 0;
1.1 root 3426:
3427: /* Read an accumulator, stores it limited */
3428:
1.1.1.6 root 3429: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
1.1.1.4 root 3430: reg = numreg & 1;
1.1 root 3431:
1.1.1.6 root 3432: value = (dsp_core.registers[DSP_REG_A2+reg]) << 24;
3433: value += dsp_core.registers[DSP_REG_A1+reg];
1.1 root 3434:
3435: switch(scaling) {
3436: case 0:
1.1.1.4 root 3437: /* No scaling */
3438: break;
3439: case 1:
3440: /* scaling down */
3441: value >>= 1;
1.1 root 3442: break;
3443: case 2:
1.1.1.4 root 3444: /* scaling up */
3445: value <<= 1;
1.1.1.6 root 3446: value |= (dsp_core.registers[DSP_REG_A0+reg]>>23) & 1;
1.1 root 3447: break;
1.1.1.4 root 3448: /* indeterminate */
1.1.1.11 root 3449: case 3:
1.1.1.4 root 3450: break;
3451: }
3452:
3453: /* limiting ? */
3454: value &= BITMASK(24);
3455:
1.1.1.6 root 3456: if (dsp_core.registers[DSP_REG_A2+reg] == 0) {
1.1.1.4 root 3457: if (value <= 0x007fffff) {
3458: /* No limiting */
3459: *dest=value;
3460: return 0;
1.1.1.11 root 3461: }
1.1.1.4 root 3462: }
3463:
1.1.1.6 root 3464: if (dsp_core.registers[DSP_REG_A2+reg] == 0xff) {
1.1.1.4 root 3465: if (value >= 0x00800000) {
3466: /* No limiting */
3467: *dest=value;
3468: return 0;
1.1.1.11 root 3469: }
1.1 root 3470: }
3471:
1.1.1.6 root 3472: if (dsp_core.registers[DSP_REG_A2+reg] & (1<<7)) {
1.1 root 3473: /* Limited to maximum negative value */
3474: *dest=0x00800000;
1.1.1.6 root 3475: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
1.1.1.2 root 3476: got_limited=1;
1.1 root 3477: } else {
3478: /* Limited to maximal positive value */
3479: *dest=0x007fffff;
1.1.1.6 root 3480: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
1.1.1.2 root 3481: got_limited=1;
1.1.1.11 root 3482: }
1.1.1.2 root 3483:
3484: return got_limited;
1.1 root 3485: }
3486:
3487: static void dsp_pm_0(void)
3488: {
1.1.1.6 root 3489: Uint32 memspace, numreg, addr, save_accu, save_xy0;
1.1 root 3490: /*
3491: 0000 100d 00mm mrrr S,x:ea x0,D
3492: 0000 100d 10mm mrrr S,y:ea y0,D
3493: */
3494: memspace = (cur_inst>>15) & 1;
3495: numreg = (cur_inst>>16) & 1;
1.1.1.6 root 3496: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &addr);
3497:
1.1.1.11 root 3498: /* Save A or B */
1.1.1.6 root 3499: dsp_pm_read_accu24(numreg, &save_accu);
1.1 root 3500:
1.1.1.6 root 3501: /* Save X0 or Y0 */
3502: save_xy0 = dsp_core.registers[DSP_REG_X0+(memspace<<1)];
3503:
3504: /* Execute parallel instruction */
3505: opcodes_alu[cur_inst & BITMASK(8)]();
3506:
1.1.1.11 root 3507: /* Move [A|B] to [x|y]:ea */
1.1.1.6 root 3508: write_memory(memspace, addr, save_accu);
3509:
3510: /* Move [x|y]0 to [A|B] */
3511: dsp_core.registers[DSP_REG_A0+numreg] = 0;
3512: dsp_core.registers[DSP_REG_A1+numreg] = save_xy0;
1.1.1.7 root 3513: dsp_core.registers[DSP_REG_A2+numreg] = save_xy0 & (1<<23) ? 0xff : 0x0;
1.1 root 3514: }
3515:
3516: static void dsp_pm_1(void)
3517: {
1.1.1.6 root 3518: Uint32 memspace, numreg1, numreg2, value, xy_addr, retour, save_1, save_2;
1.1 root 3519: /*
1.1.1.11 root 3520: 0001 ffdf w0mm mrrr x:ea,D1 S2,D2
1.1 root 3521: S1,x:ea S2,D2
3522: #xxxxxx,D1 S2,D2
1.1.1.11 root 3523: 0001 deff w1mm mrrr S1,D1 y:ea,D2
1.1 root 3524: S1,D1 S2,y:ea
3525: S1,D1 #xxxxxx,D2
3526: */
3527: value = (cur_inst>>8) & BITMASK(6);
1.1.1.11 root 3528: retour = dsp_calc_ea(value, &xy_addr);
1.1 root 3529: memspace = (cur_inst>>14) & 1;
1.1.1.6 root 3530: numreg1 = numreg2 = DSP_REG_NULL;
1.1 root 3531:
3532: if (memspace) {
3533: /* Y: */
3534: switch((cur_inst>>16) & BITMASK(2)) {
1.1.1.6 root 3535: case 0: numreg1 = DSP_REG_Y0; break;
3536: case 1: numreg1 = DSP_REG_Y1; break;
3537: case 2: numreg1 = DSP_REG_A; break;
3538: case 3: numreg1 = DSP_REG_B; break;
1.1 root 3539: }
3540: } else {
3541: /* X: */
3542: switch((cur_inst>>18) & BITMASK(2)) {
1.1.1.6 root 3543: case 0: numreg1 = DSP_REG_X0; break;
3544: case 1: numreg1 = DSP_REG_X1; break;
3545: case 2: numreg1 = DSP_REG_A; break;
3546: case 3: numreg1 = DSP_REG_B; break;
1.1 root 3547: }
3548: }
3549:
3550: if (cur_inst & (1<<15)) {
3551: /* Write D1 */
1.1.1.6 root 3552: if (retour)
3553: save_1 = xy_addr;
3554: else
3555: save_1 = read_memory(memspace, xy_addr);
1.1 root 3556: } else {
3557: /* Read S1 */
1.1.1.6 root 3558: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
3559: dsp_pm_read_accu24(numreg1, &save_1);
3560: else
3561: save_1 = dsp_core.registers[numreg1];
1.1 root 3562: }
1.1.1.11 root 3563:
1.1 root 3564: /* S2 */
3565: if (memspace) {
3566: /* Y: */
1.1.1.6 root 3567: numreg2 = DSP_REG_A + ((cur_inst>>19) & 1);
1.1 root 3568: } else {
3569: /* X: */
1.1.1.6 root 3570: numreg2 = DSP_REG_A + ((cur_inst>>17) & 1);
1.1.1.11 root 3571: }
1.1.1.6 root 3572: dsp_pm_read_accu24(numreg2, &save_2);
1.1.1.11 root 3573:
1.1.1.6 root 3574:
3575: /* Execute parallel instruction */
3576: opcodes_alu[cur_inst & BITMASK(8)]();
3577:
3578:
3579: /* Write parallel move values */
3580: if (cur_inst & (1<<15)) {
3581: /* Write D1 */
1.1.1.11 root 3582: dsp_write_reg(numreg1, save_1);
1.1.1.6 root 3583: } else {
3584: /* Read S1 */
3585: write_memory(memspace, xy_addr, save_1);
3586: }
3587:
3588: /* S2 -> D2 */
1.1 root 3589: if (memspace) {
3590: /* Y: */
1.1.1.6 root 3591: numreg2 = DSP_REG_X0 + ((cur_inst>>18) & 1);
1.1 root 3592: } else {
3593: /* X: */
1.1.1.6 root 3594: numreg2 = DSP_REG_Y0 + ((cur_inst>>16) & 1);
1.1.1.11 root 3595: }
1.1.1.6 root 3596: dsp_core.registers[numreg2] = save_2;
1.1 root 3597: }
3598:
3599: static void dsp_pm_2(void)
3600: {
1.1.1.2 root 3601: Uint32 dummy;
1.1 root 3602: /*
3603: 0010 0000 0000 0000 nop
3604: 0010 0000 010m mrrr R update
3605: 0010 00ee eeed dddd S,D
3606: 001d dddd iiii iiii #xx,D
3607: */
1.1.1.4 root 3608: if ((cur_inst & 0xffff00) == 0x200000) {
1.1.1.6 root 3609: /* Execute parallel instruction */
3610: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3611: return;
3612: }
3613:
1.1.1.4 root 3614: if ((cur_inst & 0xffe000) == 0x204000) {
1.1 root 3615: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &dummy);
1.1.1.6 root 3616: /* Execute parallel instruction */
3617: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3618: return;
3619: }
3620:
1.1.1.4 root 3621: if ((cur_inst & 0xfc0000) == 0x200000) {
1.1 root 3622: dsp_pm_2_2();
3623: return;
3624: }
3625:
3626: dsp_pm_3();
3627: }
3628:
3629: static void dsp_pm_2_2(void)
3630: {
3631: /*
3632: 0010 00ee eeed dddd S,D
3633: */
1.1.1.6 root 3634: Uint32 srcreg, dstreg, save_reg;
1.1.1.11 root 3635:
1.1 root 3636: srcreg = (cur_inst >> 13) & BITMASK(5);
3637: dstreg = (cur_inst >> 8) & BITMASK(5);
3638:
1.1.1.6 root 3639: if ((srcreg == DSP_REG_A) || (srcreg == DSP_REG_B))
3640: /* Accu to register: limited 24 bits */
3641: dsp_pm_read_accu24(srcreg, &save_reg);
3642: else
3643: save_reg = dsp_core.registers[srcreg];
3644:
3645: /* Execute parallel instruction */
3646: opcodes_alu[cur_inst & BITMASK(8)]();
3647:
3648: /* Write reg */
1.1.1.11 root 3649: dsp_core.agu_move_indirect_instr = 1;
3650: dsp_write_reg(dstreg, save_reg);
1.1 root 3651: }
3652:
3653: static void dsp_pm_3(void)
3654: {
1.1.1.6 root 3655: Uint32 dstreg, srcvalue;
1.1 root 3656: /*
3657: 001d dddd iiii iiii #xx,R
3658: */
1.1.1.6 root 3659:
3660: /* Execute parallel instruction */
3661: opcodes_alu[cur_inst & BITMASK(8)]();
3662:
3663: /* Write reg */
3664: dstreg = (cur_inst >> 16) & BITMASK(5);
1.1 root 3665: srcvalue = (cur_inst >> 8) & BITMASK(8);
3666:
1.1.1.6 root 3667: switch(dstreg) {
1.1 root 3668: case DSP_REG_X0:
3669: case DSP_REG_X1:
3670: case DSP_REG_Y0:
3671: case DSP_REG_Y1:
3672: case DSP_REG_A:
3673: case DSP_REG_B:
3674: srcvalue <<= 16;
3675: break;
3676: }
3677:
1.1.1.11 root 3678: dsp_core.agu_move_indirect_instr = 1;
3679: dsp_write_reg(dstreg, srcvalue);
1.1 root 3680: }
3681:
3682: static void dsp_pm_4(void)
3683: {
3684: /*
1.1.1.4 root 3685: 0100 l0ll w0aa aaaa l:aa,D
1.1 root 3686: S,l:aa
1.1.1.4 root 3687: 0100 l0ll w1mm mrrr l:ea,D
1.1 root 3688: S,l:ea
1.1.1.4 root 3689: 01dd 0ddd w0aa aaaa x:aa,D
1.1 root 3690: S,x:aa
1.1.1.4 root 3691: 01dd 0ddd w1mm mrrr x:ea,D
1.1 root 3692: S,x:ea
3693: #xxxxxx,D
1.1.1.4 root 3694: 01dd 1ddd w0aa aaaa y:aa,D
1.1 root 3695: S,y:aa
1.1.1.4 root 3696: 01dd 1ddd w1mm mrrr y:ea,D
1.1 root 3697: S,y:ea
3698: #xxxxxx,D
3699: */
1.1.1.4 root 3700: if ((cur_inst & 0xf40000)==0x400000) {
3701: dsp_pm_4x();
1.1 root 3702: return;
3703: }
3704:
3705: dsp_pm_5();
3706: }
3707:
1.1.1.4 root 3708: static void dsp_pm_4x(void)
1.1 root 3709: {
1.1.1.6 root 3710: Uint32 value, numreg, l_addr, save_lx, save_ly;
1.1 root 3711: /*
1.1.1.4 root 3712: 0100 l0ll w0aa aaaa l:aa,D
3713: S,l:aa
3714: 0100 l0ll w1mm mrrr l:ea,D
3715: S,l:ea
1.1 root 3716: */
1.1.1.4 root 3717: value = (cur_inst>>8) & BITMASK(6);
3718: if (cur_inst & (1<<14)) {
1.1.1.11 root 3719: dsp_calc_ea(value, &l_addr);
1.1.1.4 root 3720: } else {
3721: l_addr = value;
3722: }
3723:
1.1 root 3724: numreg = (cur_inst>>16) & BITMASK(2);
3725: numreg |= (cur_inst>>17) & (1<<2);
3726:
3727: if (cur_inst & (1<<15)) {
3728: /* Write D */
1.1.1.6 root 3729: save_lx = read_memory(DSP_SPACE_X,l_addr);
3730: save_ly = read_memory(DSP_SPACE_Y,l_addr);
3731: }
3732: else {
3733: /* Read S */
1.1.1.4 root 3734: switch(numreg) {
3735: case 0:
3736: /* A10 */
1.1.1.6 root 3737: save_lx = dsp_core.registers[DSP_REG_A1];
3738: save_ly = dsp_core.registers[DSP_REG_A0];
1.1.1.4 root 3739: break;
3740: case 1:
3741: /* B10 */
1.1.1.6 root 3742: save_lx = dsp_core.registers[DSP_REG_B1];
3743: save_ly = dsp_core.registers[DSP_REG_B0];
1.1.1.4 root 3744: break;
3745: case 2:
3746: /* X */
1.1.1.6 root 3747: save_lx = dsp_core.registers[DSP_REG_X1];
3748: save_ly = dsp_core.registers[DSP_REG_X0];
1.1.1.4 root 3749: break;
3750: case 3:
3751: /* Y */
1.1.1.6 root 3752: save_lx = dsp_core.registers[DSP_REG_Y1];
3753: save_ly = dsp_core.registers[DSP_REG_Y0];
1.1.1.4 root 3754: break;
3755: case 4:
3756: /* A */
1.1.1.6 root 3757: if (dsp_pm_read_accu24(DSP_REG_A, &save_lx)) {
3758: /* Was limited, set lower part */
3759: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3760: } else {
3761: /* Not limited */
3762: save_ly = dsp_core.registers[DSP_REG_A0];
3763: }
1.1.1.4 root 3764: break;
3765: case 5:
3766: /* B */
1.1.1.6 root 3767: if (dsp_pm_read_accu24(DSP_REG_B, &save_lx)) {
3768: /* Was limited, set lower part */
3769: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3770: } else {
3771: /* Not limited */
3772: save_ly = dsp_core.registers[DSP_REG_B0];
3773: }
1.1.1.4 root 3774: break;
3775: case 6:
3776: /* AB */
1.1.1.11 root 3777: dsp_pm_read_accu24(DSP_REG_A, &save_lx);
3778: dsp_pm_read_accu24(DSP_REG_B, &save_ly);
1.1.1.4 root 3779: break;
3780: case 7:
3781: /* BA */
1.1.1.11 root 3782: dsp_pm_read_accu24(DSP_REG_B, &save_lx);
3783: dsp_pm_read_accu24(DSP_REG_A, &save_ly);
1.1.1.4 root 3784: break;
1.1 root 3785: }
1.1.1.6 root 3786: }
1.1 root 3787:
1.1.1.6 root 3788: /* Execute parallel instruction */
3789: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3790:
1.1.1.6 root 3791:
3792: if (cur_inst & (1<<15)) {
3793: /* Write D */
1.1.1.4 root 3794: switch(numreg) {
1.1.1.6 root 3795: case 0: /* A10 */
3796: dsp_core.registers[DSP_REG_A1] = save_lx;
3797: dsp_core.registers[DSP_REG_A0] = save_ly;
1.1.1.4 root 3798: break;
1.1.1.6 root 3799: case 1: /* B10 */
3800: dsp_core.registers[DSP_REG_B1] = save_lx;
3801: dsp_core.registers[DSP_REG_B0] = save_ly;
1.1.1.4 root 3802: break;
1.1.1.6 root 3803: case 2: /* X */
3804: dsp_core.registers[DSP_REG_X1] = save_lx;
3805: dsp_core.registers[DSP_REG_X0] = save_ly;
1.1.1.4 root 3806: break;
1.1.1.6 root 3807: case 3: /* Y */
3808: dsp_core.registers[DSP_REG_Y1] = save_lx;
3809: dsp_core.registers[DSP_REG_Y0] = save_ly;
1.1.1.4 root 3810: break;
1.1.1.6 root 3811: case 4: /* A */
3812: dsp_core.registers[DSP_REG_A0] = save_ly;
3813: dsp_core.registers[DSP_REG_A1] = save_lx;
3814: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
1.1.1.4 root 3815: break;
1.1.1.6 root 3816: case 5: /* B */
3817: dsp_core.registers[DSP_REG_B0] = save_ly;
3818: dsp_core.registers[DSP_REG_B1] = save_lx;
3819: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
1.1.1.4 root 3820: break;
1.1.1.6 root 3821: case 6: /* AB */
3822: dsp_core.registers[DSP_REG_A0] = 0;
3823: dsp_core.registers[DSP_REG_A1] = save_lx;
3824: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
3825: dsp_core.registers[DSP_REG_B0] = 0;
3826: dsp_core.registers[DSP_REG_B1] = save_ly;
3827: dsp_core.registers[DSP_REG_B2] = save_ly & (1<<23) ? 0xff : 0;
1.1.1.4 root 3828: break;
1.1.1.6 root 3829: case 7: /* BA */
3830: dsp_core.registers[DSP_REG_B0] = 0;
3831: dsp_core.registers[DSP_REG_B1] = save_lx;
3832: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
3833: dsp_core.registers[DSP_REG_A0] = 0;
3834: dsp_core.registers[DSP_REG_A1] = save_ly;
3835: dsp_core.registers[DSP_REG_A2] = save_ly & (1<<23) ? 0xff : 0;
1.1.1.4 root 3836: break;
1.1 root 3837: }
1.1.1.6 root 3838: }
3839: else {
3840: /* Read S */
3841: write_memory(DSP_SPACE_X, l_addr, save_lx);
3842: write_memory(DSP_SPACE_Y, l_addr, save_ly);
1.1 root 3843: }
3844: }
3845:
3846: static void dsp_pm_5(void)
3847: {
1.1.1.2 root 3848: Uint32 memspace, numreg, value, xy_addr, retour;
1.1 root 3849: /*
1.1.1.4 root 3850: 01dd 0ddd w0aa aaaa x:aa,D
1.1 root 3851: S,x:aa
1.1.1.4 root 3852: 01dd 0ddd w1mm mrrr x:ea,D
1.1 root 3853: S,x:ea
3854: #xxxxxx,D
1.1.1.4 root 3855: 01dd 1ddd w0aa aaaa y:aa,D
1.1 root 3856: S,y:aa
1.1.1.4 root 3857: 01dd 1ddd w1mm mrrr y:ea,D
1.1 root 3858: S,y:ea
3859: #xxxxxx,D
3860: */
3861:
3862: value = (cur_inst>>8) & BITMASK(6);
3863:
3864: if (cur_inst & (1<<14)) {
1.1.1.11 root 3865: retour = dsp_calc_ea(value, &xy_addr);
1.1 root 3866: } else {
3867: xy_addr = value;
3868: retour = 0;
3869: }
3870:
3871: memspace = (cur_inst>>19) & 1;
3872: numreg = (cur_inst>>16) & BITMASK(3);
3873: numreg |= (cur_inst>>17) & (BITMASK(2)<<3);
3874:
3875: if (cur_inst & (1<<15)) {
3876: /* Write D */
1.1.1.6 root 3877: if (retour)
1.1 root 3878: value = xy_addr;
1.1.1.6 root 3879: else
1.1 root 3880: value = read_memory(memspace, xy_addr);
1.1.1.6 root 3881: }
3882: else {
1.1 root 3883: /* Read S */
1.1.1.6 root 3884: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B))
3885: dsp_pm_read_accu24(numreg, &value);
3886: else
3887: value = dsp_core.registers[numreg];
3888: }
1.1 root 3889:
3890:
1.1.1.6 root 3891: /* Execute parallel instruction */
3892: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3893:
1.1.1.6 root 3894: if (cur_inst & (1<<15)) {
3895: /* Write D */
1.1.1.11 root 3896: dsp_core.agu_move_indirect_instr = 1;
3897: dsp_write_reg(numreg, value);
1.1.1.6 root 3898: }
3899: else {
1.1.1.7 root 3900: /* Read S */
1.1.1.6 root 3901: write_memory(memspace, xy_addr, value);
1.1 root 3902: }
3903: }
3904:
3905: static void dsp_pm_8(void)
3906: {
1.1.1.2 root 3907: Uint32 ea1, ea2;
3908: Uint32 numreg1, numreg2;
1.1.1.6 root 3909: Uint32 save_reg1, save_reg2, x_addr, y_addr;
1.1 root 3910: /*
1.1.1.11 root 3911: 1wmm eeff WrrM MRRR x:ea,D1 y:ea,D2
1.1 root 3912: x:ea,D1 S2,y:ea
3913: S1,x:ea y:ea,D2
3914: S1,x:ea S2,y:ea
3915: */
3916: numreg1 = numreg2 = DSP_REG_NULL;
3917:
3918: ea1 = (cur_inst>>8) & BITMASK(5);
3919: if ((ea1>>3) == 0) {
3920: ea1 |= (1<<5);
3921: }
3922: ea2 = (cur_inst>>13) & BITMASK(2);
3923: ea2 |= (cur_inst>>17) & (BITMASK(2)<<3);
3924: if ((ea1 & (1<<2))==0) {
3925: ea2 |= 1<<2;
3926: }
3927: if ((ea2>>3) == 0) {
3928: ea2 |= (1<<5);
3929: }
3930:
1.1.1.4 root 3931: dsp_calc_ea(ea1, &x_addr);
3932: dsp_calc_ea(ea2, &y_addr);
3933:
1.1 root 3934: switch((cur_inst>>18) & BITMASK(2)) {
3935: case 0: numreg1=DSP_REG_X0; break;
3936: case 1: numreg1=DSP_REG_X1; break;
3937: case 2: numreg1=DSP_REG_A; break;
3938: case 3: numreg1=DSP_REG_B; break;
3939: }
3940: switch((cur_inst>>16) & BITMASK(2)) {
3941: case 0: numreg2=DSP_REG_Y0; break;
3942: case 1: numreg2=DSP_REG_Y1; break;
3943: case 2: numreg2=DSP_REG_A; break;
3944: case 3: numreg2=DSP_REG_B; break;
3945: }
1.1.1.11 root 3946:
1.1 root 3947: if (cur_inst & (1<<15)) {
3948: /* Write D1 */
1.1.1.6 root 3949: save_reg1 = read_memory(DSP_SPACE_X, x_addr);
1.1 root 3950: } else {
3951: /* Read S1 */
1.1.1.6 root 3952: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
3953: dsp_pm_read_accu24(numreg1, &save_reg1);
3954: else
3955: save_reg1 = dsp_core.registers[numreg1];
1.1 root 3956: }
3957:
3958: if (cur_inst & (1<<22)) {
3959: /* Write D2 */
1.1.1.6 root 3960: save_reg2 = read_memory(DSP_SPACE_Y, y_addr);
1.1 root 3961: } else {
3962: /* Read S2 */
1.1.1.6 root 3963: if ((numreg2==DSP_REG_A) || (numreg2==DSP_REG_B))
3964: dsp_pm_read_accu24(numreg2, &save_reg2);
3965: else
3966: save_reg2 = dsp_core.registers[numreg2];
1.1 root 3967: }
3968:
3969:
1.1.1.6 root 3970: /* Execute parallel instruction */
3971: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3972:
1.1.1.6 root 3973: /* Write first parallel move */
3974: if (cur_inst & (1<<15)) {
3975: /* Write D1 */
3976: if (numreg1 == DSP_REG_A) {
3977: dsp_core.registers[DSP_REG_A0] = 0x0;
3978: dsp_core.registers[DSP_REG_A1] = save_reg1;
3979: dsp_core.registers[DSP_REG_A2] = save_reg1 & (1<<23) ? 0xff : 0x0;
3980: }
3981: else if (numreg1 == DSP_REG_B) {
3982: dsp_core.registers[DSP_REG_B0] = 0x0;
3983: dsp_core.registers[DSP_REG_B1] = save_reg1;
3984: dsp_core.registers[DSP_REG_B2] = save_reg1 & (1<<23) ? 0xff : 0x0;
3985: }
3986: else {
3987: dsp_core.registers[numreg1] = save_reg1;
3988: }
3989: } else {
3990: /* Read S1 */
3991: write_memory(DSP_SPACE_X, x_addr, save_reg1);
3992: }
3993:
3994: /* Write second parallel move */
3995: if (cur_inst & (1<<22)) {
3996: /* Write D2 */
3997: if (numreg2 == DSP_REG_A) {
3998: dsp_core.registers[DSP_REG_A0] = 0x0;
3999: dsp_core.registers[DSP_REG_A1] = save_reg2;
4000: dsp_core.registers[DSP_REG_A2] = save_reg2 & (1<<23) ? 0xff : 0x0;
4001: }
4002: else if (numreg2 == DSP_REG_B) {
4003: dsp_core.registers[DSP_REG_B0] = 0x0;
4004: dsp_core.registers[DSP_REG_B1] = save_reg2;
4005: dsp_core.registers[DSP_REG_B2] = save_reg2 & (1<<23) ? 0xff : 0x0;
4006: }
4007: else {
4008: dsp_core.registers[numreg2] = save_reg2;
4009: }
4010: } else {
4011: /* Read S2 */
4012: write_memory(DSP_SPACE_Y, y_addr, save_reg2);
4013: }
4014: }
4015:
4016: /**********************************
4017: * 56bit arithmetic
4018: **********************************/
4019:
4020: /* source,dest[0] is 55:48 */
4021: /* source,dest[1] is 47:24 */
4022: /* source,dest[2] is 23:00 */
4023:
4024: static Uint16 dsp_abs56(Uint32 *dest)
1.1 root 4025: {
1.1.1.2 root 4026: Uint32 zerodest[3];
4027: Uint16 newsr;
1.1 root 4028:
4029: /* D=|D| */
4030:
4031: if (dest[0] & (1<<7)) {
4032: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4033:
4034: newsr = dsp_sub56(dest, zerodest);
4035:
4036: dest[0] = zerodest[0];
4037: dest[1] = zerodest[1];
4038: dest[2] = zerodest[2];
4039: } else {
4040: newsr = 0;
4041: }
4042:
4043: return newsr;
4044: }
4045:
1.1.1.2 root 4046: static Uint16 dsp_asl56(Uint32 *dest)
1.1 root 4047: {
1.1.1.2 root 4048: Uint16 overflow, carry;
1.1 root 4049:
4050: /* Shift left dest 1 bit: D<<=1 */
4051:
4052: carry = (dest[0]>>7) & 1;
4053:
4054: dest[0] <<= 1;
4055: dest[0] |= (dest[1]>>23) & 1;
4056: dest[0] &= BITMASK(8);
4057:
4058: dest[1] <<= 1;
4059: dest[1] |= (dest[2]>>23) & 1;
4060: dest[1] &= BITMASK(24);
1.1.1.11 root 4061:
1.1 root 4062: dest[2] <<= 1;
4063: dest[2] &= BITMASK(24);
4064:
4065: overflow = (carry != ((dest[0]>>7) & 1));
4066:
4067: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4068: }
4069:
1.1.1.2 root 4070: static Uint16 dsp_asr56(Uint32 *dest)
1.1 root 4071: {
1.1.1.2 root 4072: Uint16 carry;
1.1 root 4073:
4074: /* Shift right dest 1 bit: D>>=1 */
4075:
4076: carry = dest[2] & 1;
4077:
4078: dest[2] >>= 1;
4079: dest[2] |= (dest[1] & 1)<<23;
4080:
4081: dest[1] >>= 1;
4082: dest[1] |= (dest[0] & 1)<<23;
4083:
4084: dest[0] >>= 1;
4085: dest[0] |= (dest[0] & (1<<6))<<1;
4086:
4087: return (carry<<DSP_SR_C);
4088: }
4089:
1.1.1.2 root 4090: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest)
1.1 root 4091: {
1.1.1.4 root 4092: Uint16 overflow, carry, flg_s, flg_d, flg_r;
4093:
4094: flg_s = (source[0]>>7) & 1;
4095: flg_d = (dest[0]>>7) & 1;
4096:
1.1 root 4097: /* Add source to dest: D = D+S */
1.1.1.2 root 4098: dest[2] += source[2];
4099: dest[1] += source[1]+((dest[2]>>24) & 1);
4100: dest[0] += source[0]+((dest[1]>>24) & 1);
1.1 root 4101:
1.1.1.5 root 4102: carry = (dest[0]>>8) & 1;
4103:
1.1 root 4104: dest[2] &= BITMASK(24);
4105: dest[1] &= BITMASK(24);
4106: dest[0] &= BITMASK(8);
4107:
1.1.1.4 root 4108: flg_r = (dest[0]>>7) & 1;
4109:
4110: /*set overflow*/
4111: overflow = (flg_s ^ flg_r) & (flg_d ^ flg_r);
4112:
1.1 root 4113: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4114: }
4115:
1.1.1.2 root 4116: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest)
1.1 root 4117: {
1.1.1.5 root 4118: Uint16 overflow, carry, flg_s, flg_d, flg_r, dest_save;
1.1.1.4 root 4119:
1.1.1.5 root 4120: dest_save = dest[0];
1.1 root 4121:
1.1.1.9 root 4122: /* Subtract source from dest: D = D-S */
1.1.1.2 root 4123: dest[2] -= source[2];
4124: dest[1] -= source[1]+((dest[2]>>24) & 1);
4125: dest[0] -= source[0]+((dest[1]>>24) & 1);
1.1 root 4126:
1.1.1.5 root 4127: carry = (dest[0]>>8) & 1;
4128:
1.1 root 4129: dest[2] &= BITMASK(24);
4130: dest[1] &= BITMASK(24);
4131: dest[0] &= BITMASK(8);
4132:
1.1.1.4 root 4133: flg_s = (source[0]>>7) & 1;
1.1.1.5 root 4134: flg_d = (dest_save>>7) & 1;
1.1.1.4 root 4135: flg_r = (dest[0]>>7) & 1;
4136:
4137: /* set overflow */
4138: overflow = (flg_s ^ flg_d) & (flg_r ^ flg_d);
4139:
1.1 root 4140: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4141: }
4142:
1.1.1.5 root 4143: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe)
1.1 root 4144: {
1.1.1.2 root 4145: Uint32 part[4], zerodest[3], value;
1.1 root 4146:
4147: /* Multiply: D = S1*S2 */
4148: if (source1 & (1<<23)) {
1.1.1.5 root 4149: signe ^= 1;
1.1.1.6 root 4150: source1 = (1<<24) - source1;
1.1 root 4151: }
4152: if (source2 & (1<<23)) {
1.1.1.5 root 4153: signe ^= 1;
1.1.1.6 root 4154: source2 = (1<<24) - source2;
1.1 root 4155: }
4156:
4157: /* bits 0-11 * bits 0-11 */
4158: part[0]=(source1 & BITMASK(12))*(source2 & BITMASK(12));
4159: /* bits 12-23 * bits 0-11 */
4160: part[1]=((source1>>12) & BITMASK(12))*(source2 & BITMASK(12));
4161: /* bits 0-11 * bits 12-23 */
4162: part[2]=(source1 & BITMASK(12))*((source2>>12) & BITMASK(12));
4163: /* bits 12-23 * bits 12-23 */
4164: part[3]=((source1>>12) & BITMASK(12))*((source2>>12) & BITMASK(12));
4165:
4166: /* Calc dest 2 */
4167: dest[2] = part[0];
4168: dest[2] += (part[1] & BITMASK(12)) << 12;
4169: dest[2] += (part[2] & BITMASK(12)) << 12;
4170:
4171: /* Calc dest 1 */
4172: dest[1] = (part[1]>>12) & BITMASK(12);
4173: dest[1] += (part[2]>>12) & BITMASK(12);
4174: dest[1] += part[3];
4175:
4176: /* Calc dest 0 */
4177: dest[0] = 0;
4178:
4179: /* Add carries */
4180: value = (dest[2]>>24) & BITMASK(8);
4181: if (value) {
4182: dest[1] += value;
4183: dest[2] &= BITMASK(24);
4184: }
4185: value = (dest[1]>>24) & BITMASK(8);
4186: if (value) {
4187: dest[0] += value;
4188: dest[1] &= BITMASK(24);
4189: }
4190:
4191: /* Get rid of extra sign bit */
4192: dsp_asl56(dest);
4193:
1.1.1.5 root 4194: if (signe) {
1.1 root 4195: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4196:
4197: dsp_sub56(dest, zerodest);
4198:
4199: dest[0] = zerodest[0];
4200: dest[1] = zerodest[1];
4201: dest[2] = zerodest[2];
4202: }
4203: }
4204:
1.1.1.2 root 4205: static void dsp_rnd56(Uint32 *dest)
1.1 root 4206: {
1.1.1.4 root 4207: Uint32 rnd_const[3];
1.1 root 4208:
1.1.1.4 root 4209: rnd_const[0] = 0;
1.1 root 4210:
1.1.1.4 root 4211: /* Scaling mode S0 */
1.1.1.6 root 4212: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S0)) {
1.1.1.4 root 4213: rnd_const[1] = 1;
4214: rnd_const[2] = 0;
4215: dsp_add56(rnd_const, dest);
4216:
4217: if ((dest[2]==0) && ((dest[1] & 1) == 0)) {
4218: dest[1] &= (0xffffff - 0x3);
4219: }
4220: dest[1] &= 0xfffffe;
4221: dest[2]=0;
4222: }
4223: /* Scaling mode S1 */
1.1.1.6 root 4224: else if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S1)) {
1.1.1.4 root 4225: rnd_const[1] = 0;
4226: rnd_const[2] = (1<<22);
4227: dsp_add56(rnd_const, dest);
1.1.1.11 root 4228:
1.1.1.4 root 4229: if ((dest[2] & 0x7fffff) == 0){
4230: dest[2] = 0;
4231: }
4232: dest[2] &= 0x800000;
4233: }
4234: /* No Scaling */
4235: else {
4236: rnd_const[1] = 0;
4237: rnd_const[2] = (1<<23);
4238: dsp_add56(rnd_const, dest);
4239:
4240: if (dest[2] == 0) {
4241: dest[1] &= 0xfffffe;
1.1 root 4242: }
1.1.1.4 root 4243: dest[2]=0;
1.1 root 4244: }
4245: }
4246:
4247: /**********************************
4248: * Parallel moves instructions
4249: **********************************/
4250:
1.1.1.6 root 4251: static void dsp_abs_a(void)
1.1 root 4252: {
1.1.1.6 root 4253: Uint32 dest[3], overflowed;
1.1 root 4254:
1.1.1.6 root 4255: dest[0] = dsp_core.registers[DSP_REG_A2];
4256: dest[1] = dsp_core.registers[DSP_REG_A1];
4257: dest[2] = dsp_core.registers[DSP_REG_A0];
4258:
4259: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4260:
4261: dsp_abs56(dest);
4262:
4263: dsp_core.registers[DSP_REG_A2] = dest[0];
4264: dsp_core.registers[DSP_REG_A1] = dest[1];
4265: dsp_core.registers[DSP_REG_A0] = dest[2];
4266:
4267: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4268: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
4269:
4270: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4271: }
4272:
4273: static void dsp_abs_b(void)
4274: {
4275: Uint32 dest[3], overflowed;
1.1 root 4276:
1.1.1.6 root 4277: dest[0] = dsp_core.registers[DSP_REG_B2];
4278: dest[1] = dsp_core.registers[DSP_REG_B1];
4279: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 4280:
4281: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4282:
4283: dsp_abs56(dest);
4284:
1.1.1.6 root 4285: dsp_core.registers[DSP_REG_B2] = dest[0];
4286: dsp_core.registers[DSP_REG_B1] = dest[1];
4287: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4288:
1.1.1.6 root 4289: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4290: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
1.1.1.2 root 4291:
1.1.1.6 root 4292: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4293: }
4294:
1.1.1.6 root 4295: static void dsp_adc_x_a(void)
1.1 root 4296: {
1.1.1.6 root 4297: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4298: Uint16 newsr;
1.1 root 4299:
1.1.1.6 root 4300: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4301:
1.1.1.6 root 4302: dest[0] = dsp_core.registers[DSP_REG_A2];
4303: dest[1] = dsp_core.registers[DSP_REG_A1];
4304: dest[2] = dsp_core.registers[DSP_REG_A0];
4305:
4306: source[2] = dsp_core.registers[DSP_REG_X0];
4307: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4308: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4309:
4310: newsr = dsp_add56(source, dest);
1.1.1.11 root 4311:
1.1 root 4312: if (curcarry) {
1.1.1.6 root 4313: source[0]=0; source[1]=0; source[2]=1;
1.1 root 4314: newsr |= dsp_add56(source, dest);
4315: }
4316:
1.1.1.6 root 4317: dsp_core.registers[DSP_REG_A2] = dest[0];
4318: dsp_core.registers[DSP_REG_A1] = dest[1];
4319: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4320:
1.1.1.6 root 4321: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4322:
1.1.1.6 root 4323: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4324: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4325: }
4326:
1.1.1.6 root 4327: static void dsp_adc_x_b(void)
1.1 root 4328: {
1.1.1.6 root 4329: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4330: Uint16 newsr;
1.1 root 4331:
1.1.1.6 root 4332: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
4333:
4334: dest[0] = dsp_core.registers[DSP_REG_B2];
4335: dest[1] = dsp_core.registers[DSP_REG_B1];
4336: dest[2] = dsp_core.registers[DSP_REG_B0];
4337:
4338: source[2] = dsp_core.registers[DSP_REG_X0];
4339: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4340: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4341:
4342: newsr = dsp_add56(source, dest);
1.1.1.11 root 4343:
1.1.1.6 root 4344: if (curcarry) {
4345: source[0]=0; source[1]=0; source[2]=1;
4346: newsr |= dsp_add56(source, dest);
4347: }
1.1 root 4348:
1.1.1.6 root 4349: dsp_core.registers[DSP_REG_B2] = dest[0];
4350: dsp_core.registers[DSP_REG_B1] = dest[1];
4351: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4352:
1.1.1.6 root 4353: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4354:
1.1.1.6 root 4355: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4356: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4357: }
4358:
1.1.1.6 root 4359: static void dsp_adc_y_a(void)
1.1 root 4360: {
1.1.1.6 root 4361: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4362: Uint16 newsr;
1.1 root 4363:
1.1.1.6 root 4364: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4365:
1.1.1.6 root 4366: dest[0] = dsp_core.registers[DSP_REG_A2];
4367: dest[1] = dsp_core.registers[DSP_REG_A1];
4368: dest[2] = dsp_core.registers[DSP_REG_A0];
4369:
4370: source[2] = dsp_core.registers[DSP_REG_Y0];
4371: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4372: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4373:
1.1.1.6 root 4374: newsr = dsp_add56(source, dest);
1.1.1.11 root 4375:
1.1.1.6 root 4376: if (curcarry) {
4377: source[0]=0; source[1]=0; source[2]=1;
4378: newsr |= dsp_add56(source, dest);
4379: }
1.1 root 4380:
1.1.1.6 root 4381: dsp_core.registers[DSP_REG_A2] = dest[0];
4382: dsp_core.registers[DSP_REG_A1] = dest[1];
4383: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4384:
1.1.1.6 root 4385: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4386:
1.1.1.6 root 4387: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4388: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4389: }
4390:
1.1.1.6 root 4391: static void dsp_adc_y_b(void)
1.1 root 4392: {
1.1.1.6 root 4393: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4394: Uint16 newsr;
1.1 root 4395:
1.1.1.6 root 4396: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4397:
1.1.1.6 root 4398: dest[0] = dsp_core.registers[DSP_REG_B2];
4399: dest[1] = dsp_core.registers[DSP_REG_B1];
4400: dest[2] = dsp_core.registers[DSP_REG_B0];
4401:
4402: source[2] = dsp_core.registers[DSP_REG_Y0];
4403: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4404: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4405:
1.1.1.6 root 4406: newsr = dsp_add56(source, dest);
1.1.1.11 root 4407:
1.1.1.6 root 4408: if (curcarry) {
4409: source[0]=0; source[1]=0; source[2]=1;
4410: newsr |= dsp_add56(source, dest);
4411: }
1.1 root 4412:
1.1.1.6 root 4413: dsp_core.registers[DSP_REG_B2] = dest[0];
4414: dsp_core.registers[DSP_REG_B1] = dest[1];
4415: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4416:
1.1.1.6 root 4417: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4418:
1.1.1.6 root 4419: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4420: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4421: }
4422:
1.1.1.6 root 4423: static void dsp_add_b_a(void)
1.1 root 4424: {
1.1.1.6 root 4425: Uint32 source[3], dest[3];
4426: Uint16 newsr;
1.1 root 4427:
1.1.1.6 root 4428: dest[0] = dsp_core.registers[DSP_REG_A2];
4429: dest[1] = dsp_core.registers[DSP_REG_A1];
4430: dest[2] = dsp_core.registers[DSP_REG_A0];
4431:
4432: source[0] = dsp_core.registers[DSP_REG_B2];
4433: source[1] = dsp_core.registers[DSP_REG_B1];
4434: source[2] = dsp_core.registers[DSP_REG_B0];
4435:
4436: newsr = dsp_add56(source, dest);
4437:
4438: dsp_core.registers[DSP_REG_A2] = dest[0];
4439: dsp_core.registers[DSP_REG_A1] = dest[1];
4440: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4441:
1.1.1.6 root 4442: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4443:
1.1.1.6 root 4444: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4445: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4446: }
4447:
1.1.1.6 root 4448: static void dsp_add_a_b(void)
1.1 root 4449: {
1.1.1.6 root 4450: Uint32 source[3], dest[3];
1.1.1.2 root 4451: Uint16 newsr;
1.1 root 4452:
1.1.1.6 root 4453: dest[0] = dsp_core.registers[DSP_REG_B2];
4454: dest[1] = dsp_core.registers[DSP_REG_B1];
4455: dest[2] = dsp_core.registers[DSP_REG_B0];
4456:
4457: source[0] = dsp_core.registers[DSP_REG_A2];
4458: source[1] = dsp_core.registers[DSP_REG_A1];
4459: source[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 4460:
1.1.1.6 root 4461: newsr = dsp_add56(source, dest);
1.1 root 4462:
1.1.1.6 root 4463: dsp_core.registers[DSP_REG_B2] = dest[0];
4464: dsp_core.registers[DSP_REG_B1] = dest[1];
4465: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4466:
1.1.1.6 root 4467: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4468:
1.1.1.6 root 4469: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4470: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4471: }
4472:
1.1.1.6 root 4473: static void dsp_add_x_a(void)
1.1 root 4474: {
1.1.1.6 root 4475: Uint32 source[3], dest[3];
4476: Uint16 newsr;
1.1 root 4477:
1.1.1.6 root 4478: dest[0] = dsp_core.registers[DSP_REG_A2];
4479: dest[1] = dsp_core.registers[DSP_REG_A1];
4480: dest[2] = dsp_core.registers[DSP_REG_A0];
4481:
4482: source[1] = dsp_core.registers[DSP_REG_X1];
4483: source[2] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4484: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4485:
1.1.1.6 root 4486: newsr = dsp_add56(source, dest);
1.1 root 4487:
1.1.1.6 root 4488: dsp_core.registers[DSP_REG_A2] = dest[0];
4489: dsp_core.registers[DSP_REG_A1] = dest[1];
4490: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4491:
1.1.1.6 root 4492: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4493:
1.1.1.6 root 4494: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4495: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4496: }
4497:
1.1.1.6 root 4498: static void dsp_add_x_b(void)
1.1 root 4499: {
1.1.1.6 root 4500: Uint32 source[3], dest[3];
4501: Uint16 newsr;
1.1 root 4502:
1.1.1.6 root 4503: dest[0] = dsp_core.registers[DSP_REG_B2];
4504: dest[1] = dsp_core.registers[DSP_REG_B1];
4505: dest[2] = dsp_core.registers[DSP_REG_B0];
4506:
4507: source[1] = dsp_core.registers[DSP_REG_X1];
4508: source[2] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4509: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4510:
4511: newsr = dsp_add56(source, dest);
1.1 root 4512:
1.1.1.6 root 4513: dsp_core.registers[DSP_REG_B2] = dest[0];
4514: dsp_core.registers[DSP_REG_B1] = dest[1];
4515: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4516:
1.1.1.6 root 4517: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4518:
4519: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4520: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4521: }
4522:
1.1.1.6 root 4523: static void dsp_add_y_a(void)
1.1 root 4524: {
1.1.1.6 root 4525: Uint32 source[3], dest[3];
1.1.1.2 root 4526: Uint16 newsr;
1.1 root 4527:
1.1.1.6 root 4528: dest[0] = dsp_core.registers[DSP_REG_A2];
4529: dest[1] = dsp_core.registers[DSP_REG_A1];
4530: dest[2] = dsp_core.registers[DSP_REG_A0];
4531:
4532: source[1] = dsp_core.registers[DSP_REG_Y1];
4533: source[2] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4534: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4535:
1.1.1.6 root 4536: newsr = dsp_add56(source, dest);
1.1 root 4537:
1.1.1.6 root 4538: dsp_core.registers[DSP_REG_A2] = dest[0];
4539: dsp_core.registers[DSP_REG_A1] = dest[1];
4540: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4541:
1.1.1.6 root 4542: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4543:
4544: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4545: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4546: }
4547:
1.1.1.6 root 4548: static void dsp_add_y_b(void)
1.1 root 4549: {
1.1.1.6 root 4550: Uint32 source[3], dest[3];
1.1.1.2 root 4551: Uint16 newsr;
1.1 root 4552:
1.1.1.6 root 4553: dest[0] = dsp_core.registers[DSP_REG_B2];
4554: dest[1] = dsp_core.registers[DSP_REG_B1];
4555: dest[2] = dsp_core.registers[DSP_REG_B0];
4556:
4557: source[1] = dsp_core.registers[DSP_REG_Y1];
4558: source[2] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4559: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4560:
1.1.1.6 root 4561: newsr = dsp_add56(source, dest);
1.1 root 4562:
1.1.1.6 root 4563: dsp_core.registers[DSP_REG_B2] = dest[0];
4564: dsp_core.registers[DSP_REG_B1] = dest[1];
4565: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4566:
1.1.1.6 root 4567: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4568:
1.1.1.6 root 4569: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4570: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4571: }
4572:
1.1.1.6 root 4573: static void dsp_add_x0_a(void)
1.1 root 4574: {
1.1.1.6 root 4575: Uint32 source[3], dest[3];
4576: Uint16 newsr;
1.1 root 4577:
1.1.1.6 root 4578: dest[0] = dsp_core.registers[DSP_REG_A2];
4579: dest[1] = dsp_core.registers[DSP_REG_A1];
4580: dest[2] = dsp_core.registers[DSP_REG_A0];
4581:
4582: source[2] = 0;
4583: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4584: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4585:
4586: newsr = dsp_add56(source, dest);
4587:
4588: dsp_core.registers[DSP_REG_A2] = dest[0];
4589: dsp_core.registers[DSP_REG_A1] = dest[1];
4590: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4591:
1.1.1.6 root 4592: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4593:
1.1.1.6 root 4594: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4595: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4596: }
4597:
1.1.1.6 root 4598: static void dsp_add_x0_b(void)
1.1 root 4599: {
1.1.1.6 root 4600: Uint32 source[3], dest[3];
4601: Uint16 newsr;
4602:
4603: dest[0] = dsp_core.registers[DSP_REG_B2];
4604: dest[1] = dsp_core.registers[DSP_REG_B1];
4605: dest[2] = dsp_core.registers[DSP_REG_B0];
4606:
4607: source[2] = 0;
4608: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4609: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4610:
1.1.1.6 root 4611: newsr = dsp_add56(source, dest);
1.1 root 4612:
1.1.1.6 root 4613: dsp_core.registers[DSP_REG_B2] = dest[0];
4614: dsp_core.registers[DSP_REG_B1] = dest[1];
4615: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4616:
1.1.1.6 root 4617: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4618:
1.1.1.6 root 4619: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4620: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4621: }
4622:
1.1.1.6 root 4623: static void dsp_add_y0_a(void)
1.1 root 4624: {
1.1.1.6 root 4625: Uint32 source[3], dest[3];
4626: Uint16 newsr;
1.1 root 4627:
1.1.1.6 root 4628: dest[0] = dsp_core.registers[DSP_REG_A2];
4629: dest[1] = dsp_core.registers[DSP_REG_A1];
4630: dest[2] = dsp_core.registers[DSP_REG_A0];
4631:
4632: source[2] = 0;
4633: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4634: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4635:
1.1.1.6 root 4636: newsr = dsp_add56(source, dest);
4637:
4638: dsp_core.registers[DSP_REG_A2] = dest[0];
4639: dsp_core.registers[DSP_REG_A1] = dest[1];
4640: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4641:
1.1.1.6 root 4642: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4643:
1.1.1.6 root 4644: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4645: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4646: }
4647:
1.1.1.6 root 4648: static void dsp_add_y0_b(void)
1.1 root 4649: {
1.1.1.6 root 4650: Uint32 source[3], dest[3];
1.1.1.2 root 4651: Uint16 newsr;
1.1 root 4652:
1.1.1.6 root 4653: dest[0] = dsp_core.registers[DSP_REG_B2];
4654: dest[1] = dsp_core.registers[DSP_REG_B1];
4655: dest[2] = dsp_core.registers[DSP_REG_B0];
4656:
4657: source[2] = 0;
4658: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4659: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4660:
4661: newsr = dsp_add56(source, dest);
4662:
1.1.1.6 root 4663: dsp_core.registers[DSP_REG_B2] = dest[0];
4664: dsp_core.registers[DSP_REG_B1] = dest[1];
4665: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4666:
1.1.1.6 root 4667: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4668:
1.1.1.6 root 4669: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4670: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4671: }
4672:
1.1.1.6 root 4673: static void dsp_add_x1_a(void)
1.1 root 4674: {
1.1.1.6 root 4675: Uint32 source[3], dest[3];
1.1.1.2 root 4676: Uint16 newsr;
1.1 root 4677:
1.1.1.6 root 4678: dest[0] = dsp_core.registers[DSP_REG_A2];
4679: dest[1] = dsp_core.registers[DSP_REG_A1];
4680: dest[2] = dsp_core.registers[DSP_REG_A0];
4681:
4682: source[2] = 0;
4683: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4684: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4685:
4686: newsr = dsp_add56(source, dest);
4687:
1.1.1.6 root 4688: dsp_core.registers[DSP_REG_A2] = dest[0];
4689: dsp_core.registers[DSP_REG_A1] = dest[1];
4690: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4691:
1.1.1.6 root 4692: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4693:
1.1.1.6 root 4694: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4695: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4696: }
4697:
1.1.1.6 root 4698: static void dsp_add_x1_b(void)
1.1 root 4699: {
1.1.1.6 root 4700: Uint32 source[3], dest[3];
4701: Uint16 newsr;
4702:
4703: dest[0] = dsp_core.registers[DSP_REG_B2];
4704: dest[1] = dsp_core.registers[DSP_REG_B1];
4705: dest[2] = dsp_core.registers[DSP_REG_B0];
4706:
4707: source[2] = 0;
4708: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4709: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4710:
4711: newsr = dsp_add56(source, dest);
4712:
4713: dsp_core.registers[DSP_REG_B2] = dest[0];
4714: dsp_core.registers[DSP_REG_B1] = dest[1];
4715: dsp_core.registers[DSP_REG_B0] = dest[2];
4716:
4717: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4718:
4719: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4720: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4721: }
4722:
1.1.1.6 root 4723: static void dsp_add_y1_a(void)
1.1 root 4724: {
1.1.1.6 root 4725: Uint32 source[3], dest[3];
4726: Uint16 newsr;
1.1 root 4727:
1.1.1.6 root 4728: dest[0] = dsp_core.registers[DSP_REG_A2];
4729: dest[1] = dsp_core.registers[DSP_REG_A1];
4730: dest[2] = dsp_core.registers[DSP_REG_A0];
4731:
4732: source[2] = 0;
4733: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4734: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4735:
1.1.1.6 root 4736: newsr = dsp_add56(source, dest);
1.1 root 4737:
1.1.1.6 root 4738: dsp_core.registers[DSP_REG_A2] = dest[0];
4739: dsp_core.registers[DSP_REG_A1] = dest[1];
4740: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4741:
1.1.1.6 root 4742: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4743:
1.1.1.6 root 4744: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4745: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4746: }
4747:
1.1.1.6 root 4748: static void dsp_add_y1_b(void)
1.1 root 4749: {
1.1.1.6 root 4750: Uint32 source[3], dest[3];
4751: Uint16 newsr;
1.1 root 4752:
1.1.1.6 root 4753: dest[0] = dsp_core.registers[DSP_REG_B2];
4754: dest[1] = dsp_core.registers[DSP_REG_B1];
4755: dest[2] = dsp_core.registers[DSP_REG_B0];
4756:
4757: source[2] = 0;
4758: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4759: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4760:
1.1.1.6 root 4761: newsr = dsp_add56(source, dest);
1.1 root 4762:
1.1.1.6 root 4763: dsp_core.registers[DSP_REG_B2] = dest[0];
4764: dsp_core.registers[DSP_REG_B1] = dest[1];
4765: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4766:
1.1.1.6 root 4767: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4768:
1.1.1.6 root 4769: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4770: dsp_core.registers[DSP_REG_SR] |= newsr;
4771: }
1.1 root 4772:
1.1.1.6 root 4773: static void dsp_addl_b_a(void)
4774: {
4775: Uint32 source[3], dest[3];
4776: Uint16 newsr;
1.1.1.2 root 4777:
1.1.1.6 root 4778: dest[0] = dsp_core.registers[DSP_REG_A2];
4779: dest[1] = dsp_core.registers[DSP_REG_A1];
4780: dest[2] = dsp_core.registers[DSP_REG_A0];
4781: newsr = dsp_asl56(dest);
1.1 root 4782:
1.1.1.6 root 4783: source[0] = dsp_core.registers[DSP_REG_B2];
4784: source[1] = dsp_core.registers[DSP_REG_B1];
4785: source[2] = dsp_core.registers[DSP_REG_B0];
4786: newsr |= dsp_add56(source, dest);
1.1 root 4787:
1.1.1.6 root 4788: dsp_core.registers[DSP_REG_A2] = dest[0];
4789: dsp_core.registers[DSP_REG_A1] = dest[1];
4790: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4791:
1.1.1.6 root 4792: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4793:
1.1.1.6 root 4794: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4795: dsp_core.registers[DSP_REG_SR] |= newsr;
4796: }
1.1 root 4797:
1.1.1.6 root 4798: static void dsp_addl_a_b(void)
4799: {
4800: Uint32 source[3], dest[3];
4801: Uint16 newsr;
1.1 root 4802:
1.1.1.6 root 4803: dest[0] = dsp_core.registers[DSP_REG_B2];
4804: dest[1] = dsp_core.registers[DSP_REG_B1];
4805: dest[2] = dsp_core.registers[DSP_REG_B0];
4806: newsr = dsp_asl56(dest);
1.1 root 4807:
1.1.1.6 root 4808: source[0] = dsp_core.registers[DSP_REG_A2];
4809: source[1] = dsp_core.registers[DSP_REG_A1];
4810: source[2] = dsp_core.registers[DSP_REG_A0];
4811: newsr |= dsp_add56(source, dest);
4812:
4813: dsp_core.registers[DSP_REG_B2] = dest[0];
4814: dsp_core.registers[DSP_REG_B1] = dest[1];
4815: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4816:
1.1.1.6 root 4817: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4818:
1.1.1.6 root 4819: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4820: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4821: }
4822:
1.1.1.6 root 4823: static void dsp_addr_b_a(void)
1.1 root 4824: {
1.1.1.6 root 4825: Uint32 source[3], dest[3];
4826: Uint16 newsr;
4827:
4828: dest[0] = dsp_core.registers[DSP_REG_A2];
4829: dest[1] = dsp_core.registers[DSP_REG_A1];
4830: dest[2] = dsp_core.registers[DSP_REG_A0];
4831: newsr = dsp_asr56(dest);
4832:
4833: source[0] = dsp_core.registers[DSP_REG_B2];
4834: source[1] = dsp_core.registers[DSP_REG_B1];
4835: source[2] = dsp_core.registers[DSP_REG_B0];
4836: newsr |= dsp_add56(source, dest);
4837:
4838: dsp_core.registers[DSP_REG_A2] = dest[0];
4839: dsp_core.registers[DSP_REG_A1] = dest[1];
4840: dsp_core.registers[DSP_REG_A0] = dest[2];
4841:
4842: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4843:
4844: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4845: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4846: }
4847:
1.1.1.6 root 4848: static void dsp_addr_a_b(void)
1.1 root 4849: {
1.1.1.6 root 4850: Uint32 source[3], dest[3];
4851: Uint16 newsr;
4852:
4853: dest[0] = dsp_core.registers[DSP_REG_B2];
4854: dest[1] = dsp_core.registers[DSP_REG_B1];
4855: dest[2] = dsp_core.registers[DSP_REG_B0];
4856: newsr = dsp_asr56(dest);
4857:
4858: source[0] = dsp_core.registers[DSP_REG_A2];
4859: source[1] = dsp_core.registers[DSP_REG_A1];
4860: source[2] = dsp_core.registers[DSP_REG_A0];
4861: newsr |= dsp_add56(source, dest);
1.1 root 4862:
1.1.1.6 root 4863: dsp_core.registers[DSP_REG_B2] = dest[0];
4864: dsp_core.registers[DSP_REG_B1] = dest[1];
4865: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4866:
1.1.1.6 root 4867: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4868:
1.1.1.6 root 4869: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4870: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4871: }
4872:
1.1.1.6 root 4873: static void dsp_and_x0_a(void)
1.1 root 4874: {
1.1.1.6 root 4875: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X0];
1.1 root 4876:
1.1.1.6 root 4877: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4878: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4879: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4880: }
1.1 root 4881:
1.1.1.6 root 4882: static void dsp_and_x0_b(void)
4883: {
4884: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X0];
1.1 root 4885:
1.1.1.6 root 4886: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4887: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4888: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
1.1 root 4889: }
4890:
1.1.1.6 root 4891: static void dsp_and_y0_a(void)
1.1 root 4892: {
1.1.1.6 root 4893: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y0];
1.1 root 4894:
1.1.1.6 root 4895: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4896: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4897: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4898: }
1.1 root 4899:
1.1.1.6 root 4900: static void dsp_and_y0_b(void)
4901: {
4902: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y0];
1.1 root 4903:
1.1.1.6 root 4904: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4905: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4906: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
4907: }
1.1 root 4908:
1.1.1.6 root 4909: static void dsp_and_x1_a(void)
4910: {
4911: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X1];
1.1.1.2 root 4912:
1.1.1.6 root 4913: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4914: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4915: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
1.1 root 4916: }
4917:
1.1.1.6 root 4918: static void dsp_and_x1_b(void)
1.1 root 4919: {
1.1.1.6 root 4920: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X1];
4921:
4922: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4923: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4924: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
4925: }
1.1 root 4926:
1.1.1.6 root 4927: static void dsp_and_y1_a(void)
4928: {
4929: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y1];
1.1 root 4930:
1.1.1.6 root 4931: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4932: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4933: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4934: }
1.1 root 4935:
1.1.1.6 root 4936: static void dsp_and_y1_b(void)
4937: {
4938: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y1];
1.1.1.2 root 4939:
1.1.1.6 root 4940: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4941: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4942: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
1.1 root 4943: }
4944:
1.1.1.7 root 4945: static void dsp_asl_a(void)
1.1 root 4946: {
1.1.1.6 root 4947: Uint32 dest[3];
4948: Uint16 newsr;
1.1 root 4949:
1.1.1.6 root 4950: dest[0] = dsp_core.registers[DSP_REG_A2];
4951: dest[1] = dsp_core.registers[DSP_REG_A1];
4952: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 4953:
1.1.1.6 root 4954: newsr = dsp_asl56(dest);
4955:
4956: dsp_core.registers[DSP_REG_A2] = dest[0];
4957: dsp_core.registers[DSP_REG_A1] = dest[1];
4958: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4959:
1.1.1.6 root 4960: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
4961: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1.1.2 root 4962:
1.1.1.6 root 4963: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4964: }
4965:
1.1.1.7 root 4966: static void dsp_asl_b(void)
1.1 root 4967: {
1.1.1.6 root 4968: Uint32 dest[3];
1.1.1.2 root 4969: Uint16 newsr;
1.1 root 4970:
1.1.1.6 root 4971: dest[0] = dsp_core.registers[DSP_REG_B2];
4972: dest[1] = dsp_core.registers[DSP_REG_B1];
4973: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 4974:
1.1.1.6 root 4975: newsr = dsp_asl56(dest);
1.1 root 4976:
1.1.1.6 root 4977: dsp_core.registers[DSP_REG_B2] = dest[0];
4978: dsp_core.registers[DSP_REG_B1] = dest[1];
4979: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4980:
1.1.1.6 root 4981: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
4982: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4983:
1.1.1.6 root 4984: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4985: }
4986:
1.1.1.7 root 4987: static void dsp_asr_a(void)
1.1 root 4988: {
1.1.1.6 root 4989: Uint32 dest[3];
4990: Uint16 newsr;
4991:
4992: dest[0] = dsp_core.registers[DSP_REG_A2];
4993: dest[1] = dsp_core.registers[DSP_REG_A1];
4994: dest[2] = dsp_core.registers[DSP_REG_A0];
4995:
4996: newsr = dsp_asr56(dest);
4997:
4998: dsp_core.registers[DSP_REG_A2] = dest[0];
4999: dsp_core.registers[DSP_REG_A1] = dest[1];
5000: dsp_core.registers[DSP_REG_A0] = dest[2];
5001:
5002: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5003: dsp_core.registers[DSP_REG_SR] |= newsr;
5004:
5005: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5006: }
5007:
1.1.1.7 root 5008: static void dsp_asr_b(void)
1.1.1.6 root 5009: {
5010: Uint32 dest[3];
5011: Uint16 newsr;
5012:
5013: dest[0] = dsp_core.registers[DSP_REG_B2];
5014: dest[1] = dsp_core.registers[DSP_REG_B1];
5015: dest[2] = dsp_core.registers[DSP_REG_B0];
5016:
5017: newsr = dsp_asr56(dest);
5018:
5019: dsp_core.registers[DSP_REG_B2] = dest[0];
5020: dsp_core.registers[DSP_REG_B1] = dest[1];
5021: dsp_core.registers[DSP_REG_B0] = dest[2];
5022:
5023: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5024: dsp_core.registers[DSP_REG_SR] |= newsr;
5025:
5026: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5027: }
5028:
5029: static void dsp_clr_a(void)
5030: {
1.1.1.7 root 5031: dsp_core.registers[DSP_REG_A2] = 0;
5032: dsp_core.registers[DSP_REG_A1] = 0;
5033: dsp_core.registers[DSP_REG_A0] = 0;
1.1.1.6 root 5034:
5035: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5036: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5037: }
5038:
5039: static void dsp_clr_b(void)
5040: {
1.1.1.7 root 5041: dsp_core.registers[DSP_REG_B2] = 0;
5042: dsp_core.registers[DSP_REG_B1] = 0;
5043: dsp_core.registers[DSP_REG_B0] = 0;
1.1.1.6 root 5044:
5045: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5046: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5047: }
5048:
5049: static void dsp_cmp_b_a(void)
5050: {
5051: Uint32 source[3], dest[3];
5052: Uint16 newsr;
5053:
5054: dest[0] = dsp_core.registers[DSP_REG_A2];
5055: dest[1] = dsp_core.registers[DSP_REG_A1];
5056: dest[2] = dsp_core.registers[DSP_REG_A0];
5057:
5058: source[0] = dsp_core.registers[DSP_REG_B2];
5059: source[1] = dsp_core.registers[DSP_REG_B1];
5060: source[2] = dsp_core.registers[DSP_REG_B0];
5061:
5062: newsr = dsp_sub56(source, dest);
5063:
5064: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5065:
5066: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5067: dsp_core.registers[DSP_REG_SR] |= newsr;
5068: }
5069:
5070: static void dsp_cmp_a_b(void)
5071: {
5072: Uint32 source[3], dest[3];
5073: Uint16 newsr;
5074:
5075: dest[0] = dsp_core.registers[DSP_REG_B2];
5076: dest[1] = dsp_core.registers[DSP_REG_B1];
5077: dest[2] = dsp_core.registers[DSP_REG_B0];
5078:
5079: source[0] = dsp_core.registers[DSP_REG_A2];
5080: source[1] = dsp_core.registers[DSP_REG_A1];
5081: source[2] = dsp_core.registers[DSP_REG_A0];
5082:
5083: newsr = dsp_sub56(source, dest);
5084:
5085: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5086:
5087: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5088: dsp_core.registers[DSP_REG_SR] |= newsr;
5089: }
5090:
5091: static void dsp_cmp_x0_a(void)
5092: {
5093: Uint32 source[3], dest[3];
5094: Uint16 newsr;
5095:
5096: dest[2] = dsp_core.registers[DSP_REG_A0];
5097: dest[1] = dsp_core.registers[DSP_REG_A1];
5098: dest[0] = dsp_core.registers[DSP_REG_A2];
5099:
5100: source[2] = 0;
5101: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5102: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5103:
5104: newsr = dsp_sub56(source, dest);
5105:
5106: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5107:
5108: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5109: dsp_core.registers[DSP_REG_SR] |= newsr;
5110: }
5111:
5112: static void dsp_cmp_x0_b(void)
5113: {
5114: Uint32 source[3], dest[3];
5115: Uint16 newsr;
5116:
5117: dest[0] = dsp_core.registers[DSP_REG_B2];
5118: dest[1] = dsp_core.registers[DSP_REG_B1];
5119: dest[2] = dsp_core.registers[DSP_REG_B0];
5120:
5121: source[2] = 0;
5122: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5123: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5124:
5125: newsr = dsp_sub56(source, dest);
5126:
5127: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5128:
5129: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5130: dsp_core.registers[DSP_REG_SR] |= newsr;
5131: }
5132:
5133: static void dsp_cmp_y0_a(void)
5134: {
5135: Uint32 source[3], dest[3];
5136: Uint16 newsr;
5137:
5138: dest[2] = dsp_core.registers[DSP_REG_A0];
5139: dest[1] = dsp_core.registers[DSP_REG_A1];
5140: dest[0] = dsp_core.registers[DSP_REG_A2];
5141:
5142: source[2] = 0;
5143: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5144: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5145:
5146: newsr = dsp_sub56(source, dest);
5147:
5148: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5149:
5150: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5151: dsp_core.registers[DSP_REG_SR] |= newsr;
5152: }
5153:
5154: static void dsp_cmp_y0_b(void)
5155: {
5156: Uint32 source[3], dest[3];
5157: Uint16 newsr;
5158:
5159: dest[0] = dsp_core.registers[DSP_REG_B2];
5160: dest[1] = dsp_core.registers[DSP_REG_B1];
5161: dest[2] = dsp_core.registers[DSP_REG_B0];
5162:
5163: source[2] = 0;
5164: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5165: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5166:
5167: newsr = dsp_sub56(source, dest);
5168:
5169: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5170:
5171: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5172: dsp_core.registers[DSP_REG_SR] |= newsr;
5173: }
5174: static void dsp_cmp_x1_a(void)
5175: {
5176: Uint32 source[3], dest[3];
5177: Uint16 newsr;
5178:
5179: dest[2] = dsp_core.registers[DSP_REG_A0];
5180: dest[1] = dsp_core.registers[DSP_REG_A1];
5181: dest[0] = dsp_core.registers[DSP_REG_A2];
5182:
5183: source[2] = 0;
5184: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5185: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5186:
5187: newsr = dsp_sub56(source, dest);
5188:
5189: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5190:
5191: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5192: dsp_core.registers[DSP_REG_SR] |= newsr;
5193: }
5194:
5195: static void dsp_cmp_x1_b(void)
5196: {
5197: Uint32 source[3], dest[3];
5198: Uint16 newsr;
5199:
5200: dest[0] = dsp_core.registers[DSP_REG_B2];
5201: dest[1] = dsp_core.registers[DSP_REG_B1];
5202: dest[2] = dsp_core.registers[DSP_REG_B0];
5203:
5204: source[2] = 0;
5205: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5206: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5207:
5208: newsr = dsp_sub56(source, dest);
5209:
5210: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5211:
5212: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5213: dsp_core.registers[DSP_REG_SR] |= newsr;
5214: }
5215:
5216: static void dsp_cmp_y1_a(void)
5217: {
5218: Uint32 source[3], dest[3];
5219: Uint16 newsr;
5220:
5221: dest[2] = dsp_core.registers[DSP_REG_A0];
5222: dest[1] = dsp_core.registers[DSP_REG_A1];
5223: dest[0] = dsp_core.registers[DSP_REG_A2];
5224:
5225: source[2] = 0;
5226: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5227: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5228:
5229: newsr = dsp_sub56(source, dest);
5230:
5231: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5232:
5233: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5234: dsp_core.registers[DSP_REG_SR] |= newsr;
5235: }
5236:
5237: static void dsp_cmp_y1_b(void)
5238: {
5239: Uint32 source[3], dest[3];
5240: Uint16 newsr;
5241:
5242: dest[0] = dsp_core.registers[DSP_REG_B2];
5243: dest[1] = dsp_core.registers[DSP_REG_B1];
5244: dest[2] = dsp_core.registers[DSP_REG_B0];
5245:
5246: source[2] = 0;
5247: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5248: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5249:
5250: newsr = dsp_sub56(source, dest);
5251:
5252: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5253:
5254: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5255: dsp_core.registers[DSP_REG_SR] |= newsr;
5256: }
5257:
5258: static void dsp_cmpm_b_a(void)
5259: {
5260: Uint32 source[3], dest[3];
5261: Uint16 newsr;
5262:
5263: dest[0] = dsp_core.registers[DSP_REG_A2];
5264: dest[1] = dsp_core.registers[DSP_REG_A1];
5265: dest[2] = dsp_core.registers[DSP_REG_A0];
5266: dsp_abs56(dest);
5267:
5268: source[0] = dsp_core.registers[DSP_REG_B2];
5269: source[1] = dsp_core.registers[DSP_REG_B1];
5270: source[2] = dsp_core.registers[DSP_REG_B0];
5271: dsp_abs56(source);
5272:
5273: newsr = dsp_sub56(source, dest);
5274:
5275: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5276:
5277: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5278: dsp_core.registers[DSP_REG_SR] |= newsr;
5279: }
5280:
5281: static void dsp_cmpm_a_b(void)
5282: {
5283: Uint32 source[3], dest[3];
5284: Uint16 newsr;
5285:
5286: dest[0] = dsp_core.registers[DSP_REG_B2];
5287: dest[1] = dsp_core.registers[DSP_REG_B1];
5288: dest[2] = dsp_core.registers[DSP_REG_B0];
5289: dsp_abs56(dest);
5290:
5291: source[0] = dsp_core.registers[DSP_REG_A2];
5292: source[1] = dsp_core.registers[DSP_REG_A1];
5293: source[2] = dsp_core.registers[DSP_REG_A0];
5294: dsp_abs56(source);
5295:
5296: newsr = dsp_sub56(source, dest);
5297:
5298: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5299:
5300: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5301: dsp_core.registers[DSP_REG_SR] |= newsr;
5302: }
5303:
5304: static void dsp_cmpm_x0_a(void)
5305: {
5306: Uint32 source[3], dest[3];
5307: Uint16 newsr;
5308:
5309: dest[2] = dsp_core.registers[DSP_REG_A0];
5310: dest[1] = dsp_core.registers[DSP_REG_A1];
5311: dest[0] = dsp_core.registers[DSP_REG_A2];
5312: dsp_abs56(dest);
5313:
5314: source[2] = 0;
5315: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5316: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5317: dsp_abs56(source);
5318:
5319: newsr = dsp_sub56(source, dest);
5320:
5321: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5322:
5323: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5324: dsp_core.registers[DSP_REG_SR] |= newsr;
5325: }
5326:
5327: static void dsp_cmpm_x0_b(void)
5328: {
5329: Uint32 source[3], dest[3];
5330: Uint16 newsr;
5331:
5332: dest[0] = dsp_core.registers[DSP_REG_B2];
5333: dest[1] = dsp_core.registers[DSP_REG_B1];
5334: dest[2] = dsp_core.registers[DSP_REG_B0];
5335: dsp_abs56(dest);
5336:
5337: source[2] = 0;
5338: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5339: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5340: dsp_abs56(source);
5341:
5342: newsr = dsp_sub56(source, dest);
5343:
5344: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5345:
5346: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5347: dsp_core.registers[DSP_REG_SR] |= newsr;
5348: }
5349:
5350: static void dsp_cmpm_y0_a(void)
5351: {
5352: Uint32 source[3], dest[3];
5353: Uint16 newsr;
5354:
5355: dest[2] = dsp_core.registers[DSP_REG_A0];
5356: dest[1] = dsp_core.registers[DSP_REG_A1];
5357: dest[0] = dsp_core.registers[DSP_REG_A2];
5358: dsp_abs56(dest);
5359:
5360: source[2] = 0;
5361: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5362: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5363: dsp_abs56(source);
5364:
5365: newsr = dsp_sub56(source, dest);
5366:
5367: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5368:
5369: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5370: dsp_core.registers[DSP_REG_SR] |= newsr;
5371: }
5372:
5373: static void dsp_cmpm_y0_b(void)
5374: {
5375: Uint32 source[3], dest[3];
5376: Uint16 newsr;
5377:
5378: dest[0] = dsp_core.registers[DSP_REG_B2];
5379: dest[1] = dsp_core.registers[DSP_REG_B1];
5380: dest[2] = dsp_core.registers[DSP_REG_B0];
5381: dsp_abs56(dest);
5382:
5383: source[2] = 0;
5384: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5385: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5386: dsp_abs56(source);
5387:
5388: newsr = dsp_sub56(source, dest);
5389:
5390: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5391:
5392: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5393: dsp_core.registers[DSP_REG_SR] |= newsr;
5394: }
5395:
5396: static void dsp_cmpm_x1_a(void)
5397: {
5398: Uint32 source[3], dest[3];
5399: Uint16 newsr;
5400:
5401: dest[2] = dsp_core.registers[DSP_REG_A0];
5402: dest[1] = dsp_core.registers[DSP_REG_A1];
5403: dest[0] = dsp_core.registers[DSP_REG_A2];
5404: dsp_abs56(dest);
5405:
5406: source[2] = 0;
5407: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5408: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5409: dsp_abs56(source);
5410:
5411: newsr = dsp_sub56(source, dest);
5412:
5413: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5414:
5415: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5416: dsp_core.registers[DSP_REG_SR] |= newsr;
5417: }
5418:
5419: static void dsp_cmpm_x1_b(void)
5420: {
5421: Uint32 source[3], dest[3];
5422: Uint16 newsr;
5423:
5424: dest[0] = dsp_core.registers[DSP_REG_B2];
5425: dest[1] = dsp_core.registers[DSP_REG_B1];
5426: dest[2] = dsp_core.registers[DSP_REG_B0];
5427: dsp_abs56(dest);
5428:
5429: source[2] = 0;
5430: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5431: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5432: dsp_abs56(source);
5433:
5434: newsr = dsp_sub56(source, dest);
5435:
5436: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5437:
5438: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5439: dsp_core.registers[DSP_REG_SR] |= newsr;
5440: }
5441:
5442: static void dsp_cmpm_y1_a(void)
5443: {
5444: Uint32 source[3], dest[3];
5445: Uint16 newsr;
5446:
5447: dest[2] = dsp_core.registers[DSP_REG_A0];
5448: dest[1] = dsp_core.registers[DSP_REG_A1];
5449: dest[0] = dsp_core.registers[DSP_REG_A2];
5450: dsp_abs56(dest);
5451:
5452: source[2] = 0;
5453: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5454: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5455: dsp_abs56(source);
5456:
5457: newsr = dsp_sub56(source, dest);
5458:
5459: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5460:
5461: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5462: dsp_core.registers[DSP_REG_SR] |= newsr;
5463: }
5464:
5465: static void dsp_cmpm_y1_b(void)
5466: {
5467: Uint32 source[3], dest[3];
5468: Uint16 newsr;
5469:
5470: dest[0] = dsp_core.registers[DSP_REG_B2];
5471: dest[1] = dsp_core.registers[DSP_REG_B1];
5472: dest[2] = dsp_core.registers[DSP_REG_B0];
5473: dsp_abs56(dest);
5474:
5475: source[2] = 0;
5476: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5477: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5478: dsp_abs56(source);
5479:
5480: newsr = dsp_sub56(source, dest);
5481:
5482: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5483:
5484: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5485: dsp_core.registers[DSP_REG_SR] |= newsr;
5486: }
5487:
5488: static void dsp_eor_x0_a(void)
5489: {
5490: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X0];
5491: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5492:
5493: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5494: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5495: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5496: }
5497:
5498: static void dsp_eor_x0_b(void)
5499: {
5500: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X0];
5501: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5502:
5503: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5504: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5505: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5506: }
5507:
5508: static void dsp_eor_y0_a(void)
5509: {
5510: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y0];
5511: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5512:
5513: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5514: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5515: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5516: }
5517:
5518: static void dsp_eor_y0_b(void)
5519: {
5520: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y0];
5521: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5522:
5523: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5524: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5525: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5526: }
5527:
5528: static void dsp_eor_x1_a(void)
5529: {
5530: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X1];
5531: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5532:
5533: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5534: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5535: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5536: }
5537:
5538: static void dsp_eor_x1_b(void)
5539: {
5540: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X1];
5541: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5542:
5543: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5544: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5545: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5546: }
5547:
5548: static void dsp_eor_y1_a(void)
5549: {
5550: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y1];
5551: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5552:
5553: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5554: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5555: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5556: }
5557:
5558: static void dsp_eor_y1_b(void)
5559: {
5560: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y1];
5561: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5562:
5563: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5564: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5565: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5566: }
5567:
5568: static void dsp_lsl_a(void)
5569: {
5570: Uint32 newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
5571:
5572: dsp_core.registers[DSP_REG_A1] <<= 1;
5573: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
5574:
5575: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5576: dsp_core.registers[DSP_REG_SR] |= newcarry;
5577: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5578: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5579: }
5580:
5581: static void dsp_lsl_b(void)
5582: {
5583: Uint32 newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
5584:
5585: dsp_core.registers[DSP_REG_B1] <<= 1;
5586: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
5587:
5588: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5589: dsp_core.registers[DSP_REG_SR] |= newcarry;
5590: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5591: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5592: }
5593:
5594: static void dsp_lsr_a(void)
5595: {
5596: Uint32 newcarry = dsp_core.registers[DSP_REG_A1] & 1;
5597: dsp_core.registers[DSP_REG_A1] >>= 1;
5598:
5599: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5600: dsp_core.registers[DSP_REG_SR] |= newcarry;
5601: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5602: }
5603:
5604: static void dsp_lsr_b(void)
5605: {
5606: Uint32 newcarry = dsp_core.registers[DSP_REG_B1] & 1;
5607: dsp_core.registers[DSP_REG_B1] >>= 1;
5608:
5609: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5610: dsp_core.registers[DSP_REG_SR] |= newcarry;
5611: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5612: }
5613:
5614: static void dsp_mac_p_x0_x0_a(void)
5615: {
5616: Uint32 source[3], dest[3];
5617: Uint16 newsr;
5618:
5619: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5620:
5621: dest[0] = dsp_core.registers[DSP_REG_A2];
5622: dest[1] = dsp_core.registers[DSP_REG_A1];
5623: dest[2] = dsp_core.registers[DSP_REG_A0];
5624: newsr = dsp_add56(source, dest);
5625:
5626: dsp_core.registers[DSP_REG_A2] = dest[0];
5627: dsp_core.registers[DSP_REG_A1] = dest[1];
5628: dsp_core.registers[DSP_REG_A0] = dest[2];
5629:
5630: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5631:
5632: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5633: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5634: }
5635:
5636: static void dsp_mac_m_x0_x0_a(void)
5637: {
5638: Uint32 source[3], dest[3];
5639: Uint16 newsr;
5640:
5641: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5642:
5643: dest[0] = dsp_core.registers[DSP_REG_A2];
5644: dest[1] = dsp_core.registers[DSP_REG_A1];
5645: dest[2] = dsp_core.registers[DSP_REG_A0];
5646: newsr = dsp_add56(source, dest);
5647:
5648: dsp_core.registers[DSP_REG_A2] = dest[0];
5649: dsp_core.registers[DSP_REG_A1] = dest[1];
5650: dsp_core.registers[DSP_REG_A0] = dest[2];
5651:
5652: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5653:
5654: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5655: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5656: }
5657: static void dsp_mac_p_x0_x0_b(void)
5658: {
5659: Uint32 source[3], dest[3];
5660: Uint16 newsr;
5661:
5662: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5663:
5664: dest[0] = dsp_core.registers[DSP_REG_B2];
5665: dest[1] = dsp_core.registers[DSP_REG_B1];
5666: dest[2] = dsp_core.registers[DSP_REG_B0];
5667: newsr = dsp_add56(source, dest);
5668:
5669: dsp_core.registers[DSP_REG_B2] = dest[0];
5670: dsp_core.registers[DSP_REG_B1] = dest[1];
5671: dsp_core.registers[DSP_REG_B0] = dest[2];
5672:
5673: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5674:
5675: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5676: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5677: }
5678:
5679: static void dsp_mac_m_x0_x0_b(void)
5680: {
5681: Uint32 source[3], dest[3];
5682: Uint16 newsr;
5683:
5684: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5685:
5686: dest[0] = dsp_core.registers[DSP_REG_B2];
5687: dest[1] = dsp_core.registers[DSP_REG_B1];
5688: dest[2] = dsp_core.registers[DSP_REG_B0];
5689: newsr = dsp_add56(source, dest);
5690:
5691: dsp_core.registers[DSP_REG_B2] = dest[0];
5692: dsp_core.registers[DSP_REG_B1] = dest[1];
5693: dsp_core.registers[DSP_REG_B0] = dest[2];
5694:
5695: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5696:
5697: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5698: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5699: }
5700:
5701: static void dsp_mac_p_y0_y0_a(void)
5702: {
5703: Uint32 source[3], dest[3];
5704: Uint16 newsr;
5705:
5706: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5707:
5708: dest[0] = dsp_core.registers[DSP_REG_A2];
5709: dest[1] = dsp_core.registers[DSP_REG_A1];
5710: dest[2] = dsp_core.registers[DSP_REG_A0];
5711: newsr = dsp_add56(source, dest);
5712:
5713: dsp_core.registers[DSP_REG_A2] = dest[0];
5714: dsp_core.registers[DSP_REG_A1] = dest[1];
5715: dsp_core.registers[DSP_REG_A0] = dest[2];
5716:
5717: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5718:
5719: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5720: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5721: }
5722:
5723: static void dsp_mac_m_y0_y0_a(void)
5724: {
5725: Uint32 source[3], dest[3];
5726: Uint16 newsr;
5727:
5728: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5729:
5730: dest[0] = dsp_core.registers[DSP_REG_A2];
5731: dest[1] = dsp_core.registers[DSP_REG_A1];
5732: dest[2] = dsp_core.registers[DSP_REG_A0];
5733: newsr = dsp_add56(source, dest);
5734:
5735: dsp_core.registers[DSP_REG_A2] = dest[0];
5736: dsp_core.registers[DSP_REG_A1] = dest[1];
5737: dsp_core.registers[DSP_REG_A0] = dest[2];
5738:
5739: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5740:
5741: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5742: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5743: }
5744: static void dsp_mac_p_y0_y0_b(void)
5745: {
5746: Uint32 source[3], dest[3];
5747: Uint16 newsr;
5748:
5749: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5750:
5751: dest[0] = dsp_core.registers[DSP_REG_B2];
5752: dest[1] = dsp_core.registers[DSP_REG_B1];
5753: dest[2] = dsp_core.registers[DSP_REG_B0];
5754: newsr = dsp_add56(source, dest);
5755:
5756: dsp_core.registers[DSP_REG_B2] = dest[0];
5757: dsp_core.registers[DSP_REG_B1] = dest[1];
5758: dsp_core.registers[DSP_REG_B0] = dest[2];
5759:
5760: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5761:
5762: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5763: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5764: }
5765:
5766: static void dsp_mac_m_y0_y0_b(void)
5767: {
5768: Uint32 source[3], dest[3];
5769: Uint16 newsr;
5770:
5771: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5772:
5773: dest[0] = dsp_core.registers[DSP_REG_B2];
5774: dest[1] = dsp_core.registers[DSP_REG_B1];
5775: dest[2] = dsp_core.registers[DSP_REG_B0];
5776: newsr = dsp_add56(source, dest);
5777:
5778: dsp_core.registers[DSP_REG_B2] = dest[0];
5779: dsp_core.registers[DSP_REG_B1] = dest[1];
5780: dsp_core.registers[DSP_REG_B0] = dest[2];
5781:
5782: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5783:
5784: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5785: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5786: }
5787:
5788: static void dsp_mac_p_x1_x0_a(void)
5789: {
5790: Uint32 source[3], dest[3];
5791: Uint16 newsr;
5792:
5793: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5794:
5795: dest[0] = dsp_core.registers[DSP_REG_A2];
5796: dest[1] = dsp_core.registers[DSP_REG_A1];
5797: dest[2] = dsp_core.registers[DSP_REG_A0];
5798: newsr = dsp_add56(source, dest);
5799:
5800: dsp_core.registers[DSP_REG_A2] = dest[0];
5801: dsp_core.registers[DSP_REG_A1] = dest[1];
5802: dsp_core.registers[DSP_REG_A0] = dest[2];
5803:
5804: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5805:
5806: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5807: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5808: }
5809:
5810: static void dsp_mac_m_x1_x0_a(void)
5811: {
5812: Uint32 source[3], dest[3];
5813: Uint16 newsr;
5814:
5815: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5816:
5817: dest[0] = dsp_core.registers[DSP_REG_A2];
5818: dest[1] = dsp_core.registers[DSP_REG_A1];
5819: dest[2] = dsp_core.registers[DSP_REG_A0];
5820: newsr = dsp_add56(source, dest);
5821:
5822: dsp_core.registers[DSP_REG_A2] = dest[0];
5823: dsp_core.registers[DSP_REG_A1] = dest[1];
5824: dsp_core.registers[DSP_REG_A0] = dest[2];
5825:
5826: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5827:
5828: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5829: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5830: }
5831:
5832: static void dsp_mac_p_x1_x0_b(void)
5833: {
5834: Uint32 source[3], dest[3];
5835: Uint16 newsr;
5836:
5837: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5838:
5839: dest[0] = dsp_core.registers[DSP_REG_B2];
5840: dest[1] = dsp_core.registers[DSP_REG_B1];
5841: dest[2] = dsp_core.registers[DSP_REG_B0];
5842: newsr = dsp_add56(source, dest);
5843:
5844: dsp_core.registers[DSP_REG_B2] = dest[0];
5845: dsp_core.registers[DSP_REG_B1] = dest[1];
5846: dsp_core.registers[DSP_REG_B0] = dest[2];
5847:
5848: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5849:
5850: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5851: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5852: }
5853:
5854: static void dsp_mac_m_x1_x0_b(void)
5855: {
5856: Uint32 source[3], dest[3];
5857: Uint16 newsr;
5858:
5859: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5860:
5861: dest[0] = dsp_core.registers[DSP_REG_B2];
5862: dest[1] = dsp_core.registers[DSP_REG_B1];
5863: dest[2] = dsp_core.registers[DSP_REG_B0];
5864: newsr = dsp_add56(source, dest);
5865:
5866: dsp_core.registers[DSP_REG_B2] = dest[0];
5867: dsp_core.registers[DSP_REG_B1] = dest[1];
5868: dsp_core.registers[DSP_REG_B0] = dest[2];
5869:
5870: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5871:
5872: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5873: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5874: }
5875:
5876: static void dsp_mac_p_y1_y0_a(void)
5877: {
5878: Uint32 source[3], dest[3];
5879: Uint16 newsr;
5880:
5881: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5882:
5883: dest[0] = dsp_core.registers[DSP_REG_A2];
5884: dest[1] = dsp_core.registers[DSP_REG_A1];
5885: dest[2] = dsp_core.registers[DSP_REG_A0];
5886: newsr = dsp_add56(source, dest);
5887:
5888: dsp_core.registers[DSP_REG_A2] = dest[0];
5889: dsp_core.registers[DSP_REG_A1] = dest[1];
5890: dsp_core.registers[DSP_REG_A0] = dest[2];
5891:
5892: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5893:
5894: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5895: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5896: }
5897:
5898: static void dsp_mac_m_y1_y0_a(void)
5899: {
5900: Uint32 source[3], dest[3];
5901: Uint16 newsr;
5902:
5903: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5904:
5905: dest[0] = dsp_core.registers[DSP_REG_A2];
5906: dest[1] = dsp_core.registers[DSP_REG_A1];
5907: dest[2] = dsp_core.registers[DSP_REG_A0];
5908: newsr = dsp_add56(source, dest);
5909:
5910: dsp_core.registers[DSP_REG_A2] = dest[0];
5911: dsp_core.registers[DSP_REG_A1] = dest[1];
5912: dsp_core.registers[DSP_REG_A0] = dest[2];
5913:
5914: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5915:
5916: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5917: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5918: }
5919:
5920: static void dsp_mac_p_y1_y0_b(void)
5921: {
5922: Uint32 source[3], dest[3];
5923: Uint16 newsr;
5924:
5925: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5926:
5927: dest[0] = dsp_core.registers[DSP_REG_B2];
5928: dest[1] = dsp_core.registers[DSP_REG_B1];
5929: dest[2] = dsp_core.registers[DSP_REG_B0];
5930: newsr = dsp_add56(source, dest);
5931:
5932: dsp_core.registers[DSP_REG_B2] = dest[0];
5933: dsp_core.registers[DSP_REG_B1] = dest[1];
5934: dsp_core.registers[DSP_REG_B0] = dest[2];
5935:
5936: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5937:
5938: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5939: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5940: }
5941:
5942: static void dsp_mac_m_y1_y0_b(void)
5943: {
5944: Uint32 source[3], dest[3];
5945: Uint16 newsr;
5946:
5947: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5948:
5949: dest[0] = dsp_core.registers[DSP_REG_B2];
5950: dest[1] = dsp_core.registers[DSP_REG_B1];
5951: dest[2] = dsp_core.registers[DSP_REG_B0];
5952: newsr = dsp_add56(source, dest);
5953:
5954: dsp_core.registers[DSP_REG_B2] = dest[0];
5955: dsp_core.registers[DSP_REG_B1] = dest[1];
5956: dsp_core.registers[DSP_REG_B0] = dest[2];
5957:
5958: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5959:
5960: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5961: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5962: }
5963:
5964: static void dsp_mac_p_x0_y1_a(void)
5965: {
5966: Uint32 source[3], dest[3];
5967: Uint16 newsr;
5968:
5969: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
5970:
5971: dest[0] = dsp_core.registers[DSP_REG_A2];
5972: dest[1] = dsp_core.registers[DSP_REG_A1];
5973: dest[2] = dsp_core.registers[DSP_REG_A0];
5974: newsr = dsp_add56(source, dest);
5975:
5976: dsp_core.registers[DSP_REG_A2] = dest[0];
5977: dsp_core.registers[DSP_REG_A1] = dest[1];
5978: dsp_core.registers[DSP_REG_A0] = dest[2];
5979:
5980: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5981:
5982: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5983: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5984: }
5985:
5986: static void dsp_mac_m_x0_y1_a(void)
5987: {
5988: Uint32 source[3], dest[3];
5989: Uint16 newsr;
5990:
5991: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
5992:
5993: dest[0] = dsp_core.registers[DSP_REG_A2];
5994: dest[1] = dsp_core.registers[DSP_REG_A1];
5995: dest[2] = dsp_core.registers[DSP_REG_A0];
5996: newsr = dsp_add56(source, dest);
5997:
5998: dsp_core.registers[DSP_REG_A2] = dest[0];
5999: dsp_core.registers[DSP_REG_A1] = dest[1];
6000: dsp_core.registers[DSP_REG_A0] = dest[2];
6001:
6002: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6003:
6004: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6005: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6006: }
6007:
6008: static void dsp_mac_p_x0_y1_b(void)
6009: {
6010: Uint32 source[3], dest[3];
6011: Uint16 newsr;
6012:
6013: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6014:
6015: dest[0] = dsp_core.registers[DSP_REG_B2];
6016: dest[1] = dsp_core.registers[DSP_REG_B1];
6017: dest[2] = dsp_core.registers[DSP_REG_B0];
6018: newsr = dsp_add56(source, dest);
6019:
6020: dsp_core.registers[DSP_REG_B2] = dest[0];
6021: dsp_core.registers[DSP_REG_B1] = dest[1];
6022: dsp_core.registers[DSP_REG_B0] = dest[2];
6023:
6024: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6025:
6026: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6027: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6028: }
6029:
6030: static void dsp_mac_m_x0_y1_b(void)
6031: {
6032: Uint32 source[3], dest[3];
6033: Uint16 newsr;
6034:
6035: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6036:
6037: dest[0] = dsp_core.registers[DSP_REG_B2];
6038: dest[1] = dsp_core.registers[DSP_REG_B1];
6039: dest[2] = dsp_core.registers[DSP_REG_B0];
6040: newsr = dsp_add56(source, dest);
6041:
6042: dsp_core.registers[DSP_REG_B2] = dest[0];
6043: dsp_core.registers[DSP_REG_B1] = dest[1];
6044: dsp_core.registers[DSP_REG_B0] = dest[2];
6045:
6046: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6047:
6048: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6049: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6050: }
6051:
6052: static void dsp_mac_p_y0_x0_a(void)
6053: {
6054: Uint32 source[3], dest[3];
6055: Uint16 newsr;
6056:
6057: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6058:
6059: dest[0] = dsp_core.registers[DSP_REG_A2];
6060: dest[1] = dsp_core.registers[DSP_REG_A1];
6061: dest[2] = dsp_core.registers[DSP_REG_A0];
6062: newsr = dsp_add56(source, dest);
6063:
6064: dsp_core.registers[DSP_REG_A2] = dest[0];
6065: dsp_core.registers[DSP_REG_A1] = dest[1];
6066: dsp_core.registers[DSP_REG_A0] = dest[2];
6067:
6068: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6069:
6070: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6071: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6072: }
6073:
6074: static void dsp_mac_m_y0_x0_a(void)
6075: {
6076: Uint32 source[3], dest[3];
6077: Uint16 newsr;
6078:
6079: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6080:
6081: dest[0] = dsp_core.registers[DSP_REG_A2];
6082: dest[1] = dsp_core.registers[DSP_REG_A1];
6083: dest[2] = dsp_core.registers[DSP_REG_A0];
6084: newsr = dsp_add56(source, dest);
6085:
6086: dsp_core.registers[DSP_REG_A2] = dest[0];
6087: dsp_core.registers[DSP_REG_A1] = dest[1];
6088: dsp_core.registers[DSP_REG_A0] = dest[2];
6089:
6090: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6091:
6092: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6093: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6094: }
6095:
6096: static void dsp_mac_p_y0_x0_b(void)
6097: {
6098: Uint32 source[3], dest[3];
6099: Uint16 newsr;
6100:
6101: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6102:
6103: dest[0] = dsp_core.registers[DSP_REG_B2];
6104: dest[1] = dsp_core.registers[DSP_REG_B1];
6105: dest[2] = dsp_core.registers[DSP_REG_B0];
6106: newsr = dsp_add56(source, dest);
6107:
6108: dsp_core.registers[DSP_REG_B2] = dest[0];
6109: dsp_core.registers[DSP_REG_B1] = dest[1];
6110: dsp_core.registers[DSP_REG_B0] = dest[2];
6111:
6112: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6113:
6114: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6115: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6116: }
6117:
6118: static void dsp_mac_m_y0_x0_b(void)
6119: {
6120: Uint32 source[3], dest[3];
6121: Uint16 newsr;
6122:
6123: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6124:
6125: dest[0] = dsp_core.registers[DSP_REG_B2];
6126: dest[1] = dsp_core.registers[DSP_REG_B1];
6127: dest[2] = dsp_core.registers[DSP_REG_B0];
6128: newsr = dsp_add56(source, dest);
6129:
6130: dsp_core.registers[DSP_REG_B2] = dest[0];
6131: dsp_core.registers[DSP_REG_B1] = dest[1];
6132: dsp_core.registers[DSP_REG_B0] = dest[2];
6133:
6134: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6135:
6136: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6137: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6138: }
6139:
6140: static void dsp_mac_p_x1_y0_a(void)
6141: {
6142: Uint32 source[3], dest[3];
6143: Uint16 newsr;
6144:
6145: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6146:
6147: dest[0] = dsp_core.registers[DSP_REG_A2];
6148: dest[1] = dsp_core.registers[DSP_REG_A1];
6149: dest[2] = dsp_core.registers[DSP_REG_A0];
6150: newsr = dsp_add56(source, dest);
6151:
6152: dsp_core.registers[DSP_REG_A2] = dest[0];
6153: dsp_core.registers[DSP_REG_A1] = dest[1];
6154: dsp_core.registers[DSP_REG_A0] = dest[2];
6155:
6156: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6157:
6158: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6159: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6160: }
6161:
6162: static void dsp_mac_m_x1_y0_a(void)
6163: {
6164: Uint32 source[3], dest[3];
6165: Uint16 newsr;
6166:
6167: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6168:
6169: dest[0] = dsp_core.registers[DSP_REG_A2];
6170: dest[1] = dsp_core.registers[DSP_REG_A1];
6171: dest[2] = dsp_core.registers[DSP_REG_A0];
6172: newsr = dsp_add56(source, dest);
6173:
6174: dsp_core.registers[DSP_REG_A2] = dest[0];
6175: dsp_core.registers[DSP_REG_A1] = dest[1];
6176: dsp_core.registers[DSP_REG_A0] = dest[2];
6177:
6178: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6179:
6180: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6181: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6182: }
6183:
6184: static void dsp_mac_p_x1_y0_b(void)
6185: {
6186: Uint32 source[3], dest[3];
6187: Uint16 newsr;
6188:
6189: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6190:
6191: dest[0] = dsp_core.registers[DSP_REG_B2];
6192: dest[1] = dsp_core.registers[DSP_REG_B1];
6193: dest[2] = dsp_core.registers[DSP_REG_B0];
6194: newsr = dsp_add56(source, dest);
6195:
6196: dsp_core.registers[DSP_REG_B2] = dest[0];
6197: dsp_core.registers[DSP_REG_B1] = dest[1];
6198: dsp_core.registers[DSP_REG_B0] = dest[2];
6199:
6200: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6201:
6202: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6203: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6204: }
6205:
6206: static void dsp_mac_m_x1_y0_b(void)
6207: {
6208: Uint32 source[3], dest[3];
6209: Uint16 newsr;
6210:
6211: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6212:
6213: dest[0] = dsp_core.registers[DSP_REG_B2];
6214: dest[1] = dsp_core.registers[DSP_REG_B1];
6215: dest[2] = dsp_core.registers[DSP_REG_B0];
6216: newsr = dsp_add56(source, dest);
6217:
6218: dsp_core.registers[DSP_REG_B2] = dest[0];
6219: dsp_core.registers[DSP_REG_B1] = dest[1];
6220: dsp_core.registers[DSP_REG_B0] = dest[2];
6221:
6222: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6223:
6224: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6225: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6226: }
6227:
6228: static void dsp_mac_p_y1_x1_a(void)
6229: {
6230: Uint32 source[3], dest[3];
6231: Uint16 newsr;
6232:
6233: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6234:
6235: dest[0] = dsp_core.registers[DSP_REG_A2];
6236: dest[1] = dsp_core.registers[DSP_REG_A1];
6237: dest[2] = dsp_core.registers[DSP_REG_A0];
6238: newsr = dsp_add56(source, dest);
6239:
6240: dsp_core.registers[DSP_REG_A2] = dest[0];
6241: dsp_core.registers[DSP_REG_A1] = dest[1];
6242: dsp_core.registers[DSP_REG_A0] = dest[2];
6243:
6244: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6245:
6246: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6247: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6248: }
6249:
6250: static void dsp_mac_m_y1_x1_a(void)
6251: {
6252: Uint32 source[3], dest[3];
6253: Uint16 newsr;
6254:
6255: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6256:
6257: dest[0] = dsp_core.registers[DSP_REG_A2];
6258: dest[1] = dsp_core.registers[DSP_REG_A1];
6259: dest[2] = dsp_core.registers[DSP_REG_A0];
6260: newsr = dsp_add56(source, dest);
6261:
6262: dsp_core.registers[DSP_REG_A2] = dest[0];
6263: dsp_core.registers[DSP_REG_A1] = dest[1];
6264: dsp_core.registers[DSP_REG_A0] = dest[2];
6265:
6266: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6267:
6268: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6269: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6270: }
6271:
6272: static void dsp_mac_p_y1_x1_b(void)
6273: {
6274: Uint32 source[3], dest[3];
6275: Uint16 newsr;
6276:
6277: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6278:
6279: dest[0] = dsp_core.registers[DSP_REG_B2];
6280: dest[1] = dsp_core.registers[DSP_REG_B1];
6281: dest[2] = dsp_core.registers[DSP_REG_B0];
6282: newsr = dsp_add56(source, dest);
6283:
6284: dsp_core.registers[DSP_REG_B2] = dest[0];
6285: dsp_core.registers[DSP_REG_B1] = dest[1];
6286: dsp_core.registers[DSP_REG_B0] = dest[2];
6287:
6288: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6289:
6290: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6291: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6292: }
6293:
6294: static void dsp_mac_m_y1_x1_b(void)
6295: {
6296: Uint32 source[3], dest[3];
6297: Uint16 newsr;
6298:
6299: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6300:
6301: dest[0] = dsp_core.registers[DSP_REG_B2];
6302: dest[1] = dsp_core.registers[DSP_REG_B1];
6303: dest[2] = dsp_core.registers[DSP_REG_B0];
6304: newsr = dsp_add56(source, dest);
6305:
6306: dsp_core.registers[DSP_REG_B2] = dest[0];
6307: dsp_core.registers[DSP_REG_B1] = dest[1];
6308: dsp_core.registers[DSP_REG_B0] = dest[2];
6309:
6310: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6311:
6312: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6313: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6314: }
6315:
6316: static void dsp_macr_p_x0_x0_a(void)
6317: {
6318: Uint32 source[3], dest[3];
6319: Uint16 newsr;
6320:
6321: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6322:
6323: dest[0] = dsp_core.registers[DSP_REG_A2];
6324: dest[1] = dsp_core.registers[DSP_REG_A1];
6325: dest[2] = dsp_core.registers[DSP_REG_A0];
6326: newsr = dsp_add56(source, dest);
6327:
6328: dsp_rnd56(dest);
6329:
6330: dsp_core.registers[DSP_REG_A2] = dest[0];
6331: dsp_core.registers[DSP_REG_A1] = dest[1];
6332: dsp_core.registers[DSP_REG_A0] = dest[2];
6333:
6334: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6335:
6336: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6337: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6338: }
6339:
6340: static void dsp_macr_m_x0_x0_a(void)
6341: {
6342: Uint32 source[3], dest[3];
6343: Uint16 newsr;
6344:
6345: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6346:
6347: dest[0] = dsp_core.registers[DSP_REG_A2];
6348: dest[1] = dsp_core.registers[DSP_REG_A1];
6349: dest[2] = dsp_core.registers[DSP_REG_A0];
6350: newsr = dsp_add56(source, dest);
6351:
6352: dsp_rnd56(dest);
6353:
6354: dsp_core.registers[DSP_REG_A2] = dest[0];
6355: dsp_core.registers[DSP_REG_A1] = dest[1];
6356: dsp_core.registers[DSP_REG_A0] = dest[2];
6357:
6358: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6359:
6360: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6361: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6362: }
6363: static void dsp_macr_p_x0_x0_b(void)
6364: {
6365: Uint32 source[3], dest[3];
6366: Uint16 newsr;
6367:
6368: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6369:
6370: dest[0] = dsp_core.registers[DSP_REG_B2];
6371: dest[1] = dsp_core.registers[DSP_REG_B1];
6372: dest[2] = dsp_core.registers[DSP_REG_B0];
6373: newsr = dsp_add56(source, dest);
6374:
6375: dsp_rnd56(dest);
6376:
6377: dsp_core.registers[DSP_REG_B2] = dest[0];
6378: dsp_core.registers[DSP_REG_B1] = dest[1];
6379: dsp_core.registers[DSP_REG_B0] = dest[2];
6380:
6381: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6382:
6383: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6384: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6385: }
6386:
6387: static void dsp_macr_m_x0_x0_b(void)
6388: {
6389: Uint32 source[3], dest[3];
6390: Uint16 newsr;
6391:
6392: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6393:
6394: dest[0] = dsp_core.registers[DSP_REG_B2];
6395: dest[1] = dsp_core.registers[DSP_REG_B1];
6396: dest[2] = dsp_core.registers[DSP_REG_B0];
6397: newsr = dsp_add56(source, dest);
6398:
6399: dsp_rnd56(dest);
6400:
6401: dsp_core.registers[DSP_REG_B2] = dest[0];
6402: dsp_core.registers[DSP_REG_B1] = dest[1];
6403: dsp_core.registers[DSP_REG_B0] = dest[2];
6404:
6405: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6406:
6407: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6408: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6409: }
6410:
6411: static void dsp_macr_p_y0_y0_a(void)
6412: {
6413: Uint32 source[3], dest[3];
6414: Uint16 newsr;
6415:
6416: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6417:
6418: dest[0] = dsp_core.registers[DSP_REG_A2];
6419: dest[1] = dsp_core.registers[DSP_REG_A1];
6420: dest[2] = dsp_core.registers[DSP_REG_A0];
6421: newsr = dsp_add56(source, dest);
6422:
6423: dsp_rnd56(dest);
6424:
6425: dsp_core.registers[DSP_REG_A2] = dest[0];
6426: dsp_core.registers[DSP_REG_A1] = dest[1];
6427: dsp_core.registers[DSP_REG_A0] = dest[2];
6428:
6429: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6430:
6431: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6432: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6433: }
6434:
6435: static void dsp_macr_m_y0_y0_a(void)
6436: {
6437: Uint32 source[3], dest[3];
6438: Uint16 newsr;
6439:
6440: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6441:
6442: dest[0] = dsp_core.registers[DSP_REG_A2];
6443: dest[1] = dsp_core.registers[DSP_REG_A1];
6444: dest[2] = dsp_core.registers[DSP_REG_A0];
6445: newsr = dsp_add56(source, dest);
6446:
6447: dsp_rnd56(dest);
6448:
6449: dsp_core.registers[DSP_REG_A2] = dest[0];
6450: dsp_core.registers[DSP_REG_A1] = dest[1];
6451: dsp_core.registers[DSP_REG_A0] = dest[2];
6452:
6453: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6454:
6455: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6456: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6457: }
6458: static void dsp_macr_p_y0_y0_b(void)
6459: {
6460: Uint32 source[3], dest[3];
6461: Uint16 newsr;
6462:
6463: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6464:
6465: dest[0] = dsp_core.registers[DSP_REG_B2];
6466: dest[1] = dsp_core.registers[DSP_REG_B1];
6467: dest[2] = dsp_core.registers[DSP_REG_B0];
6468: newsr = dsp_add56(source, dest);
6469:
6470: dsp_rnd56(dest);
6471:
6472: dsp_core.registers[DSP_REG_B2] = dest[0];
6473: dsp_core.registers[DSP_REG_B1] = dest[1];
6474: dsp_core.registers[DSP_REG_B0] = dest[2];
6475:
6476: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6477:
6478: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6479: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6480: }
6481:
6482: static void dsp_macr_m_y0_y0_b(void)
6483: {
6484: Uint32 source[3], dest[3];
6485: Uint16 newsr;
6486:
6487: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6488:
6489: dest[0] = dsp_core.registers[DSP_REG_B2];
6490: dest[1] = dsp_core.registers[DSP_REG_B1];
6491: dest[2] = dsp_core.registers[DSP_REG_B0];
6492: newsr = dsp_add56(source, dest);
6493:
6494: dsp_rnd56(dest);
6495:
6496: dsp_core.registers[DSP_REG_B2] = dest[0];
6497: dsp_core.registers[DSP_REG_B1] = dest[1];
6498: dsp_core.registers[DSP_REG_B0] = dest[2];
6499:
6500: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6501:
6502: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6503: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6504: }
6505:
6506: static void dsp_macr_p_x1_x0_a(void)
6507: {
6508: Uint32 source[3], dest[3];
6509: Uint16 newsr;
6510:
6511: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6512:
6513: dest[0] = dsp_core.registers[DSP_REG_A2];
6514: dest[1] = dsp_core.registers[DSP_REG_A1];
6515: dest[2] = dsp_core.registers[DSP_REG_A0];
6516: newsr = dsp_add56(source, dest);
6517:
6518: dsp_rnd56(dest);
6519:
6520: dsp_core.registers[DSP_REG_A2] = dest[0];
6521: dsp_core.registers[DSP_REG_A1] = dest[1];
6522: dsp_core.registers[DSP_REG_A0] = dest[2];
6523:
6524: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6525:
6526: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6527: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6528: }
6529:
6530: static void dsp_macr_m_x1_x0_a(void)
6531: {
6532: Uint32 source[3], dest[3];
6533: Uint16 newsr;
6534:
6535: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6536:
6537: dest[0] = dsp_core.registers[DSP_REG_A2];
6538: dest[1] = dsp_core.registers[DSP_REG_A1];
6539: dest[2] = dsp_core.registers[DSP_REG_A0];
6540: newsr = dsp_add56(source, dest);
6541:
6542: dsp_rnd56(dest);
6543:
6544: dsp_core.registers[DSP_REG_A2] = dest[0];
6545: dsp_core.registers[DSP_REG_A1] = dest[1];
6546: dsp_core.registers[DSP_REG_A0] = dest[2];
6547:
6548: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6549:
6550: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6551: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6552: }
6553:
6554: static void dsp_macr_p_x1_x0_b(void)
6555: {
6556: Uint32 source[3], dest[3];
6557: Uint16 newsr;
6558:
6559: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6560:
6561: dest[0] = dsp_core.registers[DSP_REG_B2];
6562: dest[1] = dsp_core.registers[DSP_REG_B1];
6563: dest[2] = dsp_core.registers[DSP_REG_B0];
6564: newsr = dsp_add56(source, dest);
6565:
6566: dsp_rnd56(dest);
6567:
6568: dsp_core.registers[DSP_REG_B2] = dest[0];
6569: dsp_core.registers[DSP_REG_B1] = dest[1];
6570: dsp_core.registers[DSP_REG_B0] = dest[2];
6571:
6572: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6573:
6574: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6575: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6576: }
6577:
6578: static void dsp_macr_m_x1_x0_b(void)
6579: {
6580: Uint32 source[3], dest[3];
6581: Uint16 newsr;
6582:
6583: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6584:
6585: dest[0] = dsp_core.registers[DSP_REG_B2];
6586: dest[1] = dsp_core.registers[DSP_REG_B1];
6587: dest[2] = dsp_core.registers[DSP_REG_B0];
6588: newsr = dsp_add56(source, dest);
6589:
6590: dsp_rnd56(dest);
6591:
6592: dsp_core.registers[DSP_REG_B2] = dest[0];
6593: dsp_core.registers[DSP_REG_B1] = dest[1];
6594: dsp_core.registers[DSP_REG_B0] = dest[2];
6595:
6596: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6597:
6598: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6599: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6600: }
6601:
6602: static void dsp_macr_p_y1_y0_a(void)
6603: {
6604: Uint32 source[3], dest[3];
6605: Uint16 newsr;
6606:
6607: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6608:
6609: dest[0] = dsp_core.registers[DSP_REG_A2];
6610: dest[1] = dsp_core.registers[DSP_REG_A1];
6611: dest[2] = dsp_core.registers[DSP_REG_A0];
6612: newsr = dsp_add56(source, dest);
6613:
6614: dsp_rnd56(dest);
6615:
6616: dsp_core.registers[DSP_REG_A2] = dest[0];
6617: dsp_core.registers[DSP_REG_A1] = dest[1];
6618: dsp_core.registers[DSP_REG_A0] = dest[2];
6619:
6620: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6621:
6622: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6623: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6624: }
6625:
6626: static void dsp_macr_m_y1_y0_a(void)
6627: {
6628: Uint32 source[3], dest[3];
6629: Uint16 newsr;
6630:
6631: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6632:
6633: dest[0] = dsp_core.registers[DSP_REG_A2];
6634: dest[1] = dsp_core.registers[DSP_REG_A1];
6635: dest[2] = dsp_core.registers[DSP_REG_A0];
6636: newsr = dsp_add56(source, dest);
6637:
6638: dsp_rnd56(dest);
6639:
6640: dsp_core.registers[DSP_REG_A2] = dest[0];
6641: dsp_core.registers[DSP_REG_A1] = dest[1];
6642: dsp_core.registers[DSP_REG_A0] = dest[2];
6643:
6644: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6645:
6646: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6647: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6648: }
6649:
6650: static void dsp_macr_p_y1_y0_b(void)
6651: {
6652: Uint32 source[3], dest[3];
6653: Uint16 newsr;
6654:
6655: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6656:
6657: dest[0] = dsp_core.registers[DSP_REG_B2];
6658: dest[1] = dsp_core.registers[DSP_REG_B1];
6659: dest[2] = dsp_core.registers[DSP_REG_B0];
6660: newsr = dsp_add56(source, dest);
6661:
6662: dsp_rnd56(dest);
6663:
6664: dsp_core.registers[DSP_REG_B2] = dest[0];
6665: dsp_core.registers[DSP_REG_B1] = dest[1];
6666: dsp_core.registers[DSP_REG_B0] = dest[2];
6667:
6668: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6669:
6670: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6671: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6672: }
6673:
6674: static void dsp_macr_m_y1_y0_b(void)
6675: {
6676: Uint32 source[3], dest[3];
6677: Uint16 newsr;
6678:
6679: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6680:
6681: dest[0] = dsp_core.registers[DSP_REG_B2];
6682: dest[1] = dsp_core.registers[DSP_REG_B1];
6683: dest[2] = dsp_core.registers[DSP_REG_B0];
6684: newsr = dsp_add56(source, dest);
6685:
6686: dsp_rnd56(dest);
6687:
6688: dsp_core.registers[DSP_REG_B2] = dest[0];
6689: dsp_core.registers[DSP_REG_B1] = dest[1];
6690: dsp_core.registers[DSP_REG_B0] = dest[2];
6691:
6692: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6693:
6694: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6695: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6696: }
6697:
6698: static void dsp_macr_p_x0_y1_a(void)
6699: {
6700: Uint32 source[3], dest[3];
6701: Uint16 newsr;
6702:
6703: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6704:
6705: dest[0] = dsp_core.registers[DSP_REG_A2];
6706: dest[1] = dsp_core.registers[DSP_REG_A1];
6707: dest[2] = dsp_core.registers[DSP_REG_A0];
6708: newsr = dsp_add56(source, dest);
6709:
6710: dsp_rnd56(dest);
6711:
6712: dsp_core.registers[DSP_REG_A2] = dest[0];
6713: dsp_core.registers[DSP_REG_A1] = dest[1];
6714: dsp_core.registers[DSP_REG_A0] = dest[2];
6715:
6716: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6717:
6718: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6719: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6720: }
6721:
6722: static void dsp_macr_m_x0_y1_a(void)
6723: {
6724: Uint32 source[3], dest[3];
6725: Uint16 newsr;
6726:
6727: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6728:
6729: dest[0] = dsp_core.registers[DSP_REG_A2];
6730: dest[1] = dsp_core.registers[DSP_REG_A1];
6731: dest[2] = dsp_core.registers[DSP_REG_A0];
6732: newsr = dsp_add56(source, dest);
6733:
6734: dsp_rnd56(dest);
6735:
6736: dsp_core.registers[DSP_REG_A2] = dest[0];
6737: dsp_core.registers[DSP_REG_A1] = dest[1];
6738: dsp_core.registers[DSP_REG_A0] = dest[2];
6739:
6740: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6741:
6742: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6743: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6744: }
6745:
6746: static void dsp_macr_p_x0_y1_b(void)
6747: {
6748: Uint32 source[3], dest[3];
6749: Uint16 newsr;
6750:
6751: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6752:
6753: dest[0] = dsp_core.registers[DSP_REG_B2];
6754: dest[1] = dsp_core.registers[DSP_REG_B1];
6755: dest[2] = dsp_core.registers[DSP_REG_B0];
6756: newsr = dsp_add56(source, dest);
6757:
6758: dsp_rnd56(dest);
6759:
6760: dsp_core.registers[DSP_REG_B2] = dest[0];
6761: dsp_core.registers[DSP_REG_B1] = dest[1];
6762: dsp_core.registers[DSP_REG_B0] = dest[2];
6763:
6764: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6765:
6766: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6767: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6768: }
6769:
6770: static void dsp_macr_m_x0_y1_b(void)
6771: {
6772: Uint32 source[3], dest[3];
6773: Uint16 newsr;
6774:
6775: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6776:
6777: dest[0] = dsp_core.registers[DSP_REG_B2];
6778: dest[1] = dsp_core.registers[DSP_REG_B1];
6779: dest[2] = dsp_core.registers[DSP_REG_B0];
6780: newsr = dsp_add56(source, dest);
6781:
6782: dsp_rnd56(dest);
6783:
6784: dsp_core.registers[DSP_REG_B2] = dest[0];
6785: dsp_core.registers[DSP_REG_B1] = dest[1];
6786: dsp_core.registers[DSP_REG_B0] = dest[2];
6787:
6788: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6789:
6790: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6791: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6792: }
6793:
6794: static void dsp_macr_p_y0_x0_a(void)
6795: {
6796: Uint32 source[3], dest[3];
6797: Uint16 newsr;
6798:
6799: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6800:
6801: dest[0] = dsp_core.registers[DSP_REG_A2];
6802: dest[1] = dsp_core.registers[DSP_REG_A1];
6803: dest[2] = dsp_core.registers[DSP_REG_A0];
6804: newsr = dsp_add56(source, dest);
6805:
6806: dsp_rnd56(dest);
6807:
6808: dsp_core.registers[DSP_REG_A2] = dest[0];
6809: dsp_core.registers[DSP_REG_A1] = dest[1];
6810: dsp_core.registers[DSP_REG_A0] = dest[2];
6811:
6812: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6813:
6814: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6815: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6816: }
6817:
6818: static void dsp_macr_m_y0_x0_a(void)
6819: {
6820: Uint32 source[3], dest[3];
6821: Uint16 newsr;
6822:
6823: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6824:
6825: dest[0] = dsp_core.registers[DSP_REG_A2];
6826: dest[1] = dsp_core.registers[DSP_REG_A1];
6827: dest[2] = dsp_core.registers[DSP_REG_A0];
6828: newsr = dsp_add56(source, dest);
6829:
6830: dsp_rnd56(dest);
6831:
6832: dsp_core.registers[DSP_REG_A2] = dest[0];
6833: dsp_core.registers[DSP_REG_A1] = dest[1];
6834: dsp_core.registers[DSP_REG_A0] = dest[2];
6835:
6836: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6837:
6838: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6839: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6840: }
6841:
6842: static void dsp_macr_p_y0_x0_b(void)
6843: {
6844: Uint32 source[3], dest[3];
6845: Uint16 newsr;
6846:
6847: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6848:
6849: dest[0] = dsp_core.registers[DSP_REG_B2];
6850: dest[1] = dsp_core.registers[DSP_REG_B1];
6851: dest[2] = dsp_core.registers[DSP_REG_B0];
6852: newsr = dsp_add56(source, dest);
6853:
6854: dsp_rnd56(dest);
6855:
6856: dsp_core.registers[DSP_REG_B2] = dest[0];
6857: dsp_core.registers[DSP_REG_B1] = dest[1];
6858: dsp_core.registers[DSP_REG_B0] = dest[2];
6859:
6860: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6861:
6862: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6863: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6864: }
6865:
6866: static void dsp_macr_m_y0_x0_b(void)
6867: {
6868: Uint32 source[3], dest[3];
6869: Uint16 newsr;
6870:
6871: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6872:
6873: dest[0] = dsp_core.registers[DSP_REG_B2];
6874: dest[1] = dsp_core.registers[DSP_REG_B1];
6875: dest[2] = dsp_core.registers[DSP_REG_B0];
6876: newsr = dsp_add56(source, dest);
6877:
6878: dsp_rnd56(dest);
6879:
6880: dsp_core.registers[DSP_REG_B2] = dest[0];
6881: dsp_core.registers[DSP_REG_B1] = dest[1];
6882: dsp_core.registers[DSP_REG_B0] = dest[2];
6883:
6884: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6885:
6886: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6887: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6888: }
6889:
6890: static void dsp_macr_p_x1_y0_a(void)
6891: {
6892: Uint32 source[3], dest[3];
6893: Uint16 newsr;
6894:
6895: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6896:
6897: dest[0] = dsp_core.registers[DSP_REG_A2];
6898: dest[1] = dsp_core.registers[DSP_REG_A1];
6899: dest[2] = dsp_core.registers[DSP_REG_A0];
6900: newsr = dsp_add56(source, dest);
6901:
6902: dsp_rnd56(dest);
6903:
6904: dsp_core.registers[DSP_REG_A2] = dest[0];
6905: dsp_core.registers[DSP_REG_A1] = dest[1];
6906: dsp_core.registers[DSP_REG_A0] = dest[2];
6907:
6908: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6909:
6910: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6911: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6912: }
6913:
6914: static void dsp_macr_m_x1_y0_a(void)
6915: {
6916: Uint32 source[3], dest[3];
6917: Uint16 newsr;
6918:
6919: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6920:
6921: dest[0] = dsp_core.registers[DSP_REG_A2];
6922: dest[1] = dsp_core.registers[DSP_REG_A1];
6923: dest[2] = dsp_core.registers[DSP_REG_A0];
6924: newsr = dsp_add56(source, dest);
6925:
6926: dsp_rnd56(dest);
6927:
6928: dsp_core.registers[DSP_REG_A2] = dest[0];
6929: dsp_core.registers[DSP_REG_A1] = dest[1];
6930: dsp_core.registers[DSP_REG_A0] = dest[2];
6931:
6932: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6933:
6934: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6935: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6936: }
6937:
6938: static void dsp_macr_p_x1_y0_b(void)
6939: {
6940: Uint32 source[3], dest[3];
6941: Uint16 newsr;
6942:
6943: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6944:
6945: dest[0] = dsp_core.registers[DSP_REG_B2];
6946: dest[1] = dsp_core.registers[DSP_REG_B1];
6947: dest[2] = dsp_core.registers[DSP_REG_B0];
6948: newsr = dsp_add56(source, dest);
6949:
1.1.1.10 root 6950: dsp_rnd56(dest);
6951:
1.1.1.6 root 6952: dsp_core.registers[DSP_REG_B2] = dest[0];
6953: dsp_core.registers[DSP_REG_B1] = dest[1];
6954: dsp_core.registers[DSP_REG_B0] = dest[2];
6955:
6956: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6957:
6958: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6959: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6960: }
6961:
6962: static void dsp_macr_m_x1_y0_b(void)
6963: {
6964: Uint32 source[3], dest[3];
6965: Uint16 newsr;
6966:
6967: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6968:
6969: dest[0] = dsp_core.registers[DSP_REG_B2];
6970: dest[1] = dsp_core.registers[DSP_REG_B1];
6971: dest[2] = dsp_core.registers[DSP_REG_B0];
6972: newsr = dsp_add56(source, dest);
6973:
6974: dsp_rnd56(dest);
6975:
6976: dsp_core.registers[DSP_REG_B2] = dest[0];
6977: dsp_core.registers[DSP_REG_B1] = dest[1];
6978: dsp_core.registers[DSP_REG_B0] = dest[2];
6979:
6980: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6981:
6982: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6983: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6984: }
6985:
6986: static void dsp_macr_p_y1_x1_a(void)
6987: {
6988: Uint32 source[3], dest[3];
6989: Uint16 newsr;
6990:
6991: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6992:
6993: dest[0] = dsp_core.registers[DSP_REG_A2];
6994: dest[1] = dsp_core.registers[DSP_REG_A1];
6995: dest[2] = dsp_core.registers[DSP_REG_A0];
6996: newsr = dsp_add56(source, dest);
6997:
6998: dsp_rnd56(dest);
6999:
7000: dsp_core.registers[DSP_REG_A2] = dest[0];
7001: dsp_core.registers[DSP_REG_A1] = dest[1];
7002: dsp_core.registers[DSP_REG_A0] = dest[2];
7003:
7004: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7005:
7006: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7007: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7008: }
7009:
7010: static void dsp_macr_m_y1_x1_a(void)
7011: {
7012: Uint32 source[3], dest[3];
7013: Uint16 newsr;
7014:
7015: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7016:
7017: dest[0] = dsp_core.registers[DSP_REG_A2];
7018: dest[1] = dsp_core.registers[DSP_REG_A1];
7019: dest[2] = dsp_core.registers[DSP_REG_A0];
7020: newsr = dsp_add56(source, dest);
7021:
7022: dsp_rnd56(dest);
7023:
7024: dsp_core.registers[DSP_REG_A2] = dest[0];
7025: dsp_core.registers[DSP_REG_A1] = dest[1];
7026: dsp_core.registers[DSP_REG_A0] = dest[2];
7027:
7028: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7029:
7030: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7031: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7032: }
7033:
7034: static void dsp_macr_p_y1_x1_b(void)
7035: {
7036: Uint32 source[3], dest[3];
7037: Uint16 newsr;
7038:
7039: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7040:
7041: dest[0] = dsp_core.registers[DSP_REG_B2];
7042: dest[1] = dsp_core.registers[DSP_REG_B1];
7043: dest[2] = dsp_core.registers[DSP_REG_B0];
7044: newsr = dsp_add56(source, dest);
7045:
7046: dsp_rnd56(dest);
7047:
7048: dsp_core.registers[DSP_REG_B2] = dest[0];
7049: dsp_core.registers[DSP_REG_B1] = dest[1];
7050: dsp_core.registers[DSP_REG_B0] = dest[2];
7051:
7052: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7053:
7054: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7055: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7056: }
7057:
7058: static void dsp_macr_m_y1_x1_b(void)
7059: {
7060: Uint32 source[3], dest[3];
7061: Uint16 newsr;
7062:
7063: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7064:
7065: dest[0] = dsp_core.registers[DSP_REG_B2];
7066: dest[1] = dsp_core.registers[DSP_REG_B1];
7067: dest[2] = dsp_core.registers[DSP_REG_B0];
7068: newsr = dsp_add56(source, dest);
7069:
7070: dsp_rnd56(dest);
7071:
7072: dsp_core.registers[DSP_REG_B2] = dest[0];
7073: dsp_core.registers[DSP_REG_B1] = dest[1];
7074: dsp_core.registers[DSP_REG_B0] = dest[2];
7075:
7076: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7077:
7078: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7079: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7080: }
7081:
7082:
7083: static void dsp_move(void)
7084: {
7085: /* move instruction inside alu opcodes
7086: taken care of by parallel move dispatcher */
7087: }
7088:
7089: static void dsp_mpy_p_x0_x0_a(void)
7090: {
7091: Uint32 source[3];
7092:
7093: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7094:
7095: dsp_core.registers[DSP_REG_A2] = source[0];
7096: dsp_core.registers[DSP_REG_A1] = source[1];
7097: dsp_core.registers[DSP_REG_A0] = source[2];
7098:
7099: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7100: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7101: }
7102:
7103: static void dsp_mpy_m_x0_x0_a(void)
7104: {
7105: Uint32 source[3];
7106:
7107: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7108:
7109: dsp_core.registers[DSP_REG_A2] = source[0];
7110: dsp_core.registers[DSP_REG_A1] = source[1];
7111: dsp_core.registers[DSP_REG_A0] = source[2];
7112:
7113: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7114: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7115: }
7116:
7117: static void dsp_mpy_p_x0_x0_b(void)
7118: {
7119: Uint32 source[3];
7120:
7121: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7122:
7123: dsp_core.registers[DSP_REG_B2] = source[0];
7124: dsp_core.registers[DSP_REG_B1] = source[1];
7125: dsp_core.registers[DSP_REG_B0] = source[2];
7126:
7127: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7128: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7129: }
7130:
7131: static void dsp_mpy_m_x0_x0_b(void)
7132: {
7133: Uint32 source[3];
7134:
7135:
7136: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7137:
7138: dsp_core.registers[DSP_REG_B2] = source[0];
7139: dsp_core.registers[DSP_REG_B1] = source[1];
7140: dsp_core.registers[DSP_REG_B0] = source[2];
7141:
7142: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7143: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7144: }
7145:
7146: static void dsp_mpy_p_y0_y0_a(void)
7147: {
7148: Uint32 source[3];
7149:
7150: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7151:
7152: dsp_core.registers[DSP_REG_A2] = source[0];
7153: dsp_core.registers[DSP_REG_A1] = source[1];
7154: dsp_core.registers[DSP_REG_A0] = source[2];
7155:
7156: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7157: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7158: }
7159:
7160: static void dsp_mpy_m_y0_y0_a(void)
7161: {
7162: Uint32 source[3];
7163:
7164: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7165:
7166: dsp_core.registers[DSP_REG_A2] = source[0];
7167: dsp_core.registers[DSP_REG_A1] = source[1];
7168: dsp_core.registers[DSP_REG_A0] = source[2];
7169:
7170: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7171: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7172: }
7173:
7174: static void dsp_mpy_p_y0_y0_b(void)
7175: {
7176: Uint32 source[3];
7177:
7178: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7179:
7180: dsp_core.registers[DSP_REG_B2] = source[0];
7181: dsp_core.registers[DSP_REG_B1] = source[1];
7182: dsp_core.registers[DSP_REG_B0] = source[2];
7183:
7184: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7185: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7186: }
7187:
7188: static void dsp_mpy_m_y0_y0_b(void)
7189: {
7190: Uint32 source[3];
7191:
7192: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7193:
7194: dsp_core.registers[DSP_REG_B2] = source[0];
7195: dsp_core.registers[DSP_REG_B1] = source[1];
7196: dsp_core.registers[DSP_REG_B0] = source[2];
7197:
7198: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7199: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7200: }
7201:
7202: static void dsp_mpy_p_x1_x0_a(void)
7203: {
7204: Uint32 source[3];
7205:
7206: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7207:
7208: dsp_core.registers[DSP_REG_A2] = source[0];
7209: dsp_core.registers[DSP_REG_A1] = source[1];
7210: dsp_core.registers[DSP_REG_A0] = source[2];
7211:
7212: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7213: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7214: }
7215:
7216: static void dsp_mpy_m_x1_x0_a(void)
7217: {
7218: Uint32 source[3];
7219:
7220: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7221:
7222: dsp_core.registers[DSP_REG_A2] = source[0];
7223: dsp_core.registers[DSP_REG_A1] = source[1];
7224: dsp_core.registers[DSP_REG_A0] = source[2];
7225:
7226: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7227: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7228: }
7229:
7230: static void dsp_mpy_p_x1_x0_b(void)
7231: {
7232: Uint32 source[3];
7233:
7234: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7235:
7236: dsp_core.registers[DSP_REG_B2] = source[0];
7237: dsp_core.registers[DSP_REG_B1] = source[1];
7238: dsp_core.registers[DSP_REG_B0] = source[2];
7239:
7240: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7241: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7242: }
7243:
7244: static void dsp_mpy_m_x1_x0_b(void)
7245: {
7246: Uint32 source[3];
7247:
7248: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7249:
7250: dsp_core.registers[DSP_REG_B2] = source[0];
7251: dsp_core.registers[DSP_REG_B1] = source[1];
7252: dsp_core.registers[DSP_REG_B0] = source[2];
7253:
7254: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7255: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7256: }
7257:
7258: static void dsp_mpy_p_y1_y0_a(void)
7259: {
7260: Uint32 source[3];
7261:
7262: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7263:
7264: dsp_core.registers[DSP_REG_A2] = source[0];
7265: dsp_core.registers[DSP_REG_A1] = source[1];
7266: dsp_core.registers[DSP_REG_A0] = source[2];
7267:
7268: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7269: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7270: }
7271:
7272: static void dsp_mpy_m_y1_y0_a(void)
7273: {
7274: Uint32 source[3];
7275:
7276: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7277:
7278: dsp_core.registers[DSP_REG_A2] = source[0];
7279: dsp_core.registers[DSP_REG_A1] = source[1];
7280: dsp_core.registers[DSP_REG_A0] = source[2];
7281:
7282: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7283: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7284: }
7285:
7286: static void dsp_mpy_p_y1_y0_b(void)
7287: {
7288: Uint32 source[3];
7289:
7290: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7291:
7292: dsp_core.registers[DSP_REG_B2] = source[0];
7293: dsp_core.registers[DSP_REG_B1] = source[1];
7294: dsp_core.registers[DSP_REG_B0] = source[2];
7295:
7296: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7297: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7298: }
7299:
7300: static void dsp_mpy_m_y1_y0_b(void)
7301: {
7302: Uint32 source[3];
7303:
7304: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7305:
7306: dsp_core.registers[DSP_REG_B2] = source[0];
7307: dsp_core.registers[DSP_REG_B1] = source[1];
7308: dsp_core.registers[DSP_REG_B0] = source[2];
7309:
7310: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7311: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7312: }
7313:
7314: static void dsp_mpy_p_x0_y1_a(void)
7315: {
7316: Uint32 source[3];
7317:
7318: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7319:
7320: dsp_core.registers[DSP_REG_A2] = source[0];
7321: dsp_core.registers[DSP_REG_A1] = source[1];
7322: dsp_core.registers[DSP_REG_A0] = source[2];
7323:
7324: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7325: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7326: }
7327:
7328: static void dsp_mpy_m_x0_y1_a(void)
7329: {
7330: Uint32 source[3];
7331:
7332: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7333:
7334: dsp_core.registers[DSP_REG_A2] = source[0];
7335: dsp_core.registers[DSP_REG_A1] = source[1];
7336: dsp_core.registers[DSP_REG_A0] = source[2];
7337:
7338: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7339: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7340: }
7341:
7342: static void dsp_mpy_p_x0_y1_b(void)
7343: {
7344: Uint32 source[3];
7345:
7346: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7347:
7348: dsp_core.registers[DSP_REG_B2] = source[0];
7349: dsp_core.registers[DSP_REG_B1] = source[1];
7350: dsp_core.registers[DSP_REG_B0] = source[2];
7351:
7352: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7353: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7354: }
7355:
7356: static void dsp_mpy_m_x0_y1_b(void)
7357: {
7358: Uint32 source[3];
7359:
7360: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7361:
7362: dsp_core.registers[DSP_REG_B2] = source[0];
7363: dsp_core.registers[DSP_REG_B1] = source[1];
7364: dsp_core.registers[DSP_REG_B0] = source[2];
7365:
7366: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7367: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7368: }
7369:
7370: static void dsp_mpy_p_y0_x0_a(void)
7371: {
7372: Uint32 source[3];
7373:
7374: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7375:
7376: dsp_core.registers[DSP_REG_A2] = source[0];
7377: dsp_core.registers[DSP_REG_A1] = source[1];
7378: dsp_core.registers[DSP_REG_A0] = source[2];
7379:
7380: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7381: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7382: }
7383:
7384: static void dsp_mpy_m_y0_x0_a(void)
7385: {
7386: Uint32 source[3];
7387:
7388: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7389:
7390: dsp_core.registers[DSP_REG_A2] = source[0];
7391: dsp_core.registers[DSP_REG_A1] = source[1];
7392: dsp_core.registers[DSP_REG_A0] = source[2];
7393:
7394: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7395: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7396: }
7397:
7398: static void dsp_mpy_p_y0_x0_b(void)
7399: {
7400: Uint32 source[3];
7401:
7402: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7403:
7404: dsp_core.registers[DSP_REG_B2] = source[0];
7405: dsp_core.registers[DSP_REG_B1] = source[1];
7406: dsp_core.registers[DSP_REG_B0] = source[2];
7407:
7408: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7409: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7410: }
7411:
7412: static void dsp_mpy_m_y0_x0_b(void)
7413: {
7414: Uint32 source[3];
7415:
7416: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7417:
7418: dsp_core.registers[DSP_REG_B2] = source[0];
7419: dsp_core.registers[DSP_REG_B1] = source[1];
7420: dsp_core.registers[DSP_REG_B0] = source[2];
7421:
7422: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7423: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7424: }
7425:
7426: static void dsp_mpy_p_x1_y0_a(void)
7427: {
7428: Uint32 source[3];
7429:
7430: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7431:
7432: dsp_core.registers[DSP_REG_A2] = source[0];
7433: dsp_core.registers[DSP_REG_A1] = source[1];
7434: dsp_core.registers[DSP_REG_A0] = source[2];
7435:
7436: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7437: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7438: }
7439:
7440: static void dsp_mpy_m_x1_y0_a(void)
7441: {
7442: Uint32 source[3];
7443:
7444: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7445:
7446: dsp_core.registers[DSP_REG_A2] = source[0];
7447: dsp_core.registers[DSP_REG_A1] = source[1];
7448: dsp_core.registers[DSP_REG_A0] = source[2];
7449:
7450: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7451: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7452: }
7453:
7454: static void dsp_mpy_p_x1_y0_b(void)
7455: {
7456: Uint32 source[3];
7457:
7458: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7459:
7460: dsp_core.registers[DSP_REG_B2] = source[0];
7461: dsp_core.registers[DSP_REG_B1] = source[1];
7462: dsp_core.registers[DSP_REG_B0] = source[2];
7463:
7464: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7465: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7466: }
7467:
7468: static void dsp_mpy_m_x1_y0_b(void)
7469: {
7470: Uint32 source[3];
7471:
7472: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7473:
7474: dsp_core.registers[DSP_REG_B2] = source[0];
7475: dsp_core.registers[DSP_REG_B1] = source[1];
7476: dsp_core.registers[DSP_REG_B0] = source[2];
7477:
7478: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7479: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7480: }
7481:
7482: static void dsp_mpy_p_y1_x1_a(void)
7483: {
7484: Uint32 source[3];
7485:
7486: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7487:
7488: dsp_core.registers[DSP_REG_A2] = source[0];
7489: dsp_core.registers[DSP_REG_A1] = source[1];
7490: dsp_core.registers[DSP_REG_A0] = source[2];
7491:
7492: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7493: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7494: }
7495:
7496: static void dsp_mpy_m_y1_x1_a(void)
7497: {
7498: Uint32 source[3];
7499:
7500: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7501:
7502: dsp_core.registers[DSP_REG_A2] = source[0];
7503: dsp_core.registers[DSP_REG_A1] = source[1];
7504: dsp_core.registers[DSP_REG_A0] = source[2];
7505:
7506: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7507: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7508: }
7509:
7510: static void dsp_mpy_p_y1_x1_b(void)
7511: {
7512: Uint32 source[3];
7513:
7514: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7515:
7516: dsp_core.registers[DSP_REG_B2] = source[0];
7517: dsp_core.registers[DSP_REG_B1] = source[1];
7518: dsp_core.registers[DSP_REG_B0] = source[2];
7519:
7520: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7521: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7522: }
7523:
7524: static void dsp_mpy_m_y1_x1_b(void)
7525: {
7526: Uint32 source[3];
7527:
7528: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7529:
7530: dsp_core.registers[DSP_REG_B2] = source[0];
7531: dsp_core.registers[DSP_REG_B1] = source[1];
7532: dsp_core.registers[DSP_REG_B0] = source[2];
7533:
7534: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7535: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7536: }
7537:
7538: static void dsp_mpyr_p_x0_x0_a(void)
7539: {
7540: Uint32 source[3];
7541:
7542: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7543: dsp_rnd56(source);
7544:
7545: dsp_core.registers[DSP_REG_A2] = source[0];
7546: dsp_core.registers[DSP_REG_A1] = source[1];
7547: dsp_core.registers[DSP_REG_A0] = source[2];
7548:
7549: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7550: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7551: }
7552:
7553: static void dsp_mpyr_m_x0_x0_a(void)
7554: {
7555: Uint32 source[3];
7556:
7557: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7558: dsp_rnd56(source);
7559:
7560: dsp_core.registers[DSP_REG_A2] = source[0];
7561: dsp_core.registers[DSP_REG_A1] = source[1];
7562: dsp_core.registers[DSP_REG_A0] = source[2];
7563:
7564: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7565: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7566: }
7567:
7568: static void dsp_mpyr_p_x0_x0_b(void)
7569: {
7570: Uint32 source[3];
7571:
7572: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7573: dsp_rnd56(source);
7574:
7575: dsp_core.registers[DSP_REG_B2] = source[0];
7576: dsp_core.registers[DSP_REG_B1] = source[1];
7577: dsp_core.registers[DSP_REG_B0] = source[2];
7578:
7579: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7580: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7581: }
7582:
7583: static void dsp_mpyr_m_x0_x0_b(void)
7584: {
7585: Uint32 source[3];
7586:
7587:
7588: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7589: dsp_rnd56(source);
7590:
7591: dsp_core.registers[DSP_REG_B2] = source[0];
7592: dsp_core.registers[DSP_REG_B1] = source[1];
7593: dsp_core.registers[DSP_REG_B0] = source[2];
7594:
7595: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7596: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7597: }
7598:
7599: static void dsp_mpyr_p_y0_y0_a(void)
7600: {
7601: Uint32 source[3];
7602:
7603: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7604: dsp_rnd56(source);
7605:
7606: dsp_core.registers[DSP_REG_A2] = source[0];
7607: dsp_core.registers[DSP_REG_A1] = source[1];
7608: dsp_core.registers[DSP_REG_A0] = source[2];
7609:
7610: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7611: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7612: }
7613:
7614: static void dsp_mpyr_m_y0_y0_a(void)
7615: {
7616: Uint32 source[3];
7617:
7618: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7619: dsp_rnd56(source);
7620:
7621: dsp_core.registers[DSP_REG_A2] = source[0];
7622: dsp_core.registers[DSP_REG_A1] = source[1];
7623: dsp_core.registers[DSP_REG_A0] = source[2];
7624:
7625: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7626: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7627: }
7628:
7629: static void dsp_mpyr_p_y0_y0_b(void)
7630: {
7631: Uint32 source[3];
7632:
7633: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7634: dsp_rnd56(source);
7635:
7636: dsp_core.registers[DSP_REG_B2] = source[0];
7637: dsp_core.registers[DSP_REG_B1] = source[1];
7638: dsp_core.registers[DSP_REG_B0] = source[2];
7639:
7640: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7641: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7642: }
7643:
7644: static void dsp_mpyr_m_y0_y0_b(void)
7645: {
7646: Uint32 source[3];
7647:
7648: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7649: dsp_rnd56(source);
7650:
7651: dsp_core.registers[DSP_REG_B2] = source[0];
7652: dsp_core.registers[DSP_REG_B1] = source[1];
7653: dsp_core.registers[DSP_REG_B0] = source[2];
7654:
7655: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7656: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7657: }
7658:
7659: static void dsp_mpyr_p_x1_x0_a(void)
7660: {
7661: Uint32 source[3];
7662:
7663: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7664: dsp_rnd56(source);
7665:
7666: dsp_core.registers[DSP_REG_A2] = source[0];
7667: dsp_core.registers[DSP_REG_A1] = source[1];
7668: dsp_core.registers[DSP_REG_A0] = source[2];
7669:
7670: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7671: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7672: }
7673:
7674: static void dsp_mpyr_m_x1_x0_a(void)
7675: {
7676: Uint32 source[3];
7677:
7678: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7679: dsp_rnd56(source);
7680:
7681: dsp_core.registers[DSP_REG_A2] = source[0];
7682: dsp_core.registers[DSP_REG_A1] = source[1];
7683: dsp_core.registers[DSP_REG_A0] = source[2];
7684:
7685: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7686: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7687: }
7688:
7689: static void dsp_mpyr_p_x1_x0_b(void)
7690: {
7691: Uint32 source[3];
7692:
7693: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7694: dsp_rnd56(source);
7695:
7696: dsp_core.registers[DSP_REG_B2] = source[0];
7697: dsp_core.registers[DSP_REG_B1] = source[1];
7698: dsp_core.registers[DSP_REG_B0] = source[2];
7699:
7700: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7701: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7702: }
7703:
7704: static void dsp_mpyr_m_x1_x0_b(void)
7705: {
7706: Uint32 source[3];
7707:
7708: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7709: dsp_rnd56(source);
7710:
7711: dsp_core.registers[DSP_REG_B2] = source[0];
7712: dsp_core.registers[DSP_REG_B1] = source[1];
7713: dsp_core.registers[DSP_REG_B0] = source[2];
7714:
7715: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7716: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7717: }
7718:
7719: static void dsp_mpyr_p_y1_y0_a(void)
7720: {
7721: Uint32 source[3];
7722:
7723: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7724: dsp_rnd56(source);
7725:
7726: dsp_core.registers[DSP_REG_A2] = source[0];
7727: dsp_core.registers[DSP_REG_A1] = source[1];
7728: dsp_core.registers[DSP_REG_A0] = source[2];
7729:
7730: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7731: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7732: }
7733:
7734: static void dsp_mpyr_m_y1_y0_a(void)
7735: {
7736: Uint32 source[3];
7737:
7738: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7739: dsp_rnd56(source);
7740:
7741: dsp_core.registers[DSP_REG_A2] = source[0];
7742: dsp_core.registers[DSP_REG_A1] = source[1];
7743: dsp_core.registers[DSP_REG_A0] = source[2];
7744:
7745: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7746: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7747: }
7748:
7749: static void dsp_mpyr_p_y1_y0_b(void)
7750: {
7751: Uint32 source[3];
7752:
7753: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7754: dsp_rnd56(source);
7755:
7756: dsp_core.registers[DSP_REG_B2] = source[0];
7757: dsp_core.registers[DSP_REG_B1] = source[1];
7758: dsp_core.registers[DSP_REG_B0] = source[2];
7759:
7760: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7761: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7762: }
7763:
7764: static void dsp_mpyr_m_y1_y0_b(void)
7765: {
7766: Uint32 source[3];
7767:
7768: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7769: dsp_rnd56(source);
7770:
7771: dsp_core.registers[DSP_REG_B2] = source[0];
7772: dsp_core.registers[DSP_REG_B1] = source[1];
7773: dsp_core.registers[DSP_REG_B0] = source[2];
7774:
7775: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7776: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7777: }
7778:
7779: static void dsp_mpyr_p_x0_y1_a(void)
7780: {
7781: Uint32 source[3];
7782:
7783: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7784: dsp_rnd56(source);
7785:
7786: dsp_core.registers[DSP_REG_A2] = source[0];
7787: dsp_core.registers[DSP_REG_A1] = source[1];
7788: dsp_core.registers[DSP_REG_A0] = source[2];
7789:
7790: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7791: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7792: }
7793:
7794: static void dsp_mpyr_m_x0_y1_a(void)
7795: {
7796: Uint32 source[3];
7797:
7798: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7799: dsp_rnd56(source);
7800:
7801: dsp_core.registers[DSP_REG_A2] = source[0];
7802: dsp_core.registers[DSP_REG_A1] = source[1];
7803: dsp_core.registers[DSP_REG_A0] = source[2];
7804:
7805: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7806: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7807: }
7808:
7809: static void dsp_mpyr_p_x0_y1_b(void)
7810: {
7811: Uint32 source[3];
7812:
7813: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7814: dsp_rnd56(source);
7815:
7816: dsp_core.registers[DSP_REG_B2] = source[0];
7817: dsp_core.registers[DSP_REG_B1] = source[1];
7818: dsp_core.registers[DSP_REG_B0] = source[2];
7819:
7820: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7821: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7822: }
7823:
7824: static void dsp_mpyr_m_x0_y1_b(void)
7825: {
7826: Uint32 source[3];
7827:
7828: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7829: dsp_rnd56(source);
7830:
7831: dsp_core.registers[DSP_REG_B2] = source[0];
7832: dsp_core.registers[DSP_REG_B1] = source[1];
7833: dsp_core.registers[DSP_REG_B0] = source[2];
7834:
7835: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7836: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7837: }
7838:
7839: static void dsp_mpyr_p_y0_x0_a(void)
7840: {
7841: Uint32 source[3];
7842:
7843: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7844: dsp_rnd56(source);
7845:
7846: dsp_core.registers[DSP_REG_A2] = source[0];
7847: dsp_core.registers[DSP_REG_A1] = source[1];
7848: dsp_core.registers[DSP_REG_A0] = source[2];
7849:
7850: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7851: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7852: }
7853:
7854: static void dsp_mpyr_m_y0_x0_a(void)
7855: {
7856: Uint32 source[3];
7857:
7858: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7859: dsp_rnd56(source);
7860:
7861: dsp_core.registers[DSP_REG_A2] = source[0];
7862: dsp_core.registers[DSP_REG_A1] = source[1];
7863: dsp_core.registers[DSP_REG_A0] = source[2];
7864:
7865: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7866: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7867: }
7868:
7869: static void dsp_mpyr_p_y0_x0_b(void)
7870: {
7871: Uint32 source[3];
7872:
7873: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7874: dsp_rnd56(source);
7875:
7876: dsp_core.registers[DSP_REG_B2] = source[0];
7877: dsp_core.registers[DSP_REG_B1] = source[1];
7878: dsp_core.registers[DSP_REG_B0] = source[2];
7879:
7880: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7881: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7882: }
7883:
7884: static void dsp_mpyr_m_y0_x0_b(void)
7885: {
7886: Uint32 source[3];
7887:
7888: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7889: dsp_rnd56(source);
7890:
7891: dsp_core.registers[DSP_REG_B2] = source[0];
7892: dsp_core.registers[DSP_REG_B1] = source[1];
7893: dsp_core.registers[DSP_REG_B0] = source[2];
7894:
7895: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7896: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7897: }
7898:
7899: static void dsp_mpyr_p_x1_y0_a(void)
7900: {
7901: Uint32 source[3];
7902:
7903: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7904: dsp_rnd56(source);
7905:
7906: dsp_core.registers[DSP_REG_A2] = source[0];
7907: dsp_core.registers[DSP_REG_A1] = source[1];
7908: dsp_core.registers[DSP_REG_A0] = source[2];
7909:
7910: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7911: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7912: }
7913:
7914: static void dsp_mpyr_m_x1_y0_a(void)
7915: {
7916: Uint32 source[3];
7917:
7918: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7919: dsp_rnd56(source);
7920:
7921: dsp_core.registers[DSP_REG_A2] = source[0];
7922: dsp_core.registers[DSP_REG_A1] = source[1];
7923: dsp_core.registers[DSP_REG_A0] = source[2];
7924:
7925: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7926: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7927: }
7928:
7929: static void dsp_mpyr_p_x1_y0_b(void)
7930: {
7931: Uint32 source[3];
7932:
7933: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7934: dsp_rnd56(source);
7935:
7936: dsp_core.registers[DSP_REG_B2] = source[0];
7937: dsp_core.registers[DSP_REG_B1] = source[1];
7938: dsp_core.registers[DSP_REG_B0] = source[2];
7939:
7940: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7941: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7942: }
7943:
7944: static void dsp_mpyr_m_x1_y0_b(void)
7945: {
7946: Uint32 source[3];
7947:
7948: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7949: dsp_rnd56(source);
7950:
7951: dsp_core.registers[DSP_REG_B2] = source[0];
7952: dsp_core.registers[DSP_REG_B1] = source[1];
7953: dsp_core.registers[DSP_REG_B0] = source[2];
7954:
7955: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7956: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7957: }
7958:
7959: static void dsp_mpyr_p_y1_x1_a(void)
7960: {
7961: Uint32 source[3];
7962:
7963: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7964: dsp_rnd56(source);
7965:
7966: dsp_core.registers[DSP_REG_A2] = source[0];
7967: dsp_core.registers[DSP_REG_A1] = source[1];
7968: dsp_core.registers[DSP_REG_A0] = source[2];
7969:
7970: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7971: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7972: }
7973:
7974: static void dsp_mpyr_m_y1_x1_a(void)
7975: {
7976: Uint32 source[3];
7977:
7978: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7979: dsp_rnd56(source);
7980:
7981: dsp_core.registers[DSP_REG_A2] = source[0];
7982: dsp_core.registers[DSP_REG_A1] = source[1];
7983: dsp_core.registers[DSP_REG_A0] = source[2];
7984:
7985: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7986: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7987: }
7988:
7989: static void dsp_mpyr_p_y1_x1_b(void)
7990: {
7991: Uint32 source[3];
7992:
7993: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7994: dsp_rnd56(source);
7995:
7996: dsp_core.registers[DSP_REG_B2] = source[0];
7997: dsp_core.registers[DSP_REG_B1] = source[1];
7998: dsp_core.registers[DSP_REG_B0] = source[2];
7999:
8000: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8001: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8002: }
8003:
8004: static void dsp_mpyr_m_y1_x1_b(void)
8005: {
8006: Uint32 source[3];
8007:
8008: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
8009: dsp_rnd56(source);
8010:
8011: dsp_core.registers[DSP_REG_B2] = source[0];
8012: dsp_core.registers[DSP_REG_B1] = source[1];
8013: dsp_core.registers[DSP_REG_B0] = source[2];
8014:
8015: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8016: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8017: }
8018:
8019: static void dsp_neg_a(void)
8020: {
8021: Uint32 source[3], dest[3], overflowed;
8022:
8023: source[0] = dsp_core.registers[DSP_REG_A2];
8024: source[1] = dsp_core.registers[DSP_REG_A1];
8025: source[2] = dsp_core.registers[DSP_REG_A0];
8026:
8027: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8028:
8029: dest[0] = dest[1] = dest[2] = 0;
8030:
8031: dsp_sub56(source, dest);
8032:
8033: dsp_core.registers[DSP_REG_A2] = dest[0];
8034: dsp_core.registers[DSP_REG_A1] = dest[1];
8035: dsp_core.registers[DSP_REG_A0] = dest[2];
8036:
8037: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8038: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8039:
8040: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8041: }
8042:
8043: static void dsp_neg_b(void)
8044: {
8045: Uint32 source[3], dest[3], overflowed;
8046:
8047: source[0] = dsp_core.registers[DSP_REG_B2];
8048: source[1] = dsp_core.registers[DSP_REG_B1];
8049: source[2] = dsp_core.registers[DSP_REG_B0];
8050:
8051: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8052:
8053: dest[0] = dest[1] = dest[2] = 0;
8054:
8055: dsp_sub56(source, dest);
8056:
8057: dsp_core.registers[DSP_REG_B2] = dest[0];
8058: dsp_core.registers[DSP_REG_B1] = dest[1];
8059: dsp_core.registers[DSP_REG_B0] = dest[2];
8060:
8061: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8062: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8063:
8064: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8065: }
8066:
8067: static void dsp_nop(void)
8068: {
8069: }
8070:
8071: static void dsp_not_a(void)
8072: {
8073: dsp_core.registers[DSP_REG_A1] = ~dsp_core.registers[DSP_REG_A1];
8074: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8075:
8076: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8077: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8078: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8079: }
8080:
8081: static void dsp_not_b(void)
8082: {
8083: dsp_core.registers[DSP_REG_B1] = ~dsp_core.registers[DSP_REG_B1];
8084: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8085:
8086: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8087: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8088: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8089: }
8090:
8091: static void dsp_or_x0_a(void)
8092: {
8093: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X0];
8094: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8095:
8096: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8097: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8098: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8099: }
8100:
8101: static void dsp_or_x0_b(void)
8102: {
8103: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X0];
8104: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8105:
8106: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8107: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8108: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8109: }
8110:
8111: static void dsp_or_y0_a(void)
8112: {
8113: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y0];
8114: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8115:
8116: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8117: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8118: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8119: }
8120:
8121: static void dsp_or_y0_b(void)
8122: {
8123: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y0];
8124: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8125:
8126: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8127: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8128: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8129: }
8130:
8131: static void dsp_or_x1_a(void)
8132: {
8133: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X1];
8134: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8135:
8136: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8137: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8138: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8139: }
8140:
8141: static void dsp_or_x1_b(void)
8142: {
8143: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X1];
8144: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8145:
8146: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8147: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8148: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8149: }
8150:
8151: static void dsp_or_y1_a(void)
8152: {
8153: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y1];
8154: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8155:
8156: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8157: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8158: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8159: }
8160:
8161: static void dsp_or_y1_b(void)
8162: {
8163: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y1];
8164: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8165:
8166: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8167: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8168: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8169: }
8170:
8171: static void dsp_rnd_a(void)
8172: {
8173: Uint32 dest[3];
8174:
8175: dest[0] = dsp_core.registers[DSP_REG_A2];
8176: dest[1] = dsp_core.registers[DSP_REG_A1];
8177: dest[2] = dsp_core.registers[DSP_REG_A0];
8178:
8179: dsp_rnd56(dest);
8180:
8181: dsp_core.registers[DSP_REG_A2] = dest[0];
8182: dsp_core.registers[DSP_REG_A1] = dest[1];
8183: dsp_core.registers[DSP_REG_A0] = dest[2];
8184:
8185: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8186: }
8187:
8188: static void dsp_rnd_b(void)
8189: {
8190: Uint32 dest[3];
8191:
8192: dest[0] = dsp_core.registers[DSP_REG_B2];
8193: dest[1] = dsp_core.registers[DSP_REG_B1];
8194: dest[2] = dsp_core.registers[DSP_REG_B0];
8195:
8196: dsp_rnd56(dest);
8197:
8198: dsp_core.registers[DSP_REG_B2] = dest[0];
8199: dsp_core.registers[DSP_REG_B1] = dest[1];
8200: dsp_core.registers[DSP_REG_B0] = dest[2];
8201:
8202: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8203: }
8204:
8205: static void dsp_rol_a(void)
8206: {
8207: Uint32 newcarry;
8208:
8209: newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
8210:
8211: dsp_core.registers[DSP_REG_A1] <<= 1;
8212: dsp_core.registers[DSP_REG_A1] |= newcarry;
8213: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
8214:
8215: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8216: dsp_core.registers[DSP_REG_SR] |= newcarry;
8217: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8218: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8219: }
8220:
8221: static void dsp_rol_b(void)
8222: {
8223: Uint32 newcarry;
8224:
8225: newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
8226:
8227: dsp_core.registers[DSP_REG_B1] <<= 1;
8228: dsp_core.registers[DSP_REG_B1] |= newcarry;
8229: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
8230:
8231: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8232: dsp_core.registers[DSP_REG_SR] |= newcarry;
8233: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8234: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8235: }
8236:
8237: static void dsp_ror_a(void)
8238: {
8239: Uint32 newcarry;
8240:
8241: newcarry = dsp_core.registers[DSP_REG_A1] & 1;
8242:
8243: dsp_core.registers[DSP_REG_A1] >>= 1;
8244: dsp_core.registers[DSP_REG_A1] |= newcarry<<23;
8245:
8246: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8247: dsp_core.registers[DSP_REG_SR] |= newcarry;
8248: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8249: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8250: }
8251:
8252: static void dsp_ror_b(void)
8253: {
8254: Uint32 newcarry;
8255:
8256: newcarry = dsp_core.registers[DSP_REG_B1] & 1;
8257:
8258: dsp_core.registers[DSP_REG_B1] >>= 1;
8259: dsp_core.registers[DSP_REG_B1] |= newcarry<<23;
8260:
8261: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8262: dsp_core.registers[DSP_REG_SR] |= newcarry;
8263: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8264: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8265: }
8266:
8267: static void dsp_sbc_x_a(void)
8268: {
8269: Uint32 source[3], dest[3], curcarry;
8270: Uint16 newsr;
8271:
8272: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8273:
8274: dest[2] = dsp_core.registers[DSP_REG_A0];
8275: dest[1] = dsp_core.registers[DSP_REG_A1];
8276: dest[0] = dsp_core.registers[DSP_REG_A2];
8277:
8278: source[2] = dsp_core.registers[DSP_REG_X0];
8279: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8280: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8281:
8282: newsr = dsp_sub56(source, dest);
1.1.1.11 root 8283:
1.1.1.6 root 8284: if (curcarry) {
8285: source[0]=0; source[1]=0; source[2]=1;
8286: newsr |= dsp_sub56(source, dest);
8287: }
8288:
8289: dsp_core.registers[DSP_REG_A2] = dest[0];
8290: dsp_core.registers[DSP_REG_A1] = dest[1];
8291: dsp_core.registers[DSP_REG_A0] = dest[2];
8292:
8293: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8294:
8295: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8296: dsp_core.registers[DSP_REG_SR] |= newsr;
8297: }
8298:
8299: static void dsp_sbc_x_b(void)
8300: {
8301: Uint32 source[3], dest[3], curcarry;
8302: Uint16 newsr;
8303:
8304: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8305:
8306: dest[2] = dsp_core.registers[DSP_REG_B0];
8307: dest[1] = dsp_core.registers[DSP_REG_B1];
8308: dest[0] = dsp_core.registers[DSP_REG_B2];
8309:
8310: source[2] = dsp_core.registers[DSP_REG_X0];
8311: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8312: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8313:
8314: newsr = dsp_sub56(source, dest);
1.1.1.11 root 8315:
1.1.1.6 root 8316: if (curcarry) {
8317: source[0]=0; source[1]=0; source[2]=1;
8318: newsr |= dsp_sub56(source, dest);
8319: }
8320:
8321: dsp_core.registers[DSP_REG_B2] = dest[0];
8322: dsp_core.registers[DSP_REG_B1] = dest[1];
8323: dsp_core.registers[DSP_REG_B0] = dest[2];
8324:
8325: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8326:
8327: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8328: dsp_core.registers[DSP_REG_SR] |= newsr;
8329: }
8330:
8331: static void dsp_sbc_y_a(void)
8332: {
8333: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 8334: Uint16 newsr;
1.1 root 8335:
1.1.1.6 root 8336: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8337:
8338: dest[2] = dsp_core.registers[DSP_REG_A0];
8339: dest[1] = dsp_core.registers[DSP_REG_A1];
8340: dest[0] = dsp_core.registers[DSP_REG_A2];
8341:
8342: source[2] = dsp_core.registers[DSP_REG_Y0];
8343: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8344: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8345:
8346: newsr = dsp_sub56(source, dest);
1.1.1.11 root 8347:
1.1.1.6 root 8348: if (curcarry) {
8349: source[0]=0; source[1]=0; source[2]=1;
8350: newsr |= dsp_sub56(source, dest);
8351: }
8352:
8353: dsp_core.registers[DSP_REG_A2] = dest[0];
8354: dsp_core.registers[DSP_REG_A1] = dest[1];
8355: dsp_core.registers[DSP_REG_A0] = dest[2];
8356:
8357: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8358:
8359: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8360: dsp_core.registers[DSP_REG_SR] |= newsr;
8361: }
8362:
8363: static void dsp_sbc_y_b(void)
8364: {
8365: Uint32 source[3], dest[3], curcarry;
8366: Uint16 newsr;
8367:
8368: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8369:
8370: dest[2] = dsp_core.registers[DSP_REG_B0];
8371: dest[1] = dsp_core.registers[DSP_REG_B1];
8372: dest[0] = dsp_core.registers[DSP_REG_B2];
8373:
8374: source[2] = dsp_core.registers[DSP_REG_Y0];
8375: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8376: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8377:
8378: newsr = dsp_sub56(source, dest);
1.1.1.11 root 8379:
1.1.1.6 root 8380: if (curcarry) {
8381: source[0]=0; source[1]=0; source[2]=1;
8382: newsr |= dsp_sub56(source, dest);
1.1 root 8383: }
8384:
1.1.1.6 root 8385: dsp_core.registers[DSP_REG_B2] = dest[0];
8386: dsp_core.registers[DSP_REG_B1] = dest[1];
8387: dsp_core.registers[DSP_REG_B0] = dest[2];
8388:
8389: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8390:
8391: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8392: dsp_core.registers[DSP_REG_SR] |= newsr;
8393: }
8394:
8395: static void dsp_sub_b_a(void)
8396: {
8397: Uint32 source[3], dest[3];
8398: Uint16 newsr;
8399:
8400: dest[2] = dsp_core.registers[DSP_REG_A0];
8401: dest[1] = dsp_core.registers[DSP_REG_A1];
8402: dest[0] = dsp_core.registers[DSP_REG_A2];
8403:
8404: source[2] = dsp_core.registers[DSP_REG_B0];
8405: source[1] = dsp_core.registers[DSP_REG_B1];
8406: source[0] = dsp_core.registers[DSP_REG_B2];
8407:
1.1 root 8408: newsr = dsp_sub56(source, dest);
8409:
1.1.1.6 root 8410: dsp_core.registers[DSP_REG_A2] = dest[0];
8411: dsp_core.registers[DSP_REG_A1] = dest[1];
8412: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8413:
1.1.1.6 root 8414: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8415:
1.1.1.6 root 8416: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8417: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8418: }
8419:
1.1.1.6 root 8420: static void dsp_sub_a_b(void)
1.1 root 8421: {
1.1.1.6 root 8422: Uint32 source[3], dest[3];
1.1.1.2 root 8423: Uint16 newsr;
1.1 root 8424:
1.1.1.6 root 8425: dest[2] = dsp_core.registers[DSP_REG_B0];
8426: dest[1] = dsp_core.registers[DSP_REG_B1];
8427: dest[0] = dsp_core.registers[DSP_REG_B2];
8428:
8429: source[2] = dsp_core.registers[DSP_REG_A0];
8430: source[1] = dsp_core.registers[DSP_REG_A1];
8431: source[0] = dsp_core.registers[DSP_REG_A2];
8432:
8433: newsr = dsp_sub56(source, dest);
8434:
8435: dsp_core.registers[DSP_REG_B2] = dest[0];
8436: dsp_core.registers[DSP_REG_B1] = dest[1];
8437: dsp_core.registers[DSP_REG_B0] = dest[2];
8438:
8439: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8440:
8441: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8442: dsp_core.registers[DSP_REG_SR] |= newsr;
8443: }
8444:
8445: static void dsp_sub_x_a(void)
8446: {
8447: Uint32 source[3], dest[3];
8448: Uint16 newsr;
8449:
8450: dest[2] = dsp_core.registers[DSP_REG_A0];
8451: dest[1] = dsp_core.registers[DSP_REG_A1];
8452: dest[0] = dsp_core.registers[DSP_REG_A2];
8453:
8454: source[2] = dsp_core.registers[DSP_REG_X0];
8455: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8456: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8457:
8458: newsr = dsp_sub56(source, dest);
8459:
8460: dsp_core.registers[DSP_REG_A2] = dest[0];
8461: dsp_core.registers[DSP_REG_A1] = dest[1];
8462: dsp_core.registers[DSP_REG_A0] = dest[2];
8463:
8464: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8465:
8466: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8467: dsp_core.registers[DSP_REG_SR] |= newsr;
8468: }
8469:
8470: static void dsp_sub_x_b(void)
8471: {
8472: Uint32 source[3], dest[3];
8473: Uint16 newsr;
8474:
8475: dest[2] = dsp_core.registers[DSP_REG_B0];
8476: dest[1] = dsp_core.registers[DSP_REG_B1];
8477: dest[0] = dsp_core.registers[DSP_REG_B2];
8478:
8479: source[2] = dsp_core.registers[DSP_REG_X0];
8480: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8481: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8482:
8483: newsr = dsp_sub56(source, dest);
8484:
8485: dsp_core.registers[DSP_REG_B2] = dest[0];
8486: dsp_core.registers[DSP_REG_B1] = dest[1];
8487: dsp_core.registers[DSP_REG_B0] = dest[2];
8488:
8489: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8490:
8491: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8492: dsp_core.registers[DSP_REG_SR] |= newsr;
8493: }
8494:
8495: static void dsp_sub_y_a(void)
8496: {
8497: Uint32 source[3], dest[3];
8498: Uint16 newsr;
8499:
8500: dest[2] = dsp_core.registers[DSP_REG_A0];
8501: dest[1] = dsp_core.registers[DSP_REG_A1];
8502: dest[0] = dsp_core.registers[DSP_REG_A2];
8503:
8504: source[2] = dsp_core.registers[DSP_REG_Y0];
8505: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8506: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8507:
8508: newsr = dsp_sub56(source, dest);
8509:
8510: dsp_core.registers[DSP_REG_A2] = dest[0];
8511: dsp_core.registers[DSP_REG_A1] = dest[1];
8512: dsp_core.registers[DSP_REG_A0] = dest[2];
8513:
8514: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8515:
8516: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8517: dsp_core.registers[DSP_REG_SR] |= newsr;
8518: }
8519:
8520: static void dsp_sub_y_b(void)
8521: {
8522: Uint32 source[3], dest[3];
8523: Uint16 newsr;
8524:
8525: dest[2] = dsp_core.registers[DSP_REG_B0];
8526: dest[1] = dsp_core.registers[DSP_REG_B1];
8527: dest[0] = dsp_core.registers[DSP_REG_B2];
8528:
8529: source[2] = dsp_core.registers[DSP_REG_Y0];
8530: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8531: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8532:
8533: newsr = dsp_sub56(source, dest);
8534:
8535: dsp_core.registers[DSP_REG_B2] = dest[0];
8536: dsp_core.registers[DSP_REG_B1] = dest[1];
8537: dsp_core.registers[DSP_REG_B0] = dest[2];
8538:
8539: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8540:
8541: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8542: dsp_core.registers[DSP_REG_SR] |= newsr;
8543: }
8544:
8545: static void dsp_sub_x0_a(void)
8546: {
8547: Uint32 source[3], dest[3];
8548: Uint16 newsr;
8549:
8550: dest[2] = dsp_core.registers[DSP_REG_A0];
8551: dest[1] = dsp_core.registers[DSP_REG_A1];
8552: dest[0] = dsp_core.registers[DSP_REG_A2];
8553:
8554: source[2] = 0;
8555: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 8556: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8557:
8558: newsr = dsp_sub56(source, dest);
8559:
8560: dsp_core.registers[DSP_REG_A2] = dest[0];
8561: dsp_core.registers[DSP_REG_A1] = dest[1];
8562: dsp_core.registers[DSP_REG_A0] = dest[2];
8563:
8564: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8565:
8566: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8567: dsp_core.registers[DSP_REG_SR] |= newsr;
8568: }
8569:
8570: static void dsp_sub_x0_b(void)
8571: {
8572: Uint32 source[3], dest[3];
8573: Uint16 newsr;
8574:
8575: dest[2] = dsp_core.registers[DSP_REG_B0];
8576: dest[1] = dsp_core.registers[DSP_REG_B1];
8577: dest[0] = dsp_core.registers[DSP_REG_B2];
8578:
8579: source[2] = 0;
8580: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 8581: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8582:
8583: newsr = dsp_sub56(source, dest);
8584:
8585: dsp_core.registers[DSP_REG_B2] = dest[0];
8586: dsp_core.registers[DSP_REG_B1] = dest[1];
8587: dsp_core.registers[DSP_REG_B0] = dest[2];
8588:
8589: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8590:
8591: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8592: dsp_core.registers[DSP_REG_SR] |= newsr;
8593: }
8594:
8595: static void dsp_sub_y0_a(void)
8596: {
8597: Uint32 source[3], dest[3];
8598: Uint16 newsr;
8599:
8600: dest[2] = dsp_core.registers[DSP_REG_A0];
8601: dest[1] = dsp_core.registers[DSP_REG_A1];
8602: dest[0] = dsp_core.registers[DSP_REG_A2];
8603:
8604: source[2] = 0;
8605: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 8606: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8607:
8608: newsr = dsp_sub56(source, dest);
1.1 root 8609:
1.1.1.6 root 8610: dsp_core.registers[DSP_REG_A2] = dest[0];
8611: dsp_core.registers[DSP_REG_A1] = dest[1];
8612: dsp_core.registers[DSP_REG_A0] = dest[2];
8613:
8614: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8615:
8616: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8617: dsp_core.registers[DSP_REG_SR] |= newsr;
8618: }
8619:
8620: static void dsp_sub_y0_b(void)
8621: {
8622: Uint32 source[3], dest[3];
8623: Uint16 newsr;
8624:
8625: dest[2] = dsp_core.registers[DSP_REG_B0];
8626: dest[1] = dsp_core.registers[DSP_REG_B1];
8627: dest[0] = dsp_core.registers[DSP_REG_B2];
8628:
8629: source[2] = 0;
8630: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 8631: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8632:
8633: newsr = dsp_sub56(source, dest);
8634:
8635: dsp_core.registers[DSP_REG_B2] = dest[0];
8636: dsp_core.registers[DSP_REG_B1] = dest[1];
8637: dsp_core.registers[DSP_REG_B0] = dest[2];
8638:
8639: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8640:
8641: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8642: dsp_core.registers[DSP_REG_SR] |= newsr;
8643: }
8644:
8645: static void dsp_sub_x1_a(void)
8646: {
8647: Uint32 source[3], dest[3];
8648: Uint16 newsr;
8649:
8650: dest[2] = dsp_core.registers[DSP_REG_A0];
8651: dest[1] = dsp_core.registers[DSP_REG_A1];
8652: dest[0] = dsp_core.registers[DSP_REG_A2];
8653:
8654: source[2] = 0;
8655: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8656: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8657:
8658: newsr = dsp_sub56(source, dest);
8659:
8660: dsp_core.registers[DSP_REG_A2] = dest[0];
8661: dsp_core.registers[DSP_REG_A1] = dest[1];
8662: dsp_core.registers[DSP_REG_A0] = dest[2];
8663:
8664: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8665:
8666: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8667: dsp_core.registers[DSP_REG_SR] |= newsr;
8668: }
8669:
8670: static void dsp_sub_x1_b(void)
8671: {
8672: Uint32 source[3], dest[3];
8673: Uint16 newsr;
8674:
8675: dest[2] = dsp_core.registers[DSP_REG_B0];
8676: dest[1] = dsp_core.registers[DSP_REG_B1];
8677: dest[0] = dsp_core.registers[DSP_REG_B2];
8678:
8679: source[2] = 0;
8680: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8681: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8682:
8683: newsr = dsp_sub56(source, dest);
8684:
8685: dsp_core.registers[DSP_REG_B2] = dest[0];
8686: dsp_core.registers[DSP_REG_B1] = dest[1];
8687: dsp_core.registers[DSP_REG_B0] = dest[2];
8688:
8689: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8690:
8691: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8692: dsp_core.registers[DSP_REG_SR] |= newsr;
8693: }
8694:
8695: static void dsp_sub_y1_a(void)
8696: {
8697: Uint32 source[3], dest[3];
8698: Uint16 newsr;
8699:
8700: dest[2] = dsp_core.registers[DSP_REG_A0];
8701: dest[1] = dsp_core.registers[DSP_REG_A1];
8702: dest[0] = dsp_core.registers[DSP_REG_A2];
8703:
8704: source[2] = 0;
8705: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8706: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8707:
8708: newsr = dsp_sub56(source, dest);
8709:
8710: dsp_core.registers[DSP_REG_A2] = dest[0];
8711: dsp_core.registers[DSP_REG_A1] = dest[1];
8712: dsp_core.registers[DSP_REG_A0] = dest[2];
8713:
8714: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8715:
8716: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8717: dsp_core.registers[DSP_REG_SR] |= newsr;
8718: }
8719:
8720: static void dsp_sub_y1_b(void)
8721: {
8722: Uint32 source[3], dest[3];
8723: Uint16 newsr;
8724:
8725: dest[2] = dsp_core.registers[DSP_REG_B0];
8726: dest[1] = dsp_core.registers[DSP_REG_B1];
8727: dest[0] = dsp_core.registers[DSP_REG_B2];
8728:
8729: source[2] = 0;
8730: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8731: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8732:
8733: newsr = dsp_sub56(source, dest);
8734:
8735: dsp_core.registers[DSP_REG_B2] = dest[0];
8736: dsp_core.registers[DSP_REG_B1] = dest[1];
8737: dsp_core.registers[DSP_REG_B0] = dest[2];
8738:
8739: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8740:
8741: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8742: dsp_core.registers[DSP_REG_SR] |= newsr;
8743: }
8744:
8745: static void dsp_subl_a(void)
8746: {
8747: Uint32 source[3], dest[3];
8748: Uint16 newsr;
8749:
8750: dest[0] = dsp_core.registers[DSP_REG_A2];
8751: dest[1] = dsp_core.registers[DSP_REG_A1];
8752: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 8753: newsr = dsp_asl56(dest);
8754:
1.1.1.6 root 8755: source[0] = dsp_core.registers[DSP_REG_B2];
8756: source[1] = dsp_core.registers[DSP_REG_B1];
8757: source[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 8758: newsr |= dsp_sub56(source, dest);
8759:
1.1.1.6 root 8760: dsp_core.registers[DSP_REG_A2] = dest[0];
8761: dsp_core.registers[DSP_REG_A1] = dest[1];
8762: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8763:
1.1.1.6 root 8764: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8765:
1.1.1.6 root 8766: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8767: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8768: }
8769:
1.1.1.6 root 8770: static void dsp_subl_b(void)
1.1 root 8771: {
1.1.1.6 root 8772: Uint32 source[3], dest[3];
1.1.1.2 root 8773: Uint16 newsr;
1.1 root 8774:
1.1.1.6 root 8775: dest[0] = dsp_core.registers[DSP_REG_B2];
8776: dest[1] = dsp_core.registers[DSP_REG_B1];
8777: dest[2] = dsp_core.registers[DSP_REG_B0];
8778: newsr = dsp_asl56(dest);
1.1 root 8779:
1.1.1.6 root 8780: source[0] = dsp_core.registers[DSP_REG_A2];
8781: source[1] = dsp_core.registers[DSP_REG_A1];
8782: source[2] = dsp_core.registers[DSP_REG_A0];
8783: newsr |= dsp_sub56(source, dest);
8784:
8785: dsp_core.registers[DSP_REG_B2] = dest[0];
8786: dsp_core.registers[DSP_REG_B1] = dest[1];
8787: dsp_core.registers[DSP_REG_B0] = dest[2];
8788:
8789: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8790:
8791: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8792: dsp_core.registers[DSP_REG_SR] |= newsr;
8793: }
8794:
8795: static void dsp_subr_a(void)
8796: {
8797: Uint32 source[3], dest[3];
8798: Uint16 newsr;
8799:
8800: dest[0] = dsp_core.registers[DSP_REG_A2];
8801: dest[1] = dsp_core.registers[DSP_REG_A1];
8802: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1.1.11 root 8803:
1.1 root 8804: newsr = dsp_asr56(dest);
8805:
1.1.1.6 root 8806: source[0] = dsp_core.registers[DSP_REG_B2];
8807: source[1] = dsp_core.registers[DSP_REG_B1];
8808: source[2] = dsp_core.registers[DSP_REG_B0];
1.1.1.11 root 8809:
1.1 root 8810: newsr |= dsp_sub56(source, dest);
8811:
1.1.1.6 root 8812: dsp_core.registers[DSP_REG_A2] = dest[0];
8813: dsp_core.registers[DSP_REG_A1] = dest[1];
8814: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8815:
1.1.1.6 root 8816: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8817:
1.1.1.6 root 8818: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8819: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8820: }
8821:
1.1.1.6 root 8822: static void dsp_subr_b(void)
1.1 root 8823: {
1.1.1.6 root 8824: Uint32 source[3], dest[3];
8825: Uint16 newsr;
1.1 root 8826:
1.1.1.6 root 8827: dest[0] = dsp_core.registers[DSP_REG_B2];
8828: dest[1] = dsp_core.registers[DSP_REG_B1];
8829: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1.1.11 root 8830:
1.1.1.6 root 8831: newsr = dsp_asr56(dest);
1.1 root 8832:
1.1.1.6 root 8833: source[0] = dsp_core.registers[DSP_REG_A2];
8834: source[1] = dsp_core.registers[DSP_REG_A1];
8835: source[2] = dsp_core.registers[DSP_REG_A0];
1.1.1.11 root 8836:
1.1.1.6 root 8837: newsr |= dsp_sub56(source, dest);
1.1 root 8838:
1.1.1.6 root 8839: dsp_core.registers[DSP_REG_B2] = dest[0];
8840: dsp_core.registers[DSP_REG_B1] = dest[1];
8841: dsp_core.registers[DSP_REG_B0] = dest[2];
8842:
8843: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8844:
8845: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8846: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8847: }
8848:
1.1.1.6 root 8849: static void dsp_tfr_b_a(void)
1.1 root 8850: {
1.1.1.6 root 8851: dsp_core.registers[DSP_REG_A0] = dsp_core.registers[DSP_REG_B0];
8852: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_B1];
8853: dsp_core.registers[DSP_REG_A2] = dsp_core.registers[DSP_REG_B2];
8854: }
1.1 root 8855:
1.1.1.6 root 8856: static void dsp_tfr_a_b(void)
8857: {
8858: dsp_core.registers[DSP_REG_B0] = dsp_core.registers[DSP_REG_A0];
8859: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_A1];
8860: dsp_core.registers[DSP_REG_B2] = dsp_core.registers[DSP_REG_A2];
8861: }
8862:
8863: static void dsp_tfr_x0_a(void)
8864: {
1.1.1.11 root 8865: dsp_write_reg(DSP_REG_A, dsp_core.registers[DSP_REG_X0]);
1.1.1.6 root 8866: }
8867:
8868: static void dsp_tfr_x0_b(void)
8869: {
1.1.1.11 root 8870: dsp_write_reg(DSP_REG_B, dsp_core.registers[DSP_REG_X0]);
1.1.1.6 root 8871: }
8872:
8873: static void dsp_tfr_y0_a(void)
8874: {
1.1.1.11 root 8875: dsp_write_reg(DSP_REG_A, dsp_core.registers[DSP_REG_Y0]);
1.1.1.6 root 8876: }
8877:
8878: static void dsp_tfr_y0_b(void)
8879: {
1.1.1.11 root 8880: dsp_write_reg(DSP_REG_B, dsp_core.registers[DSP_REG_Y0]);
1.1.1.6 root 8881: }
8882:
8883: static void dsp_tfr_x1_a(void)
8884: {
1.1.1.11 root 8885: dsp_write_reg(DSP_REG_A, dsp_core.registers[DSP_REG_X1]);
1.1.1.6 root 8886: }
8887:
8888: static void dsp_tfr_x1_b(void)
8889: {
1.1.1.11 root 8890: dsp_write_reg(DSP_REG_B, dsp_core.registers[DSP_REG_X1]);
1.1.1.6 root 8891: }
8892:
8893: static void dsp_tfr_y1_a(void)
8894: {
1.1.1.11 root 8895: dsp_write_reg(DSP_REG_A, dsp_core.registers[DSP_REG_Y1]);
1.1.1.6 root 8896: }
8897:
8898: static void dsp_tfr_y1_b(void)
8899: {
1.1.1.11 root 8900: dsp_write_reg(DSP_REG_B, dsp_core.registers[DSP_REG_Y1]);
1.1.1.6 root 8901: }
8902:
8903: static void dsp_tst_a(void)
8904: {
8905: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_A2],
1.1.1.7 root 8906: dsp_core.registers[DSP_REG_A1],
8907: dsp_core.registers[DSP_REG_A0]);
1.1.1.6 root 8908:
8909: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8910: }
8911:
8912: static void dsp_tst_b(void)
8913: {
8914: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_B2],
1.1.1.7 root 8915: dsp_core.registers[DSP_REG_B1],
8916: dsp_core.registers[DSP_REG_B0]);
1.1 root 8917:
1.1.1.6 root 8918: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
1.1 root 8919: }
8920:
1.1.1.2 root 8921: /*
8922: vim:ts=4:sw=4:
8923: */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.