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1.1 root 1: /*
1.1.1.2 root 2: DSP M56001 emulation
1.1.1.4 root 3: Instructions interpreter
1.1.1.2 root 4:
5: (C) 2003-2008 ARAnyM developer team
6:
7: This program is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2 of the License, or
10: (at your option) any later version.
11:
12: This program is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
1.1.1.13! root 18: along with this program; if not, write to the Free Software Foundation,
! 19: 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335 USA
1.1.1.2 root 20: */
21:
1.1.1.7 root 22: /*
23: DSP memory mapping
24: ------------------
1.1.1.11 root 25:
1.1.1.7 root 26: The memory map is configured as follows :
27: Program space P is one contiguous block of 32K dsp Words
1.1.1.11 root 28: X and Y data space are each separate 16K dsp Word blocks.
1.1.1.7 root 29: Both X and Y can be accessed as blocks starting at 0 or 16K.
30: Program space physically overlaps both X and Y data spaces.
31: Y: memory is mapped at address $0 in P memory
1.1.1.11 root 32: X: memory is mapped at address $4000 in P memory
1.1.1.7 root 33:
34: The DSP external RAM is zero waitstate, but there is a penalty for
1.1.1.11 root 35: accessing it twice or more in a single instruction, because there is only
1.1.1.9 root 36: one external data bus. The extra access costs 2 cycles penalty.
37:
1.1.1.7 root 38: The internal buses are all separate (0 waitstate)
39:
40:
41: X: Y: P:
42: $ffff |--------------+--------------+--------------|
43: | Int. I/O | Ext. I/O | |
44: $ffc0 |--------------+--------------+ |
45: | | | |
46: | Reserved | Reserved | Reserved |
47: | | | |
48: | | | |
49: | | | |
50: $8000 |--------------+--------------+--------------|
51: | | | |
52: | 16k Shadow | 16k Shadow | |
53: | | | 32K |
54: $4000 |--------------+--------------| Program |
55: | 16K | 16K | RAM |
56: | External | External | |
57: | RAM | RAM | |
58: $0200 |--------------+--------------+--------------|
59: | Log table or | Sin table or | |
60: | external mem | external mem | Internal |
61: $0100 |--------------+--------------+ program |
62: | Internal X | Internal Y | memory |
63: | memory | memory | |
64: $0000 |--------------+--------------+--------------|
65:
66:
67: Special Note : As the Falcon DSP is a 0 waitstate access memory, I've simplified a little the cycle counting.
68: If this DSP emulator code is used in another project, one should take into account the bus control register (BCR) waitstates.
69: */
70:
1.1.1.2 root 71: #ifdef HAVE_CONFIG_H
72: #include "config.h"
73: #endif
74:
1.1.1.6 root 75: #include <stdbool.h>
76:
1.1.1.10 root 77: #include "main.h"
1.1.1.2 root 78: #include "dsp_core.h"
1.1 root 79: #include "dsp_cpu.h"
80: #include "dsp_disasm.h"
1.1.1.6 root 81: #include "log.h"
1.1.1.9 root 82: #include "debugui.h"
1.1 root 83:
1.1.1.2 root 84: #define DSP_COUNT_IPS 0 /* Count instruction per seconds */
85:
1.1 root 86:
87: /**********************************
88: * Defines
89: **********************************/
90:
1.1.1.6 root 91: #define SIGN_PLUS 0
92: #define SIGN_MINUS 1
1.1.1.4 root 93:
1.1.1.9 root 94: /* Defines some bits values for access to external memory (X, Y, P) */
95: /* These values will set/unset the corresponding bits in the variable access_to_ext_memory */
96: /* to detect how many access to the external memory were done for a single instruction */
97: #define EXT_X_MEMORY 0
98: #define EXT_Y_MEMORY 1
99: #define EXT_P_MEMORY 2
100:
101:
1.1 root 102: /**********************************
103: * Variables
104: **********************************/
105:
1.1.1.4 root 106: /* Instructions per second */
107: static Uint32 start_time;
108: static Uint32 num_inst;
109:
1.1 root 110: /* Length of current instruction */
1.1.1.2 root 111: static Uint32 cur_inst_len; /* =0:jump, >0:increment */
1.1 root 112:
113: /* Current instruction */
1.1.1.4 root 114: static Uint32 cur_inst;
1.1 root 115:
1.1.1.7 root 116: /* Counts the number of access to the external memory for one instruction */
1.1.1.9 root 117: static Uint16 access_to_ext_memory;
1.1.1.7 root 118:
1.1.1.6 root 119: /* DSP is in disasm mode ? */
120: /* If yes, stack overflow, underflow and illegal instructions messages are not displayed */
121: static bool isDsp_in_disasm_mode;
1.1 root 122:
1.1.1.7 root 123: static char str_disasm_memory[2][50]; /* Buffer for memory change text in disasm mode */
1.1.1.5 root 124: static Uint16 disasm_memory_ptr; /* Pointer for memory change in disasm mode */
1.1 root 125:
126: /**********************************
127: * Functions
128: **********************************/
129:
130: typedef void (*dsp_emul_t)(void);
131:
132: static void dsp_postexecute_update_pc(void);
133: static void dsp_postexecute_interrupts(void);
134:
1.1.1.5 root 135: static void dsp_setInterruptIPL(Uint32 value);
136:
1.1.1.6 root 137: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2);
1.1.1.2 root 138:
139: static Uint32 read_memory(int space, Uint16 address);
1.1.1.6 root 140: static inline Uint32 read_memory_p(Uint16 address);
1.1.1.2 root 141: static Uint32 read_memory_disasm(int space, Uint16 address);
1.1.1.6 root 142:
143: static inline void write_memory(int space, Uint16 address, Uint32 value);
144: static void write_memory_raw(int space, Uint16 address, Uint32 value);
1.1.1.4 root 145: static void write_memory_disasm(int space, Uint16 address, Uint32 value);
1.1.1.6 root 146:
1.1.1.11 root 147: static void dsp_write_reg(Uint32 numreg, Uint32 value);
1.1 root 148:
1.1.1.4 root 149: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly);
1.1.1.2 root 150: static void dsp_stack_pop(Uint32 *curpc, Uint32 *cursr);
1.1.1.4 root 151: static void dsp_compute_ssh_ssl(void);
1.1 root 152:
153: static void opcode8h_0(void);
154:
1.1.1.2 root 155: static void dsp_update_rn(Uint32 numreg, Sint16 modifier);
156: static void dsp_update_rn_bitreverse(Uint32 numreg);
157: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier);
158: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr);
159: static int dsp_calc_cc(Uint32 cc_code);
1.1 root 160:
161: static void dsp_undefined(void);
162:
163: /* Instructions without parallel moves */
164: static void dsp_andi(void);
1.1.1.4 root 165: static void dsp_bchg_aa(void);
166: static void dsp_bchg_ea(void);
167: static void dsp_bchg_pp(void);
168: static void dsp_bchg_reg(void);
169: static void dsp_bclr_aa(void);
170: static void dsp_bclr_ea(void);
171: static void dsp_bclr_pp(void);
172: static void dsp_bclr_reg(void);
173: static void dsp_bset_aa(void);
174: static void dsp_bset_ea(void);
175: static void dsp_bset_pp(void);
176: static void dsp_bset_reg(void);
177: static void dsp_btst_aa(void);
178: static void dsp_btst_ea(void);
179: static void dsp_btst_pp(void);
180: static void dsp_btst_reg(void);
1.1 root 181: static void dsp_div(void);
182: static void dsp_enddo(void);
183: static void dsp_illegal(void);
1.1.1.4 root 184: static void dsp_jcc_imm(void);
185: static void dsp_jcc_ea(void);
186: static void dsp_jclr_aa(void);
187: static void dsp_jclr_ea(void);
188: static void dsp_jclr_pp(void);
189: static void dsp_jclr_reg(void);
190: static void dsp_jmp_ea(void);
191: static void dsp_jmp_imm(void);
192: static void dsp_jscc_ea(void);
193: static void dsp_jscc_imm(void);
194: static void dsp_jsclr_aa(void);
195: static void dsp_jsclr_ea(void);
196: static void dsp_jsclr_pp(void);
197: static void dsp_jsclr_reg(void);
198: static void dsp_jset_aa(void);
199: static void dsp_jset_ea(void);
200: static void dsp_jset_pp(void);
201: static void dsp_jset_reg(void);
202: static void dsp_jsr_ea(void);
203: static void dsp_jsr_imm(void);
204: static void dsp_jsset_aa(void);
205: static void dsp_jsset_ea(void);
206: static void dsp_jsset_pp(void);
207: static void dsp_jsset_reg(void);
1.1 root 208: static void dsp_lua(void);
1.1.1.4 root 209: static void dsp_movem_ea(void);
210: static void dsp_movem_aa(void);
1.1 root 211: static void dsp_nop(void);
212: static void dsp_norm(void);
213: static void dsp_ori(void);
214: static void dsp_reset(void);
215: static void dsp_rti(void);
216: static void dsp_rts(void);
217: static void dsp_stop(void);
218: static void dsp_swi(void);
219: static void dsp_tcc(void);
220: static void dsp_wait(void);
221:
1.1.1.3 root 222: static void dsp_do_ea(void);
223: static void dsp_do_aa(void);
224: static void dsp_do_imm(void);
225: static void dsp_do_reg(void);
226: static void dsp_rep_aa(void);
227: static void dsp_rep_ea(void);
228: static void dsp_rep_imm(void);
229: static void dsp_rep_reg(void);
230: static void dsp_movec_aa(void);
231: static void dsp_movec_ea(void);
232: static void dsp_movec_imm(void);
233: static void dsp_movec_reg(void);
1.1 root 234: static void dsp_movep_0(void);
235: static void dsp_movep_1(void);
1.1.1.4 root 236: static void dsp_movep_23(void);
1.1 root 237:
238: /* Parallel move analyzer */
1.1.1.2 root 239: static int dsp_pm_read_accu24(int numreg, Uint32 *dest);
1.1 root 240: static void dsp_pm_0(void);
241: static void dsp_pm_1(void);
242: static void dsp_pm_2(void);
243: static void dsp_pm_2_2(void);
244: static void dsp_pm_3(void);
245: static void dsp_pm_4(void);
1.1.1.4 root 246: static void dsp_pm_4x(void);
1.1 root 247: static void dsp_pm_5(void);
248: static void dsp_pm_8(void);
249:
250: /* 56bits arithmetic */
1.1.1.2 root 251: static Uint16 dsp_abs56(Uint32 *dest);
252: static Uint16 dsp_asl56(Uint32 *dest);
253: static Uint16 dsp_asr56(Uint32 *dest);
254: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest);
255: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest);
1.1.1.5 root 256: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe);
1.1.1.2 root 257: static void dsp_rnd56(Uint32 *dest);
1.1 root 258:
259: /* Instructions with parallel moves */
1.1.1.6 root 260: static void dsp_abs_a(void);
261: static void dsp_abs_b(void);
262: static void dsp_adc_x_a(void);
263: static void dsp_adc_x_b(void);
264: static void dsp_adc_y_a(void);
265: static void dsp_adc_y_b(void);
266: static void dsp_add_b_a(void);
267: static void dsp_add_a_b(void);
268: static void dsp_add_x_a(void);
269: static void dsp_add_x_b(void);
270: static void dsp_add_y_a(void);
271: static void dsp_add_y_b(void);
272: static void dsp_add_x0_a(void);
273: static void dsp_add_x0_b(void);
274: static void dsp_add_y0_a(void);
275: static void dsp_add_y0_b(void);
276: static void dsp_add_x1_a(void);
277: static void dsp_add_x1_b(void);
278: static void dsp_add_y1_a(void);
279: static void dsp_add_y1_b(void);
280: static void dsp_addl_b_a(void);
281: static void dsp_addl_a_b(void);
282: static void dsp_addr_b_a(void);
283: static void dsp_addr_a_b(void);
284: static void dsp_and_x0_a(void);
285: static void dsp_and_x0_b(void);
286: static void dsp_and_y0_a(void);
287: static void dsp_and_y0_b(void);
288: static void dsp_and_x1_a(void);
289: static void dsp_and_x1_b(void);
290: static void dsp_and_y1_a(void);
291: static void dsp_and_y1_b(void);
1.1.1.7 root 292: static void dsp_asl_a(void);
293: static void dsp_asl_b(void);
294: static void dsp_asr_a(void);
295: static void dsp_asr_b(void);
1.1.1.6 root 296: static void dsp_clr_a(void);
297: static void dsp_clr_b(void);
298: static void dsp_cmp_b_a(void);
299: static void dsp_cmp_a_b(void);
300: static void dsp_cmp_x0_a(void);
301: static void dsp_cmp_x0_b(void);
302: static void dsp_cmp_y0_a(void);
303: static void dsp_cmp_y0_b(void);
304: static void dsp_cmp_x1_a(void);
305: static void dsp_cmp_x1_b(void);
306: static void dsp_cmp_y1_a(void);
307: static void dsp_cmp_y1_b(void);
308: static void dsp_cmpm_b_a(void);
309: static void dsp_cmpm_a_b(void);
310: static void dsp_cmpm_x0_a(void);
311: static void dsp_cmpm_x0_b(void);
312: static void dsp_cmpm_y0_a(void);
313: static void dsp_cmpm_y0_b(void);
314: static void dsp_cmpm_x1_a(void);
315: static void dsp_cmpm_x1_b(void);
316: static void dsp_cmpm_y1_a(void);
317: static void dsp_cmpm_y1_b(void);
318: static void dsp_eor_x0_a(void);
319: static void dsp_eor_x0_b(void);
320: static void dsp_eor_y0_a(void);
321: static void dsp_eor_y0_b(void);
322: static void dsp_eor_x1_a(void);
323: static void dsp_eor_x1_b(void);
324: static void dsp_eor_y1_a(void);
325: static void dsp_eor_y1_b(void);
326: static void dsp_lsl_a(void);
327: static void dsp_lsl_b(void);
328: static void dsp_lsr_a(void);
329: static void dsp_lsr_b(void);
330: static void dsp_mac_p_x0_x0_a(void);
331: static void dsp_mac_m_x0_x0_a(void);
332: static void dsp_mac_p_x0_x0_b(void);
333: static void dsp_mac_m_x0_x0_b(void);
334: static void dsp_mac_p_y0_y0_a(void);
335: static void dsp_mac_m_y0_y0_a(void);
336: static void dsp_mac_p_y0_y0_b(void);
337: static void dsp_mac_m_y0_y0_b(void);
338: static void dsp_mac_p_x1_x0_a(void);
339: static void dsp_mac_m_x1_x0_a(void);
340: static void dsp_mac_p_x1_x0_b(void);
341: static void dsp_mac_m_x1_x0_b(void);
342: static void dsp_mac_p_y1_y0_a(void);
343: static void dsp_mac_m_y1_y0_a(void);
344: static void dsp_mac_p_y1_y0_b(void);
345: static void dsp_mac_m_y1_y0_b(void);
346: static void dsp_mac_p_x0_y1_a(void);
347: static void dsp_mac_m_x0_y1_a(void);
348: static void dsp_mac_p_x0_y1_b(void);
349: static void dsp_mac_m_x0_y1_b(void);
350: static void dsp_mac_p_y0_x0_a(void);
351: static void dsp_mac_m_y0_x0_a(void);
352: static void dsp_mac_p_y0_x0_b(void);
353: static void dsp_mac_m_y0_x0_b(void);
354: static void dsp_mac_p_x1_y0_a(void);
355: static void dsp_mac_m_x1_y0_a(void);
356: static void dsp_mac_p_x1_y0_b(void);
357: static void dsp_mac_m_x1_y0_b(void);
358: static void dsp_mac_p_y1_x1_a(void);
359: static void dsp_mac_m_y1_x1_a(void);
360: static void dsp_mac_p_y1_x1_b(void);
361: static void dsp_mac_m_y1_x1_b(void);
362: static void dsp_macr_p_x0_x0_a(void);
363: static void dsp_macr_m_x0_x0_a(void);
364: static void dsp_macr_p_x0_x0_b(void);
365: static void dsp_macr_m_x0_x0_b(void);
366: static void dsp_macr_p_y0_y0_a(void);
367: static void dsp_macr_m_y0_y0_a(void);
368: static void dsp_macr_p_y0_y0_b(void);
369: static void dsp_macr_m_y0_y0_b(void);
370: static void dsp_macr_p_x1_x0_a(void);
371: static void dsp_macr_m_x1_x0_a(void);
372: static void dsp_macr_p_x1_x0_b(void);
373: static void dsp_macr_m_x1_x0_b(void);
374: static void dsp_macr_p_y1_y0_a(void);
375: static void dsp_macr_m_y1_y0_a(void);
376: static void dsp_macr_p_y1_y0_b(void);
377: static void dsp_macr_m_y1_y0_b(void);
378: static void dsp_macr_p_x0_y1_a(void);
379: static void dsp_macr_m_x0_y1_a(void);
380: static void dsp_macr_p_x0_y1_b(void);
381: static void dsp_macr_m_x0_y1_b(void);
382: static void dsp_macr_p_y0_x0_a(void);
383: static void dsp_macr_m_y0_x0_a(void);
384: static void dsp_macr_p_y0_x0_b(void);
385: static void dsp_macr_m_y0_x0_b(void);
386: static void dsp_macr_p_x1_y0_a(void);
387: static void dsp_macr_m_x1_y0_a(void);
388: static void dsp_macr_p_x1_y0_b(void);
389: static void dsp_macr_m_x1_y0_b(void);
390: static void dsp_macr_p_y1_x1_a(void);
391: static void dsp_macr_m_y1_x1_a(void);
392: static void dsp_macr_p_y1_x1_b(void);
393: static void dsp_macr_m_y1_x1_b(void);
1.1 root 394: static void dsp_move(void);
1.1.1.6 root 395: static void dsp_mpy_p_x0_x0_a(void);
396: static void dsp_mpy_m_x0_x0_a(void);
397: static void dsp_mpy_p_x0_x0_b(void);
398: static void dsp_mpy_m_x0_x0_b(void);
399: static void dsp_mpy_p_y0_y0_a(void);
400: static void dsp_mpy_m_y0_y0_a(void);
401: static void dsp_mpy_p_y0_y0_b(void);
402: static void dsp_mpy_m_y0_y0_b(void);
403: static void dsp_mpy_p_x1_x0_a(void);
404: static void dsp_mpy_m_x1_x0_a(void);
405: static void dsp_mpy_p_x1_x0_b(void);
406: static void dsp_mpy_m_x1_x0_b(void);
407: static void dsp_mpy_p_y1_y0_a(void);
408: static void dsp_mpy_m_y1_y0_a(void);
409: static void dsp_mpy_p_y1_y0_b(void);
410: static void dsp_mpy_m_y1_y0_b(void);
411: static void dsp_mpy_p_x0_y1_a(void);
412: static void dsp_mpy_m_x0_y1_a(void);
413: static void dsp_mpy_p_x0_y1_b(void);
414: static void dsp_mpy_m_x0_y1_b(void);
415: static void dsp_mpy_p_y0_x0_a(void);
416: static void dsp_mpy_m_y0_x0_a(void);
417: static void dsp_mpy_p_y0_x0_b(void);
418: static void dsp_mpy_m_y0_x0_b(void);
419: static void dsp_mpy_p_x1_y0_a(void);
420: static void dsp_mpy_m_x1_y0_a(void);
421: static void dsp_mpy_p_x1_y0_b(void);
422: static void dsp_mpy_m_x1_y0_b(void);
423: static void dsp_mpy_p_y1_x1_a(void);
424: static void dsp_mpy_m_y1_x1_a(void);
425: static void dsp_mpy_p_y1_x1_b(void);
426: static void dsp_mpy_m_y1_x1_b(void);
427: static void dsp_mpyr_p_x0_x0_a(void);
428: static void dsp_mpyr_m_x0_x0_a(void);
429: static void dsp_mpyr_p_x0_x0_b(void);
430: static void dsp_mpyr_m_x0_x0_b(void);
431: static void dsp_mpyr_p_y0_y0_a(void);
432: static void dsp_mpyr_m_y0_y0_a(void);
433: static void dsp_mpyr_p_y0_y0_b(void);
434: static void dsp_mpyr_m_y0_y0_b(void);
435: static void dsp_mpyr_p_x1_x0_a(void);
436: static void dsp_mpyr_m_x1_x0_a(void);
437: static void dsp_mpyr_p_x1_x0_b(void);
438: static void dsp_mpyr_m_x1_x0_b(void);
439: static void dsp_mpyr_p_y1_y0_a(void);
440: static void dsp_mpyr_m_y1_y0_a(void);
441: static void dsp_mpyr_p_y1_y0_b(void);
442: static void dsp_mpyr_m_y1_y0_b(void);
443: static void dsp_mpyr_p_x0_y1_a(void);
444: static void dsp_mpyr_m_x0_y1_a(void);
445: static void dsp_mpyr_p_x0_y1_b(void);
446: static void dsp_mpyr_m_x0_y1_b(void);
447: static void dsp_mpyr_p_y0_x0_a(void);
448: static void dsp_mpyr_m_y0_x0_a(void);
449: static void dsp_mpyr_p_y0_x0_b(void);
450: static void dsp_mpyr_m_y0_x0_b(void);
451: static void dsp_mpyr_p_x1_y0_a(void);
452: static void dsp_mpyr_m_x1_y0_a(void);
453: static void dsp_mpyr_p_x1_y0_b(void);
454: static void dsp_mpyr_m_x1_y0_b(void);
455: static void dsp_mpyr_p_y1_x1_a(void);
456: static void dsp_mpyr_m_y1_x1_a(void);
457: static void dsp_mpyr_p_y1_x1_b(void);
458: static void dsp_mpyr_m_y1_x1_b(void);
459: static void dsp_neg_a(void);
460: static void dsp_neg_b(void);
461: static void dsp_not_a(void);
462: static void dsp_not_b(void);
463: static void dsp_or_x0_a(void);
464: static void dsp_or_x0_b(void);
465: static void dsp_or_y0_a(void);
466: static void dsp_or_y0_b(void);
467: static void dsp_or_x1_a(void);
468: static void dsp_or_x1_b(void);
469: static void dsp_or_y1_a(void);
470: static void dsp_or_y1_b(void);
471: static void dsp_rnd_a(void);
472: static void dsp_rnd_b(void);
473: static void dsp_rol_a(void);
474: static void dsp_rol_b(void);
475: static void dsp_ror_a(void);
476: static void dsp_ror_b(void);
477: static void dsp_sbc_x_a(void);
478: static void dsp_sbc_x_b(void);
479: static void dsp_sbc_y_a(void);
480: static void dsp_sbc_y_b(void);
481: static void dsp_sub_b_a(void);
482: static void dsp_sub_a_b(void);
483: static void dsp_sub_x_a(void);
484: static void dsp_sub_x_b(void);
485: static void dsp_sub_y_a(void);
486: static void dsp_sub_y_b(void);
487: static void dsp_sub_x0_a(void);
488: static void dsp_sub_x0_b(void);
489: static void dsp_sub_y0_a(void);
490: static void dsp_sub_y0_b(void);
491: static void dsp_sub_x1_a(void);
492: static void dsp_sub_x1_b(void);
493: static void dsp_sub_y1_a(void);
494: static void dsp_sub_y1_b(void);
495: static void dsp_subl_a(void);
496: static void dsp_subl_b(void);
497: static void dsp_subr_a(void);
498: static void dsp_subr_b(void);
499: static void dsp_tfr_b_a(void);
500: static void dsp_tfr_a_b(void);
501: static void dsp_tfr_x0_a(void);
502: static void dsp_tfr_x0_b(void);
503: static void dsp_tfr_y0_a(void);
504: static void dsp_tfr_y0_b(void);
505: static void dsp_tfr_x1_a(void);
506: static void dsp_tfr_x1_b(void);
507: static void dsp_tfr_y1_a(void);
508: static void dsp_tfr_y1_b(void);
509: static void dsp_tst_a(void);
510: static void dsp_tst_b(void);
1.1 root 511:
1.1.1.6 root 512: static const dsp_emul_t opcodes8h[512] = {
1.1.1.4 root 513: /* 0x00 - 0x3f */
514: opcode8h_0, dsp_undefined, dsp_undefined, dsp_undefined, opcode8h_0, dsp_andi, dsp_undefined, dsp_ori,
515: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
516: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
517: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
518: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
519: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
520: dsp_undefined, dsp_undefined, dsp_div, dsp_div, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
521: dsp_norm, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
1.1.1.11 root 522:
1.1.1.4 root 523: /* 0x40 - 0x7f */
524: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
525: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
526: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
527: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
528: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
529: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
530: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
531: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
532:
533: /* 0x80 - 0xbf */
534: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
1.1.1.11 root 535: dsp_lua, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
1.1.1.4 root 536: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
1.1.1.11 root 537: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
1.1.1.4 root 538: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
539: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
540: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
541: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
1.1.1.11 root 542:
1.1.1.4 root 543: /* 0xc0 - 0xff */
1.1.1.11 root 544: dsp_do_aa, dsp_rep_aa, dsp_do_aa, dsp_rep_aa, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
545: dsp_do_ea, dsp_rep_ea, dsp_do_ea, dsp_rep_ea, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
546: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
547: dsp_do_reg, dsp_rep_reg, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
548: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
549: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
550: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
551: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
1.1.1.4 root 552:
553: /* 0x100 - 0x13f */
1.1.1.6 root 554: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 555: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 556: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 557: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 558: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 559: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 560: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 561: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
562:
563: /* 0x140 - 0x17f */
564: dsp_bclr_aa, dsp_bset_aa, dsp_bclr_aa, dsp_bset_aa, dsp_jclr_aa, dsp_jset_aa, dsp_jclr_aa, dsp_jset_aa,
565: dsp_bclr_ea, dsp_bset_ea, dsp_bclr_ea, dsp_bset_ea, dsp_jclr_ea, dsp_jset_ea, dsp_jclr_ea, dsp_jset_ea,
566: dsp_bclr_pp, dsp_bset_pp, dsp_bclr_pp, dsp_bset_pp, dsp_jclr_pp, dsp_jset_pp, dsp_jclr_pp, dsp_jset_pp,
567: dsp_jclr_reg, dsp_jset_reg, dsp_bclr_reg, dsp_bset_reg, dsp_jmp_ea, dsp_jcc_ea, dsp_undefined, dsp_undefined,
568: dsp_bchg_aa, dsp_btst_aa, dsp_bchg_aa, dsp_btst_aa, dsp_jsclr_aa, dsp_jsset_aa, dsp_jsclr_aa, dsp_jsset_aa,
569: dsp_bchg_ea, dsp_btst_ea, dsp_bchg_ea, dsp_btst_ea, dsp_jsclr_ea, dsp_jsset_ea, dsp_jsclr_ea, dsp_jsset_ea,
570: dsp_bchg_pp, dsp_btst_pp, dsp_bchg_pp, dsp_btst_pp, dsp_jsclr_pp, dsp_jsset_pp, dsp_jsclr_pp, dsp_jsset_pp,
571: dsp_jsclr_reg, dsp_jsset_reg, dsp_bchg_reg, dsp_btst_reg, dsp_jsr_ea, dsp_jscc_ea, dsp_undefined, dsp_undefined,
572:
573: /* 0x180 - 0x1bf */
574: dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm,
1.1.1.11 root 575: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
576: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
577: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
578: dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm,
579: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
580: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
581: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
1.1.1.4 root 582:
583: /* 0x1c0 - 0x1ff */
1.1.1.11 root 584: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
585: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
586: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
587: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
588: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
589: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
590: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
591: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
1.1 root 592: };
593:
1.1.1.6 root 594: static const dsp_emul_t opcodes_parmove[16] = {
595: dsp_pm_0, dsp_pm_1, dsp_pm_2, dsp_pm_3, dsp_pm_4, dsp_pm_5, dsp_pm_5, dsp_pm_5,
596: dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8
1.1 root 597: };
598:
1.1.1.6 root 599: static const dsp_emul_t opcodes_alu[256] = {
1.1.1.4 root 600: /* 0x00 - 0x3f */
1.1.1.6 root 601: dsp_move , dsp_tfr_b_a, dsp_addr_b_a, dsp_tst_a, dsp_undefined, dsp_cmp_b_a, dsp_subr_a, dsp_cmpm_b_a,
602: dsp_undefined, dsp_tfr_a_b, dsp_addr_a_b, dsp_tst_b, dsp_undefined, dsp_cmp_a_b, dsp_subr_b, dsp_cmpm_a_b,
603: dsp_add_b_a, dsp_rnd_a, dsp_addl_b_a, dsp_clr_a, dsp_sub_b_a, dsp_undefined, dsp_subl_a, dsp_not_a,
604: dsp_add_a_b, dsp_rnd_b, dsp_addl_a_b, dsp_clr_b, dsp_sub_a_b, dsp_undefined, dsp_subl_b, dsp_not_b,
1.1.1.7 root 605: dsp_add_x_a, dsp_adc_x_a, dsp_asr_a, dsp_lsr_a, dsp_sub_x_a, dsp_sbc_x_a, dsp_abs_a, dsp_ror_a,
606: dsp_add_x_b, dsp_adc_x_b, dsp_asr_b, dsp_lsr_b, dsp_sub_x_b, dsp_sbc_x_b, dsp_abs_b, dsp_ror_b,
607: dsp_add_y_a, dsp_adc_y_a, dsp_asl_a, dsp_lsl_a, dsp_sub_y_a, dsp_sbc_y_a, dsp_neg_a, dsp_rol_a,
608: dsp_add_y_b, dsp_adc_y_b, dsp_asl_b, dsp_lsl_b, dsp_sub_y_b, dsp_sbc_y_b, dsp_neg_b, dsp_rol_b,
1.1.1.11 root 609:
1.1.1.4 root 610: /* 0x40 - 0x7f */
1.1.1.6 root 611: dsp_add_x0_a, dsp_tfr_x0_a, dsp_or_x0_a, dsp_eor_x0_a, dsp_sub_x0_a, dsp_cmp_x0_a, dsp_and_x0_a, dsp_cmpm_x0_a,
612: dsp_add_x0_b, dsp_tfr_x0_b, dsp_or_x0_b, dsp_eor_x0_b, dsp_sub_x0_b, dsp_cmp_x0_b, dsp_and_x0_b, dsp_cmpm_x0_b,
613: dsp_add_y0_a, dsp_tfr_y0_a, dsp_or_y0_a, dsp_eor_y0_a, dsp_sub_y0_a, dsp_cmp_y0_a, dsp_and_y0_a, dsp_cmpm_y0_a,
614: dsp_add_y0_b, dsp_tfr_y0_b, dsp_or_y0_b, dsp_eor_y0_b, dsp_sub_y0_b, dsp_cmp_y0_b, dsp_and_y0_b, dsp_cmpm_y0_b,
615: dsp_add_x1_a, dsp_tfr_x1_a, dsp_or_x1_a, dsp_eor_x1_a, dsp_sub_x1_a, dsp_cmp_x1_a, dsp_and_x1_a, dsp_cmpm_x1_a,
616: dsp_add_x1_b, dsp_tfr_x1_b, dsp_or_x1_b, dsp_eor_x1_b, dsp_sub_x1_b, dsp_cmp_x1_b, dsp_and_x1_b, dsp_cmpm_x1_b,
617: dsp_add_y1_a, dsp_tfr_y1_a, dsp_or_y1_a, dsp_eor_y1_a, dsp_sub_y1_a, dsp_cmp_y1_a, dsp_and_y1_a, dsp_cmpm_y1_a,
618: dsp_add_y1_b, dsp_tfr_y1_b, dsp_or_y1_b, dsp_eor_y1_b, dsp_sub_y1_b, dsp_cmp_y1_b, dsp_and_y1_b, dsp_cmpm_y1_b,
1.1.1.4 root 619:
620: /* 0x80 - 0xbf */
1.1.1.6 root 621: dsp_mpy_p_x0_x0_a, dsp_mpyr_p_x0_x0_a, dsp_mac_p_x0_x0_a, dsp_macr_p_x0_x0_a, dsp_mpy_m_x0_x0_a, dsp_mpyr_m_x0_x0_a, dsp_mac_m_x0_x0_a, dsp_macr_m_x0_x0_a,
622: dsp_mpy_p_x0_x0_b, dsp_mpyr_p_x0_x0_b, dsp_mac_p_x0_x0_b, dsp_macr_p_x0_x0_b, dsp_mpy_m_x0_x0_b, dsp_mpyr_m_x0_x0_b, dsp_mac_m_x0_x0_b, dsp_macr_m_x0_x0_b,
623: dsp_mpy_p_y0_y0_a, dsp_mpyr_p_y0_y0_a, dsp_mac_p_y0_y0_a, dsp_macr_p_y0_y0_a, dsp_mpy_m_y0_y0_a, dsp_mpyr_m_y0_y0_a, dsp_mac_m_y0_y0_a, dsp_macr_m_y0_y0_a,
624: dsp_mpy_p_y0_y0_b, dsp_mpyr_p_y0_y0_b, dsp_mac_p_y0_y0_b, dsp_macr_p_y0_y0_b, dsp_mpy_m_y0_y0_b, dsp_mpyr_m_y0_y0_b, dsp_mac_m_y0_y0_b, dsp_macr_m_y0_y0_b,
625: dsp_mpy_p_x1_x0_a, dsp_mpyr_p_x1_x0_a, dsp_mac_p_x1_x0_a, dsp_macr_p_x1_x0_a, dsp_mpy_m_x1_x0_a, dsp_mpyr_m_x1_x0_a, dsp_mac_m_x1_x0_a, dsp_macr_m_x1_x0_a,
626: dsp_mpy_p_x1_x0_b, dsp_mpyr_p_x1_x0_b, dsp_mac_p_x1_x0_b, dsp_macr_p_x1_x0_b, dsp_mpy_m_x1_x0_b, dsp_mpyr_m_x1_x0_b, dsp_mac_m_x1_x0_b, dsp_macr_m_x1_x0_b,
627: dsp_mpy_p_y1_y0_a, dsp_mpyr_p_y1_y0_a, dsp_mac_p_y1_y0_a, dsp_macr_p_y1_y0_a, dsp_mpy_m_y1_y0_a, dsp_mpyr_m_y1_y0_a, dsp_mac_m_y1_y0_a, dsp_macr_m_y1_y0_a,
628: dsp_mpy_p_y1_y0_b, dsp_mpyr_p_y1_y0_b, dsp_mac_p_y1_y0_b, dsp_macr_p_y1_y0_b, dsp_mpy_m_y1_y0_b, dsp_mpyr_m_y1_y0_b, dsp_mac_m_y1_y0_b, dsp_macr_m_y1_y0_b,
629:
630: /* 0xc0_m_ 0xff */
631: dsp_mpy_p_x0_y1_a, dsp_mpyr_p_x0_y1_a, dsp_mac_p_x0_y1_a, dsp_macr_p_x0_y1_a, dsp_mpy_m_x0_y1_a, dsp_mpyr_m_x0_y1_a, dsp_mac_m_x0_y1_a, dsp_macr_m_x0_y1_a,
632: dsp_mpy_p_x0_y1_b, dsp_mpyr_p_x0_y1_b, dsp_mac_p_x0_y1_b, dsp_macr_p_x0_y1_b, dsp_mpy_m_x0_y1_b, dsp_mpyr_m_x0_y1_b, dsp_mac_m_x0_y1_b, dsp_macr_m_x0_y1_b,
633: dsp_mpy_p_y0_x0_a, dsp_mpyr_p_y0_x0_a, dsp_mac_p_y0_x0_a, dsp_macr_p_y0_x0_a, dsp_mpy_m_y0_x0_a, dsp_mpyr_m_y0_x0_a, dsp_mac_m_y0_x0_a, dsp_macr_m_y0_x0_a,
634: dsp_mpy_p_y0_x0_b, dsp_mpyr_p_y0_x0_b, dsp_mac_p_y0_x0_b, dsp_macr_p_y0_x0_b, dsp_mpy_m_y0_x0_b, dsp_mpyr_m_y0_x0_b, dsp_mac_m_y0_x0_b, dsp_macr_m_y0_x0_b,
635: dsp_mpy_p_x1_y0_a, dsp_mpyr_p_x1_y0_a, dsp_mac_p_x1_y0_a, dsp_macr_p_x1_y0_a, dsp_mpy_m_x1_y0_a, dsp_mpyr_m_x1_y0_a, dsp_mac_m_x1_y0_a, dsp_macr_m_x1_y0_a,
636: dsp_mpy_p_x1_y0_b, dsp_mpyr_p_x1_y0_b, dsp_mac_p_x1_y0_b, dsp_macr_p_x1_y0_b, dsp_mpy_m_x1_y0_b, dsp_mpyr_m_x1_y0_b, dsp_mac_m_x1_y0_b, dsp_macr_m_x1_y0_b,
637: dsp_mpy_p_y1_x1_a, dsp_mpyr_p_y1_x1_a, dsp_mac_p_y1_x1_a, dsp_macr_p_y1_x1_a, dsp_mpy_m_y1_x1_a, dsp_mpyr_m_y1_x1_a, dsp_mac_m_y1_x1_a, dsp_macr_m_y1_x1_a,
638: dsp_mpy_p_y1_x1_b, dsp_mpyr_p_y1_x1_b, dsp_mac_p_y1_x1_b, dsp_macr_p_y1_x1_b, dsp_mpy_m_y1_x1_b, dsp_mpyr_m_y1_x1_b, dsp_mac_m_y1_x1_b, dsp_macr_m_y1_x1_b
1.1 root 639: };
640:
1.1.1.6 root 641: static const int registers_tcc[16][2] = {
1.1 root 642: {DSP_REG_B,DSP_REG_A},
643: {DSP_REG_A,DSP_REG_B},
644: {DSP_REG_NULL,DSP_REG_NULL},
645: {DSP_REG_NULL,DSP_REG_NULL},
646:
647: {DSP_REG_NULL,DSP_REG_NULL},
648: {DSP_REG_NULL,DSP_REG_NULL},
649: {DSP_REG_NULL,DSP_REG_NULL},
650: {DSP_REG_NULL,DSP_REG_NULL},
651:
652: {DSP_REG_X0,DSP_REG_A},
653: {DSP_REG_X0,DSP_REG_B},
654: {DSP_REG_Y0,DSP_REG_A},
655: {DSP_REG_Y0,DSP_REG_B},
1.1.1.2 root 656:
657: {DSP_REG_X1,DSP_REG_A},
658: {DSP_REG_X1,DSP_REG_B},
1.1 root 659: {DSP_REG_Y1,DSP_REG_A},
660: {DSP_REG_Y1,DSP_REG_B}
661: };
662:
1.1.1.6 root 663: static const int registers_mask[64] = {
1.1 root 664: 0, 0, 0, 0,
665: 24, 24, 24, 24,
666: 24, 24, 8, 8,
667: 24, 24, 24, 24,
1.1.1.11 root 668:
1.1 root 669: 16, 16, 16, 16,
670: 16, 16, 16, 16,
671: 16, 16, 16, 16,
672: 16, 16, 16, 16,
1.1.1.11 root 673:
1.1 root 674: 16, 16, 16, 16,
675: 16, 16, 16, 16,
676: 0, 0, 0, 0,
677: 0, 0, 0, 0,
678:
679: 0, 0, 0, 0,
680: 0, 0, 0, 0,
681: 0, 16, 8, 6,
1.1.1.4 root 682: 16, 16, 16, 16
683: };
684:
1.1.1.6 root 685: static const dsp_interrupt_t dsp_interrupt[12] = {
1.1.1.5 root 686: {DSP_INTER_RESET , 0x00, 0, "Reset"},
687: {DSP_INTER_ILLEGAL , 0x3e, 0, "Illegal"},
688: {DSP_INTER_STACK_ERROR , 0x02, 0, "Stack Error"},
689: {DSP_INTER_TRACE , 0x04, 0, "Trace"},
690: {DSP_INTER_SWI , 0x06, 0, "Swi"},
691: {DSP_INTER_HOST_COMMAND , 0xff, 1, "Host Command"},
692: {DSP_INTER_HOST_RCV_DATA, 0x20, 1, "Host receive"},
693: {DSP_INTER_HOST_TRX_DATA, 0x22, 1, "Host transmit"},
694: {DSP_INTER_SSI_RCV_DATA_E, 0x0e, 2, "SSI receive with exception"},
695: {DSP_INTER_SSI_RCV_DATA , 0x0c, 2, "SSI receive"},
696: {DSP_INTER_SSI_TRX_DATA_E, 0x12, 2, "SSI transmit with exception"},
697: {DSP_INTER_SSI_TRX_DATA , 0x10, 2, "SSI tramsmit"}
1.1.1.4 root 698: };
699:
1.1.1.13! root 700: static struct {
! 701: int limit;
! 702: int count;
! 703: Uint32 inst;
! 704: Uint16 pc;
! 705: } dsp_error;
! 706:
1.1 root 707:
708: /**********************************
709: * Emulator kernel
710: **********************************/
711:
1.1.1.6 root 712: void dsp56k_init_cpu(void)
1.1 root 713: {
1.1.1.6 root 714: dsp56k_disasm_init();
715: isDsp_in_disasm_mode = false;
1.1.1.2 root 716: start_time = SDL_GetTicks();
1.1.1.13! root 717: memset(&dsp_error, 0, sizeof(dsp_error));
! 718: dsp_error.limit = 1;
1.1.1.2 root 719: num_inst = 0;
1.1 root 720: }
721:
1.1.1.6 root 722: /**
723: * Execute one instruction in trace mode at a given PC address.
724: * */
1.1.1.9 root 725: Uint16 dsp56k_execute_one_disasm_instruction(FILE *out, Uint16 pc)
1.1.1.6 root 726: {
727: dsp_core_t *ptr1, *ptr2;
728: static dsp_core_t dsp_core_save;
1.1.1.8 root 729: Uint16 instruction_length;
1.1.1.6 root 730:
731: ptr1 = &dsp_core;
732: ptr2 = &dsp_core_save;
733:
734: /* Set DSP in disasm mode */
735: isDsp_in_disasm_mode = true;
736:
737: /* Save DSP context before executing instruction */
738: memcpy(ptr2, ptr1, sizeof(dsp_core));
739:
740: /* execute and disasm instruction */
741: dsp_core.pc = pc;
742:
743: /* Disasm instruction */
1.1.1.12 root 744: instruction_length = dsp56k_disasm(DSP_DISASM_MODE, out) - 1;
1.1.1.6 root 745:
746: /* Execute instruction at address given in parameter to get the number of cycles it takes */
747: dsp56k_execute_instruction();
748:
1.1.1.9 root 749: fprintf(out, "%s", dsp56k_getInstructionText());
1.1.1.6 root 750:
751: /* Restore DSP context after executing instruction */
752: memcpy(ptr1, ptr2, sizeof(dsp_core));
1.1.1.11 root 753:
1.1.1.6 root 754: /* Unset DSP in disasm mode */
755: isDsp_in_disasm_mode = false;
756:
757: return instruction_length;
758: }
759:
1.1.1.4 root 760: void dsp56k_execute_instruction(void)
1.1 root 761: {
1.1.1.2 root 762: Uint32 value;
1.1.1.6 root 763: Uint32 disasm_return = 0;
1.1.1.5 root 764: disasm_memory_ptr = 0;
765:
1.1.1.7 root 766: /* Initialise the number of access to the external memory for this instruction */
1.1.1.9 root 767: access_to_ext_memory = 0;
1.1.1.11 root 768:
769: /* Init the indirect AGU move instruction flag */
770: dsp_core.agu_move_indirect_instr = 0;
771:
1.1 root 772: /* Decode and execute current instruction */
1.1.1.6 root 773: cur_inst = read_memory_p(dsp_core.pc);
1.1.1.11 root 774:
1.1.1.7 root 775: /* Initialize instruction size and cycle counter */
776: cur_inst_len = 1;
1.1.1.6 root 777: dsp_core.instr_cycle = 2;
1.1 root 778:
1.1.1.6 root 779: /* Disasm current instruction ? (trace mode only) */
1.1.1.11 root 780: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
1.1.1.6 root 781: /* Call dsp56k_disasm only when DSP is called in trace mode */
782: if (isDsp_in_disasm_mode == false) {
1.1.1.12 root 783: disasm_return = dsp56k_disasm(DSP_TRACE_MODE, TraceFile);
1.1.1.11 root 784:
1.1.1.6 root 785: if (disasm_return != 0 && LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG)) {
786: /* DSP regs trace enabled only if DSP DISASM is enabled */
787: dsp56k_disasm_reg_save();
788: }
789: }
790: }
1.1.1.11 root 791:
1.1.1.4 root 792: if (cur_inst < 0x100000) {
793: value = (cur_inst >> 11) & (BITMASK(6) << 3);
794: value += (cur_inst >> 5) & BITMASK(3);
1.1 root 795: opcodes8h[value]();
796: } else {
1.1.1.6 root 797: /* Do parallel move read */
798: opcodes_parmove[(cur_inst>>20) & BITMASK(4)]();
799: }
800:
1.1.1.7 root 801: /* Add the waitstate due to external memory access */
1.1.1.9 root 802: /* (2 extra cycles per extra access to the external memory after the first one */
803: if (access_to_ext_memory != 0) {
804: value = access_to_ext_memory & 1;
805: value += (access_to_ext_memory & 2) >> 1;
806: value += (access_to_ext_memory & 4) >> 2;
1.1.1.11 root 807:
1.1.1.9 root 808: if (value > 1)
809: dsp_core.instr_cycle += (value - 1) * 2;
810: }
811:
1.1.1.6 root 812: /* Disasm current instruction ? (trace mode only) */
813: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
814: /* Display only when DSP is called in trace mode */
815: if (isDsp_in_disasm_mode == false) {
816: if (disasm_return != 0) {
1.1.1.12 root 817: fprintf(TraceFile, "%s", dsp56k_getInstructionText());
1.1.1.11 root 818:
1.1.1.6 root 819: /* DSP regs trace enabled only if DSP DISASM is enabled */
820: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG))
1.1.1.12 root 821: dsp56k_disasm_reg_compare(TraceFile);
1.1.1.6 root 822:
823: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM)) {
824: /* 1 memory change to display ? */
825: if (disasm_memory_ptr == 1)
1.1.1.12 root 826: fprintf(TraceFile, "\t%s\n", str_disasm_memory[0]);
1.1.1.6 root 827: /* 2 memory changes to display ? */
828: else if (disasm_memory_ptr == 2) {
1.1.1.12 root 829: fprintf(TraceFile, "\t%s\n", str_disasm_memory[0]);
830: fprintf(TraceFile, "\t%s\n", str_disasm_memory[1]);
1.1.1.6 root 831: }
832: }
833: }
834: }
1.1 root 835: }
836:
1.1.1.4 root 837: /* Process the PC */
838: dsp_postexecute_update_pc();
1.1 root 839:
1.1.1.4 root 840: /* Process Interrupts */
1.1 root 841: dsp_postexecute_interrupts();
842:
1.1.1.4 root 843: #if DSP_COUNT_IPS
844: ++num_inst;
845: if ((num_inst & 63) == 0) {
846: /* Evaluate time after <N> instructions have been executed to avoid asking too frequently */
847: Uint32 cur_time = SDL_GetTicks();
848: if (cur_time-start_time>1000) {
849: fprintf(stderr, "Dsp: %d i/s\n", (num_inst*1000)/(cur_time-start_time));
850: start_time=cur_time;
851: num_inst=0;
852: }
853: }
854: #endif
1.1 root 855: }
856:
857: /**********************************
858: * Update the PC
859: **********************************/
860:
861: static void dsp_postexecute_update_pc(void)
862: {
863: /* When running a REP, PC must stay on the current instruction */
1.1.1.6 root 864: if (dsp_core.loop_rep) {
1.1.1.11 root 865: /* Is PC on the instruction to repeat ? */
1.1.1.6 root 866: if (dsp_core.pc_on_rep==0) {
867: --dsp_core.registers[DSP_REG_LC];
868: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1 root 869:
1.1.1.6 root 870: if (dsp_core.registers[DSP_REG_LC] > 0) {
1.1.1.7 root 871: cur_inst_len = 0; /* Stay on this instruction */
1.1 root 872: } else {
1.1.1.6 root 873: dsp_core.loop_rep = 0;
874: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[DSP_REG_LCSAVE];
1.1 root 875: }
876: } else {
877: /* Init LC at right value */
1.1.1.6 root 878: if (dsp_core.registers[DSP_REG_LC] == 0) {
879: dsp_core.registers[DSP_REG_LC] = 0x010000;
1.1 root 880: }
1.1.1.6 root 881: dsp_core.pc_on_rep = 0;
1.1 root 882: }
883: }
884:
885: /* Normal execution, go to next instruction */
1.1.1.6 root 886: dsp_core.pc += cur_inst_len;
1.1 root 887:
888: /* When running a DO loop, we test the end of loop with the */
889: /* updated PC, pointing to last instruction of the loop */
1.1.1.6 root 890: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_LF)) {
1.1 root 891:
892: /* Did we execute the last instruction in loop ? */
1.1.1.11 root 893: if (dsp_core.pc == dsp_core.registers[DSP_REG_LA] + 1) {
894: if (dsp_core.registers[DSP_REG_LC] == 1) {
895: /* end of the loop */
1.1.1.4 root 896: Uint32 saved_pc, saved_sr;
897:
898: dsp_stack_pop(&saved_pc, &saved_sr);
1.1.1.10 root 899: dsp_core.registers[DSP_REG_SR] &= 0x7fff;
1.1.1.6 root 900: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
901: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
1.1 root 902: } else {
903: /* Loop one more time */
1.1.1.11 root 904: --dsp_core.registers[DSP_REG_LC];
905: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.6 root 906: dsp_core.pc = dsp_core.registers[DSP_REG_SSH];
1.1 root 907: }
908: }
909: }
910: }
911:
912: /**********************************
913: * Interrupts
914: **********************************/
915:
1.1.1.5 root 916: /* Post a new interrupt to the interrupt table */
917: void dsp_add_interrupt(Uint16 inter)
918: {
919: /* detect if this interrupt is used or not */
1.1.1.6 root 920: if (dsp_core.interrupt_ipl[inter] == -1)
1.1.1.5 root 921: return;
922:
923: /* add this interrupt to the pending interrupts table */
1.1.1.11 root 924: if (dsp_core.interrupt_isPending[inter] == 0) {
1.1.1.6 root 925: dsp_core.interrupt_isPending[inter] = 1;
926: dsp_core.interrupt_counter ++;
1.1.1.5 root 927: }
928: }
929:
930: static void dsp_setInterruptIPL(Uint32 value)
931: {
932: Uint32 ipl_ssi, ipl_hi, i;
933:
934: ipl_ssi = ((value >> 12) & 3) - 1;
935: ipl_hi = ((value >> 10) & 3) - 1;
936:
937: /* set IPL_HI */
1.1.1.7 root 938: for (i=5; i<8; i++) {
1.1.1.6 root 939: dsp_core.interrupt_ipl[i] = ipl_hi;
1.1.1.5 root 940: }
941:
942: /* set IPL_SSI */
1.1.1.7 root 943: for (i=8; i<12; i++) {
1.1.1.6 root 944: dsp_core.interrupt_ipl[i] = ipl_ssi;
1.1.1.5 root 945: }
946: }
947:
1.1 root 948: static void dsp_postexecute_interrupts(void)
949: {
1.1.1.5 root 950: Uint32 index, instr, i;
951: Sint32 ipl_to_raise, ipl_sr;
1.1.1.4 root 952:
953: /* REP is not interruptible */
1.1.1.6 root 954: if (dsp_core.loop_rep) {
1.1.1.4 root 955: return;
956: }
957:
958: /* A fast interrupt can not be interrupted. */
1.1.1.6 root 959: if (dsp_core.interrupt_state == DSP_INTERRUPT_DISABLED) {
1.1.1.5 root 960:
1.1.1.6 root 961: switch (dsp_core.interrupt_pipeline_count) {
1.1.1.5 root 962: case 5:
1.1.1.6 root 963: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 964: return;
965: case 4:
966: /* Prefetch interrupt instruction 1 */
1.1.1.6 root 967: dsp_core.interrupt_save_pc = dsp_core.pc;
968: dsp_core.pc = dsp_core.interrupt_instr_fetch;
1.1.1.5 root 969:
970: /* is it a LONG interrupt ? */
1.1.1.6 root 971: instr = read_memory_p(dsp_core.interrupt_instr_fetch);
1.1.1.5 root 972: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1.1.1.6 root 973: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
1.1.1.11 root 974: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.6 root 975: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1.1.1.5 root 976: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
977: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1.1.1.6 root 978: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1.1.1.5 root 979: }
1.1.1.6 root 980: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 981: return;
982: case 3:
1.1.1.11 root 983: /* Prefetch interrupt instruction 2, if first one was single word */
1.1.1.6 root 984: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+1) {
985: instr = read_memory_p(dsp_core.pc);
1.1.1.5 root 986: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1.1.1.6 root 987: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
1.1.1.11 root 988: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.6 root 989: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1.1.1.5 root 990: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
991: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1.1.1.6 root 992: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1.1.1.5 root 993: }
1.1.1.11 root 994: dsp_core.interrupt_pipeline_count --;
995: return;
996: }
997: dsp_core.interrupt_pipeline_count --;
998: /* First instruction was 2 word. Fall through */
1.1.1.5 root 999: case 2:
1000: /* 1 instruction executed after interrupt */
1001: /* before re enable interrupts */
1002: /* Was it a FAST interrupt ? */
1.1.1.6 root 1003: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+2) {
1004: dsp_core.pc = dsp_core.interrupt_save_pc;
1.1.1.5 root 1005: }
1.1.1.6 root 1006: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 1007: return;
1008: case 1:
1009: /* Last instruction executed after interrupt */
1010: /* before re enable interrupts */
1.1.1.6 root 1011: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 1012: return;
1013: case 0:
1014: /* Re enable interrupts */
1.1.1.6 root 1015: /* All 6 instruction are done, Interrupts can be enabled again */
1016: dsp_core.interrupt_save_pc = -1;
1017: dsp_core.interrupt_instr_fetch = -1;
1018: dsp_core.interrupt_state = DSP_INTERRUPT_NONE;
1019: break;
1.1.1.4 root 1020: }
1021: }
1.1 root 1022:
1.1.1.4 root 1023: /* Trace Interrupt ? */
1.1.1.6 root 1024: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_T)) {
1.1.1.5 root 1025: dsp_add_interrupt(DSP_INTER_TRACE);
1.1.1.4 root 1026: }
1027:
1028: /* No interrupt to execute */
1.1.1.6 root 1029: if (dsp_core.interrupt_counter == 0) {
1.1.1.4 root 1030: return;
1.1 root 1031: }
1032:
1.1.1.5 root 1033: /* search for an interrupt */
1.1.1.6 root 1034: ipl_sr = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_I0) & BITMASK(2);
1.1.1.5 root 1035: index = 0xffff;
1036: ipl_to_raise = -1;
1037:
1038: /* Arbitrate between all pending interrupts */
1039: for (i=0; i<12; i++) {
1.1.1.6 root 1040: if (dsp_core.interrupt_isPending[i] == 1) {
1.1.1.5 root 1041:
1042: /* level 3 interrupt ? */
1.1.1.6 root 1043: if (dsp_core.interrupt_ipl[i] == 3) {
1.1.1.5 root 1044: index = i;
1045: break;
1046: }
1.1 root 1047:
1.1.1.5 root 1048: /* level 0, 1 ,2 interrupt ? */
1049: /* if interrupt is masked in SR, don't process it */
1.1.1.6 root 1050: if (dsp_core.interrupt_ipl[i] < ipl_sr)
1.1.1.5 root 1051: continue;
1.1 root 1052:
1.1.1.5 root 1053: /* if interrupt is lower or equal than current arbitrated interrupt */
1.1.1.6 root 1054: if (dsp_core.interrupt_ipl[i] <= ipl_to_raise)
1.1.1.5 root 1055: continue;
1056:
1057: /* save current arbitrated interrupt */
1058: index = i;
1.1.1.6 root 1059: ipl_to_raise = dsp_core.interrupt_ipl[i];
1.1 root 1060: }
1061: }
1.1.1.4 root 1062:
1.1.1.5 root 1063: /* If there's no interrupt to process, return */
1064: if (index == 0xffff) {
1.1.1.4 root 1065: return;
1066: }
1067:
1.1.1.5 root 1068: /* remove this interrupt from the pending interrupts table */
1.1.1.6 root 1069: dsp_core.interrupt_isPending[index] = 0;
1070: dsp_core.interrupt_counter --;
1.1.1.5 root 1071:
1072: /* process arbritrated interrupt */
1.1.1.6 root 1073: ipl_to_raise = dsp_core.interrupt_ipl[index] + 1;
1.1.1.5 root 1074: if (ipl_to_raise > 3) {
1075: ipl_to_raise = 3;
1076: }
1077:
1.1.1.6 root 1078: dsp_core.interrupt_instr_fetch = dsp_interrupt[index].vectorAddr;
1079: dsp_core.interrupt_pipeline_count = 5;
1080: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1081: dsp_core.interrupt_IplToRaise = ipl_to_raise;
1082:
1083: LOG_TRACE(TRACE_DSP_INTERRUPT, "Dsp interrupt: %s\n", dsp_interrupt[index].name);
1.1.1.5 root 1084:
1085: /* SSI receive data with exception ? */
1.1.1.6 root 1086: if (dsp_core.interrupt_instr_fetch == 0xe) {
1087: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_ROE);
1.1.1.4 root 1088: }
1089:
1.1.1.5 root 1090: /* SSI transmit data with exception ? */
1.1.1.6 root 1091: else if (dsp_core.interrupt_instr_fetch == 0x12) {
1092: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_TUE);
1.1.1.4 root 1093: }
1094:
1095: /* host command ? */
1.1.1.6 root 1096: else if (dsp_core.interrupt_instr_fetch == 0xff) {
1.1.1.4 root 1097: /* Clear HC and HCP interrupt */
1.1.1.6 root 1098: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] &= 0xff - (1<<DSP_HOST_HSR_HCP);
1.1.1.11 root 1099: dsp_core.hostport[CPU_HOST_CVR] &= 0xff - (1<<CPU_HOST_CVR_HC);
1.1.1.4 root 1100:
1.1.1.6 root 1101: dsp_core.interrupt_instr_fetch = dsp_core.hostport[CPU_HOST_CVR] & BITMASK(5);
1.1.1.11 root 1102: dsp_core.interrupt_instr_fetch *= 2;
1.1.1.4 root 1103: }
1.1 root 1104: }
1105:
1106: /**********************************
1107: * Set/clear ccr bits
1108: **********************************/
1109:
1110: /* reg0 has bits 55..48 */
1111: /* reg1 has bits 47..24 */
1112: /* reg2 has bits 23..0 */
1113:
1.1.1.11 root 1114: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2)
1.1.1.6 root 1115: {
1116: Uint32 scaling, value_e, value_u;
1.1.1.4 root 1117:
1.1.1.6 root 1118: /* Initialize SR register */
1119: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E) | (1<<DSP_SR_U) | (1<<DSP_SR_N) | (1<<DSP_SR_Z));
1.1.1.4 root 1120:
1.1.1.6 root 1121: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
1.1 root 1122: switch(scaling) {
1123: case 0:
1.1.1.6 root 1124: /* Extension Bit (E) */
1125: value_e = (reg0<<1) + (reg1>>23);
1126: if ((value_e != 0) && (value_e != BITMASK(9)))
1127: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1128:
1129: /* Unnormalized bit (U) */
1.1.1.11 root 1130: if ((reg1 & 0xc00000) == 0 || (reg1 & 0xc00000) == 0xc00000)
1.1.1.6 root 1131: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1132: break;
1133: case 1:
1.1.1.6 root 1134: /* Extension Bit (E) */
1135: if ((reg0 != 0) && (reg0 != BITMASK(8)))
1136: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1137:
1138: /* Unnormalized bit (U) */
1139: value_u = ((reg0<<1) + (reg1>>23)) & 3;
1.1.1.11 root 1140: if (value_u == 0 || value_u == 3)
1.1.1.6 root 1141: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1142: break;
1143: case 2:
1.1.1.6 root 1144: /* Extension Bit (E) */
1145: value_e = (reg0<<2) + (reg1>>22);
1146: if ((value_e != 0) && (value_e != BITMASK(10)))
1147: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1148:
1149: /* Unnormalized bit (U) */
1.1.1.11 root 1150: if ((reg1 & 0x600000) == 0 || (reg1 & 0x600000) == 0x600000)
1.1.1.6 root 1151: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1152: break;
1153: default:
1154: return;
1155: break;
1156: }
1157:
1.1.1.6 root 1158: /* Zero Flag (Z) */
1159: if ((reg1 == 0) && (reg2 == 0) && (reg0 == 0))
1160: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_Z;
1.1.1.4 root 1161:
1.1.1.6 root 1162: /* Negative Flag (N) */
1163: dsp_core.registers[DSP_REG_SR] |= (reg0>>4) & 0x8;
1.1 root 1164: }
1165:
1166: /**********************************
1167: * Read/Write memory functions
1168: **********************************/
1169:
1.1.1.2 root 1170: static Uint32 read_memory_disasm(int space, Uint16 address)
1.1 root 1171: {
1.1.1.4 root 1172: /* Internal RAM ? */
1173: if (address<0x100) {
1.1.1.6 root 1174: return dsp_core.ramint[space][address] & BITMASK(24);
1.1.1.4 root 1175: }
1.1 root 1176:
1.1.1.4 root 1177: if (space==DSP_SPACE_P) {
1178: return read_memory_p(address);
1.1 root 1179: }
1180:
1.1.1.4 root 1181: /* Internal ROM? */
1.1.1.6 root 1182: if ((dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) &&
1.1.1.4 root 1183: (address<0x200)) {
1.1.1.6 root 1184: return dsp_core.rom[space][address] & BITMASK(24);
1.1.1.4 root 1185: }
1186:
1187: /* Peripheral address ? */
1188: if (address >= 0xffc0) {
1.1.1.6 root 1189: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_HOST_HTX)) {
1190: return dsp_core.dsp_host_htx;
1.1.1.4 root 1191: }
1192: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_SSI_TX)) {
1.1.1.6 root 1193: return dsp_core.ssi.transmit_value;
1.1.1.4 root 1194: }
1.1.1.6 root 1195: return dsp_core.periph[space][address-0xffc0] & BITMASK(24);
1.1.1.4 root 1196: }
1197:
1198: /* Falcon: External RAM, map X to upper 16K of matching space in Y,P */
1199: address &= (DSP_RAMSIZE>>1) - 1;
1200: if (space == DSP_SPACE_X) {
1201: address += DSP_RAMSIZE>>1;
1202: }
1203:
1204: /* Falcon: External RAM, finally map X,Y to P */
1.1.1.6 root 1205: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1.1 root 1206: }
1207:
1.1.1.4 root 1208: static inline Uint32 read_memory_p(Uint16 address)
1209: {
1210: /* Internal RAM ? */
1.1.1.7 root 1211: if (address < 0x200) {
1.1.1.6 root 1212: return dsp_core.ramint[DSP_SPACE_P][address] & BITMASK(24);
1.1.1.4 root 1213: }
1214:
1.1.1.9 root 1215: /* Access to the external P memory */
1216: access_to_ext_memory |= 1 << EXT_P_MEMORY;
1.1.1.7 root 1217:
1.1.1.4 root 1218: /* External RAM, mask address to available ram size */
1.1.1.6 root 1219: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1.1.1.4 root 1220: }
1221:
1.1.1.2 root 1222: static Uint32 read_memory(int space, Uint16 address)
1.1 root 1223: {
1.1.1.4 root 1224: Uint32 value;
1.1 root 1225:
1.1.1.4 root 1226: /* Internal RAM ? */
1227: if (address < 0x100) {
1.1.1.6 root 1228: return dsp_core.ramint[space][address] & BITMASK(24);
1.1.1.4 root 1229: }
1.1 root 1230:
1.1.1.4 root 1231: if (space == DSP_SPACE_P) {
1232: return read_memory_p(address);
1233: }
1234:
1235: /* Internal ROM ? */
1236: if (address < 0x200) {
1.1.1.6 root 1237: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1238: return dsp_core.rom[space][address] & BITMASK(24);
1.1.1.4 root 1239: }
1240: }
1241:
1242: /* Peripheral address ? */
1243: if (address >= 0xffc0) {
1.1.1.6 root 1244: value = dsp_core.periph[space][address-0xffc0] & BITMASK(24);
1.1.1.4 root 1245: if (space == DSP_SPACE_X) {
1246: if (address == 0xffc0+DSP_HOST_HRX) {
1.1.1.6 root 1247: value = dsp_core.dsp_host_rtx;
1248: dsp_core_hostport_dspread();
1.1.1.11 root 1249: }
1.1.1.4 root 1250: else if (address == 0xffc0+DSP_SSI_RX) {
1.1.1.6 root 1251: value = dsp_core_ssi_readRX();
1.1 root 1252: }
1.1.1.4 root 1253: }
1254: return value;
1.1 root 1255: }
1256:
1.1.1.9 root 1257: /* Falcon: External X or Y RAM access */
1.1.1.4 root 1258: address &= (DSP_RAMSIZE>>1) - 1;
1259:
1260: if (space == DSP_SPACE_X) {
1.1.1.9 root 1261: /* Map X to upper 16K of matching space in Y,P */
1.1.1.4 root 1262: address += DSP_RAMSIZE>>1;
1.1.1.9 root 1263:
1264: /* Set one access to the X external memory */
1265: access_to_ext_memory |= 1 << EXT_X_MEMORY;
1266: }
1267: else {
1268: /* Access to the Y external memory */
1269: access_to_ext_memory |= 1 << EXT_Y_MEMORY;
1.1.1.4 root 1270: }
1271:
1.1.1.9 root 1272:
1.1.1.4 root 1273: /* Falcon: External RAM, finally map X,Y to P */
1.1.1.6 root 1274: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1275: }
1276:
1277: static inline void write_memory(int space, Uint16 address, Uint32 value)
1278: {
1.1.1.12 root 1279: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM))
1.1.1.6 root 1280: write_memory_disasm(space, address, value);
1.1.1.11 root 1281: else
1.1.1.6 root 1282: write_memory_raw(space, address, value);
1.1 root 1283: }
1284:
1.1.1.4 root 1285: static void write_memory_raw(int space, Uint16 address, Uint32 value)
1.1 root 1286: {
1287: value &= BITMASK(24);
1288:
1.1.1.4 root 1289: /* Peripheral address ? */
1290: if (address >= 0xffc0) {
1291: if (space == DSP_SPACE_X) {
1292: switch(address-0xffc0) {
1293: case DSP_HOST_HTX:
1.1.1.6 root 1294: dsp_core.dsp_host_htx = value;
1295: dsp_core_hostport_dspwrite();
1.1.1.4 root 1296: break;
1297: case DSP_HOST_HCR:
1.1.1.13! root 1298: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] = value & 0x1f;
1.1.1.4 root 1299: /* Set HF3 and HF2 accordingly on the host side */
1.1.1.6 root 1300: dsp_core.hostport[CPU_HOST_ISR] &=
1.1.1.4 root 1301: BITMASK(8)-((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1.1.1.6 root 1302: dsp_core.hostport[CPU_HOST_ISR] |=
1303: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] & ((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1.1.1.4 root 1304: break;
1305: case DSP_HOST_HSR:
1306: /* Read only */
1307: break;
1308: case DSP_SSI_CRA:
1309: case DSP_SSI_CRB:
1.1.1.6 root 1310: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1311: dsp_core_ssi_configure(address-0xffc0, value);
1.1.1.4 root 1312: break;
1313: case DSP_SSI_TSR:
1.1.1.6 root 1314: dsp_core_ssi_writeTSR();
1.1.1.4 root 1315: break;
1316: case DSP_SSI_TX:
1.1.1.6 root 1317: dsp_core_ssi_writeTX(value);
1.1.1.4 root 1318: break;
1.1.1.5 root 1319: case DSP_IPR:
1.1.1.6 root 1320: dsp_core.periph[DSP_SPACE_X][DSP_IPR] = value;
1.1.1.5 root 1321: dsp_setInterruptIPL(value);
1322: break;
1323: case DSP_PCD:
1.1.1.6 root 1324: dsp_core.periph[DSP_SPACE_X][DSP_PCD] = value;
1325: dsp_core_setPortCDataRegister(value);
1.1.1.5 root 1326: break;
1.1.1.4 root 1327: default:
1.1.1.6 root 1328: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1.1.1.4 root 1329: break;
1.1 root 1330: }
1.1.1.4 root 1331: return;
1.1.1.11 root 1332: }
1.1.1.4 root 1333: else if (space == DSP_SPACE_Y) {
1.1.1.6 root 1334: dsp_core.periph[DSP_SPACE_Y][address-0xffc0] = value;
1.1.1.4 root 1335: return;
1336: }
1337: }
1.1.1.11 root 1338:
1.1.1.4 root 1339: /* Internal RAM ? */
1340: if (address < 0x100) {
1.1.1.6 root 1341: dsp_core.ramint[space][address] = value;
1.1.1.4 root 1342: return;
1343: }
1.1.1.2 root 1344:
1.1.1.4 root 1345: /* Internal ROM ? */
1346: if (address < 0x200) {
1347: if (space != DSP_SPACE_P) {
1.1.1.6 root 1348: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1.1.1.2 root 1349: /* Can not write to ROM space */
1.1 root 1350: return;
1351: }
1.1.1.4 root 1352: }
1353: else {
1354: /* Space P RAM */
1.1.1.6 root 1355: dsp_core.ramint[DSP_SPACE_P][address] = value;
1.1.1.4 root 1356: return;
1357: }
1.1 root 1358: }
1359:
1.1.1.9 root 1360: /* Access to X, Y or P external RAM */
1.1.1.4 root 1361:
1.1.1.9 root 1362: if (space == DSP_SPACE_P) {
1363: /* Access to the P external RAM */
1364: access_to_ext_memory |= 1 << EXT_P_MEMORY;
1365: }
1366: else {
1.1.1.4 root 1367: address &= (DSP_RAMSIZE>>1) - 1;
1368:
1.1.1.9 root 1369: if (space == DSP_SPACE_X) {
1370: /* Access to the X external RAM */
1371: /* map X to upper 16K of matching space in Y,P */
1372: address += DSP_RAMSIZE>>1;
1373: access_to_ext_memory |= 1;
1374: }
1375: else {
1376: /* Access to the Y external RAM */
1377: access_to_ext_memory |= 1 << EXT_Y_MEMORY;
1378: }
1.1.1.4 root 1379: }
1380:
1381: /* Falcon: External RAM, map X,Y to P */
1.1.1.6 root 1382: dsp_core.ramext[address & (DSP_RAMSIZE-1)] = value;
1.1.1.2 root 1383: }
1384:
1.1.1.4 root 1385: static void write_memory_disasm(int space, Uint16 address, Uint32 value)
1.1.1.2 root 1386: {
1.1.1.4 root 1387: Uint32 oldvalue, curvalue;
1388: Uint8 space_c = 'p';
1389:
1.1.1.2 root 1390: value &= BITMASK(24);
1.1.1.6 root 1391: oldvalue = read_memory_disasm(space, address);
1.1.1.2 root 1392:
1393: write_memory_raw(space,address,value);
1394:
1.1 root 1395: switch(space) {
1396: case DSP_SPACE_X:
1.1.1.4 root 1397: space_c = 'x';
1.1 root 1398: break;
1399: case DSP_SPACE_Y:
1.1.1.4 root 1400: space_c = 'y';
1401: break;
1402: default:
1.1 root 1403: break;
1404: }
1.1.1.4 root 1405:
1.1.1.6 root 1406: curvalue = read_memory_disasm(space, address);
1.1.1.5 root 1407: sprintf(str_disasm_memory[disasm_memory_ptr],"Mem: %c:0x%04x 0x%06x -> 0x%06x", space_c, address, oldvalue, curvalue);
1408: disasm_memory_ptr ++;
1.1 root 1409: }
1410:
1.1.1.4 root 1411: static void dsp_write_reg(Uint32 numreg, Uint32 value)
1412: {
1.1.1.5 root 1413: Uint32 stack_error;
1.1.1.4 root 1414:
1.1.1.7 root 1415: switch (numreg) {
1416: case DSP_REG_A:
1417: dsp_core.registers[DSP_REG_A0] = 0;
1.1.1.11 root 1418: dsp_core.registers[DSP_REG_A1] = value & BITMASK(24);
1.1.1.7 root 1419: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
1420: break;
1421: case DSP_REG_B:
1422: dsp_core.registers[DSP_REG_B0] = 0;
1.1.1.11 root 1423: dsp_core.registers[DSP_REG_B1] = value & BITMASK(24);
1.1.1.7 root 1424: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
1425: break;
1.1.1.11 root 1426: case DSP_REG_R0:
1427: case DSP_REG_R1:
1428: case DSP_REG_R2:
1429: case DSP_REG_R3:
1430: case DSP_REG_R4:
1431: case DSP_REG_R5:
1432: case DSP_REG_R6:
1433: case DSP_REG_R7:
1434: case DSP_REG_N0:
1435: case DSP_REG_N1:
1436: case DSP_REG_N2:
1437: case DSP_REG_N3:
1438: case DSP_REG_N4:
1439: case DSP_REG_N5:
1440: case DSP_REG_N6:
1441: case DSP_REG_N7:
1442: case DSP_REG_M0:
1443: case DSP_REG_M1:
1444: case DSP_REG_M2:
1445: case DSP_REG_M3:
1446: case DSP_REG_M4:
1447: case DSP_REG_M5:
1448: case DSP_REG_M6:
1449: case DSP_REG_M7:
1450: dsp_core.registers[numreg] = value & BITMASK(16);
1451: break;
1.1.1.7 root 1452: case DSP_REG_OMR:
1453: dsp_core.registers[DSP_REG_OMR] = value & 0xc7;
1454: break;
1455: case DSP_REG_SR:
1456: dsp_core.registers[DSP_REG_SR] = value & 0xaf7f;
1457: break;
1458: case DSP_REG_SP:
1.1.1.8 root 1459: stack_error = dsp_core.registers[DSP_REG_SP] & (3<<DSP_SP_SE);
1460: if ((stack_error==0) && (value & (3<<DSP_SP_SE))) {
1461: /* Stack underflow or overflow detected, raise interrupt */
1.1.1.7 root 1462: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.9 root 1463: dsp_core.registers[DSP_REG_SP] = value & (3<<DSP_SP_SE);
1.1.1.7 root 1464: if (!isDsp_in_disasm_mode)
1.1.1.8 root 1465: fprintf(stderr,"Dsp: Stack Overflow or Underflow\n");
1.1.1.10 root 1466: if (ExceptionDebugMask & EXCEPT_DSP)
1.1.1.9 root 1467: DebugUI(REASON_DSP_EXCEPTION);
1.1.1.7 root 1468: }
1.1.1.8 root 1469: else
1.1.1.11 root 1470: dsp_core.registers[DSP_REG_SP] = value & BITMASK(6);
1.1.1.7 root 1471: dsp_compute_ssh_ssl();
1472: break;
1473: case DSP_REG_SSH:
1474: dsp_stack_push(value, 0, 1);
1475: break;
1476: case DSP_REG_SSL:
1477: numreg = dsp_core.registers[DSP_REG_SP] & BITMASK(4);
1478: if (numreg == 0) {
1479: value = 0;
1480: }
1481: dsp_core.stack[1][numreg] = value & BITMASK(16);
1482: dsp_core.registers[DSP_REG_SSL] = value & BITMASK(16);
1483: break;
1484: default:
1.1.1.11 root 1485: dsp_core.registers[numreg] = value;
1.1.1.7 root 1486: dsp_core.registers[numreg] &= BITMASK(registers_mask[numreg]);
1487: break;
1.1.1.4 root 1488: }
1489: }
1490:
1.1 root 1491: /**********************************
1492: * Stack push/pop
1493: **********************************/
1494:
1.1.1.4 root 1495: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly)
1.1 root 1496: {
1.1.1.4 root 1497: Uint32 stack_error, underflow, stack;
1498:
1.1.1.6 root 1499: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1500: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1501: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) + 1;
1.1.1.4 root 1502:
1503:
1504: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1.1 root 1505: /* Stack full, raise interrupt */
1.1.1.5 root 1506: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.6 root 1507: if (!isDsp_in_disasm_mode)
1508: fprintf(stderr,"Dsp: Stack Overflow\n");
1.1.1.10 root 1509: if (ExceptionDebugMask & EXCEPT_DSP)
1.1.1.9 root 1510: DebugUI(REASON_DSP_EXCEPTION);
1.1 root 1511: }
1.1.1.11 root 1512:
1.1.1.6 root 1513: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1.1.1.4 root 1514: stack &= BITMASK(4);
1.1 root 1515:
1.1.1.4 root 1516: if (stack) {
1517: /* SSH part */
1.1.1.6 root 1518: dsp_core.stack[0][stack] = curpc & BITMASK(16);
1.1.1.4 root 1519: /* SSL part, if instruction is not like "MOVEC xx, SSH" */
1520: if (sshOnly == 0) {
1.1.1.6 root 1521: dsp_core.stack[1][stack] = cursr & BITMASK(16);
1.1.1.4 root 1522: }
1523: } else {
1.1.1.6 root 1524: dsp_core.stack[0][0] = 0;
1525: dsp_core.stack[1][0] = 0;
1.1.1.4 root 1526: }
1.1 root 1527:
1.1.1.4 root 1528: /* Update SSH and SSL registers */
1.1.1.6 root 1529: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1530: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1 root 1531: }
1532:
1.1.1.2 root 1533: static void dsp_stack_pop(Uint32 *newpc, Uint32 *newsr)
1.1 root 1534: {
1.1.1.4 root 1535: Uint32 stack_error, underflow, stack;
1536:
1.1.1.6 root 1537: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1538: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1539: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) - 1;
1.1.1.4 root 1540:
1541: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1542: /* Stack empty*/
1.1.1.5 root 1543: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.6 root 1544: if (!isDsp_in_disasm_mode)
1545: fprintf(stderr,"Dsp: Stack underflow\n");
1.1.1.10 root 1546: if (ExceptionDebugMask & EXCEPT_DSP)
1.1.1.9 root 1547: DebugUI(REASON_DSP_EXCEPTION);
1.1 root 1548: }
1549:
1.1.1.6 root 1550: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1.1.1.4 root 1551: stack &= BITMASK(4);
1.1.1.6 root 1552: *newpc = dsp_core.registers[DSP_REG_SSH];
1553: *newsr = dsp_core.registers[DSP_REG_SSL];
1.1.1.4 root 1554:
1.1.1.6 root 1555: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1556: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1.1.4 root 1557: }
1558:
1559: static void dsp_compute_ssh_ssl(void)
1560: {
1561: Uint32 stack;
1.1 root 1562:
1.1.1.6 root 1563: stack = dsp_core.registers[DSP_REG_SP];
1.1.1.4 root 1564: stack &= BITMASK(4);
1.1.1.6 root 1565: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1566: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1 root 1567: }
1568:
1569: /**********************************
1570: * Effective address calculation
1571: **********************************/
1572:
1.1.1.2 root 1573: static void dsp_update_rn(Uint32 numreg, Sint16 modifier)
1.1 root 1574: {
1.1.1.12 root 1575: Uint32 value;
1.1.1.2 root 1576: Uint16 m_reg;
1.1 root 1577:
1.1.1.6 root 1578: m_reg = (Uint16) dsp_core.registers[DSP_REG_M0+numreg];
1.1.1.7 root 1579: if (m_reg == 65535) {
1580: /* Linear addressing mode */
1.1.1.12 root 1581: value = dsp_core.registers[DSP_REG_R0+numreg]|0x10000;
1.1.1.7 root 1582: value += modifier;
1.1.1.12 root 1583: dsp_core.registers[DSP_REG_R0+numreg] = value & BITMASK(16);
1.1.1.7 root 1584: } else if (m_reg == 0) {
1.1 root 1585: /* Bit reversed carry update */
1586: dsp_update_rn_bitreverse(numreg);
1.1.1.4 root 1587: } else if (m_reg<=32767) {
1.1 root 1588: /* Modulo update */
1589: dsp_update_rn_modulo(numreg, modifier);
1590: } else {
1591: /* Undefined */
1592: }
1593: }
1594:
1.1.1.2 root 1595: static void dsp_update_rn_bitreverse(Uint32 numreg)
1.1 root 1596: {
1597: int revbits, i;
1.1.1.2 root 1598: Uint32 value, r_reg;
1.1 root 1599:
1600: /* Check how many bits to reverse */
1.1.1.6 root 1601: value = dsp_core.registers[DSP_REG_N0+numreg];
1.1 root 1602: for (revbits=0;revbits<16;revbits++) {
1603: if (value & (1<<revbits)) {
1604: break;
1605: }
1.1.1.11 root 1606: }
1.1 root 1607: revbits++;
1.1.1.11 root 1608:
1.1 root 1609: /* Reverse Rn bits */
1.1.1.6 root 1610: r_reg = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1611: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1612: for (i=0;i<revbits;i++) {
1613: if (r_reg & (1<<i)) {
1614: value |= 1<<(revbits-i-1);
1615: }
1616: }
1617:
1618: /* Increment */
1619: value++;
1620: value &= BITMASK(revbits);
1621:
1622: /* Reverse Rn bits */
1623: r_reg &= (BITMASK(16)-BITMASK(revbits));
1624: r_reg |= value;
1625:
1626: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1627: for (i=0;i<revbits;i++) {
1628: if (r_reg & (1<<i)) {
1629: value |= 1<<(revbits-i-1);
1630: }
1631: }
1632:
1.1.1.6 root 1633: dsp_core.registers[DSP_REG_R0+numreg] = value;
1.1 root 1634: }
1635:
1.1.1.2 root 1636: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier)
1.1 root 1637: {
1.1.1.12 root 1638: Uint16 bufsize, bufmask, modulo, abs_modifier;
1639: Uint32 r_reg, lobound, hibound;
1.1 root 1640:
1.1.1.12 root 1641: r_reg = dsp_core.registers[DSP_REG_R0+numreg]|0x10000;
1.1.1.6 root 1642: modulo = dsp_core.registers[DSP_REG_M0+numreg]+1;
1.1.1.12 root 1643:
1644:
1.1 root 1645: bufsize = 1;
1646: while (bufsize < modulo) {
1647: bufsize <<= 1;
1648: }
1.1.1.12 root 1649: bufmask = bufsize - 1;
1.1.1.11 root 1650:
1.1.1.12 root 1651:
1652: lobound = r_reg - (r_reg&bufmask);
1.1.1.2 root 1653: hibound = lobound + modulo - 1;
1.1 root 1654:
1.1.1.4 root 1655:
1.1.1.12 root 1656: if (modifier<0) {
1657: abs_modifier = -modifier;
1658: } else {
1659: abs_modifier = modifier;
1.1.1.2 root 1660: }
1.1.1.4 root 1661:
1662:
1.1.1.12 root 1663: if (abs_modifier>modulo) {
1664: if (abs_modifier&bufmask) {
1665: fprintf(stderr,"Dsp: Modulo addressing result unpredictable\n");
1666: } else {
1667: r_reg += modifier;
1668: }
1669: } else {
1670: r_reg += modifier;
1671:
1672:
1.1.1.4 root 1673: if (r_reg>hibound) {
1674: r_reg -= modulo;
1675: } else if (r_reg<lobound) {
1676: r_reg += modulo;
1.1.1.11 root 1677: }
1.1 root 1678: }
1679:
1.1.1.12 root 1680: dsp_core.registers[DSP_REG_R0+numreg] = r_reg & BITMASK(16);
1.1 root 1681: }
1682:
1.1.1.2 root 1683: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr)
1.1 root 1684: {
1.1.1.2 root 1685: Uint32 value, numreg, curreg;
1.1 root 1686:
1687: value = (ea_mode >> 3) & BITMASK(3);
1688: numreg = ea_mode & BITMASK(3);
1689: switch (value) {
1690: case 0:
1691: /* (Rx)-Nx */
1.1.1.6 root 1692: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1693: dsp_update_rn(numreg, -dsp_core.registers[DSP_REG_N0+numreg]);
1.1 root 1694: break;
1695: case 1:
1696: /* (Rx)+Nx */
1.1.1.6 root 1697: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1698: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1.1 root 1699: break;
1700: case 2:
1701: /* (Rx)- */
1.1.1.6 root 1702: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1703: dsp_update_rn(numreg, -1);
1704: break;
1705: case 3:
1706: /* (Rx)+ */
1.1.1.6 root 1707: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1.1.12 root 1708: dsp_update_rn(numreg, 1);
1.1 root 1709: break;
1710: case 4:
1711: /* (Rx) */
1.1.1.6 root 1712: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1713: break;
1714: case 5:
1715: /* (Rx+Nx) */
1.1.1.6 root 1716: dsp_core.instr_cycle += 2;
1717: curreg = dsp_core.registers[DSP_REG_R0+numreg];
1718: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1719: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1720: dsp_core.registers[DSP_REG_R0+numreg] = curreg;
1.1 root 1721: break;
1722: case 6:
1723: /* aa */
1.1.1.6 root 1724: dsp_core.instr_cycle += 2;
1725: *dst_addr = read_memory_p(dsp_core.pc+1);
1.1 root 1726: cur_inst_len++;
1727: if (numreg != 0) {
1728: return 1; /* immediate value */
1729: }
1730: break;
1731: case 7:
1732: /* -(Rx) */
1.1.1.6 root 1733: dsp_core.instr_cycle += 2;
1.1 root 1734: dsp_update_rn(numreg, -1);
1.1.1.6 root 1735: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1736: break;
1737: }
1738: /* address */
1739: return 0;
1740: }
1741:
1742: /**********************************
1743: * Condition code test
1744: **********************************/
1745:
1.1.1.2 root 1746: static int dsp_calc_cc(Uint32 cc_code)
1.1 root 1747: {
1.1.1.4 root 1748: Uint16 value1, value2, value3;
1.1 root 1749:
1.1.1.4 root 1750: switch (cc_code) {
1751: case 0: /* CC (HS) */
1.1.1.6 root 1752: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1.1.1.4 root 1753: return (value1==0);
1754: case 1: /* GE */
1.1.1.6 root 1755: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1756: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1.1.1.4 root 1757: return ((value1 ^ value2) == 0);
1758: case 2: /* NE */
1.1.1.6 root 1759: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_Z);
1.1.1.4 root 1760: return (value1==0);
1761: case 3: /* PL */
1.1.1.6 root 1762: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_N);
1.1.1.4 root 1763: return (value1==0);
1764: case 4: /* NN */
1.1.1.6 root 1765: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1766: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1767: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1.1.1.4 root 1768: return ((value1 | (value2 & value3)) == 0);
1769: case 5: /* EC */
1.1.1.6 root 1770: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_E);
1.1.1.4 root 1771: return (value1==0);
1772: case 6: /* LC */
1.1.1.6 root 1773: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_L);
1.1.1.4 root 1774: return (value1==0);
1.1.1.11 root 1775: case 7: /* GT */
1.1.1.6 root 1776: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1777: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1778: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1779: return ((value3 | (value1 ^ value2)) == 0);
1780: case 8: /* CS (LO) */
1.1.1.6 root 1781: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1.1.1.4 root 1782: return (value1==1);
1783: case 9: /* LT */
1.1.1.6 root 1784: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1785: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1.1.1.4 root 1786: return ((value1 ^ value2) == 1);
1787: case 10: /* EQ */
1.1.1.6 root 1788: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1789: return (value1==1);
1790: case 11: /* MI */
1.1.1.6 root 1791: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1.1.1.4 root 1792: return (value1==1);
1793: case 12: /* NR */
1.1.1.6 root 1794: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1795: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1796: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1.1.1.4 root 1797: return ((value1 | (value2 & value3)) == 1);
1798: case 13: /* ES */
1.1.1.6 root 1799: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_E) & 1;
1.1.1.4 root 1800: return (value1==1);
1801: case 14: /* LS */
1.1.1.6 root 1802: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_L) & 1;
1.1.1.4 root 1803: return (value1==1);
1804: case 15: /* LE */
1.1.1.6 root 1805: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1806: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1807: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1808: return ((value3 | (value1 ^ value2)) == 1);
1809: }
1810: return 0;
1.1 root 1811: }
1812:
1813: /**********************************
1814: * Highbyte opcodes dispatchers
1815: **********************************/
1816:
1817: static void opcode8h_0(void)
1818: {
1.1.1.4 root 1819: switch(cur_inst) {
1820: case 0x000000:
1821: dsp_nop();
1.1 root 1822: break;
1.1.1.4 root 1823: case 0x000004:
1824: dsp_rti();
1.1 root 1825: break;
1.1.1.4 root 1826: case 0x000005:
1827: dsp_illegal();
1.1 root 1828: break;
1.1.1.4 root 1829: case 0x000006:
1830: dsp_swi();
1831: break;
1832: case 0x00000c:
1833: dsp_rts();
1834: break;
1835: case 0x000084:
1836: dsp_reset();
1837: break;
1838: case 0x000086:
1839: dsp_wait();
1840: break;
1841: case 0x000087:
1842: dsp_stop();
1843: break;
1844: case 0x00008c:
1845: dsp_enddo();
1.1 root 1846: break;
1.1.1.10 root 1847: default:
1848: dsp_undefined();
1849: break;
1.1 root 1850: }
1851: }
1852:
1853: /**********************************
1854: * Non-parallel moves instructions
1855: **********************************/
1856:
1857: static void dsp_undefined(void)
1858: {
1.1.1.6 root 1859: if (isDsp_in_disasm_mode == false) {
1860: cur_inst_len = 0;
1.1.1.7 root 1861: /* Add some artificial CPU cycles to avoid being stuck in an infinite loop */
1.1.1.6 root 1862: dsp_core.instr_cycle += 100;
1.1.1.13! root 1863:
! 1864: /* Rate limit identical messages. Required to make
! 1865: * "Terrorize your soul" demo run at usable speed
! 1866: */
! 1867: dsp_error.count++;
! 1868: if (cur_inst != dsp_error.inst || dsp_core.pc != dsp_error.pc ||
! 1869: dsp_error.count >= dsp_error.limit) {
! 1870: dsp_error.inst = cur_inst;
! 1871: dsp_error.pc = dsp_core.pc;
! 1872: fprintf(stderr, "Dsp: 0x%04hx: 0x%06x Illegal instruction (%dx times)\n",
! 1873: dsp_error.pc, dsp_error.inst, dsp_error.count);
! 1874: if (dsp_error.count >= dsp_error.limit) {
! 1875: /* next message after 2x more hits */
! 1876: dsp_error.limit *= 2;
! 1877: } else {
! 1878: dsp_error.limit = 1;
! 1879: }
! 1880: dsp_error.count = 0;
! 1881: }
! 1882: } else {
1.1.1.6 root 1883: cur_inst_len = 1;
1884: dsp_core.instr_cycle = 0;
1885: }
1.1.1.10 root 1886: if (ExceptionDebugMask & EXCEPT_DSP) {
1.1.1.9 root 1887: DebugUI(REASON_DSP_EXCEPTION);
1888: }
1.1 root 1889: }
1890:
1891: static void dsp_andi(void)
1892: {
1.1.1.2 root 1893: Uint32 regnum, value;
1.1 root 1894:
1895: value = (cur_inst >> 8) & BITMASK(8);
1896: regnum = cur_inst & BITMASK(2);
1897: switch(regnum) {
1898: case 0:
1899: /* mr */
1.1.1.6 root 1900: dsp_core.registers[DSP_REG_SR] &= (value<<8)|BITMASK(8);
1.1 root 1901: break;
1902: case 1:
1903: /* ccr */
1.1.1.6 root 1904: dsp_core.registers[DSP_REG_SR] &= (BITMASK(8)<<8)|value;
1.1 root 1905: break;
1906: case 2:
1907: /* omr */
1.1.1.6 root 1908: dsp_core.registers[DSP_REG_OMR] &= value;
1.1 root 1909: break;
1910: }
1911: }
1912:
1.1.1.4 root 1913: static void dsp_bchg_aa(void)
1.1 root 1914: {
1.1.1.4 root 1915: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 1916:
1.1 root 1917: memspace = (cur_inst>>6) & 1;
1918: value = (cur_inst>>8) & BITMASK(6);
1919: numbit = cur_inst & BITMASK(5);
1920:
1.1.1.4 root 1921: addr = value;
1922: value = read_memory(memspace, addr);
1923: newcarry = (value>>numbit) & 1;
1924: if (newcarry) {
1925: value -= (1<<numbit);
1926: } else {
1927: value += (1<<numbit);
1.1 root 1928: }
1.1.1.4 root 1929: write_memory(memspace, addr, value);
1.1 root 1930:
1931: /* Set carry */
1.1.1.6 root 1932: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1933: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1934:
1.1.1.6 root 1935: dsp_core.instr_cycle += 2;
1.1 root 1936: }
1937:
1.1.1.4 root 1938: static void dsp_bchg_ea(void)
1.1 root 1939: {
1.1.1.4 root 1940: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 1941:
1.1 root 1942: memspace = (cur_inst>>6) & 1;
1943: value = (cur_inst>>8) & BITMASK(6);
1944: numbit = cur_inst & BITMASK(5);
1945:
1.1.1.4 root 1946: dsp_calc_ea(value, &addr);
1947: value = read_memory(memspace, addr);
1948: newcarry = (value>>numbit) & 1;
1949: if (newcarry) {
1950: value -= (1<<numbit);
1951: } else {
1952: value += (1<<numbit);
1.1 root 1953: }
1.1.1.4 root 1954: write_memory(memspace, addr, value);
1.1 root 1955:
1956: /* Set carry */
1.1.1.6 root 1957: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1958: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1959:
1.1.1.6 root 1960: dsp_core.instr_cycle += 2;
1.1 root 1961: }
1962:
1.1.1.4 root 1963: static void dsp_bchg_pp(void)
1.1 root 1964: {
1.1.1.4 root 1965: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 1966:
1.1 root 1967: memspace = (cur_inst>>6) & 1;
1968: value = (cur_inst>>8) & BITMASK(6);
1969: numbit = cur_inst & BITMASK(5);
1970:
1.1.1.4 root 1971: addr = 0xffc0 + value;
1972: value = read_memory(memspace, addr);
1973: newcarry = (value>>numbit) & 1;
1974: if (newcarry) {
1975: value -= (1<<numbit);
1976: } else {
1977: value += (1<<numbit);
1.1 root 1978: }
1.1.1.4 root 1979: write_memory(memspace, addr, value);
1.1 root 1980:
1981: /* Set carry */
1.1.1.6 root 1982: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1983: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1984:
1.1.1.6 root 1985: dsp_core.instr_cycle += 2;
1.1 root 1986: }
1987:
1.1.1.4 root 1988: static void dsp_bchg_reg(void)
1.1 root 1989: {
1.1.1.4 root 1990: Uint32 value, numreg, newcarry, numbit;
1.1.1.11 root 1991:
1.1.1.4 root 1992: numreg = (cur_inst>>8) & BITMASK(6);
1.1 root 1993: numbit = cur_inst & BITMASK(5);
1994:
1.1.1.4 root 1995: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
1996: dsp_pm_read_accu24(numreg, &value);
1997: } else {
1.1.1.6 root 1998: value = dsp_core.registers[numreg];
1.1 root 1999: }
2000:
1.1.1.4 root 2001: newcarry = (value>>numbit) & 1;
2002: if (newcarry) {
2003: value -= (1<<numbit);
2004: } else {
2005: value += (1<<numbit);
2006: }
2007:
2008: dsp_write_reg(numreg, value);
2009:
1.1 root 2010: /* Set carry */
1.1.1.6 root 2011: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2012: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2013:
1.1.1.6 root 2014: dsp_core.instr_cycle += 2;
1.1 root 2015: }
2016:
1.1.1.4 root 2017: static void dsp_bclr_aa(void)
1.1 root 2018: {
1.1.1.4 root 2019: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2020:
1.1.1.4 root 2021: memspace = (cur_inst>>6) & 1;
2022: addr = (cur_inst>>8) & BITMASK(6);
2023: numbit = cur_inst & BITMASK(5);
1.1 root 2024:
1.1.1.4 root 2025: value = read_memory(memspace, addr);
2026: newcarry = (value>>numbit) & 1;
2027: value &= 0xffffffff-(1<<numbit);
2028: write_memory(memspace, addr, value);
1.1.1.2 root 2029:
1.1.1.4 root 2030: /* Set carry */
1.1.1.6 root 2031: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2032: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 2033:
1.1.1.6 root 2034: dsp_core.instr_cycle += 2;
1.1.1.4 root 2035: }
1.1 root 2036:
1.1.1.4 root 2037: static void dsp_bclr_ea(void)
2038: {
2039: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2040:
1.1.1.4 root 2041: memspace = (cur_inst>>6) & 1;
2042: value = (cur_inst>>8) & BITMASK(6);
2043: numbit = cur_inst & BITMASK(5);
1.1 root 2044:
1.1.1.4 root 2045: dsp_calc_ea(value, &addr);
2046: value = read_memory(memspace, addr);
2047: newcarry = (value>>numbit) & 1;
2048: value &= 0xffffffff-(1<<numbit);
2049: write_memory(memspace, addr, value);
1.1.1.2 root 2050:
1.1.1.4 root 2051: /* Set carry */
1.1.1.6 root 2052: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2053: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2054:
1.1.1.6 root 2055: dsp_core.instr_cycle += 2;
1.1 root 2056: }
2057:
1.1.1.4 root 2058: static void dsp_bclr_pp(void)
2059: {
2060: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2061:
1.1.1.4 root 2062: memspace = (cur_inst>>6) & 1;
2063: value = (cur_inst>>8) & BITMASK(6);
2064: numbit = cur_inst & BITMASK(5);
1.1.1.3 root 2065:
1.1.1.4 root 2066: addr = 0xffc0 + value;
2067: value = read_memory(memspace, addr);
2068: newcarry = (value>>numbit) & 1;
2069: value &= 0xffffffff-(1<<numbit);
2070: write_memory(memspace, addr, value);
1.1.1.3 root 2071:
1.1.1.4 root 2072: /* Set carry */
1.1.1.6 root 2073: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2074: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 2075:
1.1.1.6 root 2076: dsp_core.instr_cycle += 2;
1.1.1.4 root 2077: }
1.1 root 2078:
1.1.1.4 root 2079: static void dsp_bclr_reg(void)
2080: {
2081: Uint32 value, numreg, newcarry, numbit;
1.1.1.11 root 2082:
1.1.1.4 root 2083: numreg = (cur_inst>>8) & BITMASK(6);
2084: numbit = cur_inst & BITMASK(5);
1.1 root 2085:
1.1.1.4 root 2086: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2087: dsp_pm_read_accu24(numreg, &value);
2088: } else {
1.1.1.6 root 2089: value = dsp_core.registers[numreg];
1.1.1.4 root 2090: }
1.1 root 2091:
1.1.1.4 root 2092: newcarry = (value>>numbit) & 1;
2093: value &= 0xffffffff-(1<<numbit);
1.1 root 2094:
1.1.1.4 root 2095: dsp_write_reg(numreg, value);
2096:
2097: /* Set carry */
1.1.1.6 root 2098: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2099: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 2100:
1.1.1.6 root 2101: dsp_core.instr_cycle += 2;
1.1 root 2102: }
2103:
1.1.1.4 root 2104: static void dsp_bset_aa(void)
1.1 root 2105: {
1.1.1.4 root 2106: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2107:
1.1.1.4 root 2108: memspace = (cur_inst>>6) & 1;
2109: value = (cur_inst>>8) & BITMASK(6);
2110: numbit = cur_inst & BITMASK(5);
1.1 root 2111:
1.1.1.4 root 2112: addr = value;
2113: value = read_memory(memspace, addr);
2114: newcarry = (value>>numbit) & 1;
2115: value |= (1<<numbit);
2116: write_memory(memspace, addr, value);
2117:
2118: /* Set carry */
1.1.1.6 root 2119: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2120: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2121:
1.1.1.6 root 2122: dsp_core.instr_cycle += 2;
1.1.1.4 root 2123: }
2124:
2125: static void dsp_bset_ea(void)
2126: {
2127: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2128:
1.1.1.4 root 2129: memspace = (cur_inst>>6) & 1;
2130: value = (cur_inst>>8) & BITMASK(6);
2131: numbit = cur_inst & BITMASK(5);
2132:
2133: dsp_calc_ea(value, &addr);
2134: value = read_memory(memspace, addr);
2135: newcarry = (value>>numbit) & 1;
2136: value |= (1<<numbit);
2137: write_memory(memspace, addr, value);
2138:
2139: /* Set carry */
1.1.1.6 root 2140: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2141: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2142:
1.1.1.6 root 2143: dsp_core.instr_cycle += 2;
1.1.1.4 root 2144: }
2145:
2146: static void dsp_bset_pp(void)
2147: {
2148: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2149:
1.1.1.4 root 2150: memspace = (cur_inst>>6) & 1;
2151: value = (cur_inst>>8) & BITMASK(6);
2152: numbit = cur_inst & BITMASK(5);
2153: addr = 0xffc0 + value;
2154: value = read_memory(memspace, addr);
2155: newcarry = (value>>numbit) & 1;
2156: value |= (1<<numbit);
2157: write_memory(memspace, addr, value);
2158:
2159: /* Set carry */
1.1.1.6 root 2160: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2161: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2162:
1.1.1.6 root 2163: dsp_core.instr_cycle += 2;
1.1.1.4 root 2164: }
2165:
2166: static void dsp_bset_reg(void)
2167: {
2168: Uint32 value, numreg, newcarry, numbit;
1.1.1.11 root 2169:
1.1.1.4 root 2170: numreg = (cur_inst>>8) & BITMASK(6);
2171: numbit = cur_inst & BITMASK(5);
2172:
2173: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2174: dsp_pm_read_accu24(numreg, &value);
2175: } else {
1.1.1.6 root 2176: value = dsp_core.registers[numreg];
1.1.1.4 root 2177: }
2178:
2179: newcarry = (value>>numbit) & 1;
2180: value |= (1<<numbit);
2181:
2182: dsp_write_reg(numreg, value);
2183:
2184: /* Set carry */
1.1.1.6 root 2185: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2186: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2187:
1.1.1.6 root 2188: dsp_core.instr_cycle += 2;
1.1.1.4 root 2189: }
2190:
2191: static void dsp_btst_aa(void)
2192: {
2193: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2194:
1.1.1.4 root 2195: memspace = (cur_inst>>6) & 1;
2196: value = (cur_inst>>8) & BITMASK(6);
2197: numbit = cur_inst & BITMASK(5);
2198:
2199: addr = value;
2200: value = read_memory(memspace, addr);
2201: newcarry = (value>>numbit) & 1;
2202:
2203: /* Set carry */
1.1.1.6 root 2204: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2205: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2206:
1.1.1.6 root 2207: dsp_core.instr_cycle += 2;
1.1.1.4 root 2208: }
2209:
2210: static void dsp_btst_ea(void)
2211: {
2212: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2213:
1.1.1.4 root 2214: memspace = (cur_inst>>6) & 1;
2215: value = (cur_inst>>8) & BITMASK(6);
2216: numbit = cur_inst & BITMASK(5);
2217:
2218: dsp_calc_ea(value, &addr);
2219: value = read_memory(memspace, addr);
2220: newcarry = (value>>numbit) & 1;
2221:
2222: /* Set carry */
1.1.1.6 root 2223: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2224: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2225:
1.1.1.6 root 2226: dsp_core.instr_cycle += 2;
1.1.1.4 root 2227: }
2228:
2229: static void dsp_btst_pp(void)
2230: {
2231: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2232:
1.1.1.4 root 2233: memspace = (cur_inst>>6) & 1;
2234: value = (cur_inst>>8) & BITMASK(6);
2235: numbit = cur_inst & BITMASK(5);
2236:
2237: addr = 0xffc0 + value;
2238: value = read_memory(memspace, addr);
2239: newcarry = (value>>numbit) & 1;
2240:
2241: /* Set carry */
1.1.1.6 root 2242: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2243: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2244:
1.1.1.6 root 2245: dsp_core.instr_cycle += 2;
1.1.1.4 root 2246: }
2247:
2248: static void dsp_btst_reg(void)
2249: {
2250: Uint32 value, numreg, newcarry, numbit;
1.1.1.11 root 2251:
1.1.1.4 root 2252: numreg = (cur_inst>>8) & BITMASK(6);
2253: numbit = cur_inst & BITMASK(5);
2254:
2255: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2256: dsp_pm_read_accu24(numreg, &value);
2257: } else {
1.1.1.6 root 2258: value = dsp_core.registers[numreg];
1.1.1.4 root 2259: }
2260:
2261: newcarry = (value>>numbit) & 1;
2262:
2263: /* Set carry */
1.1.1.6 root 2264: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2265: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2266:
1.1.1.6 root 2267: dsp_core.instr_cycle += 2;
1.1.1.4 root 2268: }
2269:
2270: static void dsp_div(void)
2271: {
2272: Uint32 srcreg, destreg, source[3], dest[3];
2273: Uint16 newsr;
2274:
2275: srcreg = DSP_REG_NULL;
2276: switch((cur_inst>>4) & BITMASK(2)) {
2277: case 0: srcreg = DSP_REG_X0; break;
2278: case 1: srcreg = DSP_REG_Y0; break;
2279: case 2: srcreg = DSP_REG_X1; break;
2280: case 3: srcreg = DSP_REG_Y1; break;
2281: }
1.1.1.7 root 2282: source[2] = 0;
2283: source[1] = dsp_core.registers[srcreg];
2284: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.4 root 2285:
1.1.1.7 root 2286: destreg = DSP_REG_A + ((cur_inst>>3) & 1);
2287: if (destreg == DSP_REG_A) {
2288: dest[0] = dsp_core.registers[DSP_REG_A2];
2289: dest[1] = dsp_core.registers[DSP_REG_A1];
2290: dest[2] = dsp_core.registers[DSP_REG_A0];
2291: }
2292: else {
2293: dest[0] = dsp_core.registers[DSP_REG_B2];
2294: dest[1] = dsp_core.registers[DSP_REG_B1];
2295: dest[2] = dsp_core.registers[DSP_REG_B0];
2296: }
1.1.1.4 root 2297:
2298: if (((dest[0]>>7) & 1) ^ ((source[1]>>23) & 1)) {
2299: /* D += S */
2300: newsr = dsp_asl56(dest);
2301: dsp_add56(source, dest);
2302: } else {
2303: /* D -= S */
2304: newsr = dsp_asl56(dest);
2305: dsp_sub56(source, dest);
2306: }
2307:
1.1.1.6 root 2308: dest[2] |= (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1.1.4 root 2309:
1.1.1.7 root 2310: if (destreg == DSP_REG_A) {
2311: dsp_core.registers[DSP_REG_A2] = dest[0];
2312: dsp_core.registers[DSP_REG_A1] = dest[1];
2313: dsp_core.registers[DSP_REG_A0] = dest[2];
2314: }
2315: else {
2316: dsp_core.registers[DSP_REG_B2] = dest[0];
2317: dsp_core.registers[DSP_REG_B1] = dest[1];
2318: dsp_core.registers[DSP_REG_B0] = dest[2];
2319: }
1.1.1.11 root 2320:
1.1.1.6 root 2321: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
2322: dsp_core.registers[DSP_REG_SR] |= (1-((dest[0]>>7) & 1))<<DSP_SR_C;
2323: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_L);
2324: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_V);
1.1.1.4 root 2325: }
2326:
2327: /*
2328: DO instruction parameter encoding
2329:
2330: xxxxxxxx 00xxxxxx 0xxxxxxx aa
2331: xxxxxxxx 01xxxxxx 0xxxxxxx ea
2332: xxxxxxxx YYxxxxxx 1xxxxxxx imm
2333: xxxxxxxx 11xxxxxx 0xxxxxxx reg
2334: */
2335:
2336: static void dsp_do_aa(void)
2337: {
2338: Uint32 memspace, addr;
2339:
2340: /* x:aa */
2341: /* y:aa */
2342:
1.1.1.6 root 2343: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2344: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2345: cur_inst_len++;
1.1.1.6 root 2346: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2347: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1 root 2348:
2349: memspace = (cur_inst>>6) & 1;
2350: addr = (cur_inst>>8) & BITMASK(6);
1.1.1.6 root 2351: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
1.1.1.4 root 2352:
1.1.1.6 root 2353: dsp_core.instr_cycle += 4;
1.1 root 2354: }
2355:
1.1.1.3 root 2356: static void dsp_do_imm(void)
1.1 root 2357: {
2358: /* #xx */
1.1.1.3 root 2359:
1.1.1.6 root 2360: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2361: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2362: cur_inst_len++;
1.1.1.6 root 2363: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2364: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2365:
1.1.1.6 root 2366: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
1.1.1.3 root 2367: + ((cur_inst & BITMASK(4))<<8);
1.1.1.4 root 2368:
1.1.1.6 root 2369: dsp_core.instr_cycle += 4;
1.1 root 2370: }
2371:
1.1.1.3 root 2372: static void dsp_do_ea(void)
1.1 root 2373: {
1.1.1.2 root 2374: Uint32 memspace, ea_mode, addr;
1.1 root 2375:
2376: /* x:ea */
2377: /* y:ea */
2378:
1.1.1.6 root 2379: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2380: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2381: cur_inst_len++;
1.1.1.6 root 2382: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2383: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2384:
1.1 root 2385: memspace = (cur_inst>>6) & 1;
2386: ea_mode = (cur_inst>>8) & BITMASK(6);
2387: dsp_calc_ea(ea_mode, &addr);
1.1.1.6 root 2388: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
1.1.1.4 root 2389:
1.1.1.6 root 2390: dsp_core.instr_cycle += 4;
1.1 root 2391: }
2392:
1.1.1.3 root 2393: static void dsp_do_reg(void)
1.1 root 2394: {
1.1.1.2 root 2395: Uint32 numreg;
1.1 root 2396:
2397: /* S */
2398:
1.1.1.6 root 2399: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2400: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2401: cur_inst_len++;
2402:
1.1 root 2403: numreg = (cur_inst>>8) & BITMASK(6);
2404: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11 root 2405: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
1.1 root 2406: } else {
1.1.1.6 root 2407: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
1.1 root 2408: }
1.1.1.6 root 2409: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.4 root 2410:
1.1.1.6 root 2411: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2412: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2413:
1.1.1.6 root 2414: dsp_core.instr_cycle += 4;
1.1 root 2415: }
2416:
2417: static void dsp_enddo(void)
2418: {
1.1.1.4 root 2419: Uint32 saved_pc, saved_sr;
1.1 root 2420:
1.1.1.4 root 2421: dsp_stack_pop(&saved_pc, &saved_sr);
1.1.1.6 root 2422: dsp_core.registers[DSP_REG_SR] &= 0x7f;
2423: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
2424: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
1.1 root 2425: }
2426:
2427: static void dsp_illegal(void)
2428: {
2429: /* Raise interrupt p:0x003e */
1.1.1.5 root 2430: dsp_add_interrupt(DSP_INTER_ILLEGAL);
1.1.1.10 root 2431: if (ExceptionDebugMask & EXCEPT_DSP) {
1.1.1.9 root 2432: DebugUI(REASON_DSP_EXCEPTION);
2433: }
1.1 root 2434: }
2435:
1.1.1.4 root 2436: static void dsp_jcc_imm(void)
1.1 root 2437: {
1.1.1.4 root 2438: Uint32 cc_code, newpc;
1.1 root 2439:
1.1.1.4 root 2440: newpc = cur_inst & BITMASK(12);
2441: cc_code=(cur_inst>>12) & BITMASK(4);
2442: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2443: dsp_core.pc = newpc;
1.1.1.4 root 2444: cur_inst_len = 0;
2445: }
2446:
1.1.1.6 root 2447: dsp_core.instr_cycle += 2;
1.1.1.4 root 2448: }
2449:
2450: static void dsp_jcc_ea(void)
2451: {
2452: Uint32 newpc, cc_code;
2453:
2454: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2455: cc_code=cur_inst & BITMASK(4);
1.1 root 2456:
2457: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2458: dsp_core.pc = newpc;
1.1 root 2459: cur_inst_len = 0;
2460: }
1.1.1.4 root 2461:
1.1.1.6 root 2462: dsp_core.instr_cycle += 2;
1.1 root 2463: }
2464:
1.1.1.4 root 2465: static void dsp_jclr_aa(void)
1.1 root 2466: {
1.1.1.4 root 2467: Uint32 memspace, addr, value, numbit, newaddr;
1.1.1.11 root 2468:
1.1 root 2469: memspace = (cur_inst>>6) & 1;
1.1.1.4 root 2470: addr = (cur_inst>>8) & BITMASK(6);
1.1 root 2471: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2472: value = read_memory(memspace, addr);
1.1.1.6 root 2473: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2474:
1.1.1.6 root 2475: dsp_core.instr_cycle += 4;
1.1 root 2476:
1.1.1.4 root 2477: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2478: dsp_core.pc = newaddr;
1.1.1.4 root 2479: cur_inst_len = 0;
2480: return;
1.1.1.11 root 2481: }
1.1.1.2 root 2482: ++cur_inst_len;
1.1.1.4 root 2483: }
2484:
2485: static void dsp_jclr_ea(void)
2486: {
2487: Uint32 memspace, addr, value, numbit, newaddr;
1.1.1.11 root 2488:
1.1.1.4 root 2489: memspace = (cur_inst>>6) & 1;
2490: value = (cur_inst>>8) & BITMASK(6);
2491: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2492: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2493:
1.1.1.4 root 2494: dsp_calc_ea(value, &addr);
2495: value = read_memory(memspace, addr);
2496:
1.1.1.6 root 2497: dsp_core.instr_cycle += 4;
1.1 root 2498:
2499: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2500: dsp_core.pc = newaddr;
1.1.1.4 root 2501: cur_inst_len = 0;
2502: return;
1.1.1.11 root 2503: }
1.1.1.4 root 2504: ++cur_inst_len;
2505: }
1.1 root 2506:
1.1.1.4 root 2507: static void dsp_jclr_pp(void)
2508: {
2509: Uint32 memspace, addr, value, numbit, newaddr;
1.1.1.11 root 2510:
1.1.1.4 root 2511: memspace = (cur_inst>>6) & 1;
2512: value = (cur_inst>>8) & BITMASK(6);
2513: numbit = cur_inst & BITMASK(5);
2514: addr = 0xffc0 + value;
2515: value = read_memory(memspace, addr);
1.1.1.6 root 2516: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2517:
1.1.1.6 root 2518: dsp_core.instr_cycle += 4;
1.1 root 2519:
1.1.1.4 root 2520: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2521: dsp_core.pc = newaddr;
1.1.1.4 root 2522: cur_inst_len = 0;
2523: return;
1.1.1.11 root 2524: }
1.1.1.4 root 2525: ++cur_inst_len;
2526: }
1.1.1.2 root 2527:
1.1.1.4 root 2528: static void dsp_jclr_reg(void)
2529: {
2530: Uint32 value, numreg, numbit, newaddr;
1.1.1.11 root 2531:
1.1.1.4 root 2532: numreg = (cur_inst>>8) & BITMASK(6);
2533: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2534: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2535:
1.1.1.4 root 2536: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2537: dsp_pm_read_accu24(numreg, &value);
2538: } else {
1.1.1.6 root 2539: value = dsp_core.registers[numreg];
1.1.1.4 root 2540: }
1.1 root 2541:
1.1.1.6 root 2542: dsp_core.instr_cycle += 4;
1.1.1.4 root 2543:
2544: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2545: dsp_core.pc = newaddr;
1.1 root 2546: cur_inst_len = 0;
2547: return;
1.1.1.11 root 2548: }
1.1.1.4 root 2549: ++cur_inst_len;
1.1 root 2550: }
2551:
1.1.1.4 root 2552: static void dsp_jmp_ea(void)
1.1 root 2553: {
1.1.1.2 root 2554: Uint32 newpc;
1.1 root 2555:
1.1.1.4 root 2556: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &newpc);
1.1 root 2557: cur_inst_len = 0;
1.1.1.6 root 2558: dsp_core.pc = newpc;
1.1 root 2559:
1.1.1.6 root 2560: dsp_core.instr_cycle += 2;
1.1.1.4 root 2561: }
2562:
2563: static void dsp_jmp_imm(void)
2564: {
2565: Uint32 newpc;
1.1 root 2566:
1.1.1.4 root 2567: newpc = cur_inst & BITMASK(12);
2568: cur_inst_len = 0;
1.1.1.6 root 2569: dsp_core.pc = newpc;
1.1.1.4 root 2570:
1.1.1.6 root 2571: dsp_core.instr_cycle += 2;
1.1 root 2572: }
2573:
1.1.1.4 root 2574: static void dsp_jscc_ea(void)
1.1 root 2575: {
1.1.1.2 root 2576: Uint32 newpc, cc_code;
1.1 root 2577:
1.1.1.4 root 2578: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2579: cc_code=cur_inst & BITMASK(4);
2580:
2581: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2582: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2583: dsp_core.pc = newpc;
1.1.1.4 root 2584: cur_inst_len = 0;
1.1.1.11 root 2585: }
1.1.1.4 root 2586:
1.1.1.6 root 2587: dsp_core.instr_cycle += 2;
1.1.1.4 root 2588: }
1.1 root 2589:
1.1.1.4 root 2590: static void dsp_jscc_imm(void)
2591: {
2592: Uint32 cc_code, newpc;
2593:
2594: newpc = cur_inst & BITMASK(12);
2595: cc_code=(cur_inst>>12) & BITMASK(4);
1.1 root 2596: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2597: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2598: dsp_core.pc = newpc;
1.1.1.4 root 2599: cur_inst_len = 0;
1.1.1.11 root 2600: }
1.1.1.4 root 2601:
1.1.1.6 root 2602: dsp_core.instr_cycle += 2;
1.1.1.4 root 2603: }
1.1 root 2604:
1.1.1.4 root 2605: static void dsp_jsclr_aa(void)
2606: {
2607: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2608:
1.1.1.4 root 2609: memspace = (cur_inst>>6) & 1;
2610: addr = (cur_inst>>8) & BITMASK(6);
2611: numbit = cur_inst & BITMASK(5);
2612: value = read_memory(memspace, addr);
1.1.1.6 root 2613: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2614:
1.1.1.6 root 2615: dsp_core.instr_cycle += 4;
1.1.1.11 root 2616:
1.1.1.4 root 2617: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2618: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2619: newpc = newaddr;
1.1.1.6 root 2620: dsp_core.pc = newpc;
1.1 root 2621: cur_inst_len = 0;
1.1.1.4 root 2622: return;
1.1.1.11 root 2623: }
1.1.1.4 root 2624: ++cur_inst_len;
1.1 root 2625: }
2626:
1.1.1.4 root 2627: static void dsp_jsclr_ea(void)
1.1 root 2628: {
1.1.1.4 root 2629: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2630:
1.1 root 2631: memspace = (cur_inst>>6) & 1;
2632: value = (cur_inst>>8) & BITMASK(6);
2633: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2634: dsp_calc_ea(value, &addr);
2635: value = read_memory(memspace, addr);
1.1.1.6 root 2636: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2637:
1.1.1.6 root 2638: dsp_core.instr_cycle += 4;
1.1.1.11 root 2639:
1.1.1.4 root 2640: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2641: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2642: newpc = newaddr;
1.1.1.6 root 2643: dsp_core.pc = newpc;
1.1.1.4 root 2644: cur_inst_len = 0;
2645: return;
1.1.1.11 root 2646: }
1.1.1.2 root 2647: ++cur_inst_len;
1.1.1.4 root 2648: }
2649:
2650: static void dsp_jsclr_pp(void)
2651: {
2652: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2653:
1.1.1.4 root 2654: memspace = (cur_inst>>6) & 1;
2655: value = (cur_inst>>8) & BITMASK(6);
2656: numbit = cur_inst & BITMASK(5);
2657: addr = 0xffc0 + value;
2658: value = read_memory(memspace, addr);
1.1.1.6 root 2659: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2660:
1.1.1.6 root 2661: dsp_core.instr_cycle += 4;
1.1.1.11 root 2662:
1.1 root 2663: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2664: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2665: newpc = newaddr;
1.1.1.6 root 2666: dsp_core.pc = newpc;
1.1.1.4 root 2667: cur_inst_len = 0;
2668: return;
1.1.1.11 root 2669: }
1.1.1.4 root 2670: ++cur_inst_len;
2671: }
2672:
2673: static void dsp_jsclr_reg(void)
2674: {
2675: Uint32 value, numreg, newpc, numbit, newaddr;
1.1.1.11 root 2676:
1.1.1.4 root 2677: numreg = (cur_inst>>8) & BITMASK(6);
2678: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2679: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2680:
1.1.1.4 root 2681: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2682: dsp_pm_read_accu24(numreg, &value);
2683: } else {
1.1.1.6 root 2684: value = dsp_core.registers[numreg];
1.1.1.4 root 2685: }
2686:
1.1.1.6 root 2687: dsp_core.instr_cycle += 4;
1.1.1.11 root 2688:
1.1.1.4 root 2689: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2690: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2691: newpc = newaddr;
1.1.1.6 root 2692: dsp_core.pc = newpc;
1.1 root 2693: cur_inst_len = 0;
1.1.1.4 root 2694: return;
1.1.1.11 root 2695: }
1.1.1.4 root 2696: ++cur_inst_len;
1.1 root 2697: }
2698:
1.1.1.4 root 2699: static void dsp_jset_aa(void)
1.1 root 2700: {
1.1.1.4 root 2701: Uint32 memspace, addr, value, numbit, newpc, newaddr;
1.1.1.11 root 2702:
1.1.1.4 root 2703: memspace = (cur_inst>>6) & 1;
2704: addr = (cur_inst>>8) & BITMASK(6);
2705: numbit = cur_inst & BITMASK(5);
2706: value = read_memory(memspace, addr);
1.1.1.6 root 2707: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2708:
1.1.1.6 root 2709: dsp_core.instr_cycle += 4;
1.1.1.11 root 2710:
1.1.1.4 root 2711: if (value & (1<<numbit)) {
2712: newpc = newaddr;
1.1.1.6 root 2713: dsp_core.pc = newpc;
1.1.1.4 root 2714: cur_inst_len=0;
2715: return;
1.1.1.11 root 2716: }
1.1.1.4 root 2717: ++cur_inst_len;
2718: }
2719:
2720: static void dsp_jset_ea(void)
2721: {
2722: Uint32 memspace, addr, value, numbit, newpc, newaddr;
1.1.1.11 root 2723:
1.1 root 2724: memspace = (cur_inst>>6) & 1;
2725: value = (cur_inst>>8) & BITMASK(6);
2726: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2727: dsp_calc_ea(value, &addr);
2728: value = read_memory(memspace, addr);
1.1.1.6 root 2729: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2730:
1.1.1.6 root 2731: dsp_core.instr_cycle += 4;
1.1.1.7 root 2732:
1.1.1.4 root 2733: if (value & (1<<numbit)) {
2734: newpc = newaddr;
1.1.1.6 root 2735: dsp_core.pc = newpc;
1.1.1.4 root 2736: cur_inst_len=0;
2737: return;
1.1.1.11 root 2738: }
1.1.1.4 root 2739: ++cur_inst_len;
2740: }
1.1 root 2741:
1.1.1.4 root 2742: static void dsp_jset_pp(void)
2743: {
2744: Uint32 memspace, addr, value, numbit, newpc, newaddr;
1.1.1.11 root 2745:
1.1.1.4 root 2746: memspace = (cur_inst>>6) & 1;
2747: value = (cur_inst>>8) & BITMASK(6);
2748: numbit = cur_inst & BITMASK(5);
2749: addr = 0xffc0 + value;
2750: value = read_memory(memspace, addr);
1.1.1.6 root 2751: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2752:
1.1.1.6 root 2753: dsp_core.instr_cycle += 4;
1.1.1.11 root 2754:
1.1.1.4 root 2755: if (value & (1<<numbit)) {
2756: newpc = newaddr;
1.1.1.6 root 2757: dsp_core.pc = newpc;
1.1.1.4 root 2758: cur_inst_len=0;
2759: return;
1.1.1.11 root 2760: }
1.1.1.4 root 2761: ++cur_inst_len;
2762: }
2763:
2764: static void dsp_jset_reg(void)
2765: {
2766: Uint32 value, numreg, numbit, newpc, newaddr;
1.1.1.11 root 2767:
1.1.1.4 root 2768: numreg = (cur_inst>>8) & BITMASK(6);
2769: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2770: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2771:
1.1.1.4 root 2772: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2773: dsp_pm_read_accu24(numreg, &value);
2774: } else {
1.1.1.6 root 2775: value = dsp_core.registers[numreg];
1.1.1.4 root 2776: }
2777:
1.1.1.6 root 2778: dsp_core.instr_cycle += 4;
1.1.1.11 root 2779:
1.1.1.4 root 2780: if (value & (1<<numbit)) {
2781: newpc = newaddr;
1.1.1.6 root 2782: dsp_core.pc = newpc;
1.1.1.4 root 2783: cur_inst_len=0;
2784: return;
1.1.1.11 root 2785: }
1.1.1.4 root 2786: ++cur_inst_len;
2787: }
2788:
2789: static void dsp_jsr_imm(void)
2790: {
2791: Uint32 newpc;
2792:
2793: newpc = cur_inst & BITMASK(12);
2794:
1.1.1.6 root 2795: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2796: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2797: }
2798: else {
1.1.1.6 root 2799: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1.1.1.4 root 2800: }
2801:
1.1.1.6 root 2802: dsp_core.pc = newpc;
1.1.1.4 root 2803: cur_inst_len = 0;
2804:
1.1.1.6 root 2805: dsp_core.instr_cycle += 2;
1.1.1.4 root 2806: }
2807:
2808: static void dsp_jsr_ea(void)
2809: {
2810: Uint32 newpc;
2811:
2812: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&newpc);
2813:
1.1.1.6 root 2814: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2815: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2816: }
2817: else {
1.1.1.6 root 2818: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1.1.1.4 root 2819: }
2820:
1.1.1.6 root 2821: dsp_core.pc = newpc;
1.1.1.4 root 2822: cur_inst_len = 0;
2823:
1.1.1.6 root 2824: dsp_core.instr_cycle += 2;
1.1.1.4 root 2825: }
2826:
2827: static void dsp_jsset_aa(void)
2828: {
2829: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2830:
1.1.1.4 root 2831: memspace = (cur_inst>>6) & 1;
2832: addr = (cur_inst>>8) & BITMASK(6);
2833: numbit = cur_inst & BITMASK(5);
2834: value = read_memory(memspace, addr);
1.1.1.6 root 2835: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2836:
1.1.1.6 root 2837: dsp_core.instr_cycle += 4;
1.1.1.4 root 2838:
2839: if (value & (1<<numbit)) {
1.1.1.6 root 2840: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2841: newpc = newaddr;
1.1.1.6 root 2842: dsp_core.pc = newpc;
1.1.1.4 root 2843: cur_inst_len = 0;
2844: return;
1.1.1.11 root 2845: }
1.1.1.4 root 2846: ++cur_inst_len;
2847: }
2848:
2849: static void dsp_jsset_ea(void)
2850: {
2851: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2852:
1.1.1.4 root 2853: memspace = (cur_inst>>6) & 1;
2854: value = (cur_inst>>8) & BITMASK(6);
2855: numbit = cur_inst & BITMASK(5);
2856: dsp_calc_ea(value, &addr);
2857: value = read_memory(memspace, addr);
1.1.1.6 root 2858: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2859:
1.1.1.6 root 2860: dsp_core.instr_cycle += 4;
1.1 root 2861:
2862: if (value & (1<<numbit)) {
1.1.1.6 root 2863: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2864: newpc = newaddr;
1.1.1.6 root 2865: dsp_core.pc = newpc;
1.1.1.4 root 2866: cur_inst_len = 0;
2867: return;
1.1.1.11 root 2868: }
1.1.1.4 root 2869: ++cur_inst_len;
1.1 root 2870: }
2871:
1.1.1.4 root 2872: static void dsp_jsset_pp(void)
1.1 root 2873: {
1.1.1.4 root 2874: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2875:
1.1.1.4 root 2876: memspace = (cur_inst>>6) & 1;
2877: value = (cur_inst>>8) & BITMASK(6);
2878: numbit = cur_inst & BITMASK(5);
2879: addr = 0xffc0 + value;
2880: value = read_memory(memspace, addr);
1.1.1.6 root 2881: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2882:
1.1.1.6 root 2883: dsp_core.instr_cycle += 4;
1.1 root 2884:
1.1.1.4 root 2885: if (value & (1<<numbit)) {
1.1.1.6 root 2886: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2887: newpc = newaddr;
1.1.1.6 root 2888: dsp_core.pc = newpc;
1.1.1.4 root 2889: cur_inst_len = 0;
2890: return;
1.1.1.11 root 2891: }
1.1.1.4 root 2892: ++cur_inst_len;
1.1 root 2893: }
2894:
1.1.1.4 root 2895: static void dsp_jsset_reg(void)
1.1 root 2896: {
1.1.1.4 root 2897: Uint32 value, numreg, newpc, numbit, newaddr;
1.1.1.11 root 2898:
1.1.1.4 root 2899: numreg = (cur_inst>>8) & BITMASK(6);
1.1 root 2900: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2901: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2902:
1.1.1.4 root 2903: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2904: dsp_pm_read_accu24(numreg, &value);
2905: } else {
1.1.1.6 root 2906: value = dsp_core.registers[numreg];
1.1.1.4 root 2907: }
1.1 root 2908:
1.1.1.6 root 2909: dsp_core.instr_cycle += 4;
1.1 root 2910:
2911: if (value & (1<<numbit)) {
1.1.1.6 root 2912: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2913: newpc = newaddr;
1.1.1.6 root 2914: dsp_core.pc = newpc;
1.1 root 2915: cur_inst_len = 0;
1.1.1.4 root 2916: return;
1.1.1.11 root 2917: }
1.1.1.4 root 2918: ++cur_inst_len;
1.1 root 2919: }
2920:
2921: static void dsp_lua(void)
2922: {
1.1.1.2 root 2923: Uint32 value, srcreg, dstreg, srcsave, srcnew;
2924:
1.1 root 2925: srcreg = (cur_inst>>8) & BITMASK(3);
1.1.1.2 root 2926:
1.1.1.6 root 2927: srcsave = dsp_core.registers[DSP_REG_R0+srcreg];
1.1.1.2 root 2928: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &value);
1.1.1.6 root 2929: srcnew = dsp_core.registers[DSP_REG_R0+srcreg];
2930: dsp_core.registers[DSP_REG_R0+srcreg] = srcsave;
1.1.1.2 root 2931:
1.1.1.11 root 2932: if (cur_inst & (1<<3))
2933: dstreg = DSP_REG_N0 + (cur_inst & BITMASK(3));
2934: else
2935: dstreg = DSP_REG_R0 + (cur_inst & BITMASK(3));
1.1 root 2936:
1.1.1.11 root 2937: dsp_core.agu_move_indirect_instr = 1;
2938: dsp_write_reg(dstreg, srcnew);
1.1.1.6 root 2939: dsp_core.instr_cycle += 2;
1.1 root 2940: }
2941:
1.1.1.3 root 2942: static void dsp_movec_reg(void)
1.1 root 2943: {
1.1.1.4 root 2944: Uint32 numreg1, numreg2, value, dummy;
1.1 root 2945:
2946: /* S1,D2 */
2947: /* S2,D1 */
2948:
2949: numreg2 = (cur_inst>>8) & BITMASK(6);
1.1.1.4 root 2950: numreg1 = cur_inst & BITMASK(6);
1.1 root 2951:
1.1.1.11 root 2952: dsp_core.agu_move_indirect_instr = 1;
2953:
1.1 root 2954: if (cur_inst & (1<<15)) {
2955: /* Write D1 */
2956:
2957: if ((numreg2 == DSP_REG_A) || (numreg2 == DSP_REG_B)) {
1.1.1.11 root 2958: dsp_pm_read_accu24(numreg2, &value);
1.1 root 2959: } else {
1.1.1.6 root 2960: value = dsp_core.registers[numreg2];
1.1 root 2961: }
1.1.1.4 root 2962: dsp_write_reg(numreg1, value);
1.1 root 2963: } else {
2964: /* Read S1 */
1.1.1.4 root 2965: if (numreg1 == DSP_REG_SSH) {
2966: dsp_stack_pop(&value, &dummy);
1.1.1.11 root 2967: }
1.1.1.4 root 2968: else {
1.1.1.6 root 2969: value = dsp_core.registers[numreg1];
1.1.1.4 root 2970: }
1.1 root 2971:
1.1.1.11 root 2972: dsp_write_reg(numreg2, value);
1.1 root 2973: }
2974: }
2975:
1.1.1.3 root 2976: static void dsp_movec_aa(void)
1.1 root 2977: {
1.1.1.4 root 2978: Uint32 numreg, addr, memspace, value, dummy;
1.1 root 2979:
2980: /* x:aa,D1 */
2981: /* S1,x:aa */
2982: /* y:aa,D1 */
2983: /* S1,y:aa */
2984:
1.1.1.4 root 2985: numreg = cur_inst & BITMASK(6);
1.1 root 2986: addr = (cur_inst>>8) & BITMASK(6);
2987: memspace = (cur_inst>>6) & 1;
2988:
2989: if (cur_inst & (1<<15)) {
2990: /* Write D1 */
1.1.1.4 root 2991: value = read_memory(memspace, addr);
1.1.1.11 root 2992: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 2993: dsp_write_reg(numreg, value);
1.1 root 2994: } else {
2995: /* Read S1 */
1.1.1.4 root 2996: if (numreg == DSP_REG_SSH) {
2997: dsp_stack_pop(&value, &dummy);
1.1.1.11 root 2998: }
1.1.1.4 root 2999: else {
1.1.1.6 root 3000: value = dsp_core.registers[numreg];
1.1.1.4 root 3001: }
3002: write_memory(memspace, addr, value);
1.1 root 3003: }
3004: }
3005:
1.1.1.3 root 3006: static void dsp_movec_imm(void)
1.1 root 3007: {
1.1.1.4 root 3008: Uint32 numreg, value;
1.1 root 3009:
3010: /* #xx,D1 */
1.1.1.4 root 3011: numreg = cur_inst & BITMASK(6);
3012: value = (cur_inst>>8) & BITMASK(8);
1.1.1.11 root 3013: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3014: dsp_write_reg(numreg, value);
1.1 root 3015: }
3016:
1.1.1.3 root 3017: static void dsp_movec_ea(void)
1.1 root 3018: {
1.1.1.4 root 3019: Uint32 numreg, addr, memspace, ea_mode, value, dummy;
1.1 root 3020: int retour;
3021:
3022: /* x:ea,D1 */
3023: /* S1,x:ea */
3024: /* y:ea,D1 */
3025: /* S1,y:ea */
3026: /* #xxxx,D1 */
3027:
1.1.1.4 root 3028: numreg = cur_inst & BITMASK(6);
1.1 root 3029: ea_mode = (cur_inst>>8) & BITMASK(6);
3030: memspace = (cur_inst>>6) & 1;
3031:
3032: if (cur_inst & (1<<15)) {
3033: /* Write D1 */
3034: retour = dsp_calc_ea(ea_mode, &addr);
3035: if (retour) {
1.1.1.4 root 3036: value = addr;
1.1 root 3037: } else {
1.1.1.4 root 3038: value = read_memory(memspace, addr);
1.1 root 3039: }
1.1.1.11 root 3040: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3041: dsp_write_reg(numreg, value);
1.1 root 3042: } else {
3043: /* Read S1 */
1.1.1.4 root 3044: dsp_calc_ea(ea_mode, &addr);
3045: if (numreg == DSP_REG_SSH) {
3046: dsp_stack_pop(&value, &dummy);
1.1.1.11 root 3047: }
1.1.1.4 root 3048: else {
1.1.1.6 root 3049: value = dsp_core.registers[numreg];
1.1.1.4 root 3050: }
3051: write_memory(memspace, addr, value);
1.1 root 3052: }
3053: }
3054:
1.1.1.4 root 3055: static void dsp_movem_aa(void)
1.1 root 3056: {
1.1.1.4 root 3057: Uint32 numreg, addr, value, dummy;
1.1 root 3058:
3059: numreg = cur_inst & BITMASK(6);
1.1.1.4 root 3060: addr = (cur_inst>>8) & BITMASK(6);
1.1 root 3061:
1.1.1.4 root 3062: if (cur_inst & (1<<15)) {
3063: /* Write D */
3064: value = read_memory_p(addr);
1.1.1.11 root 3065: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3066: dsp_write_reg(numreg, value);
1.1 root 3067: } else {
1.1.1.4 root 3068: /* Read S */
3069: if (numreg == DSP_REG_SSH) {
3070: dsp_stack_pop(&value, &dummy);
1.1.1.11 root 3071: }
1.1.1.4 root 3072: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11 root 3073: dsp_pm_read_accu24(numreg, &value);
3074: }
1.1.1.4 root 3075: else {
1.1.1.6 root 3076: value = dsp_core.registers[numreg];
1.1.1.4 root 3077: }
3078: write_memory(DSP_SPACE_P, addr, value);
3079: }
1.1 root 3080:
1.1.1.6 root 3081: dsp_core.instr_cycle += 4;
1.1.1.4 root 3082: }
3083:
3084: static void dsp_movem_ea(void)
3085: {
3086: Uint32 numreg, addr, ea_mode, value, dummy;
3087:
3088: numreg = cur_inst & BITMASK(6);
3089: ea_mode = (cur_inst>>8) & BITMASK(6);
3090: dsp_calc_ea(ea_mode, &addr);
1.1 root 3091:
3092: if (cur_inst & (1<<15)) {
3093: /* Write D */
1.1.1.4 root 3094: value = read_memory_p(addr);
1.1.1.11 root 3095: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3096: dsp_write_reg(numreg, value);
1.1 root 3097: } else {
3098: /* Read S */
1.1.1.4 root 3099: if (numreg == DSP_REG_SSH) {
3100: dsp_stack_pop(&value, &dummy);
1.1.1.11 root 3101: }
1.1.1.4 root 3102: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11 root 3103: dsp_pm_read_accu24(numreg, &value);
3104: }
1.1.1.4 root 3105: else {
1.1.1.6 root 3106: value = dsp_core.registers[numreg];
1.1 root 3107: }
3108: write_memory(DSP_SPACE_P, addr, value);
3109: }
3110:
1.1.1.6 root 3111: dsp_core.instr_cycle += 4;
1.1 root 3112: }
3113:
3114: static void dsp_movep_0(void)
3115: {
3116: /* S,x:pp */
3117: /* x:pp,D */
3118: /* S,y:pp */
3119: /* y:pp,D */
1.1.1.11 root 3120:
1.1.1.4 root 3121: Uint32 addr, memspace, numreg, value, dummy;
1.1 root 3122:
3123: addr = 0xffc0 + (cur_inst & BITMASK(6));
3124: memspace = (cur_inst>>16) & 1;
3125: numreg = (cur_inst>>8) & BITMASK(6);
3126:
3127: if (cur_inst & (1<<15)) {
3128: /* Write pp */
3129: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11 root 3130: dsp_pm_read_accu24(numreg, &value);
1.1.1.4 root 3131: }
3132: else if (numreg == DSP_REG_SSH) {
3133: dsp_stack_pop(&value, &dummy);
3134: }
3135: else {
1.1.1.6 root 3136: value = dsp_core.registers[numreg];
1.1 root 3137: }
3138: write_memory(memspace, addr, value);
3139: } else {
3140: /* Read pp */
3141: value = read_memory(memspace, addr);
1.1.1.11 root 3142: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3143: dsp_write_reg(numreg, value);
1.1 root 3144: }
1.1.1.4 root 3145:
1.1.1.6 root 3146: dsp_core.instr_cycle += 2;
1.1 root 3147: }
3148:
3149: static void dsp_movep_1(void)
3150: {
3151: /* p:ea,x:pp */
3152: /* x:pp,p:ea */
3153: /* p:ea,y:pp */
3154: /* y:pp,p:ea */
3155:
1.1.1.2 root 3156: Uint32 xyaddr, memspace, paddr;
1.1 root 3157:
3158: xyaddr = 0xffc0 + (cur_inst & BITMASK(6));
3159: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &paddr);
3160: memspace = (cur_inst>>16) & 1;
3161:
3162: if (cur_inst & (1<<15)) {
3163: /* Write pp */
1.1.1.4 root 3164: write_memory(memspace, xyaddr, read_memory_p(paddr));
1.1 root 3165: } else {
3166: /* Read pp */
3167: write_memory(DSP_SPACE_P, paddr, read_memory(memspace, xyaddr));
3168: }
1.1.1.4 root 3169:
1.1.1.7 root 3170: /* Movep is 4 cycles, but according to the motorola doc, */
3171: /* movep from p memory to x or y peripheral memory takes */
3172: /* 2 more cycles, so +4 cycles at total */
3173: dsp_core.instr_cycle += 4;
1.1 root 3174: }
3175:
1.1.1.4 root 3176: static void dsp_movep_23(void)
1.1 root 3177: {
3178: /* x:ea,x:pp */
3179: /* y:ea,x:pp */
3180: /* #xxxxxx,x:pp */
3181: /* x:pp,x:ea */
3182: /* x:pp,y:pp */
3183: /* x:ea,y:pp */
3184: /* y:ea,y:pp */
3185: /* #xxxxxx,y:pp */
3186: /* y:pp,y:ea */
3187: /* y:pp,x:ea */
3188:
1.1.1.2 root 3189: Uint32 addr, peraddr, easpace, perspace, ea_mode;
1.1 root 3190: int retour;
3191:
3192: peraddr = 0xffc0 + (cur_inst & BITMASK(6));
3193: perspace = (cur_inst>>16) & 1;
1.1.1.11 root 3194:
1.1 root 3195: ea_mode = (cur_inst>>8) & BITMASK(6);
3196: easpace = (cur_inst>>6) & 1;
3197: retour = dsp_calc_ea(ea_mode, &addr);
3198:
3199: if (cur_inst & (1<<15)) {
3200: /* Write pp */
1.1.1.11 root 3201:
1.1 root 3202: if (retour) {
3203: write_memory(perspace, peraddr, addr);
3204: } else {
3205: write_memory(perspace, peraddr, read_memory(easpace, addr));
3206: }
3207: } else {
3208: /* Read pp */
3209: write_memory(easpace, addr, read_memory(perspace, peraddr));
3210: }
1.1.1.4 root 3211:
1.1.1.6 root 3212: dsp_core.instr_cycle += 2;
1.1 root 3213: }
3214:
3215: static void dsp_norm(void)
3216: {
1.1.1.2 root 3217: Uint32 cursr,cur_e, cur_euz, dest[3], numreg, rreg;
3218: Uint16 newsr;
1.1 root 3219:
1.1.1.6 root 3220: cursr = dsp_core.registers[DSP_REG_SR];
1.1 root 3221: cur_e = (cursr>>DSP_SR_E) & 1; /* E */
3222: cur_euz = ~cur_e; /* (not E) and U and (not Z) */
3223: cur_euz &= (cursr>>DSP_SR_U) & 1;
3224: cur_euz &= ~((cursr>>DSP_SR_Z) & 1);
3225: cur_euz &= 1;
3226:
3227: numreg = (cur_inst>>3) & 1;
1.1.1.6 root 3228: dest[0] = dsp_core.registers[DSP_REG_A2+numreg];
3229: dest[1] = dsp_core.registers[DSP_REG_A1+numreg];
3230: dest[2] = dsp_core.registers[DSP_REG_A0+numreg];
1.1 root 3231: rreg = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3232:
3233: if (cur_euz) {
3234: newsr = dsp_asl56(dest);
1.1.1.6 root 3235: --dsp_core.registers[rreg];
3236: dsp_core.registers[rreg] &= BITMASK(16);
1.1 root 3237: } else if (cur_e) {
3238: newsr = dsp_asr56(dest);
1.1.1.6 root 3239: ++dsp_core.registers[rreg];
3240: dsp_core.registers[rreg] &= BITMASK(16);
1.1 root 3241: } else {
3242: newsr = 0;
3243: }
3244:
1.1.1.6 root 3245: dsp_core.registers[DSP_REG_A2+numreg] = dest[0];
3246: dsp_core.registers[DSP_REG_A1+numreg] = dest[1];
3247: dsp_core.registers[DSP_REG_A0+numreg] = dest[2];
1.1.1.2 root 3248:
1.1.1.6 root 3249: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 3250:
1.1.1.6 root 3251: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
3252: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 3253: }
3254:
3255: static void dsp_ori(void)
3256: {
1.1.1.2 root 3257: Uint32 regnum, value;
1.1 root 3258:
3259: value = (cur_inst >> 8) & BITMASK(8);
3260: regnum = cur_inst & BITMASK(2);
3261: switch(regnum) {
3262: case 0:
3263: /* mr */
1.1.1.6 root 3264: dsp_core.registers[DSP_REG_SR] |= value<<8;
1.1 root 3265: break;
3266: case 1:
3267: /* ccr */
1.1.1.6 root 3268: dsp_core.registers[DSP_REG_SR] |= value;
1.1 root 3269: break;
3270: case 2:
3271: /* omr */
1.1.1.6 root 3272: dsp_core.registers[DSP_REG_OMR] |= value;
1.1 root 3273: break;
3274: }
3275: }
3276:
1.1.1.3 root 3277: /*
3278: REP instruction parameter encoding
3279:
3280: xxxxxxxx 00xxxxxx 0xxxxxxx aa
3281: xxxxxxxx 01xxxxxx 0xxxxxxx ea
3282: xxxxxxxx YYxxxxxx 1xxxxxxx imm
3283: xxxxxxxx 11xxxxxx 0xxxxxxx reg
3284: */
3285:
3286: static void dsp_rep_aa(void)
1.1 root 3287: {
3288: /* x:aa */
3289: /* y:aa */
1.1.1.6 root 3290: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3291: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3292: dsp_core.loop_rep = 1; /* We are now running rep */
1.1 root 3293:
1.1.1.6 root 3294: dsp_core.registers[DSP_REG_LC]=read_memory((cur_inst>>6) & 1,(cur_inst>>8) & BITMASK(6));
1.1.1.4 root 3295:
1.1.1.6 root 3296: dsp_core.instr_cycle += 2;
1.1 root 3297: }
3298:
1.1.1.3 root 3299: static void dsp_rep_imm(void)
1.1 root 3300: {
3301: /* #xxx */
3302:
1.1.1.6 root 3303: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3304: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3305: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3306:
1.1.1.6 root 3307: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
1.1.1.3 root 3308: + ((cur_inst & BITMASK(4))<<8);
1.1.1.4 root 3309:
1.1.1.6 root 3310: dsp_core.instr_cycle += 2;
1.1 root 3311: }
3312:
1.1.1.3 root 3313: static void dsp_rep_ea(void)
1.1 root 3314: {
1.1.1.2 root 3315: Uint32 value;
1.1 root 3316:
3317: /* x:ea */
3318: /* y:ea */
3319:
1.1.1.6 root 3320: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3321: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3322: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3323:
1.1 root 3324: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&value);
1.1.1.6 root 3325: dsp_core.registers[DSP_REG_LC]= read_memory((cur_inst>>6) & 1, value);
1.1.1.4 root 3326:
1.1.1.6 root 3327: dsp_core.instr_cycle += 2;
1.1 root 3328: }
3329:
1.1.1.3 root 3330: static void dsp_rep_reg(void)
1.1 root 3331: {
1.1.1.2 root 3332: Uint32 numreg;
1.1 root 3333:
3334: /* R */
3335:
1.1.1.6 root 3336: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3337: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3338: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3339:
1.1 root 3340: numreg = (cur_inst>>8) & BITMASK(6);
3341: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11 root 3342: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
1.1 root 3343: } else {
1.1.1.6 root 3344: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
1.1 root 3345: }
1.1.1.6 root 3346: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.4 root 3347:
1.1.1.6 root 3348: dsp_core.instr_cycle += 2;
1.1 root 3349: }
3350:
3351: static void dsp_reset(void)
3352: {
1.1.1.13! root 3353: /* Clear the IPR register */
! 3354: write_memory(DSP_SPACE_X, 0xffc0 + DSP_IPR, 0);
! 3355:
! 3356: /* Software reset all on-chip peripherals */
! 3357:
! 3358: /* HOST_HCR x:$FFE8 : clear the full register */
! 3359: write_memory(DSP_SPACE_X, 0xffc0 + DSP_HOST_HCR, 0);
! 3360:
! 3361: /* HOST_ICR $0 : clear the full register */
! 3362: dsp_core_write_host(CPU_HOST_ICR, 0);
! 3363:
! 3364: /* HOST_CVR $1 : set the register to $12 */
! 3365: dsp_core_write_host(CPU_HOST_CVR, 0x12);
! 3366:
! 3367: /* HOST_ISR $2 : set the bits TRDY and TXDE 1, other bits to 0 */
! 3368: dsp_core.hostport[CPU_HOST_ISR] = (1<<CPU_HOST_ISR_TRDY)|(1<<CPU_HOST_ISR_TXDE);
! 3369:
! 3370: /* HOST_IVR $3 : set the register to $0f */
! 3371: dsp_core_write_host(CPU_HOST_IVR, 0x0f);
! 3372:
! 3373: /* SSI_CRA x:$FFEC : clear the full register */
! 3374: write_memory(DSP_SPACE_X, 0xffc0 + DSP_SSI_CRA, 0);
! 3375:
! 3376: /* SSI_CRB x:$FFED : clear the full register */
! 3377: write_memory(DSP_SPACE_X, 0xffc0 + DSP_SSI_CRB, 0);
! 3378:
! 3379: /* SSI_SR x:$FFEE : set the register to $40 */
! 3380: write_memory(DSP_SPACE_X, 0xffc0 + DSP_SSI_SR, 1<<DSP_SSI_SR_TDE);
! 3381:
! 3382: /* SCI_SCR x:$FFF0 : clear the full register (not used in the Falcon) */
! 3383: write_memory(DSP_SPACE_X, 0xffc0 + DSP_SCI_SCR, 0);
! 3384:
! 3385: /* SCI_SSR x:$FFF1 : clear the register to $3 (not used in the Falcon) */
! 3386: write_memory(DSP_SPACE_X, 0xffc0 + DSP_SCI_SSR, 3);
! 3387:
! 3388: /* SCI_SCCR x:$FFF2 : clear the full register (not used in the Falcon) */
! 3389: write_memory(DSP_SPACE_X, 0xffc0 + DSP_SCI_SCCR, 0);
! 3390:
1.1.1.6 root 3391: dsp_core.instr_cycle += 2;
1.1 root 3392: }
3393:
3394: static void dsp_rti(void)
3395: {
1.1.1.2 root 3396: Uint32 newpc = 0, newsr = 0;
1.1 root 3397:
3398: dsp_stack_pop(&newpc, &newsr);
1.1.1.6 root 3399: dsp_core.pc = newpc;
3400: dsp_core.registers[DSP_REG_SR] = newsr;
1.1 root 3401: cur_inst_len = 0;
1.1.1.4 root 3402:
1.1.1.6 root 3403: dsp_core.instr_cycle += 2;
1.1 root 3404: }
3405:
3406: static void dsp_rts(void)
3407: {
1.1.1.2 root 3408: Uint32 newpc = 0, newsr;
1.1 root 3409:
3410: dsp_stack_pop(&newpc, &newsr);
1.1.1.6 root 3411: dsp_core.pc = newpc;
1.1 root 3412: cur_inst_len = 0;
1.1.1.4 root 3413:
1.1.1.6 root 3414: dsp_core.instr_cycle += 2;
1.1 root 3415: }
3416:
3417: static void dsp_stop(void)
3418: {
1.1.1.6 root 3419: LOG_TRACE(TRACE_DSP_STATE, "Dsp: STOP instruction\n");
1.1 root 3420: }
3421:
3422: static void dsp_swi(void)
3423: {
3424: /* Raise interrupt p:0x0006 */
1.1.1.6 root 3425: dsp_core.instr_cycle += 6;
1.1 root 3426: }
3427:
3428: static void dsp_tcc(void)
3429: {
1.1.1.6 root 3430: Uint32 cc_code, regsrc1, regdest1;
1.1.1.2 root 3431: Uint32 regsrc2, regdest2;
1.1.1.6 root 3432: Uint32 val0, val1, val2;
1.1.1.11 root 3433:
1.1 root 3434: cc_code = (cur_inst>>12) & BITMASK(4);
3435:
3436: if (dsp_calc_cc(cc_code)) {
3437: regsrc1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][0];
1.1.1.2 root 3438: regdest1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][1];
1.1 root 3439:
3440: /* Read S1 */
1.1.1.7 root 3441: if (regsrc1 == DSP_REG_A) {
3442: val0 = dsp_core.registers[DSP_REG_A0];
3443: val1 = dsp_core.registers[DSP_REG_A1];
3444: val2 = dsp_core.registers[DSP_REG_A2];
3445: }
3446: else if (regsrc1 == DSP_REG_B) {
3447: val0 = dsp_core.registers[DSP_REG_B0];
3448: val1 = dsp_core.registers[DSP_REG_B1];
3449: val2 = dsp_core.registers[DSP_REG_B2];
3450: }
3451: else {
1.1.1.6 root 3452: val0 = 0;
3453: val1 = dsp_core.registers[regsrc1];
1.1.1.7 root 3454: val2 = val1 & (1<<23) ? 0xff : 0x0;
1.1 root 3455: }
1.1.1.11 root 3456:
1.1 root 3457: /* Write D1 */
1.1.1.7 root 3458: if (regdest1 == DSP_REG_A) {
3459: dsp_core.registers[DSP_REG_A2] = val2;
3460: dsp_core.registers[DSP_REG_A1] = val1;
3461: dsp_core.registers[DSP_REG_A0] = val0;
3462: }
3463: else {
3464: dsp_core.registers[DSP_REG_B2] = val2;
3465: dsp_core.registers[DSP_REG_B1] = val1;
3466: dsp_core.registers[DSP_REG_B0] = val0;
3467: }
1.1 root 3468:
3469: /* S2,D2 transfer */
3470: if (cur_inst & (1<<16)) {
1.1.1.2 root 3471: regsrc2 = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3472: regdest2 = DSP_REG_R0+(cur_inst & BITMASK(3));
1.1 root 3473:
1.1.1.11 root 3474: dsp_core.agu_move_indirect_instr = 1;
3475: dsp_write_reg(regdest2, dsp_core.registers[regsrc2]);
1.1 root 3476: }
3477: }
3478: }
3479:
3480: static void dsp_wait(void)
3481: {
1.1.1.6 root 3482: LOG_TRACE(TRACE_DSP_STATE, "Dsp: WAIT instruction\n");
1.1 root 3483: }
3484:
1.1.1.2 root 3485: static int dsp_pm_read_accu24(int numreg, Uint32 *dest)
1.1 root 3486: {
1.1.1.4 root 3487: Uint32 scaling, value, reg;
1.1.1.7 root 3488: int got_limited = 0;
1.1 root 3489:
3490: /* Read an accumulator, stores it limited */
3491:
1.1.1.6 root 3492: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
1.1.1.4 root 3493: reg = numreg & 1;
1.1 root 3494:
1.1.1.6 root 3495: value = (dsp_core.registers[DSP_REG_A2+reg]) << 24;
3496: value += dsp_core.registers[DSP_REG_A1+reg];
1.1 root 3497:
3498: switch(scaling) {
3499: case 0:
1.1.1.4 root 3500: /* No scaling */
3501: break;
3502: case 1:
3503: /* scaling down */
3504: value >>= 1;
1.1 root 3505: break;
3506: case 2:
1.1.1.4 root 3507: /* scaling up */
3508: value <<= 1;
1.1.1.6 root 3509: value |= (dsp_core.registers[DSP_REG_A0+reg]>>23) & 1;
1.1 root 3510: break;
1.1.1.4 root 3511: /* indeterminate */
1.1.1.11 root 3512: case 3:
1.1.1.4 root 3513: break;
3514: }
3515:
3516: /* limiting ? */
3517: value &= BITMASK(24);
3518:
1.1.1.6 root 3519: if (dsp_core.registers[DSP_REG_A2+reg] == 0) {
1.1.1.4 root 3520: if (value <= 0x007fffff) {
3521: /* No limiting */
3522: *dest=value;
3523: return 0;
1.1.1.11 root 3524: }
1.1.1.4 root 3525: }
3526:
1.1.1.6 root 3527: if (dsp_core.registers[DSP_REG_A2+reg] == 0xff) {
1.1.1.4 root 3528: if (value >= 0x00800000) {
3529: /* No limiting */
3530: *dest=value;
3531: return 0;
1.1.1.11 root 3532: }
1.1 root 3533: }
3534:
1.1.1.6 root 3535: if (dsp_core.registers[DSP_REG_A2+reg] & (1<<7)) {
1.1 root 3536: /* Limited to maximum negative value */
3537: *dest=0x00800000;
1.1.1.6 root 3538: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
1.1.1.2 root 3539: got_limited=1;
1.1 root 3540: } else {
3541: /* Limited to maximal positive value */
3542: *dest=0x007fffff;
1.1.1.6 root 3543: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
1.1.1.2 root 3544: got_limited=1;
1.1.1.11 root 3545: }
1.1.1.2 root 3546:
3547: return got_limited;
1.1 root 3548: }
3549:
3550: static void dsp_pm_0(void)
3551: {
1.1.1.6 root 3552: Uint32 memspace, numreg, addr, save_accu, save_xy0;
1.1 root 3553: /*
3554: 0000 100d 00mm mrrr S,x:ea x0,D
3555: 0000 100d 10mm mrrr S,y:ea y0,D
3556: */
3557: memspace = (cur_inst>>15) & 1;
3558: numreg = (cur_inst>>16) & 1;
1.1.1.6 root 3559: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &addr);
3560:
1.1.1.11 root 3561: /* Save A or B */
1.1.1.6 root 3562: dsp_pm_read_accu24(numreg, &save_accu);
1.1 root 3563:
1.1.1.6 root 3564: /* Save X0 or Y0 */
3565: save_xy0 = dsp_core.registers[DSP_REG_X0+(memspace<<1)];
3566:
3567: /* Execute parallel instruction */
3568: opcodes_alu[cur_inst & BITMASK(8)]();
3569:
1.1.1.11 root 3570: /* Move [A|B] to [x|y]:ea */
1.1.1.6 root 3571: write_memory(memspace, addr, save_accu);
3572:
3573: /* Move [x|y]0 to [A|B] */
3574: dsp_core.registers[DSP_REG_A0+numreg] = 0;
3575: dsp_core.registers[DSP_REG_A1+numreg] = save_xy0;
1.1.1.7 root 3576: dsp_core.registers[DSP_REG_A2+numreg] = save_xy0 & (1<<23) ? 0xff : 0x0;
1.1 root 3577: }
3578:
3579: static void dsp_pm_1(void)
3580: {
1.1.1.6 root 3581: Uint32 memspace, numreg1, numreg2, value, xy_addr, retour, save_1, save_2;
1.1 root 3582: /*
1.1.1.11 root 3583: 0001 ffdf w0mm mrrr x:ea,D1 S2,D2
1.1 root 3584: S1,x:ea S2,D2
3585: #xxxxxx,D1 S2,D2
1.1.1.11 root 3586: 0001 deff w1mm mrrr S1,D1 y:ea,D2
1.1 root 3587: S1,D1 S2,y:ea
3588: S1,D1 #xxxxxx,D2
3589: */
3590: value = (cur_inst>>8) & BITMASK(6);
1.1.1.11 root 3591: retour = dsp_calc_ea(value, &xy_addr);
1.1 root 3592: memspace = (cur_inst>>14) & 1;
1.1.1.6 root 3593: numreg1 = numreg2 = DSP_REG_NULL;
1.1 root 3594:
3595: if (memspace) {
3596: /* Y: */
3597: switch((cur_inst>>16) & BITMASK(2)) {
1.1.1.6 root 3598: case 0: numreg1 = DSP_REG_Y0; break;
3599: case 1: numreg1 = DSP_REG_Y1; break;
3600: case 2: numreg1 = DSP_REG_A; break;
3601: case 3: numreg1 = DSP_REG_B; break;
1.1 root 3602: }
3603: } else {
3604: /* X: */
3605: switch((cur_inst>>18) & BITMASK(2)) {
1.1.1.6 root 3606: case 0: numreg1 = DSP_REG_X0; break;
3607: case 1: numreg1 = DSP_REG_X1; break;
3608: case 2: numreg1 = DSP_REG_A; break;
3609: case 3: numreg1 = DSP_REG_B; break;
1.1 root 3610: }
3611: }
3612:
3613: if (cur_inst & (1<<15)) {
3614: /* Write D1 */
1.1.1.6 root 3615: if (retour)
3616: save_1 = xy_addr;
3617: else
3618: save_1 = read_memory(memspace, xy_addr);
1.1 root 3619: } else {
3620: /* Read S1 */
1.1.1.6 root 3621: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
3622: dsp_pm_read_accu24(numreg1, &save_1);
3623: else
3624: save_1 = dsp_core.registers[numreg1];
1.1 root 3625: }
1.1.1.11 root 3626:
1.1 root 3627: /* S2 */
3628: if (memspace) {
3629: /* Y: */
1.1.1.6 root 3630: numreg2 = DSP_REG_A + ((cur_inst>>19) & 1);
1.1 root 3631: } else {
3632: /* X: */
1.1.1.6 root 3633: numreg2 = DSP_REG_A + ((cur_inst>>17) & 1);
1.1.1.11 root 3634: }
1.1.1.6 root 3635: dsp_pm_read_accu24(numreg2, &save_2);
1.1.1.11 root 3636:
1.1.1.6 root 3637:
3638: /* Execute parallel instruction */
3639: opcodes_alu[cur_inst & BITMASK(8)]();
3640:
3641:
3642: /* Write parallel move values */
3643: if (cur_inst & (1<<15)) {
3644: /* Write D1 */
1.1.1.11 root 3645: dsp_write_reg(numreg1, save_1);
1.1.1.6 root 3646: } else {
3647: /* Read S1 */
3648: write_memory(memspace, xy_addr, save_1);
3649: }
3650:
3651: /* S2 -> D2 */
1.1 root 3652: if (memspace) {
3653: /* Y: */
1.1.1.6 root 3654: numreg2 = DSP_REG_X0 + ((cur_inst>>18) & 1);
1.1 root 3655: } else {
3656: /* X: */
1.1.1.6 root 3657: numreg2 = DSP_REG_Y0 + ((cur_inst>>16) & 1);
1.1.1.11 root 3658: }
1.1.1.6 root 3659: dsp_core.registers[numreg2] = save_2;
1.1 root 3660: }
3661:
3662: static void dsp_pm_2(void)
3663: {
1.1.1.2 root 3664: Uint32 dummy;
1.1 root 3665: /*
3666: 0010 0000 0000 0000 nop
3667: 0010 0000 010m mrrr R update
3668: 0010 00ee eeed dddd S,D
3669: 001d dddd iiii iiii #xx,D
3670: */
1.1.1.4 root 3671: if ((cur_inst & 0xffff00) == 0x200000) {
1.1.1.6 root 3672: /* Execute parallel instruction */
3673: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3674: return;
3675: }
3676:
1.1.1.4 root 3677: if ((cur_inst & 0xffe000) == 0x204000) {
1.1 root 3678: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &dummy);
1.1.1.6 root 3679: /* Execute parallel instruction */
3680: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3681: return;
3682: }
3683:
1.1.1.4 root 3684: if ((cur_inst & 0xfc0000) == 0x200000) {
1.1 root 3685: dsp_pm_2_2();
3686: return;
3687: }
3688:
3689: dsp_pm_3();
3690: }
3691:
3692: static void dsp_pm_2_2(void)
3693: {
3694: /*
3695: 0010 00ee eeed dddd S,D
3696: */
1.1.1.6 root 3697: Uint32 srcreg, dstreg, save_reg;
1.1.1.11 root 3698:
1.1 root 3699: srcreg = (cur_inst >> 13) & BITMASK(5);
3700: dstreg = (cur_inst >> 8) & BITMASK(5);
3701:
1.1.1.6 root 3702: if ((srcreg == DSP_REG_A) || (srcreg == DSP_REG_B))
3703: /* Accu to register: limited 24 bits */
3704: dsp_pm_read_accu24(srcreg, &save_reg);
3705: else
3706: save_reg = dsp_core.registers[srcreg];
3707:
3708: /* Execute parallel instruction */
3709: opcodes_alu[cur_inst & BITMASK(8)]();
3710:
3711: /* Write reg */
1.1.1.11 root 3712: dsp_core.agu_move_indirect_instr = 1;
3713: dsp_write_reg(dstreg, save_reg);
1.1 root 3714: }
3715:
3716: static void dsp_pm_3(void)
3717: {
1.1.1.6 root 3718: Uint32 dstreg, srcvalue;
1.1 root 3719: /*
3720: 001d dddd iiii iiii #xx,R
3721: */
1.1.1.6 root 3722:
3723: /* Execute parallel instruction */
3724: opcodes_alu[cur_inst & BITMASK(8)]();
3725:
3726: /* Write reg */
3727: dstreg = (cur_inst >> 16) & BITMASK(5);
1.1 root 3728: srcvalue = (cur_inst >> 8) & BITMASK(8);
3729:
1.1.1.6 root 3730: switch(dstreg) {
1.1 root 3731: case DSP_REG_X0:
3732: case DSP_REG_X1:
3733: case DSP_REG_Y0:
3734: case DSP_REG_Y1:
3735: case DSP_REG_A:
3736: case DSP_REG_B:
3737: srcvalue <<= 16;
3738: break;
3739: }
3740:
1.1.1.11 root 3741: dsp_core.agu_move_indirect_instr = 1;
3742: dsp_write_reg(dstreg, srcvalue);
1.1 root 3743: }
3744:
3745: static void dsp_pm_4(void)
3746: {
3747: /*
1.1.1.4 root 3748: 0100 l0ll w0aa aaaa l:aa,D
1.1 root 3749: S,l:aa
1.1.1.4 root 3750: 0100 l0ll w1mm mrrr l:ea,D
1.1 root 3751: S,l:ea
1.1.1.4 root 3752: 01dd 0ddd w0aa aaaa x:aa,D
1.1 root 3753: S,x:aa
1.1.1.4 root 3754: 01dd 0ddd w1mm mrrr x:ea,D
1.1 root 3755: S,x:ea
3756: #xxxxxx,D
1.1.1.4 root 3757: 01dd 1ddd w0aa aaaa y:aa,D
1.1 root 3758: S,y:aa
1.1.1.4 root 3759: 01dd 1ddd w1mm mrrr y:ea,D
1.1 root 3760: S,y:ea
3761: #xxxxxx,D
3762: */
1.1.1.4 root 3763: if ((cur_inst & 0xf40000)==0x400000) {
3764: dsp_pm_4x();
1.1 root 3765: return;
3766: }
3767:
3768: dsp_pm_5();
3769: }
3770:
1.1.1.4 root 3771: static void dsp_pm_4x(void)
1.1 root 3772: {
1.1.1.6 root 3773: Uint32 value, numreg, l_addr, save_lx, save_ly;
1.1 root 3774: /*
1.1.1.4 root 3775: 0100 l0ll w0aa aaaa l:aa,D
3776: S,l:aa
3777: 0100 l0ll w1mm mrrr l:ea,D
3778: S,l:ea
1.1 root 3779: */
1.1.1.4 root 3780: value = (cur_inst>>8) & BITMASK(6);
3781: if (cur_inst & (1<<14)) {
1.1.1.11 root 3782: dsp_calc_ea(value, &l_addr);
1.1.1.4 root 3783: } else {
3784: l_addr = value;
3785: }
3786:
1.1 root 3787: numreg = (cur_inst>>16) & BITMASK(2);
3788: numreg |= (cur_inst>>17) & (1<<2);
3789:
3790: if (cur_inst & (1<<15)) {
3791: /* Write D */
1.1.1.6 root 3792: save_lx = read_memory(DSP_SPACE_X,l_addr);
3793: save_ly = read_memory(DSP_SPACE_Y,l_addr);
3794: }
3795: else {
3796: /* Read S */
1.1.1.4 root 3797: switch(numreg) {
3798: case 0:
3799: /* A10 */
1.1.1.6 root 3800: save_lx = dsp_core.registers[DSP_REG_A1];
3801: save_ly = dsp_core.registers[DSP_REG_A0];
1.1.1.4 root 3802: break;
3803: case 1:
3804: /* B10 */
1.1.1.6 root 3805: save_lx = dsp_core.registers[DSP_REG_B1];
3806: save_ly = dsp_core.registers[DSP_REG_B0];
1.1.1.4 root 3807: break;
3808: case 2:
3809: /* X */
1.1.1.6 root 3810: save_lx = dsp_core.registers[DSP_REG_X1];
3811: save_ly = dsp_core.registers[DSP_REG_X0];
1.1.1.4 root 3812: break;
3813: case 3:
3814: /* Y */
1.1.1.6 root 3815: save_lx = dsp_core.registers[DSP_REG_Y1];
3816: save_ly = dsp_core.registers[DSP_REG_Y0];
1.1.1.4 root 3817: break;
3818: case 4:
3819: /* A */
1.1.1.6 root 3820: if (dsp_pm_read_accu24(DSP_REG_A, &save_lx)) {
3821: /* Was limited, set lower part */
3822: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3823: } else {
3824: /* Not limited */
3825: save_ly = dsp_core.registers[DSP_REG_A0];
3826: }
1.1.1.4 root 3827: break;
3828: case 5:
3829: /* B */
1.1.1.6 root 3830: if (dsp_pm_read_accu24(DSP_REG_B, &save_lx)) {
3831: /* Was limited, set lower part */
3832: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3833: } else {
3834: /* Not limited */
3835: save_ly = dsp_core.registers[DSP_REG_B0];
3836: }
1.1.1.4 root 3837: break;
3838: case 6:
3839: /* AB */
1.1.1.11 root 3840: dsp_pm_read_accu24(DSP_REG_A, &save_lx);
3841: dsp_pm_read_accu24(DSP_REG_B, &save_ly);
1.1.1.4 root 3842: break;
3843: case 7:
3844: /* BA */
1.1.1.11 root 3845: dsp_pm_read_accu24(DSP_REG_B, &save_lx);
3846: dsp_pm_read_accu24(DSP_REG_A, &save_ly);
1.1.1.4 root 3847: break;
1.1 root 3848: }
1.1.1.6 root 3849: }
1.1 root 3850:
1.1.1.6 root 3851: /* Execute parallel instruction */
3852: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3853:
1.1.1.6 root 3854:
3855: if (cur_inst & (1<<15)) {
3856: /* Write D */
1.1.1.4 root 3857: switch(numreg) {
1.1.1.6 root 3858: case 0: /* A10 */
3859: dsp_core.registers[DSP_REG_A1] = save_lx;
3860: dsp_core.registers[DSP_REG_A0] = save_ly;
1.1.1.4 root 3861: break;
1.1.1.6 root 3862: case 1: /* B10 */
3863: dsp_core.registers[DSP_REG_B1] = save_lx;
3864: dsp_core.registers[DSP_REG_B0] = save_ly;
1.1.1.4 root 3865: break;
1.1.1.6 root 3866: case 2: /* X */
3867: dsp_core.registers[DSP_REG_X1] = save_lx;
3868: dsp_core.registers[DSP_REG_X0] = save_ly;
1.1.1.4 root 3869: break;
1.1.1.6 root 3870: case 3: /* Y */
3871: dsp_core.registers[DSP_REG_Y1] = save_lx;
3872: dsp_core.registers[DSP_REG_Y0] = save_ly;
1.1.1.4 root 3873: break;
1.1.1.6 root 3874: case 4: /* A */
3875: dsp_core.registers[DSP_REG_A0] = save_ly;
3876: dsp_core.registers[DSP_REG_A1] = save_lx;
3877: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
1.1.1.4 root 3878: break;
1.1.1.6 root 3879: case 5: /* B */
3880: dsp_core.registers[DSP_REG_B0] = save_ly;
3881: dsp_core.registers[DSP_REG_B1] = save_lx;
3882: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
1.1.1.4 root 3883: break;
1.1.1.6 root 3884: case 6: /* AB */
3885: dsp_core.registers[DSP_REG_A0] = 0;
3886: dsp_core.registers[DSP_REG_A1] = save_lx;
3887: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
3888: dsp_core.registers[DSP_REG_B0] = 0;
3889: dsp_core.registers[DSP_REG_B1] = save_ly;
3890: dsp_core.registers[DSP_REG_B2] = save_ly & (1<<23) ? 0xff : 0;
1.1.1.4 root 3891: break;
1.1.1.6 root 3892: case 7: /* BA */
3893: dsp_core.registers[DSP_REG_B0] = 0;
3894: dsp_core.registers[DSP_REG_B1] = save_lx;
3895: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
3896: dsp_core.registers[DSP_REG_A0] = 0;
3897: dsp_core.registers[DSP_REG_A1] = save_ly;
3898: dsp_core.registers[DSP_REG_A2] = save_ly & (1<<23) ? 0xff : 0;
1.1.1.4 root 3899: break;
1.1 root 3900: }
1.1.1.6 root 3901: }
3902: else {
3903: /* Read S */
3904: write_memory(DSP_SPACE_X, l_addr, save_lx);
3905: write_memory(DSP_SPACE_Y, l_addr, save_ly);
1.1 root 3906: }
3907: }
3908:
3909: static void dsp_pm_5(void)
3910: {
1.1.1.2 root 3911: Uint32 memspace, numreg, value, xy_addr, retour;
1.1 root 3912: /*
1.1.1.4 root 3913: 01dd 0ddd w0aa aaaa x:aa,D
1.1 root 3914: S,x:aa
1.1.1.4 root 3915: 01dd 0ddd w1mm mrrr x:ea,D
1.1 root 3916: S,x:ea
3917: #xxxxxx,D
1.1.1.4 root 3918: 01dd 1ddd w0aa aaaa y:aa,D
1.1 root 3919: S,y:aa
1.1.1.4 root 3920: 01dd 1ddd w1mm mrrr y:ea,D
1.1 root 3921: S,y:ea
3922: #xxxxxx,D
3923: */
3924:
3925: value = (cur_inst>>8) & BITMASK(6);
3926:
3927: if (cur_inst & (1<<14)) {
1.1.1.11 root 3928: retour = dsp_calc_ea(value, &xy_addr);
1.1 root 3929: } else {
3930: xy_addr = value;
3931: retour = 0;
3932: }
3933:
3934: memspace = (cur_inst>>19) & 1;
3935: numreg = (cur_inst>>16) & BITMASK(3);
3936: numreg |= (cur_inst>>17) & (BITMASK(2)<<3);
3937:
3938: if (cur_inst & (1<<15)) {
3939: /* Write D */
1.1.1.6 root 3940: if (retour)
1.1 root 3941: value = xy_addr;
1.1.1.6 root 3942: else
1.1 root 3943: value = read_memory(memspace, xy_addr);
1.1.1.6 root 3944: }
3945: else {
1.1 root 3946: /* Read S */
1.1.1.6 root 3947: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B))
3948: dsp_pm_read_accu24(numreg, &value);
3949: else
3950: value = dsp_core.registers[numreg];
3951: }
1.1 root 3952:
3953:
1.1.1.6 root 3954: /* Execute parallel instruction */
3955: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3956:
1.1.1.6 root 3957: if (cur_inst & (1<<15)) {
3958: /* Write D */
1.1.1.11 root 3959: dsp_core.agu_move_indirect_instr = 1;
3960: dsp_write_reg(numreg, value);
1.1.1.6 root 3961: }
3962: else {
1.1.1.7 root 3963: /* Read S */
1.1.1.6 root 3964: write_memory(memspace, xy_addr, value);
1.1 root 3965: }
3966: }
3967:
3968: static void dsp_pm_8(void)
3969: {
1.1.1.2 root 3970: Uint32 ea1, ea2;
3971: Uint32 numreg1, numreg2;
1.1.1.6 root 3972: Uint32 save_reg1, save_reg2, x_addr, y_addr;
1.1 root 3973: /*
1.1.1.11 root 3974: 1wmm eeff WrrM MRRR x:ea,D1 y:ea,D2
1.1 root 3975: x:ea,D1 S2,y:ea
3976: S1,x:ea y:ea,D2
3977: S1,x:ea S2,y:ea
3978: */
3979: numreg1 = numreg2 = DSP_REG_NULL;
3980:
3981: ea1 = (cur_inst>>8) & BITMASK(5);
3982: if ((ea1>>3) == 0) {
3983: ea1 |= (1<<5);
3984: }
3985: ea2 = (cur_inst>>13) & BITMASK(2);
3986: ea2 |= (cur_inst>>17) & (BITMASK(2)<<3);
3987: if ((ea1 & (1<<2))==0) {
3988: ea2 |= 1<<2;
3989: }
3990: if ((ea2>>3) == 0) {
3991: ea2 |= (1<<5);
3992: }
3993:
1.1.1.4 root 3994: dsp_calc_ea(ea1, &x_addr);
3995: dsp_calc_ea(ea2, &y_addr);
3996:
1.1 root 3997: switch((cur_inst>>18) & BITMASK(2)) {
3998: case 0: numreg1=DSP_REG_X0; break;
3999: case 1: numreg1=DSP_REG_X1; break;
4000: case 2: numreg1=DSP_REG_A; break;
4001: case 3: numreg1=DSP_REG_B; break;
4002: }
4003: switch((cur_inst>>16) & BITMASK(2)) {
4004: case 0: numreg2=DSP_REG_Y0; break;
4005: case 1: numreg2=DSP_REG_Y1; break;
4006: case 2: numreg2=DSP_REG_A; break;
4007: case 3: numreg2=DSP_REG_B; break;
4008: }
1.1.1.11 root 4009:
1.1 root 4010: if (cur_inst & (1<<15)) {
4011: /* Write D1 */
1.1.1.6 root 4012: save_reg1 = read_memory(DSP_SPACE_X, x_addr);
1.1 root 4013: } else {
4014: /* Read S1 */
1.1.1.6 root 4015: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
4016: dsp_pm_read_accu24(numreg1, &save_reg1);
4017: else
4018: save_reg1 = dsp_core.registers[numreg1];
1.1 root 4019: }
4020:
4021: if (cur_inst & (1<<22)) {
4022: /* Write D2 */
1.1.1.6 root 4023: save_reg2 = read_memory(DSP_SPACE_Y, y_addr);
1.1 root 4024: } else {
4025: /* Read S2 */
1.1.1.6 root 4026: if ((numreg2==DSP_REG_A) || (numreg2==DSP_REG_B))
4027: dsp_pm_read_accu24(numreg2, &save_reg2);
4028: else
4029: save_reg2 = dsp_core.registers[numreg2];
1.1 root 4030: }
4031:
4032:
1.1.1.6 root 4033: /* Execute parallel instruction */
4034: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 4035:
1.1.1.6 root 4036: /* Write first parallel move */
4037: if (cur_inst & (1<<15)) {
4038: /* Write D1 */
4039: if (numreg1 == DSP_REG_A) {
4040: dsp_core.registers[DSP_REG_A0] = 0x0;
4041: dsp_core.registers[DSP_REG_A1] = save_reg1;
4042: dsp_core.registers[DSP_REG_A2] = save_reg1 & (1<<23) ? 0xff : 0x0;
4043: }
4044: else if (numreg1 == DSP_REG_B) {
4045: dsp_core.registers[DSP_REG_B0] = 0x0;
4046: dsp_core.registers[DSP_REG_B1] = save_reg1;
4047: dsp_core.registers[DSP_REG_B2] = save_reg1 & (1<<23) ? 0xff : 0x0;
4048: }
4049: else {
4050: dsp_core.registers[numreg1] = save_reg1;
4051: }
4052: } else {
4053: /* Read S1 */
4054: write_memory(DSP_SPACE_X, x_addr, save_reg1);
4055: }
4056:
4057: /* Write second parallel move */
4058: if (cur_inst & (1<<22)) {
4059: /* Write D2 */
4060: if (numreg2 == DSP_REG_A) {
4061: dsp_core.registers[DSP_REG_A0] = 0x0;
4062: dsp_core.registers[DSP_REG_A1] = save_reg2;
4063: dsp_core.registers[DSP_REG_A2] = save_reg2 & (1<<23) ? 0xff : 0x0;
4064: }
4065: else if (numreg2 == DSP_REG_B) {
4066: dsp_core.registers[DSP_REG_B0] = 0x0;
4067: dsp_core.registers[DSP_REG_B1] = save_reg2;
4068: dsp_core.registers[DSP_REG_B2] = save_reg2 & (1<<23) ? 0xff : 0x0;
4069: }
4070: else {
4071: dsp_core.registers[numreg2] = save_reg2;
4072: }
4073: } else {
4074: /* Read S2 */
4075: write_memory(DSP_SPACE_Y, y_addr, save_reg2);
4076: }
4077: }
4078:
4079: /**********************************
4080: * 56bit arithmetic
4081: **********************************/
4082:
4083: /* source,dest[0] is 55:48 */
4084: /* source,dest[1] is 47:24 */
4085: /* source,dest[2] is 23:00 */
4086:
4087: static Uint16 dsp_abs56(Uint32 *dest)
1.1 root 4088: {
1.1.1.2 root 4089: Uint32 zerodest[3];
4090: Uint16 newsr;
1.1 root 4091:
4092: /* D=|D| */
4093:
4094: if (dest[0] & (1<<7)) {
4095: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4096:
4097: newsr = dsp_sub56(dest, zerodest);
4098:
4099: dest[0] = zerodest[0];
4100: dest[1] = zerodest[1];
4101: dest[2] = zerodest[2];
4102: } else {
4103: newsr = 0;
4104: }
4105:
4106: return newsr;
4107: }
4108:
1.1.1.2 root 4109: static Uint16 dsp_asl56(Uint32 *dest)
1.1 root 4110: {
1.1.1.2 root 4111: Uint16 overflow, carry;
1.1 root 4112:
4113: /* Shift left dest 1 bit: D<<=1 */
4114:
4115: carry = (dest[0]>>7) & 1;
4116:
4117: dest[0] <<= 1;
4118: dest[0] |= (dest[1]>>23) & 1;
4119: dest[0] &= BITMASK(8);
4120:
4121: dest[1] <<= 1;
4122: dest[1] |= (dest[2]>>23) & 1;
4123: dest[1] &= BITMASK(24);
1.1.1.11 root 4124:
1.1 root 4125: dest[2] <<= 1;
4126: dest[2] &= BITMASK(24);
4127:
4128: overflow = (carry != ((dest[0]>>7) & 1));
4129:
4130: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4131: }
4132:
1.1.1.2 root 4133: static Uint16 dsp_asr56(Uint32 *dest)
1.1 root 4134: {
1.1.1.2 root 4135: Uint16 carry;
1.1 root 4136:
4137: /* Shift right dest 1 bit: D>>=1 */
4138:
4139: carry = dest[2] & 1;
4140:
4141: dest[2] >>= 1;
4142: dest[2] |= (dest[1] & 1)<<23;
4143:
4144: dest[1] >>= 1;
4145: dest[1] |= (dest[0] & 1)<<23;
4146:
4147: dest[0] >>= 1;
4148: dest[0] |= (dest[0] & (1<<6))<<1;
4149:
4150: return (carry<<DSP_SR_C);
4151: }
4152:
1.1.1.2 root 4153: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest)
1.1 root 4154: {
1.1.1.4 root 4155: Uint16 overflow, carry, flg_s, flg_d, flg_r;
4156:
4157: flg_s = (source[0]>>7) & 1;
4158: flg_d = (dest[0]>>7) & 1;
4159:
1.1 root 4160: /* Add source to dest: D = D+S */
1.1.1.2 root 4161: dest[2] += source[2];
4162: dest[1] += source[1]+((dest[2]>>24) & 1);
4163: dest[0] += source[0]+((dest[1]>>24) & 1);
1.1 root 4164:
1.1.1.5 root 4165: carry = (dest[0]>>8) & 1;
4166:
1.1 root 4167: dest[2] &= BITMASK(24);
4168: dest[1] &= BITMASK(24);
4169: dest[0] &= BITMASK(8);
4170:
1.1.1.4 root 4171: flg_r = (dest[0]>>7) & 1;
4172:
4173: /*set overflow*/
4174: overflow = (flg_s ^ flg_r) & (flg_d ^ flg_r);
4175:
1.1 root 4176: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4177: }
4178:
1.1.1.2 root 4179: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest)
1.1 root 4180: {
1.1.1.5 root 4181: Uint16 overflow, carry, flg_s, flg_d, flg_r, dest_save;
1.1.1.4 root 4182:
1.1.1.5 root 4183: dest_save = dest[0];
1.1 root 4184:
1.1.1.9 root 4185: /* Subtract source from dest: D = D-S */
1.1.1.2 root 4186: dest[2] -= source[2];
4187: dest[1] -= source[1]+((dest[2]>>24) & 1);
4188: dest[0] -= source[0]+((dest[1]>>24) & 1);
1.1 root 4189:
1.1.1.5 root 4190: carry = (dest[0]>>8) & 1;
4191:
1.1 root 4192: dest[2] &= BITMASK(24);
4193: dest[1] &= BITMASK(24);
4194: dest[0] &= BITMASK(8);
4195:
1.1.1.4 root 4196: flg_s = (source[0]>>7) & 1;
1.1.1.5 root 4197: flg_d = (dest_save>>7) & 1;
1.1.1.4 root 4198: flg_r = (dest[0]>>7) & 1;
4199:
4200: /* set overflow */
4201: overflow = (flg_s ^ flg_d) & (flg_r ^ flg_d);
4202:
1.1 root 4203: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4204: }
4205:
1.1.1.5 root 4206: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe)
1.1 root 4207: {
1.1.1.2 root 4208: Uint32 part[4], zerodest[3], value;
1.1 root 4209:
4210: /* Multiply: D = S1*S2 */
4211: if (source1 & (1<<23)) {
1.1.1.5 root 4212: signe ^= 1;
1.1.1.6 root 4213: source1 = (1<<24) - source1;
1.1 root 4214: }
4215: if (source2 & (1<<23)) {
1.1.1.5 root 4216: signe ^= 1;
1.1.1.6 root 4217: source2 = (1<<24) - source2;
1.1 root 4218: }
4219:
4220: /* bits 0-11 * bits 0-11 */
4221: part[0]=(source1 & BITMASK(12))*(source2 & BITMASK(12));
4222: /* bits 12-23 * bits 0-11 */
4223: part[1]=((source1>>12) & BITMASK(12))*(source2 & BITMASK(12));
4224: /* bits 0-11 * bits 12-23 */
4225: part[2]=(source1 & BITMASK(12))*((source2>>12) & BITMASK(12));
4226: /* bits 12-23 * bits 12-23 */
4227: part[3]=((source1>>12) & BITMASK(12))*((source2>>12) & BITMASK(12));
4228:
4229: /* Calc dest 2 */
4230: dest[2] = part[0];
4231: dest[2] += (part[1] & BITMASK(12)) << 12;
4232: dest[2] += (part[2] & BITMASK(12)) << 12;
4233:
4234: /* Calc dest 1 */
4235: dest[1] = (part[1]>>12) & BITMASK(12);
4236: dest[1] += (part[2]>>12) & BITMASK(12);
4237: dest[1] += part[3];
4238:
4239: /* Calc dest 0 */
4240: dest[0] = 0;
4241:
4242: /* Add carries */
4243: value = (dest[2]>>24) & BITMASK(8);
4244: if (value) {
4245: dest[1] += value;
4246: dest[2] &= BITMASK(24);
4247: }
4248: value = (dest[1]>>24) & BITMASK(8);
4249: if (value) {
4250: dest[0] += value;
4251: dest[1] &= BITMASK(24);
4252: }
4253:
4254: /* Get rid of extra sign bit */
4255: dsp_asl56(dest);
4256:
1.1.1.5 root 4257: if (signe) {
1.1 root 4258: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4259:
4260: dsp_sub56(dest, zerodest);
4261:
4262: dest[0] = zerodest[0];
4263: dest[1] = zerodest[1];
4264: dest[2] = zerodest[2];
4265: }
4266: }
4267:
1.1.1.2 root 4268: static void dsp_rnd56(Uint32 *dest)
1.1 root 4269: {
1.1.1.4 root 4270: Uint32 rnd_const[3];
1.1 root 4271:
1.1.1.4 root 4272: rnd_const[0] = 0;
1.1 root 4273:
1.1.1.4 root 4274: /* Scaling mode S0 */
1.1.1.6 root 4275: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S0)) {
1.1.1.4 root 4276: rnd_const[1] = 1;
4277: rnd_const[2] = 0;
4278: dsp_add56(rnd_const, dest);
4279:
4280: if ((dest[2]==0) && ((dest[1] & 1) == 0)) {
4281: dest[1] &= (0xffffff - 0x3);
4282: }
4283: dest[1] &= 0xfffffe;
4284: dest[2]=0;
4285: }
4286: /* Scaling mode S1 */
1.1.1.6 root 4287: else if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S1)) {
1.1.1.4 root 4288: rnd_const[1] = 0;
4289: rnd_const[2] = (1<<22);
4290: dsp_add56(rnd_const, dest);
1.1.1.11 root 4291:
1.1.1.4 root 4292: if ((dest[2] & 0x7fffff) == 0){
4293: dest[2] = 0;
4294: }
4295: dest[2] &= 0x800000;
4296: }
4297: /* No Scaling */
4298: else {
4299: rnd_const[1] = 0;
4300: rnd_const[2] = (1<<23);
4301: dsp_add56(rnd_const, dest);
4302:
4303: if (dest[2] == 0) {
4304: dest[1] &= 0xfffffe;
1.1 root 4305: }
1.1.1.4 root 4306: dest[2]=0;
1.1 root 4307: }
4308: }
4309:
4310: /**********************************
4311: * Parallel moves instructions
4312: **********************************/
4313:
1.1.1.6 root 4314: static void dsp_abs_a(void)
1.1 root 4315: {
1.1.1.6 root 4316: Uint32 dest[3], overflowed;
1.1 root 4317:
1.1.1.6 root 4318: dest[0] = dsp_core.registers[DSP_REG_A2];
4319: dest[1] = dsp_core.registers[DSP_REG_A1];
4320: dest[2] = dsp_core.registers[DSP_REG_A0];
4321:
4322: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4323:
4324: dsp_abs56(dest);
4325:
4326: dsp_core.registers[DSP_REG_A2] = dest[0];
4327: dsp_core.registers[DSP_REG_A1] = dest[1];
4328: dsp_core.registers[DSP_REG_A0] = dest[2];
4329:
4330: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4331: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
4332:
4333: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4334: }
4335:
4336: static void dsp_abs_b(void)
4337: {
4338: Uint32 dest[3], overflowed;
1.1 root 4339:
1.1.1.6 root 4340: dest[0] = dsp_core.registers[DSP_REG_B2];
4341: dest[1] = dsp_core.registers[DSP_REG_B1];
4342: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 4343:
4344: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4345:
4346: dsp_abs56(dest);
4347:
1.1.1.6 root 4348: dsp_core.registers[DSP_REG_B2] = dest[0];
4349: dsp_core.registers[DSP_REG_B1] = dest[1];
4350: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4351:
1.1.1.6 root 4352: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4353: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
1.1.1.2 root 4354:
1.1.1.6 root 4355: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4356: }
4357:
1.1.1.6 root 4358: static void dsp_adc_x_a(void)
1.1 root 4359: {
1.1.1.6 root 4360: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4361: Uint16 newsr;
1.1 root 4362:
1.1.1.6 root 4363: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4364:
1.1.1.6 root 4365: dest[0] = dsp_core.registers[DSP_REG_A2];
4366: dest[1] = dsp_core.registers[DSP_REG_A1];
4367: dest[2] = dsp_core.registers[DSP_REG_A0];
4368:
4369: source[2] = dsp_core.registers[DSP_REG_X0];
4370: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4371: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4372:
4373: newsr = dsp_add56(source, dest);
1.1.1.11 root 4374:
1.1 root 4375: if (curcarry) {
1.1.1.6 root 4376: source[0]=0; source[1]=0; source[2]=1;
1.1 root 4377: newsr |= dsp_add56(source, dest);
4378: }
4379:
1.1.1.6 root 4380: dsp_core.registers[DSP_REG_A2] = dest[0];
4381: dsp_core.registers[DSP_REG_A1] = dest[1];
4382: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4383:
1.1.1.6 root 4384: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4385:
1.1.1.6 root 4386: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4387: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4388: }
4389:
1.1.1.6 root 4390: static void dsp_adc_x_b(void)
1.1 root 4391: {
1.1.1.6 root 4392: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4393: Uint16 newsr;
1.1 root 4394:
1.1.1.6 root 4395: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
4396:
4397: dest[0] = dsp_core.registers[DSP_REG_B2];
4398: dest[1] = dsp_core.registers[DSP_REG_B1];
4399: dest[2] = dsp_core.registers[DSP_REG_B0];
4400:
4401: source[2] = dsp_core.registers[DSP_REG_X0];
4402: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4403: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4404:
4405: newsr = dsp_add56(source, dest);
1.1.1.11 root 4406:
1.1.1.6 root 4407: if (curcarry) {
4408: source[0]=0; source[1]=0; source[2]=1;
4409: newsr |= dsp_add56(source, dest);
4410: }
1.1 root 4411:
1.1.1.6 root 4412: dsp_core.registers[DSP_REG_B2] = dest[0];
4413: dsp_core.registers[DSP_REG_B1] = dest[1];
4414: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4415:
1.1.1.6 root 4416: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4417:
1.1.1.6 root 4418: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4419: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4420: }
4421:
1.1.1.6 root 4422: static void dsp_adc_y_a(void)
1.1 root 4423: {
1.1.1.6 root 4424: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4425: Uint16 newsr;
1.1 root 4426:
1.1.1.6 root 4427: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4428:
1.1.1.6 root 4429: dest[0] = dsp_core.registers[DSP_REG_A2];
4430: dest[1] = dsp_core.registers[DSP_REG_A1];
4431: dest[2] = dsp_core.registers[DSP_REG_A0];
4432:
4433: source[2] = dsp_core.registers[DSP_REG_Y0];
4434: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4435: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4436:
1.1.1.6 root 4437: newsr = dsp_add56(source, dest);
1.1.1.11 root 4438:
1.1.1.6 root 4439: if (curcarry) {
4440: source[0]=0; source[1]=0; source[2]=1;
4441: newsr |= dsp_add56(source, dest);
4442: }
1.1 root 4443:
1.1.1.6 root 4444: dsp_core.registers[DSP_REG_A2] = dest[0];
4445: dsp_core.registers[DSP_REG_A1] = dest[1];
4446: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4447:
1.1.1.6 root 4448: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4449:
1.1.1.6 root 4450: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4451: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4452: }
4453:
1.1.1.6 root 4454: static void dsp_adc_y_b(void)
1.1 root 4455: {
1.1.1.6 root 4456: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4457: Uint16 newsr;
1.1 root 4458:
1.1.1.6 root 4459: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4460:
1.1.1.6 root 4461: dest[0] = dsp_core.registers[DSP_REG_B2];
4462: dest[1] = dsp_core.registers[DSP_REG_B1];
4463: dest[2] = dsp_core.registers[DSP_REG_B0];
4464:
4465: source[2] = dsp_core.registers[DSP_REG_Y0];
4466: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4467: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4468:
1.1.1.6 root 4469: newsr = dsp_add56(source, dest);
1.1.1.11 root 4470:
1.1.1.6 root 4471: if (curcarry) {
4472: source[0]=0; source[1]=0; source[2]=1;
4473: newsr |= dsp_add56(source, dest);
4474: }
1.1 root 4475:
1.1.1.6 root 4476: dsp_core.registers[DSP_REG_B2] = dest[0];
4477: dsp_core.registers[DSP_REG_B1] = dest[1];
4478: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4479:
1.1.1.6 root 4480: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4481:
1.1.1.6 root 4482: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4483: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4484: }
4485:
1.1.1.6 root 4486: static void dsp_add_b_a(void)
1.1 root 4487: {
1.1.1.6 root 4488: Uint32 source[3], dest[3];
4489: Uint16 newsr;
1.1 root 4490:
1.1.1.6 root 4491: dest[0] = dsp_core.registers[DSP_REG_A2];
4492: dest[1] = dsp_core.registers[DSP_REG_A1];
4493: dest[2] = dsp_core.registers[DSP_REG_A0];
4494:
4495: source[0] = dsp_core.registers[DSP_REG_B2];
4496: source[1] = dsp_core.registers[DSP_REG_B1];
4497: source[2] = dsp_core.registers[DSP_REG_B0];
4498:
4499: newsr = dsp_add56(source, dest);
4500:
4501: dsp_core.registers[DSP_REG_A2] = dest[0];
4502: dsp_core.registers[DSP_REG_A1] = dest[1];
4503: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4504:
1.1.1.6 root 4505: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4506:
1.1.1.6 root 4507: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4508: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4509: }
4510:
1.1.1.6 root 4511: static void dsp_add_a_b(void)
1.1 root 4512: {
1.1.1.6 root 4513: Uint32 source[3], dest[3];
1.1.1.2 root 4514: Uint16 newsr;
1.1 root 4515:
1.1.1.6 root 4516: dest[0] = dsp_core.registers[DSP_REG_B2];
4517: dest[1] = dsp_core.registers[DSP_REG_B1];
4518: dest[2] = dsp_core.registers[DSP_REG_B0];
4519:
4520: source[0] = dsp_core.registers[DSP_REG_A2];
4521: source[1] = dsp_core.registers[DSP_REG_A1];
4522: source[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 4523:
1.1.1.6 root 4524: newsr = dsp_add56(source, dest);
1.1 root 4525:
1.1.1.6 root 4526: dsp_core.registers[DSP_REG_B2] = dest[0];
4527: dsp_core.registers[DSP_REG_B1] = dest[1];
4528: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4529:
1.1.1.6 root 4530: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4531:
1.1.1.6 root 4532: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4533: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4534: }
4535:
1.1.1.6 root 4536: static void dsp_add_x_a(void)
1.1 root 4537: {
1.1.1.6 root 4538: Uint32 source[3], dest[3];
4539: Uint16 newsr;
1.1 root 4540:
1.1.1.6 root 4541: dest[0] = dsp_core.registers[DSP_REG_A2];
4542: dest[1] = dsp_core.registers[DSP_REG_A1];
4543: dest[2] = dsp_core.registers[DSP_REG_A0];
4544:
4545: source[1] = dsp_core.registers[DSP_REG_X1];
4546: source[2] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4547: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4548:
1.1.1.6 root 4549: newsr = dsp_add56(source, dest);
1.1 root 4550:
1.1.1.6 root 4551: dsp_core.registers[DSP_REG_A2] = dest[0];
4552: dsp_core.registers[DSP_REG_A1] = dest[1];
4553: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4554:
1.1.1.6 root 4555: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4556:
1.1.1.6 root 4557: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4558: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4559: }
4560:
1.1.1.6 root 4561: static void dsp_add_x_b(void)
1.1 root 4562: {
1.1.1.6 root 4563: Uint32 source[3], dest[3];
4564: Uint16 newsr;
1.1 root 4565:
1.1.1.6 root 4566: dest[0] = dsp_core.registers[DSP_REG_B2];
4567: dest[1] = dsp_core.registers[DSP_REG_B1];
4568: dest[2] = dsp_core.registers[DSP_REG_B0];
4569:
4570: source[1] = dsp_core.registers[DSP_REG_X1];
4571: source[2] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4572: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4573:
4574: newsr = dsp_add56(source, dest);
1.1 root 4575:
1.1.1.6 root 4576: dsp_core.registers[DSP_REG_B2] = dest[0];
4577: dsp_core.registers[DSP_REG_B1] = dest[1];
4578: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4579:
1.1.1.6 root 4580: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4581:
4582: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4583: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4584: }
4585:
1.1.1.6 root 4586: static void dsp_add_y_a(void)
1.1 root 4587: {
1.1.1.6 root 4588: Uint32 source[3], dest[3];
1.1.1.2 root 4589: Uint16 newsr;
1.1 root 4590:
1.1.1.6 root 4591: dest[0] = dsp_core.registers[DSP_REG_A2];
4592: dest[1] = dsp_core.registers[DSP_REG_A1];
4593: dest[2] = dsp_core.registers[DSP_REG_A0];
4594:
4595: source[1] = dsp_core.registers[DSP_REG_Y1];
4596: source[2] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4597: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4598:
1.1.1.6 root 4599: newsr = dsp_add56(source, dest);
1.1 root 4600:
1.1.1.6 root 4601: dsp_core.registers[DSP_REG_A2] = dest[0];
4602: dsp_core.registers[DSP_REG_A1] = dest[1];
4603: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4604:
1.1.1.6 root 4605: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4606:
4607: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4608: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4609: }
4610:
1.1.1.6 root 4611: static void dsp_add_y_b(void)
1.1 root 4612: {
1.1.1.6 root 4613: Uint32 source[3], dest[3];
1.1.1.2 root 4614: Uint16 newsr;
1.1 root 4615:
1.1.1.6 root 4616: dest[0] = dsp_core.registers[DSP_REG_B2];
4617: dest[1] = dsp_core.registers[DSP_REG_B1];
4618: dest[2] = dsp_core.registers[DSP_REG_B0];
4619:
4620: source[1] = dsp_core.registers[DSP_REG_Y1];
4621: source[2] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4622: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4623:
1.1.1.6 root 4624: newsr = dsp_add56(source, dest);
1.1 root 4625:
1.1.1.6 root 4626: dsp_core.registers[DSP_REG_B2] = dest[0];
4627: dsp_core.registers[DSP_REG_B1] = dest[1];
4628: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4629:
1.1.1.6 root 4630: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4631:
1.1.1.6 root 4632: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4633: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4634: }
4635:
1.1.1.6 root 4636: static void dsp_add_x0_a(void)
1.1 root 4637: {
1.1.1.6 root 4638: Uint32 source[3], dest[3];
4639: Uint16 newsr;
1.1 root 4640:
1.1.1.6 root 4641: dest[0] = dsp_core.registers[DSP_REG_A2];
4642: dest[1] = dsp_core.registers[DSP_REG_A1];
4643: dest[2] = dsp_core.registers[DSP_REG_A0];
4644:
4645: source[2] = 0;
4646: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4647: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4648:
4649: newsr = dsp_add56(source, dest);
4650:
4651: dsp_core.registers[DSP_REG_A2] = dest[0];
4652: dsp_core.registers[DSP_REG_A1] = dest[1];
4653: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4654:
1.1.1.6 root 4655: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4656:
1.1.1.6 root 4657: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4658: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4659: }
4660:
1.1.1.6 root 4661: static void dsp_add_x0_b(void)
1.1 root 4662: {
1.1.1.6 root 4663: Uint32 source[3], dest[3];
4664: Uint16 newsr;
4665:
4666: dest[0] = dsp_core.registers[DSP_REG_B2];
4667: dest[1] = dsp_core.registers[DSP_REG_B1];
4668: dest[2] = dsp_core.registers[DSP_REG_B0];
4669:
4670: source[2] = 0;
4671: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4672: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4673:
1.1.1.6 root 4674: newsr = dsp_add56(source, dest);
1.1 root 4675:
1.1.1.6 root 4676: dsp_core.registers[DSP_REG_B2] = dest[0];
4677: dsp_core.registers[DSP_REG_B1] = dest[1];
4678: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4679:
1.1.1.6 root 4680: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4681:
1.1.1.6 root 4682: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4683: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4684: }
4685:
1.1.1.6 root 4686: static void dsp_add_y0_a(void)
1.1 root 4687: {
1.1.1.6 root 4688: Uint32 source[3], dest[3];
4689: Uint16 newsr;
1.1 root 4690:
1.1.1.6 root 4691: dest[0] = dsp_core.registers[DSP_REG_A2];
4692: dest[1] = dsp_core.registers[DSP_REG_A1];
4693: dest[2] = dsp_core.registers[DSP_REG_A0];
4694:
4695: source[2] = 0;
4696: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4697: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4698:
1.1.1.6 root 4699: newsr = dsp_add56(source, dest);
4700:
4701: dsp_core.registers[DSP_REG_A2] = dest[0];
4702: dsp_core.registers[DSP_REG_A1] = dest[1];
4703: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4704:
1.1.1.6 root 4705: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4706:
1.1.1.6 root 4707: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4708: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4709: }
4710:
1.1.1.6 root 4711: static void dsp_add_y0_b(void)
1.1 root 4712: {
1.1.1.6 root 4713: Uint32 source[3], dest[3];
1.1.1.2 root 4714: Uint16 newsr;
1.1 root 4715:
1.1.1.6 root 4716: dest[0] = dsp_core.registers[DSP_REG_B2];
4717: dest[1] = dsp_core.registers[DSP_REG_B1];
4718: dest[2] = dsp_core.registers[DSP_REG_B0];
4719:
4720: source[2] = 0;
4721: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4722: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4723:
4724: newsr = dsp_add56(source, dest);
4725:
1.1.1.6 root 4726: dsp_core.registers[DSP_REG_B2] = dest[0];
4727: dsp_core.registers[DSP_REG_B1] = dest[1];
4728: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4729:
1.1.1.6 root 4730: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4731:
1.1.1.6 root 4732: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4733: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4734: }
4735:
1.1.1.6 root 4736: static void dsp_add_x1_a(void)
1.1 root 4737: {
1.1.1.6 root 4738: Uint32 source[3], dest[3];
1.1.1.2 root 4739: Uint16 newsr;
1.1 root 4740:
1.1.1.6 root 4741: dest[0] = dsp_core.registers[DSP_REG_A2];
4742: dest[1] = dsp_core.registers[DSP_REG_A1];
4743: dest[2] = dsp_core.registers[DSP_REG_A0];
4744:
4745: source[2] = 0;
4746: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4747: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4748:
4749: newsr = dsp_add56(source, dest);
4750:
1.1.1.6 root 4751: dsp_core.registers[DSP_REG_A2] = dest[0];
4752: dsp_core.registers[DSP_REG_A1] = dest[1];
4753: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4754:
1.1.1.6 root 4755: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4756:
1.1.1.6 root 4757: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4758: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4759: }
4760:
1.1.1.6 root 4761: static void dsp_add_x1_b(void)
1.1 root 4762: {
1.1.1.6 root 4763: Uint32 source[3], dest[3];
4764: Uint16 newsr;
4765:
4766: dest[0] = dsp_core.registers[DSP_REG_B2];
4767: dest[1] = dsp_core.registers[DSP_REG_B1];
4768: dest[2] = dsp_core.registers[DSP_REG_B0];
4769:
4770: source[2] = 0;
4771: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4772: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4773:
4774: newsr = dsp_add56(source, dest);
4775:
4776: dsp_core.registers[DSP_REG_B2] = dest[0];
4777: dsp_core.registers[DSP_REG_B1] = dest[1];
4778: dsp_core.registers[DSP_REG_B0] = dest[2];
4779:
4780: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4781:
4782: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4783: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4784: }
4785:
1.1.1.6 root 4786: static void dsp_add_y1_a(void)
1.1 root 4787: {
1.1.1.6 root 4788: Uint32 source[3], dest[3];
4789: Uint16 newsr;
1.1 root 4790:
1.1.1.6 root 4791: dest[0] = dsp_core.registers[DSP_REG_A2];
4792: dest[1] = dsp_core.registers[DSP_REG_A1];
4793: dest[2] = dsp_core.registers[DSP_REG_A0];
4794:
4795: source[2] = 0;
4796: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4797: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4798:
1.1.1.6 root 4799: newsr = dsp_add56(source, dest);
1.1 root 4800:
1.1.1.6 root 4801: dsp_core.registers[DSP_REG_A2] = dest[0];
4802: dsp_core.registers[DSP_REG_A1] = dest[1];
4803: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4804:
1.1.1.6 root 4805: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4806:
1.1.1.6 root 4807: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4808: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4809: }
4810:
1.1.1.6 root 4811: static void dsp_add_y1_b(void)
1.1 root 4812: {
1.1.1.6 root 4813: Uint32 source[3], dest[3];
4814: Uint16 newsr;
1.1 root 4815:
1.1.1.6 root 4816: dest[0] = dsp_core.registers[DSP_REG_B2];
4817: dest[1] = dsp_core.registers[DSP_REG_B1];
4818: dest[2] = dsp_core.registers[DSP_REG_B0];
4819:
4820: source[2] = 0;
4821: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4822: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4823:
1.1.1.6 root 4824: newsr = dsp_add56(source, dest);
1.1 root 4825:
1.1.1.6 root 4826: dsp_core.registers[DSP_REG_B2] = dest[0];
4827: dsp_core.registers[DSP_REG_B1] = dest[1];
4828: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4829:
1.1.1.6 root 4830: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4831:
1.1.1.6 root 4832: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4833: dsp_core.registers[DSP_REG_SR] |= newsr;
4834: }
1.1 root 4835:
1.1.1.6 root 4836: static void dsp_addl_b_a(void)
4837: {
4838: Uint32 source[3], dest[3];
4839: Uint16 newsr;
1.1.1.2 root 4840:
1.1.1.6 root 4841: dest[0] = dsp_core.registers[DSP_REG_A2];
4842: dest[1] = dsp_core.registers[DSP_REG_A1];
4843: dest[2] = dsp_core.registers[DSP_REG_A0];
4844: newsr = dsp_asl56(dest);
1.1 root 4845:
1.1.1.6 root 4846: source[0] = dsp_core.registers[DSP_REG_B2];
4847: source[1] = dsp_core.registers[DSP_REG_B1];
4848: source[2] = dsp_core.registers[DSP_REG_B0];
4849: newsr |= dsp_add56(source, dest);
1.1 root 4850:
1.1.1.6 root 4851: dsp_core.registers[DSP_REG_A2] = dest[0];
4852: dsp_core.registers[DSP_REG_A1] = dest[1];
4853: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4854:
1.1.1.6 root 4855: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4856:
1.1.1.6 root 4857: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4858: dsp_core.registers[DSP_REG_SR] |= newsr;
4859: }
1.1 root 4860:
1.1.1.6 root 4861: static void dsp_addl_a_b(void)
4862: {
4863: Uint32 source[3], dest[3];
4864: Uint16 newsr;
1.1 root 4865:
1.1.1.6 root 4866: dest[0] = dsp_core.registers[DSP_REG_B2];
4867: dest[1] = dsp_core.registers[DSP_REG_B1];
4868: dest[2] = dsp_core.registers[DSP_REG_B0];
4869: newsr = dsp_asl56(dest);
1.1 root 4870:
1.1.1.6 root 4871: source[0] = dsp_core.registers[DSP_REG_A2];
4872: source[1] = dsp_core.registers[DSP_REG_A1];
4873: source[2] = dsp_core.registers[DSP_REG_A0];
4874: newsr |= dsp_add56(source, dest);
4875:
4876: dsp_core.registers[DSP_REG_B2] = dest[0];
4877: dsp_core.registers[DSP_REG_B1] = dest[1];
4878: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4879:
1.1.1.6 root 4880: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4881:
1.1.1.6 root 4882: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4883: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4884: }
4885:
1.1.1.6 root 4886: static void dsp_addr_b_a(void)
1.1 root 4887: {
1.1.1.6 root 4888: Uint32 source[3], dest[3];
4889: Uint16 newsr;
4890:
4891: dest[0] = dsp_core.registers[DSP_REG_A2];
4892: dest[1] = dsp_core.registers[DSP_REG_A1];
4893: dest[2] = dsp_core.registers[DSP_REG_A0];
4894: newsr = dsp_asr56(dest);
4895:
4896: source[0] = dsp_core.registers[DSP_REG_B2];
4897: source[1] = dsp_core.registers[DSP_REG_B1];
4898: source[2] = dsp_core.registers[DSP_REG_B0];
4899: newsr |= dsp_add56(source, dest);
4900:
4901: dsp_core.registers[DSP_REG_A2] = dest[0];
4902: dsp_core.registers[DSP_REG_A1] = dest[1];
4903: dsp_core.registers[DSP_REG_A0] = dest[2];
4904:
4905: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4906:
4907: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4908: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4909: }
4910:
1.1.1.6 root 4911: static void dsp_addr_a_b(void)
1.1 root 4912: {
1.1.1.6 root 4913: Uint32 source[3], dest[3];
4914: Uint16 newsr;
4915:
4916: dest[0] = dsp_core.registers[DSP_REG_B2];
4917: dest[1] = dsp_core.registers[DSP_REG_B1];
4918: dest[2] = dsp_core.registers[DSP_REG_B0];
4919: newsr = dsp_asr56(dest);
4920:
4921: source[0] = dsp_core.registers[DSP_REG_A2];
4922: source[1] = dsp_core.registers[DSP_REG_A1];
4923: source[2] = dsp_core.registers[DSP_REG_A0];
4924: newsr |= dsp_add56(source, dest);
1.1 root 4925:
1.1.1.6 root 4926: dsp_core.registers[DSP_REG_B2] = dest[0];
4927: dsp_core.registers[DSP_REG_B1] = dest[1];
4928: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4929:
1.1.1.6 root 4930: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4931:
1.1.1.6 root 4932: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4933: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4934: }
4935:
1.1.1.6 root 4936: static void dsp_and_x0_a(void)
1.1 root 4937: {
1.1.1.6 root 4938: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X0];
1.1 root 4939:
1.1.1.6 root 4940: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4941: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4942: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4943: }
1.1 root 4944:
1.1.1.6 root 4945: static void dsp_and_x0_b(void)
4946: {
4947: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X0];
1.1 root 4948:
1.1.1.6 root 4949: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4950: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4951: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
1.1 root 4952: }
4953:
1.1.1.6 root 4954: static void dsp_and_y0_a(void)
1.1 root 4955: {
1.1.1.6 root 4956: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y0];
1.1 root 4957:
1.1.1.6 root 4958: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4959: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4960: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4961: }
1.1 root 4962:
1.1.1.6 root 4963: static void dsp_and_y0_b(void)
4964: {
4965: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y0];
1.1 root 4966:
1.1.1.6 root 4967: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4968: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4969: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
4970: }
1.1 root 4971:
1.1.1.6 root 4972: static void dsp_and_x1_a(void)
4973: {
4974: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X1];
1.1.1.2 root 4975:
1.1.1.6 root 4976: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4977: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4978: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
1.1 root 4979: }
4980:
1.1.1.6 root 4981: static void dsp_and_x1_b(void)
1.1 root 4982: {
1.1.1.6 root 4983: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X1];
4984:
4985: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4986: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4987: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
4988: }
1.1 root 4989:
1.1.1.6 root 4990: static void dsp_and_y1_a(void)
4991: {
4992: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y1];
1.1 root 4993:
1.1.1.6 root 4994: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4995: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4996: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4997: }
1.1 root 4998:
1.1.1.6 root 4999: static void dsp_and_y1_b(void)
5000: {
5001: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y1];
1.1.1.2 root 5002:
1.1.1.6 root 5003: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5004: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5005: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
1.1 root 5006: }
5007:
1.1.1.7 root 5008: static void dsp_asl_a(void)
1.1 root 5009: {
1.1.1.6 root 5010: Uint32 dest[3];
5011: Uint16 newsr;
1.1 root 5012:
1.1.1.6 root 5013: dest[0] = dsp_core.registers[DSP_REG_A2];
5014: dest[1] = dsp_core.registers[DSP_REG_A1];
5015: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 5016:
1.1.1.6 root 5017: newsr = dsp_asl56(dest);
5018:
5019: dsp_core.registers[DSP_REG_A2] = dest[0];
5020: dsp_core.registers[DSP_REG_A1] = dest[1];
5021: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 5022:
1.1.1.6 root 5023: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5024: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1.1.2 root 5025:
1.1.1.6 root 5026: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 5027: }
5028:
1.1.1.7 root 5029: static void dsp_asl_b(void)
1.1 root 5030: {
1.1.1.6 root 5031: Uint32 dest[3];
1.1.1.2 root 5032: Uint16 newsr;
1.1 root 5033:
1.1.1.6 root 5034: dest[0] = dsp_core.registers[DSP_REG_B2];
5035: dest[1] = dsp_core.registers[DSP_REG_B1];
5036: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 5037:
1.1.1.6 root 5038: newsr = dsp_asl56(dest);
1.1 root 5039:
1.1.1.6 root 5040: dsp_core.registers[DSP_REG_B2] = dest[0];
5041: dsp_core.registers[DSP_REG_B1] = dest[1];
5042: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 5043:
1.1.1.6 root 5044: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5045: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 5046:
1.1.1.6 root 5047: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 5048: }
5049:
1.1.1.7 root 5050: static void dsp_asr_a(void)
1.1 root 5051: {
1.1.1.6 root 5052: Uint32 dest[3];
5053: Uint16 newsr;
5054:
5055: dest[0] = dsp_core.registers[DSP_REG_A2];
5056: dest[1] = dsp_core.registers[DSP_REG_A1];
5057: dest[2] = dsp_core.registers[DSP_REG_A0];
5058:
5059: newsr = dsp_asr56(dest);
5060:
5061: dsp_core.registers[DSP_REG_A2] = dest[0];
5062: dsp_core.registers[DSP_REG_A1] = dest[1];
5063: dsp_core.registers[DSP_REG_A0] = dest[2];
5064:
5065: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5066: dsp_core.registers[DSP_REG_SR] |= newsr;
5067:
5068: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5069: }
5070:
1.1.1.7 root 5071: static void dsp_asr_b(void)
1.1.1.6 root 5072: {
5073: Uint32 dest[3];
5074: Uint16 newsr;
5075:
5076: dest[0] = dsp_core.registers[DSP_REG_B2];
5077: dest[1] = dsp_core.registers[DSP_REG_B1];
5078: dest[2] = dsp_core.registers[DSP_REG_B0];
5079:
5080: newsr = dsp_asr56(dest);
5081:
5082: dsp_core.registers[DSP_REG_B2] = dest[0];
5083: dsp_core.registers[DSP_REG_B1] = dest[1];
5084: dsp_core.registers[DSP_REG_B0] = dest[2];
5085:
5086: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5087: dsp_core.registers[DSP_REG_SR] |= newsr;
5088:
5089: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5090: }
5091:
5092: static void dsp_clr_a(void)
5093: {
1.1.1.7 root 5094: dsp_core.registers[DSP_REG_A2] = 0;
5095: dsp_core.registers[DSP_REG_A1] = 0;
5096: dsp_core.registers[DSP_REG_A0] = 0;
1.1.1.6 root 5097:
5098: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5099: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5100: }
5101:
5102: static void dsp_clr_b(void)
5103: {
1.1.1.7 root 5104: dsp_core.registers[DSP_REG_B2] = 0;
5105: dsp_core.registers[DSP_REG_B1] = 0;
5106: dsp_core.registers[DSP_REG_B0] = 0;
1.1.1.6 root 5107:
5108: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5109: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5110: }
5111:
5112: static void dsp_cmp_b_a(void)
5113: {
5114: Uint32 source[3], dest[3];
5115: Uint16 newsr;
5116:
5117: dest[0] = dsp_core.registers[DSP_REG_A2];
5118: dest[1] = dsp_core.registers[DSP_REG_A1];
5119: dest[2] = dsp_core.registers[DSP_REG_A0];
5120:
5121: source[0] = dsp_core.registers[DSP_REG_B2];
5122: source[1] = dsp_core.registers[DSP_REG_B1];
5123: source[2] = dsp_core.registers[DSP_REG_B0];
5124:
5125: newsr = dsp_sub56(source, dest);
5126:
5127: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5128:
5129: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5130: dsp_core.registers[DSP_REG_SR] |= newsr;
5131: }
5132:
5133: static void dsp_cmp_a_b(void)
5134: {
5135: Uint32 source[3], dest[3];
5136: Uint16 newsr;
5137:
5138: dest[0] = dsp_core.registers[DSP_REG_B2];
5139: dest[1] = dsp_core.registers[DSP_REG_B1];
5140: dest[2] = dsp_core.registers[DSP_REG_B0];
5141:
5142: source[0] = dsp_core.registers[DSP_REG_A2];
5143: source[1] = dsp_core.registers[DSP_REG_A1];
5144: source[2] = dsp_core.registers[DSP_REG_A0];
5145:
5146: newsr = dsp_sub56(source, dest);
5147:
5148: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5149:
5150: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5151: dsp_core.registers[DSP_REG_SR] |= newsr;
5152: }
5153:
5154: static void dsp_cmp_x0_a(void)
5155: {
5156: Uint32 source[3], dest[3];
5157: Uint16 newsr;
5158:
5159: dest[2] = dsp_core.registers[DSP_REG_A0];
5160: dest[1] = dsp_core.registers[DSP_REG_A1];
5161: dest[0] = dsp_core.registers[DSP_REG_A2];
5162:
5163: source[2] = 0;
5164: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5165: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5166:
5167: newsr = dsp_sub56(source, dest);
5168:
5169: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5170:
5171: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5172: dsp_core.registers[DSP_REG_SR] |= newsr;
5173: }
5174:
5175: static void dsp_cmp_x0_b(void)
5176: {
5177: Uint32 source[3], dest[3];
5178: Uint16 newsr;
5179:
5180: dest[0] = dsp_core.registers[DSP_REG_B2];
5181: dest[1] = dsp_core.registers[DSP_REG_B1];
5182: dest[2] = dsp_core.registers[DSP_REG_B0];
5183:
5184: source[2] = 0;
5185: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5186: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5187:
5188: newsr = dsp_sub56(source, dest);
5189:
5190: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5191:
5192: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5193: dsp_core.registers[DSP_REG_SR] |= newsr;
5194: }
5195:
5196: static void dsp_cmp_y0_a(void)
5197: {
5198: Uint32 source[3], dest[3];
5199: Uint16 newsr;
5200:
5201: dest[2] = dsp_core.registers[DSP_REG_A0];
5202: dest[1] = dsp_core.registers[DSP_REG_A1];
5203: dest[0] = dsp_core.registers[DSP_REG_A2];
5204:
5205: source[2] = 0;
5206: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5207: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5208:
5209: newsr = dsp_sub56(source, dest);
5210:
5211: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5212:
5213: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5214: dsp_core.registers[DSP_REG_SR] |= newsr;
5215: }
5216:
5217: static void dsp_cmp_y0_b(void)
5218: {
5219: Uint32 source[3], dest[3];
5220: Uint16 newsr;
5221:
5222: dest[0] = dsp_core.registers[DSP_REG_B2];
5223: dest[1] = dsp_core.registers[DSP_REG_B1];
5224: dest[2] = dsp_core.registers[DSP_REG_B0];
5225:
5226: source[2] = 0;
5227: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5228: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5229:
5230: newsr = dsp_sub56(source, dest);
5231:
5232: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5233:
5234: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5235: dsp_core.registers[DSP_REG_SR] |= newsr;
5236: }
5237: static void dsp_cmp_x1_a(void)
5238: {
5239: Uint32 source[3], dest[3];
5240: Uint16 newsr;
5241:
5242: dest[2] = dsp_core.registers[DSP_REG_A0];
5243: dest[1] = dsp_core.registers[DSP_REG_A1];
5244: dest[0] = dsp_core.registers[DSP_REG_A2];
5245:
5246: source[2] = 0;
5247: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5248: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5249:
5250: newsr = dsp_sub56(source, dest);
5251:
5252: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5253:
5254: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5255: dsp_core.registers[DSP_REG_SR] |= newsr;
5256: }
5257:
5258: static void dsp_cmp_x1_b(void)
5259: {
5260: Uint32 source[3], dest[3];
5261: Uint16 newsr;
5262:
5263: dest[0] = dsp_core.registers[DSP_REG_B2];
5264: dest[1] = dsp_core.registers[DSP_REG_B1];
5265: dest[2] = dsp_core.registers[DSP_REG_B0];
5266:
5267: source[2] = 0;
5268: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5269: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5270:
5271: newsr = dsp_sub56(source, dest);
5272:
5273: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5274:
5275: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5276: dsp_core.registers[DSP_REG_SR] |= newsr;
5277: }
5278:
5279: static void dsp_cmp_y1_a(void)
5280: {
5281: Uint32 source[3], dest[3];
5282: Uint16 newsr;
5283:
5284: dest[2] = dsp_core.registers[DSP_REG_A0];
5285: dest[1] = dsp_core.registers[DSP_REG_A1];
5286: dest[0] = dsp_core.registers[DSP_REG_A2];
5287:
5288: source[2] = 0;
5289: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5290: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5291:
5292: newsr = dsp_sub56(source, dest);
5293:
5294: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5295:
5296: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5297: dsp_core.registers[DSP_REG_SR] |= newsr;
5298: }
5299:
5300: static void dsp_cmp_y1_b(void)
5301: {
5302: Uint32 source[3], dest[3];
5303: Uint16 newsr;
5304:
5305: dest[0] = dsp_core.registers[DSP_REG_B2];
5306: dest[1] = dsp_core.registers[DSP_REG_B1];
5307: dest[2] = dsp_core.registers[DSP_REG_B0];
5308:
5309: source[2] = 0;
5310: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5311: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5312:
5313: newsr = dsp_sub56(source, dest);
5314:
5315: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5316:
5317: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5318: dsp_core.registers[DSP_REG_SR] |= newsr;
5319: }
5320:
5321: static void dsp_cmpm_b_a(void)
5322: {
5323: Uint32 source[3], dest[3];
5324: Uint16 newsr;
5325:
5326: dest[0] = dsp_core.registers[DSP_REG_A2];
5327: dest[1] = dsp_core.registers[DSP_REG_A1];
5328: dest[2] = dsp_core.registers[DSP_REG_A0];
5329: dsp_abs56(dest);
5330:
5331: source[0] = dsp_core.registers[DSP_REG_B2];
5332: source[1] = dsp_core.registers[DSP_REG_B1];
5333: source[2] = dsp_core.registers[DSP_REG_B0];
5334: dsp_abs56(source);
5335:
5336: newsr = dsp_sub56(source, dest);
5337:
5338: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5339:
5340: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5341: dsp_core.registers[DSP_REG_SR] |= newsr;
5342: }
5343:
5344: static void dsp_cmpm_a_b(void)
5345: {
5346: Uint32 source[3], dest[3];
5347: Uint16 newsr;
5348:
5349: dest[0] = dsp_core.registers[DSP_REG_B2];
5350: dest[1] = dsp_core.registers[DSP_REG_B1];
5351: dest[2] = dsp_core.registers[DSP_REG_B0];
5352: dsp_abs56(dest);
5353:
5354: source[0] = dsp_core.registers[DSP_REG_A2];
5355: source[1] = dsp_core.registers[DSP_REG_A1];
5356: source[2] = dsp_core.registers[DSP_REG_A0];
5357: dsp_abs56(source);
5358:
5359: newsr = dsp_sub56(source, dest);
5360:
5361: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5362:
5363: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5364: dsp_core.registers[DSP_REG_SR] |= newsr;
5365: }
5366:
5367: static void dsp_cmpm_x0_a(void)
5368: {
5369: Uint32 source[3], dest[3];
5370: Uint16 newsr;
5371:
5372: dest[2] = dsp_core.registers[DSP_REG_A0];
5373: dest[1] = dsp_core.registers[DSP_REG_A1];
5374: dest[0] = dsp_core.registers[DSP_REG_A2];
5375: dsp_abs56(dest);
5376:
5377: source[2] = 0;
5378: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5379: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5380: dsp_abs56(source);
5381:
5382: newsr = dsp_sub56(source, dest);
5383:
5384: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5385:
5386: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5387: dsp_core.registers[DSP_REG_SR] |= newsr;
5388: }
5389:
5390: static void dsp_cmpm_x0_b(void)
5391: {
5392: Uint32 source[3], dest[3];
5393: Uint16 newsr;
5394:
5395: dest[0] = dsp_core.registers[DSP_REG_B2];
5396: dest[1] = dsp_core.registers[DSP_REG_B1];
5397: dest[2] = dsp_core.registers[DSP_REG_B0];
5398: dsp_abs56(dest);
5399:
5400: source[2] = 0;
5401: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5402: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5403: dsp_abs56(source);
5404:
5405: newsr = dsp_sub56(source, dest);
5406:
5407: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5408:
5409: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5410: dsp_core.registers[DSP_REG_SR] |= newsr;
5411: }
5412:
5413: static void dsp_cmpm_y0_a(void)
5414: {
5415: Uint32 source[3], dest[3];
5416: Uint16 newsr;
5417:
5418: dest[2] = dsp_core.registers[DSP_REG_A0];
5419: dest[1] = dsp_core.registers[DSP_REG_A1];
5420: dest[0] = dsp_core.registers[DSP_REG_A2];
5421: dsp_abs56(dest);
5422:
5423: source[2] = 0;
5424: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5425: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5426: dsp_abs56(source);
5427:
5428: newsr = dsp_sub56(source, dest);
5429:
5430: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5431:
5432: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5433: dsp_core.registers[DSP_REG_SR] |= newsr;
5434: }
5435:
5436: static void dsp_cmpm_y0_b(void)
5437: {
5438: Uint32 source[3], dest[3];
5439: Uint16 newsr;
5440:
5441: dest[0] = dsp_core.registers[DSP_REG_B2];
5442: dest[1] = dsp_core.registers[DSP_REG_B1];
5443: dest[2] = dsp_core.registers[DSP_REG_B0];
5444: dsp_abs56(dest);
5445:
5446: source[2] = 0;
5447: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5448: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5449: dsp_abs56(source);
5450:
5451: newsr = dsp_sub56(source, dest);
5452:
5453: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5454:
5455: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5456: dsp_core.registers[DSP_REG_SR] |= newsr;
5457: }
5458:
5459: static void dsp_cmpm_x1_a(void)
5460: {
5461: Uint32 source[3], dest[3];
5462: Uint16 newsr;
5463:
5464: dest[2] = dsp_core.registers[DSP_REG_A0];
5465: dest[1] = dsp_core.registers[DSP_REG_A1];
5466: dest[0] = dsp_core.registers[DSP_REG_A2];
5467: dsp_abs56(dest);
5468:
5469: source[2] = 0;
5470: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5471: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5472: dsp_abs56(source);
5473:
5474: newsr = dsp_sub56(source, dest);
5475:
5476: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5477:
5478: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5479: dsp_core.registers[DSP_REG_SR] |= newsr;
5480: }
5481:
5482: static void dsp_cmpm_x1_b(void)
5483: {
5484: Uint32 source[3], dest[3];
5485: Uint16 newsr;
5486:
5487: dest[0] = dsp_core.registers[DSP_REG_B2];
5488: dest[1] = dsp_core.registers[DSP_REG_B1];
5489: dest[2] = dsp_core.registers[DSP_REG_B0];
5490: dsp_abs56(dest);
5491:
5492: source[2] = 0;
5493: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5494: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5495: dsp_abs56(source);
5496:
5497: newsr = dsp_sub56(source, dest);
5498:
5499: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5500:
5501: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5502: dsp_core.registers[DSP_REG_SR] |= newsr;
5503: }
5504:
5505: static void dsp_cmpm_y1_a(void)
5506: {
5507: Uint32 source[3], dest[3];
5508: Uint16 newsr;
5509:
5510: dest[2] = dsp_core.registers[DSP_REG_A0];
5511: dest[1] = dsp_core.registers[DSP_REG_A1];
5512: dest[0] = dsp_core.registers[DSP_REG_A2];
5513: dsp_abs56(dest);
5514:
5515: source[2] = 0;
5516: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5517: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5518: dsp_abs56(source);
5519:
5520: newsr = dsp_sub56(source, dest);
5521:
5522: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5523:
5524: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5525: dsp_core.registers[DSP_REG_SR] |= newsr;
5526: }
5527:
5528: static void dsp_cmpm_y1_b(void)
5529: {
5530: Uint32 source[3], dest[3];
5531: Uint16 newsr;
5532:
5533: dest[0] = dsp_core.registers[DSP_REG_B2];
5534: dest[1] = dsp_core.registers[DSP_REG_B1];
5535: dest[2] = dsp_core.registers[DSP_REG_B0];
5536: dsp_abs56(dest);
5537:
5538: source[2] = 0;
5539: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5540: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5541: dsp_abs56(source);
5542:
5543: newsr = dsp_sub56(source, dest);
5544:
5545: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5546:
5547: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5548: dsp_core.registers[DSP_REG_SR] |= newsr;
5549: }
5550:
5551: static void dsp_eor_x0_a(void)
5552: {
5553: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X0];
5554: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5555:
5556: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5557: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5558: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5559: }
5560:
5561: static void dsp_eor_x0_b(void)
5562: {
5563: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X0];
5564: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5565:
5566: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5567: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5568: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5569: }
5570:
5571: static void dsp_eor_y0_a(void)
5572: {
5573: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y0];
5574: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5575:
5576: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5577: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5578: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5579: }
5580:
5581: static void dsp_eor_y0_b(void)
5582: {
5583: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y0];
5584: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5585:
5586: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5587: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5588: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5589: }
5590:
5591: static void dsp_eor_x1_a(void)
5592: {
5593: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X1];
5594: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5595:
5596: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5597: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5598: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5599: }
5600:
5601: static void dsp_eor_x1_b(void)
5602: {
5603: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X1];
5604: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5605:
5606: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5607: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5608: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5609: }
5610:
5611: static void dsp_eor_y1_a(void)
5612: {
5613: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y1];
5614: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5615:
5616: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5617: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5618: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5619: }
5620:
5621: static void dsp_eor_y1_b(void)
5622: {
5623: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y1];
5624: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5625:
5626: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5627: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5628: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5629: }
5630:
5631: static void dsp_lsl_a(void)
5632: {
5633: Uint32 newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
5634:
5635: dsp_core.registers[DSP_REG_A1] <<= 1;
5636: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
5637:
5638: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5639: dsp_core.registers[DSP_REG_SR] |= newcarry;
5640: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5641: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5642: }
5643:
5644: static void dsp_lsl_b(void)
5645: {
5646: Uint32 newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
5647:
5648: dsp_core.registers[DSP_REG_B1] <<= 1;
5649: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
5650:
5651: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5652: dsp_core.registers[DSP_REG_SR] |= newcarry;
5653: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5654: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5655: }
5656:
5657: static void dsp_lsr_a(void)
5658: {
5659: Uint32 newcarry = dsp_core.registers[DSP_REG_A1] & 1;
5660: dsp_core.registers[DSP_REG_A1] >>= 1;
5661:
5662: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5663: dsp_core.registers[DSP_REG_SR] |= newcarry;
5664: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5665: }
5666:
5667: static void dsp_lsr_b(void)
5668: {
5669: Uint32 newcarry = dsp_core.registers[DSP_REG_B1] & 1;
5670: dsp_core.registers[DSP_REG_B1] >>= 1;
5671:
5672: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5673: dsp_core.registers[DSP_REG_SR] |= newcarry;
5674: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5675: }
5676:
5677: static void dsp_mac_p_x0_x0_a(void)
5678: {
5679: Uint32 source[3], dest[3];
5680: Uint16 newsr;
5681:
5682: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5683:
5684: dest[0] = dsp_core.registers[DSP_REG_A2];
5685: dest[1] = dsp_core.registers[DSP_REG_A1];
5686: dest[2] = dsp_core.registers[DSP_REG_A0];
5687: newsr = dsp_add56(source, dest);
5688:
5689: dsp_core.registers[DSP_REG_A2] = dest[0];
5690: dsp_core.registers[DSP_REG_A1] = dest[1];
5691: dsp_core.registers[DSP_REG_A0] = dest[2];
5692:
5693: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5694:
5695: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5696: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5697: }
5698:
5699: static void dsp_mac_m_x0_x0_a(void)
5700: {
5701: Uint32 source[3], dest[3];
5702: Uint16 newsr;
5703:
5704: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5705:
5706: dest[0] = dsp_core.registers[DSP_REG_A2];
5707: dest[1] = dsp_core.registers[DSP_REG_A1];
5708: dest[2] = dsp_core.registers[DSP_REG_A0];
5709: newsr = dsp_add56(source, dest);
5710:
5711: dsp_core.registers[DSP_REG_A2] = dest[0];
5712: dsp_core.registers[DSP_REG_A1] = dest[1];
5713: dsp_core.registers[DSP_REG_A0] = dest[2];
5714:
5715: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5716:
5717: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5718: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5719: }
5720: static void dsp_mac_p_x0_x0_b(void)
5721: {
5722: Uint32 source[3], dest[3];
5723: Uint16 newsr;
5724:
5725: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5726:
5727: dest[0] = dsp_core.registers[DSP_REG_B2];
5728: dest[1] = dsp_core.registers[DSP_REG_B1];
5729: dest[2] = dsp_core.registers[DSP_REG_B0];
5730: newsr = dsp_add56(source, dest);
5731:
5732: dsp_core.registers[DSP_REG_B2] = dest[0];
5733: dsp_core.registers[DSP_REG_B1] = dest[1];
5734: dsp_core.registers[DSP_REG_B0] = dest[2];
5735:
5736: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5737:
5738: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5739: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5740: }
5741:
5742: static void dsp_mac_m_x0_x0_b(void)
5743: {
5744: Uint32 source[3], dest[3];
5745: Uint16 newsr;
5746:
5747: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5748:
5749: dest[0] = dsp_core.registers[DSP_REG_B2];
5750: dest[1] = dsp_core.registers[DSP_REG_B1];
5751: dest[2] = dsp_core.registers[DSP_REG_B0];
5752: newsr = dsp_add56(source, dest);
5753:
5754: dsp_core.registers[DSP_REG_B2] = dest[0];
5755: dsp_core.registers[DSP_REG_B1] = dest[1];
5756: dsp_core.registers[DSP_REG_B0] = dest[2];
5757:
5758: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5759:
5760: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5761: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5762: }
5763:
5764: static void dsp_mac_p_y0_y0_a(void)
5765: {
5766: Uint32 source[3], dest[3];
5767: Uint16 newsr;
5768:
5769: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5770:
5771: dest[0] = dsp_core.registers[DSP_REG_A2];
5772: dest[1] = dsp_core.registers[DSP_REG_A1];
5773: dest[2] = dsp_core.registers[DSP_REG_A0];
5774: newsr = dsp_add56(source, dest);
5775:
5776: dsp_core.registers[DSP_REG_A2] = dest[0];
5777: dsp_core.registers[DSP_REG_A1] = dest[1];
5778: dsp_core.registers[DSP_REG_A0] = dest[2];
5779:
5780: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5781:
5782: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5783: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5784: }
5785:
5786: static void dsp_mac_m_y0_y0_a(void)
5787: {
5788: Uint32 source[3], dest[3];
5789: Uint16 newsr;
5790:
5791: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5792:
5793: dest[0] = dsp_core.registers[DSP_REG_A2];
5794: dest[1] = dsp_core.registers[DSP_REG_A1];
5795: dest[2] = dsp_core.registers[DSP_REG_A0];
5796: newsr = dsp_add56(source, dest);
5797:
5798: dsp_core.registers[DSP_REG_A2] = dest[0];
5799: dsp_core.registers[DSP_REG_A1] = dest[1];
5800: dsp_core.registers[DSP_REG_A0] = dest[2];
5801:
5802: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5803:
5804: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5805: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5806: }
5807: static void dsp_mac_p_y0_y0_b(void)
5808: {
5809: Uint32 source[3], dest[3];
5810: Uint16 newsr;
5811:
5812: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5813:
5814: dest[0] = dsp_core.registers[DSP_REG_B2];
5815: dest[1] = dsp_core.registers[DSP_REG_B1];
5816: dest[2] = dsp_core.registers[DSP_REG_B0];
5817: newsr = dsp_add56(source, dest);
5818:
5819: dsp_core.registers[DSP_REG_B2] = dest[0];
5820: dsp_core.registers[DSP_REG_B1] = dest[1];
5821: dsp_core.registers[DSP_REG_B0] = dest[2];
5822:
5823: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5824:
5825: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5826: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5827: }
5828:
5829: static void dsp_mac_m_y0_y0_b(void)
5830: {
5831: Uint32 source[3], dest[3];
5832: Uint16 newsr;
5833:
5834: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5835:
5836: dest[0] = dsp_core.registers[DSP_REG_B2];
5837: dest[1] = dsp_core.registers[DSP_REG_B1];
5838: dest[2] = dsp_core.registers[DSP_REG_B0];
5839: newsr = dsp_add56(source, dest);
5840:
5841: dsp_core.registers[DSP_REG_B2] = dest[0];
5842: dsp_core.registers[DSP_REG_B1] = dest[1];
5843: dsp_core.registers[DSP_REG_B0] = dest[2];
5844:
5845: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5846:
5847: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5848: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5849: }
5850:
5851: static void dsp_mac_p_x1_x0_a(void)
5852: {
5853: Uint32 source[3], dest[3];
5854: Uint16 newsr;
5855:
5856: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5857:
5858: dest[0] = dsp_core.registers[DSP_REG_A2];
5859: dest[1] = dsp_core.registers[DSP_REG_A1];
5860: dest[2] = dsp_core.registers[DSP_REG_A0];
5861: newsr = dsp_add56(source, dest);
5862:
5863: dsp_core.registers[DSP_REG_A2] = dest[0];
5864: dsp_core.registers[DSP_REG_A1] = dest[1];
5865: dsp_core.registers[DSP_REG_A0] = dest[2];
5866:
5867: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5868:
5869: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5870: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5871: }
5872:
5873: static void dsp_mac_m_x1_x0_a(void)
5874: {
5875: Uint32 source[3], dest[3];
5876: Uint16 newsr;
5877:
5878: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5879:
5880: dest[0] = dsp_core.registers[DSP_REG_A2];
5881: dest[1] = dsp_core.registers[DSP_REG_A1];
5882: dest[2] = dsp_core.registers[DSP_REG_A0];
5883: newsr = dsp_add56(source, dest);
5884:
5885: dsp_core.registers[DSP_REG_A2] = dest[0];
5886: dsp_core.registers[DSP_REG_A1] = dest[1];
5887: dsp_core.registers[DSP_REG_A0] = dest[2];
5888:
5889: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5890:
5891: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5892: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5893: }
5894:
5895: static void dsp_mac_p_x1_x0_b(void)
5896: {
5897: Uint32 source[3], dest[3];
5898: Uint16 newsr;
5899:
5900: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5901:
5902: dest[0] = dsp_core.registers[DSP_REG_B2];
5903: dest[1] = dsp_core.registers[DSP_REG_B1];
5904: dest[2] = dsp_core.registers[DSP_REG_B0];
5905: newsr = dsp_add56(source, dest);
5906:
5907: dsp_core.registers[DSP_REG_B2] = dest[0];
5908: dsp_core.registers[DSP_REG_B1] = dest[1];
5909: dsp_core.registers[DSP_REG_B0] = dest[2];
5910:
5911: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5912:
5913: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5914: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5915: }
5916:
5917: static void dsp_mac_m_x1_x0_b(void)
5918: {
5919: Uint32 source[3], dest[3];
5920: Uint16 newsr;
5921:
5922: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5923:
5924: dest[0] = dsp_core.registers[DSP_REG_B2];
5925: dest[1] = dsp_core.registers[DSP_REG_B1];
5926: dest[2] = dsp_core.registers[DSP_REG_B0];
5927: newsr = dsp_add56(source, dest);
5928:
5929: dsp_core.registers[DSP_REG_B2] = dest[0];
5930: dsp_core.registers[DSP_REG_B1] = dest[1];
5931: dsp_core.registers[DSP_REG_B0] = dest[2];
5932:
5933: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5934:
5935: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5936: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5937: }
5938:
5939: static void dsp_mac_p_y1_y0_a(void)
5940: {
5941: Uint32 source[3], dest[3];
5942: Uint16 newsr;
5943:
5944: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5945:
5946: dest[0] = dsp_core.registers[DSP_REG_A2];
5947: dest[1] = dsp_core.registers[DSP_REG_A1];
5948: dest[2] = dsp_core.registers[DSP_REG_A0];
5949: newsr = dsp_add56(source, dest);
5950:
5951: dsp_core.registers[DSP_REG_A2] = dest[0];
5952: dsp_core.registers[DSP_REG_A1] = dest[1];
5953: dsp_core.registers[DSP_REG_A0] = dest[2];
5954:
5955: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5956:
5957: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5958: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5959: }
5960:
5961: static void dsp_mac_m_y1_y0_a(void)
5962: {
5963: Uint32 source[3], dest[3];
5964: Uint16 newsr;
5965:
5966: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5967:
5968: dest[0] = dsp_core.registers[DSP_REG_A2];
5969: dest[1] = dsp_core.registers[DSP_REG_A1];
5970: dest[2] = dsp_core.registers[DSP_REG_A0];
5971: newsr = dsp_add56(source, dest);
5972:
5973: dsp_core.registers[DSP_REG_A2] = dest[0];
5974: dsp_core.registers[DSP_REG_A1] = dest[1];
5975: dsp_core.registers[DSP_REG_A0] = dest[2];
5976:
5977: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5978:
5979: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5980: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5981: }
5982:
5983: static void dsp_mac_p_y1_y0_b(void)
5984: {
5985: Uint32 source[3], dest[3];
5986: Uint16 newsr;
5987:
5988: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5989:
5990: dest[0] = dsp_core.registers[DSP_REG_B2];
5991: dest[1] = dsp_core.registers[DSP_REG_B1];
5992: dest[2] = dsp_core.registers[DSP_REG_B0];
5993: newsr = dsp_add56(source, dest);
5994:
5995: dsp_core.registers[DSP_REG_B2] = dest[0];
5996: dsp_core.registers[DSP_REG_B1] = dest[1];
5997: dsp_core.registers[DSP_REG_B0] = dest[2];
5998:
5999: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6000:
6001: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6002: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6003: }
6004:
6005: static void dsp_mac_m_y1_y0_b(void)
6006: {
6007: Uint32 source[3], dest[3];
6008: Uint16 newsr;
6009:
6010: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6011:
6012: dest[0] = dsp_core.registers[DSP_REG_B2];
6013: dest[1] = dsp_core.registers[DSP_REG_B1];
6014: dest[2] = dsp_core.registers[DSP_REG_B0];
6015: newsr = dsp_add56(source, dest);
6016:
6017: dsp_core.registers[DSP_REG_B2] = dest[0];
6018: dsp_core.registers[DSP_REG_B1] = dest[1];
6019: dsp_core.registers[DSP_REG_B0] = dest[2];
6020:
6021: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6022:
6023: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6024: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6025: }
6026:
6027: static void dsp_mac_p_x0_y1_a(void)
6028: {
6029: Uint32 source[3], dest[3];
6030: Uint16 newsr;
6031:
6032: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6033:
6034: dest[0] = dsp_core.registers[DSP_REG_A2];
6035: dest[1] = dsp_core.registers[DSP_REG_A1];
6036: dest[2] = dsp_core.registers[DSP_REG_A0];
6037: newsr = dsp_add56(source, dest);
6038:
6039: dsp_core.registers[DSP_REG_A2] = dest[0];
6040: dsp_core.registers[DSP_REG_A1] = dest[1];
6041: dsp_core.registers[DSP_REG_A0] = dest[2];
6042:
6043: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6044:
6045: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6046: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6047: }
6048:
6049: static void dsp_mac_m_x0_y1_a(void)
6050: {
6051: Uint32 source[3], dest[3];
6052: Uint16 newsr;
6053:
6054: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6055:
6056: dest[0] = dsp_core.registers[DSP_REG_A2];
6057: dest[1] = dsp_core.registers[DSP_REG_A1];
6058: dest[2] = dsp_core.registers[DSP_REG_A0];
6059: newsr = dsp_add56(source, dest);
6060:
6061: dsp_core.registers[DSP_REG_A2] = dest[0];
6062: dsp_core.registers[DSP_REG_A1] = dest[1];
6063: dsp_core.registers[DSP_REG_A0] = dest[2];
6064:
6065: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6066:
6067: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6068: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6069: }
6070:
6071: static void dsp_mac_p_x0_y1_b(void)
6072: {
6073: Uint32 source[3], dest[3];
6074: Uint16 newsr;
6075:
6076: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6077:
6078: dest[0] = dsp_core.registers[DSP_REG_B2];
6079: dest[1] = dsp_core.registers[DSP_REG_B1];
6080: dest[2] = dsp_core.registers[DSP_REG_B0];
6081: newsr = dsp_add56(source, dest);
6082:
6083: dsp_core.registers[DSP_REG_B2] = dest[0];
6084: dsp_core.registers[DSP_REG_B1] = dest[1];
6085: dsp_core.registers[DSP_REG_B0] = dest[2];
6086:
6087: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6088:
6089: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6090: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6091: }
6092:
6093: static void dsp_mac_m_x0_y1_b(void)
6094: {
6095: Uint32 source[3], dest[3];
6096: Uint16 newsr;
6097:
6098: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6099:
6100: dest[0] = dsp_core.registers[DSP_REG_B2];
6101: dest[1] = dsp_core.registers[DSP_REG_B1];
6102: dest[2] = dsp_core.registers[DSP_REG_B0];
6103: newsr = dsp_add56(source, dest);
6104:
6105: dsp_core.registers[DSP_REG_B2] = dest[0];
6106: dsp_core.registers[DSP_REG_B1] = dest[1];
6107: dsp_core.registers[DSP_REG_B0] = dest[2];
6108:
6109: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6110:
6111: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6112: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6113: }
6114:
6115: static void dsp_mac_p_y0_x0_a(void)
6116: {
6117: Uint32 source[3], dest[3];
6118: Uint16 newsr;
6119:
6120: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6121:
6122: dest[0] = dsp_core.registers[DSP_REG_A2];
6123: dest[1] = dsp_core.registers[DSP_REG_A1];
6124: dest[2] = dsp_core.registers[DSP_REG_A0];
6125: newsr = dsp_add56(source, dest);
6126:
6127: dsp_core.registers[DSP_REG_A2] = dest[0];
6128: dsp_core.registers[DSP_REG_A1] = dest[1];
6129: dsp_core.registers[DSP_REG_A0] = dest[2];
6130:
6131: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6132:
6133: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6134: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6135: }
6136:
6137: static void dsp_mac_m_y0_x0_a(void)
6138: {
6139: Uint32 source[3], dest[3];
6140: Uint16 newsr;
6141:
6142: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6143:
6144: dest[0] = dsp_core.registers[DSP_REG_A2];
6145: dest[1] = dsp_core.registers[DSP_REG_A1];
6146: dest[2] = dsp_core.registers[DSP_REG_A0];
6147: newsr = dsp_add56(source, dest);
6148:
6149: dsp_core.registers[DSP_REG_A2] = dest[0];
6150: dsp_core.registers[DSP_REG_A1] = dest[1];
6151: dsp_core.registers[DSP_REG_A0] = dest[2];
6152:
6153: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6154:
6155: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6156: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6157: }
6158:
6159: static void dsp_mac_p_y0_x0_b(void)
6160: {
6161: Uint32 source[3], dest[3];
6162: Uint16 newsr;
6163:
6164: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6165:
6166: dest[0] = dsp_core.registers[DSP_REG_B2];
6167: dest[1] = dsp_core.registers[DSP_REG_B1];
6168: dest[2] = dsp_core.registers[DSP_REG_B0];
6169: newsr = dsp_add56(source, dest);
6170:
6171: dsp_core.registers[DSP_REG_B2] = dest[0];
6172: dsp_core.registers[DSP_REG_B1] = dest[1];
6173: dsp_core.registers[DSP_REG_B0] = dest[2];
6174:
6175: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6176:
6177: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6178: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6179: }
6180:
6181: static void dsp_mac_m_y0_x0_b(void)
6182: {
6183: Uint32 source[3], dest[3];
6184: Uint16 newsr;
6185:
6186: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6187:
6188: dest[0] = dsp_core.registers[DSP_REG_B2];
6189: dest[1] = dsp_core.registers[DSP_REG_B1];
6190: dest[2] = dsp_core.registers[DSP_REG_B0];
6191: newsr = dsp_add56(source, dest);
6192:
6193: dsp_core.registers[DSP_REG_B2] = dest[0];
6194: dsp_core.registers[DSP_REG_B1] = dest[1];
6195: dsp_core.registers[DSP_REG_B0] = dest[2];
6196:
6197: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6198:
6199: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6200: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6201: }
6202:
6203: static void dsp_mac_p_x1_y0_a(void)
6204: {
6205: Uint32 source[3], dest[3];
6206: Uint16 newsr;
6207:
6208: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6209:
6210: dest[0] = dsp_core.registers[DSP_REG_A2];
6211: dest[1] = dsp_core.registers[DSP_REG_A1];
6212: dest[2] = dsp_core.registers[DSP_REG_A0];
6213: newsr = dsp_add56(source, dest);
6214:
6215: dsp_core.registers[DSP_REG_A2] = dest[0];
6216: dsp_core.registers[DSP_REG_A1] = dest[1];
6217: dsp_core.registers[DSP_REG_A0] = dest[2];
6218:
6219: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6220:
6221: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6222: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6223: }
6224:
6225: static void dsp_mac_m_x1_y0_a(void)
6226: {
6227: Uint32 source[3], dest[3];
6228: Uint16 newsr;
6229:
6230: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6231:
6232: dest[0] = dsp_core.registers[DSP_REG_A2];
6233: dest[1] = dsp_core.registers[DSP_REG_A1];
6234: dest[2] = dsp_core.registers[DSP_REG_A0];
6235: newsr = dsp_add56(source, dest);
6236:
6237: dsp_core.registers[DSP_REG_A2] = dest[0];
6238: dsp_core.registers[DSP_REG_A1] = dest[1];
6239: dsp_core.registers[DSP_REG_A0] = dest[2];
6240:
6241: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6242:
6243: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6244: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6245: }
6246:
6247: static void dsp_mac_p_x1_y0_b(void)
6248: {
6249: Uint32 source[3], dest[3];
6250: Uint16 newsr;
6251:
6252: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6253:
6254: dest[0] = dsp_core.registers[DSP_REG_B2];
6255: dest[1] = dsp_core.registers[DSP_REG_B1];
6256: dest[2] = dsp_core.registers[DSP_REG_B0];
6257: newsr = dsp_add56(source, dest);
6258:
6259: dsp_core.registers[DSP_REG_B2] = dest[0];
6260: dsp_core.registers[DSP_REG_B1] = dest[1];
6261: dsp_core.registers[DSP_REG_B0] = dest[2];
6262:
6263: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6264:
6265: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6266: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6267: }
6268:
6269: static void dsp_mac_m_x1_y0_b(void)
6270: {
6271: Uint32 source[3], dest[3];
6272: Uint16 newsr;
6273:
6274: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6275:
6276: dest[0] = dsp_core.registers[DSP_REG_B2];
6277: dest[1] = dsp_core.registers[DSP_REG_B1];
6278: dest[2] = dsp_core.registers[DSP_REG_B0];
6279: newsr = dsp_add56(source, dest);
6280:
6281: dsp_core.registers[DSP_REG_B2] = dest[0];
6282: dsp_core.registers[DSP_REG_B1] = dest[1];
6283: dsp_core.registers[DSP_REG_B0] = dest[2];
6284:
6285: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6286:
6287: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6288: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6289: }
6290:
6291: static void dsp_mac_p_y1_x1_a(void)
6292: {
6293: Uint32 source[3], dest[3];
6294: Uint16 newsr;
6295:
6296: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6297:
6298: dest[0] = dsp_core.registers[DSP_REG_A2];
6299: dest[1] = dsp_core.registers[DSP_REG_A1];
6300: dest[2] = dsp_core.registers[DSP_REG_A0];
6301: newsr = dsp_add56(source, dest);
6302:
6303: dsp_core.registers[DSP_REG_A2] = dest[0];
6304: dsp_core.registers[DSP_REG_A1] = dest[1];
6305: dsp_core.registers[DSP_REG_A0] = dest[2];
6306:
6307: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6308:
6309: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6310: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6311: }
6312:
6313: static void dsp_mac_m_y1_x1_a(void)
6314: {
6315: Uint32 source[3], dest[3];
6316: Uint16 newsr;
6317:
6318: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6319:
6320: dest[0] = dsp_core.registers[DSP_REG_A2];
6321: dest[1] = dsp_core.registers[DSP_REG_A1];
6322: dest[2] = dsp_core.registers[DSP_REG_A0];
6323: newsr = dsp_add56(source, dest);
6324:
6325: dsp_core.registers[DSP_REG_A2] = dest[0];
6326: dsp_core.registers[DSP_REG_A1] = dest[1];
6327: dsp_core.registers[DSP_REG_A0] = dest[2];
6328:
6329: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6330:
6331: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6332: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6333: }
6334:
6335: static void dsp_mac_p_y1_x1_b(void)
6336: {
6337: Uint32 source[3], dest[3];
6338: Uint16 newsr;
6339:
6340: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6341:
6342: dest[0] = dsp_core.registers[DSP_REG_B2];
6343: dest[1] = dsp_core.registers[DSP_REG_B1];
6344: dest[2] = dsp_core.registers[DSP_REG_B0];
6345: newsr = dsp_add56(source, dest);
6346:
6347: dsp_core.registers[DSP_REG_B2] = dest[0];
6348: dsp_core.registers[DSP_REG_B1] = dest[1];
6349: dsp_core.registers[DSP_REG_B0] = dest[2];
6350:
6351: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6352:
6353: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6354: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6355: }
6356:
6357: static void dsp_mac_m_y1_x1_b(void)
6358: {
6359: Uint32 source[3], dest[3];
6360: Uint16 newsr;
6361:
6362: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6363:
6364: dest[0] = dsp_core.registers[DSP_REG_B2];
6365: dest[1] = dsp_core.registers[DSP_REG_B1];
6366: dest[2] = dsp_core.registers[DSP_REG_B0];
6367: newsr = dsp_add56(source, dest);
6368:
6369: dsp_core.registers[DSP_REG_B2] = dest[0];
6370: dsp_core.registers[DSP_REG_B1] = dest[1];
6371: dsp_core.registers[DSP_REG_B0] = dest[2];
6372:
6373: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6374:
6375: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6376: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6377: }
6378:
6379: static void dsp_macr_p_x0_x0_a(void)
6380: {
6381: Uint32 source[3], dest[3];
6382: Uint16 newsr;
6383:
6384: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6385:
6386: dest[0] = dsp_core.registers[DSP_REG_A2];
6387: dest[1] = dsp_core.registers[DSP_REG_A1];
6388: dest[2] = dsp_core.registers[DSP_REG_A0];
6389: newsr = dsp_add56(source, dest);
6390:
6391: dsp_rnd56(dest);
6392:
6393: dsp_core.registers[DSP_REG_A2] = dest[0];
6394: dsp_core.registers[DSP_REG_A1] = dest[1];
6395: dsp_core.registers[DSP_REG_A0] = dest[2];
6396:
6397: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6398:
6399: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6400: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6401: }
6402:
6403: static void dsp_macr_m_x0_x0_a(void)
6404: {
6405: Uint32 source[3], dest[3];
6406: Uint16 newsr;
6407:
6408: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6409:
6410: dest[0] = dsp_core.registers[DSP_REG_A2];
6411: dest[1] = dsp_core.registers[DSP_REG_A1];
6412: dest[2] = dsp_core.registers[DSP_REG_A0];
6413: newsr = dsp_add56(source, dest);
6414:
6415: dsp_rnd56(dest);
6416:
6417: dsp_core.registers[DSP_REG_A2] = dest[0];
6418: dsp_core.registers[DSP_REG_A1] = dest[1];
6419: dsp_core.registers[DSP_REG_A0] = dest[2];
6420:
6421: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6422:
6423: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6424: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6425: }
6426: static void dsp_macr_p_x0_x0_b(void)
6427: {
6428: Uint32 source[3], dest[3];
6429: Uint16 newsr;
6430:
6431: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6432:
6433: dest[0] = dsp_core.registers[DSP_REG_B2];
6434: dest[1] = dsp_core.registers[DSP_REG_B1];
6435: dest[2] = dsp_core.registers[DSP_REG_B0];
6436: newsr = dsp_add56(source, dest);
6437:
6438: dsp_rnd56(dest);
6439:
6440: dsp_core.registers[DSP_REG_B2] = dest[0];
6441: dsp_core.registers[DSP_REG_B1] = dest[1];
6442: dsp_core.registers[DSP_REG_B0] = dest[2];
6443:
6444: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6445:
6446: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6447: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6448: }
6449:
6450: static void dsp_macr_m_x0_x0_b(void)
6451: {
6452: Uint32 source[3], dest[3];
6453: Uint16 newsr;
6454:
6455: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6456:
6457: dest[0] = dsp_core.registers[DSP_REG_B2];
6458: dest[1] = dsp_core.registers[DSP_REG_B1];
6459: dest[2] = dsp_core.registers[DSP_REG_B0];
6460: newsr = dsp_add56(source, dest);
6461:
6462: dsp_rnd56(dest);
6463:
6464: dsp_core.registers[DSP_REG_B2] = dest[0];
6465: dsp_core.registers[DSP_REG_B1] = dest[1];
6466: dsp_core.registers[DSP_REG_B0] = dest[2];
6467:
6468: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6469:
6470: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6471: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6472: }
6473:
6474: static void dsp_macr_p_y0_y0_a(void)
6475: {
6476: Uint32 source[3], dest[3];
6477: Uint16 newsr;
6478:
6479: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6480:
6481: dest[0] = dsp_core.registers[DSP_REG_A2];
6482: dest[1] = dsp_core.registers[DSP_REG_A1];
6483: dest[2] = dsp_core.registers[DSP_REG_A0];
6484: newsr = dsp_add56(source, dest);
6485:
6486: dsp_rnd56(dest);
6487:
6488: dsp_core.registers[DSP_REG_A2] = dest[0];
6489: dsp_core.registers[DSP_REG_A1] = dest[1];
6490: dsp_core.registers[DSP_REG_A0] = dest[2];
6491:
6492: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6493:
6494: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6495: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6496: }
6497:
6498: static void dsp_macr_m_y0_y0_a(void)
6499: {
6500: Uint32 source[3], dest[3];
6501: Uint16 newsr;
6502:
6503: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6504:
6505: dest[0] = dsp_core.registers[DSP_REG_A2];
6506: dest[1] = dsp_core.registers[DSP_REG_A1];
6507: dest[2] = dsp_core.registers[DSP_REG_A0];
6508: newsr = dsp_add56(source, dest);
6509:
6510: dsp_rnd56(dest);
6511:
6512: dsp_core.registers[DSP_REG_A2] = dest[0];
6513: dsp_core.registers[DSP_REG_A1] = dest[1];
6514: dsp_core.registers[DSP_REG_A0] = dest[2];
6515:
6516: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6517:
6518: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6519: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6520: }
6521: static void dsp_macr_p_y0_y0_b(void)
6522: {
6523: Uint32 source[3], dest[3];
6524: Uint16 newsr;
6525:
6526: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6527:
6528: dest[0] = dsp_core.registers[DSP_REG_B2];
6529: dest[1] = dsp_core.registers[DSP_REG_B1];
6530: dest[2] = dsp_core.registers[DSP_REG_B0];
6531: newsr = dsp_add56(source, dest);
6532:
6533: dsp_rnd56(dest);
6534:
6535: dsp_core.registers[DSP_REG_B2] = dest[0];
6536: dsp_core.registers[DSP_REG_B1] = dest[1];
6537: dsp_core.registers[DSP_REG_B0] = dest[2];
6538:
6539: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6540:
6541: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6542: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6543: }
6544:
6545: static void dsp_macr_m_y0_y0_b(void)
6546: {
6547: Uint32 source[3], dest[3];
6548: Uint16 newsr;
6549:
6550: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6551:
6552: dest[0] = dsp_core.registers[DSP_REG_B2];
6553: dest[1] = dsp_core.registers[DSP_REG_B1];
6554: dest[2] = dsp_core.registers[DSP_REG_B0];
6555: newsr = dsp_add56(source, dest);
6556:
6557: dsp_rnd56(dest);
6558:
6559: dsp_core.registers[DSP_REG_B2] = dest[0];
6560: dsp_core.registers[DSP_REG_B1] = dest[1];
6561: dsp_core.registers[DSP_REG_B0] = dest[2];
6562:
6563: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6564:
6565: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6566: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6567: }
6568:
6569: static void dsp_macr_p_x1_x0_a(void)
6570: {
6571: Uint32 source[3], dest[3];
6572: Uint16 newsr;
6573:
6574: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6575:
6576: dest[0] = dsp_core.registers[DSP_REG_A2];
6577: dest[1] = dsp_core.registers[DSP_REG_A1];
6578: dest[2] = dsp_core.registers[DSP_REG_A0];
6579: newsr = dsp_add56(source, dest);
6580:
6581: dsp_rnd56(dest);
6582:
6583: dsp_core.registers[DSP_REG_A2] = dest[0];
6584: dsp_core.registers[DSP_REG_A1] = dest[1];
6585: dsp_core.registers[DSP_REG_A0] = dest[2];
6586:
6587: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6588:
6589: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6590: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6591: }
6592:
6593: static void dsp_macr_m_x1_x0_a(void)
6594: {
6595: Uint32 source[3], dest[3];
6596: Uint16 newsr;
6597:
6598: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6599:
6600: dest[0] = dsp_core.registers[DSP_REG_A2];
6601: dest[1] = dsp_core.registers[DSP_REG_A1];
6602: dest[2] = dsp_core.registers[DSP_REG_A0];
6603: newsr = dsp_add56(source, dest);
6604:
6605: dsp_rnd56(dest);
6606:
6607: dsp_core.registers[DSP_REG_A2] = dest[0];
6608: dsp_core.registers[DSP_REG_A1] = dest[1];
6609: dsp_core.registers[DSP_REG_A0] = dest[2];
6610:
6611: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6612:
6613: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6614: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6615: }
6616:
6617: static void dsp_macr_p_x1_x0_b(void)
6618: {
6619: Uint32 source[3], dest[3];
6620: Uint16 newsr;
6621:
6622: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6623:
6624: dest[0] = dsp_core.registers[DSP_REG_B2];
6625: dest[1] = dsp_core.registers[DSP_REG_B1];
6626: dest[2] = dsp_core.registers[DSP_REG_B0];
6627: newsr = dsp_add56(source, dest);
6628:
6629: dsp_rnd56(dest);
6630:
6631: dsp_core.registers[DSP_REG_B2] = dest[0];
6632: dsp_core.registers[DSP_REG_B1] = dest[1];
6633: dsp_core.registers[DSP_REG_B0] = dest[2];
6634:
6635: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6636:
6637: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6638: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6639: }
6640:
6641: static void dsp_macr_m_x1_x0_b(void)
6642: {
6643: Uint32 source[3], dest[3];
6644: Uint16 newsr;
6645:
6646: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6647:
6648: dest[0] = dsp_core.registers[DSP_REG_B2];
6649: dest[1] = dsp_core.registers[DSP_REG_B1];
6650: dest[2] = dsp_core.registers[DSP_REG_B0];
6651: newsr = dsp_add56(source, dest);
6652:
6653: dsp_rnd56(dest);
6654:
6655: dsp_core.registers[DSP_REG_B2] = dest[0];
6656: dsp_core.registers[DSP_REG_B1] = dest[1];
6657: dsp_core.registers[DSP_REG_B0] = dest[2];
6658:
6659: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6660:
6661: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6662: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6663: }
6664:
6665: static void dsp_macr_p_y1_y0_a(void)
6666: {
6667: Uint32 source[3], dest[3];
6668: Uint16 newsr;
6669:
6670: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6671:
6672: dest[0] = dsp_core.registers[DSP_REG_A2];
6673: dest[1] = dsp_core.registers[DSP_REG_A1];
6674: dest[2] = dsp_core.registers[DSP_REG_A0];
6675: newsr = dsp_add56(source, dest);
6676:
6677: dsp_rnd56(dest);
6678:
6679: dsp_core.registers[DSP_REG_A2] = dest[0];
6680: dsp_core.registers[DSP_REG_A1] = dest[1];
6681: dsp_core.registers[DSP_REG_A0] = dest[2];
6682:
6683: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6684:
6685: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6686: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6687: }
6688:
6689: static void dsp_macr_m_y1_y0_a(void)
6690: {
6691: Uint32 source[3], dest[3];
6692: Uint16 newsr;
6693:
6694: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6695:
6696: dest[0] = dsp_core.registers[DSP_REG_A2];
6697: dest[1] = dsp_core.registers[DSP_REG_A1];
6698: dest[2] = dsp_core.registers[DSP_REG_A0];
6699: newsr = dsp_add56(source, dest);
6700:
6701: dsp_rnd56(dest);
6702:
6703: dsp_core.registers[DSP_REG_A2] = dest[0];
6704: dsp_core.registers[DSP_REG_A1] = dest[1];
6705: dsp_core.registers[DSP_REG_A0] = dest[2];
6706:
6707: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6708:
6709: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6710: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6711: }
6712:
6713: static void dsp_macr_p_y1_y0_b(void)
6714: {
6715: Uint32 source[3], dest[3];
6716: Uint16 newsr;
6717:
6718: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6719:
6720: dest[0] = dsp_core.registers[DSP_REG_B2];
6721: dest[1] = dsp_core.registers[DSP_REG_B1];
6722: dest[2] = dsp_core.registers[DSP_REG_B0];
6723: newsr = dsp_add56(source, dest);
6724:
6725: dsp_rnd56(dest);
6726:
6727: dsp_core.registers[DSP_REG_B2] = dest[0];
6728: dsp_core.registers[DSP_REG_B1] = dest[1];
6729: dsp_core.registers[DSP_REG_B0] = dest[2];
6730:
6731: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6732:
6733: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6734: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6735: }
6736:
6737: static void dsp_macr_m_y1_y0_b(void)
6738: {
6739: Uint32 source[3], dest[3];
6740: Uint16 newsr;
6741:
6742: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6743:
6744: dest[0] = dsp_core.registers[DSP_REG_B2];
6745: dest[1] = dsp_core.registers[DSP_REG_B1];
6746: dest[2] = dsp_core.registers[DSP_REG_B0];
6747: newsr = dsp_add56(source, dest);
6748:
6749: dsp_rnd56(dest);
6750:
6751: dsp_core.registers[DSP_REG_B2] = dest[0];
6752: dsp_core.registers[DSP_REG_B1] = dest[1];
6753: dsp_core.registers[DSP_REG_B0] = dest[2];
6754:
6755: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6756:
6757: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6758: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6759: }
6760:
6761: static void dsp_macr_p_x0_y1_a(void)
6762: {
6763: Uint32 source[3], dest[3];
6764: Uint16 newsr;
6765:
6766: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6767:
6768: dest[0] = dsp_core.registers[DSP_REG_A2];
6769: dest[1] = dsp_core.registers[DSP_REG_A1];
6770: dest[2] = dsp_core.registers[DSP_REG_A0];
6771: newsr = dsp_add56(source, dest);
6772:
6773: dsp_rnd56(dest);
6774:
6775: dsp_core.registers[DSP_REG_A2] = dest[0];
6776: dsp_core.registers[DSP_REG_A1] = dest[1];
6777: dsp_core.registers[DSP_REG_A0] = dest[2];
6778:
6779: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6780:
6781: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6782: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6783: }
6784:
6785: static void dsp_macr_m_x0_y1_a(void)
6786: {
6787: Uint32 source[3], dest[3];
6788: Uint16 newsr;
6789:
6790: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6791:
6792: dest[0] = dsp_core.registers[DSP_REG_A2];
6793: dest[1] = dsp_core.registers[DSP_REG_A1];
6794: dest[2] = dsp_core.registers[DSP_REG_A0];
6795: newsr = dsp_add56(source, dest);
6796:
6797: dsp_rnd56(dest);
6798:
6799: dsp_core.registers[DSP_REG_A2] = dest[0];
6800: dsp_core.registers[DSP_REG_A1] = dest[1];
6801: dsp_core.registers[DSP_REG_A0] = dest[2];
6802:
6803: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6804:
6805: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6806: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6807: }
6808:
6809: static void dsp_macr_p_x0_y1_b(void)
6810: {
6811: Uint32 source[3], dest[3];
6812: Uint16 newsr;
6813:
6814: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6815:
6816: dest[0] = dsp_core.registers[DSP_REG_B2];
6817: dest[1] = dsp_core.registers[DSP_REG_B1];
6818: dest[2] = dsp_core.registers[DSP_REG_B0];
6819: newsr = dsp_add56(source, dest);
6820:
6821: dsp_rnd56(dest);
6822:
6823: dsp_core.registers[DSP_REG_B2] = dest[0];
6824: dsp_core.registers[DSP_REG_B1] = dest[1];
6825: dsp_core.registers[DSP_REG_B0] = dest[2];
6826:
6827: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6828:
6829: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6830: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6831: }
6832:
6833: static void dsp_macr_m_x0_y1_b(void)
6834: {
6835: Uint32 source[3], dest[3];
6836: Uint16 newsr;
6837:
6838: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6839:
6840: dest[0] = dsp_core.registers[DSP_REG_B2];
6841: dest[1] = dsp_core.registers[DSP_REG_B1];
6842: dest[2] = dsp_core.registers[DSP_REG_B0];
6843: newsr = dsp_add56(source, dest);
6844:
6845: dsp_rnd56(dest);
6846:
6847: dsp_core.registers[DSP_REG_B2] = dest[0];
6848: dsp_core.registers[DSP_REG_B1] = dest[1];
6849: dsp_core.registers[DSP_REG_B0] = dest[2];
6850:
6851: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6852:
6853: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6854: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6855: }
6856:
6857: static void dsp_macr_p_y0_x0_a(void)
6858: {
6859: Uint32 source[3], dest[3];
6860: Uint16 newsr;
6861:
6862: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6863:
6864: dest[0] = dsp_core.registers[DSP_REG_A2];
6865: dest[1] = dsp_core.registers[DSP_REG_A1];
6866: dest[2] = dsp_core.registers[DSP_REG_A0];
6867: newsr = dsp_add56(source, dest);
6868:
6869: dsp_rnd56(dest);
6870:
6871: dsp_core.registers[DSP_REG_A2] = dest[0];
6872: dsp_core.registers[DSP_REG_A1] = dest[1];
6873: dsp_core.registers[DSP_REG_A0] = dest[2];
6874:
6875: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6876:
6877: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6878: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6879: }
6880:
6881: static void dsp_macr_m_y0_x0_a(void)
6882: {
6883: Uint32 source[3], dest[3];
6884: Uint16 newsr;
6885:
6886: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6887:
6888: dest[0] = dsp_core.registers[DSP_REG_A2];
6889: dest[1] = dsp_core.registers[DSP_REG_A1];
6890: dest[2] = dsp_core.registers[DSP_REG_A0];
6891: newsr = dsp_add56(source, dest);
6892:
6893: dsp_rnd56(dest);
6894:
6895: dsp_core.registers[DSP_REG_A2] = dest[0];
6896: dsp_core.registers[DSP_REG_A1] = dest[1];
6897: dsp_core.registers[DSP_REG_A0] = dest[2];
6898:
6899: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6900:
6901: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6902: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6903: }
6904:
6905: static void dsp_macr_p_y0_x0_b(void)
6906: {
6907: Uint32 source[3], dest[3];
6908: Uint16 newsr;
6909:
6910: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6911:
6912: dest[0] = dsp_core.registers[DSP_REG_B2];
6913: dest[1] = dsp_core.registers[DSP_REG_B1];
6914: dest[2] = dsp_core.registers[DSP_REG_B0];
6915: newsr = dsp_add56(source, dest);
6916:
6917: dsp_rnd56(dest);
6918:
6919: dsp_core.registers[DSP_REG_B2] = dest[0];
6920: dsp_core.registers[DSP_REG_B1] = dest[1];
6921: dsp_core.registers[DSP_REG_B0] = dest[2];
6922:
6923: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6924:
6925: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6926: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6927: }
6928:
6929: static void dsp_macr_m_y0_x0_b(void)
6930: {
6931: Uint32 source[3], dest[3];
6932: Uint16 newsr;
6933:
6934: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6935:
6936: dest[0] = dsp_core.registers[DSP_REG_B2];
6937: dest[1] = dsp_core.registers[DSP_REG_B1];
6938: dest[2] = dsp_core.registers[DSP_REG_B0];
6939: newsr = dsp_add56(source, dest);
6940:
6941: dsp_rnd56(dest);
6942:
6943: dsp_core.registers[DSP_REG_B2] = dest[0];
6944: dsp_core.registers[DSP_REG_B1] = dest[1];
6945: dsp_core.registers[DSP_REG_B0] = dest[2];
6946:
6947: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6948:
6949: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6950: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6951: }
6952:
6953: static void dsp_macr_p_x1_y0_a(void)
6954: {
6955: Uint32 source[3], dest[3];
6956: Uint16 newsr;
6957:
6958: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6959:
6960: dest[0] = dsp_core.registers[DSP_REG_A2];
6961: dest[1] = dsp_core.registers[DSP_REG_A1];
6962: dest[2] = dsp_core.registers[DSP_REG_A0];
6963: newsr = dsp_add56(source, dest);
6964:
6965: dsp_rnd56(dest);
6966:
6967: dsp_core.registers[DSP_REG_A2] = dest[0];
6968: dsp_core.registers[DSP_REG_A1] = dest[1];
6969: dsp_core.registers[DSP_REG_A0] = dest[2];
6970:
6971: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6972:
6973: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6974: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6975: }
6976:
6977: static void dsp_macr_m_x1_y0_a(void)
6978: {
6979: Uint32 source[3], dest[3];
6980: Uint16 newsr;
6981:
6982: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6983:
6984: dest[0] = dsp_core.registers[DSP_REG_A2];
6985: dest[1] = dsp_core.registers[DSP_REG_A1];
6986: dest[2] = dsp_core.registers[DSP_REG_A0];
6987: newsr = dsp_add56(source, dest);
6988:
6989: dsp_rnd56(dest);
6990:
6991: dsp_core.registers[DSP_REG_A2] = dest[0];
6992: dsp_core.registers[DSP_REG_A1] = dest[1];
6993: dsp_core.registers[DSP_REG_A0] = dest[2];
6994:
6995: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6996:
6997: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6998: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6999: }
7000:
7001: static void dsp_macr_p_x1_y0_b(void)
7002: {
7003: Uint32 source[3], dest[3];
7004: Uint16 newsr;
7005:
7006: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7007:
7008: dest[0] = dsp_core.registers[DSP_REG_B2];
7009: dest[1] = dsp_core.registers[DSP_REG_B1];
7010: dest[2] = dsp_core.registers[DSP_REG_B0];
7011: newsr = dsp_add56(source, dest);
7012:
1.1.1.10 root 7013: dsp_rnd56(dest);
7014:
1.1.1.6 root 7015: dsp_core.registers[DSP_REG_B2] = dest[0];
7016: dsp_core.registers[DSP_REG_B1] = dest[1];
7017: dsp_core.registers[DSP_REG_B0] = dest[2];
7018:
7019: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7020:
7021: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7022: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7023: }
7024:
7025: static void dsp_macr_m_x1_y0_b(void)
7026: {
7027: Uint32 source[3], dest[3];
7028: Uint16 newsr;
7029:
7030: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7031:
7032: dest[0] = dsp_core.registers[DSP_REG_B2];
7033: dest[1] = dsp_core.registers[DSP_REG_B1];
7034: dest[2] = dsp_core.registers[DSP_REG_B0];
7035: newsr = dsp_add56(source, dest);
7036:
7037: dsp_rnd56(dest);
7038:
7039: dsp_core.registers[DSP_REG_B2] = dest[0];
7040: dsp_core.registers[DSP_REG_B1] = dest[1];
7041: dsp_core.registers[DSP_REG_B0] = dest[2];
7042:
7043: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7044:
7045: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7046: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7047: }
7048:
7049: static void dsp_macr_p_y1_x1_a(void)
7050: {
7051: Uint32 source[3], dest[3];
7052: Uint16 newsr;
7053:
7054: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7055:
7056: dest[0] = dsp_core.registers[DSP_REG_A2];
7057: dest[1] = dsp_core.registers[DSP_REG_A1];
7058: dest[2] = dsp_core.registers[DSP_REG_A0];
7059: newsr = dsp_add56(source, dest);
7060:
7061: dsp_rnd56(dest);
7062:
7063: dsp_core.registers[DSP_REG_A2] = dest[0];
7064: dsp_core.registers[DSP_REG_A1] = dest[1];
7065: dsp_core.registers[DSP_REG_A0] = dest[2];
7066:
7067: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7068:
7069: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7070: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7071: }
7072:
7073: static void dsp_macr_m_y1_x1_a(void)
7074: {
7075: Uint32 source[3], dest[3];
7076: Uint16 newsr;
7077:
7078: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7079:
7080: dest[0] = dsp_core.registers[DSP_REG_A2];
7081: dest[1] = dsp_core.registers[DSP_REG_A1];
7082: dest[2] = dsp_core.registers[DSP_REG_A0];
7083: newsr = dsp_add56(source, dest);
7084:
7085: dsp_rnd56(dest);
7086:
7087: dsp_core.registers[DSP_REG_A2] = dest[0];
7088: dsp_core.registers[DSP_REG_A1] = dest[1];
7089: dsp_core.registers[DSP_REG_A0] = dest[2];
7090:
7091: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7092:
7093: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7094: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7095: }
7096:
7097: static void dsp_macr_p_y1_x1_b(void)
7098: {
7099: Uint32 source[3], dest[3];
7100: Uint16 newsr;
7101:
7102: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7103:
7104: dest[0] = dsp_core.registers[DSP_REG_B2];
7105: dest[1] = dsp_core.registers[DSP_REG_B1];
7106: dest[2] = dsp_core.registers[DSP_REG_B0];
7107: newsr = dsp_add56(source, dest);
7108:
7109: dsp_rnd56(dest);
7110:
7111: dsp_core.registers[DSP_REG_B2] = dest[0];
7112: dsp_core.registers[DSP_REG_B1] = dest[1];
7113: dsp_core.registers[DSP_REG_B0] = dest[2];
7114:
7115: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7116:
7117: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7118: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7119: }
7120:
7121: static void dsp_macr_m_y1_x1_b(void)
7122: {
7123: Uint32 source[3], dest[3];
7124: Uint16 newsr;
7125:
7126: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7127:
7128: dest[0] = dsp_core.registers[DSP_REG_B2];
7129: dest[1] = dsp_core.registers[DSP_REG_B1];
7130: dest[2] = dsp_core.registers[DSP_REG_B0];
7131: newsr = dsp_add56(source, dest);
7132:
7133: dsp_rnd56(dest);
7134:
7135: dsp_core.registers[DSP_REG_B2] = dest[0];
7136: dsp_core.registers[DSP_REG_B1] = dest[1];
7137: dsp_core.registers[DSP_REG_B0] = dest[2];
7138:
7139: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7140:
7141: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7142: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7143: }
7144:
7145:
7146: static void dsp_move(void)
7147: {
7148: /* move instruction inside alu opcodes
7149: taken care of by parallel move dispatcher */
7150: }
7151:
7152: static void dsp_mpy_p_x0_x0_a(void)
7153: {
7154: Uint32 source[3];
7155:
7156: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7157:
7158: dsp_core.registers[DSP_REG_A2] = source[0];
7159: dsp_core.registers[DSP_REG_A1] = source[1];
7160: dsp_core.registers[DSP_REG_A0] = source[2];
7161:
7162: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7163: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7164: }
7165:
7166: static void dsp_mpy_m_x0_x0_a(void)
7167: {
7168: Uint32 source[3];
7169:
7170: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7171:
7172: dsp_core.registers[DSP_REG_A2] = source[0];
7173: dsp_core.registers[DSP_REG_A1] = source[1];
7174: dsp_core.registers[DSP_REG_A0] = source[2];
7175:
7176: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7177: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7178: }
7179:
7180: static void dsp_mpy_p_x0_x0_b(void)
7181: {
7182: Uint32 source[3];
7183:
7184: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7185:
7186: dsp_core.registers[DSP_REG_B2] = source[0];
7187: dsp_core.registers[DSP_REG_B1] = source[1];
7188: dsp_core.registers[DSP_REG_B0] = source[2];
7189:
7190: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7191: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7192: }
7193:
7194: static void dsp_mpy_m_x0_x0_b(void)
7195: {
7196: Uint32 source[3];
7197:
7198:
7199: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7200:
7201: dsp_core.registers[DSP_REG_B2] = source[0];
7202: dsp_core.registers[DSP_REG_B1] = source[1];
7203: dsp_core.registers[DSP_REG_B0] = source[2];
7204:
7205: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7206: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7207: }
7208:
7209: static void dsp_mpy_p_y0_y0_a(void)
7210: {
7211: Uint32 source[3];
7212:
7213: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7214:
7215: dsp_core.registers[DSP_REG_A2] = source[0];
7216: dsp_core.registers[DSP_REG_A1] = source[1];
7217: dsp_core.registers[DSP_REG_A0] = source[2];
7218:
7219: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7220: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7221: }
7222:
7223: static void dsp_mpy_m_y0_y0_a(void)
7224: {
7225: Uint32 source[3];
7226:
7227: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7228:
7229: dsp_core.registers[DSP_REG_A2] = source[0];
7230: dsp_core.registers[DSP_REG_A1] = source[1];
7231: dsp_core.registers[DSP_REG_A0] = source[2];
7232:
7233: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7234: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7235: }
7236:
7237: static void dsp_mpy_p_y0_y0_b(void)
7238: {
7239: Uint32 source[3];
7240:
7241: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7242:
7243: dsp_core.registers[DSP_REG_B2] = source[0];
7244: dsp_core.registers[DSP_REG_B1] = source[1];
7245: dsp_core.registers[DSP_REG_B0] = source[2];
7246:
7247: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7248: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7249: }
7250:
7251: static void dsp_mpy_m_y0_y0_b(void)
7252: {
7253: Uint32 source[3];
7254:
7255: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7256:
7257: dsp_core.registers[DSP_REG_B2] = source[0];
7258: dsp_core.registers[DSP_REG_B1] = source[1];
7259: dsp_core.registers[DSP_REG_B0] = source[2];
7260:
7261: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7262: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7263: }
7264:
7265: static void dsp_mpy_p_x1_x0_a(void)
7266: {
7267: Uint32 source[3];
7268:
7269: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7270:
7271: dsp_core.registers[DSP_REG_A2] = source[0];
7272: dsp_core.registers[DSP_REG_A1] = source[1];
7273: dsp_core.registers[DSP_REG_A0] = source[2];
7274:
7275: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7276: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7277: }
7278:
7279: static void dsp_mpy_m_x1_x0_a(void)
7280: {
7281: Uint32 source[3];
7282:
7283: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7284:
7285: dsp_core.registers[DSP_REG_A2] = source[0];
7286: dsp_core.registers[DSP_REG_A1] = source[1];
7287: dsp_core.registers[DSP_REG_A0] = source[2];
7288:
7289: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7290: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7291: }
7292:
7293: static void dsp_mpy_p_x1_x0_b(void)
7294: {
7295: Uint32 source[3];
7296:
7297: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7298:
7299: dsp_core.registers[DSP_REG_B2] = source[0];
7300: dsp_core.registers[DSP_REG_B1] = source[1];
7301: dsp_core.registers[DSP_REG_B0] = source[2];
7302:
7303: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7304: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7305: }
7306:
7307: static void dsp_mpy_m_x1_x0_b(void)
7308: {
7309: Uint32 source[3];
7310:
7311: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7312:
7313: dsp_core.registers[DSP_REG_B2] = source[0];
7314: dsp_core.registers[DSP_REG_B1] = source[1];
7315: dsp_core.registers[DSP_REG_B0] = source[2];
7316:
7317: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7318: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7319: }
7320:
7321: static void dsp_mpy_p_y1_y0_a(void)
7322: {
7323: Uint32 source[3];
7324:
7325: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7326:
7327: dsp_core.registers[DSP_REG_A2] = source[0];
7328: dsp_core.registers[DSP_REG_A1] = source[1];
7329: dsp_core.registers[DSP_REG_A0] = source[2];
7330:
7331: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7332: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7333: }
7334:
7335: static void dsp_mpy_m_y1_y0_a(void)
7336: {
7337: Uint32 source[3];
7338:
7339: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7340:
7341: dsp_core.registers[DSP_REG_A2] = source[0];
7342: dsp_core.registers[DSP_REG_A1] = source[1];
7343: dsp_core.registers[DSP_REG_A0] = source[2];
7344:
7345: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7346: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7347: }
7348:
7349: static void dsp_mpy_p_y1_y0_b(void)
7350: {
7351: Uint32 source[3];
7352:
7353: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7354:
7355: dsp_core.registers[DSP_REG_B2] = source[0];
7356: dsp_core.registers[DSP_REG_B1] = source[1];
7357: dsp_core.registers[DSP_REG_B0] = source[2];
7358:
7359: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7360: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7361: }
7362:
7363: static void dsp_mpy_m_y1_y0_b(void)
7364: {
7365: Uint32 source[3];
7366:
7367: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7368:
7369: dsp_core.registers[DSP_REG_B2] = source[0];
7370: dsp_core.registers[DSP_REG_B1] = source[1];
7371: dsp_core.registers[DSP_REG_B0] = source[2];
7372:
7373: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7374: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7375: }
7376:
7377: static void dsp_mpy_p_x0_y1_a(void)
7378: {
7379: Uint32 source[3];
7380:
7381: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7382:
7383: dsp_core.registers[DSP_REG_A2] = source[0];
7384: dsp_core.registers[DSP_REG_A1] = source[1];
7385: dsp_core.registers[DSP_REG_A0] = source[2];
7386:
7387: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7388: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7389: }
7390:
7391: static void dsp_mpy_m_x0_y1_a(void)
7392: {
7393: Uint32 source[3];
7394:
7395: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7396:
7397: dsp_core.registers[DSP_REG_A2] = source[0];
7398: dsp_core.registers[DSP_REG_A1] = source[1];
7399: dsp_core.registers[DSP_REG_A0] = source[2];
7400:
7401: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7402: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7403: }
7404:
7405: static void dsp_mpy_p_x0_y1_b(void)
7406: {
7407: Uint32 source[3];
7408:
7409: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7410:
7411: dsp_core.registers[DSP_REG_B2] = source[0];
7412: dsp_core.registers[DSP_REG_B1] = source[1];
7413: dsp_core.registers[DSP_REG_B0] = source[2];
7414:
7415: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7416: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7417: }
7418:
7419: static void dsp_mpy_m_x0_y1_b(void)
7420: {
7421: Uint32 source[3];
7422:
7423: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7424:
7425: dsp_core.registers[DSP_REG_B2] = source[0];
7426: dsp_core.registers[DSP_REG_B1] = source[1];
7427: dsp_core.registers[DSP_REG_B0] = source[2];
7428:
7429: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7430: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7431: }
7432:
7433: static void dsp_mpy_p_y0_x0_a(void)
7434: {
7435: Uint32 source[3];
7436:
7437: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7438:
7439: dsp_core.registers[DSP_REG_A2] = source[0];
7440: dsp_core.registers[DSP_REG_A1] = source[1];
7441: dsp_core.registers[DSP_REG_A0] = source[2];
7442:
7443: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7444: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7445: }
7446:
7447: static void dsp_mpy_m_y0_x0_a(void)
7448: {
7449: Uint32 source[3];
7450:
7451: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7452:
7453: dsp_core.registers[DSP_REG_A2] = source[0];
7454: dsp_core.registers[DSP_REG_A1] = source[1];
7455: dsp_core.registers[DSP_REG_A0] = source[2];
7456:
7457: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7458: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7459: }
7460:
7461: static void dsp_mpy_p_y0_x0_b(void)
7462: {
7463: Uint32 source[3];
7464:
7465: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7466:
7467: dsp_core.registers[DSP_REG_B2] = source[0];
7468: dsp_core.registers[DSP_REG_B1] = source[1];
7469: dsp_core.registers[DSP_REG_B0] = source[2];
7470:
7471: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7472: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7473: }
7474:
7475: static void dsp_mpy_m_y0_x0_b(void)
7476: {
7477: Uint32 source[3];
7478:
7479: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7480:
7481: dsp_core.registers[DSP_REG_B2] = source[0];
7482: dsp_core.registers[DSP_REG_B1] = source[1];
7483: dsp_core.registers[DSP_REG_B0] = source[2];
7484:
7485: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7486: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7487: }
7488:
7489: static void dsp_mpy_p_x1_y0_a(void)
7490: {
7491: Uint32 source[3];
7492:
7493: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7494:
7495: dsp_core.registers[DSP_REG_A2] = source[0];
7496: dsp_core.registers[DSP_REG_A1] = source[1];
7497: dsp_core.registers[DSP_REG_A0] = source[2];
7498:
7499: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7500: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7501: }
7502:
7503: static void dsp_mpy_m_x1_y0_a(void)
7504: {
7505: Uint32 source[3];
7506:
7507: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7508:
7509: dsp_core.registers[DSP_REG_A2] = source[0];
7510: dsp_core.registers[DSP_REG_A1] = source[1];
7511: dsp_core.registers[DSP_REG_A0] = source[2];
7512:
7513: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7514: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7515: }
7516:
7517: static void dsp_mpy_p_x1_y0_b(void)
7518: {
7519: Uint32 source[3];
7520:
7521: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7522:
7523: dsp_core.registers[DSP_REG_B2] = source[0];
7524: dsp_core.registers[DSP_REG_B1] = source[1];
7525: dsp_core.registers[DSP_REG_B0] = source[2];
7526:
7527: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7528: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7529: }
7530:
7531: static void dsp_mpy_m_x1_y0_b(void)
7532: {
7533: Uint32 source[3];
7534:
7535: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7536:
7537: dsp_core.registers[DSP_REG_B2] = source[0];
7538: dsp_core.registers[DSP_REG_B1] = source[1];
7539: dsp_core.registers[DSP_REG_B0] = source[2];
7540:
7541: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7542: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7543: }
7544:
7545: static void dsp_mpy_p_y1_x1_a(void)
7546: {
7547: Uint32 source[3];
7548:
7549: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7550:
7551: dsp_core.registers[DSP_REG_A2] = source[0];
7552: dsp_core.registers[DSP_REG_A1] = source[1];
7553: dsp_core.registers[DSP_REG_A0] = source[2];
7554:
7555: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7556: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7557: }
7558:
7559: static void dsp_mpy_m_y1_x1_a(void)
7560: {
7561: Uint32 source[3];
7562:
7563: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7564:
7565: dsp_core.registers[DSP_REG_A2] = source[0];
7566: dsp_core.registers[DSP_REG_A1] = source[1];
7567: dsp_core.registers[DSP_REG_A0] = source[2];
7568:
7569: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7570: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7571: }
7572:
7573: static void dsp_mpy_p_y1_x1_b(void)
7574: {
7575: Uint32 source[3];
7576:
7577: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7578:
7579: dsp_core.registers[DSP_REG_B2] = source[0];
7580: dsp_core.registers[DSP_REG_B1] = source[1];
7581: dsp_core.registers[DSP_REG_B0] = source[2];
7582:
7583: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7584: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7585: }
7586:
7587: static void dsp_mpy_m_y1_x1_b(void)
7588: {
7589: Uint32 source[3];
7590:
7591: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7592:
7593: dsp_core.registers[DSP_REG_B2] = source[0];
7594: dsp_core.registers[DSP_REG_B1] = source[1];
7595: dsp_core.registers[DSP_REG_B0] = source[2];
7596:
7597: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7598: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7599: }
7600:
7601: static void dsp_mpyr_p_x0_x0_a(void)
7602: {
7603: Uint32 source[3];
7604:
7605: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7606: dsp_rnd56(source);
7607:
7608: dsp_core.registers[DSP_REG_A2] = source[0];
7609: dsp_core.registers[DSP_REG_A1] = source[1];
7610: dsp_core.registers[DSP_REG_A0] = source[2];
7611:
7612: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7613: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7614: }
7615:
7616: static void dsp_mpyr_m_x0_x0_a(void)
7617: {
7618: Uint32 source[3];
7619:
7620: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7621: dsp_rnd56(source);
7622:
7623: dsp_core.registers[DSP_REG_A2] = source[0];
7624: dsp_core.registers[DSP_REG_A1] = source[1];
7625: dsp_core.registers[DSP_REG_A0] = source[2];
7626:
7627: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7628: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7629: }
7630:
7631: static void dsp_mpyr_p_x0_x0_b(void)
7632: {
7633: Uint32 source[3];
7634:
7635: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7636: dsp_rnd56(source);
7637:
7638: dsp_core.registers[DSP_REG_B2] = source[0];
7639: dsp_core.registers[DSP_REG_B1] = source[1];
7640: dsp_core.registers[DSP_REG_B0] = source[2];
7641:
7642: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7643: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7644: }
7645:
7646: static void dsp_mpyr_m_x0_x0_b(void)
7647: {
7648: Uint32 source[3];
7649:
7650:
7651: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7652: dsp_rnd56(source);
7653:
7654: dsp_core.registers[DSP_REG_B2] = source[0];
7655: dsp_core.registers[DSP_REG_B1] = source[1];
7656: dsp_core.registers[DSP_REG_B0] = source[2];
7657:
7658: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7659: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7660: }
7661:
7662: static void dsp_mpyr_p_y0_y0_a(void)
7663: {
7664: Uint32 source[3];
7665:
7666: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7667: dsp_rnd56(source);
7668:
7669: dsp_core.registers[DSP_REG_A2] = source[0];
7670: dsp_core.registers[DSP_REG_A1] = source[1];
7671: dsp_core.registers[DSP_REG_A0] = source[2];
7672:
7673: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7674: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7675: }
7676:
7677: static void dsp_mpyr_m_y0_y0_a(void)
7678: {
7679: Uint32 source[3];
7680:
7681: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7682: dsp_rnd56(source);
7683:
7684: dsp_core.registers[DSP_REG_A2] = source[0];
7685: dsp_core.registers[DSP_REG_A1] = source[1];
7686: dsp_core.registers[DSP_REG_A0] = source[2];
7687:
7688: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7689: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7690: }
7691:
7692: static void dsp_mpyr_p_y0_y0_b(void)
7693: {
7694: Uint32 source[3];
7695:
7696: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7697: dsp_rnd56(source);
7698:
7699: dsp_core.registers[DSP_REG_B2] = source[0];
7700: dsp_core.registers[DSP_REG_B1] = source[1];
7701: dsp_core.registers[DSP_REG_B0] = source[2];
7702:
7703: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7704: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7705: }
7706:
7707: static void dsp_mpyr_m_y0_y0_b(void)
7708: {
7709: Uint32 source[3];
7710:
7711: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7712: dsp_rnd56(source);
7713:
7714: dsp_core.registers[DSP_REG_B2] = source[0];
7715: dsp_core.registers[DSP_REG_B1] = source[1];
7716: dsp_core.registers[DSP_REG_B0] = source[2];
7717:
7718: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7719: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7720: }
7721:
7722: static void dsp_mpyr_p_x1_x0_a(void)
7723: {
7724: Uint32 source[3];
7725:
7726: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7727: dsp_rnd56(source);
7728:
7729: dsp_core.registers[DSP_REG_A2] = source[0];
7730: dsp_core.registers[DSP_REG_A1] = source[1];
7731: dsp_core.registers[DSP_REG_A0] = source[2];
7732:
7733: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7734: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7735: }
7736:
7737: static void dsp_mpyr_m_x1_x0_a(void)
7738: {
7739: Uint32 source[3];
7740:
7741: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7742: dsp_rnd56(source);
7743:
7744: dsp_core.registers[DSP_REG_A2] = source[0];
7745: dsp_core.registers[DSP_REG_A1] = source[1];
7746: dsp_core.registers[DSP_REG_A0] = source[2];
7747:
7748: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7749: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7750: }
7751:
7752: static void dsp_mpyr_p_x1_x0_b(void)
7753: {
7754: Uint32 source[3];
7755:
7756: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7757: dsp_rnd56(source);
7758:
7759: dsp_core.registers[DSP_REG_B2] = source[0];
7760: dsp_core.registers[DSP_REG_B1] = source[1];
7761: dsp_core.registers[DSP_REG_B0] = source[2];
7762:
7763: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7764: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7765: }
7766:
7767: static void dsp_mpyr_m_x1_x0_b(void)
7768: {
7769: Uint32 source[3];
7770:
7771: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7772: dsp_rnd56(source);
7773:
7774: dsp_core.registers[DSP_REG_B2] = source[0];
7775: dsp_core.registers[DSP_REG_B1] = source[1];
7776: dsp_core.registers[DSP_REG_B0] = source[2];
7777:
7778: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7779: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7780: }
7781:
7782: static void dsp_mpyr_p_y1_y0_a(void)
7783: {
7784: Uint32 source[3];
7785:
7786: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7787: dsp_rnd56(source);
7788:
7789: dsp_core.registers[DSP_REG_A2] = source[0];
7790: dsp_core.registers[DSP_REG_A1] = source[1];
7791: dsp_core.registers[DSP_REG_A0] = source[2];
7792:
7793: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7794: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7795: }
7796:
7797: static void dsp_mpyr_m_y1_y0_a(void)
7798: {
7799: Uint32 source[3];
7800:
7801: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7802: dsp_rnd56(source);
7803:
7804: dsp_core.registers[DSP_REG_A2] = source[0];
7805: dsp_core.registers[DSP_REG_A1] = source[1];
7806: dsp_core.registers[DSP_REG_A0] = source[2];
7807:
7808: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7809: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7810: }
7811:
7812: static void dsp_mpyr_p_y1_y0_b(void)
7813: {
7814: Uint32 source[3];
7815:
7816: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7817: dsp_rnd56(source);
7818:
7819: dsp_core.registers[DSP_REG_B2] = source[0];
7820: dsp_core.registers[DSP_REG_B1] = source[1];
7821: dsp_core.registers[DSP_REG_B0] = source[2];
7822:
7823: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7824: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7825: }
7826:
7827: static void dsp_mpyr_m_y1_y0_b(void)
7828: {
7829: Uint32 source[3];
7830:
7831: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7832: dsp_rnd56(source);
7833:
7834: dsp_core.registers[DSP_REG_B2] = source[0];
7835: dsp_core.registers[DSP_REG_B1] = source[1];
7836: dsp_core.registers[DSP_REG_B0] = source[2];
7837:
7838: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7839: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7840: }
7841:
7842: static void dsp_mpyr_p_x0_y1_a(void)
7843: {
7844: Uint32 source[3];
7845:
7846: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7847: dsp_rnd56(source);
7848:
7849: dsp_core.registers[DSP_REG_A2] = source[0];
7850: dsp_core.registers[DSP_REG_A1] = source[1];
7851: dsp_core.registers[DSP_REG_A0] = source[2];
7852:
7853: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7854: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7855: }
7856:
7857: static void dsp_mpyr_m_x0_y1_a(void)
7858: {
7859: Uint32 source[3];
7860:
7861: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7862: dsp_rnd56(source);
7863:
7864: dsp_core.registers[DSP_REG_A2] = source[0];
7865: dsp_core.registers[DSP_REG_A1] = source[1];
7866: dsp_core.registers[DSP_REG_A0] = source[2];
7867:
7868: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7869: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7870: }
7871:
7872: static void dsp_mpyr_p_x0_y1_b(void)
7873: {
7874: Uint32 source[3];
7875:
7876: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7877: dsp_rnd56(source);
7878:
7879: dsp_core.registers[DSP_REG_B2] = source[0];
7880: dsp_core.registers[DSP_REG_B1] = source[1];
7881: dsp_core.registers[DSP_REG_B0] = source[2];
7882:
7883: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7884: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7885: }
7886:
7887: static void dsp_mpyr_m_x0_y1_b(void)
7888: {
7889: Uint32 source[3];
7890:
7891: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7892: dsp_rnd56(source);
7893:
7894: dsp_core.registers[DSP_REG_B2] = source[0];
7895: dsp_core.registers[DSP_REG_B1] = source[1];
7896: dsp_core.registers[DSP_REG_B0] = source[2];
7897:
7898: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7899: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7900: }
7901:
7902: static void dsp_mpyr_p_y0_x0_a(void)
7903: {
7904: Uint32 source[3];
7905:
7906: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7907: dsp_rnd56(source);
7908:
7909: dsp_core.registers[DSP_REG_A2] = source[0];
7910: dsp_core.registers[DSP_REG_A1] = source[1];
7911: dsp_core.registers[DSP_REG_A0] = source[2];
7912:
7913: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7914: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7915: }
7916:
7917: static void dsp_mpyr_m_y0_x0_a(void)
7918: {
7919: Uint32 source[3];
7920:
7921: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7922: dsp_rnd56(source);
7923:
7924: dsp_core.registers[DSP_REG_A2] = source[0];
7925: dsp_core.registers[DSP_REG_A1] = source[1];
7926: dsp_core.registers[DSP_REG_A0] = source[2];
7927:
7928: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7929: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7930: }
7931:
7932: static void dsp_mpyr_p_y0_x0_b(void)
7933: {
7934: Uint32 source[3];
7935:
7936: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7937: dsp_rnd56(source);
7938:
7939: dsp_core.registers[DSP_REG_B2] = source[0];
7940: dsp_core.registers[DSP_REG_B1] = source[1];
7941: dsp_core.registers[DSP_REG_B0] = source[2];
7942:
7943: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7944: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7945: }
7946:
7947: static void dsp_mpyr_m_y0_x0_b(void)
7948: {
7949: Uint32 source[3];
7950:
7951: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7952: dsp_rnd56(source);
7953:
7954: dsp_core.registers[DSP_REG_B2] = source[0];
7955: dsp_core.registers[DSP_REG_B1] = source[1];
7956: dsp_core.registers[DSP_REG_B0] = source[2];
7957:
7958: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7959: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7960: }
7961:
7962: static void dsp_mpyr_p_x1_y0_a(void)
7963: {
7964: Uint32 source[3];
7965:
7966: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7967: dsp_rnd56(source);
7968:
7969: dsp_core.registers[DSP_REG_A2] = source[0];
7970: dsp_core.registers[DSP_REG_A1] = source[1];
7971: dsp_core.registers[DSP_REG_A0] = source[2];
7972:
7973: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7974: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7975: }
7976:
7977: static void dsp_mpyr_m_x1_y0_a(void)
7978: {
7979: Uint32 source[3];
7980:
7981: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7982: dsp_rnd56(source);
7983:
7984: dsp_core.registers[DSP_REG_A2] = source[0];
7985: dsp_core.registers[DSP_REG_A1] = source[1];
7986: dsp_core.registers[DSP_REG_A0] = source[2];
7987:
7988: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7989: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7990: }
7991:
7992: static void dsp_mpyr_p_x1_y0_b(void)
7993: {
7994: Uint32 source[3];
7995:
7996: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7997: dsp_rnd56(source);
7998:
7999: dsp_core.registers[DSP_REG_B2] = source[0];
8000: dsp_core.registers[DSP_REG_B1] = source[1];
8001: dsp_core.registers[DSP_REG_B0] = source[2];
8002:
8003: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8004: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8005: }
8006:
8007: static void dsp_mpyr_m_x1_y0_b(void)
8008: {
8009: Uint32 source[3];
8010:
8011: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
8012: dsp_rnd56(source);
8013:
8014: dsp_core.registers[DSP_REG_B2] = source[0];
8015: dsp_core.registers[DSP_REG_B1] = source[1];
8016: dsp_core.registers[DSP_REG_B0] = source[2];
8017:
8018: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8019: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8020: }
8021:
8022: static void dsp_mpyr_p_y1_x1_a(void)
8023: {
8024: Uint32 source[3];
8025:
8026: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
8027: dsp_rnd56(source);
8028:
8029: dsp_core.registers[DSP_REG_A2] = source[0];
8030: dsp_core.registers[DSP_REG_A1] = source[1];
8031: dsp_core.registers[DSP_REG_A0] = source[2];
8032:
8033: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8034: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8035: }
8036:
8037: static void dsp_mpyr_m_y1_x1_a(void)
8038: {
8039: Uint32 source[3];
8040:
8041: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
8042: dsp_rnd56(source);
8043:
8044: dsp_core.registers[DSP_REG_A2] = source[0];
8045: dsp_core.registers[DSP_REG_A1] = source[1];
8046: dsp_core.registers[DSP_REG_A0] = source[2];
8047:
8048: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8049: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8050: }
8051:
8052: static void dsp_mpyr_p_y1_x1_b(void)
8053: {
8054: Uint32 source[3];
8055:
8056: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
8057: dsp_rnd56(source);
8058:
8059: dsp_core.registers[DSP_REG_B2] = source[0];
8060: dsp_core.registers[DSP_REG_B1] = source[1];
8061: dsp_core.registers[DSP_REG_B0] = source[2];
8062:
8063: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8064: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8065: }
8066:
8067: static void dsp_mpyr_m_y1_x1_b(void)
8068: {
8069: Uint32 source[3];
8070:
8071: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
8072: dsp_rnd56(source);
8073:
8074: dsp_core.registers[DSP_REG_B2] = source[0];
8075: dsp_core.registers[DSP_REG_B1] = source[1];
8076: dsp_core.registers[DSP_REG_B0] = source[2];
8077:
8078: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8079: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8080: }
8081:
8082: static void dsp_neg_a(void)
8083: {
8084: Uint32 source[3], dest[3], overflowed;
8085:
8086: source[0] = dsp_core.registers[DSP_REG_A2];
8087: source[1] = dsp_core.registers[DSP_REG_A1];
8088: source[2] = dsp_core.registers[DSP_REG_A0];
8089:
8090: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8091:
8092: dest[0] = dest[1] = dest[2] = 0;
8093:
8094: dsp_sub56(source, dest);
8095:
8096: dsp_core.registers[DSP_REG_A2] = dest[0];
8097: dsp_core.registers[DSP_REG_A1] = dest[1];
8098: dsp_core.registers[DSP_REG_A0] = dest[2];
8099:
8100: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8101: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8102:
8103: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8104: }
8105:
8106: static void dsp_neg_b(void)
8107: {
8108: Uint32 source[3], dest[3], overflowed;
8109:
8110: source[0] = dsp_core.registers[DSP_REG_B2];
8111: source[1] = dsp_core.registers[DSP_REG_B1];
8112: source[2] = dsp_core.registers[DSP_REG_B0];
8113:
8114: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8115:
8116: dest[0] = dest[1] = dest[2] = 0;
8117:
8118: dsp_sub56(source, dest);
8119:
8120: dsp_core.registers[DSP_REG_B2] = dest[0];
8121: dsp_core.registers[DSP_REG_B1] = dest[1];
8122: dsp_core.registers[DSP_REG_B0] = dest[2];
8123:
8124: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8125: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8126:
8127: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8128: }
8129:
8130: static void dsp_nop(void)
8131: {
8132: }
8133:
8134: static void dsp_not_a(void)
8135: {
8136: dsp_core.registers[DSP_REG_A1] = ~dsp_core.registers[DSP_REG_A1];
8137: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8138:
8139: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8140: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8141: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8142: }
8143:
8144: static void dsp_not_b(void)
8145: {
8146: dsp_core.registers[DSP_REG_B1] = ~dsp_core.registers[DSP_REG_B1];
8147: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8148:
8149: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8150: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8151: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8152: }
8153:
8154: static void dsp_or_x0_a(void)
8155: {
8156: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X0];
8157: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8158:
8159: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8160: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8161: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8162: }
8163:
8164: static void dsp_or_x0_b(void)
8165: {
8166: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X0];
8167: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8168:
8169: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8170: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8171: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8172: }
8173:
8174: static void dsp_or_y0_a(void)
8175: {
8176: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y0];
8177: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8178:
8179: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8180: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8181: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8182: }
8183:
8184: static void dsp_or_y0_b(void)
8185: {
8186: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y0];
8187: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8188:
8189: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8190: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8191: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8192: }
8193:
8194: static void dsp_or_x1_a(void)
8195: {
8196: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X1];
8197: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8198:
8199: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8200: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8201: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8202: }
8203:
8204: static void dsp_or_x1_b(void)
8205: {
8206: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X1];
8207: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8208:
8209: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8210: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8211: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8212: }
8213:
8214: static void dsp_or_y1_a(void)
8215: {
8216: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y1];
8217: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8218:
8219: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8220: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8221: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8222: }
8223:
8224: static void dsp_or_y1_b(void)
8225: {
8226: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y1];
8227: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8228:
8229: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8230: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8231: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8232: }
8233:
8234: static void dsp_rnd_a(void)
8235: {
8236: Uint32 dest[3];
8237:
8238: dest[0] = dsp_core.registers[DSP_REG_A2];
8239: dest[1] = dsp_core.registers[DSP_REG_A1];
8240: dest[2] = dsp_core.registers[DSP_REG_A0];
8241:
8242: dsp_rnd56(dest);
8243:
8244: dsp_core.registers[DSP_REG_A2] = dest[0];
8245: dsp_core.registers[DSP_REG_A1] = dest[1];
8246: dsp_core.registers[DSP_REG_A0] = dest[2];
8247:
8248: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8249: }
8250:
8251: static void dsp_rnd_b(void)
8252: {
8253: Uint32 dest[3];
8254:
8255: dest[0] = dsp_core.registers[DSP_REG_B2];
8256: dest[1] = dsp_core.registers[DSP_REG_B1];
8257: dest[2] = dsp_core.registers[DSP_REG_B0];
8258:
8259: dsp_rnd56(dest);
8260:
8261: dsp_core.registers[DSP_REG_B2] = dest[0];
8262: dsp_core.registers[DSP_REG_B1] = dest[1];
8263: dsp_core.registers[DSP_REG_B0] = dest[2];
8264:
8265: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8266: }
8267:
8268: static void dsp_rol_a(void)
8269: {
8270: Uint32 newcarry;
8271:
8272: newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
8273:
8274: dsp_core.registers[DSP_REG_A1] <<= 1;
8275: dsp_core.registers[DSP_REG_A1] |= newcarry;
8276: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
8277:
8278: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8279: dsp_core.registers[DSP_REG_SR] |= newcarry;
8280: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8281: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8282: }
8283:
8284: static void dsp_rol_b(void)
8285: {
8286: Uint32 newcarry;
8287:
8288: newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
8289:
8290: dsp_core.registers[DSP_REG_B1] <<= 1;
8291: dsp_core.registers[DSP_REG_B1] |= newcarry;
8292: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
8293:
8294: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8295: dsp_core.registers[DSP_REG_SR] |= newcarry;
8296: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8297: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8298: }
8299:
8300: static void dsp_ror_a(void)
8301: {
8302: Uint32 newcarry;
8303:
8304: newcarry = dsp_core.registers[DSP_REG_A1] & 1;
8305:
8306: dsp_core.registers[DSP_REG_A1] >>= 1;
8307: dsp_core.registers[DSP_REG_A1] |= newcarry<<23;
8308:
8309: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8310: dsp_core.registers[DSP_REG_SR] |= newcarry;
8311: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8312: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8313: }
8314:
8315: static void dsp_ror_b(void)
8316: {
8317: Uint32 newcarry;
8318:
8319: newcarry = dsp_core.registers[DSP_REG_B1] & 1;
8320:
8321: dsp_core.registers[DSP_REG_B1] >>= 1;
8322: dsp_core.registers[DSP_REG_B1] |= newcarry<<23;
8323:
8324: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8325: dsp_core.registers[DSP_REG_SR] |= newcarry;
8326: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8327: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8328: }
8329:
8330: static void dsp_sbc_x_a(void)
8331: {
8332: Uint32 source[3], dest[3], curcarry;
8333: Uint16 newsr;
8334:
8335: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8336:
8337: dest[2] = dsp_core.registers[DSP_REG_A0];
8338: dest[1] = dsp_core.registers[DSP_REG_A1];
8339: dest[0] = dsp_core.registers[DSP_REG_A2];
8340:
8341: source[2] = dsp_core.registers[DSP_REG_X0];
8342: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8343: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8344:
8345: newsr = dsp_sub56(source, dest);
1.1.1.11 root 8346:
1.1.1.6 root 8347: if (curcarry) {
8348: source[0]=0; source[1]=0; source[2]=1;
8349: newsr |= dsp_sub56(source, dest);
8350: }
8351:
8352: dsp_core.registers[DSP_REG_A2] = dest[0];
8353: dsp_core.registers[DSP_REG_A1] = dest[1];
8354: dsp_core.registers[DSP_REG_A0] = dest[2];
8355:
8356: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8357:
8358: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8359: dsp_core.registers[DSP_REG_SR] |= newsr;
8360: }
8361:
8362: static void dsp_sbc_x_b(void)
8363: {
8364: Uint32 source[3], dest[3], curcarry;
8365: Uint16 newsr;
8366:
8367: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8368:
8369: dest[2] = dsp_core.registers[DSP_REG_B0];
8370: dest[1] = dsp_core.registers[DSP_REG_B1];
8371: dest[0] = dsp_core.registers[DSP_REG_B2];
8372:
8373: source[2] = dsp_core.registers[DSP_REG_X0];
8374: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8375: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8376:
8377: newsr = dsp_sub56(source, dest);
1.1.1.11 root 8378:
1.1.1.6 root 8379: if (curcarry) {
8380: source[0]=0; source[1]=0; source[2]=1;
8381: newsr |= dsp_sub56(source, dest);
8382: }
8383:
8384: dsp_core.registers[DSP_REG_B2] = dest[0];
8385: dsp_core.registers[DSP_REG_B1] = dest[1];
8386: dsp_core.registers[DSP_REG_B0] = dest[2];
8387:
8388: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8389:
8390: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8391: dsp_core.registers[DSP_REG_SR] |= newsr;
8392: }
8393:
8394: static void dsp_sbc_y_a(void)
8395: {
8396: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 8397: Uint16 newsr;
1.1 root 8398:
1.1.1.6 root 8399: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8400:
8401: dest[2] = dsp_core.registers[DSP_REG_A0];
8402: dest[1] = dsp_core.registers[DSP_REG_A1];
8403: dest[0] = dsp_core.registers[DSP_REG_A2];
8404:
8405: source[2] = dsp_core.registers[DSP_REG_Y0];
8406: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8407: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8408:
8409: newsr = dsp_sub56(source, dest);
1.1.1.11 root 8410:
1.1.1.6 root 8411: if (curcarry) {
8412: source[0]=0; source[1]=0; source[2]=1;
8413: newsr |= dsp_sub56(source, dest);
8414: }
8415:
8416: dsp_core.registers[DSP_REG_A2] = dest[0];
8417: dsp_core.registers[DSP_REG_A1] = dest[1];
8418: dsp_core.registers[DSP_REG_A0] = dest[2];
8419:
8420: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8421:
8422: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8423: dsp_core.registers[DSP_REG_SR] |= newsr;
8424: }
8425:
8426: static void dsp_sbc_y_b(void)
8427: {
8428: Uint32 source[3], dest[3], curcarry;
8429: Uint16 newsr;
8430:
8431: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8432:
8433: dest[2] = dsp_core.registers[DSP_REG_B0];
8434: dest[1] = dsp_core.registers[DSP_REG_B1];
8435: dest[0] = dsp_core.registers[DSP_REG_B2];
8436:
8437: source[2] = dsp_core.registers[DSP_REG_Y0];
8438: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8439: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8440:
8441: newsr = dsp_sub56(source, dest);
1.1.1.11 root 8442:
1.1.1.6 root 8443: if (curcarry) {
8444: source[0]=0; source[1]=0; source[2]=1;
8445: newsr |= dsp_sub56(source, dest);
1.1 root 8446: }
8447:
1.1.1.6 root 8448: dsp_core.registers[DSP_REG_B2] = dest[0];
8449: dsp_core.registers[DSP_REG_B1] = dest[1];
8450: dsp_core.registers[DSP_REG_B0] = dest[2];
8451:
8452: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8453:
8454: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8455: dsp_core.registers[DSP_REG_SR] |= newsr;
8456: }
8457:
8458: static void dsp_sub_b_a(void)
8459: {
8460: Uint32 source[3], dest[3];
8461: Uint16 newsr;
8462:
8463: dest[2] = dsp_core.registers[DSP_REG_A0];
8464: dest[1] = dsp_core.registers[DSP_REG_A1];
8465: dest[0] = dsp_core.registers[DSP_REG_A2];
8466:
8467: source[2] = dsp_core.registers[DSP_REG_B0];
8468: source[1] = dsp_core.registers[DSP_REG_B1];
8469: source[0] = dsp_core.registers[DSP_REG_B2];
8470:
1.1 root 8471: newsr = dsp_sub56(source, dest);
8472:
1.1.1.6 root 8473: dsp_core.registers[DSP_REG_A2] = dest[0];
8474: dsp_core.registers[DSP_REG_A1] = dest[1];
8475: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8476:
1.1.1.6 root 8477: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8478:
1.1.1.6 root 8479: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8480: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8481: }
8482:
1.1.1.6 root 8483: static void dsp_sub_a_b(void)
1.1 root 8484: {
1.1.1.6 root 8485: Uint32 source[3], dest[3];
1.1.1.2 root 8486: Uint16 newsr;
1.1 root 8487:
1.1.1.6 root 8488: dest[2] = dsp_core.registers[DSP_REG_B0];
8489: dest[1] = dsp_core.registers[DSP_REG_B1];
8490: dest[0] = dsp_core.registers[DSP_REG_B2];
8491:
8492: source[2] = dsp_core.registers[DSP_REG_A0];
8493: source[1] = dsp_core.registers[DSP_REG_A1];
8494: source[0] = dsp_core.registers[DSP_REG_A2];
8495:
8496: newsr = dsp_sub56(source, dest);
8497:
8498: dsp_core.registers[DSP_REG_B2] = dest[0];
8499: dsp_core.registers[DSP_REG_B1] = dest[1];
8500: dsp_core.registers[DSP_REG_B0] = dest[2];
8501:
8502: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8503:
8504: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8505: dsp_core.registers[DSP_REG_SR] |= newsr;
8506: }
8507:
8508: static void dsp_sub_x_a(void)
8509: {
8510: Uint32 source[3], dest[3];
8511: Uint16 newsr;
8512:
8513: dest[2] = dsp_core.registers[DSP_REG_A0];
8514: dest[1] = dsp_core.registers[DSP_REG_A1];
8515: dest[0] = dsp_core.registers[DSP_REG_A2];
8516:
8517: source[2] = dsp_core.registers[DSP_REG_X0];
8518: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8519: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8520:
8521: newsr = dsp_sub56(source, dest);
8522:
8523: dsp_core.registers[DSP_REG_A2] = dest[0];
8524: dsp_core.registers[DSP_REG_A1] = dest[1];
8525: dsp_core.registers[DSP_REG_A0] = dest[2];
8526:
8527: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8528:
8529: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8530: dsp_core.registers[DSP_REG_SR] |= newsr;
8531: }
8532:
8533: static void dsp_sub_x_b(void)
8534: {
8535: Uint32 source[3], dest[3];
8536: Uint16 newsr;
8537:
8538: dest[2] = dsp_core.registers[DSP_REG_B0];
8539: dest[1] = dsp_core.registers[DSP_REG_B1];
8540: dest[0] = dsp_core.registers[DSP_REG_B2];
8541:
8542: source[2] = dsp_core.registers[DSP_REG_X0];
8543: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8544: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8545:
8546: newsr = dsp_sub56(source, dest);
8547:
8548: dsp_core.registers[DSP_REG_B2] = dest[0];
8549: dsp_core.registers[DSP_REG_B1] = dest[1];
8550: dsp_core.registers[DSP_REG_B0] = dest[2];
8551:
8552: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8553:
8554: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8555: dsp_core.registers[DSP_REG_SR] |= newsr;
8556: }
8557:
8558: static void dsp_sub_y_a(void)
8559: {
8560: Uint32 source[3], dest[3];
8561: Uint16 newsr;
8562:
8563: dest[2] = dsp_core.registers[DSP_REG_A0];
8564: dest[1] = dsp_core.registers[DSP_REG_A1];
8565: dest[0] = dsp_core.registers[DSP_REG_A2];
8566:
8567: source[2] = dsp_core.registers[DSP_REG_Y0];
8568: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8569: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8570:
8571: newsr = dsp_sub56(source, dest);
8572:
8573: dsp_core.registers[DSP_REG_A2] = dest[0];
8574: dsp_core.registers[DSP_REG_A1] = dest[1];
8575: dsp_core.registers[DSP_REG_A0] = dest[2];
8576:
8577: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8578:
8579: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8580: dsp_core.registers[DSP_REG_SR] |= newsr;
8581: }
8582:
8583: static void dsp_sub_y_b(void)
8584: {
8585: Uint32 source[3], dest[3];
8586: Uint16 newsr;
8587:
8588: dest[2] = dsp_core.registers[DSP_REG_B0];
8589: dest[1] = dsp_core.registers[DSP_REG_B1];
8590: dest[0] = dsp_core.registers[DSP_REG_B2];
8591:
8592: source[2] = dsp_core.registers[DSP_REG_Y0];
8593: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8594: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8595:
8596: newsr = dsp_sub56(source, dest);
8597:
8598: dsp_core.registers[DSP_REG_B2] = dest[0];
8599: dsp_core.registers[DSP_REG_B1] = dest[1];
8600: dsp_core.registers[DSP_REG_B0] = dest[2];
8601:
8602: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8603:
8604: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8605: dsp_core.registers[DSP_REG_SR] |= newsr;
8606: }
8607:
8608: static void dsp_sub_x0_a(void)
8609: {
8610: Uint32 source[3], dest[3];
8611: Uint16 newsr;
8612:
8613: dest[2] = dsp_core.registers[DSP_REG_A0];
8614: dest[1] = dsp_core.registers[DSP_REG_A1];
8615: dest[0] = dsp_core.registers[DSP_REG_A2];
8616:
8617: source[2] = 0;
8618: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 8619: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8620:
8621: newsr = dsp_sub56(source, dest);
8622:
8623: dsp_core.registers[DSP_REG_A2] = dest[0];
8624: dsp_core.registers[DSP_REG_A1] = dest[1];
8625: dsp_core.registers[DSP_REG_A0] = dest[2];
8626:
8627: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8628:
8629: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8630: dsp_core.registers[DSP_REG_SR] |= newsr;
8631: }
8632:
8633: static void dsp_sub_x0_b(void)
8634: {
8635: Uint32 source[3], dest[3];
8636: Uint16 newsr;
8637:
8638: dest[2] = dsp_core.registers[DSP_REG_B0];
8639: dest[1] = dsp_core.registers[DSP_REG_B1];
8640: dest[0] = dsp_core.registers[DSP_REG_B2];
8641:
8642: source[2] = 0;
8643: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 8644: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8645:
8646: newsr = dsp_sub56(source, dest);
8647:
8648: dsp_core.registers[DSP_REG_B2] = dest[0];
8649: dsp_core.registers[DSP_REG_B1] = dest[1];
8650: dsp_core.registers[DSP_REG_B0] = dest[2];
8651:
8652: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8653:
8654: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8655: dsp_core.registers[DSP_REG_SR] |= newsr;
8656: }
8657:
8658: static void dsp_sub_y0_a(void)
8659: {
8660: Uint32 source[3], dest[3];
8661: Uint16 newsr;
8662:
8663: dest[2] = dsp_core.registers[DSP_REG_A0];
8664: dest[1] = dsp_core.registers[DSP_REG_A1];
8665: dest[0] = dsp_core.registers[DSP_REG_A2];
8666:
8667: source[2] = 0;
8668: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 8669: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8670:
8671: newsr = dsp_sub56(source, dest);
1.1 root 8672:
1.1.1.6 root 8673: dsp_core.registers[DSP_REG_A2] = dest[0];
8674: dsp_core.registers[DSP_REG_A1] = dest[1];
8675: dsp_core.registers[DSP_REG_A0] = dest[2];
8676:
8677: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8678:
8679: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8680: dsp_core.registers[DSP_REG_SR] |= newsr;
8681: }
8682:
8683: static void dsp_sub_y0_b(void)
8684: {
8685: Uint32 source[3], dest[3];
8686: Uint16 newsr;
8687:
8688: dest[2] = dsp_core.registers[DSP_REG_B0];
8689: dest[1] = dsp_core.registers[DSP_REG_B1];
8690: dest[0] = dsp_core.registers[DSP_REG_B2];
8691:
8692: source[2] = 0;
8693: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 8694: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8695:
8696: newsr = dsp_sub56(source, dest);
8697:
8698: dsp_core.registers[DSP_REG_B2] = dest[0];
8699: dsp_core.registers[DSP_REG_B1] = dest[1];
8700: dsp_core.registers[DSP_REG_B0] = dest[2];
8701:
8702: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8703:
8704: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8705: dsp_core.registers[DSP_REG_SR] |= newsr;
8706: }
8707:
8708: static void dsp_sub_x1_a(void)
8709: {
8710: Uint32 source[3], dest[3];
8711: Uint16 newsr;
8712:
8713: dest[2] = dsp_core.registers[DSP_REG_A0];
8714: dest[1] = dsp_core.registers[DSP_REG_A1];
8715: dest[0] = dsp_core.registers[DSP_REG_A2];
8716:
8717: source[2] = 0;
8718: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8719: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8720:
8721: newsr = dsp_sub56(source, dest);
8722:
8723: dsp_core.registers[DSP_REG_A2] = dest[0];
8724: dsp_core.registers[DSP_REG_A1] = dest[1];
8725: dsp_core.registers[DSP_REG_A0] = dest[2];
8726:
8727: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8728:
8729: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8730: dsp_core.registers[DSP_REG_SR] |= newsr;
8731: }
8732:
8733: static void dsp_sub_x1_b(void)
8734: {
8735: Uint32 source[3], dest[3];
8736: Uint16 newsr;
8737:
8738: dest[2] = dsp_core.registers[DSP_REG_B0];
8739: dest[1] = dsp_core.registers[DSP_REG_B1];
8740: dest[0] = dsp_core.registers[DSP_REG_B2];
8741:
8742: source[2] = 0;
8743: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8744: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8745:
8746: newsr = dsp_sub56(source, dest);
8747:
8748: dsp_core.registers[DSP_REG_B2] = dest[0];
8749: dsp_core.registers[DSP_REG_B1] = dest[1];
8750: dsp_core.registers[DSP_REG_B0] = dest[2];
8751:
8752: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8753:
8754: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8755: dsp_core.registers[DSP_REG_SR] |= newsr;
8756: }
8757:
8758: static void dsp_sub_y1_a(void)
8759: {
8760: Uint32 source[3], dest[3];
8761: Uint16 newsr;
8762:
8763: dest[2] = dsp_core.registers[DSP_REG_A0];
8764: dest[1] = dsp_core.registers[DSP_REG_A1];
8765: dest[0] = dsp_core.registers[DSP_REG_A2];
8766:
8767: source[2] = 0;
8768: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8769: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8770:
8771: newsr = dsp_sub56(source, dest);
8772:
8773: dsp_core.registers[DSP_REG_A2] = dest[0];
8774: dsp_core.registers[DSP_REG_A1] = dest[1];
8775: dsp_core.registers[DSP_REG_A0] = dest[2];
8776:
8777: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8778:
8779: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8780: dsp_core.registers[DSP_REG_SR] |= newsr;
8781: }
8782:
8783: static void dsp_sub_y1_b(void)
8784: {
8785: Uint32 source[3], dest[3];
8786: Uint16 newsr;
8787:
8788: dest[2] = dsp_core.registers[DSP_REG_B0];
8789: dest[1] = dsp_core.registers[DSP_REG_B1];
8790: dest[0] = dsp_core.registers[DSP_REG_B2];
8791:
8792: source[2] = 0;
8793: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8794: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8795:
8796: newsr = dsp_sub56(source, dest);
8797:
8798: dsp_core.registers[DSP_REG_B2] = dest[0];
8799: dsp_core.registers[DSP_REG_B1] = dest[1];
8800: dsp_core.registers[DSP_REG_B0] = dest[2];
8801:
8802: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8803:
8804: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8805: dsp_core.registers[DSP_REG_SR] |= newsr;
8806: }
8807:
8808: static void dsp_subl_a(void)
8809: {
8810: Uint32 source[3], dest[3];
8811: Uint16 newsr;
8812:
8813: dest[0] = dsp_core.registers[DSP_REG_A2];
8814: dest[1] = dsp_core.registers[DSP_REG_A1];
8815: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 8816: newsr = dsp_asl56(dest);
8817:
1.1.1.6 root 8818: source[0] = dsp_core.registers[DSP_REG_B2];
8819: source[1] = dsp_core.registers[DSP_REG_B1];
8820: source[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 8821: newsr |= dsp_sub56(source, dest);
8822:
1.1.1.6 root 8823: dsp_core.registers[DSP_REG_A2] = dest[0];
8824: dsp_core.registers[DSP_REG_A1] = dest[1];
8825: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8826:
1.1.1.6 root 8827: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8828:
1.1.1.6 root 8829: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8830: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8831: }
8832:
1.1.1.6 root 8833: static void dsp_subl_b(void)
1.1 root 8834: {
1.1.1.6 root 8835: Uint32 source[3], dest[3];
1.1.1.2 root 8836: Uint16 newsr;
1.1 root 8837:
1.1.1.6 root 8838: dest[0] = dsp_core.registers[DSP_REG_B2];
8839: dest[1] = dsp_core.registers[DSP_REG_B1];
8840: dest[2] = dsp_core.registers[DSP_REG_B0];
8841: newsr = dsp_asl56(dest);
1.1 root 8842:
1.1.1.6 root 8843: source[0] = dsp_core.registers[DSP_REG_A2];
8844: source[1] = dsp_core.registers[DSP_REG_A1];
8845: source[2] = dsp_core.registers[DSP_REG_A0];
8846: newsr |= dsp_sub56(source, dest);
8847:
8848: dsp_core.registers[DSP_REG_B2] = dest[0];
8849: dsp_core.registers[DSP_REG_B1] = dest[1];
8850: dsp_core.registers[DSP_REG_B0] = dest[2];
8851:
8852: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8853:
8854: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8855: dsp_core.registers[DSP_REG_SR] |= newsr;
8856: }
8857:
8858: static void dsp_subr_a(void)
8859: {
8860: Uint32 source[3], dest[3];
8861: Uint16 newsr;
8862:
8863: dest[0] = dsp_core.registers[DSP_REG_A2];
8864: dest[1] = dsp_core.registers[DSP_REG_A1];
8865: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1.1.11 root 8866:
1.1 root 8867: newsr = dsp_asr56(dest);
8868:
1.1.1.6 root 8869: source[0] = dsp_core.registers[DSP_REG_B2];
8870: source[1] = dsp_core.registers[DSP_REG_B1];
8871: source[2] = dsp_core.registers[DSP_REG_B0];
1.1.1.11 root 8872:
1.1 root 8873: newsr |= dsp_sub56(source, dest);
8874:
1.1.1.6 root 8875: dsp_core.registers[DSP_REG_A2] = dest[0];
8876: dsp_core.registers[DSP_REG_A1] = dest[1];
8877: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8878:
1.1.1.6 root 8879: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8880:
1.1.1.6 root 8881: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8882: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8883: }
8884:
1.1.1.6 root 8885: static void dsp_subr_b(void)
1.1 root 8886: {
1.1.1.6 root 8887: Uint32 source[3], dest[3];
8888: Uint16 newsr;
1.1 root 8889:
1.1.1.6 root 8890: dest[0] = dsp_core.registers[DSP_REG_B2];
8891: dest[1] = dsp_core.registers[DSP_REG_B1];
8892: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1.1.11 root 8893:
1.1.1.6 root 8894: newsr = dsp_asr56(dest);
1.1 root 8895:
1.1.1.6 root 8896: source[0] = dsp_core.registers[DSP_REG_A2];
8897: source[1] = dsp_core.registers[DSP_REG_A1];
8898: source[2] = dsp_core.registers[DSP_REG_A0];
1.1.1.11 root 8899:
1.1.1.6 root 8900: newsr |= dsp_sub56(source, dest);
1.1 root 8901:
1.1.1.6 root 8902: dsp_core.registers[DSP_REG_B2] = dest[0];
8903: dsp_core.registers[DSP_REG_B1] = dest[1];
8904: dsp_core.registers[DSP_REG_B0] = dest[2];
8905:
8906: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8907:
8908: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8909: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8910: }
8911:
1.1.1.6 root 8912: static void dsp_tfr_b_a(void)
1.1 root 8913: {
1.1.1.6 root 8914: dsp_core.registers[DSP_REG_A0] = dsp_core.registers[DSP_REG_B0];
8915: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_B1];
8916: dsp_core.registers[DSP_REG_A2] = dsp_core.registers[DSP_REG_B2];
8917: }
1.1 root 8918:
1.1.1.6 root 8919: static void dsp_tfr_a_b(void)
8920: {
8921: dsp_core.registers[DSP_REG_B0] = dsp_core.registers[DSP_REG_A0];
8922: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_A1];
8923: dsp_core.registers[DSP_REG_B2] = dsp_core.registers[DSP_REG_A2];
8924: }
8925:
8926: static void dsp_tfr_x0_a(void)
8927: {
1.1.1.11 root 8928: dsp_write_reg(DSP_REG_A, dsp_core.registers[DSP_REG_X0]);
1.1.1.6 root 8929: }
8930:
8931: static void dsp_tfr_x0_b(void)
8932: {
1.1.1.11 root 8933: dsp_write_reg(DSP_REG_B, dsp_core.registers[DSP_REG_X0]);
1.1.1.6 root 8934: }
8935:
8936: static void dsp_tfr_y0_a(void)
8937: {
1.1.1.11 root 8938: dsp_write_reg(DSP_REG_A, dsp_core.registers[DSP_REG_Y0]);
1.1.1.6 root 8939: }
8940:
8941: static void dsp_tfr_y0_b(void)
8942: {
1.1.1.11 root 8943: dsp_write_reg(DSP_REG_B, dsp_core.registers[DSP_REG_Y0]);
1.1.1.6 root 8944: }
8945:
8946: static void dsp_tfr_x1_a(void)
8947: {
1.1.1.11 root 8948: dsp_write_reg(DSP_REG_A, dsp_core.registers[DSP_REG_X1]);
1.1.1.6 root 8949: }
8950:
8951: static void dsp_tfr_x1_b(void)
8952: {
1.1.1.11 root 8953: dsp_write_reg(DSP_REG_B, dsp_core.registers[DSP_REG_X1]);
1.1.1.6 root 8954: }
8955:
8956: static void dsp_tfr_y1_a(void)
8957: {
1.1.1.11 root 8958: dsp_write_reg(DSP_REG_A, dsp_core.registers[DSP_REG_Y1]);
1.1.1.6 root 8959: }
8960:
8961: static void dsp_tfr_y1_b(void)
8962: {
1.1.1.11 root 8963: dsp_write_reg(DSP_REG_B, dsp_core.registers[DSP_REG_Y1]);
1.1.1.6 root 8964: }
8965:
8966: static void dsp_tst_a(void)
8967: {
8968: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_A2],
1.1.1.7 root 8969: dsp_core.registers[DSP_REG_A1],
8970: dsp_core.registers[DSP_REG_A0]);
1.1.1.6 root 8971:
8972: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8973: }
8974:
8975: static void dsp_tst_b(void)
8976: {
8977: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_B2],
1.1.1.7 root 8978: dsp_core.registers[DSP_REG_B1],
8979: dsp_core.registers[DSP_REG_B0]);
1.1 root 8980:
1.1.1.6 root 8981: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
1.1 root 8982: }
8983:
1.1.1.2 root 8984: /*
8985: vim:ts=4:sw=4:
8986: */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.