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1.1 root 1: /*
1.1.1.2 root 2: DSP M56001 emulation
1.1.1.4 root 3: Instructions interpreter
1.1.1.2 root 4:
5: (C) 2003-2008 ARAnyM developer team
6:
7: This program is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2 of the License, or
10: (at your option) any later version.
11:
12: This program is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
1.1.1.13 root 18: along with this program; if not, write to the Free Software Foundation,
19: 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335 USA
1.1.1.2 root 20: */
21:
1.1.1.7 root 22: /*
23: DSP memory mapping
24: ------------------
1.1.1.11 root 25:
1.1.1.7 root 26: The memory map is configured as follows :
27: Program space P is one contiguous block of 32K dsp Words
1.1.1.11 root 28: X and Y data space are each separate 16K dsp Word blocks.
1.1.1.7 root 29: Both X and Y can be accessed as blocks starting at 0 or 16K.
30: Program space physically overlaps both X and Y data spaces.
31: Y: memory is mapped at address $0 in P memory
1.1.1.11 root 32: X: memory is mapped at address $4000 in P memory
1.1.1.7 root 33:
34: The DSP external RAM is zero waitstate, but there is a penalty for
1.1.1.11 root 35: accessing it twice or more in a single instruction, because there is only
1.1.1.9 root 36: one external data bus. The extra access costs 2 cycles penalty.
37:
1.1.1.7 root 38: The internal buses are all separate (0 waitstate)
39:
40:
41: X: Y: P:
42: $ffff |--------------+--------------+--------------|
43: | Int. I/O | Ext. I/O | |
44: $ffc0 |--------------+--------------+ |
45: | | | |
46: | Reserved | Reserved | Reserved |
47: | | | |
48: | | | |
49: | | | |
50: $8000 |--------------+--------------+--------------|
51: | | | |
52: | 16k Shadow | 16k Shadow | |
53: | | | 32K |
54: $4000 |--------------+--------------| Program |
55: | 16K | 16K | RAM |
56: | External | External | |
57: | RAM | RAM | |
58: $0200 |--------------+--------------+--------------|
59: | Log table or | Sin table or | |
60: | external mem | external mem | Internal |
61: $0100 |--------------+--------------+ program |
62: | Internal X | Internal Y | memory |
63: | memory | memory | |
64: $0000 |--------------+--------------+--------------|
65:
66:
67: Special Note : As the Falcon DSP is a 0 waitstate access memory, I've simplified a little the cycle counting.
68: If this DSP emulator code is used in another project, one should take into account the bus control register (BCR) waitstates.
69: */
70:
1.1.1.2 root 71: #ifdef HAVE_CONFIG_H
72: #include "config.h"
73: #endif
74:
1.1.1.6 root 75: #include <stdbool.h>
76:
1.1.1.10 root 77: #include "main.h"
1.1.1.2 root 78: #include "dsp_core.h"
1.1 root 79: #include "dsp_cpu.h"
80: #include "dsp_disasm.h"
1.1.1.6 root 81: #include "log.h"
1.1.1.9 root 82: #include "debugui.h"
1.1 root 83:
1.1.1.2 root 84: #define DSP_COUNT_IPS 0 /* Count instruction per seconds */
85:
1.1.1.14! root 86: #if DSP_COUNT_IPS
! 87: /* For counting instructions per second */
! 88: #include <SDL_timer.h>
! 89: static Uint32 start_time;
! 90: static Uint32 num_inst;
! 91: #endif
1.1 root 92:
93: /**********************************
94: * Defines
95: **********************************/
96:
1.1.1.6 root 97: #define SIGN_PLUS 0
98: #define SIGN_MINUS 1
1.1.1.4 root 99:
1.1.1.9 root 100: /* Defines some bits values for access to external memory (X, Y, P) */
101: /* These values will set/unset the corresponding bits in the variable access_to_ext_memory */
102: /* to detect how many access to the external memory were done for a single instruction */
103: #define EXT_X_MEMORY 0
104: #define EXT_Y_MEMORY 1
105: #define EXT_P_MEMORY 2
106:
107:
1.1 root 108: /**********************************
109: * Variables
110: **********************************/
111:
112: /* Length of current instruction */
1.1.1.2 root 113: static Uint32 cur_inst_len; /* =0:jump, >0:increment */
1.1 root 114:
115: /* Current instruction */
1.1.1.4 root 116: static Uint32 cur_inst;
1.1 root 117:
1.1.1.7 root 118: /* Counts the number of access to the external memory for one instruction */
1.1.1.9 root 119: static Uint16 access_to_ext_memory;
1.1.1.7 root 120:
1.1.1.6 root 121: /* DSP is in disasm mode ? */
122: /* If yes, stack overflow, underflow and illegal instructions messages are not displayed */
123: static bool isDsp_in_disasm_mode;
1.1 root 124:
1.1.1.7 root 125: static char str_disasm_memory[2][50]; /* Buffer for memory change text in disasm mode */
1.1.1.5 root 126: static Uint16 disasm_memory_ptr; /* Pointer for memory change in disasm mode */
1.1 root 127:
128: /**********************************
129: * Functions
130: **********************************/
131:
132: typedef void (*dsp_emul_t)(void);
133:
134: static void dsp_postexecute_update_pc(void);
135: static void dsp_postexecute_interrupts(void);
136:
1.1.1.5 root 137: static void dsp_setInterruptIPL(Uint32 value);
138:
1.1.1.6 root 139: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2);
1.1.1.2 root 140:
141: static Uint32 read_memory(int space, Uint16 address);
1.1.1.6 root 142: static inline Uint32 read_memory_p(Uint16 address);
1.1.1.2 root 143: static Uint32 read_memory_disasm(int space, Uint16 address);
1.1.1.6 root 144:
145: static inline void write_memory(int space, Uint16 address, Uint32 value);
146: static void write_memory_raw(int space, Uint16 address, Uint32 value);
1.1.1.4 root 147: static void write_memory_disasm(int space, Uint16 address, Uint32 value);
1.1.1.6 root 148:
1.1.1.11 root 149: static void dsp_write_reg(Uint32 numreg, Uint32 value);
1.1 root 150:
1.1.1.4 root 151: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly);
1.1.1.2 root 152: static void dsp_stack_pop(Uint32 *curpc, Uint32 *cursr);
1.1.1.4 root 153: static void dsp_compute_ssh_ssl(void);
1.1 root 154:
155: static void opcode8h_0(void);
156:
1.1.1.2 root 157: static void dsp_update_rn(Uint32 numreg, Sint16 modifier);
158: static void dsp_update_rn_bitreverse(Uint32 numreg);
159: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier);
160: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr);
161: static int dsp_calc_cc(Uint32 cc_code);
1.1 root 162:
163: static void dsp_undefined(void);
164:
165: /* Instructions without parallel moves */
166: static void dsp_andi(void);
1.1.1.4 root 167: static void dsp_bchg_aa(void);
168: static void dsp_bchg_ea(void);
169: static void dsp_bchg_pp(void);
170: static void dsp_bchg_reg(void);
171: static void dsp_bclr_aa(void);
172: static void dsp_bclr_ea(void);
173: static void dsp_bclr_pp(void);
174: static void dsp_bclr_reg(void);
175: static void dsp_bset_aa(void);
176: static void dsp_bset_ea(void);
177: static void dsp_bset_pp(void);
178: static void dsp_bset_reg(void);
179: static void dsp_btst_aa(void);
180: static void dsp_btst_ea(void);
181: static void dsp_btst_pp(void);
182: static void dsp_btst_reg(void);
1.1 root 183: static void dsp_div(void);
184: static void dsp_enddo(void);
185: static void dsp_illegal(void);
1.1.1.4 root 186: static void dsp_jcc_imm(void);
187: static void dsp_jcc_ea(void);
188: static void dsp_jclr_aa(void);
189: static void dsp_jclr_ea(void);
190: static void dsp_jclr_pp(void);
191: static void dsp_jclr_reg(void);
192: static void dsp_jmp_ea(void);
193: static void dsp_jmp_imm(void);
194: static void dsp_jscc_ea(void);
195: static void dsp_jscc_imm(void);
196: static void dsp_jsclr_aa(void);
197: static void dsp_jsclr_ea(void);
198: static void dsp_jsclr_pp(void);
199: static void dsp_jsclr_reg(void);
200: static void dsp_jset_aa(void);
201: static void dsp_jset_ea(void);
202: static void dsp_jset_pp(void);
203: static void dsp_jset_reg(void);
204: static void dsp_jsr_ea(void);
205: static void dsp_jsr_imm(void);
206: static void dsp_jsset_aa(void);
207: static void dsp_jsset_ea(void);
208: static void dsp_jsset_pp(void);
209: static void dsp_jsset_reg(void);
1.1 root 210: static void dsp_lua(void);
1.1.1.4 root 211: static void dsp_movem_ea(void);
212: static void dsp_movem_aa(void);
1.1 root 213: static void dsp_nop(void);
214: static void dsp_norm(void);
215: static void dsp_ori(void);
216: static void dsp_reset(void);
217: static void dsp_rti(void);
218: static void dsp_rts(void);
219: static void dsp_stop(void);
220: static void dsp_swi(void);
221: static void dsp_tcc(void);
222: static void dsp_wait(void);
223:
1.1.1.3 root 224: static void dsp_do_ea(void);
225: static void dsp_do_aa(void);
226: static void dsp_do_imm(void);
227: static void dsp_do_reg(void);
228: static void dsp_rep_aa(void);
229: static void dsp_rep_ea(void);
230: static void dsp_rep_imm(void);
231: static void dsp_rep_reg(void);
232: static void dsp_movec_aa(void);
233: static void dsp_movec_ea(void);
234: static void dsp_movec_imm(void);
235: static void dsp_movec_reg(void);
1.1 root 236: static void dsp_movep_0(void);
237: static void dsp_movep_1(void);
1.1.1.4 root 238: static void dsp_movep_23(void);
1.1 root 239:
240: /* Parallel move analyzer */
1.1.1.2 root 241: static int dsp_pm_read_accu24(int numreg, Uint32 *dest);
1.1 root 242: static void dsp_pm_0(void);
243: static void dsp_pm_1(void);
244: static void dsp_pm_2(void);
245: static void dsp_pm_2_2(void);
246: static void dsp_pm_3(void);
247: static void dsp_pm_4(void);
1.1.1.4 root 248: static void dsp_pm_4x(void);
1.1 root 249: static void dsp_pm_5(void);
250: static void dsp_pm_8(void);
251:
252: /* 56bits arithmetic */
1.1.1.2 root 253: static Uint16 dsp_abs56(Uint32 *dest);
254: static Uint16 dsp_asl56(Uint32 *dest);
255: static Uint16 dsp_asr56(Uint32 *dest);
256: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest);
257: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest);
1.1.1.5 root 258: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe);
1.1.1.2 root 259: static void dsp_rnd56(Uint32 *dest);
1.1 root 260:
261: /* Instructions with parallel moves */
1.1.1.6 root 262: static void dsp_abs_a(void);
263: static void dsp_abs_b(void);
264: static void dsp_adc_x_a(void);
265: static void dsp_adc_x_b(void);
266: static void dsp_adc_y_a(void);
267: static void dsp_adc_y_b(void);
268: static void dsp_add_b_a(void);
269: static void dsp_add_a_b(void);
270: static void dsp_add_x_a(void);
271: static void dsp_add_x_b(void);
272: static void dsp_add_y_a(void);
273: static void dsp_add_y_b(void);
274: static void dsp_add_x0_a(void);
275: static void dsp_add_x0_b(void);
276: static void dsp_add_y0_a(void);
277: static void dsp_add_y0_b(void);
278: static void dsp_add_x1_a(void);
279: static void dsp_add_x1_b(void);
280: static void dsp_add_y1_a(void);
281: static void dsp_add_y1_b(void);
282: static void dsp_addl_b_a(void);
283: static void dsp_addl_a_b(void);
284: static void dsp_addr_b_a(void);
285: static void dsp_addr_a_b(void);
286: static void dsp_and_x0_a(void);
287: static void dsp_and_x0_b(void);
288: static void dsp_and_y0_a(void);
289: static void dsp_and_y0_b(void);
290: static void dsp_and_x1_a(void);
291: static void dsp_and_x1_b(void);
292: static void dsp_and_y1_a(void);
293: static void dsp_and_y1_b(void);
1.1.1.7 root 294: static void dsp_asl_a(void);
295: static void dsp_asl_b(void);
296: static void dsp_asr_a(void);
297: static void dsp_asr_b(void);
1.1.1.6 root 298: static void dsp_clr_a(void);
299: static void dsp_clr_b(void);
300: static void dsp_cmp_b_a(void);
301: static void dsp_cmp_a_b(void);
302: static void dsp_cmp_x0_a(void);
303: static void dsp_cmp_x0_b(void);
304: static void dsp_cmp_y0_a(void);
305: static void dsp_cmp_y0_b(void);
306: static void dsp_cmp_x1_a(void);
307: static void dsp_cmp_x1_b(void);
308: static void dsp_cmp_y1_a(void);
309: static void dsp_cmp_y1_b(void);
310: static void dsp_cmpm_b_a(void);
311: static void dsp_cmpm_a_b(void);
312: static void dsp_cmpm_x0_a(void);
313: static void dsp_cmpm_x0_b(void);
314: static void dsp_cmpm_y0_a(void);
315: static void dsp_cmpm_y0_b(void);
316: static void dsp_cmpm_x1_a(void);
317: static void dsp_cmpm_x1_b(void);
318: static void dsp_cmpm_y1_a(void);
319: static void dsp_cmpm_y1_b(void);
320: static void dsp_eor_x0_a(void);
321: static void dsp_eor_x0_b(void);
322: static void dsp_eor_y0_a(void);
323: static void dsp_eor_y0_b(void);
324: static void dsp_eor_x1_a(void);
325: static void dsp_eor_x1_b(void);
326: static void dsp_eor_y1_a(void);
327: static void dsp_eor_y1_b(void);
328: static void dsp_lsl_a(void);
329: static void dsp_lsl_b(void);
330: static void dsp_lsr_a(void);
331: static void dsp_lsr_b(void);
332: static void dsp_mac_p_x0_x0_a(void);
333: static void dsp_mac_m_x0_x0_a(void);
334: static void dsp_mac_p_x0_x0_b(void);
335: static void dsp_mac_m_x0_x0_b(void);
336: static void dsp_mac_p_y0_y0_a(void);
337: static void dsp_mac_m_y0_y0_a(void);
338: static void dsp_mac_p_y0_y0_b(void);
339: static void dsp_mac_m_y0_y0_b(void);
340: static void dsp_mac_p_x1_x0_a(void);
341: static void dsp_mac_m_x1_x0_a(void);
342: static void dsp_mac_p_x1_x0_b(void);
343: static void dsp_mac_m_x1_x0_b(void);
344: static void dsp_mac_p_y1_y0_a(void);
345: static void dsp_mac_m_y1_y0_a(void);
346: static void dsp_mac_p_y1_y0_b(void);
347: static void dsp_mac_m_y1_y0_b(void);
348: static void dsp_mac_p_x0_y1_a(void);
349: static void dsp_mac_m_x0_y1_a(void);
350: static void dsp_mac_p_x0_y1_b(void);
351: static void dsp_mac_m_x0_y1_b(void);
352: static void dsp_mac_p_y0_x0_a(void);
353: static void dsp_mac_m_y0_x0_a(void);
354: static void dsp_mac_p_y0_x0_b(void);
355: static void dsp_mac_m_y0_x0_b(void);
356: static void dsp_mac_p_x1_y0_a(void);
357: static void dsp_mac_m_x1_y0_a(void);
358: static void dsp_mac_p_x1_y0_b(void);
359: static void dsp_mac_m_x1_y0_b(void);
360: static void dsp_mac_p_y1_x1_a(void);
361: static void dsp_mac_m_y1_x1_a(void);
362: static void dsp_mac_p_y1_x1_b(void);
363: static void dsp_mac_m_y1_x1_b(void);
364: static void dsp_macr_p_x0_x0_a(void);
365: static void dsp_macr_m_x0_x0_a(void);
366: static void dsp_macr_p_x0_x0_b(void);
367: static void dsp_macr_m_x0_x0_b(void);
368: static void dsp_macr_p_y0_y0_a(void);
369: static void dsp_macr_m_y0_y0_a(void);
370: static void dsp_macr_p_y0_y0_b(void);
371: static void dsp_macr_m_y0_y0_b(void);
372: static void dsp_macr_p_x1_x0_a(void);
373: static void dsp_macr_m_x1_x0_a(void);
374: static void dsp_macr_p_x1_x0_b(void);
375: static void dsp_macr_m_x1_x0_b(void);
376: static void dsp_macr_p_y1_y0_a(void);
377: static void dsp_macr_m_y1_y0_a(void);
378: static void dsp_macr_p_y1_y0_b(void);
379: static void dsp_macr_m_y1_y0_b(void);
380: static void dsp_macr_p_x0_y1_a(void);
381: static void dsp_macr_m_x0_y1_a(void);
382: static void dsp_macr_p_x0_y1_b(void);
383: static void dsp_macr_m_x0_y1_b(void);
384: static void dsp_macr_p_y0_x0_a(void);
385: static void dsp_macr_m_y0_x0_a(void);
386: static void dsp_macr_p_y0_x0_b(void);
387: static void dsp_macr_m_y0_x0_b(void);
388: static void dsp_macr_p_x1_y0_a(void);
389: static void dsp_macr_m_x1_y0_a(void);
390: static void dsp_macr_p_x1_y0_b(void);
391: static void dsp_macr_m_x1_y0_b(void);
392: static void dsp_macr_p_y1_x1_a(void);
393: static void dsp_macr_m_y1_x1_a(void);
394: static void dsp_macr_p_y1_x1_b(void);
395: static void dsp_macr_m_y1_x1_b(void);
1.1 root 396: static void dsp_move(void);
1.1.1.6 root 397: static void dsp_mpy_p_x0_x0_a(void);
398: static void dsp_mpy_m_x0_x0_a(void);
399: static void dsp_mpy_p_x0_x0_b(void);
400: static void dsp_mpy_m_x0_x0_b(void);
401: static void dsp_mpy_p_y0_y0_a(void);
402: static void dsp_mpy_m_y0_y0_a(void);
403: static void dsp_mpy_p_y0_y0_b(void);
404: static void dsp_mpy_m_y0_y0_b(void);
405: static void dsp_mpy_p_x1_x0_a(void);
406: static void dsp_mpy_m_x1_x0_a(void);
407: static void dsp_mpy_p_x1_x0_b(void);
408: static void dsp_mpy_m_x1_x0_b(void);
409: static void dsp_mpy_p_y1_y0_a(void);
410: static void dsp_mpy_m_y1_y0_a(void);
411: static void dsp_mpy_p_y1_y0_b(void);
412: static void dsp_mpy_m_y1_y0_b(void);
413: static void dsp_mpy_p_x0_y1_a(void);
414: static void dsp_mpy_m_x0_y1_a(void);
415: static void dsp_mpy_p_x0_y1_b(void);
416: static void dsp_mpy_m_x0_y1_b(void);
417: static void dsp_mpy_p_y0_x0_a(void);
418: static void dsp_mpy_m_y0_x0_a(void);
419: static void dsp_mpy_p_y0_x0_b(void);
420: static void dsp_mpy_m_y0_x0_b(void);
421: static void dsp_mpy_p_x1_y0_a(void);
422: static void dsp_mpy_m_x1_y0_a(void);
423: static void dsp_mpy_p_x1_y0_b(void);
424: static void dsp_mpy_m_x1_y0_b(void);
425: static void dsp_mpy_p_y1_x1_a(void);
426: static void dsp_mpy_m_y1_x1_a(void);
427: static void dsp_mpy_p_y1_x1_b(void);
428: static void dsp_mpy_m_y1_x1_b(void);
429: static void dsp_mpyr_p_x0_x0_a(void);
430: static void dsp_mpyr_m_x0_x0_a(void);
431: static void dsp_mpyr_p_x0_x0_b(void);
432: static void dsp_mpyr_m_x0_x0_b(void);
433: static void dsp_mpyr_p_y0_y0_a(void);
434: static void dsp_mpyr_m_y0_y0_a(void);
435: static void dsp_mpyr_p_y0_y0_b(void);
436: static void dsp_mpyr_m_y0_y0_b(void);
437: static void dsp_mpyr_p_x1_x0_a(void);
438: static void dsp_mpyr_m_x1_x0_a(void);
439: static void dsp_mpyr_p_x1_x0_b(void);
440: static void dsp_mpyr_m_x1_x0_b(void);
441: static void dsp_mpyr_p_y1_y0_a(void);
442: static void dsp_mpyr_m_y1_y0_a(void);
443: static void dsp_mpyr_p_y1_y0_b(void);
444: static void dsp_mpyr_m_y1_y0_b(void);
445: static void dsp_mpyr_p_x0_y1_a(void);
446: static void dsp_mpyr_m_x0_y1_a(void);
447: static void dsp_mpyr_p_x0_y1_b(void);
448: static void dsp_mpyr_m_x0_y1_b(void);
449: static void dsp_mpyr_p_y0_x0_a(void);
450: static void dsp_mpyr_m_y0_x0_a(void);
451: static void dsp_mpyr_p_y0_x0_b(void);
452: static void dsp_mpyr_m_y0_x0_b(void);
453: static void dsp_mpyr_p_x1_y0_a(void);
454: static void dsp_mpyr_m_x1_y0_a(void);
455: static void dsp_mpyr_p_x1_y0_b(void);
456: static void dsp_mpyr_m_x1_y0_b(void);
457: static void dsp_mpyr_p_y1_x1_a(void);
458: static void dsp_mpyr_m_y1_x1_a(void);
459: static void dsp_mpyr_p_y1_x1_b(void);
460: static void dsp_mpyr_m_y1_x1_b(void);
461: static void dsp_neg_a(void);
462: static void dsp_neg_b(void);
463: static void dsp_not_a(void);
464: static void dsp_not_b(void);
465: static void dsp_or_x0_a(void);
466: static void dsp_or_x0_b(void);
467: static void dsp_or_y0_a(void);
468: static void dsp_or_y0_b(void);
469: static void dsp_or_x1_a(void);
470: static void dsp_or_x1_b(void);
471: static void dsp_or_y1_a(void);
472: static void dsp_or_y1_b(void);
473: static void dsp_rnd_a(void);
474: static void dsp_rnd_b(void);
475: static void dsp_rol_a(void);
476: static void dsp_rol_b(void);
477: static void dsp_ror_a(void);
478: static void dsp_ror_b(void);
479: static void dsp_sbc_x_a(void);
480: static void dsp_sbc_x_b(void);
481: static void dsp_sbc_y_a(void);
482: static void dsp_sbc_y_b(void);
483: static void dsp_sub_b_a(void);
484: static void dsp_sub_a_b(void);
485: static void dsp_sub_x_a(void);
486: static void dsp_sub_x_b(void);
487: static void dsp_sub_y_a(void);
488: static void dsp_sub_y_b(void);
489: static void dsp_sub_x0_a(void);
490: static void dsp_sub_x0_b(void);
491: static void dsp_sub_y0_a(void);
492: static void dsp_sub_y0_b(void);
493: static void dsp_sub_x1_a(void);
494: static void dsp_sub_x1_b(void);
495: static void dsp_sub_y1_a(void);
496: static void dsp_sub_y1_b(void);
497: static void dsp_subl_a(void);
498: static void dsp_subl_b(void);
499: static void dsp_subr_a(void);
500: static void dsp_subr_b(void);
501: static void dsp_tfr_b_a(void);
502: static void dsp_tfr_a_b(void);
503: static void dsp_tfr_x0_a(void);
504: static void dsp_tfr_x0_b(void);
505: static void dsp_tfr_y0_a(void);
506: static void dsp_tfr_y0_b(void);
507: static void dsp_tfr_x1_a(void);
508: static void dsp_tfr_x1_b(void);
509: static void dsp_tfr_y1_a(void);
510: static void dsp_tfr_y1_b(void);
511: static void dsp_tst_a(void);
512: static void dsp_tst_b(void);
1.1 root 513:
1.1.1.6 root 514: static const dsp_emul_t opcodes8h[512] = {
1.1.1.4 root 515: /* 0x00 - 0x3f */
516: opcode8h_0, dsp_undefined, dsp_undefined, dsp_undefined, opcode8h_0, dsp_andi, dsp_undefined, dsp_ori,
517: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
518: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
519: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
520: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
521: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
522: dsp_undefined, dsp_undefined, dsp_div, dsp_div, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
523: dsp_norm, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
1.1.1.11 root 524:
1.1.1.4 root 525: /* 0x40 - 0x7f */
526: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
527: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
528: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
529: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
530: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
531: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
532: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
533: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
534:
535: /* 0x80 - 0xbf */
536: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
1.1.1.11 root 537: dsp_lua, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
1.1.1.4 root 538: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
1.1.1.11 root 539: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
1.1.1.4 root 540: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
541: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
542: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
543: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
1.1.1.11 root 544:
1.1.1.4 root 545: /* 0xc0 - 0xff */
1.1.1.11 root 546: dsp_do_aa, dsp_rep_aa, dsp_do_aa, dsp_rep_aa, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
547: dsp_do_ea, dsp_rep_ea, dsp_do_ea, dsp_rep_ea, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
548: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
549: dsp_do_reg, dsp_rep_reg, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
550: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
551: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
552: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
553: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
1.1.1.4 root 554:
555: /* 0x100 - 0x13f */
1.1.1.6 root 556: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 557: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 558: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 559: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 560: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 561: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 562: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 563: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
564:
565: /* 0x140 - 0x17f */
566: dsp_bclr_aa, dsp_bset_aa, dsp_bclr_aa, dsp_bset_aa, dsp_jclr_aa, dsp_jset_aa, dsp_jclr_aa, dsp_jset_aa,
567: dsp_bclr_ea, dsp_bset_ea, dsp_bclr_ea, dsp_bset_ea, dsp_jclr_ea, dsp_jset_ea, dsp_jclr_ea, dsp_jset_ea,
568: dsp_bclr_pp, dsp_bset_pp, dsp_bclr_pp, dsp_bset_pp, dsp_jclr_pp, dsp_jset_pp, dsp_jclr_pp, dsp_jset_pp,
569: dsp_jclr_reg, dsp_jset_reg, dsp_bclr_reg, dsp_bset_reg, dsp_jmp_ea, dsp_jcc_ea, dsp_undefined, dsp_undefined,
570: dsp_bchg_aa, dsp_btst_aa, dsp_bchg_aa, dsp_btst_aa, dsp_jsclr_aa, dsp_jsset_aa, dsp_jsclr_aa, dsp_jsset_aa,
571: dsp_bchg_ea, dsp_btst_ea, dsp_bchg_ea, dsp_btst_ea, dsp_jsclr_ea, dsp_jsset_ea, dsp_jsclr_ea, dsp_jsset_ea,
572: dsp_bchg_pp, dsp_btst_pp, dsp_bchg_pp, dsp_btst_pp, dsp_jsclr_pp, dsp_jsset_pp, dsp_jsclr_pp, dsp_jsset_pp,
573: dsp_jsclr_reg, dsp_jsset_reg, dsp_bchg_reg, dsp_btst_reg, dsp_jsr_ea, dsp_jscc_ea, dsp_undefined, dsp_undefined,
574:
575: /* 0x180 - 0x1bf */
576: dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm,
1.1.1.11 root 577: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
578: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
579: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
580: dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm,
581: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
582: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
583: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
1.1.1.4 root 584:
585: /* 0x1c0 - 0x1ff */
1.1.1.11 root 586: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
587: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
588: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
589: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
590: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
591: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
592: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
593: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
1.1 root 594: };
595:
1.1.1.6 root 596: static const dsp_emul_t opcodes_parmove[16] = {
597: dsp_pm_0, dsp_pm_1, dsp_pm_2, dsp_pm_3, dsp_pm_4, dsp_pm_5, dsp_pm_5, dsp_pm_5,
598: dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8
1.1 root 599: };
600:
1.1.1.6 root 601: static const dsp_emul_t opcodes_alu[256] = {
1.1.1.4 root 602: /* 0x00 - 0x3f */
1.1.1.6 root 603: dsp_move , dsp_tfr_b_a, dsp_addr_b_a, dsp_tst_a, dsp_undefined, dsp_cmp_b_a, dsp_subr_a, dsp_cmpm_b_a,
604: dsp_undefined, dsp_tfr_a_b, dsp_addr_a_b, dsp_tst_b, dsp_undefined, dsp_cmp_a_b, dsp_subr_b, dsp_cmpm_a_b,
605: dsp_add_b_a, dsp_rnd_a, dsp_addl_b_a, dsp_clr_a, dsp_sub_b_a, dsp_undefined, dsp_subl_a, dsp_not_a,
606: dsp_add_a_b, dsp_rnd_b, dsp_addl_a_b, dsp_clr_b, dsp_sub_a_b, dsp_undefined, dsp_subl_b, dsp_not_b,
1.1.1.7 root 607: dsp_add_x_a, dsp_adc_x_a, dsp_asr_a, dsp_lsr_a, dsp_sub_x_a, dsp_sbc_x_a, dsp_abs_a, dsp_ror_a,
608: dsp_add_x_b, dsp_adc_x_b, dsp_asr_b, dsp_lsr_b, dsp_sub_x_b, dsp_sbc_x_b, dsp_abs_b, dsp_ror_b,
609: dsp_add_y_a, dsp_adc_y_a, dsp_asl_a, dsp_lsl_a, dsp_sub_y_a, dsp_sbc_y_a, dsp_neg_a, dsp_rol_a,
610: dsp_add_y_b, dsp_adc_y_b, dsp_asl_b, dsp_lsl_b, dsp_sub_y_b, dsp_sbc_y_b, dsp_neg_b, dsp_rol_b,
1.1.1.11 root 611:
1.1.1.4 root 612: /* 0x40 - 0x7f */
1.1.1.6 root 613: dsp_add_x0_a, dsp_tfr_x0_a, dsp_or_x0_a, dsp_eor_x0_a, dsp_sub_x0_a, dsp_cmp_x0_a, dsp_and_x0_a, dsp_cmpm_x0_a,
614: dsp_add_x0_b, dsp_tfr_x0_b, dsp_or_x0_b, dsp_eor_x0_b, dsp_sub_x0_b, dsp_cmp_x0_b, dsp_and_x0_b, dsp_cmpm_x0_b,
615: dsp_add_y0_a, dsp_tfr_y0_a, dsp_or_y0_a, dsp_eor_y0_a, dsp_sub_y0_a, dsp_cmp_y0_a, dsp_and_y0_a, dsp_cmpm_y0_a,
616: dsp_add_y0_b, dsp_tfr_y0_b, dsp_or_y0_b, dsp_eor_y0_b, dsp_sub_y0_b, dsp_cmp_y0_b, dsp_and_y0_b, dsp_cmpm_y0_b,
617: dsp_add_x1_a, dsp_tfr_x1_a, dsp_or_x1_a, dsp_eor_x1_a, dsp_sub_x1_a, dsp_cmp_x1_a, dsp_and_x1_a, dsp_cmpm_x1_a,
618: dsp_add_x1_b, dsp_tfr_x1_b, dsp_or_x1_b, dsp_eor_x1_b, dsp_sub_x1_b, dsp_cmp_x1_b, dsp_and_x1_b, dsp_cmpm_x1_b,
619: dsp_add_y1_a, dsp_tfr_y1_a, dsp_or_y1_a, dsp_eor_y1_a, dsp_sub_y1_a, dsp_cmp_y1_a, dsp_and_y1_a, dsp_cmpm_y1_a,
620: dsp_add_y1_b, dsp_tfr_y1_b, dsp_or_y1_b, dsp_eor_y1_b, dsp_sub_y1_b, dsp_cmp_y1_b, dsp_and_y1_b, dsp_cmpm_y1_b,
1.1.1.4 root 621:
622: /* 0x80 - 0xbf */
1.1.1.6 root 623: dsp_mpy_p_x0_x0_a, dsp_mpyr_p_x0_x0_a, dsp_mac_p_x0_x0_a, dsp_macr_p_x0_x0_a, dsp_mpy_m_x0_x0_a, dsp_mpyr_m_x0_x0_a, dsp_mac_m_x0_x0_a, dsp_macr_m_x0_x0_a,
624: dsp_mpy_p_x0_x0_b, dsp_mpyr_p_x0_x0_b, dsp_mac_p_x0_x0_b, dsp_macr_p_x0_x0_b, dsp_mpy_m_x0_x0_b, dsp_mpyr_m_x0_x0_b, dsp_mac_m_x0_x0_b, dsp_macr_m_x0_x0_b,
625: dsp_mpy_p_y0_y0_a, dsp_mpyr_p_y0_y0_a, dsp_mac_p_y0_y0_a, dsp_macr_p_y0_y0_a, dsp_mpy_m_y0_y0_a, dsp_mpyr_m_y0_y0_a, dsp_mac_m_y0_y0_a, dsp_macr_m_y0_y0_a,
626: dsp_mpy_p_y0_y0_b, dsp_mpyr_p_y0_y0_b, dsp_mac_p_y0_y0_b, dsp_macr_p_y0_y0_b, dsp_mpy_m_y0_y0_b, dsp_mpyr_m_y0_y0_b, dsp_mac_m_y0_y0_b, dsp_macr_m_y0_y0_b,
627: dsp_mpy_p_x1_x0_a, dsp_mpyr_p_x1_x0_a, dsp_mac_p_x1_x0_a, dsp_macr_p_x1_x0_a, dsp_mpy_m_x1_x0_a, dsp_mpyr_m_x1_x0_a, dsp_mac_m_x1_x0_a, dsp_macr_m_x1_x0_a,
628: dsp_mpy_p_x1_x0_b, dsp_mpyr_p_x1_x0_b, dsp_mac_p_x1_x0_b, dsp_macr_p_x1_x0_b, dsp_mpy_m_x1_x0_b, dsp_mpyr_m_x1_x0_b, dsp_mac_m_x1_x0_b, dsp_macr_m_x1_x0_b,
629: dsp_mpy_p_y1_y0_a, dsp_mpyr_p_y1_y0_a, dsp_mac_p_y1_y0_a, dsp_macr_p_y1_y0_a, dsp_mpy_m_y1_y0_a, dsp_mpyr_m_y1_y0_a, dsp_mac_m_y1_y0_a, dsp_macr_m_y1_y0_a,
630: dsp_mpy_p_y1_y0_b, dsp_mpyr_p_y1_y0_b, dsp_mac_p_y1_y0_b, dsp_macr_p_y1_y0_b, dsp_mpy_m_y1_y0_b, dsp_mpyr_m_y1_y0_b, dsp_mac_m_y1_y0_b, dsp_macr_m_y1_y0_b,
631:
632: /* 0xc0_m_ 0xff */
633: dsp_mpy_p_x0_y1_a, dsp_mpyr_p_x0_y1_a, dsp_mac_p_x0_y1_a, dsp_macr_p_x0_y1_a, dsp_mpy_m_x0_y1_a, dsp_mpyr_m_x0_y1_a, dsp_mac_m_x0_y1_a, dsp_macr_m_x0_y1_a,
634: dsp_mpy_p_x0_y1_b, dsp_mpyr_p_x0_y1_b, dsp_mac_p_x0_y1_b, dsp_macr_p_x0_y1_b, dsp_mpy_m_x0_y1_b, dsp_mpyr_m_x0_y1_b, dsp_mac_m_x0_y1_b, dsp_macr_m_x0_y1_b,
635: dsp_mpy_p_y0_x0_a, dsp_mpyr_p_y0_x0_a, dsp_mac_p_y0_x0_a, dsp_macr_p_y0_x0_a, dsp_mpy_m_y0_x0_a, dsp_mpyr_m_y0_x0_a, dsp_mac_m_y0_x0_a, dsp_macr_m_y0_x0_a,
636: dsp_mpy_p_y0_x0_b, dsp_mpyr_p_y0_x0_b, dsp_mac_p_y0_x0_b, dsp_macr_p_y0_x0_b, dsp_mpy_m_y0_x0_b, dsp_mpyr_m_y0_x0_b, dsp_mac_m_y0_x0_b, dsp_macr_m_y0_x0_b,
637: dsp_mpy_p_x1_y0_a, dsp_mpyr_p_x1_y0_a, dsp_mac_p_x1_y0_a, dsp_macr_p_x1_y0_a, dsp_mpy_m_x1_y0_a, dsp_mpyr_m_x1_y0_a, dsp_mac_m_x1_y0_a, dsp_macr_m_x1_y0_a,
638: dsp_mpy_p_x1_y0_b, dsp_mpyr_p_x1_y0_b, dsp_mac_p_x1_y0_b, dsp_macr_p_x1_y0_b, dsp_mpy_m_x1_y0_b, dsp_mpyr_m_x1_y0_b, dsp_mac_m_x1_y0_b, dsp_macr_m_x1_y0_b,
639: dsp_mpy_p_y1_x1_a, dsp_mpyr_p_y1_x1_a, dsp_mac_p_y1_x1_a, dsp_macr_p_y1_x1_a, dsp_mpy_m_y1_x1_a, dsp_mpyr_m_y1_x1_a, dsp_mac_m_y1_x1_a, dsp_macr_m_y1_x1_a,
640: dsp_mpy_p_y1_x1_b, dsp_mpyr_p_y1_x1_b, dsp_mac_p_y1_x1_b, dsp_macr_p_y1_x1_b, dsp_mpy_m_y1_x1_b, dsp_mpyr_m_y1_x1_b, dsp_mac_m_y1_x1_b, dsp_macr_m_y1_x1_b
1.1 root 641: };
642:
1.1.1.6 root 643: static const int registers_tcc[16][2] = {
1.1 root 644: {DSP_REG_B,DSP_REG_A},
645: {DSP_REG_A,DSP_REG_B},
646: {DSP_REG_NULL,DSP_REG_NULL},
647: {DSP_REG_NULL,DSP_REG_NULL},
648:
649: {DSP_REG_NULL,DSP_REG_NULL},
650: {DSP_REG_NULL,DSP_REG_NULL},
651: {DSP_REG_NULL,DSP_REG_NULL},
652: {DSP_REG_NULL,DSP_REG_NULL},
653:
654: {DSP_REG_X0,DSP_REG_A},
655: {DSP_REG_X0,DSP_REG_B},
656: {DSP_REG_Y0,DSP_REG_A},
657: {DSP_REG_Y0,DSP_REG_B},
1.1.1.2 root 658:
659: {DSP_REG_X1,DSP_REG_A},
660: {DSP_REG_X1,DSP_REG_B},
1.1 root 661: {DSP_REG_Y1,DSP_REG_A},
662: {DSP_REG_Y1,DSP_REG_B}
663: };
664:
1.1.1.6 root 665: static const int registers_mask[64] = {
1.1 root 666: 0, 0, 0, 0,
667: 24, 24, 24, 24,
668: 24, 24, 8, 8,
669: 24, 24, 24, 24,
1.1.1.11 root 670:
1.1 root 671: 16, 16, 16, 16,
672: 16, 16, 16, 16,
673: 16, 16, 16, 16,
674: 16, 16, 16, 16,
1.1.1.11 root 675:
1.1 root 676: 16, 16, 16, 16,
677: 16, 16, 16, 16,
678: 0, 0, 0, 0,
679: 0, 0, 0, 0,
680:
681: 0, 0, 0, 0,
682: 0, 0, 0, 0,
683: 0, 16, 8, 6,
1.1.1.4 root 684: 16, 16, 16, 16
685: };
686:
1.1.1.6 root 687: static const dsp_interrupt_t dsp_interrupt[12] = {
1.1.1.5 root 688: {DSP_INTER_RESET , 0x00, 0, "Reset"},
689: {DSP_INTER_ILLEGAL , 0x3e, 0, "Illegal"},
690: {DSP_INTER_STACK_ERROR , 0x02, 0, "Stack Error"},
691: {DSP_INTER_TRACE , 0x04, 0, "Trace"},
692: {DSP_INTER_SWI , 0x06, 0, "Swi"},
693: {DSP_INTER_HOST_COMMAND , 0xff, 1, "Host Command"},
694: {DSP_INTER_HOST_RCV_DATA, 0x20, 1, "Host receive"},
695: {DSP_INTER_HOST_TRX_DATA, 0x22, 1, "Host transmit"},
696: {DSP_INTER_SSI_RCV_DATA_E, 0x0e, 2, "SSI receive with exception"},
697: {DSP_INTER_SSI_RCV_DATA , 0x0c, 2, "SSI receive"},
698: {DSP_INTER_SSI_TRX_DATA_E, 0x12, 2, "SSI transmit with exception"},
699: {DSP_INTER_SSI_TRX_DATA , 0x10, 2, "SSI tramsmit"}
1.1.1.4 root 700: };
701:
1.1.1.13 root 702: static struct {
703: int limit;
704: int count;
705: Uint32 inst;
706: Uint16 pc;
707: } dsp_error;
708:
1.1 root 709:
710: /**********************************
711: * Emulator kernel
712: **********************************/
713:
1.1.1.6 root 714: void dsp56k_init_cpu(void)
1.1 root 715: {
1.1.1.6 root 716: dsp56k_disasm_init();
717: isDsp_in_disasm_mode = false;
1.1.1.13 root 718: memset(&dsp_error, 0, sizeof(dsp_error));
719: dsp_error.limit = 1;
1.1.1.14! root 720: #if DSP_COUNT_IPS
! 721: start_time = SDL_GetTicks();
1.1.1.2 root 722: num_inst = 0;
1.1.1.14! root 723: #endif
1.1 root 724: }
725:
1.1.1.6 root 726: /**
727: * Execute one instruction in trace mode at a given PC address.
728: * */
1.1.1.9 root 729: Uint16 dsp56k_execute_one_disasm_instruction(FILE *out, Uint16 pc)
1.1.1.6 root 730: {
731: dsp_core_t *ptr1, *ptr2;
732: static dsp_core_t dsp_core_save;
1.1.1.8 root 733: Uint16 instruction_length;
1.1.1.6 root 734:
735: ptr1 = &dsp_core;
736: ptr2 = &dsp_core_save;
737:
738: /* Set DSP in disasm mode */
739: isDsp_in_disasm_mode = true;
740:
741: /* Save DSP context before executing instruction */
742: memcpy(ptr2, ptr1, sizeof(dsp_core));
743:
744: /* execute and disasm instruction */
745: dsp_core.pc = pc;
746:
747: /* Disasm instruction */
1.1.1.12 root 748: instruction_length = dsp56k_disasm(DSP_DISASM_MODE, out) - 1;
1.1.1.6 root 749:
750: /* Execute instruction at address given in parameter to get the number of cycles it takes */
751: dsp56k_execute_instruction();
752:
1.1.1.9 root 753: fprintf(out, "%s", dsp56k_getInstructionText());
1.1.1.6 root 754:
755: /* Restore DSP context after executing instruction */
756: memcpy(ptr1, ptr2, sizeof(dsp_core));
1.1.1.11 root 757:
1.1.1.6 root 758: /* Unset DSP in disasm mode */
759: isDsp_in_disasm_mode = false;
760:
761: return instruction_length;
762: }
763:
1.1.1.4 root 764: void dsp56k_execute_instruction(void)
1.1 root 765: {
1.1.1.2 root 766: Uint32 value;
1.1.1.6 root 767: Uint32 disasm_return = 0;
1.1.1.5 root 768: disasm_memory_ptr = 0;
769:
1.1.1.7 root 770: /* Initialise the number of access to the external memory for this instruction */
1.1.1.9 root 771: access_to_ext_memory = 0;
1.1.1.11 root 772:
773: /* Init the indirect AGU move instruction flag */
774: dsp_core.agu_move_indirect_instr = 0;
775:
1.1 root 776: /* Decode and execute current instruction */
1.1.1.6 root 777: cur_inst = read_memory_p(dsp_core.pc);
1.1.1.11 root 778:
1.1.1.7 root 779: /* Initialize instruction size and cycle counter */
780: cur_inst_len = 1;
1.1.1.6 root 781: dsp_core.instr_cycle = 2;
1.1 root 782:
1.1.1.6 root 783: /* Disasm current instruction ? (trace mode only) */
1.1.1.11 root 784: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
1.1.1.6 root 785: /* Call dsp56k_disasm only when DSP is called in trace mode */
786: if (isDsp_in_disasm_mode == false) {
1.1.1.12 root 787: disasm_return = dsp56k_disasm(DSP_TRACE_MODE, TraceFile);
1.1.1.11 root 788:
1.1.1.6 root 789: if (disasm_return != 0 && LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG)) {
790: /* DSP regs trace enabled only if DSP DISASM is enabled */
791: dsp56k_disasm_reg_save();
792: }
793: }
794: }
1.1.1.11 root 795:
1.1.1.4 root 796: if (cur_inst < 0x100000) {
797: value = (cur_inst >> 11) & (BITMASK(6) << 3);
798: value += (cur_inst >> 5) & BITMASK(3);
1.1 root 799: opcodes8h[value]();
800: } else {
1.1.1.6 root 801: /* Do parallel move read */
802: opcodes_parmove[(cur_inst>>20) & BITMASK(4)]();
803: }
804:
1.1.1.7 root 805: /* Add the waitstate due to external memory access */
1.1.1.9 root 806: /* (2 extra cycles per extra access to the external memory after the first one */
807: if (access_to_ext_memory != 0) {
808: value = access_to_ext_memory & 1;
809: value += (access_to_ext_memory & 2) >> 1;
810: value += (access_to_ext_memory & 4) >> 2;
1.1.1.11 root 811:
1.1.1.9 root 812: if (value > 1)
813: dsp_core.instr_cycle += (value - 1) * 2;
814: }
815:
1.1.1.6 root 816: /* Disasm current instruction ? (trace mode only) */
817: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
818: /* Display only when DSP is called in trace mode */
819: if (isDsp_in_disasm_mode == false) {
820: if (disasm_return != 0) {
1.1.1.12 root 821: fprintf(TraceFile, "%s", dsp56k_getInstructionText());
1.1.1.11 root 822:
1.1.1.6 root 823: /* DSP regs trace enabled only if DSP DISASM is enabled */
824: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG))
1.1.1.12 root 825: dsp56k_disasm_reg_compare(TraceFile);
1.1.1.6 root 826:
827: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM)) {
828: /* 1 memory change to display ? */
829: if (disasm_memory_ptr == 1)
1.1.1.12 root 830: fprintf(TraceFile, "\t%s\n", str_disasm_memory[0]);
1.1.1.6 root 831: /* 2 memory changes to display ? */
832: else if (disasm_memory_ptr == 2) {
1.1.1.12 root 833: fprintf(TraceFile, "\t%s\n", str_disasm_memory[0]);
834: fprintf(TraceFile, "\t%s\n", str_disasm_memory[1]);
1.1.1.6 root 835: }
836: }
837: }
838: }
1.1 root 839: }
840:
1.1.1.4 root 841: /* Process the PC */
842: dsp_postexecute_update_pc();
1.1 root 843:
1.1.1.4 root 844: /* Process Interrupts */
1.1 root 845: dsp_postexecute_interrupts();
846:
1.1.1.4 root 847: #if DSP_COUNT_IPS
848: ++num_inst;
849: if ((num_inst & 63) == 0) {
850: /* Evaluate time after <N> instructions have been executed to avoid asking too frequently */
851: Uint32 cur_time = SDL_GetTicks();
852: if (cur_time-start_time>1000) {
853: fprintf(stderr, "Dsp: %d i/s\n", (num_inst*1000)/(cur_time-start_time));
854: start_time=cur_time;
855: num_inst=0;
856: }
857: }
858: #endif
1.1 root 859: }
860:
861: /**********************************
862: * Update the PC
863: **********************************/
864:
865: static void dsp_postexecute_update_pc(void)
866: {
867: /* When running a REP, PC must stay on the current instruction */
1.1.1.6 root 868: if (dsp_core.loop_rep) {
1.1.1.11 root 869: /* Is PC on the instruction to repeat ? */
1.1.1.6 root 870: if (dsp_core.pc_on_rep==0) {
871: --dsp_core.registers[DSP_REG_LC];
872: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1 root 873:
1.1.1.6 root 874: if (dsp_core.registers[DSP_REG_LC] > 0) {
1.1.1.7 root 875: cur_inst_len = 0; /* Stay on this instruction */
1.1 root 876: } else {
1.1.1.6 root 877: dsp_core.loop_rep = 0;
878: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[DSP_REG_LCSAVE];
1.1 root 879: }
880: } else {
881: /* Init LC at right value */
1.1.1.6 root 882: if (dsp_core.registers[DSP_REG_LC] == 0) {
883: dsp_core.registers[DSP_REG_LC] = 0x010000;
1.1 root 884: }
1.1.1.6 root 885: dsp_core.pc_on_rep = 0;
1.1 root 886: }
887: }
888:
889: /* Normal execution, go to next instruction */
1.1.1.6 root 890: dsp_core.pc += cur_inst_len;
1.1 root 891:
892: /* When running a DO loop, we test the end of loop with the */
893: /* updated PC, pointing to last instruction of the loop */
1.1.1.6 root 894: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_LF)) {
1.1 root 895:
896: /* Did we execute the last instruction in loop ? */
1.1.1.11 root 897: if (dsp_core.pc == dsp_core.registers[DSP_REG_LA] + 1) {
898: if (dsp_core.registers[DSP_REG_LC] == 1) {
899: /* end of the loop */
1.1.1.4 root 900: Uint32 saved_pc, saved_sr;
901:
902: dsp_stack_pop(&saved_pc, &saved_sr);
1.1.1.10 root 903: dsp_core.registers[DSP_REG_SR] &= 0x7fff;
1.1.1.6 root 904: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
905: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
1.1 root 906: } else {
907: /* Loop one more time */
1.1.1.11 root 908: --dsp_core.registers[DSP_REG_LC];
909: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.6 root 910: dsp_core.pc = dsp_core.registers[DSP_REG_SSH];
1.1 root 911: }
912: }
913: }
914: }
915:
916: /**********************************
917: * Interrupts
918: **********************************/
919:
1.1.1.5 root 920: /* Post a new interrupt to the interrupt table */
921: void dsp_add_interrupt(Uint16 inter)
922: {
923: /* detect if this interrupt is used or not */
1.1.1.6 root 924: if (dsp_core.interrupt_ipl[inter] == -1)
1.1.1.5 root 925: return;
926:
927: /* add this interrupt to the pending interrupts table */
1.1.1.11 root 928: if (dsp_core.interrupt_isPending[inter] == 0) {
1.1.1.6 root 929: dsp_core.interrupt_isPending[inter] = 1;
930: dsp_core.interrupt_counter ++;
1.1.1.5 root 931: }
932: }
933:
934: static void dsp_setInterruptIPL(Uint32 value)
935: {
936: Uint32 ipl_ssi, ipl_hi, i;
937:
938: ipl_ssi = ((value >> 12) & 3) - 1;
939: ipl_hi = ((value >> 10) & 3) - 1;
940:
941: /* set IPL_HI */
1.1.1.7 root 942: for (i=5; i<8; i++) {
1.1.1.6 root 943: dsp_core.interrupt_ipl[i] = ipl_hi;
1.1.1.5 root 944: }
945:
946: /* set IPL_SSI */
1.1.1.7 root 947: for (i=8; i<12; i++) {
1.1.1.6 root 948: dsp_core.interrupt_ipl[i] = ipl_ssi;
1.1.1.5 root 949: }
950: }
951:
1.1 root 952: static void dsp_postexecute_interrupts(void)
953: {
1.1.1.5 root 954: Uint32 index, instr, i;
955: Sint32 ipl_to_raise, ipl_sr;
1.1.1.4 root 956:
957: /* REP is not interruptible */
1.1.1.6 root 958: if (dsp_core.loop_rep) {
1.1.1.4 root 959: return;
960: }
961:
962: /* A fast interrupt can not be interrupted. */
1.1.1.6 root 963: if (dsp_core.interrupt_state == DSP_INTERRUPT_DISABLED) {
1.1.1.5 root 964:
1.1.1.6 root 965: switch (dsp_core.interrupt_pipeline_count) {
1.1.1.5 root 966: case 5:
1.1.1.6 root 967: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 968: return;
969: case 4:
970: /* Prefetch interrupt instruction 1 */
1.1.1.6 root 971: dsp_core.interrupt_save_pc = dsp_core.pc;
972: dsp_core.pc = dsp_core.interrupt_instr_fetch;
1.1.1.5 root 973:
974: /* is it a LONG interrupt ? */
1.1.1.6 root 975: instr = read_memory_p(dsp_core.interrupt_instr_fetch);
1.1.1.5 root 976: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1.1.1.6 root 977: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
1.1.1.11 root 978: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.6 root 979: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1.1.1.5 root 980: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
981: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1.1.1.6 root 982: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1.1.1.5 root 983: }
1.1.1.6 root 984: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 985: return;
986: case 3:
1.1.1.11 root 987: /* Prefetch interrupt instruction 2, if first one was single word */
1.1.1.6 root 988: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+1) {
989: instr = read_memory_p(dsp_core.pc);
1.1.1.5 root 990: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1.1.1.6 root 991: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
1.1.1.11 root 992: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.6 root 993: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1.1.1.5 root 994: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
995: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1.1.1.6 root 996: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1.1.1.5 root 997: }
1.1.1.11 root 998: dsp_core.interrupt_pipeline_count --;
999: return;
1000: }
1001: dsp_core.interrupt_pipeline_count --;
1002: /* First instruction was 2 word. Fall through */
1.1.1.5 root 1003: case 2:
1004: /* 1 instruction executed after interrupt */
1005: /* before re enable interrupts */
1006: /* Was it a FAST interrupt ? */
1.1.1.6 root 1007: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+2) {
1008: dsp_core.pc = dsp_core.interrupt_save_pc;
1.1.1.5 root 1009: }
1.1.1.6 root 1010: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 1011: return;
1012: case 1:
1013: /* Last instruction executed after interrupt */
1014: /* before re enable interrupts */
1.1.1.6 root 1015: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 1016: return;
1017: case 0:
1018: /* Re enable interrupts */
1.1.1.6 root 1019: /* All 6 instruction are done, Interrupts can be enabled again */
1020: dsp_core.interrupt_save_pc = -1;
1021: dsp_core.interrupt_instr_fetch = -1;
1022: dsp_core.interrupt_state = DSP_INTERRUPT_NONE;
1023: break;
1.1.1.4 root 1024: }
1025: }
1.1 root 1026:
1.1.1.4 root 1027: /* Trace Interrupt ? */
1.1.1.6 root 1028: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_T)) {
1.1.1.5 root 1029: dsp_add_interrupt(DSP_INTER_TRACE);
1.1.1.4 root 1030: }
1031:
1032: /* No interrupt to execute */
1.1.1.6 root 1033: if (dsp_core.interrupt_counter == 0) {
1.1.1.4 root 1034: return;
1.1 root 1035: }
1036:
1.1.1.5 root 1037: /* search for an interrupt */
1.1.1.6 root 1038: ipl_sr = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_I0) & BITMASK(2);
1.1.1.5 root 1039: index = 0xffff;
1040: ipl_to_raise = -1;
1041:
1042: /* Arbitrate between all pending interrupts */
1043: for (i=0; i<12; i++) {
1.1.1.6 root 1044: if (dsp_core.interrupt_isPending[i] == 1) {
1.1.1.5 root 1045:
1046: /* level 3 interrupt ? */
1.1.1.6 root 1047: if (dsp_core.interrupt_ipl[i] == 3) {
1.1.1.5 root 1048: index = i;
1049: break;
1050: }
1.1 root 1051:
1.1.1.5 root 1052: /* level 0, 1 ,2 interrupt ? */
1053: /* if interrupt is masked in SR, don't process it */
1.1.1.6 root 1054: if (dsp_core.interrupt_ipl[i] < ipl_sr)
1.1.1.5 root 1055: continue;
1.1 root 1056:
1.1.1.5 root 1057: /* if interrupt is lower or equal than current arbitrated interrupt */
1.1.1.6 root 1058: if (dsp_core.interrupt_ipl[i] <= ipl_to_raise)
1.1.1.5 root 1059: continue;
1060:
1061: /* save current arbitrated interrupt */
1062: index = i;
1.1.1.6 root 1063: ipl_to_raise = dsp_core.interrupt_ipl[i];
1.1 root 1064: }
1065: }
1.1.1.4 root 1066:
1.1.1.5 root 1067: /* If there's no interrupt to process, return */
1068: if (index == 0xffff) {
1.1.1.4 root 1069: return;
1070: }
1071:
1.1.1.5 root 1072: /* remove this interrupt from the pending interrupts table */
1.1.1.6 root 1073: dsp_core.interrupt_isPending[index] = 0;
1074: dsp_core.interrupt_counter --;
1.1.1.5 root 1075:
1076: /* process arbritrated interrupt */
1.1.1.6 root 1077: ipl_to_raise = dsp_core.interrupt_ipl[index] + 1;
1.1.1.5 root 1078: if (ipl_to_raise > 3) {
1079: ipl_to_raise = 3;
1080: }
1081:
1.1.1.6 root 1082: dsp_core.interrupt_instr_fetch = dsp_interrupt[index].vectorAddr;
1083: dsp_core.interrupt_pipeline_count = 5;
1084: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1085: dsp_core.interrupt_IplToRaise = ipl_to_raise;
1086:
1087: LOG_TRACE(TRACE_DSP_INTERRUPT, "Dsp interrupt: %s\n", dsp_interrupt[index].name);
1.1.1.5 root 1088:
1089: /* SSI receive data with exception ? */
1.1.1.6 root 1090: if (dsp_core.interrupt_instr_fetch == 0xe) {
1091: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_ROE);
1.1.1.4 root 1092: }
1093:
1.1.1.5 root 1094: /* SSI transmit data with exception ? */
1.1.1.6 root 1095: else if (dsp_core.interrupt_instr_fetch == 0x12) {
1096: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_TUE);
1.1.1.4 root 1097: }
1098:
1099: /* host command ? */
1.1.1.6 root 1100: else if (dsp_core.interrupt_instr_fetch == 0xff) {
1.1.1.4 root 1101: /* Clear HC and HCP interrupt */
1.1.1.6 root 1102: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] &= 0xff - (1<<DSP_HOST_HSR_HCP);
1.1.1.11 root 1103: dsp_core.hostport[CPU_HOST_CVR] &= 0xff - (1<<CPU_HOST_CVR_HC);
1.1.1.4 root 1104:
1.1.1.6 root 1105: dsp_core.interrupt_instr_fetch = dsp_core.hostport[CPU_HOST_CVR] & BITMASK(5);
1.1.1.11 root 1106: dsp_core.interrupt_instr_fetch *= 2;
1.1.1.4 root 1107: }
1.1 root 1108: }
1109:
1110: /**********************************
1111: * Set/clear ccr bits
1112: **********************************/
1113:
1114: /* reg0 has bits 55..48 */
1115: /* reg1 has bits 47..24 */
1116: /* reg2 has bits 23..0 */
1117:
1.1.1.11 root 1118: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2)
1.1.1.6 root 1119: {
1120: Uint32 scaling, value_e, value_u;
1.1.1.4 root 1121:
1.1.1.6 root 1122: /* Initialize SR register */
1123: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E) | (1<<DSP_SR_U) | (1<<DSP_SR_N) | (1<<DSP_SR_Z));
1.1.1.4 root 1124:
1.1.1.6 root 1125: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
1.1 root 1126: switch(scaling) {
1127: case 0:
1.1.1.6 root 1128: /* Extension Bit (E) */
1129: value_e = (reg0<<1) + (reg1>>23);
1130: if ((value_e != 0) && (value_e != BITMASK(9)))
1131: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1132:
1133: /* Unnormalized bit (U) */
1.1.1.11 root 1134: if ((reg1 & 0xc00000) == 0 || (reg1 & 0xc00000) == 0xc00000)
1.1.1.6 root 1135: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1136: break;
1137: case 1:
1.1.1.6 root 1138: /* Extension Bit (E) */
1139: if ((reg0 != 0) && (reg0 != BITMASK(8)))
1140: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1141:
1142: /* Unnormalized bit (U) */
1143: value_u = ((reg0<<1) + (reg1>>23)) & 3;
1.1.1.11 root 1144: if (value_u == 0 || value_u == 3)
1.1.1.6 root 1145: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1146: break;
1147: case 2:
1.1.1.6 root 1148: /* Extension Bit (E) */
1149: value_e = (reg0<<2) + (reg1>>22);
1150: if ((value_e != 0) && (value_e != BITMASK(10)))
1151: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1152:
1153: /* Unnormalized bit (U) */
1.1.1.11 root 1154: if ((reg1 & 0x600000) == 0 || (reg1 & 0x600000) == 0x600000)
1.1.1.6 root 1155: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1156: break;
1157: default:
1158: return;
1159: break;
1160: }
1161:
1.1.1.6 root 1162: /* Zero Flag (Z) */
1163: if ((reg1 == 0) && (reg2 == 0) && (reg0 == 0))
1164: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_Z;
1.1.1.4 root 1165:
1.1.1.6 root 1166: /* Negative Flag (N) */
1167: dsp_core.registers[DSP_REG_SR] |= (reg0>>4) & 0x8;
1.1 root 1168: }
1169:
1170: /**********************************
1171: * Read/Write memory functions
1172: **********************************/
1173:
1.1.1.2 root 1174: static Uint32 read_memory_disasm(int space, Uint16 address)
1.1 root 1175: {
1.1.1.4 root 1176: /* Internal RAM ? */
1177: if (address<0x100) {
1.1.1.6 root 1178: return dsp_core.ramint[space][address] & BITMASK(24);
1.1.1.4 root 1179: }
1.1 root 1180:
1.1.1.4 root 1181: if (space==DSP_SPACE_P) {
1182: return read_memory_p(address);
1.1 root 1183: }
1184:
1.1.1.4 root 1185: /* Internal ROM? */
1.1.1.6 root 1186: if ((dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) &&
1.1.1.4 root 1187: (address<0x200)) {
1.1.1.6 root 1188: return dsp_core.rom[space][address] & BITMASK(24);
1.1.1.4 root 1189: }
1190:
1191: /* Peripheral address ? */
1192: if (address >= 0xffc0) {
1.1.1.6 root 1193: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_HOST_HTX)) {
1194: return dsp_core.dsp_host_htx;
1.1.1.4 root 1195: }
1196: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_SSI_TX)) {
1.1.1.6 root 1197: return dsp_core.ssi.transmit_value;
1.1.1.4 root 1198: }
1.1.1.6 root 1199: return dsp_core.periph[space][address-0xffc0] & BITMASK(24);
1.1.1.4 root 1200: }
1201:
1202: /* Falcon: External RAM, map X to upper 16K of matching space in Y,P */
1203: address &= (DSP_RAMSIZE>>1) - 1;
1204: if (space == DSP_SPACE_X) {
1205: address += DSP_RAMSIZE>>1;
1206: }
1207:
1208: /* Falcon: External RAM, finally map X,Y to P */
1.1.1.6 root 1209: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1.1 root 1210: }
1211:
1.1.1.4 root 1212: static inline Uint32 read_memory_p(Uint16 address)
1213: {
1214: /* Internal RAM ? */
1.1.1.7 root 1215: if (address < 0x200) {
1.1.1.6 root 1216: return dsp_core.ramint[DSP_SPACE_P][address] & BITMASK(24);
1.1.1.4 root 1217: }
1218:
1.1.1.9 root 1219: /* Access to the external P memory */
1220: access_to_ext_memory |= 1 << EXT_P_MEMORY;
1.1.1.7 root 1221:
1.1.1.4 root 1222: /* External RAM, mask address to available ram size */
1.1.1.6 root 1223: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1.1.1.4 root 1224: }
1225:
1.1.1.2 root 1226: static Uint32 read_memory(int space, Uint16 address)
1.1 root 1227: {
1.1.1.4 root 1228: Uint32 value;
1.1 root 1229:
1.1.1.4 root 1230: /* Internal RAM ? */
1231: if (address < 0x100) {
1.1.1.6 root 1232: return dsp_core.ramint[space][address] & BITMASK(24);
1.1.1.4 root 1233: }
1.1 root 1234:
1.1.1.4 root 1235: if (space == DSP_SPACE_P) {
1236: return read_memory_p(address);
1237: }
1238:
1239: /* Internal ROM ? */
1240: if (address < 0x200) {
1.1.1.6 root 1241: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1242: return dsp_core.rom[space][address] & BITMASK(24);
1.1.1.4 root 1243: }
1244: }
1245:
1246: /* Peripheral address ? */
1247: if (address >= 0xffc0) {
1.1.1.6 root 1248: value = dsp_core.periph[space][address-0xffc0] & BITMASK(24);
1.1.1.4 root 1249: if (space == DSP_SPACE_X) {
1250: if (address == 0xffc0+DSP_HOST_HRX) {
1.1.1.6 root 1251: value = dsp_core.dsp_host_rtx;
1252: dsp_core_hostport_dspread();
1.1.1.11 root 1253: }
1.1.1.4 root 1254: else if (address == 0xffc0+DSP_SSI_RX) {
1.1.1.6 root 1255: value = dsp_core_ssi_readRX();
1.1 root 1256: }
1.1.1.4 root 1257: }
1258: return value;
1.1 root 1259: }
1260:
1.1.1.9 root 1261: /* Falcon: External X or Y RAM access */
1.1.1.4 root 1262: address &= (DSP_RAMSIZE>>1) - 1;
1263:
1264: if (space == DSP_SPACE_X) {
1.1.1.9 root 1265: /* Map X to upper 16K of matching space in Y,P */
1.1.1.4 root 1266: address += DSP_RAMSIZE>>1;
1.1.1.9 root 1267:
1268: /* Set one access to the X external memory */
1269: access_to_ext_memory |= 1 << EXT_X_MEMORY;
1270: }
1271: else {
1272: /* Access to the Y external memory */
1273: access_to_ext_memory |= 1 << EXT_Y_MEMORY;
1.1.1.4 root 1274: }
1275:
1.1.1.9 root 1276:
1.1.1.4 root 1277: /* Falcon: External RAM, finally map X,Y to P */
1.1.1.6 root 1278: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1279: }
1280:
1281: static inline void write_memory(int space, Uint16 address, Uint32 value)
1282: {
1.1.1.12 root 1283: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM))
1.1.1.6 root 1284: write_memory_disasm(space, address, value);
1.1.1.11 root 1285: else
1.1.1.6 root 1286: write_memory_raw(space, address, value);
1.1 root 1287: }
1288:
1.1.1.4 root 1289: static void write_memory_raw(int space, Uint16 address, Uint32 value)
1.1 root 1290: {
1291: value &= BITMASK(24);
1292:
1.1.1.4 root 1293: /* Peripheral address ? */
1294: if (address >= 0xffc0) {
1295: if (space == DSP_SPACE_X) {
1296: switch(address-0xffc0) {
1297: case DSP_HOST_HTX:
1.1.1.6 root 1298: dsp_core.dsp_host_htx = value;
1299: dsp_core_hostport_dspwrite();
1.1.1.4 root 1300: break;
1301: case DSP_HOST_HCR:
1.1.1.13 root 1302: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] = value & 0x1f;
1.1.1.4 root 1303: /* Set HF3 and HF2 accordingly on the host side */
1.1.1.6 root 1304: dsp_core.hostport[CPU_HOST_ISR] &=
1.1.1.4 root 1305: BITMASK(8)-((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1.1.1.6 root 1306: dsp_core.hostport[CPU_HOST_ISR] |=
1307: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] & ((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1.1.1.4 root 1308: break;
1309: case DSP_HOST_HSR:
1310: /* Read only */
1311: break;
1312: case DSP_SSI_CRA:
1313: case DSP_SSI_CRB:
1.1.1.6 root 1314: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1315: dsp_core_ssi_configure(address-0xffc0, value);
1.1.1.4 root 1316: break;
1317: case DSP_SSI_TSR:
1.1.1.6 root 1318: dsp_core_ssi_writeTSR();
1.1.1.4 root 1319: break;
1320: case DSP_SSI_TX:
1.1.1.6 root 1321: dsp_core_ssi_writeTX(value);
1.1.1.4 root 1322: break;
1.1.1.5 root 1323: case DSP_IPR:
1.1.1.6 root 1324: dsp_core.periph[DSP_SPACE_X][DSP_IPR] = value;
1.1.1.5 root 1325: dsp_setInterruptIPL(value);
1326: break;
1327: case DSP_PCD:
1.1.1.6 root 1328: dsp_core.periph[DSP_SPACE_X][DSP_PCD] = value;
1329: dsp_core_setPortCDataRegister(value);
1.1.1.5 root 1330: break;
1.1.1.4 root 1331: default:
1.1.1.6 root 1332: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1.1.1.4 root 1333: break;
1.1 root 1334: }
1.1.1.4 root 1335: return;
1.1.1.11 root 1336: }
1.1.1.4 root 1337: else if (space == DSP_SPACE_Y) {
1.1.1.6 root 1338: dsp_core.periph[DSP_SPACE_Y][address-0xffc0] = value;
1.1.1.4 root 1339: return;
1340: }
1341: }
1.1.1.11 root 1342:
1.1.1.4 root 1343: /* Internal RAM ? */
1344: if (address < 0x100) {
1.1.1.6 root 1345: dsp_core.ramint[space][address] = value;
1.1.1.4 root 1346: return;
1347: }
1.1.1.2 root 1348:
1.1.1.4 root 1349: /* Internal ROM ? */
1350: if (address < 0x200) {
1351: if (space != DSP_SPACE_P) {
1.1.1.6 root 1352: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1.1.1.2 root 1353: /* Can not write to ROM space */
1.1 root 1354: return;
1355: }
1.1.1.4 root 1356: }
1357: else {
1358: /* Space P RAM */
1.1.1.6 root 1359: dsp_core.ramint[DSP_SPACE_P][address] = value;
1.1.1.4 root 1360: return;
1361: }
1.1 root 1362: }
1363:
1.1.1.9 root 1364: /* Access to X, Y or P external RAM */
1.1.1.4 root 1365:
1.1.1.9 root 1366: if (space == DSP_SPACE_P) {
1367: /* Access to the P external RAM */
1368: access_to_ext_memory |= 1 << EXT_P_MEMORY;
1369: }
1370: else {
1.1.1.4 root 1371: address &= (DSP_RAMSIZE>>1) - 1;
1372:
1.1.1.9 root 1373: if (space == DSP_SPACE_X) {
1374: /* Access to the X external RAM */
1375: /* map X to upper 16K of matching space in Y,P */
1376: address += DSP_RAMSIZE>>1;
1377: access_to_ext_memory |= 1;
1378: }
1379: else {
1380: /* Access to the Y external RAM */
1381: access_to_ext_memory |= 1 << EXT_Y_MEMORY;
1382: }
1.1.1.4 root 1383: }
1384:
1385: /* Falcon: External RAM, map X,Y to P */
1.1.1.6 root 1386: dsp_core.ramext[address & (DSP_RAMSIZE-1)] = value;
1.1.1.2 root 1387: }
1388:
1.1.1.4 root 1389: static void write_memory_disasm(int space, Uint16 address, Uint32 value)
1.1.1.2 root 1390: {
1.1.1.4 root 1391: Uint32 oldvalue, curvalue;
1392: Uint8 space_c = 'p';
1393:
1.1.1.2 root 1394: value &= BITMASK(24);
1.1.1.6 root 1395: oldvalue = read_memory_disasm(space, address);
1.1.1.2 root 1396:
1397: write_memory_raw(space,address,value);
1398:
1.1 root 1399: switch(space) {
1400: case DSP_SPACE_X:
1.1.1.4 root 1401: space_c = 'x';
1.1 root 1402: break;
1403: case DSP_SPACE_Y:
1.1.1.4 root 1404: space_c = 'y';
1405: break;
1406: default:
1.1 root 1407: break;
1408: }
1.1.1.4 root 1409:
1.1.1.6 root 1410: curvalue = read_memory_disasm(space, address);
1.1.1.5 root 1411: sprintf(str_disasm_memory[disasm_memory_ptr],"Mem: %c:0x%04x 0x%06x -> 0x%06x", space_c, address, oldvalue, curvalue);
1412: disasm_memory_ptr ++;
1.1 root 1413: }
1414:
1.1.1.4 root 1415: static void dsp_write_reg(Uint32 numreg, Uint32 value)
1416: {
1.1.1.5 root 1417: Uint32 stack_error;
1.1.1.4 root 1418:
1.1.1.7 root 1419: switch (numreg) {
1420: case DSP_REG_A:
1421: dsp_core.registers[DSP_REG_A0] = 0;
1.1.1.11 root 1422: dsp_core.registers[DSP_REG_A1] = value & BITMASK(24);
1.1.1.7 root 1423: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
1424: break;
1425: case DSP_REG_B:
1426: dsp_core.registers[DSP_REG_B0] = 0;
1.1.1.11 root 1427: dsp_core.registers[DSP_REG_B1] = value & BITMASK(24);
1.1.1.7 root 1428: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
1429: break;
1.1.1.11 root 1430: case DSP_REG_R0:
1431: case DSP_REG_R1:
1432: case DSP_REG_R2:
1433: case DSP_REG_R3:
1434: case DSP_REG_R4:
1435: case DSP_REG_R5:
1436: case DSP_REG_R6:
1437: case DSP_REG_R7:
1438: case DSP_REG_N0:
1439: case DSP_REG_N1:
1440: case DSP_REG_N2:
1441: case DSP_REG_N3:
1442: case DSP_REG_N4:
1443: case DSP_REG_N5:
1444: case DSP_REG_N6:
1445: case DSP_REG_N7:
1446: case DSP_REG_M0:
1447: case DSP_REG_M1:
1448: case DSP_REG_M2:
1449: case DSP_REG_M3:
1450: case DSP_REG_M4:
1451: case DSP_REG_M5:
1452: case DSP_REG_M6:
1453: case DSP_REG_M7:
1454: dsp_core.registers[numreg] = value & BITMASK(16);
1455: break;
1.1.1.7 root 1456: case DSP_REG_OMR:
1457: dsp_core.registers[DSP_REG_OMR] = value & 0xc7;
1458: break;
1459: case DSP_REG_SR:
1460: dsp_core.registers[DSP_REG_SR] = value & 0xaf7f;
1461: break;
1462: case DSP_REG_SP:
1.1.1.8 root 1463: stack_error = dsp_core.registers[DSP_REG_SP] & (3<<DSP_SP_SE);
1464: if ((stack_error==0) && (value & (3<<DSP_SP_SE))) {
1465: /* Stack underflow or overflow detected, raise interrupt */
1.1.1.7 root 1466: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.9 root 1467: dsp_core.registers[DSP_REG_SP] = value & (3<<DSP_SP_SE);
1.1.1.7 root 1468: if (!isDsp_in_disasm_mode)
1.1.1.8 root 1469: fprintf(stderr,"Dsp: Stack Overflow or Underflow\n");
1.1.1.10 root 1470: if (ExceptionDebugMask & EXCEPT_DSP)
1.1.1.9 root 1471: DebugUI(REASON_DSP_EXCEPTION);
1.1.1.7 root 1472: }
1.1.1.8 root 1473: else
1.1.1.11 root 1474: dsp_core.registers[DSP_REG_SP] = value & BITMASK(6);
1.1.1.7 root 1475: dsp_compute_ssh_ssl();
1476: break;
1477: case DSP_REG_SSH:
1478: dsp_stack_push(value, 0, 1);
1479: break;
1480: case DSP_REG_SSL:
1481: numreg = dsp_core.registers[DSP_REG_SP] & BITMASK(4);
1482: if (numreg == 0) {
1483: value = 0;
1484: }
1485: dsp_core.stack[1][numreg] = value & BITMASK(16);
1486: dsp_core.registers[DSP_REG_SSL] = value & BITMASK(16);
1487: break;
1488: default:
1.1.1.11 root 1489: dsp_core.registers[numreg] = value;
1.1.1.7 root 1490: dsp_core.registers[numreg] &= BITMASK(registers_mask[numreg]);
1491: break;
1.1.1.4 root 1492: }
1493: }
1494:
1.1 root 1495: /**********************************
1496: * Stack push/pop
1497: **********************************/
1498:
1.1.1.4 root 1499: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly)
1.1 root 1500: {
1.1.1.4 root 1501: Uint32 stack_error, underflow, stack;
1502:
1.1.1.6 root 1503: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1504: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1505: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) + 1;
1.1.1.4 root 1506:
1507:
1508: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1.1 root 1509: /* Stack full, raise interrupt */
1.1.1.5 root 1510: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.6 root 1511: if (!isDsp_in_disasm_mode)
1512: fprintf(stderr,"Dsp: Stack Overflow\n");
1.1.1.10 root 1513: if (ExceptionDebugMask & EXCEPT_DSP)
1.1.1.9 root 1514: DebugUI(REASON_DSP_EXCEPTION);
1.1 root 1515: }
1.1.1.11 root 1516:
1.1.1.6 root 1517: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1.1.1.4 root 1518: stack &= BITMASK(4);
1.1 root 1519:
1.1.1.4 root 1520: if (stack) {
1521: /* SSH part */
1.1.1.6 root 1522: dsp_core.stack[0][stack] = curpc & BITMASK(16);
1.1.1.4 root 1523: /* SSL part, if instruction is not like "MOVEC xx, SSH" */
1524: if (sshOnly == 0) {
1.1.1.6 root 1525: dsp_core.stack[1][stack] = cursr & BITMASK(16);
1.1.1.4 root 1526: }
1527: } else {
1.1.1.6 root 1528: dsp_core.stack[0][0] = 0;
1529: dsp_core.stack[1][0] = 0;
1.1.1.4 root 1530: }
1.1 root 1531:
1.1.1.4 root 1532: /* Update SSH and SSL registers */
1.1.1.6 root 1533: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1534: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1 root 1535: }
1536:
1.1.1.2 root 1537: static void dsp_stack_pop(Uint32 *newpc, Uint32 *newsr)
1.1 root 1538: {
1.1.1.4 root 1539: Uint32 stack_error, underflow, stack;
1540:
1.1.1.6 root 1541: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1542: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1543: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) - 1;
1.1.1.4 root 1544:
1545: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1546: /* Stack empty*/
1.1.1.5 root 1547: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.6 root 1548: if (!isDsp_in_disasm_mode)
1549: fprintf(stderr,"Dsp: Stack underflow\n");
1.1.1.10 root 1550: if (ExceptionDebugMask & EXCEPT_DSP)
1.1.1.9 root 1551: DebugUI(REASON_DSP_EXCEPTION);
1.1 root 1552: }
1553:
1.1.1.6 root 1554: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1.1.1.4 root 1555: stack &= BITMASK(4);
1.1.1.6 root 1556: *newpc = dsp_core.registers[DSP_REG_SSH];
1557: *newsr = dsp_core.registers[DSP_REG_SSL];
1.1.1.4 root 1558:
1.1.1.6 root 1559: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1560: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1.1.4 root 1561: }
1562:
1563: static void dsp_compute_ssh_ssl(void)
1564: {
1565: Uint32 stack;
1.1 root 1566:
1.1.1.6 root 1567: stack = dsp_core.registers[DSP_REG_SP];
1.1.1.4 root 1568: stack &= BITMASK(4);
1.1.1.6 root 1569: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1570: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1 root 1571: }
1572:
1573: /**********************************
1574: * Effective address calculation
1575: **********************************/
1576:
1.1.1.2 root 1577: static void dsp_update_rn(Uint32 numreg, Sint16 modifier)
1.1 root 1578: {
1.1.1.12 root 1579: Uint32 value;
1.1.1.2 root 1580: Uint16 m_reg;
1.1 root 1581:
1.1.1.6 root 1582: m_reg = (Uint16) dsp_core.registers[DSP_REG_M0+numreg];
1.1.1.7 root 1583: if (m_reg == 65535) {
1584: /* Linear addressing mode */
1.1.1.12 root 1585: value = dsp_core.registers[DSP_REG_R0+numreg]|0x10000;
1.1.1.7 root 1586: value += modifier;
1.1.1.12 root 1587: dsp_core.registers[DSP_REG_R0+numreg] = value & BITMASK(16);
1.1.1.7 root 1588: } else if (m_reg == 0) {
1.1 root 1589: /* Bit reversed carry update */
1590: dsp_update_rn_bitreverse(numreg);
1.1.1.4 root 1591: } else if (m_reg<=32767) {
1.1 root 1592: /* Modulo update */
1593: dsp_update_rn_modulo(numreg, modifier);
1594: } else {
1595: /* Undefined */
1596: }
1597: }
1598:
1.1.1.2 root 1599: static void dsp_update_rn_bitreverse(Uint32 numreg)
1.1 root 1600: {
1601: int revbits, i;
1.1.1.2 root 1602: Uint32 value, r_reg;
1.1 root 1603:
1604: /* Check how many bits to reverse */
1.1.1.6 root 1605: value = dsp_core.registers[DSP_REG_N0+numreg];
1.1 root 1606: for (revbits=0;revbits<16;revbits++) {
1607: if (value & (1<<revbits)) {
1608: break;
1609: }
1.1.1.11 root 1610: }
1.1 root 1611: revbits++;
1.1.1.11 root 1612:
1.1 root 1613: /* Reverse Rn bits */
1.1.1.6 root 1614: r_reg = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1615: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1616: for (i=0;i<revbits;i++) {
1617: if (r_reg & (1<<i)) {
1618: value |= 1<<(revbits-i-1);
1619: }
1620: }
1621:
1622: /* Increment */
1623: value++;
1624: value &= BITMASK(revbits);
1625:
1626: /* Reverse Rn bits */
1627: r_reg &= (BITMASK(16)-BITMASK(revbits));
1628: r_reg |= value;
1629:
1630: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1631: for (i=0;i<revbits;i++) {
1632: if (r_reg & (1<<i)) {
1633: value |= 1<<(revbits-i-1);
1634: }
1635: }
1636:
1.1.1.6 root 1637: dsp_core.registers[DSP_REG_R0+numreg] = value;
1.1 root 1638: }
1639:
1.1.1.2 root 1640: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier)
1.1 root 1641: {
1.1.1.12 root 1642: Uint16 bufsize, bufmask, modulo, abs_modifier;
1643: Uint32 r_reg, lobound, hibound;
1.1 root 1644:
1.1.1.12 root 1645: r_reg = dsp_core.registers[DSP_REG_R0+numreg]|0x10000;
1.1.1.6 root 1646: modulo = dsp_core.registers[DSP_REG_M0+numreg]+1;
1.1.1.12 root 1647:
1648:
1.1 root 1649: bufsize = 1;
1650: while (bufsize < modulo) {
1651: bufsize <<= 1;
1652: }
1.1.1.12 root 1653: bufmask = bufsize - 1;
1.1.1.11 root 1654:
1.1.1.12 root 1655:
1656: lobound = r_reg - (r_reg&bufmask);
1.1.1.2 root 1657: hibound = lobound + modulo - 1;
1.1 root 1658:
1.1.1.4 root 1659:
1.1.1.12 root 1660: if (modifier<0) {
1661: abs_modifier = -modifier;
1662: } else {
1663: abs_modifier = modifier;
1.1.1.2 root 1664: }
1.1.1.4 root 1665:
1666:
1.1.1.12 root 1667: if (abs_modifier>modulo) {
1668: if (abs_modifier&bufmask) {
1669: fprintf(stderr,"Dsp: Modulo addressing result unpredictable\n");
1670: } else {
1671: r_reg += modifier;
1672: }
1673: } else {
1674: r_reg += modifier;
1675:
1676:
1.1.1.4 root 1677: if (r_reg>hibound) {
1678: r_reg -= modulo;
1679: } else if (r_reg<lobound) {
1680: r_reg += modulo;
1.1.1.11 root 1681: }
1.1 root 1682: }
1683:
1.1.1.12 root 1684: dsp_core.registers[DSP_REG_R0+numreg] = r_reg & BITMASK(16);
1.1 root 1685: }
1686:
1.1.1.2 root 1687: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr)
1.1 root 1688: {
1.1.1.2 root 1689: Uint32 value, numreg, curreg;
1.1 root 1690:
1691: value = (ea_mode >> 3) & BITMASK(3);
1692: numreg = ea_mode & BITMASK(3);
1693: switch (value) {
1694: case 0:
1695: /* (Rx)-Nx */
1.1.1.6 root 1696: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1697: dsp_update_rn(numreg, -dsp_core.registers[DSP_REG_N0+numreg]);
1.1 root 1698: break;
1699: case 1:
1700: /* (Rx)+Nx */
1.1.1.6 root 1701: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1702: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1.1 root 1703: break;
1704: case 2:
1705: /* (Rx)- */
1.1.1.6 root 1706: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1707: dsp_update_rn(numreg, -1);
1708: break;
1709: case 3:
1710: /* (Rx)+ */
1.1.1.6 root 1711: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1.1.12 root 1712: dsp_update_rn(numreg, 1);
1.1 root 1713: break;
1714: case 4:
1715: /* (Rx) */
1.1.1.6 root 1716: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1717: break;
1718: case 5:
1719: /* (Rx+Nx) */
1.1.1.6 root 1720: dsp_core.instr_cycle += 2;
1721: curreg = dsp_core.registers[DSP_REG_R0+numreg];
1722: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1723: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1724: dsp_core.registers[DSP_REG_R0+numreg] = curreg;
1.1 root 1725: break;
1726: case 6:
1727: /* aa */
1.1.1.6 root 1728: dsp_core.instr_cycle += 2;
1729: *dst_addr = read_memory_p(dsp_core.pc+1);
1.1 root 1730: cur_inst_len++;
1731: if (numreg != 0) {
1732: return 1; /* immediate value */
1733: }
1734: break;
1735: case 7:
1736: /* -(Rx) */
1.1.1.6 root 1737: dsp_core.instr_cycle += 2;
1.1 root 1738: dsp_update_rn(numreg, -1);
1.1.1.6 root 1739: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1740: break;
1741: }
1742: /* address */
1743: return 0;
1744: }
1745:
1746: /**********************************
1747: * Condition code test
1748: **********************************/
1749:
1.1.1.2 root 1750: static int dsp_calc_cc(Uint32 cc_code)
1.1 root 1751: {
1.1.1.4 root 1752: Uint16 value1, value2, value3;
1.1 root 1753:
1.1.1.4 root 1754: switch (cc_code) {
1755: case 0: /* CC (HS) */
1.1.1.6 root 1756: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1.1.1.4 root 1757: return (value1==0);
1758: case 1: /* GE */
1.1.1.6 root 1759: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1760: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1.1.1.4 root 1761: return ((value1 ^ value2) == 0);
1762: case 2: /* NE */
1.1.1.6 root 1763: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_Z);
1.1.1.4 root 1764: return (value1==0);
1765: case 3: /* PL */
1.1.1.6 root 1766: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_N);
1.1.1.4 root 1767: return (value1==0);
1768: case 4: /* NN */
1.1.1.6 root 1769: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1770: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1771: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1.1.1.4 root 1772: return ((value1 | (value2 & value3)) == 0);
1773: case 5: /* EC */
1.1.1.6 root 1774: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_E);
1.1.1.4 root 1775: return (value1==0);
1776: case 6: /* LC */
1.1.1.6 root 1777: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_L);
1.1.1.4 root 1778: return (value1==0);
1.1.1.11 root 1779: case 7: /* GT */
1.1.1.6 root 1780: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1781: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1782: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1783: return ((value3 | (value1 ^ value2)) == 0);
1784: case 8: /* CS (LO) */
1.1.1.6 root 1785: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1.1.1.4 root 1786: return (value1==1);
1787: case 9: /* LT */
1.1.1.6 root 1788: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1789: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1.1.1.4 root 1790: return ((value1 ^ value2) == 1);
1791: case 10: /* EQ */
1.1.1.6 root 1792: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1793: return (value1==1);
1794: case 11: /* MI */
1.1.1.6 root 1795: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1.1.1.4 root 1796: return (value1==1);
1797: case 12: /* NR */
1.1.1.6 root 1798: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1799: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1800: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1.1.1.4 root 1801: return ((value1 | (value2 & value3)) == 1);
1802: case 13: /* ES */
1.1.1.6 root 1803: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_E) & 1;
1.1.1.4 root 1804: return (value1==1);
1805: case 14: /* LS */
1.1.1.6 root 1806: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_L) & 1;
1.1.1.4 root 1807: return (value1==1);
1808: case 15: /* LE */
1.1.1.6 root 1809: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1810: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1811: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1812: return ((value3 | (value1 ^ value2)) == 1);
1813: }
1814: return 0;
1.1 root 1815: }
1816:
1817: /**********************************
1818: * Highbyte opcodes dispatchers
1819: **********************************/
1820:
1821: static void opcode8h_0(void)
1822: {
1.1.1.4 root 1823: switch(cur_inst) {
1824: case 0x000000:
1825: dsp_nop();
1.1 root 1826: break;
1.1.1.4 root 1827: case 0x000004:
1828: dsp_rti();
1.1 root 1829: break;
1.1.1.4 root 1830: case 0x000005:
1831: dsp_illegal();
1.1 root 1832: break;
1.1.1.4 root 1833: case 0x000006:
1834: dsp_swi();
1835: break;
1836: case 0x00000c:
1837: dsp_rts();
1838: break;
1839: case 0x000084:
1840: dsp_reset();
1841: break;
1842: case 0x000086:
1843: dsp_wait();
1844: break;
1845: case 0x000087:
1846: dsp_stop();
1847: break;
1848: case 0x00008c:
1849: dsp_enddo();
1.1 root 1850: break;
1.1.1.10 root 1851: default:
1852: dsp_undefined();
1853: break;
1.1 root 1854: }
1855: }
1856:
1857: /**********************************
1858: * Non-parallel moves instructions
1859: **********************************/
1860:
1861: static void dsp_undefined(void)
1862: {
1.1.1.6 root 1863: if (isDsp_in_disasm_mode == false) {
1864: cur_inst_len = 0;
1.1.1.7 root 1865: /* Add some artificial CPU cycles to avoid being stuck in an infinite loop */
1.1.1.6 root 1866: dsp_core.instr_cycle += 100;
1.1.1.13 root 1867:
1868: /* Rate limit identical messages. Required to make
1869: * "Terrorize your soul" demo run at usable speed
1870: */
1871: dsp_error.count++;
1872: if (cur_inst != dsp_error.inst || dsp_core.pc != dsp_error.pc ||
1873: dsp_error.count >= dsp_error.limit) {
1874: dsp_error.inst = cur_inst;
1875: dsp_error.pc = dsp_core.pc;
1876: fprintf(stderr, "Dsp: 0x%04hx: 0x%06x Illegal instruction (%dx times)\n",
1877: dsp_error.pc, dsp_error.inst, dsp_error.count);
1878: if (dsp_error.count >= dsp_error.limit) {
1879: /* next message after 2x more hits */
1880: dsp_error.limit *= 2;
1881: } else {
1882: dsp_error.limit = 1;
1883: }
1884: dsp_error.count = 0;
1885: }
1886: } else {
1.1.1.6 root 1887: cur_inst_len = 1;
1888: dsp_core.instr_cycle = 0;
1889: }
1.1.1.10 root 1890: if (ExceptionDebugMask & EXCEPT_DSP) {
1.1.1.9 root 1891: DebugUI(REASON_DSP_EXCEPTION);
1892: }
1.1 root 1893: }
1894:
1895: static void dsp_andi(void)
1896: {
1.1.1.2 root 1897: Uint32 regnum, value;
1.1 root 1898:
1899: value = (cur_inst >> 8) & BITMASK(8);
1900: regnum = cur_inst & BITMASK(2);
1901: switch(regnum) {
1902: case 0:
1903: /* mr */
1.1.1.6 root 1904: dsp_core.registers[DSP_REG_SR] &= (value<<8)|BITMASK(8);
1.1 root 1905: break;
1906: case 1:
1907: /* ccr */
1.1.1.6 root 1908: dsp_core.registers[DSP_REG_SR] &= (BITMASK(8)<<8)|value;
1.1 root 1909: break;
1910: case 2:
1911: /* omr */
1.1.1.6 root 1912: dsp_core.registers[DSP_REG_OMR] &= value;
1.1 root 1913: break;
1914: }
1915: }
1916:
1.1.1.4 root 1917: static void dsp_bchg_aa(void)
1.1 root 1918: {
1.1.1.4 root 1919: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 1920:
1.1 root 1921: memspace = (cur_inst>>6) & 1;
1922: value = (cur_inst>>8) & BITMASK(6);
1923: numbit = cur_inst & BITMASK(5);
1924:
1.1.1.4 root 1925: addr = value;
1926: value = read_memory(memspace, addr);
1927: newcarry = (value>>numbit) & 1;
1928: if (newcarry) {
1929: value -= (1<<numbit);
1930: } else {
1931: value += (1<<numbit);
1.1 root 1932: }
1.1.1.4 root 1933: write_memory(memspace, addr, value);
1.1 root 1934:
1935: /* Set carry */
1.1.1.6 root 1936: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1937: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1938:
1.1.1.6 root 1939: dsp_core.instr_cycle += 2;
1.1 root 1940: }
1941:
1.1.1.4 root 1942: static void dsp_bchg_ea(void)
1.1 root 1943: {
1.1.1.4 root 1944: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 1945:
1.1 root 1946: memspace = (cur_inst>>6) & 1;
1947: value = (cur_inst>>8) & BITMASK(6);
1948: numbit = cur_inst & BITMASK(5);
1949:
1.1.1.4 root 1950: dsp_calc_ea(value, &addr);
1951: value = read_memory(memspace, addr);
1952: newcarry = (value>>numbit) & 1;
1953: if (newcarry) {
1954: value -= (1<<numbit);
1955: } else {
1956: value += (1<<numbit);
1.1 root 1957: }
1.1.1.4 root 1958: write_memory(memspace, addr, value);
1.1 root 1959:
1960: /* Set carry */
1.1.1.6 root 1961: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1962: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1963:
1.1.1.6 root 1964: dsp_core.instr_cycle += 2;
1.1 root 1965: }
1966:
1.1.1.4 root 1967: static void dsp_bchg_pp(void)
1.1 root 1968: {
1.1.1.4 root 1969: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 1970:
1.1 root 1971: memspace = (cur_inst>>6) & 1;
1972: value = (cur_inst>>8) & BITMASK(6);
1973: numbit = cur_inst & BITMASK(5);
1974:
1.1.1.4 root 1975: addr = 0xffc0 + value;
1976: value = read_memory(memspace, addr);
1977: newcarry = (value>>numbit) & 1;
1978: if (newcarry) {
1979: value -= (1<<numbit);
1980: } else {
1981: value += (1<<numbit);
1.1 root 1982: }
1.1.1.4 root 1983: write_memory(memspace, addr, value);
1.1 root 1984:
1985: /* Set carry */
1.1.1.6 root 1986: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1987: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1988:
1.1.1.6 root 1989: dsp_core.instr_cycle += 2;
1.1 root 1990: }
1991:
1.1.1.4 root 1992: static void dsp_bchg_reg(void)
1.1 root 1993: {
1.1.1.4 root 1994: Uint32 value, numreg, newcarry, numbit;
1.1.1.11 root 1995:
1.1.1.4 root 1996: numreg = (cur_inst>>8) & BITMASK(6);
1.1 root 1997: numbit = cur_inst & BITMASK(5);
1998:
1.1.1.4 root 1999: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2000: dsp_pm_read_accu24(numreg, &value);
2001: } else {
1.1.1.6 root 2002: value = dsp_core.registers[numreg];
1.1 root 2003: }
2004:
1.1.1.4 root 2005: newcarry = (value>>numbit) & 1;
2006: if (newcarry) {
2007: value -= (1<<numbit);
2008: } else {
2009: value += (1<<numbit);
2010: }
2011:
2012: dsp_write_reg(numreg, value);
2013:
1.1 root 2014: /* Set carry */
1.1.1.6 root 2015: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2016: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2017:
1.1.1.6 root 2018: dsp_core.instr_cycle += 2;
1.1 root 2019: }
2020:
1.1.1.4 root 2021: static void dsp_bclr_aa(void)
1.1 root 2022: {
1.1.1.4 root 2023: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2024:
1.1.1.4 root 2025: memspace = (cur_inst>>6) & 1;
2026: addr = (cur_inst>>8) & BITMASK(6);
2027: numbit = cur_inst & BITMASK(5);
1.1 root 2028:
1.1.1.4 root 2029: value = read_memory(memspace, addr);
2030: newcarry = (value>>numbit) & 1;
2031: value &= 0xffffffff-(1<<numbit);
2032: write_memory(memspace, addr, value);
1.1.1.2 root 2033:
1.1.1.4 root 2034: /* Set carry */
1.1.1.6 root 2035: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2036: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 2037:
1.1.1.6 root 2038: dsp_core.instr_cycle += 2;
1.1.1.4 root 2039: }
1.1 root 2040:
1.1.1.4 root 2041: static void dsp_bclr_ea(void)
2042: {
2043: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2044:
1.1.1.4 root 2045: memspace = (cur_inst>>6) & 1;
2046: value = (cur_inst>>8) & BITMASK(6);
2047: numbit = cur_inst & BITMASK(5);
1.1 root 2048:
1.1.1.4 root 2049: dsp_calc_ea(value, &addr);
2050: value = read_memory(memspace, addr);
2051: newcarry = (value>>numbit) & 1;
2052: value &= 0xffffffff-(1<<numbit);
2053: write_memory(memspace, addr, value);
1.1.1.2 root 2054:
1.1.1.4 root 2055: /* Set carry */
1.1.1.6 root 2056: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2057: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2058:
1.1.1.6 root 2059: dsp_core.instr_cycle += 2;
1.1 root 2060: }
2061:
1.1.1.4 root 2062: static void dsp_bclr_pp(void)
2063: {
2064: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2065:
1.1.1.4 root 2066: memspace = (cur_inst>>6) & 1;
2067: value = (cur_inst>>8) & BITMASK(6);
2068: numbit = cur_inst & BITMASK(5);
1.1.1.3 root 2069:
1.1.1.4 root 2070: addr = 0xffc0 + value;
2071: value = read_memory(memspace, addr);
2072: newcarry = (value>>numbit) & 1;
2073: value &= 0xffffffff-(1<<numbit);
2074: write_memory(memspace, addr, value);
1.1.1.3 root 2075:
1.1.1.4 root 2076: /* Set carry */
1.1.1.6 root 2077: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2078: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 2079:
1.1.1.6 root 2080: dsp_core.instr_cycle += 2;
1.1.1.4 root 2081: }
1.1 root 2082:
1.1.1.4 root 2083: static void dsp_bclr_reg(void)
2084: {
2085: Uint32 value, numreg, newcarry, numbit;
1.1.1.11 root 2086:
1.1.1.4 root 2087: numreg = (cur_inst>>8) & BITMASK(6);
2088: numbit = cur_inst & BITMASK(5);
1.1 root 2089:
1.1.1.4 root 2090: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2091: dsp_pm_read_accu24(numreg, &value);
2092: } else {
1.1.1.6 root 2093: value = dsp_core.registers[numreg];
1.1.1.4 root 2094: }
1.1 root 2095:
1.1.1.4 root 2096: newcarry = (value>>numbit) & 1;
2097: value &= 0xffffffff-(1<<numbit);
1.1 root 2098:
1.1.1.4 root 2099: dsp_write_reg(numreg, value);
2100:
2101: /* Set carry */
1.1.1.6 root 2102: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2103: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 2104:
1.1.1.6 root 2105: dsp_core.instr_cycle += 2;
1.1 root 2106: }
2107:
1.1.1.4 root 2108: static void dsp_bset_aa(void)
1.1 root 2109: {
1.1.1.4 root 2110: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2111:
1.1.1.4 root 2112: memspace = (cur_inst>>6) & 1;
2113: value = (cur_inst>>8) & BITMASK(6);
2114: numbit = cur_inst & BITMASK(5);
1.1 root 2115:
1.1.1.4 root 2116: addr = value;
2117: value = read_memory(memspace, addr);
2118: newcarry = (value>>numbit) & 1;
2119: value |= (1<<numbit);
2120: write_memory(memspace, addr, value);
2121:
2122: /* Set carry */
1.1.1.6 root 2123: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2124: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2125:
1.1.1.6 root 2126: dsp_core.instr_cycle += 2;
1.1.1.4 root 2127: }
2128:
2129: static void dsp_bset_ea(void)
2130: {
2131: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2132:
1.1.1.4 root 2133: memspace = (cur_inst>>6) & 1;
2134: value = (cur_inst>>8) & BITMASK(6);
2135: numbit = cur_inst & BITMASK(5);
2136:
2137: dsp_calc_ea(value, &addr);
2138: value = read_memory(memspace, addr);
2139: newcarry = (value>>numbit) & 1;
2140: value |= (1<<numbit);
2141: write_memory(memspace, addr, value);
2142:
2143: /* Set carry */
1.1.1.6 root 2144: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2145: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2146:
1.1.1.6 root 2147: dsp_core.instr_cycle += 2;
1.1.1.4 root 2148: }
2149:
2150: static void dsp_bset_pp(void)
2151: {
2152: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2153:
1.1.1.4 root 2154: memspace = (cur_inst>>6) & 1;
2155: value = (cur_inst>>8) & BITMASK(6);
2156: numbit = cur_inst & BITMASK(5);
2157: addr = 0xffc0 + value;
2158: value = read_memory(memspace, addr);
2159: newcarry = (value>>numbit) & 1;
2160: value |= (1<<numbit);
2161: write_memory(memspace, addr, value);
2162:
2163: /* Set carry */
1.1.1.6 root 2164: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2165: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2166:
1.1.1.6 root 2167: dsp_core.instr_cycle += 2;
1.1.1.4 root 2168: }
2169:
2170: static void dsp_bset_reg(void)
2171: {
2172: Uint32 value, numreg, newcarry, numbit;
1.1.1.11 root 2173:
1.1.1.4 root 2174: numreg = (cur_inst>>8) & BITMASK(6);
2175: numbit = cur_inst & BITMASK(5);
2176:
2177: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2178: dsp_pm_read_accu24(numreg, &value);
2179: } else {
1.1.1.6 root 2180: value = dsp_core.registers[numreg];
1.1.1.4 root 2181: }
2182:
2183: newcarry = (value>>numbit) & 1;
2184: value |= (1<<numbit);
2185:
2186: dsp_write_reg(numreg, value);
2187:
2188: /* Set carry */
1.1.1.6 root 2189: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2190: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2191:
1.1.1.6 root 2192: dsp_core.instr_cycle += 2;
1.1.1.4 root 2193: }
2194:
2195: static void dsp_btst_aa(void)
2196: {
2197: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2198:
1.1.1.4 root 2199: memspace = (cur_inst>>6) & 1;
2200: value = (cur_inst>>8) & BITMASK(6);
2201: numbit = cur_inst & BITMASK(5);
2202:
2203: addr = value;
2204: value = read_memory(memspace, addr);
2205: newcarry = (value>>numbit) & 1;
2206:
2207: /* Set carry */
1.1.1.6 root 2208: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2209: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2210:
1.1.1.6 root 2211: dsp_core.instr_cycle += 2;
1.1.1.4 root 2212: }
2213:
2214: static void dsp_btst_ea(void)
2215: {
2216: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2217:
1.1.1.4 root 2218: memspace = (cur_inst>>6) & 1;
2219: value = (cur_inst>>8) & BITMASK(6);
2220: numbit = cur_inst & BITMASK(5);
2221:
2222: dsp_calc_ea(value, &addr);
2223: value = read_memory(memspace, addr);
2224: newcarry = (value>>numbit) & 1;
2225:
2226: /* Set carry */
1.1.1.6 root 2227: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2228: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2229:
1.1.1.6 root 2230: dsp_core.instr_cycle += 2;
1.1.1.4 root 2231: }
2232:
2233: static void dsp_btst_pp(void)
2234: {
2235: Uint32 memspace, addr, value, newcarry, numbit;
1.1.1.11 root 2236:
1.1.1.4 root 2237: memspace = (cur_inst>>6) & 1;
2238: value = (cur_inst>>8) & BITMASK(6);
2239: numbit = cur_inst & BITMASK(5);
2240:
2241: addr = 0xffc0 + value;
2242: value = read_memory(memspace, addr);
2243: newcarry = (value>>numbit) & 1;
2244:
2245: /* Set carry */
1.1.1.6 root 2246: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2247: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2248:
1.1.1.6 root 2249: dsp_core.instr_cycle += 2;
1.1.1.4 root 2250: }
2251:
2252: static void dsp_btst_reg(void)
2253: {
2254: Uint32 value, numreg, newcarry, numbit;
1.1.1.11 root 2255:
1.1.1.4 root 2256: numreg = (cur_inst>>8) & BITMASK(6);
2257: numbit = cur_inst & BITMASK(5);
2258:
2259: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2260: dsp_pm_read_accu24(numreg, &value);
2261: } else {
1.1.1.6 root 2262: value = dsp_core.registers[numreg];
1.1.1.4 root 2263: }
2264:
2265: newcarry = (value>>numbit) & 1;
2266:
2267: /* Set carry */
1.1.1.6 root 2268: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2269: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2270:
1.1.1.6 root 2271: dsp_core.instr_cycle += 2;
1.1.1.4 root 2272: }
2273:
2274: static void dsp_div(void)
2275: {
2276: Uint32 srcreg, destreg, source[3], dest[3];
2277: Uint16 newsr;
2278:
2279: srcreg = DSP_REG_NULL;
2280: switch((cur_inst>>4) & BITMASK(2)) {
2281: case 0: srcreg = DSP_REG_X0; break;
2282: case 1: srcreg = DSP_REG_Y0; break;
2283: case 2: srcreg = DSP_REG_X1; break;
2284: case 3: srcreg = DSP_REG_Y1; break;
2285: }
1.1.1.7 root 2286: source[2] = 0;
2287: source[1] = dsp_core.registers[srcreg];
2288: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.4 root 2289:
1.1.1.7 root 2290: destreg = DSP_REG_A + ((cur_inst>>3) & 1);
2291: if (destreg == DSP_REG_A) {
2292: dest[0] = dsp_core.registers[DSP_REG_A2];
2293: dest[1] = dsp_core.registers[DSP_REG_A1];
2294: dest[2] = dsp_core.registers[DSP_REG_A0];
2295: }
2296: else {
2297: dest[0] = dsp_core.registers[DSP_REG_B2];
2298: dest[1] = dsp_core.registers[DSP_REG_B1];
2299: dest[2] = dsp_core.registers[DSP_REG_B0];
2300: }
1.1.1.4 root 2301:
2302: if (((dest[0]>>7) & 1) ^ ((source[1]>>23) & 1)) {
2303: /* D += S */
2304: newsr = dsp_asl56(dest);
2305: dsp_add56(source, dest);
2306: } else {
2307: /* D -= S */
2308: newsr = dsp_asl56(dest);
2309: dsp_sub56(source, dest);
2310: }
2311:
1.1.1.6 root 2312: dest[2] |= (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1.1.4 root 2313:
1.1.1.7 root 2314: if (destreg == DSP_REG_A) {
2315: dsp_core.registers[DSP_REG_A2] = dest[0];
2316: dsp_core.registers[DSP_REG_A1] = dest[1];
2317: dsp_core.registers[DSP_REG_A0] = dest[2];
2318: }
2319: else {
2320: dsp_core.registers[DSP_REG_B2] = dest[0];
2321: dsp_core.registers[DSP_REG_B1] = dest[1];
2322: dsp_core.registers[DSP_REG_B0] = dest[2];
2323: }
1.1.1.11 root 2324:
1.1.1.6 root 2325: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
2326: dsp_core.registers[DSP_REG_SR] |= (1-((dest[0]>>7) & 1))<<DSP_SR_C;
2327: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_L);
2328: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_V);
1.1.1.4 root 2329: }
2330:
2331: /*
2332: DO instruction parameter encoding
2333:
2334: xxxxxxxx 00xxxxxx 0xxxxxxx aa
2335: xxxxxxxx 01xxxxxx 0xxxxxxx ea
2336: xxxxxxxx YYxxxxxx 1xxxxxxx imm
2337: xxxxxxxx 11xxxxxx 0xxxxxxx reg
2338: */
2339:
2340: static void dsp_do_aa(void)
2341: {
2342: Uint32 memspace, addr;
2343:
2344: /* x:aa */
2345: /* y:aa */
2346:
1.1.1.6 root 2347: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2348: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2349: cur_inst_len++;
1.1.1.6 root 2350: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2351: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1 root 2352:
2353: memspace = (cur_inst>>6) & 1;
2354: addr = (cur_inst>>8) & BITMASK(6);
1.1.1.6 root 2355: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
1.1.1.4 root 2356:
1.1.1.6 root 2357: dsp_core.instr_cycle += 4;
1.1 root 2358: }
2359:
1.1.1.3 root 2360: static void dsp_do_imm(void)
1.1 root 2361: {
2362: /* #xx */
1.1.1.3 root 2363:
1.1.1.6 root 2364: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2365: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2366: cur_inst_len++;
1.1.1.6 root 2367: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2368: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2369:
1.1.1.6 root 2370: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
1.1.1.3 root 2371: + ((cur_inst & BITMASK(4))<<8);
1.1.1.4 root 2372:
1.1.1.6 root 2373: dsp_core.instr_cycle += 4;
1.1 root 2374: }
2375:
1.1.1.3 root 2376: static void dsp_do_ea(void)
1.1 root 2377: {
1.1.1.2 root 2378: Uint32 memspace, ea_mode, addr;
1.1 root 2379:
2380: /* x:ea */
2381: /* y:ea */
2382:
1.1.1.6 root 2383: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2384: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2385: cur_inst_len++;
1.1.1.6 root 2386: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2387: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2388:
1.1 root 2389: memspace = (cur_inst>>6) & 1;
2390: ea_mode = (cur_inst>>8) & BITMASK(6);
2391: dsp_calc_ea(ea_mode, &addr);
1.1.1.6 root 2392: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
1.1.1.4 root 2393:
1.1.1.6 root 2394: dsp_core.instr_cycle += 4;
1.1 root 2395: }
2396:
1.1.1.3 root 2397: static void dsp_do_reg(void)
1.1 root 2398: {
1.1.1.2 root 2399: Uint32 numreg;
1.1 root 2400:
2401: /* S */
2402:
1.1.1.6 root 2403: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2404: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2405: cur_inst_len++;
2406:
1.1 root 2407: numreg = (cur_inst>>8) & BITMASK(6);
2408: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11 root 2409: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
1.1 root 2410: } else {
1.1.1.6 root 2411: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
1.1 root 2412: }
1.1.1.6 root 2413: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.4 root 2414:
1.1.1.6 root 2415: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2416: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2417:
1.1.1.6 root 2418: dsp_core.instr_cycle += 4;
1.1 root 2419: }
2420:
2421: static void dsp_enddo(void)
2422: {
1.1.1.4 root 2423: Uint32 saved_pc, saved_sr;
1.1 root 2424:
1.1.1.4 root 2425: dsp_stack_pop(&saved_pc, &saved_sr);
1.1.1.6 root 2426: dsp_core.registers[DSP_REG_SR] &= 0x7f;
2427: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
2428: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
1.1 root 2429: }
2430:
2431: static void dsp_illegal(void)
2432: {
2433: /* Raise interrupt p:0x003e */
1.1.1.5 root 2434: dsp_add_interrupt(DSP_INTER_ILLEGAL);
1.1.1.10 root 2435: if (ExceptionDebugMask & EXCEPT_DSP) {
1.1.1.9 root 2436: DebugUI(REASON_DSP_EXCEPTION);
2437: }
1.1 root 2438: }
2439:
1.1.1.4 root 2440: static void dsp_jcc_imm(void)
1.1 root 2441: {
1.1.1.4 root 2442: Uint32 cc_code, newpc;
1.1 root 2443:
1.1.1.4 root 2444: newpc = cur_inst & BITMASK(12);
2445: cc_code=(cur_inst>>12) & BITMASK(4);
2446: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2447: dsp_core.pc = newpc;
1.1.1.4 root 2448: cur_inst_len = 0;
2449: }
2450:
1.1.1.6 root 2451: dsp_core.instr_cycle += 2;
1.1.1.4 root 2452: }
2453:
2454: static void dsp_jcc_ea(void)
2455: {
2456: Uint32 newpc, cc_code;
2457:
2458: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2459: cc_code=cur_inst & BITMASK(4);
1.1 root 2460:
2461: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2462: dsp_core.pc = newpc;
1.1 root 2463: cur_inst_len = 0;
2464: }
1.1.1.4 root 2465:
1.1.1.6 root 2466: dsp_core.instr_cycle += 2;
1.1 root 2467: }
2468:
1.1.1.4 root 2469: static void dsp_jclr_aa(void)
1.1 root 2470: {
1.1.1.4 root 2471: Uint32 memspace, addr, value, numbit, newaddr;
1.1.1.11 root 2472:
1.1 root 2473: memspace = (cur_inst>>6) & 1;
1.1.1.4 root 2474: addr = (cur_inst>>8) & BITMASK(6);
1.1 root 2475: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2476: value = read_memory(memspace, addr);
1.1.1.6 root 2477: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2478:
1.1.1.6 root 2479: dsp_core.instr_cycle += 4;
1.1 root 2480:
1.1.1.4 root 2481: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2482: dsp_core.pc = newaddr;
1.1.1.4 root 2483: cur_inst_len = 0;
2484: return;
1.1.1.11 root 2485: }
1.1.1.2 root 2486: ++cur_inst_len;
1.1.1.4 root 2487: }
2488:
2489: static void dsp_jclr_ea(void)
2490: {
2491: Uint32 memspace, addr, value, numbit, newaddr;
1.1.1.11 root 2492:
1.1.1.4 root 2493: memspace = (cur_inst>>6) & 1;
2494: value = (cur_inst>>8) & BITMASK(6);
2495: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2496: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2497:
1.1.1.4 root 2498: dsp_calc_ea(value, &addr);
2499: value = read_memory(memspace, addr);
2500:
1.1.1.6 root 2501: dsp_core.instr_cycle += 4;
1.1 root 2502:
2503: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2504: dsp_core.pc = newaddr;
1.1.1.4 root 2505: cur_inst_len = 0;
2506: return;
1.1.1.11 root 2507: }
1.1.1.4 root 2508: ++cur_inst_len;
2509: }
1.1 root 2510:
1.1.1.4 root 2511: static void dsp_jclr_pp(void)
2512: {
2513: Uint32 memspace, addr, value, numbit, newaddr;
1.1.1.11 root 2514:
1.1.1.4 root 2515: memspace = (cur_inst>>6) & 1;
2516: value = (cur_inst>>8) & BITMASK(6);
2517: numbit = cur_inst & BITMASK(5);
2518: addr = 0xffc0 + value;
2519: value = read_memory(memspace, addr);
1.1.1.6 root 2520: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2521:
1.1.1.6 root 2522: dsp_core.instr_cycle += 4;
1.1 root 2523:
1.1.1.4 root 2524: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2525: dsp_core.pc = newaddr;
1.1.1.4 root 2526: cur_inst_len = 0;
2527: return;
1.1.1.11 root 2528: }
1.1.1.4 root 2529: ++cur_inst_len;
2530: }
1.1.1.2 root 2531:
1.1.1.4 root 2532: static void dsp_jclr_reg(void)
2533: {
2534: Uint32 value, numreg, numbit, newaddr;
1.1.1.11 root 2535:
1.1.1.4 root 2536: numreg = (cur_inst>>8) & BITMASK(6);
2537: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2538: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2539:
1.1.1.4 root 2540: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2541: dsp_pm_read_accu24(numreg, &value);
2542: } else {
1.1.1.6 root 2543: value = dsp_core.registers[numreg];
1.1.1.4 root 2544: }
1.1 root 2545:
1.1.1.6 root 2546: dsp_core.instr_cycle += 4;
1.1.1.4 root 2547:
2548: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2549: dsp_core.pc = newaddr;
1.1 root 2550: cur_inst_len = 0;
2551: return;
1.1.1.11 root 2552: }
1.1.1.4 root 2553: ++cur_inst_len;
1.1 root 2554: }
2555:
1.1.1.4 root 2556: static void dsp_jmp_ea(void)
1.1 root 2557: {
1.1.1.2 root 2558: Uint32 newpc;
1.1 root 2559:
1.1.1.4 root 2560: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &newpc);
1.1 root 2561: cur_inst_len = 0;
1.1.1.6 root 2562: dsp_core.pc = newpc;
1.1 root 2563:
1.1.1.6 root 2564: dsp_core.instr_cycle += 2;
1.1.1.4 root 2565: }
2566:
2567: static void dsp_jmp_imm(void)
2568: {
2569: Uint32 newpc;
1.1 root 2570:
1.1.1.4 root 2571: newpc = cur_inst & BITMASK(12);
2572: cur_inst_len = 0;
1.1.1.6 root 2573: dsp_core.pc = newpc;
1.1.1.4 root 2574:
1.1.1.6 root 2575: dsp_core.instr_cycle += 2;
1.1 root 2576: }
2577:
1.1.1.4 root 2578: static void dsp_jscc_ea(void)
1.1 root 2579: {
1.1.1.2 root 2580: Uint32 newpc, cc_code;
1.1 root 2581:
1.1.1.4 root 2582: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2583: cc_code=cur_inst & BITMASK(4);
2584:
2585: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2586: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2587: dsp_core.pc = newpc;
1.1.1.4 root 2588: cur_inst_len = 0;
1.1.1.11 root 2589: }
1.1.1.4 root 2590:
1.1.1.6 root 2591: dsp_core.instr_cycle += 2;
1.1.1.4 root 2592: }
1.1 root 2593:
1.1.1.4 root 2594: static void dsp_jscc_imm(void)
2595: {
2596: Uint32 cc_code, newpc;
2597:
2598: newpc = cur_inst & BITMASK(12);
2599: cc_code=(cur_inst>>12) & BITMASK(4);
1.1 root 2600: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2601: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2602: dsp_core.pc = newpc;
1.1.1.4 root 2603: cur_inst_len = 0;
1.1.1.11 root 2604: }
1.1.1.4 root 2605:
1.1.1.6 root 2606: dsp_core.instr_cycle += 2;
1.1.1.4 root 2607: }
1.1 root 2608:
1.1.1.4 root 2609: static void dsp_jsclr_aa(void)
2610: {
2611: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2612:
1.1.1.4 root 2613: memspace = (cur_inst>>6) & 1;
2614: addr = (cur_inst>>8) & BITMASK(6);
2615: numbit = cur_inst & BITMASK(5);
2616: value = read_memory(memspace, addr);
1.1.1.6 root 2617: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2618:
1.1.1.6 root 2619: dsp_core.instr_cycle += 4;
1.1.1.11 root 2620:
1.1.1.4 root 2621: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2622: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2623: newpc = newaddr;
1.1.1.6 root 2624: dsp_core.pc = newpc;
1.1 root 2625: cur_inst_len = 0;
1.1.1.4 root 2626: return;
1.1.1.11 root 2627: }
1.1.1.4 root 2628: ++cur_inst_len;
1.1 root 2629: }
2630:
1.1.1.4 root 2631: static void dsp_jsclr_ea(void)
1.1 root 2632: {
1.1.1.4 root 2633: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2634:
1.1 root 2635: memspace = (cur_inst>>6) & 1;
2636: value = (cur_inst>>8) & BITMASK(6);
2637: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2638: dsp_calc_ea(value, &addr);
2639: value = read_memory(memspace, addr);
1.1.1.6 root 2640: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2641:
1.1.1.6 root 2642: dsp_core.instr_cycle += 4;
1.1.1.11 root 2643:
1.1.1.4 root 2644: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2645: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2646: newpc = newaddr;
1.1.1.6 root 2647: dsp_core.pc = newpc;
1.1.1.4 root 2648: cur_inst_len = 0;
2649: return;
1.1.1.11 root 2650: }
1.1.1.2 root 2651: ++cur_inst_len;
1.1.1.4 root 2652: }
2653:
2654: static void dsp_jsclr_pp(void)
2655: {
2656: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2657:
1.1.1.4 root 2658: memspace = (cur_inst>>6) & 1;
2659: value = (cur_inst>>8) & BITMASK(6);
2660: numbit = cur_inst & BITMASK(5);
2661: addr = 0xffc0 + value;
2662: value = read_memory(memspace, addr);
1.1.1.6 root 2663: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2664:
1.1.1.6 root 2665: dsp_core.instr_cycle += 4;
1.1.1.11 root 2666:
1.1 root 2667: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2668: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2669: newpc = newaddr;
1.1.1.6 root 2670: dsp_core.pc = newpc;
1.1.1.4 root 2671: cur_inst_len = 0;
2672: return;
1.1.1.11 root 2673: }
1.1.1.4 root 2674: ++cur_inst_len;
2675: }
2676:
2677: static void dsp_jsclr_reg(void)
2678: {
2679: Uint32 value, numreg, newpc, numbit, newaddr;
1.1.1.11 root 2680:
1.1.1.4 root 2681: numreg = (cur_inst>>8) & BITMASK(6);
2682: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2683: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2684:
1.1.1.4 root 2685: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2686: dsp_pm_read_accu24(numreg, &value);
2687: } else {
1.1.1.6 root 2688: value = dsp_core.registers[numreg];
1.1.1.4 root 2689: }
2690:
1.1.1.6 root 2691: dsp_core.instr_cycle += 4;
1.1.1.11 root 2692:
1.1.1.4 root 2693: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2694: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2695: newpc = newaddr;
1.1.1.6 root 2696: dsp_core.pc = newpc;
1.1 root 2697: cur_inst_len = 0;
1.1.1.4 root 2698: return;
1.1.1.11 root 2699: }
1.1.1.4 root 2700: ++cur_inst_len;
1.1 root 2701: }
2702:
1.1.1.4 root 2703: static void dsp_jset_aa(void)
1.1 root 2704: {
1.1.1.4 root 2705: Uint32 memspace, addr, value, numbit, newpc, newaddr;
1.1.1.11 root 2706:
1.1.1.4 root 2707: memspace = (cur_inst>>6) & 1;
2708: addr = (cur_inst>>8) & BITMASK(6);
2709: numbit = cur_inst & BITMASK(5);
2710: value = read_memory(memspace, addr);
1.1.1.6 root 2711: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2712:
1.1.1.6 root 2713: dsp_core.instr_cycle += 4;
1.1.1.11 root 2714:
1.1.1.4 root 2715: if (value & (1<<numbit)) {
2716: newpc = newaddr;
1.1.1.6 root 2717: dsp_core.pc = newpc;
1.1.1.4 root 2718: cur_inst_len=0;
2719: return;
1.1.1.11 root 2720: }
1.1.1.4 root 2721: ++cur_inst_len;
2722: }
2723:
2724: static void dsp_jset_ea(void)
2725: {
2726: Uint32 memspace, addr, value, numbit, newpc, newaddr;
1.1.1.11 root 2727:
1.1 root 2728: memspace = (cur_inst>>6) & 1;
2729: value = (cur_inst>>8) & BITMASK(6);
2730: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2731: dsp_calc_ea(value, &addr);
2732: value = read_memory(memspace, addr);
1.1.1.6 root 2733: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2734:
1.1.1.6 root 2735: dsp_core.instr_cycle += 4;
1.1.1.7 root 2736:
1.1.1.4 root 2737: if (value & (1<<numbit)) {
2738: newpc = newaddr;
1.1.1.6 root 2739: dsp_core.pc = newpc;
1.1.1.4 root 2740: cur_inst_len=0;
2741: return;
1.1.1.11 root 2742: }
1.1.1.4 root 2743: ++cur_inst_len;
2744: }
1.1 root 2745:
1.1.1.4 root 2746: static void dsp_jset_pp(void)
2747: {
2748: Uint32 memspace, addr, value, numbit, newpc, newaddr;
1.1.1.11 root 2749:
1.1.1.4 root 2750: memspace = (cur_inst>>6) & 1;
2751: value = (cur_inst>>8) & BITMASK(6);
2752: numbit = cur_inst & BITMASK(5);
2753: addr = 0xffc0 + value;
2754: value = read_memory(memspace, addr);
1.1.1.6 root 2755: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2756:
1.1.1.6 root 2757: dsp_core.instr_cycle += 4;
1.1.1.11 root 2758:
1.1.1.4 root 2759: if (value & (1<<numbit)) {
2760: newpc = newaddr;
1.1.1.6 root 2761: dsp_core.pc = newpc;
1.1.1.4 root 2762: cur_inst_len=0;
2763: return;
1.1.1.11 root 2764: }
1.1.1.4 root 2765: ++cur_inst_len;
2766: }
2767:
2768: static void dsp_jset_reg(void)
2769: {
2770: Uint32 value, numreg, numbit, newpc, newaddr;
1.1.1.11 root 2771:
1.1.1.4 root 2772: numreg = (cur_inst>>8) & BITMASK(6);
2773: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2774: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2775:
1.1.1.4 root 2776: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2777: dsp_pm_read_accu24(numreg, &value);
2778: } else {
1.1.1.6 root 2779: value = dsp_core.registers[numreg];
1.1.1.4 root 2780: }
2781:
1.1.1.6 root 2782: dsp_core.instr_cycle += 4;
1.1.1.11 root 2783:
1.1.1.4 root 2784: if (value & (1<<numbit)) {
2785: newpc = newaddr;
1.1.1.6 root 2786: dsp_core.pc = newpc;
1.1.1.4 root 2787: cur_inst_len=0;
2788: return;
1.1.1.11 root 2789: }
1.1.1.4 root 2790: ++cur_inst_len;
2791: }
2792:
2793: static void dsp_jsr_imm(void)
2794: {
2795: Uint32 newpc;
2796:
2797: newpc = cur_inst & BITMASK(12);
2798:
1.1.1.6 root 2799: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2800: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2801: }
2802: else {
1.1.1.6 root 2803: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1.1.1.4 root 2804: }
2805:
1.1.1.6 root 2806: dsp_core.pc = newpc;
1.1.1.4 root 2807: cur_inst_len = 0;
2808:
1.1.1.6 root 2809: dsp_core.instr_cycle += 2;
1.1.1.4 root 2810: }
2811:
2812: static void dsp_jsr_ea(void)
2813: {
2814: Uint32 newpc;
2815:
2816: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&newpc);
2817:
1.1.1.6 root 2818: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2819: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2820: }
2821: else {
1.1.1.6 root 2822: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1.1.1.4 root 2823: }
2824:
1.1.1.6 root 2825: dsp_core.pc = newpc;
1.1.1.4 root 2826: cur_inst_len = 0;
2827:
1.1.1.6 root 2828: dsp_core.instr_cycle += 2;
1.1.1.4 root 2829: }
2830:
2831: static void dsp_jsset_aa(void)
2832: {
2833: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2834:
1.1.1.4 root 2835: memspace = (cur_inst>>6) & 1;
2836: addr = (cur_inst>>8) & BITMASK(6);
2837: numbit = cur_inst & BITMASK(5);
2838: value = read_memory(memspace, addr);
1.1.1.6 root 2839: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2840:
1.1.1.6 root 2841: dsp_core.instr_cycle += 4;
1.1.1.4 root 2842:
2843: if (value & (1<<numbit)) {
1.1.1.6 root 2844: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2845: newpc = newaddr;
1.1.1.6 root 2846: dsp_core.pc = newpc;
1.1.1.4 root 2847: cur_inst_len = 0;
2848: return;
1.1.1.11 root 2849: }
1.1.1.4 root 2850: ++cur_inst_len;
2851: }
2852:
2853: static void dsp_jsset_ea(void)
2854: {
2855: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2856:
1.1.1.4 root 2857: memspace = (cur_inst>>6) & 1;
2858: value = (cur_inst>>8) & BITMASK(6);
2859: numbit = cur_inst & BITMASK(5);
2860: dsp_calc_ea(value, &addr);
2861: value = read_memory(memspace, addr);
1.1.1.6 root 2862: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2863:
1.1.1.6 root 2864: dsp_core.instr_cycle += 4;
1.1 root 2865:
2866: if (value & (1<<numbit)) {
1.1.1.6 root 2867: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2868: newpc = newaddr;
1.1.1.6 root 2869: dsp_core.pc = newpc;
1.1.1.4 root 2870: cur_inst_len = 0;
2871: return;
1.1.1.11 root 2872: }
1.1.1.4 root 2873: ++cur_inst_len;
1.1 root 2874: }
2875:
1.1.1.4 root 2876: static void dsp_jsset_pp(void)
1.1 root 2877: {
1.1.1.4 root 2878: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1.1.11 root 2879:
1.1.1.4 root 2880: memspace = (cur_inst>>6) & 1;
2881: value = (cur_inst>>8) & BITMASK(6);
2882: numbit = cur_inst & BITMASK(5);
2883: addr = 0xffc0 + value;
2884: value = read_memory(memspace, addr);
1.1.1.6 root 2885: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2886:
1.1.1.6 root 2887: dsp_core.instr_cycle += 4;
1.1 root 2888:
1.1.1.4 root 2889: if (value & (1<<numbit)) {
1.1.1.6 root 2890: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2891: newpc = newaddr;
1.1.1.6 root 2892: dsp_core.pc = newpc;
1.1.1.4 root 2893: cur_inst_len = 0;
2894: return;
1.1.1.11 root 2895: }
1.1.1.4 root 2896: ++cur_inst_len;
1.1 root 2897: }
2898:
1.1.1.4 root 2899: static void dsp_jsset_reg(void)
1.1 root 2900: {
1.1.1.4 root 2901: Uint32 value, numreg, newpc, numbit, newaddr;
1.1.1.11 root 2902:
1.1.1.4 root 2903: numreg = (cur_inst>>8) & BITMASK(6);
1.1 root 2904: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2905: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.11 root 2906:
1.1.1.4 root 2907: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2908: dsp_pm_read_accu24(numreg, &value);
2909: } else {
1.1.1.6 root 2910: value = dsp_core.registers[numreg];
1.1.1.4 root 2911: }
1.1 root 2912:
1.1.1.6 root 2913: dsp_core.instr_cycle += 4;
1.1 root 2914:
2915: if (value & (1<<numbit)) {
1.1.1.6 root 2916: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2917: newpc = newaddr;
1.1.1.6 root 2918: dsp_core.pc = newpc;
1.1 root 2919: cur_inst_len = 0;
1.1.1.4 root 2920: return;
1.1.1.11 root 2921: }
1.1.1.4 root 2922: ++cur_inst_len;
1.1 root 2923: }
2924:
2925: static void dsp_lua(void)
2926: {
1.1.1.2 root 2927: Uint32 value, srcreg, dstreg, srcsave, srcnew;
2928:
1.1 root 2929: srcreg = (cur_inst>>8) & BITMASK(3);
1.1.1.2 root 2930:
1.1.1.6 root 2931: srcsave = dsp_core.registers[DSP_REG_R0+srcreg];
1.1.1.2 root 2932: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &value);
1.1.1.6 root 2933: srcnew = dsp_core.registers[DSP_REG_R0+srcreg];
2934: dsp_core.registers[DSP_REG_R0+srcreg] = srcsave;
1.1.1.2 root 2935:
1.1.1.11 root 2936: if (cur_inst & (1<<3))
2937: dstreg = DSP_REG_N0 + (cur_inst & BITMASK(3));
2938: else
2939: dstreg = DSP_REG_R0 + (cur_inst & BITMASK(3));
1.1 root 2940:
1.1.1.11 root 2941: dsp_core.agu_move_indirect_instr = 1;
2942: dsp_write_reg(dstreg, srcnew);
1.1.1.6 root 2943: dsp_core.instr_cycle += 2;
1.1 root 2944: }
2945:
1.1.1.3 root 2946: static void dsp_movec_reg(void)
1.1 root 2947: {
1.1.1.4 root 2948: Uint32 numreg1, numreg2, value, dummy;
1.1 root 2949:
2950: /* S1,D2 */
2951: /* S2,D1 */
2952:
2953: numreg2 = (cur_inst>>8) & BITMASK(6);
1.1.1.4 root 2954: numreg1 = cur_inst & BITMASK(6);
1.1 root 2955:
1.1.1.11 root 2956: dsp_core.agu_move_indirect_instr = 1;
2957:
1.1 root 2958: if (cur_inst & (1<<15)) {
2959: /* Write D1 */
2960:
2961: if ((numreg2 == DSP_REG_A) || (numreg2 == DSP_REG_B)) {
1.1.1.11 root 2962: dsp_pm_read_accu24(numreg2, &value);
1.1 root 2963: } else {
1.1.1.6 root 2964: value = dsp_core.registers[numreg2];
1.1 root 2965: }
1.1.1.4 root 2966: dsp_write_reg(numreg1, value);
1.1 root 2967: } else {
2968: /* Read S1 */
1.1.1.4 root 2969: if (numreg1 == DSP_REG_SSH) {
2970: dsp_stack_pop(&value, &dummy);
1.1.1.11 root 2971: }
1.1.1.4 root 2972: else {
1.1.1.6 root 2973: value = dsp_core.registers[numreg1];
1.1.1.4 root 2974: }
1.1 root 2975:
1.1.1.11 root 2976: dsp_write_reg(numreg2, value);
1.1 root 2977: }
2978: }
2979:
1.1.1.3 root 2980: static void dsp_movec_aa(void)
1.1 root 2981: {
1.1.1.4 root 2982: Uint32 numreg, addr, memspace, value, dummy;
1.1 root 2983:
2984: /* x:aa,D1 */
2985: /* S1,x:aa */
2986: /* y:aa,D1 */
2987: /* S1,y:aa */
2988:
1.1.1.4 root 2989: numreg = cur_inst & BITMASK(6);
1.1 root 2990: addr = (cur_inst>>8) & BITMASK(6);
2991: memspace = (cur_inst>>6) & 1;
2992:
2993: if (cur_inst & (1<<15)) {
2994: /* Write D1 */
1.1.1.4 root 2995: value = read_memory(memspace, addr);
1.1.1.11 root 2996: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 2997: dsp_write_reg(numreg, value);
1.1 root 2998: } else {
2999: /* Read S1 */
1.1.1.4 root 3000: if (numreg == DSP_REG_SSH) {
3001: dsp_stack_pop(&value, &dummy);
1.1.1.11 root 3002: }
1.1.1.4 root 3003: else {
1.1.1.6 root 3004: value = dsp_core.registers[numreg];
1.1.1.4 root 3005: }
3006: write_memory(memspace, addr, value);
1.1 root 3007: }
3008: }
3009:
1.1.1.3 root 3010: static void dsp_movec_imm(void)
1.1 root 3011: {
1.1.1.4 root 3012: Uint32 numreg, value;
1.1 root 3013:
3014: /* #xx,D1 */
1.1.1.4 root 3015: numreg = cur_inst & BITMASK(6);
3016: value = (cur_inst>>8) & BITMASK(8);
1.1.1.11 root 3017: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3018: dsp_write_reg(numreg, value);
1.1 root 3019: }
3020:
1.1.1.3 root 3021: static void dsp_movec_ea(void)
1.1 root 3022: {
1.1.1.4 root 3023: Uint32 numreg, addr, memspace, ea_mode, value, dummy;
1.1 root 3024: int retour;
3025:
3026: /* x:ea,D1 */
3027: /* S1,x:ea */
3028: /* y:ea,D1 */
3029: /* S1,y:ea */
3030: /* #xxxx,D1 */
3031:
1.1.1.4 root 3032: numreg = cur_inst & BITMASK(6);
1.1 root 3033: ea_mode = (cur_inst>>8) & BITMASK(6);
3034: memspace = (cur_inst>>6) & 1;
3035:
3036: if (cur_inst & (1<<15)) {
3037: /* Write D1 */
3038: retour = dsp_calc_ea(ea_mode, &addr);
3039: if (retour) {
1.1.1.4 root 3040: value = addr;
1.1 root 3041: } else {
1.1.1.4 root 3042: value = read_memory(memspace, addr);
1.1 root 3043: }
1.1.1.11 root 3044: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3045: dsp_write_reg(numreg, value);
1.1 root 3046: } else {
3047: /* Read S1 */
1.1.1.4 root 3048: dsp_calc_ea(ea_mode, &addr);
3049: if (numreg == DSP_REG_SSH) {
3050: dsp_stack_pop(&value, &dummy);
1.1.1.11 root 3051: }
1.1.1.4 root 3052: else {
1.1.1.6 root 3053: value = dsp_core.registers[numreg];
1.1.1.4 root 3054: }
3055: write_memory(memspace, addr, value);
1.1 root 3056: }
3057: }
3058:
1.1.1.4 root 3059: static void dsp_movem_aa(void)
1.1 root 3060: {
1.1.1.4 root 3061: Uint32 numreg, addr, value, dummy;
1.1 root 3062:
3063: numreg = cur_inst & BITMASK(6);
1.1.1.4 root 3064: addr = (cur_inst>>8) & BITMASK(6);
1.1 root 3065:
1.1.1.4 root 3066: if (cur_inst & (1<<15)) {
3067: /* Write D */
3068: value = read_memory_p(addr);
1.1.1.11 root 3069: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3070: dsp_write_reg(numreg, value);
1.1 root 3071: } else {
1.1.1.4 root 3072: /* Read S */
3073: if (numreg == DSP_REG_SSH) {
3074: dsp_stack_pop(&value, &dummy);
1.1.1.11 root 3075: }
1.1.1.4 root 3076: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11 root 3077: dsp_pm_read_accu24(numreg, &value);
3078: }
1.1.1.4 root 3079: else {
1.1.1.6 root 3080: value = dsp_core.registers[numreg];
1.1.1.4 root 3081: }
3082: write_memory(DSP_SPACE_P, addr, value);
3083: }
1.1 root 3084:
1.1.1.6 root 3085: dsp_core.instr_cycle += 4;
1.1.1.4 root 3086: }
3087:
3088: static void dsp_movem_ea(void)
3089: {
3090: Uint32 numreg, addr, ea_mode, value, dummy;
3091:
3092: numreg = cur_inst & BITMASK(6);
3093: ea_mode = (cur_inst>>8) & BITMASK(6);
3094: dsp_calc_ea(ea_mode, &addr);
1.1 root 3095:
3096: if (cur_inst & (1<<15)) {
3097: /* Write D */
1.1.1.4 root 3098: value = read_memory_p(addr);
1.1.1.11 root 3099: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3100: dsp_write_reg(numreg, value);
1.1 root 3101: } else {
3102: /* Read S */
1.1.1.4 root 3103: if (numreg == DSP_REG_SSH) {
3104: dsp_stack_pop(&value, &dummy);
1.1.1.11 root 3105: }
1.1.1.4 root 3106: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11 root 3107: dsp_pm_read_accu24(numreg, &value);
3108: }
1.1.1.4 root 3109: else {
1.1.1.6 root 3110: value = dsp_core.registers[numreg];
1.1 root 3111: }
3112: write_memory(DSP_SPACE_P, addr, value);
3113: }
3114:
1.1.1.6 root 3115: dsp_core.instr_cycle += 4;
1.1 root 3116: }
3117:
3118: static void dsp_movep_0(void)
3119: {
3120: /* S,x:pp */
3121: /* x:pp,D */
3122: /* S,y:pp */
3123: /* y:pp,D */
1.1.1.11 root 3124:
1.1.1.4 root 3125: Uint32 addr, memspace, numreg, value, dummy;
1.1 root 3126:
3127: addr = 0xffc0 + (cur_inst & BITMASK(6));
3128: memspace = (cur_inst>>16) & 1;
3129: numreg = (cur_inst>>8) & BITMASK(6);
3130:
3131: if (cur_inst & (1<<15)) {
3132: /* Write pp */
3133: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11 root 3134: dsp_pm_read_accu24(numreg, &value);
1.1.1.4 root 3135: }
3136: else if (numreg == DSP_REG_SSH) {
3137: dsp_stack_pop(&value, &dummy);
3138: }
3139: else {
1.1.1.6 root 3140: value = dsp_core.registers[numreg];
1.1 root 3141: }
3142: write_memory(memspace, addr, value);
3143: } else {
3144: /* Read pp */
3145: value = read_memory(memspace, addr);
1.1.1.11 root 3146: dsp_core.agu_move_indirect_instr = 1;
1.1.1.4 root 3147: dsp_write_reg(numreg, value);
1.1 root 3148: }
1.1.1.4 root 3149:
1.1.1.6 root 3150: dsp_core.instr_cycle += 2;
1.1 root 3151: }
3152:
3153: static void dsp_movep_1(void)
3154: {
3155: /* p:ea,x:pp */
3156: /* x:pp,p:ea */
3157: /* p:ea,y:pp */
3158: /* y:pp,p:ea */
3159:
1.1.1.2 root 3160: Uint32 xyaddr, memspace, paddr;
1.1 root 3161:
3162: xyaddr = 0xffc0 + (cur_inst & BITMASK(6));
3163: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &paddr);
3164: memspace = (cur_inst>>16) & 1;
3165:
3166: if (cur_inst & (1<<15)) {
3167: /* Write pp */
1.1.1.4 root 3168: write_memory(memspace, xyaddr, read_memory_p(paddr));
1.1 root 3169: } else {
3170: /* Read pp */
3171: write_memory(DSP_SPACE_P, paddr, read_memory(memspace, xyaddr));
3172: }
1.1.1.4 root 3173:
1.1.1.7 root 3174: /* Movep is 4 cycles, but according to the motorola doc, */
3175: /* movep from p memory to x or y peripheral memory takes */
3176: /* 2 more cycles, so +4 cycles at total */
3177: dsp_core.instr_cycle += 4;
1.1 root 3178: }
3179:
1.1.1.4 root 3180: static void dsp_movep_23(void)
1.1 root 3181: {
3182: /* x:ea,x:pp */
3183: /* y:ea,x:pp */
3184: /* #xxxxxx,x:pp */
3185: /* x:pp,x:ea */
3186: /* x:pp,y:pp */
3187: /* x:ea,y:pp */
3188: /* y:ea,y:pp */
3189: /* #xxxxxx,y:pp */
3190: /* y:pp,y:ea */
3191: /* y:pp,x:ea */
3192:
1.1.1.2 root 3193: Uint32 addr, peraddr, easpace, perspace, ea_mode;
1.1 root 3194: int retour;
3195:
3196: peraddr = 0xffc0 + (cur_inst & BITMASK(6));
3197: perspace = (cur_inst>>16) & 1;
1.1.1.11 root 3198:
1.1 root 3199: ea_mode = (cur_inst>>8) & BITMASK(6);
3200: easpace = (cur_inst>>6) & 1;
3201: retour = dsp_calc_ea(ea_mode, &addr);
3202:
3203: if (cur_inst & (1<<15)) {
3204: /* Write pp */
1.1.1.11 root 3205:
1.1 root 3206: if (retour) {
3207: write_memory(perspace, peraddr, addr);
3208: } else {
3209: write_memory(perspace, peraddr, read_memory(easpace, addr));
3210: }
3211: } else {
3212: /* Read pp */
3213: write_memory(easpace, addr, read_memory(perspace, peraddr));
3214: }
1.1.1.4 root 3215:
1.1.1.6 root 3216: dsp_core.instr_cycle += 2;
1.1 root 3217: }
3218:
3219: static void dsp_norm(void)
3220: {
1.1.1.2 root 3221: Uint32 cursr,cur_e, cur_euz, dest[3], numreg, rreg;
3222: Uint16 newsr;
1.1 root 3223:
1.1.1.6 root 3224: cursr = dsp_core.registers[DSP_REG_SR];
1.1 root 3225: cur_e = (cursr>>DSP_SR_E) & 1; /* E */
3226: cur_euz = ~cur_e; /* (not E) and U and (not Z) */
3227: cur_euz &= (cursr>>DSP_SR_U) & 1;
3228: cur_euz &= ~((cursr>>DSP_SR_Z) & 1);
3229: cur_euz &= 1;
3230:
3231: numreg = (cur_inst>>3) & 1;
1.1.1.6 root 3232: dest[0] = dsp_core.registers[DSP_REG_A2+numreg];
3233: dest[1] = dsp_core.registers[DSP_REG_A1+numreg];
3234: dest[2] = dsp_core.registers[DSP_REG_A0+numreg];
1.1 root 3235: rreg = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3236:
3237: if (cur_euz) {
3238: newsr = dsp_asl56(dest);
1.1.1.6 root 3239: --dsp_core.registers[rreg];
3240: dsp_core.registers[rreg] &= BITMASK(16);
1.1 root 3241: } else if (cur_e) {
3242: newsr = dsp_asr56(dest);
1.1.1.6 root 3243: ++dsp_core.registers[rreg];
3244: dsp_core.registers[rreg] &= BITMASK(16);
1.1 root 3245: } else {
3246: newsr = 0;
3247: }
3248:
1.1.1.6 root 3249: dsp_core.registers[DSP_REG_A2+numreg] = dest[0];
3250: dsp_core.registers[DSP_REG_A1+numreg] = dest[1];
3251: dsp_core.registers[DSP_REG_A0+numreg] = dest[2];
1.1.1.2 root 3252:
1.1.1.6 root 3253: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 3254:
1.1.1.6 root 3255: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
3256: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 3257: }
3258:
3259: static void dsp_ori(void)
3260: {
1.1.1.2 root 3261: Uint32 regnum, value;
1.1 root 3262:
3263: value = (cur_inst >> 8) & BITMASK(8);
3264: regnum = cur_inst & BITMASK(2);
3265: switch(regnum) {
3266: case 0:
3267: /* mr */
1.1.1.6 root 3268: dsp_core.registers[DSP_REG_SR] |= value<<8;
1.1 root 3269: break;
3270: case 1:
3271: /* ccr */
1.1.1.6 root 3272: dsp_core.registers[DSP_REG_SR] |= value;
1.1 root 3273: break;
3274: case 2:
3275: /* omr */
1.1.1.6 root 3276: dsp_core.registers[DSP_REG_OMR] |= value;
1.1 root 3277: break;
3278: }
3279: }
3280:
1.1.1.3 root 3281: /*
3282: REP instruction parameter encoding
3283:
3284: xxxxxxxx 00xxxxxx 0xxxxxxx aa
3285: xxxxxxxx 01xxxxxx 0xxxxxxx ea
3286: xxxxxxxx YYxxxxxx 1xxxxxxx imm
3287: xxxxxxxx 11xxxxxx 0xxxxxxx reg
3288: */
3289:
3290: static void dsp_rep_aa(void)
1.1 root 3291: {
3292: /* x:aa */
3293: /* y:aa */
1.1.1.6 root 3294: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3295: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3296: dsp_core.loop_rep = 1; /* We are now running rep */
1.1 root 3297:
1.1.1.6 root 3298: dsp_core.registers[DSP_REG_LC]=read_memory((cur_inst>>6) & 1,(cur_inst>>8) & BITMASK(6));
1.1.1.4 root 3299:
1.1.1.6 root 3300: dsp_core.instr_cycle += 2;
1.1 root 3301: }
3302:
1.1.1.3 root 3303: static void dsp_rep_imm(void)
1.1 root 3304: {
3305: /* #xxx */
3306:
1.1.1.6 root 3307: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3308: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3309: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3310:
1.1.1.6 root 3311: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
1.1.1.3 root 3312: + ((cur_inst & BITMASK(4))<<8);
1.1.1.4 root 3313:
1.1.1.6 root 3314: dsp_core.instr_cycle += 2;
1.1 root 3315: }
3316:
1.1.1.3 root 3317: static void dsp_rep_ea(void)
1.1 root 3318: {
1.1.1.2 root 3319: Uint32 value;
1.1 root 3320:
3321: /* x:ea */
3322: /* y:ea */
3323:
1.1.1.6 root 3324: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3325: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3326: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3327:
1.1 root 3328: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&value);
1.1.1.6 root 3329: dsp_core.registers[DSP_REG_LC]= read_memory((cur_inst>>6) & 1, value);
1.1.1.4 root 3330:
1.1.1.6 root 3331: dsp_core.instr_cycle += 2;
1.1 root 3332: }
3333:
1.1.1.3 root 3334: static void dsp_rep_reg(void)
1.1 root 3335: {
1.1.1.2 root 3336: Uint32 numreg;
1.1 root 3337:
3338: /* R */
3339:
1.1.1.6 root 3340: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3341: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3342: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3343:
1.1 root 3344: numreg = (cur_inst>>8) & BITMASK(6);
3345: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.11 root 3346: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
1.1 root 3347: } else {
1.1.1.6 root 3348: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
1.1 root 3349: }
1.1.1.6 root 3350: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.4 root 3351:
1.1.1.6 root 3352: dsp_core.instr_cycle += 2;
1.1 root 3353: }
3354:
3355: static void dsp_reset(void)
3356: {
1.1.1.13 root 3357: /* Clear the IPR register */
3358: write_memory(DSP_SPACE_X, 0xffc0 + DSP_IPR, 0);
3359:
3360: /* Software reset all on-chip peripherals */
3361:
3362: /* HOST_HCR x:$FFE8 : clear the full register */
3363: write_memory(DSP_SPACE_X, 0xffc0 + DSP_HOST_HCR, 0);
3364:
3365: /* HOST_ICR $0 : clear the full register */
3366: dsp_core_write_host(CPU_HOST_ICR, 0);
3367:
3368: /* HOST_CVR $1 : set the register to $12 */
3369: dsp_core_write_host(CPU_HOST_CVR, 0x12);
3370:
3371: /* HOST_ISR $2 : set the bits TRDY and TXDE 1, other bits to 0 */
3372: dsp_core.hostport[CPU_HOST_ISR] = (1<<CPU_HOST_ISR_TRDY)|(1<<CPU_HOST_ISR_TXDE);
3373:
3374: /* HOST_IVR $3 : set the register to $0f */
3375: dsp_core_write_host(CPU_HOST_IVR, 0x0f);
3376:
3377: /* SSI_CRA x:$FFEC : clear the full register */
3378: write_memory(DSP_SPACE_X, 0xffc0 + DSP_SSI_CRA, 0);
3379:
3380: /* SSI_CRB x:$FFED : clear the full register */
3381: write_memory(DSP_SPACE_X, 0xffc0 + DSP_SSI_CRB, 0);
3382:
3383: /* SSI_SR x:$FFEE : set the register to $40 */
3384: write_memory(DSP_SPACE_X, 0xffc0 + DSP_SSI_SR, 1<<DSP_SSI_SR_TDE);
3385:
3386: /* SCI_SCR x:$FFF0 : clear the full register (not used in the Falcon) */
3387: write_memory(DSP_SPACE_X, 0xffc0 + DSP_SCI_SCR, 0);
3388:
3389: /* SCI_SSR x:$FFF1 : clear the register to $3 (not used in the Falcon) */
3390: write_memory(DSP_SPACE_X, 0xffc0 + DSP_SCI_SSR, 3);
3391:
3392: /* SCI_SCCR x:$FFF2 : clear the full register (not used in the Falcon) */
3393: write_memory(DSP_SPACE_X, 0xffc0 + DSP_SCI_SCCR, 0);
3394:
1.1.1.6 root 3395: dsp_core.instr_cycle += 2;
1.1 root 3396: }
3397:
3398: static void dsp_rti(void)
3399: {
1.1.1.2 root 3400: Uint32 newpc = 0, newsr = 0;
1.1 root 3401:
3402: dsp_stack_pop(&newpc, &newsr);
1.1.1.6 root 3403: dsp_core.pc = newpc;
3404: dsp_core.registers[DSP_REG_SR] = newsr;
1.1 root 3405: cur_inst_len = 0;
1.1.1.4 root 3406:
1.1.1.6 root 3407: dsp_core.instr_cycle += 2;
1.1 root 3408: }
3409:
3410: static void dsp_rts(void)
3411: {
1.1.1.2 root 3412: Uint32 newpc = 0, newsr;
1.1 root 3413:
3414: dsp_stack_pop(&newpc, &newsr);
1.1.1.6 root 3415: dsp_core.pc = newpc;
1.1 root 3416: cur_inst_len = 0;
1.1.1.4 root 3417:
1.1.1.6 root 3418: dsp_core.instr_cycle += 2;
1.1 root 3419: }
3420:
3421: static void dsp_stop(void)
3422: {
1.1.1.6 root 3423: LOG_TRACE(TRACE_DSP_STATE, "Dsp: STOP instruction\n");
1.1 root 3424: }
3425:
3426: static void dsp_swi(void)
3427: {
3428: /* Raise interrupt p:0x0006 */
1.1.1.6 root 3429: dsp_core.instr_cycle += 6;
1.1 root 3430: }
3431:
3432: static void dsp_tcc(void)
3433: {
1.1.1.6 root 3434: Uint32 cc_code, regsrc1, regdest1;
1.1.1.2 root 3435: Uint32 regsrc2, regdest2;
1.1.1.6 root 3436: Uint32 val0, val1, val2;
1.1.1.11 root 3437:
1.1 root 3438: cc_code = (cur_inst>>12) & BITMASK(4);
3439:
3440: if (dsp_calc_cc(cc_code)) {
3441: regsrc1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][0];
1.1.1.2 root 3442: regdest1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][1];
1.1 root 3443:
3444: /* Read S1 */
1.1.1.7 root 3445: if (regsrc1 == DSP_REG_A) {
3446: val0 = dsp_core.registers[DSP_REG_A0];
3447: val1 = dsp_core.registers[DSP_REG_A1];
3448: val2 = dsp_core.registers[DSP_REG_A2];
3449: }
3450: else if (regsrc1 == DSP_REG_B) {
3451: val0 = dsp_core.registers[DSP_REG_B0];
3452: val1 = dsp_core.registers[DSP_REG_B1];
3453: val2 = dsp_core.registers[DSP_REG_B2];
3454: }
3455: else {
1.1.1.6 root 3456: val0 = 0;
3457: val1 = dsp_core.registers[regsrc1];
1.1.1.7 root 3458: val2 = val1 & (1<<23) ? 0xff : 0x0;
1.1 root 3459: }
1.1.1.11 root 3460:
1.1 root 3461: /* Write D1 */
1.1.1.7 root 3462: if (regdest1 == DSP_REG_A) {
3463: dsp_core.registers[DSP_REG_A2] = val2;
3464: dsp_core.registers[DSP_REG_A1] = val1;
3465: dsp_core.registers[DSP_REG_A0] = val0;
3466: }
3467: else {
3468: dsp_core.registers[DSP_REG_B2] = val2;
3469: dsp_core.registers[DSP_REG_B1] = val1;
3470: dsp_core.registers[DSP_REG_B0] = val0;
3471: }
1.1 root 3472:
3473: /* S2,D2 transfer */
3474: if (cur_inst & (1<<16)) {
1.1.1.2 root 3475: regsrc2 = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3476: regdest2 = DSP_REG_R0+(cur_inst & BITMASK(3));
1.1 root 3477:
1.1.1.11 root 3478: dsp_core.agu_move_indirect_instr = 1;
3479: dsp_write_reg(regdest2, dsp_core.registers[regsrc2]);
1.1 root 3480: }
3481: }
3482: }
3483:
3484: static void dsp_wait(void)
3485: {
1.1.1.6 root 3486: LOG_TRACE(TRACE_DSP_STATE, "Dsp: WAIT instruction\n");
1.1 root 3487: }
3488:
1.1.1.2 root 3489: static int dsp_pm_read_accu24(int numreg, Uint32 *dest)
1.1 root 3490: {
1.1.1.4 root 3491: Uint32 scaling, value, reg;
1.1.1.7 root 3492: int got_limited = 0;
1.1 root 3493:
3494: /* Read an accumulator, stores it limited */
3495:
1.1.1.6 root 3496: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
1.1.1.4 root 3497: reg = numreg & 1;
1.1 root 3498:
1.1.1.6 root 3499: value = (dsp_core.registers[DSP_REG_A2+reg]) << 24;
3500: value += dsp_core.registers[DSP_REG_A1+reg];
1.1 root 3501:
3502: switch(scaling) {
3503: case 0:
1.1.1.4 root 3504: /* No scaling */
3505: break;
3506: case 1:
3507: /* scaling down */
3508: value >>= 1;
1.1 root 3509: break;
3510: case 2:
1.1.1.4 root 3511: /* scaling up */
3512: value <<= 1;
1.1.1.6 root 3513: value |= (dsp_core.registers[DSP_REG_A0+reg]>>23) & 1;
1.1 root 3514: break;
1.1.1.4 root 3515: /* indeterminate */
1.1.1.11 root 3516: case 3:
1.1.1.4 root 3517: break;
3518: }
3519:
3520: /* limiting ? */
3521: value &= BITMASK(24);
3522:
1.1.1.6 root 3523: if (dsp_core.registers[DSP_REG_A2+reg] == 0) {
1.1.1.4 root 3524: if (value <= 0x007fffff) {
3525: /* No limiting */
3526: *dest=value;
3527: return 0;
1.1.1.11 root 3528: }
1.1.1.4 root 3529: }
3530:
1.1.1.6 root 3531: if (dsp_core.registers[DSP_REG_A2+reg] == 0xff) {
1.1.1.4 root 3532: if (value >= 0x00800000) {
3533: /* No limiting */
3534: *dest=value;
3535: return 0;
1.1.1.11 root 3536: }
1.1 root 3537: }
3538:
1.1.1.6 root 3539: if (dsp_core.registers[DSP_REG_A2+reg] & (1<<7)) {
1.1 root 3540: /* Limited to maximum negative value */
3541: *dest=0x00800000;
1.1.1.6 root 3542: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
1.1.1.2 root 3543: got_limited=1;
1.1 root 3544: } else {
3545: /* Limited to maximal positive value */
3546: *dest=0x007fffff;
1.1.1.6 root 3547: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
1.1.1.2 root 3548: got_limited=1;
1.1.1.11 root 3549: }
1.1.1.2 root 3550:
3551: return got_limited;
1.1 root 3552: }
3553:
3554: static void dsp_pm_0(void)
3555: {
1.1.1.6 root 3556: Uint32 memspace, numreg, addr, save_accu, save_xy0;
1.1 root 3557: /*
3558: 0000 100d 00mm mrrr S,x:ea x0,D
3559: 0000 100d 10mm mrrr S,y:ea y0,D
3560: */
3561: memspace = (cur_inst>>15) & 1;
3562: numreg = (cur_inst>>16) & 1;
1.1.1.6 root 3563: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &addr);
3564:
1.1.1.11 root 3565: /* Save A or B */
1.1.1.6 root 3566: dsp_pm_read_accu24(numreg, &save_accu);
1.1 root 3567:
1.1.1.6 root 3568: /* Save X0 or Y0 */
3569: save_xy0 = dsp_core.registers[DSP_REG_X0+(memspace<<1)];
3570:
3571: /* Execute parallel instruction */
3572: opcodes_alu[cur_inst & BITMASK(8)]();
3573:
1.1.1.11 root 3574: /* Move [A|B] to [x|y]:ea */
1.1.1.6 root 3575: write_memory(memspace, addr, save_accu);
3576:
3577: /* Move [x|y]0 to [A|B] */
3578: dsp_core.registers[DSP_REG_A0+numreg] = 0;
3579: dsp_core.registers[DSP_REG_A1+numreg] = save_xy0;
1.1.1.7 root 3580: dsp_core.registers[DSP_REG_A2+numreg] = save_xy0 & (1<<23) ? 0xff : 0x0;
1.1 root 3581: }
3582:
3583: static void dsp_pm_1(void)
3584: {
1.1.1.6 root 3585: Uint32 memspace, numreg1, numreg2, value, xy_addr, retour, save_1, save_2;
1.1 root 3586: /*
1.1.1.11 root 3587: 0001 ffdf w0mm mrrr x:ea,D1 S2,D2
1.1 root 3588: S1,x:ea S2,D2
3589: #xxxxxx,D1 S2,D2
1.1.1.11 root 3590: 0001 deff w1mm mrrr S1,D1 y:ea,D2
1.1 root 3591: S1,D1 S2,y:ea
3592: S1,D1 #xxxxxx,D2
3593: */
3594: value = (cur_inst>>8) & BITMASK(6);
1.1.1.11 root 3595: retour = dsp_calc_ea(value, &xy_addr);
1.1 root 3596: memspace = (cur_inst>>14) & 1;
1.1.1.6 root 3597: numreg1 = numreg2 = DSP_REG_NULL;
1.1 root 3598:
3599: if (memspace) {
3600: /* Y: */
3601: switch((cur_inst>>16) & BITMASK(2)) {
1.1.1.6 root 3602: case 0: numreg1 = DSP_REG_Y0; break;
3603: case 1: numreg1 = DSP_REG_Y1; break;
3604: case 2: numreg1 = DSP_REG_A; break;
3605: case 3: numreg1 = DSP_REG_B; break;
1.1 root 3606: }
3607: } else {
3608: /* X: */
3609: switch((cur_inst>>18) & BITMASK(2)) {
1.1.1.6 root 3610: case 0: numreg1 = DSP_REG_X0; break;
3611: case 1: numreg1 = DSP_REG_X1; break;
3612: case 2: numreg1 = DSP_REG_A; break;
3613: case 3: numreg1 = DSP_REG_B; break;
1.1 root 3614: }
3615: }
3616:
3617: if (cur_inst & (1<<15)) {
3618: /* Write D1 */
1.1.1.6 root 3619: if (retour)
3620: save_1 = xy_addr;
3621: else
3622: save_1 = read_memory(memspace, xy_addr);
1.1 root 3623: } else {
3624: /* Read S1 */
1.1.1.6 root 3625: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
3626: dsp_pm_read_accu24(numreg1, &save_1);
3627: else
3628: save_1 = dsp_core.registers[numreg1];
1.1 root 3629: }
1.1.1.11 root 3630:
1.1 root 3631: /* S2 */
3632: if (memspace) {
3633: /* Y: */
1.1.1.6 root 3634: numreg2 = DSP_REG_A + ((cur_inst>>19) & 1);
1.1 root 3635: } else {
3636: /* X: */
1.1.1.6 root 3637: numreg2 = DSP_REG_A + ((cur_inst>>17) & 1);
1.1.1.11 root 3638: }
1.1.1.6 root 3639: dsp_pm_read_accu24(numreg2, &save_2);
1.1.1.11 root 3640:
1.1.1.6 root 3641:
3642: /* Execute parallel instruction */
3643: opcodes_alu[cur_inst & BITMASK(8)]();
3644:
3645:
3646: /* Write parallel move values */
3647: if (cur_inst & (1<<15)) {
3648: /* Write D1 */
1.1.1.11 root 3649: dsp_write_reg(numreg1, save_1);
1.1.1.6 root 3650: } else {
3651: /* Read S1 */
3652: write_memory(memspace, xy_addr, save_1);
3653: }
3654:
3655: /* S2 -> D2 */
1.1 root 3656: if (memspace) {
3657: /* Y: */
1.1.1.6 root 3658: numreg2 = DSP_REG_X0 + ((cur_inst>>18) & 1);
1.1 root 3659: } else {
3660: /* X: */
1.1.1.6 root 3661: numreg2 = DSP_REG_Y0 + ((cur_inst>>16) & 1);
1.1.1.11 root 3662: }
1.1.1.6 root 3663: dsp_core.registers[numreg2] = save_2;
1.1 root 3664: }
3665:
3666: static void dsp_pm_2(void)
3667: {
1.1.1.2 root 3668: Uint32 dummy;
1.1 root 3669: /*
3670: 0010 0000 0000 0000 nop
3671: 0010 0000 010m mrrr R update
3672: 0010 00ee eeed dddd S,D
3673: 001d dddd iiii iiii #xx,D
3674: */
1.1.1.4 root 3675: if ((cur_inst & 0xffff00) == 0x200000) {
1.1.1.6 root 3676: /* Execute parallel instruction */
3677: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3678: return;
3679: }
3680:
1.1.1.4 root 3681: if ((cur_inst & 0xffe000) == 0x204000) {
1.1 root 3682: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &dummy);
1.1.1.6 root 3683: /* Execute parallel instruction */
3684: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3685: return;
3686: }
3687:
1.1.1.4 root 3688: if ((cur_inst & 0xfc0000) == 0x200000) {
1.1 root 3689: dsp_pm_2_2();
3690: return;
3691: }
3692:
3693: dsp_pm_3();
3694: }
3695:
3696: static void dsp_pm_2_2(void)
3697: {
3698: /*
3699: 0010 00ee eeed dddd S,D
3700: */
1.1.1.6 root 3701: Uint32 srcreg, dstreg, save_reg;
1.1.1.11 root 3702:
1.1 root 3703: srcreg = (cur_inst >> 13) & BITMASK(5);
3704: dstreg = (cur_inst >> 8) & BITMASK(5);
3705:
1.1.1.6 root 3706: if ((srcreg == DSP_REG_A) || (srcreg == DSP_REG_B))
3707: /* Accu to register: limited 24 bits */
3708: dsp_pm_read_accu24(srcreg, &save_reg);
3709: else
3710: save_reg = dsp_core.registers[srcreg];
3711:
3712: /* Execute parallel instruction */
3713: opcodes_alu[cur_inst & BITMASK(8)]();
3714:
3715: /* Write reg */
1.1.1.11 root 3716: dsp_core.agu_move_indirect_instr = 1;
3717: dsp_write_reg(dstreg, save_reg);
1.1 root 3718: }
3719:
3720: static void dsp_pm_3(void)
3721: {
1.1.1.6 root 3722: Uint32 dstreg, srcvalue;
1.1 root 3723: /*
3724: 001d dddd iiii iiii #xx,R
3725: */
1.1.1.6 root 3726:
3727: /* Execute parallel instruction */
3728: opcodes_alu[cur_inst & BITMASK(8)]();
3729:
3730: /* Write reg */
3731: dstreg = (cur_inst >> 16) & BITMASK(5);
1.1 root 3732: srcvalue = (cur_inst >> 8) & BITMASK(8);
3733:
1.1.1.6 root 3734: switch(dstreg) {
1.1 root 3735: case DSP_REG_X0:
3736: case DSP_REG_X1:
3737: case DSP_REG_Y0:
3738: case DSP_REG_Y1:
3739: case DSP_REG_A:
3740: case DSP_REG_B:
3741: srcvalue <<= 16;
3742: break;
3743: }
3744:
1.1.1.11 root 3745: dsp_core.agu_move_indirect_instr = 1;
3746: dsp_write_reg(dstreg, srcvalue);
1.1 root 3747: }
3748:
3749: static void dsp_pm_4(void)
3750: {
3751: /*
1.1.1.4 root 3752: 0100 l0ll w0aa aaaa l:aa,D
1.1 root 3753: S,l:aa
1.1.1.4 root 3754: 0100 l0ll w1mm mrrr l:ea,D
1.1 root 3755: S,l:ea
1.1.1.4 root 3756: 01dd 0ddd w0aa aaaa x:aa,D
1.1 root 3757: S,x:aa
1.1.1.4 root 3758: 01dd 0ddd w1mm mrrr x:ea,D
1.1 root 3759: S,x:ea
3760: #xxxxxx,D
1.1.1.4 root 3761: 01dd 1ddd w0aa aaaa y:aa,D
1.1 root 3762: S,y:aa
1.1.1.4 root 3763: 01dd 1ddd w1mm mrrr y:ea,D
1.1 root 3764: S,y:ea
3765: #xxxxxx,D
3766: */
1.1.1.4 root 3767: if ((cur_inst & 0xf40000)==0x400000) {
3768: dsp_pm_4x();
1.1 root 3769: return;
3770: }
3771:
3772: dsp_pm_5();
3773: }
3774:
1.1.1.4 root 3775: static void dsp_pm_4x(void)
1.1 root 3776: {
1.1.1.6 root 3777: Uint32 value, numreg, l_addr, save_lx, save_ly;
1.1 root 3778: /*
1.1.1.4 root 3779: 0100 l0ll w0aa aaaa l:aa,D
3780: S,l:aa
3781: 0100 l0ll w1mm mrrr l:ea,D
3782: S,l:ea
1.1 root 3783: */
1.1.1.4 root 3784: value = (cur_inst>>8) & BITMASK(6);
3785: if (cur_inst & (1<<14)) {
1.1.1.11 root 3786: dsp_calc_ea(value, &l_addr);
1.1.1.4 root 3787: } else {
3788: l_addr = value;
3789: }
3790:
1.1 root 3791: numreg = (cur_inst>>16) & BITMASK(2);
3792: numreg |= (cur_inst>>17) & (1<<2);
3793:
3794: if (cur_inst & (1<<15)) {
3795: /* Write D */
1.1.1.6 root 3796: save_lx = read_memory(DSP_SPACE_X,l_addr);
3797: save_ly = read_memory(DSP_SPACE_Y,l_addr);
3798: }
3799: else {
3800: /* Read S */
1.1.1.4 root 3801: switch(numreg) {
3802: case 0:
3803: /* A10 */
1.1.1.6 root 3804: save_lx = dsp_core.registers[DSP_REG_A1];
3805: save_ly = dsp_core.registers[DSP_REG_A0];
1.1.1.4 root 3806: break;
3807: case 1:
3808: /* B10 */
1.1.1.6 root 3809: save_lx = dsp_core.registers[DSP_REG_B1];
3810: save_ly = dsp_core.registers[DSP_REG_B0];
1.1.1.4 root 3811: break;
3812: case 2:
3813: /* X */
1.1.1.6 root 3814: save_lx = dsp_core.registers[DSP_REG_X1];
3815: save_ly = dsp_core.registers[DSP_REG_X0];
1.1.1.4 root 3816: break;
3817: case 3:
3818: /* Y */
1.1.1.6 root 3819: save_lx = dsp_core.registers[DSP_REG_Y1];
3820: save_ly = dsp_core.registers[DSP_REG_Y0];
1.1.1.4 root 3821: break;
3822: case 4:
3823: /* A */
1.1.1.6 root 3824: if (dsp_pm_read_accu24(DSP_REG_A, &save_lx)) {
3825: /* Was limited, set lower part */
3826: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3827: } else {
3828: /* Not limited */
3829: save_ly = dsp_core.registers[DSP_REG_A0];
3830: }
1.1.1.4 root 3831: break;
3832: case 5:
3833: /* B */
1.1.1.6 root 3834: if (dsp_pm_read_accu24(DSP_REG_B, &save_lx)) {
3835: /* Was limited, set lower part */
3836: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3837: } else {
3838: /* Not limited */
3839: save_ly = dsp_core.registers[DSP_REG_B0];
3840: }
1.1.1.4 root 3841: break;
3842: case 6:
3843: /* AB */
1.1.1.11 root 3844: dsp_pm_read_accu24(DSP_REG_A, &save_lx);
3845: dsp_pm_read_accu24(DSP_REG_B, &save_ly);
1.1.1.4 root 3846: break;
3847: case 7:
3848: /* BA */
1.1.1.11 root 3849: dsp_pm_read_accu24(DSP_REG_B, &save_lx);
3850: dsp_pm_read_accu24(DSP_REG_A, &save_ly);
1.1.1.4 root 3851: break;
1.1 root 3852: }
1.1.1.6 root 3853: }
1.1 root 3854:
1.1.1.6 root 3855: /* Execute parallel instruction */
3856: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3857:
1.1.1.6 root 3858:
3859: if (cur_inst & (1<<15)) {
3860: /* Write D */
1.1.1.4 root 3861: switch(numreg) {
1.1.1.6 root 3862: case 0: /* A10 */
3863: dsp_core.registers[DSP_REG_A1] = save_lx;
3864: dsp_core.registers[DSP_REG_A0] = save_ly;
1.1.1.4 root 3865: break;
1.1.1.6 root 3866: case 1: /* B10 */
3867: dsp_core.registers[DSP_REG_B1] = save_lx;
3868: dsp_core.registers[DSP_REG_B0] = save_ly;
1.1.1.4 root 3869: break;
1.1.1.6 root 3870: case 2: /* X */
3871: dsp_core.registers[DSP_REG_X1] = save_lx;
3872: dsp_core.registers[DSP_REG_X0] = save_ly;
1.1.1.4 root 3873: break;
1.1.1.6 root 3874: case 3: /* Y */
3875: dsp_core.registers[DSP_REG_Y1] = save_lx;
3876: dsp_core.registers[DSP_REG_Y0] = save_ly;
1.1.1.4 root 3877: break;
1.1.1.6 root 3878: case 4: /* A */
3879: dsp_core.registers[DSP_REG_A0] = save_ly;
3880: dsp_core.registers[DSP_REG_A1] = save_lx;
3881: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
1.1.1.4 root 3882: break;
1.1.1.6 root 3883: case 5: /* B */
3884: dsp_core.registers[DSP_REG_B0] = save_ly;
3885: dsp_core.registers[DSP_REG_B1] = save_lx;
3886: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
1.1.1.4 root 3887: break;
1.1.1.6 root 3888: case 6: /* AB */
3889: dsp_core.registers[DSP_REG_A0] = 0;
3890: dsp_core.registers[DSP_REG_A1] = save_lx;
3891: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
3892: dsp_core.registers[DSP_REG_B0] = 0;
3893: dsp_core.registers[DSP_REG_B1] = save_ly;
3894: dsp_core.registers[DSP_REG_B2] = save_ly & (1<<23) ? 0xff : 0;
1.1.1.4 root 3895: break;
1.1.1.6 root 3896: case 7: /* BA */
3897: dsp_core.registers[DSP_REG_B0] = 0;
3898: dsp_core.registers[DSP_REG_B1] = save_lx;
3899: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
3900: dsp_core.registers[DSP_REG_A0] = 0;
3901: dsp_core.registers[DSP_REG_A1] = save_ly;
3902: dsp_core.registers[DSP_REG_A2] = save_ly & (1<<23) ? 0xff : 0;
1.1.1.4 root 3903: break;
1.1 root 3904: }
1.1.1.6 root 3905: }
3906: else {
3907: /* Read S */
3908: write_memory(DSP_SPACE_X, l_addr, save_lx);
3909: write_memory(DSP_SPACE_Y, l_addr, save_ly);
1.1 root 3910: }
3911: }
3912:
3913: static void dsp_pm_5(void)
3914: {
1.1.1.2 root 3915: Uint32 memspace, numreg, value, xy_addr, retour;
1.1 root 3916: /*
1.1.1.4 root 3917: 01dd 0ddd w0aa aaaa x:aa,D
1.1 root 3918: S,x:aa
1.1.1.4 root 3919: 01dd 0ddd w1mm mrrr x:ea,D
1.1 root 3920: S,x:ea
3921: #xxxxxx,D
1.1.1.4 root 3922: 01dd 1ddd w0aa aaaa y:aa,D
1.1 root 3923: S,y:aa
1.1.1.4 root 3924: 01dd 1ddd w1mm mrrr y:ea,D
1.1 root 3925: S,y:ea
3926: #xxxxxx,D
3927: */
3928:
3929: value = (cur_inst>>8) & BITMASK(6);
3930:
3931: if (cur_inst & (1<<14)) {
1.1.1.11 root 3932: retour = dsp_calc_ea(value, &xy_addr);
1.1 root 3933: } else {
3934: xy_addr = value;
3935: retour = 0;
3936: }
3937:
3938: memspace = (cur_inst>>19) & 1;
3939: numreg = (cur_inst>>16) & BITMASK(3);
3940: numreg |= (cur_inst>>17) & (BITMASK(2)<<3);
3941:
3942: if (cur_inst & (1<<15)) {
3943: /* Write D */
1.1.1.6 root 3944: if (retour)
1.1 root 3945: value = xy_addr;
1.1.1.6 root 3946: else
1.1 root 3947: value = read_memory(memspace, xy_addr);
1.1.1.6 root 3948: }
3949: else {
1.1 root 3950: /* Read S */
1.1.1.6 root 3951: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B))
3952: dsp_pm_read_accu24(numreg, &value);
3953: else
3954: value = dsp_core.registers[numreg];
3955: }
1.1 root 3956:
3957:
1.1.1.6 root 3958: /* Execute parallel instruction */
3959: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3960:
1.1.1.6 root 3961: if (cur_inst & (1<<15)) {
3962: /* Write D */
1.1.1.11 root 3963: dsp_core.agu_move_indirect_instr = 1;
3964: dsp_write_reg(numreg, value);
1.1.1.6 root 3965: }
3966: else {
1.1.1.7 root 3967: /* Read S */
1.1.1.6 root 3968: write_memory(memspace, xy_addr, value);
1.1 root 3969: }
3970: }
3971:
3972: static void dsp_pm_8(void)
3973: {
1.1.1.2 root 3974: Uint32 ea1, ea2;
3975: Uint32 numreg1, numreg2;
1.1.1.6 root 3976: Uint32 save_reg1, save_reg2, x_addr, y_addr;
1.1 root 3977: /*
1.1.1.11 root 3978: 1wmm eeff WrrM MRRR x:ea,D1 y:ea,D2
1.1 root 3979: x:ea,D1 S2,y:ea
3980: S1,x:ea y:ea,D2
3981: S1,x:ea S2,y:ea
3982: */
3983: numreg1 = numreg2 = DSP_REG_NULL;
3984:
3985: ea1 = (cur_inst>>8) & BITMASK(5);
3986: if ((ea1>>3) == 0) {
3987: ea1 |= (1<<5);
3988: }
3989: ea2 = (cur_inst>>13) & BITMASK(2);
3990: ea2 |= (cur_inst>>17) & (BITMASK(2)<<3);
3991: if ((ea1 & (1<<2))==0) {
3992: ea2 |= 1<<2;
3993: }
3994: if ((ea2>>3) == 0) {
3995: ea2 |= (1<<5);
3996: }
3997:
1.1.1.4 root 3998: dsp_calc_ea(ea1, &x_addr);
3999: dsp_calc_ea(ea2, &y_addr);
4000:
1.1 root 4001: switch((cur_inst>>18) & BITMASK(2)) {
4002: case 0: numreg1=DSP_REG_X0; break;
4003: case 1: numreg1=DSP_REG_X1; break;
4004: case 2: numreg1=DSP_REG_A; break;
4005: case 3: numreg1=DSP_REG_B; break;
4006: }
4007: switch((cur_inst>>16) & BITMASK(2)) {
4008: case 0: numreg2=DSP_REG_Y0; break;
4009: case 1: numreg2=DSP_REG_Y1; break;
4010: case 2: numreg2=DSP_REG_A; break;
4011: case 3: numreg2=DSP_REG_B; break;
4012: }
1.1.1.11 root 4013:
1.1 root 4014: if (cur_inst & (1<<15)) {
4015: /* Write D1 */
1.1.1.6 root 4016: save_reg1 = read_memory(DSP_SPACE_X, x_addr);
1.1 root 4017: } else {
4018: /* Read S1 */
1.1.1.6 root 4019: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
4020: dsp_pm_read_accu24(numreg1, &save_reg1);
4021: else
4022: save_reg1 = dsp_core.registers[numreg1];
1.1 root 4023: }
4024:
4025: if (cur_inst & (1<<22)) {
4026: /* Write D2 */
1.1.1.6 root 4027: save_reg2 = read_memory(DSP_SPACE_Y, y_addr);
1.1 root 4028: } else {
4029: /* Read S2 */
1.1.1.6 root 4030: if ((numreg2==DSP_REG_A) || (numreg2==DSP_REG_B))
4031: dsp_pm_read_accu24(numreg2, &save_reg2);
4032: else
4033: save_reg2 = dsp_core.registers[numreg2];
1.1 root 4034: }
4035:
4036:
1.1.1.6 root 4037: /* Execute parallel instruction */
4038: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 4039:
1.1.1.6 root 4040: /* Write first parallel move */
4041: if (cur_inst & (1<<15)) {
4042: /* Write D1 */
4043: if (numreg1 == DSP_REG_A) {
4044: dsp_core.registers[DSP_REG_A0] = 0x0;
4045: dsp_core.registers[DSP_REG_A1] = save_reg1;
4046: dsp_core.registers[DSP_REG_A2] = save_reg1 & (1<<23) ? 0xff : 0x0;
4047: }
4048: else if (numreg1 == DSP_REG_B) {
4049: dsp_core.registers[DSP_REG_B0] = 0x0;
4050: dsp_core.registers[DSP_REG_B1] = save_reg1;
4051: dsp_core.registers[DSP_REG_B2] = save_reg1 & (1<<23) ? 0xff : 0x0;
4052: }
4053: else {
4054: dsp_core.registers[numreg1] = save_reg1;
4055: }
4056: } else {
4057: /* Read S1 */
4058: write_memory(DSP_SPACE_X, x_addr, save_reg1);
4059: }
4060:
4061: /* Write second parallel move */
4062: if (cur_inst & (1<<22)) {
4063: /* Write D2 */
4064: if (numreg2 == DSP_REG_A) {
4065: dsp_core.registers[DSP_REG_A0] = 0x0;
4066: dsp_core.registers[DSP_REG_A1] = save_reg2;
4067: dsp_core.registers[DSP_REG_A2] = save_reg2 & (1<<23) ? 0xff : 0x0;
4068: }
4069: else if (numreg2 == DSP_REG_B) {
4070: dsp_core.registers[DSP_REG_B0] = 0x0;
4071: dsp_core.registers[DSP_REG_B1] = save_reg2;
4072: dsp_core.registers[DSP_REG_B2] = save_reg2 & (1<<23) ? 0xff : 0x0;
4073: }
4074: else {
4075: dsp_core.registers[numreg2] = save_reg2;
4076: }
4077: } else {
4078: /* Read S2 */
4079: write_memory(DSP_SPACE_Y, y_addr, save_reg2);
4080: }
4081: }
4082:
4083: /**********************************
4084: * 56bit arithmetic
4085: **********************************/
4086:
4087: /* source,dest[0] is 55:48 */
4088: /* source,dest[1] is 47:24 */
4089: /* source,dest[2] is 23:00 */
4090:
4091: static Uint16 dsp_abs56(Uint32 *dest)
1.1 root 4092: {
1.1.1.2 root 4093: Uint32 zerodest[3];
4094: Uint16 newsr;
1.1 root 4095:
4096: /* D=|D| */
4097:
4098: if (dest[0] & (1<<7)) {
4099: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4100:
4101: newsr = dsp_sub56(dest, zerodest);
4102:
4103: dest[0] = zerodest[0];
4104: dest[1] = zerodest[1];
4105: dest[2] = zerodest[2];
4106: } else {
4107: newsr = 0;
4108: }
4109:
4110: return newsr;
4111: }
4112:
1.1.1.2 root 4113: static Uint16 dsp_asl56(Uint32 *dest)
1.1 root 4114: {
1.1.1.2 root 4115: Uint16 overflow, carry;
1.1 root 4116:
4117: /* Shift left dest 1 bit: D<<=1 */
4118:
4119: carry = (dest[0]>>7) & 1;
4120:
4121: dest[0] <<= 1;
4122: dest[0] |= (dest[1]>>23) & 1;
4123: dest[0] &= BITMASK(8);
4124:
4125: dest[1] <<= 1;
4126: dest[1] |= (dest[2]>>23) & 1;
4127: dest[1] &= BITMASK(24);
1.1.1.11 root 4128:
1.1 root 4129: dest[2] <<= 1;
4130: dest[2] &= BITMASK(24);
4131:
4132: overflow = (carry != ((dest[0]>>7) & 1));
4133:
4134: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4135: }
4136:
1.1.1.2 root 4137: static Uint16 dsp_asr56(Uint32 *dest)
1.1 root 4138: {
1.1.1.2 root 4139: Uint16 carry;
1.1 root 4140:
4141: /* Shift right dest 1 bit: D>>=1 */
4142:
4143: carry = dest[2] & 1;
4144:
4145: dest[2] >>= 1;
4146: dest[2] |= (dest[1] & 1)<<23;
4147:
4148: dest[1] >>= 1;
4149: dest[1] |= (dest[0] & 1)<<23;
4150:
4151: dest[0] >>= 1;
4152: dest[0] |= (dest[0] & (1<<6))<<1;
4153:
4154: return (carry<<DSP_SR_C);
4155: }
4156:
1.1.1.2 root 4157: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest)
1.1 root 4158: {
1.1.1.4 root 4159: Uint16 overflow, carry, flg_s, flg_d, flg_r;
4160:
4161: flg_s = (source[0]>>7) & 1;
4162: flg_d = (dest[0]>>7) & 1;
4163:
1.1 root 4164: /* Add source to dest: D = D+S */
1.1.1.2 root 4165: dest[2] += source[2];
4166: dest[1] += source[1]+((dest[2]>>24) & 1);
4167: dest[0] += source[0]+((dest[1]>>24) & 1);
1.1 root 4168:
1.1.1.5 root 4169: carry = (dest[0]>>8) & 1;
4170:
1.1 root 4171: dest[2] &= BITMASK(24);
4172: dest[1] &= BITMASK(24);
4173: dest[0] &= BITMASK(8);
4174:
1.1.1.4 root 4175: flg_r = (dest[0]>>7) & 1;
4176:
4177: /*set overflow*/
4178: overflow = (flg_s ^ flg_r) & (flg_d ^ flg_r);
4179:
1.1 root 4180: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4181: }
4182:
1.1.1.2 root 4183: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest)
1.1 root 4184: {
1.1.1.5 root 4185: Uint16 overflow, carry, flg_s, flg_d, flg_r, dest_save;
1.1.1.4 root 4186:
1.1.1.5 root 4187: dest_save = dest[0];
1.1 root 4188:
1.1.1.9 root 4189: /* Subtract source from dest: D = D-S */
1.1.1.2 root 4190: dest[2] -= source[2];
4191: dest[1] -= source[1]+((dest[2]>>24) & 1);
4192: dest[0] -= source[0]+((dest[1]>>24) & 1);
1.1 root 4193:
1.1.1.5 root 4194: carry = (dest[0]>>8) & 1;
4195:
1.1 root 4196: dest[2] &= BITMASK(24);
4197: dest[1] &= BITMASK(24);
4198: dest[0] &= BITMASK(8);
4199:
1.1.1.4 root 4200: flg_s = (source[0]>>7) & 1;
1.1.1.5 root 4201: flg_d = (dest_save>>7) & 1;
1.1.1.4 root 4202: flg_r = (dest[0]>>7) & 1;
4203:
4204: /* set overflow */
4205: overflow = (flg_s ^ flg_d) & (flg_r ^ flg_d);
4206:
1.1 root 4207: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4208: }
4209:
1.1.1.5 root 4210: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe)
1.1 root 4211: {
1.1.1.2 root 4212: Uint32 part[4], zerodest[3], value;
1.1 root 4213:
4214: /* Multiply: D = S1*S2 */
4215: if (source1 & (1<<23)) {
1.1.1.5 root 4216: signe ^= 1;
1.1.1.6 root 4217: source1 = (1<<24) - source1;
1.1 root 4218: }
4219: if (source2 & (1<<23)) {
1.1.1.5 root 4220: signe ^= 1;
1.1.1.6 root 4221: source2 = (1<<24) - source2;
1.1 root 4222: }
4223:
4224: /* bits 0-11 * bits 0-11 */
4225: part[0]=(source1 & BITMASK(12))*(source2 & BITMASK(12));
4226: /* bits 12-23 * bits 0-11 */
4227: part[1]=((source1>>12) & BITMASK(12))*(source2 & BITMASK(12));
4228: /* bits 0-11 * bits 12-23 */
4229: part[2]=(source1 & BITMASK(12))*((source2>>12) & BITMASK(12));
4230: /* bits 12-23 * bits 12-23 */
4231: part[3]=((source1>>12) & BITMASK(12))*((source2>>12) & BITMASK(12));
4232:
4233: /* Calc dest 2 */
4234: dest[2] = part[0];
4235: dest[2] += (part[1] & BITMASK(12)) << 12;
4236: dest[2] += (part[2] & BITMASK(12)) << 12;
4237:
4238: /* Calc dest 1 */
4239: dest[1] = (part[1]>>12) & BITMASK(12);
4240: dest[1] += (part[2]>>12) & BITMASK(12);
4241: dest[1] += part[3];
4242:
4243: /* Calc dest 0 */
4244: dest[0] = 0;
4245:
4246: /* Add carries */
4247: value = (dest[2]>>24) & BITMASK(8);
4248: if (value) {
4249: dest[1] += value;
4250: dest[2] &= BITMASK(24);
4251: }
4252: value = (dest[1]>>24) & BITMASK(8);
4253: if (value) {
4254: dest[0] += value;
4255: dest[1] &= BITMASK(24);
4256: }
4257:
4258: /* Get rid of extra sign bit */
4259: dsp_asl56(dest);
4260:
1.1.1.5 root 4261: if (signe) {
1.1 root 4262: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4263:
4264: dsp_sub56(dest, zerodest);
4265:
4266: dest[0] = zerodest[0];
4267: dest[1] = zerodest[1];
4268: dest[2] = zerodest[2];
4269: }
4270: }
4271:
1.1.1.2 root 4272: static void dsp_rnd56(Uint32 *dest)
1.1 root 4273: {
1.1.1.4 root 4274: Uint32 rnd_const[3];
1.1 root 4275:
1.1.1.4 root 4276: rnd_const[0] = 0;
1.1 root 4277:
1.1.1.4 root 4278: /* Scaling mode S0 */
1.1.1.6 root 4279: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S0)) {
1.1.1.4 root 4280: rnd_const[1] = 1;
4281: rnd_const[2] = 0;
4282: dsp_add56(rnd_const, dest);
4283:
4284: if ((dest[2]==0) && ((dest[1] & 1) == 0)) {
4285: dest[1] &= (0xffffff - 0x3);
4286: }
4287: dest[1] &= 0xfffffe;
4288: dest[2]=0;
4289: }
4290: /* Scaling mode S1 */
1.1.1.6 root 4291: else if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S1)) {
1.1.1.4 root 4292: rnd_const[1] = 0;
4293: rnd_const[2] = (1<<22);
4294: dsp_add56(rnd_const, dest);
1.1.1.11 root 4295:
1.1.1.4 root 4296: if ((dest[2] & 0x7fffff) == 0){
4297: dest[2] = 0;
4298: }
4299: dest[2] &= 0x800000;
4300: }
4301: /* No Scaling */
4302: else {
4303: rnd_const[1] = 0;
4304: rnd_const[2] = (1<<23);
4305: dsp_add56(rnd_const, dest);
4306:
4307: if (dest[2] == 0) {
4308: dest[1] &= 0xfffffe;
1.1 root 4309: }
1.1.1.4 root 4310: dest[2]=0;
1.1 root 4311: }
4312: }
4313:
4314: /**********************************
4315: * Parallel moves instructions
4316: **********************************/
4317:
1.1.1.6 root 4318: static void dsp_abs_a(void)
1.1 root 4319: {
1.1.1.6 root 4320: Uint32 dest[3], overflowed;
1.1 root 4321:
1.1.1.6 root 4322: dest[0] = dsp_core.registers[DSP_REG_A2];
4323: dest[1] = dsp_core.registers[DSP_REG_A1];
4324: dest[2] = dsp_core.registers[DSP_REG_A0];
4325:
4326: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4327:
4328: dsp_abs56(dest);
4329:
4330: dsp_core.registers[DSP_REG_A2] = dest[0];
4331: dsp_core.registers[DSP_REG_A1] = dest[1];
4332: dsp_core.registers[DSP_REG_A0] = dest[2];
4333:
4334: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4335: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
4336:
4337: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4338: }
4339:
4340: static void dsp_abs_b(void)
4341: {
4342: Uint32 dest[3], overflowed;
1.1 root 4343:
1.1.1.6 root 4344: dest[0] = dsp_core.registers[DSP_REG_B2];
4345: dest[1] = dsp_core.registers[DSP_REG_B1];
4346: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 4347:
4348: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4349:
4350: dsp_abs56(dest);
4351:
1.1.1.6 root 4352: dsp_core.registers[DSP_REG_B2] = dest[0];
4353: dsp_core.registers[DSP_REG_B1] = dest[1];
4354: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4355:
1.1.1.6 root 4356: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4357: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
1.1.1.2 root 4358:
1.1.1.6 root 4359: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4360: }
4361:
1.1.1.6 root 4362: static void dsp_adc_x_a(void)
1.1 root 4363: {
1.1.1.6 root 4364: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4365: Uint16 newsr;
1.1 root 4366:
1.1.1.6 root 4367: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4368:
1.1.1.6 root 4369: dest[0] = dsp_core.registers[DSP_REG_A2];
4370: dest[1] = dsp_core.registers[DSP_REG_A1];
4371: dest[2] = dsp_core.registers[DSP_REG_A0];
4372:
4373: source[2] = dsp_core.registers[DSP_REG_X0];
4374: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4375: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4376:
4377: newsr = dsp_add56(source, dest);
1.1.1.11 root 4378:
1.1 root 4379: if (curcarry) {
1.1.1.6 root 4380: source[0]=0; source[1]=0; source[2]=1;
1.1 root 4381: newsr |= dsp_add56(source, dest);
4382: }
4383:
1.1.1.6 root 4384: dsp_core.registers[DSP_REG_A2] = dest[0];
4385: dsp_core.registers[DSP_REG_A1] = dest[1];
4386: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4387:
1.1.1.6 root 4388: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4389:
1.1.1.6 root 4390: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4391: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4392: }
4393:
1.1.1.6 root 4394: static void dsp_adc_x_b(void)
1.1 root 4395: {
1.1.1.6 root 4396: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4397: Uint16 newsr;
1.1 root 4398:
1.1.1.6 root 4399: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
4400:
4401: dest[0] = dsp_core.registers[DSP_REG_B2];
4402: dest[1] = dsp_core.registers[DSP_REG_B1];
4403: dest[2] = dsp_core.registers[DSP_REG_B0];
4404:
4405: source[2] = dsp_core.registers[DSP_REG_X0];
4406: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4407: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4408:
4409: newsr = dsp_add56(source, dest);
1.1.1.11 root 4410:
1.1.1.6 root 4411: if (curcarry) {
4412: source[0]=0; source[1]=0; source[2]=1;
4413: newsr |= dsp_add56(source, dest);
4414: }
1.1 root 4415:
1.1.1.6 root 4416: dsp_core.registers[DSP_REG_B2] = dest[0];
4417: dsp_core.registers[DSP_REG_B1] = dest[1];
4418: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4419:
1.1.1.6 root 4420: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4421:
1.1.1.6 root 4422: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4423: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4424: }
4425:
1.1.1.6 root 4426: static void dsp_adc_y_a(void)
1.1 root 4427: {
1.1.1.6 root 4428: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4429: Uint16 newsr;
1.1 root 4430:
1.1.1.6 root 4431: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4432:
1.1.1.6 root 4433: dest[0] = dsp_core.registers[DSP_REG_A2];
4434: dest[1] = dsp_core.registers[DSP_REG_A1];
4435: dest[2] = dsp_core.registers[DSP_REG_A0];
4436:
4437: source[2] = dsp_core.registers[DSP_REG_Y0];
4438: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4439: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4440:
1.1.1.6 root 4441: newsr = dsp_add56(source, dest);
1.1.1.11 root 4442:
1.1.1.6 root 4443: if (curcarry) {
4444: source[0]=0; source[1]=0; source[2]=1;
4445: newsr |= dsp_add56(source, dest);
4446: }
1.1 root 4447:
1.1.1.6 root 4448: dsp_core.registers[DSP_REG_A2] = dest[0];
4449: dsp_core.registers[DSP_REG_A1] = dest[1];
4450: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4451:
1.1.1.6 root 4452: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4453:
1.1.1.6 root 4454: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4455: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4456: }
4457:
1.1.1.6 root 4458: static void dsp_adc_y_b(void)
1.1 root 4459: {
1.1.1.6 root 4460: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4461: Uint16 newsr;
1.1 root 4462:
1.1.1.6 root 4463: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4464:
1.1.1.6 root 4465: dest[0] = dsp_core.registers[DSP_REG_B2];
4466: dest[1] = dsp_core.registers[DSP_REG_B1];
4467: dest[2] = dsp_core.registers[DSP_REG_B0];
4468:
4469: source[2] = dsp_core.registers[DSP_REG_Y0];
4470: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4471: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4472:
1.1.1.6 root 4473: newsr = dsp_add56(source, dest);
1.1.1.11 root 4474:
1.1.1.6 root 4475: if (curcarry) {
4476: source[0]=0; source[1]=0; source[2]=1;
4477: newsr |= dsp_add56(source, dest);
4478: }
1.1 root 4479:
1.1.1.6 root 4480: dsp_core.registers[DSP_REG_B2] = dest[0];
4481: dsp_core.registers[DSP_REG_B1] = dest[1];
4482: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4483:
1.1.1.6 root 4484: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4485:
1.1.1.6 root 4486: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4487: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4488: }
4489:
1.1.1.6 root 4490: static void dsp_add_b_a(void)
1.1 root 4491: {
1.1.1.6 root 4492: Uint32 source[3], dest[3];
4493: Uint16 newsr;
1.1 root 4494:
1.1.1.6 root 4495: dest[0] = dsp_core.registers[DSP_REG_A2];
4496: dest[1] = dsp_core.registers[DSP_REG_A1];
4497: dest[2] = dsp_core.registers[DSP_REG_A0];
4498:
4499: source[0] = dsp_core.registers[DSP_REG_B2];
4500: source[1] = dsp_core.registers[DSP_REG_B1];
4501: source[2] = dsp_core.registers[DSP_REG_B0];
4502:
4503: newsr = dsp_add56(source, dest);
4504:
4505: dsp_core.registers[DSP_REG_A2] = dest[0];
4506: dsp_core.registers[DSP_REG_A1] = dest[1];
4507: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4508:
1.1.1.6 root 4509: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4510:
1.1.1.6 root 4511: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4512: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4513: }
4514:
1.1.1.6 root 4515: static void dsp_add_a_b(void)
1.1 root 4516: {
1.1.1.6 root 4517: Uint32 source[3], dest[3];
1.1.1.2 root 4518: Uint16 newsr;
1.1 root 4519:
1.1.1.6 root 4520: dest[0] = dsp_core.registers[DSP_REG_B2];
4521: dest[1] = dsp_core.registers[DSP_REG_B1];
4522: dest[2] = dsp_core.registers[DSP_REG_B0];
4523:
4524: source[0] = dsp_core.registers[DSP_REG_A2];
4525: source[1] = dsp_core.registers[DSP_REG_A1];
4526: source[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 4527:
1.1.1.6 root 4528: newsr = dsp_add56(source, dest);
1.1 root 4529:
1.1.1.6 root 4530: dsp_core.registers[DSP_REG_B2] = dest[0];
4531: dsp_core.registers[DSP_REG_B1] = dest[1];
4532: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4533:
1.1.1.6 root 4534: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4535:
1.1.1.6 root 4536: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4537: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4538: }
4539:
1.1.1.6 root 4540: static void dsp_add_x_a(void)
1.1 root 4541: {
1.1.1.6 root 4542: Uint32 source[3], dest[3];
4543: Uint16 newsr;
1.1 root 4544:
1.1.1.6 root 4545: dest[0] = dsp_core.registers[DSP_REG_A2];
4546: dest[1] = dsp_core.registers[DSP_REG_A1];
4547: dest[2] = dsp_core.registers[DSP_REG_A0];
4548:
4549: source[1] = dsp_core.registers[DSP_REG_X1];
4550: source[2] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4551: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4552:
1.1.1.6 root 4553: newsr = dsp_add56(source, dest);
1.1 root 4554:
1.1.1.6 root 4555: dsp_core.registers[DSP_REG_A2] = dest[0];
4556: dsp_core.registers[DSP_REG_A1] = dest[1];
4557: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4558:
1.1.1.6 root 4559: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4560:
1.1.1.6 root 4561: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4562: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4563: }
4564:
1.1.1.6 root 4565: static void dsp_add_x_b(void)
1.1 root 4566: {
1.1.1.6 root 4567: Uint32 source[3], dest[3];
4568: Uint16 newsr;
1.1 root 4569:
1.1.1.6 root 4570: dest[0] = dsp_core.registers[DSP_REG_B2];
4571: dest[1] = dsp_core.registers[DSP_REG_B1];
4572: dest[2] = dsp_core.registers[DSP_REG_B0];
4573:
4574: source[1] = dsp_core.registers[DSP_REG_X1];
4575: source[2] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4576: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4577:
4578: newsr = dsp_add56(source, dest);
1.1 root 4579:
1.1.1.6 root 4580: dsp_core.registers[DSP_REG_B2] = dest[0];
4581: dsp_core.registers[DSP_REG_B1] = dest[1];
4582: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4583:
1.1.1.6 root 4584: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4585:
4586: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4587: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4588: }
4589:
1.1.1.6 root 4590: static void dsp_add_y_a(void)
1.1 root 4591: {
1.1.1.6 root 4592: Uint32 source[3], dest[3];
1.1.1.2 root 4593: Uint16 newsr;
1.1 root 4594:
1.1.1.6 root 4595: dest[0] = dsp_core.registers[DSP_REG_A2];
4596: dest[1] = dsp_core.registers[DSP_REG_A1];
4597: dest[2] = dsp_core.registers[DSP_REG_A0];
4598:
4599: source[1] = dsp_core.registers[DSP_REG_Y1];
4600: source[2] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4601: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4602:
1.1.1.6 root 4603: newsr = dsp_add56(source, dest);
1.1 root 4604:
1.1.1.6 root 4605: dsp_core.registers[DSP_REG_A2] = dest[0];
4606: dsp_core.registers[DSP_REG_A1] = dest[1];
4607: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4608:
1.1.1.6 root 4609: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4610:
4611: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4612: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4613: }
4614:
1.1.1.6 root 4615: static void dsp_add_y_b(void)
1.1 root 4616: {
1.1.1.6 root 4617: Uint32 source[3], dest[3];
1.1.1.2 root 4618: Uint16 newsr;
1.1 root 4619:
1.1.1.6 root 4620: dest[0] = dsp_core.registers[DSP_REG_B2];
4621: dest[1] = dsp_core.registers[DSP_REG_B1];
4622: dest[2] = dsp_core.registers[DSP_REG_B0];
4623:
4624: source[1] = dsp_core.registers[DSP_REG_Y1];
4625: source[2] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4626: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4627:
1.1.1.6 root 4628: newsr = dsp_add56(source, dest);
1.1 root 4629:
1.1.1.6 root 4630: dsp_core.registers[DSP_REG_B2] = dest[0];
4631: dsp_core.registers[DSP_REG_B1] = dest[1];
4632: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4633:
1.1.1.6 root 4634: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4635:
1.1.1.6 root 4636: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4637: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4638: }
4639:
1.1.1.6 root 4640: static void dsp_add_x0_a(void)
1.1 root 4641: {
1.1.1.6 root 4642: Uint32 source[3], dest[3];
4643: Uint16 newsr;
1.1 root 4644:
1.1.1.6 root 4645: dest[0] = dsp_core.registers[DSP_REG_A2];
4646: dest[1] = dsp_core.registers[DSP_REG_A1];
4647: dest[2] = dsp_core.registers[DSP_REG_A0];
4648:
4649: source[2] = 0;
4650: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4651: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4652:
4653: newsr = dsp_add56(source, dest);
4654:
4655: dsp_core.registers[DSP_REG_A2] = dest[0];
4656: dsp_core.registers[DSP_REG_A1] = dest[1];
4657: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4658:
1.1.1.6 root 4659: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4660:
1.1.1.6 root 4661: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4662: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4663: }
4664:
1.1.1.6 root 4665: static void dsp_add_x0_b(void)
1.1 root 4666: {
1.1.1.6 root 4667: Uint32 source[3], dest[3];
4668: Uint16 newsr;
4669:
4670: dest[0] = dsp_core.registers[DSP_REG_B2];
4671: dest[1] = dsp_core.registers[DSP_REG_B1];
4672: dest[2] = dsp_core.registers[DSP_REG_B0];
4673:
4674: source[2] = 0;
4675: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4676: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4677:
1.1.1.6 root 4678: newsr = dsp_add56(source, dest);
1.1 root 4679:
1.1.1.6 root 4680: dsp_core.registers[DSP_REG_B2] = dest[0];
4681: dsp_core.registers[DSP_REG_B1] = dest[1];
4682: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4683:
1.1.1.6 root 4684: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4685:
1.1.1.6 root 4686: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4687: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4688: }
4689:
1.1.1.6 root 4690: static void dsp_add_y0_a(void)
1.1 root 4691: {
1.1.1.6 root 4692: Uint32 source[3], dest[3];
4693: Uint16 newsr;
1.1 root 4694:
1.1.1.6 root 4695: dest[0] = dsp_core.registers[DSP_REG_A2];
4696: dest[1] = dsp_core.registers[DSP_REG_A1];
4697: dest[2] = dsp_core.registers[DSP_REG_A0];
4698:
4699: source[2] = 0;
4700: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4701: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4702:
1.1.1.6 root 4703: newsr = dsp_add56(source, dest);
4704:
4705: dsp_core.registers[DSP_REG_A2] = dest[0];
4706: dsp_core.registers[DSP_REG_A1] = dest[1];
4707: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4708:
1.1.1.6 root 4709: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4710:
1.1.1.6 root 4711: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4712: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4713: }
4714:
1.1.1.6 root 4715: static void dsp_add_y0_b(void)
1.1 root 4716: {
1.1.1.6 root 4717: Uint32 source[3], dest[3];
1.1.1.2 root 4718: Uint16 newsr;
1.1 root 4719:
1.1.1.6 root 4720: dest[0] = dsp_core.registers[DSP_REG_B2];
4721: dest[1] = dsp_core.registers[DSP_REG_B1];
4722: dest[2] = dsp_core.registers[DSP_REG_B0];
4723:
4724: source[2] = 0;
4725: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4726: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4727:
4728: newsr = dsp_add56(source, dest);
4729:
1.1.1.6 root 4730: dsp_core.registers[DSP_REG_B2] = dest[0];
4731: dsp_core.registers[DSP_REG_B1] = dest[1];
4732: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4733:
1.1.1.6 root 4734: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4735:
1.1.1.6 root 4736: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4737: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4738: }
4739:
1.1.1.6 root 4740: static void dsp_add_x1_a(void)
1.1 root 4741: {
1.1.1.6 root 4742: Uint32 source[3], dest[3];
1.1.1.2 root 4743: Uint16 newsr;
1.1 root 4744:
1.1.1.6 root 4745: dest[0] = dsp_core.registers[DSP_REG_A2];
4746: dest[1] = dsp_core.registers[DSP_REG_A1];
4747: dest[2] = dsp_core.registers[DSP_REG_A0];
4748:
4749: source[2] = 0;
4750: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4751: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4752:
4753: newsr = dsp_add56(source, dest);
4754:
1.1.1.6 root 4755: dsp_core.registers[DSP_REG_A2] = dest[0];
4756: dsp_core.registers[DSP_REG_A1] = dest[1];
4757: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4758:
1.1.1.6 root 4759: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4760:
1.1.1.6 root 4761: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4762: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4763: }
4764:
1.1.1.6 root 4765: static void dsp_add_x1_b(void)
1.1 root 4766: {
1.1.1.6 root 4767: Uint32 source[3], dest[3];
4768: Uint16 newsr;
4769:
4770: dest[0] = dsp_core.registers[DSP_REG_B2];
4771: dest[1] = dsp_core.registers[DSP_REG_B1];
4772: dest[2] = dsp_core.registers[DSP_REG_B0];
4773:
4774: source[2] = 0;
4775: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4776: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4777:
4778: newsr = dsp_add56(source, dest);
4779:
4780: dsp_core.registers[DSP_REG_B2] = dest[0];
4781: dsp_core.registers[DSP_REG_B1] = dest[1];
4782: dsp_core.registers[DSP_REG_B0] = dest[2];
4783:
4784: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4785:
4786: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4787: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4788: }
4789:
1.1.1.6 root 4790: static void dsp_add_y1_a(void)
1.1 root 4791: {
1.1.1.6 root 4792: Uint32 source[3], dest[3];
4793: Uint16 newsr;
1.1 root 4794:
1.1.1.6 root 4795: dest[0] = dsp_core.registers[DSP_REG_A2];
4796: dest[1] = dsp_core.registers[DSP_REG_A1];
4797: dest[2] = dsp_core.registers[DSP_REG_A0];
4798:
4799: source[2] = 0;
4800: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4801: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4802:
1.1.1.6 root 4803: newsr = dsp_add56(source, dest);
1.1 root 4804:
1.1.1.6 root 4805: dsp_core.registers[DSP_REG_A2] = dest[0];
4806: dsp_core.registers[DSP_REG_A1] = dest[1];
4807: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4808:
1.1.1.6 root 4809: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4810:
1.1.1.6 root 4811: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4812: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4813: }
4814:
1.1.1.6 root 4815: static void dsp_add_y1_b(void)
1.1 root 4816: {
1.1.1.6 root 4817: Uint32 source[3], dest[3];
4818: Uint16 newsr;
1.1 root 4819:
1.1.1.6 root 4820: dest[0] = dsp_core.registers[DSP_REG_B2];
4821: dest[1] = dsp_core.registers[DSP_REG_B1];
4822: dest[2] = dsp_core.registers[DSP_REG_B0];
4823:
4824: source[2] = 0;
4825: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4826: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4827:
1.1.1.6 root 4828: newsr = dsp_add56(source, dest);
1.1 root 4829:
1.1.1.6 root 4830: dsp_core.registers[DSP_REG_B2] = dest[0];
4831: dsp_core.registers[DSP_REG_B1] = dest[1];
4832: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4833:
1.1.1.6 root 4834: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4835:
1.1.1.6 root 4836: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4837: dsp_core.registers[DSP_REG_SR] |= newsr;
4838: }
1.1 root 4839:
1.1.1.6 root 4840: static void dsp_addl_b_a(void)
4841: {
4842: Uint32 source[3], dest[3];
4843: Uint16 newsr;
1.1.1.2 root 4844:
1.1.1.6 root 4845: dest[0] = dsp_core.registers[DSP_REG_A2];
4846: dest[1] = dsp_core.registers[DSP_REG_A1];
4847: dest[2] = dsp_core.registers[DSP_REG_A0];
4848: newsr = dsp_asl56(dest);
1.1 root 4849:
1.1.1.6 root 4850: source[0] = dsp_core.registers[DSP_REG_B2];
4851: source[1] = dsp_core.registers[DSP_REG_B1];
4852: source[2] = dsp_core.registers[DSP_REG_B0];
4853: newsr |= dsp_add56(source, dest);
1.1 root 4854:
1.1.1.6 root 4855: dsp_core.registers[DSP_REG_A2] = dest[0];
4856: dsp_core.registers[DSP_REG_A1] = dest[1];
4857: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4858:
1.1.1.6 root 4859: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4860:
1.1.1.6 root 4861: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4862: dsp_core.registers[DSP_REG_SR] |= newsr;
4863: }
1.1 root 4864:
1.1.1.6 root 4865: static void dsp_addl_a_b(void)
4866: {
4867: Uint32 source[3], dest[3];
4868: Uint16 newsr;
1.1 root 4869:
1.1.1.6 root 4870: dest[0] = dsp_core.registers[DSP_REG_B2];
4871: dest[1] = dsp_core.registers[DSP_REG_B1];
4872: dest[2] = dsp_core.registers[DSP_REG_B0];
4873: newsr = dsp_asl56(dest);
1.1 root 4874:
1.1.1.6 root 4875: source[0] = dsp_core.registers[DSP_REG_A2];
4876: source[1] = dsp_core.registers[DSP_REG_A1];
4877: source[2] = dsp_core.registers[DSP_REG_A0];
4878: newsr |= dsp_add56(source, dest);
4879:
4880: dsp_core.registers[DSP_REG_B2] = dest[0];
4881: dsp_core.registers[DSP_REG_B1] = dest[1];
4882: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4883:
1.1.1.6 root 4884: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4885:
1.1.1.6 root 4886: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4887: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4888: }
4889:
1.1.1.6 root 4890: static void dsp_addr_b_a(void)
1.1 root 4891: {
1.1.1.6 root 4892: Uint32 source[3], dest[3];
4893: Uint16 newsr;
4894:
4895: dest[0] = dsp_core.registers[DSP_REG_A2];
4896: dest[1] = dsp_core.registers[DSP_REG_A1];
4897: dest[2] = dsp_core.registers[DSP_REG_A0];
4898: newsr = dsp_asr56(dest);
4899:
4900: source[0] = dsp_core.registers[DSP_REG_B2];
4901: source[1] = dsp_core.registers[DSP_REG_B1];
4902: source[2] = dsp_core.registers[DSP_REG_B0];
4903: newsr |= dsp_add56(source, dest);
4904:
4905: dsp_core.registers[DSP_REG_A2] = dest[0];
4906: dsp_core.registers[DSP_REG_A1] = dest[1];
4907: dsp_core.registers[DSP_REG_A0] = dest[2];
4908:
4909: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4910:
4911: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4912: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4913: }
4914:
1.1.1.6 root 4915: static void dsp_addr_a_b(void)
1.1 root 4916: {
1.1.1.6 root 4917: Uint32 source[3], dest[3];
4918: Uint16 newsr;
4919:
4920: dest[0] = dsp_core.registers[DSP_REG_B2];
4921: dest[1] = dsp_core.registers[DSP_REG_B1];
4922: dest[2] = dsp_core.registers[DSP_REG_B0];
4923: newsr = dsp_asr56(dest);
4924:
4925: source[0] = dsp_core.registers[DSP_REG_A2];
4926: source[1] = dsp_core.registers[DSP_REG_A1];
4927: source[2] = dsp_core.registers[DSP_REG_A0];
4928: newsr |= dsp_add56(source, dest);
1.1 root 4929:
1.1.1.6 root 4930: dsp_core.registers[DSP_REG_B2] = dest[0];
4931: dsp_core.registers[DSP_REG_B1] = dest[1];
4932: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4933:
1.1.1.6 root 4934: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4935:
1.1.1.6 root 4936: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4937: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4938: }
4939:
1.1.1.6 root 4940: static void dsp_and_x0_a(void)
1.1 root 4941: {
1.1.1.6 root 4942: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X0];
1.1 root 4943:
1.1.1.6 root 4944: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4945: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4946: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4947: }
1.1 root 4948:
1.1.1.6 root 4949: static void dsp_and_x0_b(void)
4950: {
4951: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X0];
1.1 root 4952:
1.1.1.6 root 4953: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4954: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4955: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
1.1 root 4956: }
4957:
1.1.1.6 root 4958: static void dsp_and_y0_a(void)
1.1 root 4959: {
1.1.1.6 root 4960: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y0];
1.1 root 4961:
1.1.1.6 root 4962: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4963: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4964: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4965: }
1.1 root 4966:
1.1.1.6 root 4967: static void dsp_and_y0_b(void)
4968: {
4969: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y0];
1.1 root 4970:
1.1.1.6 root 4971: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4972: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4973: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
4974: }
1.1 root 4975:
1.1.1.6 root 4976: static void dsp_and_x1_a(void)
4977: {
4978: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X1];
1.1.1.2 root 4979:
1.1.1.6 root 4980: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4981: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4982: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
1.1 root 4983: }
4984:
1.1.1.6 root 4985: static void dsp_and_x1_b(void)
1.1 root 4986: {
1.1.1.6 root 4987: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X1];
4988:
4989: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4990: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4991: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
4992: }
1.1 root 4993:
1.1.1.6 root 4994: static void dsp_and_y1_a(void)
4995: {
4996: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y1];
1.1 root 4997:
1.1.1.6 root 4998: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4999: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5000: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5001: }
1.1 root 5002:
1.1.1.6 root 5003: static void dsp_and_y1_b(void)
5004: {
5005: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y1];
1.1.1.2 root 5006:
1.1.1.6 root 5007: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5008: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5009: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
1.1 root 5010: }
5011:
1.1.1.7 root 5012: static void dsp_asl_a(void)
1.1 root 5013: {
1.1.1.6 root 5014: Uint32 dest[3];
5015: Uint16 newsr;
1.1 root 5016:
1.1.1.6 root 5017: dest[0] = dsp_core.registers[DSP_REG_A2];
5018: dest[1] = dsp_core.registers[DSP_REG_A1];
5019: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 5020:
1.1.1.6 root 5021: newsr = dsp_asl56(dest);
5022:
5023: dsp_core.registers[DSP_REG_A2] = dest[0];
5024: dsp_core.registers[DSP_REG_A1] = dest[1];
5025: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 5026:
1.1.1.6 root 5027: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5028: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1.1.2 root 5029:
1.1.1.6 root 5030: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 5031: }
5032:
1.1.1.7 root 5033: static void dsp_asl_b(void)
1.1 root 5034: {
1.1.1.6 root 5035: Uint32 dest[3];
1.1.1.2 root 5036: Uint16 newsr;
1.1 root 5037:
1.1.1.6 root 5038: dest[0] = dsp_core.registers[DSP_REG_B2];
5039: dest[1] = dsp_core.registers[DSP_REG_B1];
5040: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 5041:
1.1.1.6 root 5042: newsr = dsp_asl56(dest);
1.1 root 5043:
1.1.1.6 root 5044: dsp_core.registers[DSP_REG_B2] = dest[0];
5045: dsp_core.registers[DSP_REG_B1] = dest[1];
5046: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 5047:
1.1.1.6 root 5048: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5049: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 5050:
1.1.1.6 root 5051: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 5052: }
5053:
1.1.1.7 root 5054: static void dsp_asr_a(void)
1.1 root 5055: {
1.1.1.6 root 5056: Uint32 dest[3];
5057: Uint16 newsr;
5058:
5059: dest[0] = dsp_core.registers[DSP_REG_A2];
5060: dest[1] = dsp_core.registers[DSP_REG_A1];
5061: dest[2] = dsp_core.registers[DSP_REG_A0];
5062:
5063: newsr = dsp_asr56(dest);
5064:
5065: dsp_core.registers[DSP_REG_A2] = dest[0];
5066: dsp_core.registers[DSP_REG_A1] = dest[1];
5067: dsp_core.registers[DSP_REG_A0] = dest[2];
5068:
5069: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5070: dsp_core.registers[DSP_REG_SR] |= newsr;
5071:
5072: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5073: }
5074:
1.1.1.7 root 5075: static void dsp_asr_b(void)
1.1.1.6 root 5076: {
5077: Uint32 dest[3];
5078: Uint16 newsr;
5079:
5080: dest[0] = dsp_core.registers[DSP_REG_B2];
5081: dest[1] = dsp_core.registers[DSP_REG_B1];
5082: dest[2] = dsp_core.registers[DSP_REG_B0];
5083:
5084: newsr = dsp_asr56(dest);
5085:
5086: dsp_core.registers[DSP_REG_B2] = dest[0];
5087: dsp_core.registers[DSP_REG_B1] = dest[1];
5088: dsp_core.registers[DSP_REG_B0] = dest[2];
5089:
5090: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5091: dsp_core.registers[DSP_REG_SR] |= newsr;
5092:
5093: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5094: }
5095:
5096: static void dsp_clr_a(void)
5097: {
1.1.1.7 root 5098: dsp_core.registers[DSP_REG_A2] = 0;
5099: dsp_core.registers[DSP_REG_A1] = 0;
5100: dsp_core.registers[DSP_REG_A0] = 0;
1.1.1.6 root 5101:
5102: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5103: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5104: }
5105:
5106: static void dsp_clr_b(void)
5107: {
1.1.1.7 root 5108: dsp_core.registers[DSP_REG_B2] = 0;
5109: dsp_core.registers[DSP_REG_B1] = 0;
5110: dsp_core.registers[DSP_REG_B0] = 0;
1.1.1.6 root 5111:
5112: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5113: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5114: }
5115:
5116: static void dsp_cmp_b_a(void)
5117: {
5118: Uint32 source[3], dest[3];
5119: Uint16 newsr;
5120:
5121: dest[0] = dsp_core.registers[DSP_REG_A2];
5122: dest[1] = dsp_core.registers[DSP_REG_A1];
5123: dest[2] = dsp_core.registers[DSP_REG_A0];
5124:
5125: source[0] = dsp_core.registers[DSP_REG_B2];
5126: source[1] = dsp_core.registers[DSP_REG_B1];
5127: source[2] = dsp_core.registers[DSP_REG_B0];
5128:
5129: newsr = dsp_sub56(source, dest);
5130:
5131: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5132:
5133: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5134: dsp_core.registers[DSP_REG_SR] |= newsr;
5135: }
5136:
5137: static void dsp_cmp_a_b(void)
5138: {
5139: Uint32 source[3], dest[3];
5140: Uint16 newsr;
5141:
5142: dest[0] = dsp_core.registers[DSP_REG_B2];
5143: dest[1] = dsp_core.registers[DSP_REG_B1];
5144: dest[2] = dsp_core.registers[DSP_REG_B0];
5145:
5146: source[0] = dsp_core.registers[DSP_REG_A2];
5147: source[1] = dsp_core.registers[DSP_REG_A1];
5148: source[2] = dsp_core.registers[DSP_REG_A0];
5149:
5150: newsr = dsp_sub56(source, dest);
5151:
5152: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5153:
5154: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5155: dsp_core.registers[DSP_REG_SR] |= newsr;
5156: }
5157:
5158: static void dsp_cmp_x0_a(void)
5159: {
5160: Uint32 source[3], dest[3];
5161: Uint16 newsr;
5162:
5163: dest[2] = dsp_core.registers[DSP_REG_A0];
5164: dest[1] = dsp_core.registers[DSP_REG_A1];
5165: dest[0] = dsp_core.registers[DSP_REG_A2];
5166:
5167: source[2] = 0;
5168: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5169: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5170:
5171: newsr = dsp_sub56(source, dest);
5172:
5173: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5174:
5175: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5176: dsp_core.registers[DSP_REG_SR] |= newsr;
5177: }
5178:
5179: static void dsp_cmp_x0_b(void)
5180: {
5181: Uint32 source[3], dest[3];
5182: Uint16 newsr;
5183:
5184: dest[0] = dsp_core.registers[DSP_REG_B2];
5185: dest[1] = dsp_core.registers[DSP_REG_B1];
5186: dest[2] = dsp_core.registers[DSP_REG_B0];
5187:
5188: source[2] = 0;
5189: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5190: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5191:
5192: newsr = dsp_sub56(source, dest);
5193:
5194: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5195:
5196: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5197: dsp_core.registers[DSP_REG_SR] |= newsr;
5198: }
5199:
5200: static void dsp_cmp_y0_a(void)
5201: {
5202: Uint32 source[3], dest[3];
5203: Uint16 newsr;
5204:
5205: dest[2] = dsp_core.registers[DSP_REG_A0];
5206: dest[1] = dsp_core.registers[DSP_REG_A1];
5207: dest[0] = dsp_core.registers[DSP_REG_A2];
5208:
5209: source[2] = 0;
5210: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5211: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5212:
5213: newsr = dsp_sub56(source, dest);
5214:
5215: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5216:
5217: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5218: dsp_core.registers[DSP_REG_SR] |= newsr;
5219: }
5220:
5221: static void dsp_cmp_y0_b(void)
5222: {
5223: Uint32 source[3], dest[3];
5224: Uint16 newsr;
5225:
5226: dest[0] = dsp_core.registers[DSP_REG_B2];
5227: dest[1] = dsp_core.registers[DSP_REG_B1];
5228: dest[2] = dsp_core.registers[DSP_REG_B0];
5229:
5230: source[2] = 0;
5231: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5232: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5233:
5234: newsr = dsp_sub56(source, dest);
5235:
5236: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5237:
5238: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5239: dsp_core.registers[DSP_REG_SR] |= newsr;
5240: }
5241: static void dsp_cmp_x1_a(void)
5242: {
5243: Uint32 source[3], dest[3];
5244: Uint16 newsr;
5245:
5246: dest[2] = dsp_core.registers[DSP_REG_A0];
5247: dest[1] = dsp_core.registers[DSP_REG_A1];
5248: dest[0] = dsp_core.registers[DSP_REG_A2];
5249:
5250: source[2] = 0;
5251: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5252: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5253:
5254: newsr = dsp_sub56(source, dest);
5255:
5256: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5257:
5258: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5259: dsp_core.registers[DSP_REG_SR] |= newsr;
5260: }
5261:
5262: static void dsp_cmp_x1_b(void)
5263: {
5264: Uint32 source[3], dest[3];
5265: Uint16 newsr;
5266:
5267: dest[0] = dsp_core.registers[DSP_REG_B2];
5268: dest[1] = dsp_core.registers[DSP_REG_B1];
5269: dest[2] = dsp_core.registers[DSP_REG_B0];
5270:
5271: source[2] = 0;
5272: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5273: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5274:
5275: newsr = dsp_sub56(source, dest);
5276:
5277: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5278:
5279: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5280: dsp_core.registers[DSP_REG_SR] |= newsr;
5281: }
5282:
5283: static void dsp_cmp_y1_a(void)
5284: {
5285: Uint32 source[3], dest[3];
5286: Uint16 newsr;
5287:
5288: dest[2] = dsp_core.registers[DSP_REG_A0];
5289: dest[1] = dsp_core.registers[DSP_REG_A1];
5290: dest[0] = dsp_core.registers[DSP_REG_A2];
5291:
5292: source[2] = 0;
5293: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5294: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5295:
5296: newsr = dsp_sub56(source, dest);
5297:
5298: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5299:
5300: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5301: dsp_core.registers[DSP_REG_SR] |= newsr;
5302: }
5303:
5304: static void dsp_cmp_y1_b(void)
5305: {
5306: Uint32 source[3], dest[3];
5307: Uint16 newsr;
5308:
5309: dest[0] = dsp_core.registers[DSP_REG_B2];
5310: dest[1] = dsp_core.registers[DSP_REG_B1];
5311: dest[2] = dsp_core.registers[DSP_REG_B0];
5312:
5313: source[2] = 0;
5314: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5315: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5316:
5317: newsr = dsp_sub56(source, dest);
5318:
5319: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5320:
5321: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5322: dsp_core.registers[DSP_REG_SR] |= newsr;
5323: }
5324:
5325: static void dsp_cmpm_b_a(void)
5326: {
5327: Uint32 source[3], dest[3];
5328: Uint16 newsr;
5329:
5330: dest[0] = dsp_core.registers[DSP_REG_A2];
5331: dest[1] = dsp_core.registers[DSP_REG_A1];
5332: dest[2] = dsp_core.registers[DSP_REG_A0];
5333: dsp_abs56(dest);
5334:
5335: source[0] = dsp_core.registers[DSP_REG_B2];
5336: source[1] = dsp_core.registers[DSP_REG_B1];
5337: source[2] = dsp_core.registers[DSP_REG_B0];
5338: dsp_abs56(source);
5339:
5340: newsr = dsp_sub56(source, dest);
5341:
5342: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5343:
5344: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5345: dsp_core.registers[DSP_REG_SR] |= newsr;
5346: }
5347:
5348: static void dsp_cmpm_a_b(void)
5349: {
5350: Uint32 source[3], dest[3];
5351: Uint16 newsr;
5352:
5353: dest[0] = dsp_core.registers[DSP_REG_B2];
5354: dest[1] = dsp_core.registers[DSP_REG_B1];
5355: dest[2] = dsp_core.registers[DSP_REG_B0];
5356: dsp_abs56(dest);
5357:
5358: source[0] = dsp_core.registers[DSP_REG_A2];
5359: source[1] = dsp_core.registers[DSP_REG_A1];
5360: source[2] = dsp_core.registers[DSP_REG_A0];
5361: dsp_abs56(source);
5362:
5363: newsr = dsp_sub56(source, dest);
5364:
5365: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5366:
5367: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5368: dsp_core.registers[DSP_REG_SR] |= newsr;
5369: }
5370:
5371: static void dsp_cmpm_x0_a(void)
5372: {
5373: Uint32 source[3], dest[3];
5374: Uint16 newsr;
5375:
5376: dest[2] = dsp_core.registers[DSP_REG_A0];
5377: dest[1] = dsp_core.registers[DSP_REG_A1];
5378: dest[0] = dsp_core.registers[DSP_REG_A2];
5379: dsp_abs56(dest);
5380:
5381: source[2] = 0;
5382: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5383: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5384: dsp_abs56(source);
5385:
5386: newsr = dsp_sub56(source, dest);
5387:
5388: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5389:
5390: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5391: dsp_core.registers[DSP_REG_SR] |= newsr;
5392: }
5393:
5394: static void dsp_cmpm_x0_b(void)
5395: {
5396: Uint32 source[3], dest[3];
5397: Uint16 newsr;
5398:
5399: dest[0] = dsp_core.registers[DSP_REG_B2];
5400: dest[1] = dsp_core.registers[DSP_REG_B1];
5401: dest[2] = dsp_core.registers[DSP_REG_B0];
5402: dsp_abs56(dest);
5403:
5404: source[2] = 0;
5405: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5406: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5407: dsp_abs56(source);
5408:
5409: newsr = dsp_sub56(source, dest);
5410:
5411: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5412:
5413: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5414: dsp_core.registers[DSP_REG_SR] |= newsr;
5415: }
5416:
5417: static void dsp_cmpm_y0_a(void)
5418: {
5419: Uint32 source[3], dest[3];
5420: Uint16 newsr;
5421:
5422: dest[2] = dsp_core.registers[DSP_REG_A0];
5423: dest[1] = dsp_core.registers[DSP_REG_A1];
5424: dest[0] = dsp_core.registers[DSP_REG_A2];
5425: dsp_abs56(dest);
5426:
5427: source[2] = 0;
5428: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5429: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5430: dsp_abs56(source);
5431:
5432: newsr = dsp_sub56(source, dest);
5433:
5434: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5435:
5436: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5437: dsp_core.registers[DSP_REG_SR] |= newsr;
5438: }
5439:
5440: static void dsp_cmpm_y0_b(void)
5441: {
5442: Uint32 source[3], dest[3];
5443: Uint16 newsr;
5444:
5445: dest[0] = dsp_core.registers[DSP_REG_B2];
5446: dest[1] = dsp_core.registers[DSP_REG_B1];
5447: dest[2] = dsp_core.registers[DSP_REG_B0];
5448: dsp_abs56(dest);
5449:
5450: source[2] = 0;
5451: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5452: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5453: dsp_abs56(source);
5454:
5455: newsr = dsp_sub56(source, dest);
5456:
5457: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5458:
5459: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5460: dsp_core.registers[DSP_REG_SR] |= newsr;
5461: }
5462:
5463: static void dsp_cmpm_x1_a(void)
5464: {
5465: Uint32 source[3], dest[3];
5466: Uint16 newsr;
5467:
5468: dest[2] = dsp_core.registers[DSP_REG_A0];
5469: dest[1] = dsp_core.registers[DSP_REG_A1];
5470: dest[0] = dsp_core.registers[DSP_REG_A2];
5471: dsp_abs56(dest);
5472:
5473: source[2] = 0;
5474: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5475: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5476: dsp_abs56(source);
5477:
5478: newsr = dsp_sub56(source, dest);
5479:
5480: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5481:
5482: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5483: dsp_core.registers[DSP_REG_SR] |= newsr;
5484: }
5485:
5486: static void dsp_cmpm_x1_b(void)
5487: {
5488: Uint32 source[3], dest[3];
5489: Uint16 newsr;
5490:
5491: dest[0] = dsp_core.registers[DSP_REG_B2];
5492: dest[1] = dsp_core.registers[DSP_REG_B1];
5493: dest[2] = dsp_core.registers[DSP_REG_B0];
5494: dsp_abs56(dest);
5495:
5496: source[2] = 0;
5497: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5498: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5499: dsp_abs56(source);
5500:
5501: newsr = dsp_sub56(source, dest);
5502:
5503: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5504:
5505: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5506: dsp_core.registers[DSP_REG_SR] |= newsr;
5507: }
5508:
5509: static void dsp_cmpm_y1_a(void)
5510: {
5511: Uint32 source[3], dest[3];
5512: Uint16 newsr;
5513:
5514: dest[2] = dsp_core.registers[DSP_REG_A0];
5515: dest[1] = dsp_core.registers[DSP_REG_A1];
5516: dest[0] = dsp_core.registers[DSP_REG_A2];
5517: dsp_abs56(dest);
5518:
5519: source[2] = 0;
5520: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5521: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5522: dsp_abs56(source);
5523:
5524: newsr = dsp_sub56(source, dest);
5525:
5526: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5527:
5528: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5529: dsp_core.registers[DSP_REG_SR] |= newsr;
5530: }
5531:
5532: static void dsp_cmpm_y1_b(void)
5533: {
5534: Uint32 source[3], dest[3];
5535: Uint16 newsr;
5536:
5537: dest[0] = dsp_core.registers[DSP_REG_B2];
5538: dest[1] = dsp_core.registers[DSP_REG_B1];
5539: dest[2] = dsp_core.registers[DSP_REG_B0];
5540: dsp_abs56(dest);
5541:
5542: source[2] = 0;
5543: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5544: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5545: dsp_abs56(source);
5546:
5547: newsr = dsp_sub56(source, dest);
5548:
5549: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5550:
5551: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5552: dsp_core.registers[DSP_REG_SR] |= newsr;
5553: }
5554:
5555: static void dsp_eor_x0_a(void)
5556: {
5557: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X0];
5558: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5559:
5560: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5561: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5562: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5563: }
5564:
5565: static void dsp_eor_x0_b(void)
5566: {
5567: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X0];
5568: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5569:
5570: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5571: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5572: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5573: }
5574:
5575: static void dsp_eor_y0_a(void)
5576: {
5577: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y0];
5578: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5579:
5580: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5581: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5582: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5583: }
5584:
5585: static void dsp_eor_y0_b(void)
5586: {
5587: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y0];
5588: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5589:
5590: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5591: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5592: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5593: }
5594:
5595: static void dsp_eor_x1_a(void)
5596: {
5597: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X1];
5598: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5599:
5600: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5601: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5602: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5603: }
5604:
5605: static void dsp_eor_x1_b(void)
5606: {
5607: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X1];
5608: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5609:
5610: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5611: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5612: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5613: }
5614:
5615: static void dsp_eor_y1_a(void)
5616: {
5617: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y1];
5618: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5619:
5620: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5621: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5622: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5623: }
5624:
5625: static void dsp_eor_y1_b(void)
5626: {
5627: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y1];
5628: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5629:
5630: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5631: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5632: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5633: }
5634:
5635: static void dsp_lsl_a(void)
5636: {
5637: Uint32 newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
5638:
5639: dsp_core.registers[DSP_REG_A1] <<= 1;
5640: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
5641:
5642: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5643: dsp_core.registers[DSP_REG_SR] |= newcarry;
5644: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5645: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5646: }
5647:
5648: static void dsp_lsl_b(void)
5649: {
5650: Uint32 newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
5651:
5652: dsp_core.registers[DSP_REG_B1] <<= 1;
5653: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
5654:
5655: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5656: dsp_core.registers[DSP_REG_SR] |= newcarry;
5657: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5658: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5659: }
5660:
5661: static void dsp_lsr_a(void)
5662: {
5663: Uint32 newcarry = dsp_core.registers[DSP_REG_A1] & 1;
5664: dsp_core.registers[DSP_REG_A1] >>= 1;
5665:
5666: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5667: dsp_core.registers[DSP_REG_SR] |= newcarry;
5668: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5669: }
5670:
5671: static void dsp_lsr_b(void)
5672: {
5673: Uint32 newcarry = dsp_core.registers[DSP_REG_B1] & 1;
5674: dsp_core.registers[DSP_REG_B1] >>= 1;
5675:
5676: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5677: dsp_core.registers[DSP_REG_SR] |= newcarry;
5678: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5679: }
5680:
5681: static void dsp_mac_p_x0_x0_a(void)
5682: {
5683: Uint32 source[3], dest[3];
5684: Uint16 newsr;
5685:
5686: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5687:
5688: dest[0] = dsp_core.registers[DSP_REG_A2];
5689: dest[1] = dsp_core.registers[DSP_REG_A1];
5690: dest[2] = dsp_core.registers[DSP_REG_A0];
5691: newsr = dsp_add56(source, dest);
5692:
5693: dsp_core.registers[DSP_REG_A2] = dest[0];
5694: dsp_core.registers[DSP_REG_A1] = dest[1];
5695: dsp_core.registers[DSP_REG_A0] = dest[2];
5696:
5697: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5698:
5699: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5700: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5701: }
5702:
5703: static void dsp_mac_m_x0_x0_a(void)
5704: {
5705: Uint32 source[3], dest[3];
5706: Uint16 newsr;
5707:
5708: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5709:
5710: dest[0] = dsp_core.registers[DSP_REG_A2];
5711: dest[1] = dsp_core.registers[DSP_REG_A1];
5712: dest[2] = dsp_core.registers[DSP_REG_A0];
5713: newsr = dsp_add56(source, dest);
5714:
5715: dsp_core.registers[DSP_REG_A2] = dest[0];
5716: dsp_core.registers[DSP_REG_A1] = dest[1];
5717: dsp_core.registers[DSP_REG_A0] = dest[2];
5718:
5719: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5720:
5721: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5722: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5723: }
5724: static void dsp_mac_p_x0_x0_b(void)
5725: {
5726: Uint32 source[3], dest[3];
5727: Uint16 newsr;
5728:
5729: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5730:
5731: dest[0] = dsp_core.registers[DSP_REG_B2];
5732: dest[1] = dsp_core.registers[DSP_REG_B1];
5733: dest[2] = dsp_core.registers[DSP_REG_B0];
5734: newsr = dsp_add56(source, dest);
5735:
5736: dsp_core.registers[DSP_REG_B2] = dest[0];
5737: dsp_core.registers[DSP_REG_B1] = dest[1];
5738: dsp_core.registers[DSP_REG_B0] = dest[2];
5739:
5740: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5741:
5742: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5743: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5744: }
5745:
5746: static void dsp_mac_m_x0_x0_b(void)
5747: {
5748: Uint32 source[3], dest[3];
5749: Uint16 newsr;
5750:
5751: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5752:
5753: dest[0] = dsp_core.registers[DSP_REG_B2];
5754: dest[1] = dsp_core.registers[DSP_REG_B1];
5755: dest[2] = dsp_core.registers[DSP_REG_B0];
5756: newsr = dsp_add56(source, dest);
5757:
5758: dsp_core.registers[DSP_REG_B2] = dest[0];
5759: dsp_core.registers[DSP_REG_B1] = dest[1];
5760: dsp_core.registers[DSP_REG_B0] = dest[2];
5761:
5762: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5763:
5764: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5765: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5766: }
5767:
5768: static void dsp_mac_p_y0_y0_a(void)
5769: {
5770: Uint32 source[3], dest[3];
5771: Uint16 newsr;
5772:
5773: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5774:
5775: dest[0] = dsp_core.registers[DSP_REG_A2];
5776: dest[1] = dsp_core.registers[DSP_REG_A1];
5777: dest[2] = dsp_core.registers[DSP_REG_A0];
5778: newsr = dsp_add56(source, dest);
5779:
5780: dsp_core.registers[DSP_REG_A2] = dest[0];
5781: dsp_core.registers[DSP_REG_A1] = dest[1];
5782: dsp_core.registers[DSP_REG_A0] = dest[2];
5783:
5784: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5785:
5786: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5787: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5788: }
5789:
5790: static void dsp_mac_m_y0_y0_a(void)
5791: {
5792: Uint32 source[3], dest[3];
5793: Uint16 newsr;
5794:
5795: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5796:
5797: dest[0] = dsp_core.registers[DSP_REG_A2];
5798: dest[1] = dsp_core.registers[DSP_REG_A1];
5799: dest[2] = dsp_core.registers[DSP_REG_A0];
5800: newsr = dsp_add56(source, dest);
5801:
5802: dsp_core.registers[DSP_REG_A2] = dest[0];
5803: dsp_core.registers[DSP_REG_A1] = dest[1];
5804: dsp_core.registers[DSP_REG_A0] = dest[2];
5805:
5806: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5807:
5808: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5809: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5810: }
5811: static void dsp_mac_p_y0_y0_b(void)
5812: {
5813: Uint32 source[3], dest[3];
5814: Uint16 newsr;
5815:
5816: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5817:
5818: dest[0] = dsp_core.registers[DSP_REG_B2];
5819: dest[1] = dsp_core.registers[DSP_REG_B1];
5820: dest[2] = dsp_core.registers[DSP_REG_B0];
5821: newsr = dsp_add56(source, dest);
5822:
5823: dsp_core.registers[DSP_REG_B2] = dest[0];
5824: dsp_core.registers[DSP_REG_B1] = dest[1];
5825: dsp_core.registers[DSP_REG_B0] = dest[2];
5826:
5827: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5828:
5829: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5830: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5831: }
5832:
5833: static void dsp_mac_m_y0_y0_b(void)
5834: {
5835: Uint32 source[3], dest[3];
5836: Uint16 newsr;
5837:
5838: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5839:
5840: dest[0] = dsp_core.registers[DSP_REG_B2];
5841: dest[1] = dsp_core.registers[DSP_REG_B1];
5842: dest[2] = dsp_core.registers[DSP_REG_B0];
5843: newsr = dsp_add56(source, dest);
5844:
5845: dsp_core.registers[DSP_REG_B2] = dest[0];
5846: dsp_core.registers[DSP_REG_B1] = dest[1];
5847: dsp_core.registers[DSP_REG_B0] = dest[2];
5848:
5849: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5850:
5851: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5852: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5853: }
5854:
5855: static void dsp_mac_p_x1_x0_a(void)
5856: {
5857: Uint32 source[3], dest[3];
5858: Uint16 newsr;
5859:
5860: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5861:
5862: dest[0] = dsp_core.registers[DSP_REG_A2];
5863: dest[1] = dsp_core.registers[DSP_REG_A1];
5864: dest[2] = dsp_core.registers[DSP_REG_A0];
5865: newsr = dsp_add56(source, dest);
5866:
5867: dsp_core.registers[DSP_REG_A2] = dest[0];
5868: dsp_core.registers[DSP_REG_A1] = dest[1];
5869: dsp_core.registers[DSP_REG_A0] = dest[2];
5870:
5871: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5872:
5873: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5874: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5875: }
5876:
5877: static void dsp_mac_m_x1_x0_a(void)
5878: {
5879: Uint32 source[3], dest[3];
5880: Uint16 newsr;
5881:
5882: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5883:
5884: dest[0] = dsp_core.registers[DSP_REG_A2];
5885: dest[1] = dsp_core.registers[DSP_REG_A1];
5886: dest[2] = dsp_core.registers[DSP_REG_A0];
5887: newsr = dsp_add56(source, dest);
5888:
5889: dsp_core.registers[DSP_REG_A2] = dest[0];
5890: dsp_core.registers[DSP_REG_A1] = dest[1];
5891: dsp_core.registers[DSP_REG_A0] = dest[2];
5892:
5893: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5894:
5895: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5896: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5897: }
5898:
5899: static void dsp_mac_p_x1_x0_b(void)
5900: {
5901: Uint32 source[3], dest[3];
5902: Uint16 newsr;
5903:
5904: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5905:
5906: dest[0] = dsp_core.registers[DSP_REG_B2];
5907: dest[1] = dsp_core.registers[DSP_REG_B1];
5908: dest[2] = dsp_core.registers[DSP_REG_B0];
5909: newsr = dsp_add56(source, dest);
5910:
5911: dsp_core.registers[DSP_REG_B2] = dest[0];
5912: dsp_core.registers[DSP_REG_B1] = dest[1];
5913: dsp_core.registers[DSP_REG_B0] = dest[2];
5914:
5915: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5916:
5917: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5918: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5919: }
5920:
5921: static void dsp_mac_m_x1_x0_b(void)
5922: {
5923: Uint32 source[3], dest[3];
5924: Uint16 newsr;
5925:
5926: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5927:
5928: dest[0] = dsp_core.registers[DSP_REG_B2];
5929: dest[1] = dsp_core.registers[DSP_REG_B1];
5930: dest[2] = dsp_core.registers[DSP_REG_B0];
5931: newsr = dsp_add56(source, dest);
5932:
5933: dsp_core.registers[DSP_REG_B2] = dest[0];
5934: dsp_core.registers[DSP_REG_B1] = dest[1];
5935: dsp_core.registers[DSP_REG_B0] = dest[2];
5936:
5937: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5938:
5939: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5940: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5941: }
5942:
5943: static void dsp_mac_p_y1_y0_a(void)
5944: {
5945: Uint32 source[3], dest[3];
5946: Uint16 newsr;
5947:
5948: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5949:
5950: dest[0] = dsp_core.registers[DSP_REG_A2];
5951: dest[1] = dsp_core.registers[DSP_REG_A1];
5952: dest[2] = dsp_core.registers[DSP_REG_A0];
5953: newsr = dsp_add56(source, dest);
5954:
5955: dsp_core.registers[DSP_REG_A2] = dest[0];
5956: dsp_core.registers[DSP_REG_A1] = dest[1];
5957: dsp_core.registers[DSP_REG_A0] = dest[2];
5958:
5959: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5960:
5961: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5962: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5963: }
5964:
5965: static void dsp_mac_m_y1_y0_a(void)
5966: {
5967: Uint32 source[3], dest[3];
5968: Uint16 newsr;
5969:
5970: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5971:
5972: dest[0] = dsp_core.registers[DSP_REG_A2];
5973: dest[1] = dsp_core.registers[DSP_REG_A1];
5974: dest[2] = dsp_core.registers[DSP_REG_A0];
5975: newsr = dsp_add56(source, dest);
5976:
5977: dsp_core.registers[DSP_REG_A2] = dest[0];
5978: dsp_core.registers[DSP_REG_A1] = dest[1];
5979: dsp_core.registers[DSP_REG_A0] = dest[2];
5980:
5981: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5982:
5983: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5984: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5985: }
5986:
5987: static void dsp_mac_p_y1_y0_b(void)
5988: {
5989: Uint32 source[3], dest[3];
5990: Uint16 newsr;
5991:
5992: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5993:
5994: dest[0] = dsp_core.registers[DSP_REG_B2];
5995: dest[1] = dsp_core.registers[DSP_REG_B1];
5996: dest[2] = dsp_core.registers[DSP_REG_B0];
5997: newsr = dsp_add56(source, dest);
5998:
5999: dsp_core.registers[DSP_REG_B2] = dest[0];
6000: dsp_core.registers[DSP_REG_B1] = dest[1];
6001: dsp_core.registers[DSP_REG_B0] = dest[2];
6002:
6003: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6004:
6005: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6006: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6007: }
6008:
6009: static void dsp_mac_m_y1_y0_b(void)
6010: {
6011: Uint32 source[3], dest[3];
6012: Uint16 newsr;
6013:
6014: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6015:
6016: dest[0] = dsp_core.registers[DSP_REG_B2];
6017: dest[1] = dsp_core.registers[DSP_REG_B1];
6018: dest[2] = dsp_core.registers[DSP_REG_B0];
6019: newsr = dsp_add56(source, dest);
6020:
6021: dsp_core.registers[DSP_REG_B2] = dest[0];
6022: dsp_core.registers[DSP_REG_B1] = dest[1];
6023: dsp_core.registers[DSP_REG_B0] = dest[2];
6024:
6025: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6026:
6027: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6028: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6029: }
6030:
6031: static void dsp_mac_p_x0_y1_a(void)
6032: {
6033: Uint32 source[3], dest[3];
6034: Uint16 newsr;
6035:
6036: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6037:
6038: dest[0] = dsp_core.registers[DSP_REG_A2];
6039: dest[1] = dsp_core.registers[DSP_REG_A1];
6040: dest[2] = dsp_core.registers[DSP_REG_A0];
6041: newsr = dsp_add56(source, dest);
6042:
6043: dsp_core.registers[DSP_REG_A2] = dest[0];
6044: dsp_core.registers[DSP_REG_A1] = dest[1];
6045: dsp_core.registers[DSP_REG_A0] = dest[2];
6046:
6047: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6048:
6049: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6050: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6051: }
6052:
6053: static void dsp_mac_m_x0_y1_a(void)
6054: {
6055: Uint32 source[3], dest[3];
6056: Uint16 newsr;
6057:
6058: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6059:
6060: dest[0] = dsp_core.registers[DSP_REG_A2];
6061: dest[1] = dsp_core.registers[DSP_REG_A1];
6062: dest[2] = dsp_core.registers[DSP_REG_A0];
6063: newsr = dsp_add56(source, dest);
6064:
6065: dsp_core.registers[DSP_REG_A2] = dest[0];
6066: dsp_core.registers[DSP_REG_A1] = dest[1];
6067: dsp_core.registers[DSP_REG_A0] = dest[2];
6068:
6069: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6070:
6071: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6072: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6073: }
6074:
6075: static void dsp_mac_p_x0_y1_b(void)
6076: {
6077: Uint32 source[3], dest[3];
6078: Uint16 newsr;
6079:
6080: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6081:
6082: dest[0] = dsp_core.registers[DSP_REG_B2];
6083: dest[1] = dsp_core.registers[DSP_REG_B1];
6084: dest[2] = dsp_core.registers[DSP_REG_B0];
6085: newsr = dsp_add56(source, dest);
6086:
6087: dsp_core.registers[DSP_REG_B2] = dest[0];
6088: dsp_core.registers[DSP_REG_B1] = dest[1];
6089: dsp_core.registers[DSP_REG_B0] = dest[2];
6090:
6091: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6092:
6093: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6094: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6095: }
6096:
6097: static void dsp_mac_m_x0_y1_b(void)
6098: {
6099: Uint32 source[3], dest[3];
6100: Uint16 newsr;
6101:
6102: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6103:
6104: dest[0] = dsp_core.registers[DSP_REG_B2];
6105: dest[1] = dsp_core.registers[DSP_REG_B1];
6106: dest[2] = dsp_core.registers[DSP_REG_B0];
6107: newsr = dsp_add56(source, dest);
6108:
6109: dsp_core.registers[DSP_REG_B2] = dest[0];
6110: dsp_core.registers[DSP_REG_B1] = dest[1];
6111: dsp_core.registers[DSP_REG_B0] = dest[2];
6112:
6113: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6114:
6115: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6116: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6117: }
6118:
6119: static void dsp_mac_p_y0_x0_a(void)
6120: {
6121: Uint32 source[3], dest[3];
6122: Uint16 newsr;
6123:
6124: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6125:
6126: dest[0] = dsp_core.registers[DSP_REG_A2];
6127: dest[1] = dsp_core.registers[DSP_REG_A1];
6128: dest[2] = dsp_core.registers[DSP_REG_A0];
6129: newsr = dsp_add56(source, dest);
6130:
6131: dsp_core.registers[DSP_REG_A2] = dest[0];
6132: dsp_core.registers[DSP_REG_A1] = dest[1];
6133: dsp_core.registers[DSP_REG_A0] = dest[2];
6134:
6135: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6136:
6137: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6138: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6139: }
6140:
6141: static void dsp_mac_m_y0_x0_a(void)
6142: {
6143: Uint32 source[3], dest[3];
6144: Uint16 newsr;
6145:
6146: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6147:
6148: dest[0] = dsp_core.registers[DSP_REG_A2];
6149: dest[1] = dsp_core.registers[DSP_REG_A1];
6150: dest[2] = dsp_core.registers[DSP_REG_A0];
6151: newsr = dsp_add56(source, dest);
6152:
6153: dsp_core.registers[DSP_REG_A2] = dest[0];
6154: dsp_core.registers[DSP_REG_A1] = dest[1];
6155: dsp_core.registers[DSP_REG_A0] = dest[2];
6156:
6157: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6158:
6159: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6160: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6161: }
6162:
6163: static void dsp_mac_p_y0_x0_b(void)
6164: {
6165: Uint32 source[3], dest[3];
6166: Uint16 newsr;
6167:
6168: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6169:
6170: dest[0] = dsp_core.registers[DSP_REG_B2];
6171: dest[1] = dsp_core.registers[DSP_REG_B1];
6172: dest[2] = dsp_core.registers[DSP_REG_B0];
6173: newsr = dsp_add56(source, dest);
6174:
6175: dsp_core.registers[DSP_REG_B2] = dest[0];
6176: dsp_core.registers[DSP_REG_B1] = dest[1];
6177: dsp_core.registers[DSP_REG_B0] = dest[2];
6178:
6179: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6180:
6181: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6182: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6183: }
6184:
6185: static void dsp_mac_m_y0_x0_b(void)
6186: {
6187: Uint32 source[3], dest[3];
6188: Uint16 newsr;
6189:
6190: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6191:
6192: dest[0] = dsp_core.registers[DSP_REG_B2];
6193: dest[1] = dsp_core.registers[DSP_REG_B1];
6194: dest[2] = dsp_core.registers[DSP_REG_B0];
6195: newsr = dsp_add56(source, dest);
6196:
6197: dsp_core.registers[DSP_REG_B2] = dest[0];
6198: dsp_core.registers[DSP_REG_B1] = dest[1];
6199: dsp_core.registers[DSP_REG_B0] = dest[2];
6200:
6201: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6202:
6203: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6204: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6205: }
6206:
6207: static void dsp_mac_p_x1_y0_a(void)
6208: {
6209: Uint32 source[3], dest[3];
6210: Uint16 newsr;
6211:
6212: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6213:
6214: dest[0] = dsp_core.registers[DSP_REG_A2];
6215: dest[1] = dsp_core.registers[DSP_REG_A1];
6216: dest[2] = dsp_core.registers[DSP_REG_A0];
6217: newsr = dsp_add56(source, dest);
6218:
6219: dsp_core.registers[DSP_REG_A2] = dest[0];
6220: dsp_core.registers[DSP_REG_A1] = dest[1];
6221: dsp_core.registers[DSP_REG_A0] = dest[2];
6222:
6223: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6224:
6225: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6226: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6227: }
6228:
6229: static void dsp_mac_m_x1_y0_a(void)
6230: {
6231: Uint32 source[3], dest[3];
6232: Uint16 newsr;
6233:
6234: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6235:
6236: dest[0] = dsp_core.registers[DSP_REG_A2];
6237: dest[1] = dsp_core.registers[DSP_REG_A1];
6238: dest[2] = dsp_core.registers[DSP_REG_A0];
6239: newsr = dsp_add56(source, dest);
6240:
6241: dsp_core.registers[DSP_REG_A2] = dest[0];
6242: dsp_core.registers[DSP_REG_A1] = dest[1];
6243: dsp_core.registers[DSP_REG_A0] = dest[2];
6244:
6245: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6246:
6247: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6248: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6249: }
6250:
6251: static void dsp_mac_p_x1_y0_b(void)
6252: {
6253: Uint32 source[3], dest[3];
6254: Uint16 newsr;
6255:
6256: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6257:
6258: dest[0] = dsp_core.registers[DSP_REG_B2];
6259: dest[1] = dsp_core.registers[DSP_REG_B1];
6260: dest[2] = dsp_core.registers[DSP_REG_B0];
6261: newsr = dsp_add56(source, dest);
6262:
6263: dsp_core.registers[DSP_REG_B2] = dest[0];
6264: dsp_core.registers[DSP_REG_B1] = dest[1];
6265: dsp_core.registers[DSP_REG_B0] = dest[2];
6266:
6267: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6268:
6269: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6270: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6271: }
6272:
6273: static void dsp_mac_m_x1_y0_b(void)
6274: {
6275: Uint32 source[3], dest[3];
6276: Uint16 newsr;
6277:
6278: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6279:
6280: dest[0] = dsp_core.registers[DSP_REG_B2];
6281: dest[1] = dsp_core.registers[DSP_REG_B1];
6282: dest[2] = dsp_core.registers[DSP_REG_B0];
6283: newsr = dsp_add56(source, dest);
6284:
6285: dsp_core.registers[DSP_REG_B2] = dest[0];
6286: dsp_core.registers[DSP_REG_B1] = dest[1];
6287: dsp_core.registers[DSP_REG_B0] = dest[2];
6288:
6289: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6290:
6291: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6292: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6293: }
6294:
6295: static void dsp_mac_p_y1_x1_a(void)
6296: {
6297: Uint32 source[3], dest[3];
6298: Uint16 newsr;
6299:
6300: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6301:
6302: dest[0] = dsp_core.registers[DSP_REG_A2];
6303: dest[1] = dsp_core.registers[DSP_REG_A1];
6304: dest[2] = dsp_core.registers[DSP_REG_A0];
6305: newsr = dsp_add56(source, dest);
6306:
6307: dsp_core.registers[DSP_REG_A2] = dest[0];
6308: dsp_core.registers[DSP_REG_A1] = dest[1];
6309: dsp_core.registers[DSP_REG_A0] = dest[2];
6310:
6311: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6312:
6313: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6314: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6315: }
6316:
6317: static void dsp_mac_m_y1_x1_a(void)
6318: {
6319: Uint32 source[3], dest[3];
6320: Uint16 newsr;
6321:
6322: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6323:
6324: dest[0] = dsp_core.registers[DSP_REG_A2];
6325: dest[1] = dsp_core.registers[DSP_REG_A1];
6326: dest[2] = dsp_core.registers[DSP_REG_A0];
6327: newsr = dsp_add56(source, dest);
6328:
6329: dsp_core.registers[DSP_REG_A2] = dest[0];
6330: dsp_core.registers[DSP_REG_A1] = dest[1];
6331: dsp_core.registers[DSP_REG_A0] = dest[2];
6332:
6333: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6334:
6335: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6336: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6337: }
6338:
6339: static void dsp_mac_p_y1_x1_b(void)
6340: {
6341: Uint32 source[3], dest[3];
6342: Uint16 newsr;
6343:
6344: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6345:
6346: dest[0] = dsp_core.registers[DSP_REG_B2];
6347: dest[1] = dsp_core.registers[DSP_REG_B1];
6348: dest[2] = dsp_core.registers[DSP_REG_B0];
6349: newsr = dsp_add56(source, dest);
6350:
6351: dsp_core.registers[DSP_REG_B2] = dest[0];
6352: dsp_core.registers[DSP_REG_B1] = dest[1];
6353: dsp_core.registers[DSP_REG_B0] = dest[2];
6354:
6355: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6356:
6357: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6358: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6359: }
6360:
6361: static void dsp_mac_m_y1_x1_b(void)
6362: {
6363: Uint32 source[3], dest[3];
6364: Uint16 newsr;
6365:
6366: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6367:
6368: dest[0] = dsp_core.registers[DSP_REG_B2];
6369: dest[1] = dsp_core.registers[DSP_REG_B1];
6370: dest[2] = dsp_core.registers[DSP_REG_B0];
6371: newsr = dsp_add56(source, dest);
6372:
6373: dsp_core.registers[DSP_REG_B2] = dest[0];
6374: dsp_core.registers[DSP_REG_B1] = dest[1];
6375: dsp_core.registers[DSP_REG_B0] = dest[2];
6376:
6377: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6378:
6379: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6380: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6381: }
6382:
6383: static void dsp_macr_p_x0_x0_a(void)
6384: {
6385: Uint32 source[3], dest[3];
6386: Uint16 newsr;
6387:
6388: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6389:
6390: dest[0] = dsp_core.registers[DSP_REG_A2];
6391: dest[1] = dsp_core.registers[DSP_REG_A1];
6392: dest[2] = dsp_core.registers[DSP_REG_A0];
6393: newsr = dsp_add56(source, dest);
6394:
6395: dsp_rnd56(dest);
6396:
6397: dsp_core.registers[DSP_REG_A2] = dest[0];
6398: dsp_core.registers[DSP_REG_A1] = dest[1];
6399: dsp_core.registers[DSP_REG_A0] = dest[2];
6400:
6401: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6402:
6403: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6404: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6405: }
6406:
6407: static void dsp_macr_m_x0_x0_a(void)
6408: {
6409: Uint32 source[3], dest[3];
6410: Uint16 newsr;
6411:
6412: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6413:
6414: dest[0] = dsp_core.registers[DSP_REG_A2];
6415: dest[1] = dsp_core.registers[DSP_REG_A1];
6416: dest[2] = dsp_core.registers[DSP_REG_A0];
6417: newsr = dsp_add56(source, dest);
6418:
6419: dsp_rnd56(dest);
6420:
6421: dsp_core.registers[DSP_REG_A2] = dest[0];
6422: dsp_core.registers[DSP_REG_A1] = dest[1];
6423: dsp_core.registers[DSP_REG_A0] = dest[2];
6424:
6425: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6426:
6427: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6428: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6429: }
6430: static void dsp_macr_p_x0_x0_b(void)
6431: {
6432: Uint32 source[3], dest[3];
6433: Uint16 newsr;
6434:
6435: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6436:
6437: dest[0] = dsp_core.registers[DSP_REG_B2];
6438: dest[1] = dsp_core.registers[DSP_REG_B1];
6439: dest[2] = dsp_core.registers[DSP_REG_B0];
6440: newsr = dsp_add56(source, dest);
6441:
6442: dsp_rnd56(dest);
6443:
6444: dsp_core.registers[DSP_REG_B2] = dest[0];
6445: dsp_core.registers[DSP_REG_B1] = dest[1];
6446: dsp_core.registers[DSP_REG_B0] = dest[2];
6447:
6448: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6449:
6450: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6451: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6452: }
6453:
6454: static void dsp_macr_m_x0_x0_b(void)
6455: {
6456: Uint32 source[3], dest[3];
6457: Uint16 newsr;
6458:
6459: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6460:
6461: dest[0] = dsp_core.registers[DSP_REG_B2];
6462: dest[1] = dsp_core.registers[DSP_REG_B1];
6463: dest[2] = dsp_core.registers[DSP_REG_B0];
6464: newsr = dsp_add56(source, dest);
6465:
6466: dsp_rnd56(dest);
6467:
6468: dsp_core.registers[DSP_REG_B2] = dest[0];
6469: dsp_core.registers[DSP_REG_B1] = dest[1];
6470: dsp_core.registers[DSP_REG_B0] = dest[2];
6471:
6472: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6473:
6474: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6475: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6476: }
6477:
6478: static void dsp_macr_p_y0_y0_a(void)
6479: {
6480: Uint32 source[3], dest[3];
6481: Uint16 newsr;
6482:
6483: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6484:
6485: dest[0] = dsp_core.registers[DSP_REG_A2];
6486: dest[1] = dsp_core.registers[DSP_REG_A1];
6487: dest[2] = dsp_core.registers[DSP_REG_A0];
6488: newsr = dsp_add56(source, dest);
6489:
6490: dsp_rnd56(dest);
6491:
6492: dsp_core.registers[DSP_REG_A2] = dest[0];
6493: dsp_core.registers[DSP_REG_A1] = dest[1];
6494: dsp_core.registers[DSP_REG_A0] = dest[2];
6495:
6496: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6497:
6498: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6499: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6500: }
6501:
6502: static void dsp_macr_m_y0_y0_a(void)
6503: {
6504: Uint32 source[3], dest[3];
6505: Uint16 newsr;
6506:
6507: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6508:
6509: dest[0] = dsp_core.registers[DSP_REG_A2];
6510: dest[1] = dsp_core.registers[DSP_REG_A1];
6511: dest[2] = dsp_core.registers[DSP_REG_A0];
6512: newsr = dsp_add56(source, dest);
6513:
6514: dsp_rnd56(dest);
6515:
6516: dsp_core.registers[DSP_REG_A2] = dest[0];
6517: dsp_core.registers[DSP_REG_A1] = dest[1];
6518: dsp_core.registers[DSP_REG_A0] = dest[2];
6519:
6520: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6521:
6522: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6523: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6524: }
6525: static void dsp_macr_p_y0_y0_b(void)
6526: {
6527: Uint32 source[3], dest[3];
6528: Uint16 newsr;
6529:
6530: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6531:
6532: dest[0] = dsp_core.registers[DSP_REG_B2];
6533: dest[1] = dsp_core.registers[DSP_REG_B1];
6534: dest[2] = dsp_core.registers[DSP_REG_B0];
6535: newsr = dsp_add56(source, dest);
6536:
6537: dsp_rnd56(dest);
6538:
6539: dsp_core.registers[DSP_REG_B2] = dest[0];
6540: dsp_core.registers[DSP_REG_B1] = dest[1];
6541: dsp_core.registers[DSP_REG_B0] = dest[2];
6542:
6543: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6544:
6545: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6546: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6547: }
6548:
6549: static void dsp_macr_m_y0_y0_b(void)
6550: {
6551: Uint32 source[3], dest[3];
6552: Uint16 newsr;
6553:
6554: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6555:
6556: dest[0] = dsp_core.registers[DSP_REG_B2];
6557: dest[1] = dsp_core.registers[DSP_REG_B1];
6558: dest[2] = dsp_core.registers[DSP_REG_B0];
6559: newsr = dsp_add56(source, dest);
6560:
6561: dsp_rnd56(dest);
6562:
6563: dsp_core.registers[DSP_REG_B2] = dest[0];
6564: dsp_core.registers[DSP_REG_B1] = dest[1];
6565: dsp_core.registers[DSP_REG_B0] = dest[2];
6566:
6567: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6568:
6569: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6570: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6571: }
6572:
6573: static void dsp_macr_p_x1_x0_a(void)
6574: {
6575: Uint32 source[3], dest[3];
6576: Uint16 newsr;
6577:
6578: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6579:
6580: dest[0] = dsp_core.registers[DSP_REG_A2];
6581: dest[1] = dsp_core.registers[DSP_REG_A1];
6582: dest[2] = dsp_core.registers[DSP_REG_A0];
6583: newsr = dsp_add56(source, dest);
6584:
6585: dsp_rnd56(dest);
6586:
6587: dsp_core.registers[DSP_REG_A2] = dest[0];
6588: dsp_core.registers[DSP_REG_A1] = dest[1];
6589: dsp_core.registers[DSP_REG_A0] = dest[2];
6590:
6591: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6592:
6593: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6594: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6595: }
6596:
6597: static void dsp_macr_m_x1_x0_a(void)
6598: {
6599: Uint32 source[3], dest[3];
6600: Uint16 newsr;
6601:
6602: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6603:
6604: dest[0] = dsp_core.registers[DSP_REG_A2];
6605: dest[1] = dsp_core.registers[DSP_REG_A1];
6606: dest[2] = dsp_core.registers[DSP_REG_A0];
6607: newsr = dsp_add56(source, dest);
6608:
6609: dsp_rnd56(dest);
6610:
6611: dsp_core.registers[DSP_REG_A2] = dest[0];
6612: dsp_core.registers[DSP_REG_A1] = dest[1];
6613: dsp_core.registers[DSP_REG_A0] = dest[2];
6614:
6615: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6616:
6617: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6618: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6619: }
6620:
6621: static void dsp_macr_p_x1_x0_b(void)
6622: {
6623: Uint32 source[3], dest[3];
6624: Uint16 newsr;
6625:
6626: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6627:
6628: dest[0] = dsp_core.registers[DSP_REG_B2];
6629: dest[1] = dsp_core.registers[DSP_REG_B1];
6630: dest[2] = dsp_core.registers[DSP_REG_B0];
6631: newsr = dsp_add56(source, dest);
6632:
6633: dsp_rnd56(dest);
6634:
6635: dsp_core.registers[DSP_REG_B2] = dest[0];
6636: dsp_core.registers[DSP_REG_B1] = dest[1];
6637: dsp_core.registers[DSP_REG_B0] = dest[2];
6638:
6639: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6640:
6641: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6642: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6643: }
6644:
6645: static void dsp_macr_m_x1_x0_b(void)
6646: {
6647: Uint32 source[3], dest[3];
6648: Uint16 newsr;
6649:
6650: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6651:
6652: dest[0] = dsp_core.registers[DSP_REG_B2];
6653: dest[1] = dsp_core.registers[DSP_REG_B1];
6654: dest[2] = dsp_core.registers[DSP_REG_B0];
6655: newsr = dsp_add56(source, dest);
6656:
6657: dsp_rnd56(dest);
6658:
6659: dsp_core.registers[DSP_REG_B2] = dest[0];
6660: dsp_core.registers[DSP_REG_B1] = dest[1];
6661: dsp_core.registers[DSP_REG_B0] = dest[2];
6662:
6663: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6664:
6665: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6666: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6667: }
6668:
6669: static void dsp_macr_p_y1_y0_a(void)
6670: {
6671: Uint32 source[3], dest[3];
6672: Uint16 newsr;
6673:
6674: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6675:
6676: dest[0] = dsp_core.registers[DSP_REG_A2];
6677: dest[1] = dsp_core.registers[DSP_REG_A1];
6678: dest[2] = dsp_core.registers[DSP_REG_A0];
6679: newsr = dsp_add56(source, dest);
6680:
6681: dsp_rnd56(dest);
6682:
6683: dsp_core.registers[DSP_REG_A2] = dest[0];
6684: dsp_core.registers[DSP_REG_A1] = dest[1];
6685: dsp_core.registers[DSP_REG_A0] = dest[2];
6686:
6687: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6688:
6689: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6690: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6691: }
6692:
6693: static void dsp_macr_m_y1_y0_a(void)
6694: {
6695: Uint32 source[3], dest[3];
6696: Uint16 newsr;
6697:
6698: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6699:
6700: dest[0] = dsp_core.registers[DSP_REG_A2];
6701: dest[1] = dsp_core.registers[DSP_REG_A1];
6702: dest[2] = dsp_core.registers[DSP_REG_A0];
6703: newsr = dsp_add56(source, dest);
6704:
6705: dsp_rnd56(dest);
6706:
6707: dsp_core.registers[DSP_REG_A2] = dest[0];
6708: dsp_core.registers[DSP_REG_A1] = dest[1];
6709: dsp_core.registers[DSP_REG_A0] = dest[2];
6710:
6711: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6712:
6713: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6714: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6715: }
6716:
6717: static void dsp_macr_p_y1_y0_b(void)
6718: {
6719: Uint32 source[3], dest[3];
6720: Uint16 newsr;
6721:
6722: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6723:
6724: dest[0] = dsp_core.registers[DSP_REG_B2];
6725: dest[1] = dsp_core.registers[DSP_REG_B1];
6726: dest[2] = dsp_core.registers[DSP_REG_B0];
6727: newsr = dsp_add56(source, dest);
6728:
6729: dsp_rnd56(dest);
6730:
6731: dsp_core.registers[DSP_REG_B2] = dest[0];
6732: dsp_core.registers[DSP_REG_B1] = dest[1];
6733: dsp_core.registers[DSP_REG_B0] = dest[2];
6734:
6735: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6736:
6737: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6738: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6739: }
6740:
6741: static void dsp_macr_m_y1_y0_b(void)
6742: {
6743: Uint32 source[3], dest[3];
6744: Uint16 newsr;
6745:
6746: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6747:
6748: dest[0] = dsp_core.registers[DSP_REG_B2];
6749: dest[1] = dsp_core.registers[DSP_REG_B1];
6750: dest[2] = dsp_core.registers[DSP_REG_B0];
6751: newsr = dsp_add56(source, dest);
6752:
6753: dsp_rnd56(dest);
6754:
6755: dsp_core.registers[DSP_REG_B2] = dest[0];
6756: dsp_core.registers[DSP_REG_B1] = dest[1];
6757: dsp_core.registers[DSP_REG_B0] = dest[2];
6758:
6759: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6760:
6761: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6762: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6763: }
6764:
6765: static void dsp_macr_p_x0_y1_a(void)
6766: {
6767: Uint32 source[3], dest[3];
6768: Uint16 newsr;
6769:
6770: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6771:
6772: dest[0] = dsp_core.registers[DSP_REG_A2];
6773: dest[1] = dsp_core.registers[DSP_REG_A1];
6774: dest[2] = dsp_core.registers[DSP_REG_A0];
6775: newsr = dsp_add56(source, dest);
6776:
6777: dsp_rnd56(dest);
6778:
6779: dsp_core.registers[DSP_REG_A2] = dest[0];
6780: dsp_core.registers[DSP_REG_A1] = dest[1];
6781: dsp_core.registers[DSP_REG_A0] = dest[2];
6782:
6783: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6784:
6785: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6786: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6787: }
6788:
6789: static void dsp_macr_m_x0_y1_a(void)
6790: {
6791: Uint32 source[3], dest[3];
6792: Uint16 newsr;
6793:
6794: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6795:
6796: dest[0] = dsp_core.registers[DSP_REG_A2];
6797: dest[1] = dsp_core.registers[DSP_REG_A1];
6798: dest[2] = dsp_core.registers[DSP_REG_A0];
6799: newsr = dsp_add56(source, dest);
6800:
6801: dsp_rnd56(dest);
6802:
6803: dsp_core.registers[DSP_REG_A2] = dest[0];
6804: dsp_core.registers[DSP_REG_A1] = dest[1];
6805: dsp_core.registers[DSP_REG_A0] = dest[2];
6806:
6807: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6808:
6809: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6810: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6811: }
6812:
6813: static void dsp_macr_p_x0_y1_b(void)
6814: {
6815: Uint32 source[3], dest[3];
6816: Uint16 newsr;
6817:
6818: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6819:
6820: dest[0] = dsp_core.registers[DSP_REG_B2];
6821: dest[1] = dsp_core.registers[DSP_REG_B1];
6822: dest[2] = dsp_core.registers[DSP_REG_B0];
6823: newsr = dsp_add56(source, dest);
6824:
6825: dsp_rnd56(dest);
6826:
6827: dsp_core.registers[DSP_REG_B2] = dest[0];
6828: dsp_core.registers[DSP_REG_B1] = dest[1];
6829: dsp_core.registers[DSP_REG_B0] = dest[2];
6830:
6831: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6832:
6833: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6834: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6835: }
6836:
6837: static void dsp_macr_m_x0_y1_b(void)
6838: {
6839: Uint32 source[3], dest[3];
6840: Uint16 newsr;
6841:
6842: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6843:
6844: dest[0] = dsp_core.registers[DSP_REG_B2];
6845: dest[1] = dsp_core.registers[DSP_REG_B1];
6846: dest[2] = dsp_core.registers[DSP_REG_B0];
6847: newsr = dsp_add56(source, dest);
6848:
6849: dsp_rnd56(dest);
6850:
6851: dsp_core.registers[DSP_REG_B2] = dest[0];
6852: dsp_core.registers[DSP_REG_B1] = dest[1];
6853: dsp_core.registers[DSP_REG_B0] = dest[2];
6854:
6855: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6856:
6857: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6858: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6859: }
6860:
6861: static void dsp_macr_p_y0_x0_a(void)
6862: {
6863: Uint32 source[3], dest[3];
6864: Uint16 newsr;
6865:
6866: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6867:
6868: dest[0] = dsp_core.registers[DSP_REG_A2];
6869: dest[1] = dsp_core.registers[DSP_REG_A1];
6870: dest[2] = dsp_core.registers[DSP_REG_A0];
6871: newsr = dsp_add56(source, dest);
6872:
6873: dsp_rnd56(dest);
6874:
6875: dsp_core.registers[DSP_REG_A2] = dest[0];
6876: dsp_core.registers[DSP_REG_A1] = dest[1];
6877: dsp_core.registers[DSP_REG_A0] = dest[2];
6878:
6879: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6880:
6881: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6882: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6883: }
6884:
6885: static void dsp_macr_m_y0_x0_a(void)
6886: {
6887: Uint32 source[3], dest[3];
6888: Uint16 newsr;
6889:
6890: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6891:
6892: dest[0] = dsp_core.registers[DSP_REG_A2];
6893: dest[1] = dsp_core.registers[DSP_REG_A1];
6894: dest[2] = dsp_core.registers[DSP_REG_A0];
6895: newsr = dsp_add56(source, dest);
6896:
6897: dsp_rnd56(dest);
6898:
6899: dsp_core.registers[DSP_REG_A2] = dest[0];
6900: dsp_core.registers[DSP_REG_A1] = dest[1];
6901: dsp_core.registers[DSP_REG_A0] = dest[2];
6902:
6903: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6904:
6905: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6906: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6907: }
6908:
6909: static void dsp_macr_p_y0_x0_b(void)
6910: {
6911: Uint32 source[3], dest[3];
6912: Uint16 newsr;
6913:
6914: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6915:
6916: dest[0] = dsp_core.registers[DSP_REG_B2];
6917: dest[1] = dsp_core.registers[DSP_REG_B1];
6918: dest[2] = dsp_core.registers[DSP_REG_B0];
6919: newsr = dsp_add56(source, dest);
6920:
6921: dsp_rnd56(dest);
6922:
6923: dsp_core.registers[DSP_REG_B2] = dest[0];
6924: dsp_core.registers[DSP_REG_B1] = dest[1];
6925: dsp_core.registers[DSP_REG_B0] = dest[2];
6926:
6927: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6928:
6929: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6930: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6931: }
6932:
6933: static void dsp_macr_m_y0_x0_b(void)
6934: {
6935: Uint32 source[3], dest[3];
6936: Uint16 newsr;
6937:
6938: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6939:
6940: dest[0] = dsp_core.registers[DSP_REG_B2];
6941: dest[1] = dsp_core.registers[DSP_REG_B1];
6942: dest[2] = dsp_core.registers[DSP_REG_B0];
6943: newsr = dsp_add56(source, dest);
6944:
6945: dsp_rnd56(dest);
6946:
6947: dsp_core.registers[DSP_REG_B2] = dest[0];
6948: dsp_core.registers[DSP_REG_B1] = dest[1];
6949: dsp_core.registers[DSP_REG_B0] = dest[2];
6950:
6951: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6952:
6953: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6954: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6955: }
6956:
6957: static void dsp_macr_p_x1_y0_a(void)
6958: {
6959: Uint32 source[3], dest[3];
6960: Uint16 newsr;
6961:
6962: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6963:
6964: dest[0] = dsp_core.registers[DSP_REG_A2];
6965: dest[1] = dsp_core.registers[DSP_REG_A1];
6966: dest[2] = dsp_core.registers[DSP_REG_A0];
6967: newsr = dsp_add56(source, dest);
6968:
6969: dsp_rnd56(dest);
6970:
6971: dsp_core.registers[DSP_REG_A2] = dest[0];
6972: dsp_core.registers[DSP_REG_A1] = dest[1];
6973: dsp_core.registers[DSP_REG_A0] = dest[2];
6974:
6975: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6976:
6977: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6978: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6979: }
6980:
6981: static void dsp_macr_m_x1_y0_a(void)
6982: {
6983: Uint32 source[3], dest[3];
6984: Uint16 newsr;
6985:
6986: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6987:
6988: dest[0] = dsp_core.registers[DSP_REG_A2];
6989: dest[1] = dsp_core.registers[DSP_REG_A1];
6990: dest[2] = dsp_core.registers[DSP_REG_A0];
6991: newsr = dsp_add56(source, dest);
6992:
6993: dsp_rnd56(dest);
6994:
6995: dsp_core.registers[DSP_REG_A2] = dest[0];
6996: dsp_core.registers[DSP_REG_A1] = dest[1];
6997: dsp_core.registers[DSP_REG_A0] = dest[2];
6998:
6999: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7000:
7001: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7002: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7003: }
7004:
7005: static void dsp_macr_p_x1_y0_b(void)
7006: {
7007: Uint32 source[3], dest[3];
7008: Uint16 newsr;
7009:
7010: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7011:
7012: dest[0] = dsp_core.registers[DSP_REG_B2];
7013: dest[1] = dsp_core.registers[DSP_REG_B1];
7014: dest[2] = dsp_core.registers[DSP_REG_B0];
7015: newsr = dsp_add56(source, dest);
7016:
1.1.1.10 root 7017: dsp_rnd56(dest);
7018:
1.1.1.6 root 7019: dsp_core.registers[DSP_REG_B2] = dest[0];
7020: dsp_core.registers[DSP_REG_B1] = dest[1];
7021: dsp_core.registers[DSP_REG_B0] = dest[2];
7022:
7023: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7024:
7025: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7026: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7027: }
7028:
7029: static void dsp_macr_m_x1_y0_b(void)
7030: {
7031: Uint32 source[3], dest[3];
7032: Uint16 newsr;
7033:
7034: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7035:
7036: dest[0] = dsp_core.registers[DSP_REG_B2];
7037: dest[1] = dsp_core.registers[DSP_REG_B1];
7038: dest[2] = dsp_core.registers[DSP_REG_B0];
7039: newsr = dsp_add56(source, dest);
7040:
7041: dsp_rnd56(dest);
7042:
7043: dsp_core.registers[DSP_REG_B2] = dest[0];
7044: dsp_core.registers[DSP_REG_B1] = dest[1];
7045: dsp_core.registers[DSP_REG_B0] = dest[2];
7046:
7047: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7048:
7049: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7050: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7051: }
7052:
7053: static void dsp_macr_p_y1_x1_a(void)
7054: {
7055: Uint32 source[3], dest[3];
7056: Uint16 newsr;
7057:
7058: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7059:
7060: dest[0] = dsp_core.registers[DSP_REG_A2];
7061: dest[1] = dsp_core.registers[DSP_REG_A1];
7062: dest[2] = dsp_core.registers[DSP_REG_A0];
7063: newsr = dsp_add56(source, dest);
7064:
7065: dsp_rnd56(dest);
7066:
7067: dsp_core.registers[DSP_REG_A2] = dest[0];
7068: dsp_core.registers[DSP_REG_A1] = dest[1];
7069: dsp_core.registers[DSP_REG_A0] = dest[2];
7070:
7071: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7072:
7073: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7074: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7075: }
7076:
7077: static void dsp_macr_m_y1_x1_a(void)
7078: {
7079: Uint32 source[3], dest[3];
7080: Uint16 newsr;
7081:
7082: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7083:
7084: dest[0] = dsp_core.registers[DSP_REG_A2];
7085: dest[1] = dsp_core.registers[DSP_REG_A1];
7086: dest[2] = dsp_core.registers[DSP_REG_A0];
7087: newsr = dsp_add56(source, dest);
7088:
7089: dsp_rnd56(dest);
7090:
7091: dsp_core.registers[DSP_REG_A2] = dest[0];
7092: dsp_core.registers[DSP_REG_A1] = dest[1];
7093: dsp_core.registers[DSP_REG_A0] = dest[2];
7094:
7095: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7096:
7097: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7098: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7099: }
7100:
7101: static void dsp_macr_p_y1_x1_b(void)
7102: {
7103: Uint32 source[3], dest[3];
7104: Uint16 newsr;
7105:
7106: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7107:
7108: dest[0] = dsp_core.registers[DSP_REG_B2];
7109: dest[1] = dsp_core.registers[DSP_REG_B1];
7110: dest[2] = dsp_core.registers[DSP_REG_B0];
7111: newsr = dsp_add56(source, dest);
7112:
7113: dsp_rnd56(dest);
7114:
7115: dsp_core.registers[DSP_REG_B2] = dest[0];
7116: dsp_core.registers[DSP_REG_B1] = dest[1];
7117: dsp_core.registers[DSP_REG_B0] = dest[2];
7118:
7119: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7120:
7121: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7122: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7123: }
7124:
7125: static void dsp_macr_m_y1_x1_b(void)
7126: {
7127: Uint32 source[3], dest[3];
7128: Uint16 newsr;
7129:
7130: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7131:
7132: dest[0] = dsp_core.registers[DSP_REG_B2];
7133: dest[1] = dsp_core.registers[DSP_REG_B1];
7134: dest[2] = dsp_core.registers[DSP_REG_B0];
7135: newsr = dsp_add56(source, dest);
7136:
7137: dsp_rnd56(dest);
7138:
7139: dsp_core.registers[DSP_REG_B2] = dest[0];
7140: dsp_core.registers[DSP_REG_B1] = dest[1];
7141: dsp_core.registers[DSP_REG_B0] = dest[2];
7142:
7143: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7144:
7145: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7146: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7147: }
7148:
7149:
7150: static void dsp_move(void)
7151: {
7152: /* move instruction inside alu opcodes
7153: taken care of by parallel move dispatcher */
7154: }
7155:
7156: static void dsp_mpy_p_x0_x0_a(void)
7157: {
7158: Uint32 source[3];
7159:
7160: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7161:
7162: dsp_core.registers[DSP_REG_A2] = source[0];
7163: dsp_core.registers[DSP_REG_A1] = source[1];
7164: dsp_core.registers[DSP_REG_A0] = source[2];
7165:
7166: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7167: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7168: }
7169:
7170: static void dsp_mpy_m_x0_x0_a(void)
7171: {
7172: Uint32 source[3];
7173:
7174: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7175:
7176: dsp_core.registers[DSP_REG_A2] = source[0];
7177: dsp_core.registers[DSP_REG_A1] = source[1];
7178: dsp_core.registers[DSP_REG_A0] = source[2];
7179:
7180: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7181: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7182: }
7183:
7184: static void dsp_mpy_p_x0_x0_b(void)
7185: {
7186: Uint32 source[3];
7187:
7188: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7189:
7190: dsp_core.registers[DSP_REG_B2] = source[0];
7191: dsp_core.registers[DSP_REG_B1] = source[1];
7192: dsp_core.registers[DSP_REG_B0] = source[2];
7193:
7194: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7195: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7196: }
7197:
7198: static void dsp_mpy_m_x0_x0_b(void)
7199: {
7200: Uint32 source[3];
7201:
7202:
7203: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7204:
7205: dsp_core.registers[DSP_REG_B2] = source[0];
7206: dsp_core.registers[DSP_REG_B1] = source[1];
7207: dsp_core.registers[DSP_REG_B0] = source[2];
7208:
7209: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7210: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7211: }
7212:
7213: static void dsp_mpy_p_y0_y0_a(void)
7214: {
7215: Uint32 source[3];
7216:
7217: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7218:
7219: dsp_core.registers[DSP_REG_A2] = source[0];
7220: dsp_core.registers[DSP_REG_A1] = source[1];
7221: dsp_core.registers[DSP_REG_A0] = source[2];
7222:
7223: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7224: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7225: }
7226:
7227: static void dsp_mpy_m_y0_y0_a(void)
7228: {
7229: Uint32 source[3];
7230:
7231: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7232:
7233: dsp_core.registers[DSP_REG_A2] = source[0];
7234: dsp_core.registers[DSP_REG_A1] = source[1];
7235: dsp_core.registers[DSP_REG_A0] = source[2];
7236:
7237: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7238: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7239: }
7240:
7241: static void dsp_mpy_p_y0_y0_b(void)
7242: {
7243: Uint32 source[3];
7244:
7245: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7246:
7247: dsp_core.registers[DSP_REG_B2] = source[0];
7248: dsp_core.registers[DSP_REG_B1] = source[1];
7249: dsp_core.registers[DSP_REG_B0] = source[2];
7250:
7251: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7252: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7253: }
7254:
7255: static void dsp_mpy_m_y0_y0_b(void)
7256: {
7257: Uint32 source[3];
7258:
7259: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7260:
7261: dsp_core.registers[DSP_REG_B2] = source[0];
7262: dsp_core.registers[DSP_REG_B1] = source[1];
7263: dsp_core.registers[DSP_REG_B0] = source[2];
7264:
7265: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7266: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7267: }
7268:
7269: static void dsp_mpy_p_x1_x0_a(void)
7270: {
7271: Uint32 source[3];
7272:
7273: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7274:
7275: dsp_core.registers[DSP_REG_A2] = source[0];
7276: dsp_core.registers[DSP_REG_A1] = source[1];
7277: dsp_core.registers[DSP_REG_A0] = source[2];
7278:
7279: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7280: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7281: }
7282:
7283: static void dsp_mpy_m_x1_x0_a(void)
7284: {
7285: Uint32 source[3];
7286:
7287: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7288:
7289: dsp_core.registers[DSP_REG_A2] = source[0];
7290: dsp_core.registers[DSP_REG_A1] = source[1];
7291: dsp_core.registers[DSP_REG_A0] = source[2];
7292:
7293: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7294: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7295: }
7296:
7297: static void dsp_mpy_p_x1_x0_b(void)
7298: {
7299: Uint32 source[3];
7300:
7301: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7302:
7303: dsp_core.registers[DSP_REG_B2] = source[0];
7304: dsp_core.registers[DSP_REG_B1] = source[1];
7305: dsp_core.registers[DSP_REG_B0] = source[2];
7306:
7307: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7308: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7309: }
7310:
7311: static void dsp_mpy_m_x1_x0_b(void)
7312: {
7313: Uint32 source[3];
7314:
7315: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7316:
7317: dsp_core.registers[DSP_REG_B2] = source[0];
7318: dsp_core.registers[DSP_REG_B1] = source[1];
7319: dsp_core.registers[DSP_REG_B0] = source[2];
7320:
7321: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7322: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7323: }
7324:
7325: static void dsp_mpy_p_y1_y0_a(void)
7326: {
7327: Uint32 source[3];
7328:
7329: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7330:
7331: dsp_core.registers[DSP_REG_A2] = source[0];
7332: dsp_core.registers[DSP_REG_A1] = source[1];
7333: dsp_core.registers[DSP_REG_A0] = source[2];
7334:
7335: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7336: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7337: }
7338:
7339: static void dsp_mpy_m_y1_y0_a(void)
7340: {
7341: Uint32 source[3];
7342:
7343: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7344:
7345: dsp_core.registers[DSP_REG_A2] = source[0];
7346: dsp_core.registers[DSP_REG_A1] = source[1];
7347: dsp_core.registers[DSP_REG_A0] = source[2];
7348:
7349: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7350: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7351: }
7352:
7353: static void dsp_mpy_p_y1_y0_b(void)
7354: {
7355: Uint32 source[3];
7356:
7357: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7358:
7359: dsp_core.registers[DSP_REG_B2] = source[0];
7360: dsp_core.registers[DSP_REG_B1] = source[1];
7361: dsp_core.registers[DSP_REG_B0] = source[2];
7362:
7363: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7364: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7365: }
7366:
7367: static void dsp_mpy_m_y1_y0_b(void)
7368: {
7369: Uint32 source[3];
7370:
7371: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7372:
7373: dsp_core.registers[DSP_REG_B2] = source[0];
7374: dsp_core.registers[DSP_REG_B1] = source[1];
7375: dsp_core.registers[DSP_REG_B0] = source[2];
7376:
7377: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7378: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7379: }
7380:
7381: static void dsp_mpy_p_x0_y1_a(void)
7382: {
7383: Uint32 source[3];
7384:
7385: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7386:
7387: dsp_core.registers[DSP_REG_A2] = source[0];
7388: dsp_core.registers[DSP_REG_A1] = source[1];
7389: dsp_core.registers[DSP_REG_A0] = source[2];
7390:
7391: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7392: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7393: }
7394:
7395: static void dsp_mpy_m_x0_y1_a(void)
7396: {
7397: Uint32 source[3];
7398:
7399: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7400:
7401: dsp_core.registers[DSP_REG_A2] = source[0];
7402: dsp_core.registers[DSP_REG_A1] = source[1];
7403: dsp_core.registers[DSP_REG_A0] = source[2];
7404:
7405: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7406: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7407: }
7408:
7409: static void dsp_mpy_p_x0_y1_b(void)
7410: {
7411: Uint32 source[3];
7412:
7413: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7414:
7415: dsp_core.registers[DSP_REG_B2] = source[0];
7416: dsp_core.registers[DSP_REG_B1] = source[1];
7417: dsp_core.registers[DSP_REG_B0] = source[2];
7418:
7419: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7420: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7421: }
7422:
7423: static void dsp_mpy_m_x0_y1_b(void)
7424: {
7425: Uint32 source[3];
7426:
7427: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7428:
7429: dsp_core.registers[DSP_REG_B2] = source[0];
7430: dsp_core.registers[DSP_REG_B1] = source[1];
7431: dsp_core.registers[DSP_REG_B0] = source[2];
7432:
7433: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7434: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7435: }
7436:
7437: static void dsp_mpy_p_y0_x0_a(void)
7438: {
7439: Uint32 source[3];
7440:
7441: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7442:
7443: dsp_core.registers[DSP_REG_A2] = source[0];
7444: dsp_core.registers[DSP_REG_A1] = source[1];
7445: dsp_core.registers[DSP_REG_A0] = source[2];
7446:
7447: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7448: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7449: }
7450:
7451: static void dsp_mpy_m_y0_x0_a(void)
7452: {
7453: Uint32 source[3];
7454:
7455: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7456:
7457: dsp_core.registers[DSP_REG_A2] = source[0];
7458: dsp_core.registers[DSP_REG_A1] = source[1];
7459: dsp_core.registers[DSP_REG_A0] = source[2];
7460:
7461: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7462: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7463: }
7464:
7465: static void dsp_mpy_p_y0_x0_b(void)
7466: {
7467: Uint32 source[3];
7468:
7469: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7470:
7471: dsp_core.registers[DSP_REG_B2] = source[0];
7472: dsp_core.registers[DSP_REG_B1] = source[1];
7473: dsp_core.registers[DSP_REG_B0] = source[2];
7474:
7475: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7476: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7477: }
7478:
7479: static void dsp_mpy_m_y0_x0_b(void)
7480: {
7481: Uint32 source[3];
7482:
7483: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7484:
7485: dsp_core.registers[DSP_REG_B2] = source[0];
7486: dsp_core.registers[DSP_REG_B1] = source[1];
7487: dsp_core.registers[DSP_REG_B0] = source[2];
7488:
7489: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7490: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7491: }
7492:
7493: static void dsp_mpy_p_x1_y0_a(void)
7494: {
7495: Uint32 source[3];
7496:
7497: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7498:
7499: dsp_core.registers[DSP_REG_A2] = source[0];
7500: dsp_core.registers[DSP_REG_A1] = source[1];
7501: dsp_core.registers[DSP_REG_A0] = source[2];
7502:
7503: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7504: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7505: }
7506:
7507: static void dsp_mpy_m_x1_y0_a(void)
7508: {
7509: Uint32 source[3];
7510:
7511: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7512:
7513: dsp_core.registers[DSP_REG_A2] = source[0];
7514: dsp_core.registers[DSP_REG_A1] = source[1];
7515: dsp_core.registers[DSP_REG_A0] = source[2];
7516:
7517: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7518: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7519: }
7520:
7521: static void dsp_mpy_p_x1_y0_b(void)
7522: {
7523: Uint32 source[3];
7524:
7525: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7526:
7527: dsp_core.registers[DSP_REG_B2] = source[0];
7528: dsp_core.registers[DSP_REG_B1] = source[1];
7529: dsp_core.registers[DSP_REG_B0] = source[2];
7530:
7531: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7532: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7533: }
7534:
7535: static void dsp_mpy_m_x1_y0_b(void)
7536: {
7537: Uint32 source[3];
7538:
7539: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7540:
7541: dsp_core.registers[DSP_REG_B2] = source[0];
7542: dsp_core.registers[DSP_REG_B1] = source[1];
7543: dsp_core.registers[DSP_REG_B0] = source[2];
7544:
7545: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7546: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7547: }
7548:
7549: static void dsp_mpy_p_y1_x1_a(void)
7550: {
7551: Uint32 source[3];
7552:
7553: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7554:
7555: dsp_core.registers[DSP_REG_A2] = source[0];
7556: dsp_core.registers[DSP_REG_A1] = source[1];
7557: dsp_core.registers[DSP_REG_A0] = source[2];
7558:
7559: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7560: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7561: }
7562:
7563: static void dsp_mpy_m_y1_x1_a(void)
7564: {
7565: Uint32 source[3];
7566:
7567: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7568:
7569: dsp_core.registers[DSP_REG_A2] = source[0];
7570: dsp_core.registers[DSP_REG_A1] = source[1];
7571: dsp_core.registers[DSP_REG_A0] = source[2];
7572:
7573: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7574: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7575: }
7576:
7577: static void dsp_mpy_p_y1_x1_b(void)
7578: {
7579: Uint32 source[3];
7580:
7581: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7582:
7583: dsp_core.registers[DSP_REG_B2] = source[0];
7584: dsp_core.registers[DSP_REG_B1] = source[1];
7585: dsp_core.registers[DSP_REG_B0] = source[2];
7586:
7587: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7588: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7589: }
7590:
7591: static void dsp_mpy_m_y1_x1_b(void)
7592: {
7593: Uint32 source[3];
7594:
7595: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7596:
7597: dsp_core.registers[DSP_REG_B2] = source[0];
7598: dsp_core.registers[DSP_REG_B1] = source[1];
7599: dsp_core.registers[DSP_REG_B0] = source[2];
7600:
7601: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7602: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7603: }
7604:
7605: static void dsp_mpyr_p_x0_x0_a(void)
7606: {
7607: Uint32 source[3];
7608:
7609: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7610: dsp_rnd56(source);
7611:
7612: dsp_core.registers[DSP_REG_A2] = source[0];
7613: dsp_core.registers[DSP_REG_A1] = source[1];
7614: dsp_core.registers[DSP_REG_A0] = source[2];
7615:
7616: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7617: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7618: }
7619:
7620: static void dsp_mpyr_m_x0_x0_a(void)
7621: {
7622: Uint32 source[3];
7623:
7624: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7625: dsp_rnd56(source);
7626:
7627: dsp_core.registers[DSP_REG_A2] = source[0];
7628: dsp_core.registers[DSP_REG_A1] = source[1];
7629: dsp_core.registers[DSP_REG_A0] = source[2];
7630:
7631: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7632: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7633: }
7634:
7635: static void dsp_mpyr_p_x0_x0_b(void)
7636: {
7637: Uint32 source[3];
7638:
7639: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7640: dsp_rnd56(source);
7641:
7642: dsp_core.registers[DSP_REG_B2] = source[0];
7643: dsp_core.registers[DSP_REG_B1] = source[1];
7644: dsp_core.registers[DSP_REG_B0] = source[2];
7645:
7646: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7647: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7648: }
7649:
7650: static void dsp_mpyr_m_x0_x0_b(void)
7651: {
7652: Uint32 source[3];
7653:
7654:
7655: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7656: dsp_rnd56(source);
7657:
7658: dsp_core.registers[DSP_REG_B2] = source[0];
7659: dsp_core.registers[DSP_REG_B1] = source[1];
7660: dsp_core.registers[DSP_REG_B0] = source[2];
7661:
7662: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7663: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7664: }
7665:
7666: static void dsp_mpyr_p_y0_y0_a(void)
7667: {
7668: Uint32 source[3];
7669:
7670: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7671: dsp_rnd56(source);
7672:
7673: dsp_core.registers[DSP_REG_A2] = source[0];
7674: dsp_core.registers[DSP_REG_A1] = source[1];
7675: dsp_core.registers[DSP_REG_A0] = source[2];
7676:
7677: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7678: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7679: }
7680:
7681: static void dsp_mpyr_m_y0_y0_a(void)
7682: {
7683: Uint32 source[3];
7684:
7685: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7686: dsp_rnd56(source);
7687:
7688: dsp_core.registers[DSP_REG_A2] = source[0];
7689: dsp_core.registers[DSP_REG_A1] = source[1];
7690: dsp_core.registers[DSP_REG_A0] = source[2];
7691:
7692: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7693: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7694: }
7695:
7696: static void dsp_mpyr_p_y0_y0_b(void)
7697: {
7698: Uint32 source[3];
7699:
7700: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7701: dsp_rnd56(source);
7702:
7703: dsp_core.registers[DSP_REG_B2] = source[0];
7704: dsp_core.registers[DSP_REG_B1] = source[1];
7705: dsp_core.registers[DSP_REG_B0] = source[2];
7706:
7707: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7708: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7709: }
7710:
7711: static void dsp_mpyr_m_y0_y0_b(void)
7712: {
7713: Uint32 source[3];
7714:
7715: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7716: dsp_rnd56(source);
7717:
7718: dsp_core.registers[DSP_REG_B2] = source[0];
7719: dsp_core.registers[DSP_REG_B1] = source[1];
7720: dsp_core.registers[DSP_REG_B0] = source[2];
7721:
7722: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7723: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7724: }
7725:
7726: static void dsp_mpyr_p_x1_x0_a(void)
7727: {
7728: Uint32 source[3];
7729:
7730: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7731: dsp_rnd56(source);
7732:
7733: dsp_core.registers[DSP_REG_A2] = source[0];
7734: dsp_core.registers[DSP_REG_A1] = source[1];
7735: dsp_core.registers[DSP_REG_A0] = source[2];
7736:
7737: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7738: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7739: }
7740:
7741: static void dsp_mpyr_m_x1_x0_a(void)
7742: {
7743: Uint32 source[3];
7744:
7745: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7746: dsp_rnd56(source);
7747:
7748: dsp_core.registers[DSP_REG_A2] = source[0];
7749: dsp_core.registers[DSP_REG_A1] = source[1];
7750: dsp_core.registers[DSP_REG_A0] = source[2];
7751:
7752: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7753: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7754: }
7755:
7756: static void dsp_mpyr_p_x1_x0_b(void)
7757: {
7758: Uint32 source[3];
7759:
7760: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7761: dsp_rnd56(source);
7762:
7763: dsp_core.registers[DSP_REG_B2] = source[0];
7764: dsp_core.registers[DSP_REG_B1] = source[1];
7765: dsp_core.registers[DSP_REG_B0] = source[2];
7766:
7767: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7768: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7769: }
7770:
7771: static void dsp_mpyr_m_x1_x0_b(void)
7772: {
7773: Uint32 source[3];
7774:
7775: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7776: dsp_rnd56(source);
7777:
7778: dsp_core.registers[DSP_REG_B2] = source[0];
7779: dsp_core.registers[DSP_REG_B1] = source[1];
7780: dsp_core.registers[DSP_REG_B0] = source[2];
7781:
7782: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7783: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7784: }
7785:
7786: static void dsp_mpyr_p_y1_y0_a(void)
7787: {
7788: Uint32 source[3];
7789:
7790: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7791: dsp_rnd56(source);
7792:
7793: dsp_core.registers[DSP_REG_A2] = source[0];
7794: dsp_core.registers[DSP_REG_A1] = source[1];
7795: dsp_core.registers[DSP_REG_A0] = source[2];
7796:
7797: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7798: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7799: }
7800:
7801: static void dsp_mpyr_m_y1_y0_a(void)
7802: {
7803: Uint32 source[3];
7804:
7805: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7806: dsp_rnd56(source);
7807:
7808: dsp_core.registers[DSP_REG_A2] = source[0];
7809: dsp_core.registers[DSP_REG_A1] = source[1];
7810: dsp_core.registers[DSP_REG_A0] = source[2];
7811:
7812: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7813: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7814: }
7815:
7816: static void dsp_mpyr_p_y1_y0_b(void)
7817: {
7818: Uint32 source[3];
7819:
7820: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7821: dsp_rnd56(source);
7822:
7823: dsp_core.registers[DSP_REG_B2] = source[0];
7824: dsp_core.registers[DSP_REG_B1] = source[1];
7825: dsp_core.registers[DSP_REG_B0] = source[2];
7826:
7827: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7828: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7829: }
7830:
7831: static void dsp_mpyr_m_y1_y0_b(void)
7832: {
7833: Uint32 source[3];
7834:
7835: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7836: dsp_rnd56(source);
7837:
7838: dsp_core.registers[DSP_REG_B2] = source[0];
7839: dsp_core.registers[DSP_REG_B1] = source[1];
7840: dsp_core.registers[DSP_REG_B0] = source[2];
7841:
7842: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7843: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7844: }
7845:
7846: static void dsp_mpyr_p_x0_y1_a(void)
7847: {
7848: Uint32 source[3];
7849:
7850: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7851: dsp_rnd56(source);
7852:
7853: dsp_core.registers[DSP_REG_A2] = source[0];
7854: dsp_core.registers[DSP_REG_A1] = source[1];
7855: dsp_core.registers[DSP_REG_A0] = source[2];
7856:
7857: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7858: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7859: }
7860:
7861: static void dsp_mpyr_m_x0_y1_a(void)
7862: {
7863: Uint32 source[3];
7864:
7865: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7866: dsp_rnd56(source);
7867:
7868: dsp_core.registers[DSP_REG_A2] = source[0];
7869: dsp_core.registers[DSP_REG_A1] = source[1];
7870: dsp_core.registers[DSP_REG_A0] = source[2];
7871:
7872: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7873: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7874: }
7875:
7876: static void dsp_mpyr_p_x0_y1_b(void)
7877: {
7878: Uint32 source[3];
7879:
7880: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7881: dsp_rnd56(source);
7882:
7883: dsp_core.registers[DSP_REG_B2] = source[0];
7884: dsp_core.registers[DSP_REG_B1] = source[1];
7885: dsp_core.registers[DSP_REG_B0] = source[2];
7886:
7887: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7888: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7889: }
7890:
7891: static void dsp_mpyr_m_x0_y1_b(void)
7892: {
7893: Uint32 source[3];
7894:
7895: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7896: dsp_rnd56(source);
7897:
7898: dsp_core.registers[DSP_REG_B2] = source[0];
7899: dsp_core.registers[DSP_REG_B1] = source[1];
7900: dsp_core.registers[DSP_REG_B0] = source[2];
7901:
7902: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7903: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7904: }
7905:
7906: static void dsp_mpyr_p_y0_x0_a(void)
7907: {
7908: Uint32 source[3];
7909:
7910: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7911: dsp_rnd56(source);
7912:
7913: dsp_core.registers[DSP_REG_A2] = source[0];
7914: dsp_core.registers[DSP_REG_A1] = source[1];
7915: dsp_core.registers[DSP_REG_A0] = source[2];
7916:
7917: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7918: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7919: }
7920:
7921: static void dsp_mpyr_m_y0_x0_a(void)
7922: {
7923: Uint32 source[3];
7924:
7925: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7926: dsp_rnd56(source);
7927:
7928: dsp_core.registers[DSP_REG_A2] = source[0];
7929: dsp_core.registers[DSP_REG_A1] = source[1];
7930: dsp_core.registers[DSP_REG_A0] = source[2];
7931:
7932: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7933: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7934: }
7935:
7936: static void dsp_mpyr_p_y0_x0_b(void)
7937: {
7938: Uint32 source[3];
7939:
7940: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7941: dsp_rnd56(source);
7942:
7943: dsp_core.registers[DSP_REG_B2] = source[0];
7944: dsp_core.registers[DSP_REG_B1] = source[1];
7945: dsp_core.registers[DSP_REG_B0] = source[2];
7946:
7947: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7948: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7949: }
7950:
7951: static void dsp_mpyr_m_y0_x0_b(void)
7952: {
7953: Uint32 source[3];
7954:
7955: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7956: dsp_rnd56(source);
7957:
7958: dsp_core.registers[DSP_REG_B2] = source[0];
7959: dsp_core.registers[DSP_REG_B1] = source[1];
7960: dsp_core.registers[DSP_REG_B0] = source[2];
7961:
7962: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7963: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7964: }
7965:
7966: static void dsp_mpyr_p_x1_y0_a(void)
7967: {
7968: Uint32 source[3];
7969:
7970: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7971: dsp_rnd56(source);
7972:
7973: dsp_core.registers[DSP_REG_A2] = source[0];
7974: dsp_core.registers[DSP_REG_A1] = source[1];
7975: dsp_core.registers[DSP_REG_A0] = source[2];
7976:
7977: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7978: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7979: }
7980:
7981: static void dsp_mpyr_m_x1_y0_a(void)
7982: {
7983: Uint32 source[3];
7984:
7985: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7986: dsp_rnd56(source);
7987:
7988: dsp_core.registers[DSP_REG_A2] = source[0];
7989: dsp_core.registers[DSP_REG_A1] = source[1];
7990: dsp_core.registers[DSP_REG_A0] = source[2];
7991:
7992: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7993: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7994: }
7995:
7996: static void dsp_mpyr_p_x1_y0_b(void)
7997: {
7998: Uint32 source[3];
7999:
8000: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
8001: dsp_rnd56(source);
8002:
8003: dsp_core.registers[DSP_REG_B2] = source[0];
8004: dsp_core.registers[DSP_REG_B1] = source[1];
8005: dsp_core.registers[DSP_REG_B0] = source[2];
8006:
8007: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8008: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8009: }
8010:
8011: static void dsp_mpyr_m_x1_y0_b(void)
8012: {
8013: Uint32 source[3];
8014:
8015: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
8016: dsp_rnd56(source);
8017:
8018: dsp_core.registers[DSP_REG_B2] = source[0];
8019: dsp_core.registers[DSP_REG_B1] = source[1];
8020: dsp_core.registers[DSP_REG_B0] = source[2];
8021:
8022: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8023: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8024: }
8025:
8026: static void dsp_mpyr_p_y1_x1_a(void)
8027: {
8028: Uint32 source[3];
8029:
8030: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
8031: dsp_rnd56(source);
8032:
8033: dsp_core.registers[DSP_REG_A2] = source[0];
8034: dsp_core.registers[DSP_REG_A1] = source[1];
8035: dsp_core.registers[DSP_REG_A0] = source[2];
8036:
8037: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8038: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8039: }
8040:
8041: static void dsp_mpyr_m_y1_x1_a(void)
8042: {
8043: Uint32 source[3];
8044:
8045: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
8046: dsp_rnd56(source);
8047:
8048: dsp_core.registers[DSP_REG_A2] = source[0];
8049: dsp_core.registers[DSP_REG_A1] = source[1];
8050: dsp_core.registers[DSP_REG_A0] = source[2];
8051:
8052: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8053: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8054: }
8055:
8056: static void dsp_mpyr_p_y1_x1_b(void)
8057: {
8058: Uint32 source[3];
8059:
8060: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
8061: dsp_rnd56(source);
8062:
8063: dsp_core.registers[DSP_REG_B2] = source[0];
8064: dsp_core.registers[DSP_REG_B1] = source[1];
8065: dsp_core.registers[DSP_REG_B0] = source[2];
8066:
8067: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8068: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8069: }
8070:
8071: static void dsp_mpyr_m_y1_x1_b(void)
8072: {
8073: Uint32 source[3];
8074:
8075: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
8076: dsp_rnd56(source);
8077:
8078: dsp_core.registers[DSP_REG_B2] = source[0];
8079: dsp_core.registers[DSP_REG_B1] = source[1];
8080: dsp_core.registers[DSP_REG_B0] = source[2];
8081:
8082: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8083: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8084: }
8085:
8086: static void dsp_neg_a(void)
8087: {
8088: Uint32 source[3], dest[3], overflowed;
8089:
8090: source[0] = dsp_core.registers[DSP_REG_A2];
8091: source[1] = dsp_core.registers[DSP_REG_A1];
8092: source[2] = dsp_core.registers[DSP_REG_A0];
8093:
8094: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8095:
8096: dest[0] = dest[1] = dest[2] = 0;
8097:
8098: dsp_sub56(source, dest);
8099:
8100: dsp_core.registers[DSP_REG_A2] = dest[0];
8101: dsp_core.registers[DSP_REG_A1] = dest[1];
8102: dsp_core.registers[DSP_REG_A0] = dest[2];
8103:
8104: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8105: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8106:
8107: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8108: }
8109:
8110: static void dsp_neg_b(void)
8111: {
8112: Uint32 source[3], dest[3], overflowed;
8113:
8114: source[0] = dsp_core.registers[DSP_REG_B2];
8115: source[1] = dsp_core.registers[DSP_REG_B1];
8116: source[2] = dsp_core.registers[DSP_REG_B0];
8117:
8118: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8119:
8120: dest[0] = dest[1] = dest[2] = 0;
8121:
8122: dsp_sub56(source, dest);
8123:
8124: dsp_core.registers[DSP_REG_B2] = dest[0];
8125: dsp_core.registers[DSP_REG_B1] = dest[1];
8126: dsp_core.registers[DSP_REG_B0] = dest[2];
8127:
8128: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8129: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8130:
8131: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8132: }
8133:
8134: static void dsp_nop(void)
8135: {
8136: }
8137:
8138: static void dsp_not_a(void)
8139: {
8140: dsp_core.registers[DSP_REG_A1] = ~dsp_core.registers[DSP_REG_A1];
8141: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8142:
8143: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8144: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8145: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8146: }
8147:
8148: static void dsp_not_b(void)
8149: {
8150: dsp_core.registers[DSP_REG_B1] = ~dsp_core.registers[DSP_REG_B1];
8151: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8152:
8153: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8154: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8155: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8156: }
8157:
8158: static void dsp_or_x0_a(void)
8159: {
8160: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X0];
8161: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8162:
8163: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8164: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8165: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8166: }
8167:
8168: static void dsp_or_x0_b(void)
8169: {
8170: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X0];
8171: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8172:
8173: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8174: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8175: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8176: }
8177:
8178: static void dsp_or_y0_a(void)
8179: {
8180: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y0];
8181: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8182:
8183: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8184: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8185: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8186: }
8187:
8188: static void dsp_or_y0_b(void)
8189: {
8190: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y0];
8191: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8192:
8193: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8194: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8195: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8196: }
8197:
8198: static void dsp_or_x1_a(void)
8199: {
8200: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X1];
8201: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8202:
8203: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8204: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8205: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8206: }
8207:
8208: static void dsp_or_x1_b(void)
8209: {
8210: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X1];
8211: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8212:
8213: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8214: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8215: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8216: }
8217:
8218: static void dsp_or_y1_a(void)
8219: {
8220: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y1];
8221: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8222:
8223: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8224: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8225: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8226: }
8227:
8228: static void dsp_or_y1_b(void)
8229: {
8230: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y1];
8231: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8232:
8233: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8234: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8235: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8236: }
8237:
8238: static void dsp_rnd_a(void)
8239: {
8240: Uint32 dest[3];
8241:
8242: dest[0] = dsp_core.registers[DSP_REG_A2];
8243: dest[1] = dsp_core.registers[DSP_REG_A1];
8244: dest[2] = dsp_core.registers[DSP_REG_A0];
8245:
8246: dsp_rnd56(dest);
8247:
8248: dsp_core.registers[DSP_REG_A2] = dest[0];
8249: dsp_core.registers[DSP_REG_A1] = dest[1];
8250: dsp_core.registers[DSP_REG_A0] = dest[2];
8251:
8252: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8253: }
8254:
8255: static void dsp_rnd_b(void)
8256: {
8257: Uint32 dest[3];
8258:
8259: dest[0] = dsp_core.registers[DSP_REG_B2];
8260: dest[1] = dsp_core.registers[DSP_REG_B1];
8261: dest[2] = dsp_core.registers[DSP_REG_B0];
8262:
8263: dsp_rnd56(dest);
8264:
8265: dsp_core.registers[DSP_REG_B2] = dest[0];
8266: dsp_core.registers[DSP_REG_B1] = dest[1];
8267: dsp_core.registers[DSP_REG_B0] = dest[2];
8268:
8269: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8270: }
8271:
8272: static void dsp_rol_a(void)
8273: {
8274: Uint32 newcarry;
8275:
8276: newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
8277:
8278: dsp_core.registers[DSP_REG_A1] <<= 1;
1.1.1.14! root 8279: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_SR] & 1;
1.1.1.6 root 8280: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
8281:
8282: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8283: dsp_core.registers[DSP_REG_SR] |= newcarry;
8284: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8285: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8286: }
8287:
8288: static void dsp_rol_b(void)
8289: {
8290: Uint32 newcarry;
8291:
8292: newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
8293:
8294: dsp_core.registers[DSP_REG_B1] <<= 1;
1.1.1.14! root 8295: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_SR] & 1;
1.1.1.6 root 8296: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
8297:
8298: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8299: dsp_core.registers[DSP_REG_SR] |= newcarry;
8300: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8301: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8302: }
8303:
8304: static void dsp_ror_a(void)
8305: {
8306: Uint32 newcarry;
8307:
8308: newcarry = dsp_core.registers[DSP_REG_A1] & 1;
8309:
8310: dsp_core.registers[DSP_REG_A1] >>= 1;
1.1.1.14! root 8311: dsp_core.registers[DSP_REG_A1] |= (dsp_core.registers[DSP_REG_SR] & 1)<<23;
1.1.1.6 root 8312:
8313: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8314: dsp_core.registers[DSP_REG_SR] |= newcarry;
8315: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8316: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8317: }
8318:
8319: static void dsp_ror_b(void)
8320: {
8321: Uint32 newcarry;
8322:
8323: newcarry = dsp_core.registers[DSP_REG_B1] & 1;
8324:
8325: dsp_core.registers[DSP_REG_B1] >>= 1;
1.1.1.14! root 8326: dsp_core.registers[DSP_REG_B1] |= (dsp_core.registers[DSP_REG_SR] & 1)<<23;
1.1.1.6 root 8327:
8328: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8329: dsp_core.registers[DSP_REG_SR] |= newcarry;
8330: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8331: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8332: }
8333:
8334: static void dsp_sbc_x_a(void)
8335: {
8336: Uint32 source[3], dest[3], curcarry;
8337: Uint16 newsr;
8338:
8339: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8340:
8341: dest[2] = dsp_core.registers[DSP_REG_A0];
8342: dest[1] = dsp_core.registers[DSP_REG_A1];
8343: dest[0] = dsp_core.registers[DSP_REG_A2];
8344:
8345: source[2] = dsp_core.registers[DSP_REG_X0];
8346: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8347: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8348:
8349: newsr = dsp_sub56(source, dest);
1.1.1.11 root 8350:
1.1.1.6 root 8351: if (curcarry) {
8352: source[0]=0; source[1]=0; source[2]=1;
8353: newsr |= dsp_sub56(source, dest);
8354: }
8355:
8356: dsp_core.registers[DSP_REG_A2] = dest[0];
8357: dsp_core.registers[DSP_REG_A1] = dest[1];
8358: dsp_core.registers[DSP_REG_A0] = dest[2];
8359:
8360: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8361:
8362: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8363: dsp_core.registers[DSP_REG_SR] |= newsr;
8364: }
8365:
8366: static void dsp_sbc_x_b(void)
8367: {
8368: Uint32 source[3], dest[3], curcarry;
8369: Uint16 newsr;
8370:
8371: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8372:
8373: dest[2] = dsp_core.registers[DSP_REG_B0];
8374: dest[1] = dsp_core.registers[DSP_REG_B1];
8375: dest[0] = dsp_core.registers[DSP_REG_B2];
8376:
8377: source[2] = dsp_core.registers[DSP_REG_X0];
8378: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8379: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8380:
8381: newsr = dsp_sub56(source, dest);
1.1.1.11 root 8382:
1.1.1.6 root 8383: if (curcarry) {
8384: source[0]=0; source[1]=0; source[2]=1;
8385: newsr |= dsp_sub56(source, dest);
8386: }
8387:
8388: dsp_core.registers[DSP_REG_B2] = dest[0];
8389: dsp_core.registers[DSP_REG_B1] = dest[1];
8390: dsp_core.registers[DSP_REG_B0] = dest[2];
8391:
8392: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8393:
8394: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8395: dsp_core.registers[DSP_REG_SR] |= newsr;
8396: }
8397:
8398: static void dsp_sbc_y_a(void)
8399: {
8400: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 8401: Uint16 newsr;
1.1 root 8402:
1.1.1.6 root 8403: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8404:
8405: dest[2] = dsp_core.registers[DSP_REG_A0];
8406: dest[1] = dsp_core.registers[DSP_REG_A1];
8407: dest[0] = dsp_core.registers[DSP_REG_A2];
8408:
8409: source[2] = dsp_core.registers[DSP_REG_Y0];
8410: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8411: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8412:
8413: newsr = dsp_sub56(source, dest);
1.1.1.11 root 8414:
1.1.1.6 root 8415: if (curcarry) {
8416: source[0]=0; source[1]=0; source[2]=1;
8417: newsr |= dsp_sub56(source, dest);
8418: }
8419:
8420: dsp_core.registers[DSP_REG_A2] = dest[0];
8421: dsp_core.registers[DSP_REG_A1] = dest[1];
8422: dsp_core.registers[DSP_REG_A0] = dest[2];
8423:
8424: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8425:
8426: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8427: dsp_core.registers[DSP_REG_SR] |= newsr;
8428: }
8429:
8430: static void dsp_sbc_y_b(void)
8431: {
8432: Uint32 source[3], dest[3], curcarry;
8433: Uint16 newsr;
8434:
8435: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8436:
8437: dest[2] = dsp_core.registers[DSP_REG_B0];
8438: dest[1] = dsp_core.registers[DSP_REG_B1];
8439: dest[0] = dsp_core.registers[DSP_REG_B2];
8440:
8441: source[2] = dsp_core.registers[DSP_REG_Y0];
8442: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8443: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8444:
8445: newsr = dsp_sub56(source, dest);
1.1.1.11 root 8446:
1.1.1.6 root 8447: if (curcarry) {
8448: source[0]=0; source[1]=0; source[2]=1;
8449: newsr |= dsp_sub56(source, dest);
1.1 root 8450: }
8451:
1.1.1.6 root 8452: dsp_core.registers[DSP_REG_B2] = dest[0];
8453: dsp_core.registers[DSP_REG_B1] = dest[1];
8454: dsp_core.registers[DSP_REG_B0] = dest[2];
8455:
8456: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8457:
8458: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8459: dsp_core.registers[DSP_REG_SR] |= newsr;
8460: }
8461:
8462: static void dsp_sub_b_a(void)
8463: {
8464: Uint32 source[3], dest[3];
8465: Uint16 newsr;
8466:
8467: dest[2] = dsp_core.registers[DSP_REG_A0];
8468: dest[1] = dsp_core.registers[DSP_REG_A1];
8469: dest[0] = dsp_core.registers[DSP_REG_A2];
8470:
8471: source[2] = dsp_core.registers[DSP_REG_B0];
8472: source[1] = dsp_core.registers[DSP_REG_B1];
8473: source[0] = dsp_core.registers[DSP_REG_B2];
8474:
1.1 root 8475: newsr = dsp_sub56(source, dest);
8476:
1.1.1.6 root 8477: dsp_core.registers[DSP_REG_A2] = dest[0];
8478: dsp_core.registers[DSP_REG_A1] = dest[1];
8479: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8480:
1.1.1.6 root 8481: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8482:
1.1.1.6 root 8483: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8484: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8485: }
8486:
1.1.1.6 root 8487: static void dsp_sub_a_b(void)
1.1 root 8488: {
1.1.1.6 root 8489: Uint32 source[3], dest[3];
1.1.1.2 root 8490: Uint16 newsr;
1.1 root 8491:
1.1.1.6 root 8492: dest[2] = dsp_core.registers[DSP_REG_B0];
8493: dest[1] = dsp_core.registers[DSP_REG_B1];
8494: dest[0] = dsp_core.registers[DSP_REG_B2];
8495:
8496: source[2] = dsp_core.registers[DSP_REG_A0];
8497: source[1] = dsp_core.registers[DSP_REG_A1];
8498: source[0] = dsp_core.registers[DSP_REG_A2];
8499:
8500: newsr = dsp_sub56(source, dest);
8501:
8502: dsp_core.registers[DSP_REG_B2] = dest[0];
8503: dsp_core.registers[DSP_REG_B1] = dest[1];
8504: dsp_core.registers[DSP_REG_B0] = dest[2];
8505:
8506: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8507:
8508: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8509: dsp_core.registers[DSP_REG_SR] |= newsr;
8510: }
8511:
8512: static void dsp_sub_x_a(void)
8513: {
8514: Uint32 source[3], dest[3];
8515: Uint16 newsr;
8516:
8517: dest[2] = dsp_core.registers[DSP_REG_A0];
8518: dest[1] = dsp_core.registers[DSP_REG_A1];
8519: dest[0] = dsp_core.registers[DSP_REG_A2];
8520:
8521: source[2] = dsp_core.registers[DSP_REG_X0];
8522: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8523: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8524:
8525: newsr = dsp_sub56(source, dest);
8526:
8527: dsp_core.registers[DSP_REG_A2] = dest[0];
8528: dsp_core.registers[DSP_REG_A1] = dest[1];
8529: dsp_core.registers[DSP_REG_A0] = dest[2];
8530:
8531: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8532:
8533: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8534: dsp_core.registers[DSP_REG_SR] |= newsr;
8535: }
8536:
8537: static void dsp_sub_x_b(void)
8538: {
8539: Uint32 source[3], dest[3];
8540: Uint16 newsr;
8541:
8542: dest[2] = dsp_core.registers[DSP_REG_B0];
8543: dest[1] = dsp_core.registers[DSP_REG_B1];
8544: dest[0] = dsp_core.registers[DSP_REG_B2];
8545:
8546: source[2] = dsp_core.registers[DSP_REG_X0];
8547: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8548: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8549:
8550: newsr = dsp_sub56(source, dest);
8551:
8552: dsp_core.registers[DSP_REG_B2] = dest[0];
8553: dsp_core.registers[DSP_REG_B1] = dest[1];
8554: dsp_core.registers[DSP_REG_B0] = dest[2];
8555:
8556: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8557:
8558: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8559: dsp_core.registers[DSP_REG_SR] |= newsr;
8560: }
8561:
8562: static void dsp_sub_y_a(void)
8563: {
8564: Uint32 source[3], dest[3];
8565: Uint16 newsr;
8566:
8567: dest[2] = dsp_core.registers[DSP_REG_A0];
8568: dest[1] = dsp_core.registers[DSP_REG_A1];
8569: dest[0] = dsp_core.registers[DSP_REG_A2];
8570:
8571: source[2] = dsp_core.registers[DSP_REG_Y0];
8572: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8573: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8574:
8575: newsr = dsp_sub56(source, dest);
8576:
8577: dsp_core.registers[DSP_REG_A2] = dest[0];
8578: dsp_core.registers[DSP_REG_A1] = dest[1];
8579: dsp_core.registers[DSP_REG_A0] = dest[2];
8580:
8581: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8582:
8583: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8584: dsp_core.registers[DSP_REG_SR] |= newsr;
8585: }
8586:
8587: static void dsp_sub_y_b(void)
8588: {
8589: Uint32 source[3], dest[3];
8590: Uint16 newsr;
8591:
8592: dest[2] = dsp_core.registers[DSP_REG_B0];
8593: dest[1] = dsp_core.registers[DSP_REG_B1];
8594: dest[0] = dsp_core.registers[DSP_REG_B2];
8595:
8596: source[2] = dsp_core.registers[DSP_REG_Y0];
8597: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8598: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8599:
8600: newsr = dsp_sub56(source, dest);
8601:
8602: dsp_core.registers[DSP_REG_B2] = dest[0];
8603: dsp_core.registers[DSP_REG_B1] = dest[1];
8604: dsp_core.registers[DSP_REG_B0] = dest[2];
8605:
8606: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8607:
8608: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8609: dsp_core.registers[DSP_REG_SR] |= newsr;
8610: }
8611:
8612: static void dsp_sub_x0_a(void)
8613: {
8614: Uint32 source[3], dest[3];
8615: Uint16 newsr;
8616:
8617: dest[2] = dsp_core.registers[DSP_REG_A0];
8618: dest[1] = dsp_core.registers[DSP_REG_A1];
8619: dest[0] = dsp_core.registers[DSP_REG_A2];
8620:
8621: source[2] = 0;
8622: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 8623: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8624:
8625: newsr = dsp_sub56(source, dest);
8626:
8627: dsp_core.registers[DSP_REG_A2] = dest[0];
8628: dsp_core.registers[DSP_REG_A1] = dest[1];
8629: dsp_core.registers[DSP_REG_A0] = dest[2];
8630:
8631: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8632:
8633: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8634: dsp_core.registers[DSP_REG_SR] |= newsr;
8635: }
8636:
8637: static void dsp_sub_x0_b(void)
8638: {
8639: Uint32 source[3], dest[3];
8640: Uint16 newsr;
8641:
8642: dest[2] = dsp_core.registers[DSP_REG_B0];
8643: dest[1] = dsp_core.registers[DSP_REG_B1];
8644: dest[0] = dsp_core.registers[DSP_REG_B2];
8645:
8646: source[2] = 0;
8647: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 8648: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8649:
8650: newsr = dsp_sub56(source, dest);
8651:
8652: dsp_core.registers[DSP_REG_B2] = dest[0];
8653: dsp_core.registers[DSP_REG_B1] = dest[1];
8654: dsp_core.registers[DSP_REG_B0] = dest[2];
8655:
8656: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8657:
8658: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8659: dsp_core.registers[DSP_REG_SR] |= newsr;
8660: }
8661:
8662: static void dsp_sub_y0_a(void)
8663: {
8664: Uint32 source[3], dest[3];
8665: Uint16 newsr;
8666:
8667: dest[2] = dsp_core.registers[DSP_REG_A0];
8668: dest[1] = dsp_core.registers[DSP_REG_A1];
8669: dest[0] = dsp_core.registers[DSP_REG_A2];
8670:
8671: source[2] = 0;
8672: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 8673: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8674:
8675: newsr = dsp_sub56(source, dest);
1.1 root 8676:
1.1.1.6 root 8677: dsp_core.registers[DSP_REG_A2] = dest[0];
8678: dsp_core.registers[DSP_REG_A1] = dest[1];
8679: dsp_core.registers[DSP_REG_A0] = dest[2];
8680:
8681: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8682:
8683: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8684: dsp_core.registers[DSP_REG_SR] |= newsr;
8685: }
8686:
8687: static void dsp_sub_y0_b(void)
8688: {
8689: Uint32 source[3], dest[3];
8690: Uint16 newsr;
8691:
8692: dest[2] = dsp_core.registers[DSP_REG_B0];
8693: dest[1] = dsp_core.registers[DSP_REG_B1];
8694: dest[0] = dsp_core.registers[DSP_REG_B2];
8695:
8696: source[2] = 0;
8697: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 8698: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8699:
8700: newsr = dsp_sub56(source, dest);
8701:
8702: dsp_core.registers[DSP_REG_B2] = dest[0];
8703: dsp_core.registers[DSP_REG_B1] = dest[1];
8704: dsp_core.registers[DSP_REG_B0] = dest[2];
8705:
8706: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8707:
8708: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8709: dsp_core.registers[DSP_REG_SR] |= newsr;
8710: }
8711:
8712: static void dsp_sub_x1_a(void)
8713: {
8714: Uint32 source[3], dest[3];
8715: Uint16 newsr;
8716:
8717: dest[2] = dsp_core.registers[DSP_REG_A0];
8718: dest[1] = dsp_core.registers[DSP_REG_A1];
8719: dest[0] = dsp_core.registers[DSP_REG_A2];
8720:
8721: source[2] = 0;
8722: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8723: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8724:
8725: newsr = dsp_sub56(source, dest);
8726:
8727: dsp_core.registers[DSP_REG_A2] = dest[0];
8728: dsp_core.registers[DSP_REG_A1] = dest[1];
8729: dsp_core.registers[DSP_REG_A0] = dest[2];
8730:
8731: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8732:
8733: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8734: dsp_core.registers[DSP_REG_SR] |= newsr;
8735: }
8736:
8737: static void dsp_sub_x1_b(void)
8738: {
8739: Uint32 source[3], dest[3];
8740: Uint16 newsr;
8741:
8742: dest[2] = dsp_core.registers[DSP_REG_B0];
8743: dest[1] = dsp_core.registers[DSP_REG_B1];
8744: dest[0] = dsp_core.registers[DSP_REG_B2];
8745:
8746: source[2] = 0;
8747: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8748: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8749:
8750: newsr = dsp_sub56(source, dest);
8751:
8752: dsp_core.registers[DSP_REG_B2] = dest[0];
8753: dsp_core.registers[DSP_REG_B1] = dest[1];
8754: dsp_core.registers[DSP_REG_B0] = dest[2];
8755:
8756: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8757:
8758: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8759: dsp_core.registers[DSP_REG_SR] |= newsr;
8760: }
8761:
8762: static void dsp_sub_y1_a(void)
8763: {
8764: Uint32 source[3], dest[3];
8765: Uint16 newsr;
8766:
8767: dest[2] = dsp_core.registers[DSP_REG_A0];
8768: dest[1] = dsp_core.registers[DSP_REG_A1];
8769: dest[0] = dsp_core.registers[DSP_REG_A2];
8770:
8771: source[2] = 0;
8772: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8773: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8774:
8775: newsr = dsp_sub56(source, dest);
8776:
8777: dsp_core.registers[DSP_REG_A2] = dest[0];
8778: dsp_core.registers[DSP_REG_A1] = dest[1];
8779: dsp_core.registers[DSP_REG_A0] = dest[2];
8780:
8781: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8782:
8783: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8784: dsp_core.registers[DSP_REG_SR] |= newsr;
8785: }
8786:
8787: static void dsp_sub_y1_b(void)
8788: {
8789: Uint32 source[3], dest[3];
8790: Uint16 newsr;
8791:
8792: dest[2] = dsp_core.registers[DSP_REG_B0];
8793: dest[1] = dsp_core.registers[DSP_REG_B1];
8794: dest[0] = dsp_core.registers[DSP_REG_B2];
8795:
8796: source[2] = 0;
8797: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8798: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8799:
8800: newsr = dsp_sub56(source, dest);
8801:
8802: dsp_core.registers[DSP_REG_B2] = dest[0];
8803: dsp_core.registers[DSP_REG_B1] = dest[1];
8804: dsp_core.registers[DSP_REG_B0] = dest[2];
8805:
8806: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8807:
8808: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8809: dsp_core.registers[DSP_REG_SR] |= newsr;
8810: }
8811:
8812: static void dsp_subl_a(void)
8813: {
8814: Uint32 source[3], dest[3];
8815: Uint16 newsr;
8816:
8817: dest[0] = dsp_core.registers[DSP_REG_A2];
8818: dest[1] = dsp_core.registers[DSP_REG_A1];
8819: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 8820: newsr = dsp_asl56(dest);
8821:
1.1.1.6 root 8822: source[0] = dsp_core.registers[DSP_REG_B2];
8823: source[1] = dsp_core.registers[DSP_REG_B1];
8824: source[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 8825: newsr |= dsp_sub56(source, dest);
8826:
1.1.1.6 root 8827: dsp_core.registers[DSP_REG_A2] = dest[0];
8828: dsp_core.registers[DSP_REG_A1] = dest[1];
8829: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8830:
1.1.1.6 root 8831: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8832:
1.1.1.6 root 8833: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8834: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8835: }
8836:
1.1.1.6 root 8837: static void dsp_subl_b(void)
1.1 root 8838: {
1.1.1.6 root 8839: Uint32 source[3], dest[3];
1.1.1.2 root 8840: Uint16 newsr;
1.1 root 8841:
1.1.1.6 root 8842: dest[0] = dsp_core.registers[DSP_REG_B2];
8843: dest[1] = dsp_core.registers[DSP_REG_B1];
8844: dest[2] = dsp_core.registers[DSP_REG_B0];
8845: newsr = dsp_asl56(dest);
1.1 root 8846:
1.1.1.6 root 8847: source[0] = dsp_core.registers[DSP_REG_A2];
8848: source[1] = dsp_core.registers[DSP_REG_A1];
8849: source[2] = dsp_core.registers[DSP_REG_A0];
8850: newsr |= dsp_sub56(source, dest);
8851:
8852: dsp_core.registers[DSP_REG_B2] = dest[0];
8853: dsp_core.registers[DSP_REG_B1] = dest[1];
8854: dsp_core.registers[DSP_REG_B0] = dest[2];
8855:
8856: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8857:
8858: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8859: dsp_core.registers[DSP_REG_SR] |= newsr;
8860: }
8861:
8862: static void dsp_subr_a(void)
8863: {
8864: Uint32 source[3], dest[3];
8865: Uint16 newsr;
8866:
8867: dest[0] = dsp_core.registers[DSP_REG_A2];
8868: dest[1] = dsp_core.registers[DSP_REG_A1];
8869: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1.1.11 root 8870:
1.1 root 8871: newsr = dsp_asr56(dest);
8872:
1.1.1.6 root 8873: source[0] = dsp_core.registers[DSP_REG_B2];
8874: source[1] = dsp_core.registers[DSP_REG_B1];
8875: source[2] = dsp_core.registers[DSP_REG_B0];
1.1.1.11 root 8876:
1.1 root 8877: newsr |= dsp_sub56(source, dest);
8878:
1.1.1.6 root 8879: dsp_core.registers[DSP_REG_A2] = dest[0];
8880: dsp_core.registers[DSP_REG_A1] = dest[1];
8881: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8882:
1.1.1.6 root 8883: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8884:
1.1.1.6 root 8885: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8886: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8887: }
8888:
1.1.1.6 root 8889: static void dsp_subr_b(void)
1.1 root 8890: {
1.1.1.6 root 8891: Uint32 source[3], dest[3];
8892: Uint16 newsr;
1.1 root 8893:
1.1.1.6 root 8894: dest[0] = dsp_core.registers[DSP_REG_B2];
8895: dest[1] = dsp_core.registers[DSP_REG_B1];
8896: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1.1.11 root 8897:
1.1.1.6 root 8898: newsr = dsp_asr56(dest);
1.1 root 8899:
1.1.1.6 root 8900: source[0] = dsp_core.registers[DSP_REG_A2];
8901: source[1] = dsp_core.registers[DSP_REG_A1];
8902: source[2] = dsp_core.registers[DSP_REG_A0];
1.1.1.11 root 8903:
1.1.1.6 root 8904: newsr |= dsp_sub56(source, dest);
1.1 root 8905:
1.1.1.6 root 8906: dsp_core.registers[DSP_REG_B2] = dest[0];
8907: dsp_core.registers[DSP_REG_B1] = dest[1];
8908: dsp_core.registers[DSP_REG_B0] = dest[2];
8909:
8910: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8911:
8912: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8913: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8914: }
8915:
1.1.1.6 root 8916: static void dsp_tfr_b_a(void)
1.1 root 8917: {
1.1.1.6 root 8918: dsp_core.registers[DSP_REG_A0] = dsp_core.registers[DSP_REG_B0];
8919: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_B1];
8920: dsp_core.registers[DSP_REG_A2] = dsp_core.registers[DSP_REG_B2];
8921: }
1.1 root 8922:
1.1.1.6 root 8923: static void dsp_tfr_a_b(void)
8924: {
8925: dsp_core.registers[DSP_REG_B0] = dsp_core.registers[DSP_REG_A0];
8926: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_A1];
8927: dsp_core.registers[DSP_REG_B2] = dsp_core.registers[DSP_REG_A2];
8928: }
8929:
8930: static void dsp_tfr_x0_a(void)
8931: {
1.1.1.11 root 8932: dsp_write_reg(DSP_REG_A, dsp_core.registers[DSP_REG_X0]);
1.1.1.6 root 8933: }
8934:
8935: static void dsp_tfr_x0_b(void)
8936: {
1.1.1.11 root 8937: dsp_write_reg(DSP_REG_B, dsp_core.registers[DSP_REG_X0]);
1.1.1.6 root 8938: }
8939:
8940: static void dsp_tfr_y0_a(void)
8941: {
1.1.1.11 root 8942: dsp_write_reg(DSP_REG_A, dsp_core.registers[DSP_REG_Y0]);
1.1.1.6 root 8943: }
8944:
8945: static void dsp_tfr_y0_b(void)
8946: {
1.1.1.11 root 8947: dsp_write_reg(DSP_REG_B, dsp_core.registers[DSP_REG_Y0]);
1.1.1.6 root 8948: }
8949:
8950: static void dsp_tfr_x1_a(void)
8951: {
1.1.1.11 root 8952: dsp_write_reg(DSP_REG_A, dsp_core.registers[DSP_REG_X1]);
1.1.1.6 root 8953: }
8954:
8955: static void dsp_tfr_x1_b(void)
8956: {
1.1.1.11 root 8957: dsp_write_reg(DSP_REG_B, dsp_core.registers[DSP_REG_X1]);
1.1.1.6 root 8958: }
8959:
8960: static void dsp_tfr_y1_a(void)
8961: {
1.1.1.11 root 8962: dsp_write_reg(DSP_REG_A, dsp_core.registers[DSP_REG_Y1]);
1.1.1.6 root 8963: }
8964:
8965: static void dsp_tfr_y1_b(void)
8966: {
1.1.1.11 root 8967: dsp_write_reg(DSP_REG_B, dsp_core.registers[DSP_REG_Y1]);
1.1.1.6 root 8968: }
8969:
8970: static void dsp_tst_a(void)
8971: {
8972: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_A2],
1.1.1.7 root 8973: dsp_core.registers[DSP_REG_A1],
8974: dsp_core.registers[DSP_REG_A0]);
1.1.1.6 root 8975:
8976: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8977: }
8978:
8979: static void dsp_tst_b(void)
8980: {
8981: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_B2],
1.1.1.7 root 8982: dsp_core.registers[DSP_REG_B1],
8983: dsp_core.registers[DSP_REG_B0]);
1.1 root 8984:
1.1.1.6 root 8985: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
1.1 root 8986: }
8987:
1.1.1.2 root 8988: /*
8989: vim:ts=4:sw=4:
8990: */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.