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1.1 root 1: /*
1.1.1.2 root 2: DSP M56001 emulation
1.1.1.4 root 3: Instructions interpreter
1.1.1.2 root 4:
5: (C) 2003-2008 ARAnyM developer team
6:
7: This program is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2 of the License, or
10: (at your option) any later version.
11:
12: This program is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
18: along with this program; if not, write to the Free Software
19: Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20: */
21:
1.1.1.7 ! root 22: /*
! 23: DSP memory mapping
! 24: ------------------
! 25:
! 26: The memory map is configured as follows :
! 27: Program space P is one contiguous block of 32K dsp Words
! 28: X and Y data space are each separate 16K dsp Word blocks.
! 29: Both X and Y can be accessed as blocks starting at 0 or 16K.
! 30: Program space physically overlaps both X and Y data spaces.
! 31: Y: memory is mapped at address $0 in P memory
! 32: X: memory is mapped at address $4000 in P memory
! 33:
! 34: The DSP external RAM is zero waitstate, but there is a penalty for
! 35: accessing it twice in a single instruction, because there is only
! 36: one external data bus.
! 37: The internal buses are all separate (0 waitstate)
! 38:
! 39:
! 40: X: Y: P:
! 41: $ffff |--------------+--------------+--------------|
! 42: | Int. I/O | Ext. I/O | |
! 43: $ffc0 |--------------+--------------+ |
! 44: | | | |
! 45: | Reserved | Reserved | Reserved |
! 46: | | | |
! 47: | | | |
! 48: | | | |
! 49: $8000 |--------------+--------------+--------------|
! 50: | | | |
! 51: | 16k Shadow | 16k Shadow | |
! 52: | | | 32K |
! 53: $4000 |--------------+--------------| Program |
! 54: | 16K | 16K | RAM |
! 55: | External | External | |
! 56: | RAM | RAM | |
! 57: $0200 |--------------+--------------+--------------|
! 58: | Log table or | Sin table or | |
! 59: | external mem | external mem | Internal |
! 60: $0100 |--------------+--------------+ program |
! 61: | Internal X | Internal Y | memory |
! 62: | memory | memory | |
! 63: $0000 |--------------+--------------+--------------|
! 64:
! 65:
! 66: Special Note : As the Falcon DSP is a 0 waitstate access memory, I've simplified a little the cycle counting.
! 67: If this DSP emulator code is used in another project, one should take into account the bus control register (BCR) waitstates.
! 68: */
! 69:
1.1.1.2 root 70: #ifdef HAVE_CONFIG_H
71: #include "config.h"
72: #endif
73:
1.1.1.6 root 74: #include <stdbool.h>
75:
1.1.1.2 root 76: #include "dsp_core.h"
1.1 root 77: #include "dsp_cpu.h"
78: #include "dsp_disasm.h"
1.1.1.6 root 79: #include "log.h"
80: # include "main.h"
1.1 root 81:
82:
1.1.1.2 root 83: #define DSP_COUNT_IPS 0 /* Count instruction per seconds */
84:
1.1 root 85:
86: /**********************************
87: * Defines
88: **********************************/
89:
1.1.1.6 root 90: #define SIGN_PLUS 0
91: #define SIGN_MINUS 1
1.1.1.4 root 92:
1.1 root 93: /**********************************
94: * Variables
95: **********************************/
96:
1.1.1.4 root 97: /* Instructions per second */
98: static Uint32 start_time;
99: static Uint32 num_inst;
100:
1.1 root 101: /* Length of current instruction */
1.1.1.2 root 102: static Uint32 cur_inst_len; /* =0:jump, >0:increment */
1.1 root 103:
104: /* Current instruction */
1.1.1.4 root 105: static Uint32 cur_inst;
1.1 root 106:
1.1.1.7 ! root 107: /* Counts the number of access to the external memory for one instruction */
! 108: static Uint16 nb_access_to_extMemory;
! 109:
1.1.1.6 root 110: /* DSP is in disasm mode ? */
111: /* If yes, stack overflow, underflow and illegal instructions messages are not displayed */
112: static bool isDsp_in_disasm_mode;
1.1 root 113:
1.1.1.7 ! root 114: static char str_disasm_memory[2][50]; /* Buffer for memory change text in disasm mode */
1.1.1.5 root 115: static Uint16 disasm_memory_ptr; /* Pointer for memory change in disasm mode */
1.1 root 116:
117: /**********************************
118: * Functions
119: **********************************/
120:
121: typedef void (*dsp_emul_t)(void);
122:
123: static void dsp_postexecute_update_pc(void);
124: static void dsp_postexecute_interrupts(void);
125:
1.1.1.5 root 126: static void dsp_setInterruptIPL(Uint32 value);
127:
1.1.1.6 root 128: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2);
1.1.1.2 root 129:
130: static Uint32 read_memory(int space, Uint16 address);
1.1.1.6 root 131: static inline Uint32 read_memory_p(Uint16 address);
1.1.1.2 root 132: static Uint32 read_memory_disasm(int space, Uint16 address);
1.1.1.6 root 133:
134: static inline void write_memory(int space, Uint16 address, Uint32 value);
135: static void write_memory_raw(int space, Uint16 address, Uint32 value);
1.1.1.4 root 136: static void write_memory_disasm(int space, Uint16 address, Uint32 value);
1.1.1.6 root 137:
1.1.1.4 root 138: static void dsp_write_reg(Uint32 numreg, Uint32 value);
1.1 root 139:
1.1.1.4 root 140: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly);
1.1.1.2 root 141: static void dsp_stack_pop(Uint32 *curpc, Uint32 *cursr);
1.1.1.4 root 142: static void dsp_compute_ssh_ssl(void);
1.1 root 143:
144: static void opcode8h_0(void);
145:
1.1.1.2 root 146: static void dsp_update_rn(Uint32 numreg, Sint16 modifier);
147: static void dsp_update_rn_bitreverse(Uint32 numreg);
148: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier);
149: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr);
150: static int dsp_calc_cc(Uint32 cc_code);
1.1 root 151:
152: static void dsp_undefined(void);
153:
154: /* Instructions without parallel moves */
155: static void dsp_andi(void);
1.1.1.4 root 156: static void dsp_bchg_aa(void);
157: static void dsp_bchg_ea(void);
158: static void dsp_bchg_pp(void);
159: static void dsp_bchg_reg(void);
160: static void dsp_bclr_aa(void);
161: static void dsp_bclr_ea(void);
162: static void dsp_bclr_pp(void);
163: static void dsp_bclr_reg(void);
164: static void dsp_bset_aa(void);
165: static void dsp_bset_ea(void);
166: static void dsp_bset_pp(void);
167: static void dsp_bset_reg(void);
168: static void dsp_btst_aa(void);
169: static void dsp_btst_ea(void);
170: static void dsp_btst_pp(void);
171: static void dsp_btst_reg(void);
1.1 root 172: static void dsp_div(void);
173: static void dsp_enddo(void);
174: static void dsp_illegal(void);
1.1.1.4 root 175: static void dsp_jcc_imm(void);
176: static void dsp_jcc_ea(void);
177: static void dsp_jclr_aa(void);
178: static void dsp_jclr_ea(void);
179: static void dsp_jclr_pp(void);
180: static void dsp_jclr_reg(void);
181: static void dsp_jmp_ea(void);
182: static void dsp_jmp_imm(void);
183: static void dsp_jscc_ea(void);
184: static void dsp_jscc_imm(void);
185: static void dsp_jsclr_aa(void);
186: static void dsp_jsclr_ea(void);
187: static void dsp_jsclr_pp(void);
188: static void dsp_jsclr_reg(void);
189: static void dsp_jset_aa(void);
190: static void dsp_jset_ea(void);
191: static void dsp_jset_pp(void);
192: static void dsp_jset_reg(void);
193: static void dsp_jsr_ea(void);
194: static void dsp_jsr_imm(void);
195: static void dsp_jsset_aa(void);
196: static void dsp_jsset_ea(void);
197: static void dsp_jsset_pp(void);
198: static void dsp_jsset_reg(void);
1.1 root 199: static void dsp_lua(void);
1.1.1.4 root 200: static void dsp_movem_ea(void);
201: static void dsp_movem_aa(void);
1.1 root 202: static void dsp_nop(void);
203: static void dsp_norm(void);
204: static void dsp_ori(void);
205: static void dsp_reset(void);
206: static void dsp_rti(void);
207: static void dsp_rts(void);
208: static void dsp_stop(void);
209: static void dsp_swi(void);
210: static void dsp_tcc(void);
211: static void dsp_wait(void);
212:
1.1.1.3 root 213: static void dsp_do_ea(void);
214: static void dsp_do_aa(void);
215: static void dsp_do_imm(void);
216: static void dsp_do_reg(void);
217: static void dsp_rep_aa(void);
218: static void dsp_rep_ea(void);
219: static void dsp_rep_imm(void);
220: static void dsp_rep_reg(void);
221: static void dsp_movec_aa(void);
222: static void dsp_movec_ea(void);
223: static void dsp_movec_imm(void);
224: static void dsp_movec_reg(void);
1.1 root 225: static void dsp_movep_0(void);
226: static void dsp_movep_1(void);
1.1.1.4 root 227: static void dsp_movep_23(void);
1.1 root 228:
229: /* Parallel move analyzer */
1.1.1.2 root 230: static int dsp_pm_read_accu24(int numreg, Uint32 *dest);
1.1 root 231: static void dsp_pm_0(void);
232: static void dsp_pm_1(void);
233: static void dsp_pm_2(void);
234: static void dsp_pm_2_2(void);
235: static void dsp_pm_3(void);
236: static void dsp_pm_4(void);
1.1.1.4 root 237: static void dsp_pm_4x(void);
1.1 root 238: static void dsp_pm_5(void);
239: static void dsp_pm_8(void);
240:
241: /* 56bits arithmetic */
1.1.1.2 root 242: static Uint16 dsp_abs56(Uint32 *dest);
243: static Uint16 dsp_asl56(Uint32 *dest);
244: static Uint16 dsp_asr56(Uint32 *dest);
245: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest);
246: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest);
1.1.1.5 root 247: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe);
1.1.1.2 root 248: static void dsp_rnd56(Uint32 *dest);
1.1 root 249:
250: /* Instructions with parallel moves */
1.1.1.6 root 251: static void dsp_abs_a(void);
252: static void dsp_abs_b(void);
253: static void dsp_adc_x_a(void);
254: static void dsp_adc_x_b(void);
255: static void dsp_adc_y_a(void);
256: static void dsp_adc_y_b(void);
257: static void dsp_add_b_a(void);
258: static void dsp_add_a_b(void);
259: static void dsp_add_x_a(void);
260: static void dsp_add_x_b(void);
261: static void dsp_add_y_a(void);
262: static void dsp_add_y_b(void);
263: static void dsp_add_x0_a(void);
264: static void dsp_add_x0_b(void);
265: static void dsp_add_y0_a(void);
266: static void dsp_add_y0_b(void);
267: static void dsp_add_x1_a(void);
268: static void dsp_add_x1_b(void);
269: static void dsp_add_y1_a(void);
270: static void dsp_add_y1_b(void);
271: static void dsp_addl_b_a(void);
272: static void dsp_addl_b_a(void);
273: static void dsp_addl_a_b(void);
274: static void dsp_addr_b_a(void);
275: static void dsp_addr_a_b(void);
276: static void dsp_and_x0_a(void);
277: static void dsp_and_x0_b(void);
278: static void dsp_and_y0_a(void);
279: static void dsp_and_y0_b(void);
280: static void dsp_and_x1_a(void);
281: static void dsp_and_x1_b(void);
282: static void dsp_and_y1_a(void);
283: static void dsp_and_y1_b(void);
1.1.1.7 ! root 284: static void dsp_asl_a(void);
! 285: static void dsp_asl_b(void);
! 286: static void dsp_asr_a(void);
! 287: static void dsp_asr_b(void);
1.1.1.6 root 288: static void dsp_clr_a(void);
289: static void dsp_clr_b(void);
290: static void dsp_cmp_b_a(void);
291: static void dsp_cmp_a_b(void);
292: static void dsp_cmp_x0_a(void);
293: static void dsp_cmp_x0_b(void);
294: static void dsp_cmp_y0_a(void);
295: static void dsp_cmp_y0_b(void);
296: static void dsp_cmp_x1_a(void);
297: static void dsp_cmp_x1_b(void);
298: static void dsp_cmp_y1_a(void);
299: static void dsp_cmp_y1_b(void);
300: static void dsp_cmpm_b_a(void);
301: static void dsp_cmpm_a_b(void);
302: static void dsp_cmpm_x0_a(void);
303: static void dsp_cmpm_x0_b(void);
304: static void dsp_cmpm_y0_a(void);
305: static void dsp_cmpm_y0_b(void);
306: static void dsp_cmpm_x1_a(void);
307: static void dsp_cmpm_x1_b(void);
308: static void dsp_cmpm_y1_a(void);
309: static void dsp_cmpm_y1_b(void);
310: static void dsp_eor_x0_a(void);
311: static void dsp_eor_x0_b(void);
312: static void dsp_eor_y0_a(void);
313: static void dsp_eor_y0_b(void);
314: static void dsp_eor_x1_a(void);
315: static void dsp_eor_x1_b(void);
316: static void dsp_eor_y1_a(void);
317: static void dsp_eor_y1_b(void);
318: static void dsp_lsl_a(void);
319: static void dsp_lsl_b(void);
320: static void dsp_lsr_a(void);
321: static void dsp_lsr_b(void);
322: static void dsp_mac_p_x0_x0_a(void);
323: static void dsp_mac_m_x0_x0_a(void);
324: static void dsp_mac_p_x0_x0_b(void);
325: static void dsp_mac_m_x0_x0_b(void);
326: static void dsp_mac_p_y0_y0_a(void);
327: static void dsp_mac_m_y0_y0_a(void);
328: static void dsp_mac_p_y0_y0_b(void);
329: static void dsp_mac_m_y0_y0_b(void);
330: static void dsp_mac_p_x1_x0_a(void);
331: static void dsp_mac_m_x1_x0_a(void);
332: static void dsp_mac_p_x1_x0_b(void);
333: static void dsp_mac_m_x1_x0_b(void);
334: static void dsp_mac_p_y1_y0_a(void);
335: static void dsp_mac_m_y1_y0_a(void);
336: static void dsp_mac_p_y1_y0_b(void);
337: static void dsp_mac_m_y1_y0_b(void);
338: static void dsp_mac_p_x0_y1_a(void);
339: static void dsp_mac_m_x0_y1_a(void);
340: static void dsp_mac_p_x0_y1_b(void);
341: static void dsp_mac_m_x0_y1_b(void);
342: static void dsp_mac_p_y0_x0_a(void);
343: static void dsp_mac_m_y0_x0_a(void);
344: static void dsp_mac_p_y0_x0_b(void);
345: static void dsp_mac_m_y0_x0_b(void);
346: static void dsp_mac_p_x1_y0_a(void);
347: static void dsp_mac_m_x1_y0_a(void);
348: static void dsp_mac_p_x1_y0_b(void);
349: static void dsp_mac_m_x1_y0_b(void);
350: static void dsp_mac_p_y1_x1_a(void);
351: static void dsp_mac_m_y1_x1_a(void);
352: static void dsp_mac_p_y1_x1_b(void);
353: static void dsp_mac_m_y1_x1_b(void);
354: static void dsp_macr_p_x0_x0_a(void);
355: static void dsp_macr_m_x0_x0_a(void);
356: static void dsp_macr_p_x0_x0_b(void);
357: static void dsp_macr_m_x0_x0_b(void);
358: static void dsp_macr_p_y0_y0_a(void);
359: static void dsp_macr_m_y0_y0_a(void);
360: static void dsp_macr_p_y0_y0_b(void);
361: static void dsp_macr_m_y0_y0_b(void);
362: static void dsp_macr_p_x1_x0_a(void);
363: static void dsp_macr_m_x1_x0_a(void);
364: static void dsp_macr_p_x1_x0_b(void);
365: static void dsp_macr_m_x1_x0_b(void);
366: static void dsp_macr_p_y1_y0_a(void);
367: static void dsp_macr_m_y1_y0_a(void);
368: static void dsp_macr_p_y1_y0_b(void);
369: static void dsp_macr_m_y1_y0_b(void);
370: static void dsp_macr_p_x0_y1_a(void);
371: static void dsp_macr_m_x0_y1_a(void);
372: static void dsp_macr_p_x0_y1_b(void);
373: static void dsp_macr_m_x0_y1_b(void);
374: static void dsp_macr_p_y0_x0_a(void);
375: static void dsp_macr_m_y0_x0_a(void);
376: static void dsp_macr_p_y0_x0_b(void);
377: static void dsp_macr_m_y0_x0_b(void);
378: static void dsp_macr_p_x1_y0_a(void);
379: static void dsp_macr_m_x1_y0_a(void);
380: static void dsp_macr_p_x1_y0_b(void);
381: static void dsp_macr_m_x1_y0_b(void);
382: static void dsp_macr_p_y1_x1_a(void);
383: static void dsp_macr_m_y1_x1_a(void);
384: static void dsp_macr_p_y1_x1_b(void);
385: static void dsp_macr_m_y1_x1_b(void);
1.1 root 386: static void dsp_move(void);
1.1.1.6 root 387: static void dsp_mpy_p_x0_x0_a(void);
388: static void dsp_mpy_m_x0_x0_a(void);
389: static void dsp_mpy_p_x0_x0_b(void);
390: static void dsp_mpy_m_x0_x0_b(void);
391: static void dsp_mpy_p_y0_y0_a(void);
392: static void dsp_mpy_m_y0_y0_a(void);
393: static void dsp_mpy_p_y0_y0_b(void);
394: static void dsp_mpy_m_y0_y0_b(void);
395: static void dsp_mpy_p_x1_x0_a(void);
396: static void dsp_mpy_m_x1_x0_a(void);
397: static void dsp_mpy_p_x1_x0_b(void);
398: static void dsp_mpy_m_x1_x0_b(void);
399: static void dsp_mpy_p_y1_y0_a(void);
400: static void dsp_mpy_m_y1_y0_a(void);
401: static void dsp_mpy_p_y1_y0_b(void);
402: static void dsp_mpy_m_y1_y0_b(void);
403: static void dsp_mpy_p_x0_y1_a(void);
404: static void dsp_mpy_m_x0_y1_a(void);
405: static void dsp_mpy_p_x0_y1_b(void);
406: static void dsp_mpy_m_x0_y1_b(void);
407: static void dsp_mpy_p_y0_x0_a(void);
408: static void dsp_mpy_m_y0_x0_a(void);
409: static void dsp_mpy_p_y0_x0_b(void);
410: static void dsp_mpy_m_y0_x0_b(void);
411: static void dsp_mpy_p_x1_y0_a(void);
412: static void dsp_mpy_m_x1_y0_a(void);
413: static void dsp_mpy_p_x1_y0_b(void);
414: static void dsp_mpy_m_x1_y0_b(void);
415: static void dsp_mpy_p_y1_x1_a(void);
416: static void dsp_mpy_m_y1_x1_a(void);
417: static void dsp_mpy_p_y1_x1_b(void);
418: static void dsp_mpy_m_y1_x1_b(void);
419: static void dsp_mpyr_p_x0_x0_a(void);
420: static void dsp_mpyr_m_x0_x0_a(void);
421: static void dsp_mpyr_p_x0_x0_b(void);
422: static void dsp_mpyr_m_x0_x0_b(void);
423: static void dsp_mpyr_p_y0_y0_a(void);
424: static void dsp_mpyr_m_y0_y0_a(void);
425: static void dsp_mpyr_p_y0_y0_b(void);
426: static void dsp_mpyr_m_y0_y0_b(void);
427: static void dsp_mpyr_p_x1_x0_a(void);
428: static void dsp_mpyr_m_x1_x0_a(void);
429: static void dsp_mpyr_p_x1_x0_b(void);
430: static void dsp_mpyr_m_x1_x0_b(void);
431: static void dsp_mpyr_p_y1_y0_a(void);
432: static void dsp_mpyr_m_y1_y0_a(void);
433: static void dsp_mpyr_p_y1_y0_b(void);
434: static void dsp_mpyr_m_y1_y0_b(void);
435: static void dsp_mpyr_p_x0_y1_a(void);
436: static void dsp_mpyr_m_x0_y1_a(void);
437: static void dsp_mpyr_p_x0_y1_b(void);
438: static void dsp_mpyr_m_x0_y1_b(void);
439: static void dsp_mpyr_p_y0_x0_a(void);
440: static void dsp_mpyr_m_y0_x0_a(void);
441: static void dsp_mpyr_p_y0_x0_b(void);
442: static void dsp_mpyr_m_y0_x0_b(void);
443: static void dsp_mpyr_p_x1_y0_a(void);
444: static void dsp_mpyr_m_x1_y0_a(void);
445: static void dsp_mpyr_p_x1_y0_b(void);
446: static void dsp_mpyr_m_x1_y0_b(void);
447: static void dsp_mpyr_p_y1_x1_a(void);
448: static void dsp_mpyr_m_y1_x1_a(void);
449: static void dsp_mpyr_p_y1_x1_b(void);
450: static void dsp_mpyr_m_y1_x1_b(void);
451: static void dsp_neg_a(void);
452: static void dsp_neg_b(void);
453: static void dsp_not_a(void);
454: static void dsp_not_b(void);
455: static void dsp_or_x0_a(void);
456: static void dsp_or_x0_b(void);
457: static void dsp_or_y0_a(void);
458: static void dsp_or_y0_b(void);
459: static void dsp_or_x1_a(void);
460: static void dsp_or_x1_b(void);
461: static void dsp_or_y1_a(void);
462: static void dsp_or_y1_b(void);
463: static void dsp_rnd_a(void);
464: static void dsp_rnd_b(void);
465: static void dsp_rol_a(void);
466: static void dsp_rol_b(void);
467: static void dsp_ror_a(void);
468: static void dsp_ror_b(void);
469: static void dsp_sbc_x_a(void);
470: static void dsp_sbc_x_b(void);
471: static void dsp_sbc_y_a(void);
472: static void dsp_sbc_y_b(void);
473: static void dsp_sub_b_a(void);
474: static void dsp_sub_a_b(void);
475: static void dsp_sub_x_a(void);
476: static void dsp_sub_x_b(void);
477: static void dsp_sub_y_a(void);
478: static void dsp_sub_y_b(void);
479: static void dsp_sub_x0_a(void);
480: static void dsp_sub_x0_b(void);
481: static void dsp_sub_y0_a(void);
482: static void dsp_sub_y0_b(void);
483: static void dsp_sub_x1_a(void);
484: static void dsp_sub_x1_b(void);
485: static void dsp_sub_y1_a(void);
486: static void dsp_sub_y1_b(void);
487: static void dsp_subl_a(void);
488: static void dsp_subl_b(void);
489: static void dsp_subr_a(void);
490: static void dsp_subr_b(void);
491: static void dsp_tfr_b_a(void);
492: static void dsp_tfr_a_b(void);
493: static void dsp_tfr_x0_a(void);
494: static void dsp_tfr_x0_b(void);
495: static void dsp_tfr_y0_a(void);
496: static void dsp_tfr_y0_b(void);
497: static void dsp_tfr_x1_a(void);
498: static void dsp_tfr_x1_b(void);
499: static void dsp_tfr_y1_a(void);
500: static void dsp_tfr_y1_b(void);
501: static void dsp_tst_a(void);
502: static void dsp_tst_b(void);
1.1 root 503:
1.1.1.6 root 504: static const dsp_emul_t opcodes8h[512] = {
1.1.1.4 root 505: /* 0x00 - 0x3f */
506: opcode8h_0, dsp_undefined, dsp_undefined, dsp_undefined, opcode8h_0, dsp_andi, dsp_undefined, dsp_ori,
507: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
508: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
509: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
510: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
511: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
512: dsp_undefined, dsp_undefined, dsp_div, dsp_div, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
513: dsp_norm, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
514:
515: /* 0x40 - 0x7f */
516: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
517: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
518: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
519: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
520: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
521: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
522: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
523: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
524:
525: /* 0x80 - 0xbf */
526: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
527: dsp_lua, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
528: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
529: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
530: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
531: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
532: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
533: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
534:
535: /* 0xc0 - 0xff */
536: dsp_do_aa, dsp_rep_aa, dsp_do_aa, dsp_rep_aa, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
537: dsp_do_ea, dsp_rep_ea, dsp_do_ea, dsp_rep_ea, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
538: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
539: dsp_do_reg, dsp_rep_reg, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
540: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
541: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
542: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
543: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
544:
545: /* 0x100 - 0x13f */
1.1.1.6 root 546: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 547: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 548: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 549: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 550: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 551: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 552: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 553: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
554:
555: /* 0x140 - 0x17f */
556: dsp_bclr_aa, dsp_bset_aa, dsp_bclr_aa, dsp_bset_aa, dsp_jclr_aa, dsp_jset_aa, dsp_jclr_aa, dsp_jset_aa,
557: dsp_bclr_ea, dsp_bset_ea, dsp_bclr_ea, dsp_bset_ea, dsp_jclr_ea, dsp_jset_ea, dsp_jclr_ea, dsp_jset_ea,
558: dsp_bclr_pp, dsp_bset_pp, dsp_bclr_pp, dsp_bset_pp, dsp_jclr_pp, dsp_jset_pp, dsp_jclr_pp, dsp_jset_pp,
559: dsp_jclr_reg, dsp_jset_reg, dsp_bclr_reg, dsp_bset_reg, dsp_jmp_ea, dsp_jcc_ea, dsp_undefined, dsp_undefined,
560: dsp_bchg_aa, dsp_btst_aa, dsp_bchg_aa, dsp_btst_aa, dsp_jsclr_aa, dsp_jsset_aa, dsp_jsclr_aa, dsp_jsset_aa,
561: dsp_bchg_ea, dsp_btst_ea, dsp_bchg_ea, dsp_btst_ea, dsp_jsclr_ea, dsp_jsset_ea, dsp_jsclr_ea, dsp_jsset_ea,
562: dsp_bchg_pp, dsp_btst_pp, dsp_bchg_pp, dsp_btst_pp, dsp_jsclr_pp, dsp_jsset_pp, dsp_jsclr_pp, dsp_jsset_pp,
563: dsp_jsclr_reg, dsp_jsset_reg, dsp_bchg_reg, dsp_btst_reg, dsp_jsr_ea, dsp_jscc_ea, dsp_undefined, dsp_undefined,
564:
565: /* 0x180 - 0x1bf */
566: dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm,
567: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
568: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
569: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
570: dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm,
571: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
572: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
573: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
574:
575: /* 0x1c0 - 0x1ff */
576: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
577: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
578: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
579: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
580: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
581: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
582: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
583: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
1.1 root 584: };
585:
1.1.1.6 root 586: static const dsp_emul_t opcodes_parmove[16] = {
587: dsp_pm_0, dsp_pm_1, dsp_pm_2, dsp_pm_3, dsp_pm_4, dsp_pm_5, dsp_pm_5, dsp_pm_5,
588: dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8
1.1 root 589: };
590:
1.1.1.6 root 591: static const dsp_emul_t opcodes_alu[256] = {
1.1.1.4 root 592: /* 0x00 - 0x3f */
1.1.1.6 root 593: dsp_move , dsp_tfr_b_a, dsp_addr_b_a, dsp_tst_a, dsp_undefined, dsp_cmp_b_a, dsp_subr_a, dsp_cmpm_b_a,
594: dsp_undefined, dsp_tfr_a_b, dsp_addr_a_b, dsp_tst_b, dsp_undefined, dsp_cmp_a_b, dsp_subr_b, dsp_cmpm_a_b,
595: dsp_add_b_a, dsp_rnd_a, dsp_addl_b_a, dsp_clr_a, dsp_sub_b_a, dsp_undefined, dsp_subl_a, dsp_not_a,
596: dsp_add_a_b, dsp_rnd_b, dsp_addl_a_b, dsp_clr_b, dsp_sub_a_b, dsp_undefined, dsp_subl_b, dsp_not_b,
1.1.1.7 ! root 597: dsp_add_x_a, dsp_adc_x_a, dsp_asr_a, dsp_lsr_a, dsp_sub_x_a, dsp_sbc_x_a, dsp_abs_a, dsp_ror_a,
! 598: dsp_add_x_b, dsp_adc_x_b, dsp_asr_b, dsp_lsr_b, dsp_sub_x_b, dsp_sbc_x_b, dsp_abs_b, dsp_ror_b,
! 599: dsp_add_y_a, dsp_adc_y_a, dsp_asl_a, dsp_lsl_a, dsp_sub_y_a, dsp_sbc_y_a, dsp_neg_a, dsp_rol_a,
! 600: dsp_add_y_b, dsp_adc_y_b, dsp_asl_b, dsp_lsl_b, dsp_sub_y_b, dsp_sbc_y_b, dsp_neg_b, dsp_rol_b,
1.1.1.4 root 601:
602: /* 0x40 - 0x7f */
1.1.1.6 root 603: dsp_add_x0_a, dsp_tfr_x0_a, dsp_or_x0_a, dsp_eor_x0_a, dsp_sub_x0_a, dsp_cmp_x0_a, dsp_and_x0_a, dsp_cmpm_x0_a,
604: dsp_add_x0_b, dsp_tfr_x0_b, dsp_or_x0_b, dsp_eor_x0_b, dsp_sub_x0_b, dsp_cmp_x0_b, dsp_and_x0_b, dsp_cmpm_x0_b,
605: dsp_add_y0_a, dsp_tfr_y0_a, dsp_or_y0_a, dsp_eor_y0_a, dsp_sub_y0_a, dsp_cmp_y0_a, dsp_and_y0_a, dsp_cmpm_y0_a,
606: dsp_add_y0_b, dsp_tfr_y0_b, dsp_or_y0_b, dsp_eor_y0_b, dsp_sub_y0_b, dsp_cmp_y0_b, dsp_and_y0_b, dsp_cmpm_y0_b,
607: dsp_add_x1_a, dsp_tfr_x1_a, dsp_or_x1_a, dsp_eor_x1_a, dsp_sub_x1_a, dsp_cmp_x1_a, dsp_and_x1_a, dsp_cmpm_x1_a,
608: dsp_add_x1_b, dsp_tfr_x1_b, dsp_or_x1_b, dsp_eor_x1_b, dsp_sub_x1_b, dsp_cmp_x1_b, dsp_and_x1_b, dsp_cmpm_x1_b,
609: dsp_add_y1_a, dsp_tfr_y1_a, dsp_or_y1_a, dsp_eor_y1_a, dsp_sub_y1_a, dsp_cmp_y1_a, dsp_and_y1_a, dsp_cmpm_y1_a,
610: dsp_add_y1_b, dsp_tfr_y1_b, dsp_or_y1_b, dsp_eor_y1_b, dsp_sub_y1_b, dsp_cmp_y1_b, dsp_and_y1_b, dsp_cmpm_y1_b,
1.1.1.4 root 611:
612: /* 0x80 - 0xbf */
1.1.1.6 root 613: dsp_mpy_p_x0_x0_a, dsp_mpyr_p_x0_x0_a, dsp_mac_p_x0_x0_a, dsp_macr_p_x0_x0_a, dsp_mpy_m_x0_x0_a, dsp_mpyr_m_x0_x0_a, dsp_mac_m_x0_x0_a, dsp_macr_m_x0_x0_a,
614: dsp_mpy_p_x0_x0_b, dsp_mpyr_p_x0_x0_b, dsp_mac_p_x0_x0_b, dsp_macr_p_x0_x0_b, dsp_mpy_m_x0_x0_b, dsp_mpyr_m_x0_x0_b, dsp_mac_m_x0_x0_b, dsp_macr_m_x0_x0_b,
615: dsp_mpy_p_y0_y0_a, dsp_mpyr_p_y0_y0_a, dsp_mac_p_y0_y0_a, dsp_macr_p_y0_y0_a, dsp_mpy_m_y0_y0_a, dsp_mpyr_m_y0_y0_a, dsp_mac_m_y0_y0_a, dsp_macr_m_y0_y0_a,
616: dsp_mpy_p_y0_y0_b, dsp_mpyr_p_y0_y0_b, dsp_mac_p_y0_y0_b, dsp_macr_p_y0_y0_b, dsp_mpy_m_y0_y0_b, dsp_mpyr_m_y0_y0_b, dsp_mac_m_y0_y0_b, dsp_macr_m_y0_y0_b,
617: dsp_mpy_p_x1_x0_a, dsp_mpyr_p_x1_x0_a, dsp_mac_p_x1_x0_a, dsp_macr_p_x1_x0_a, dsp_mpy_m_x1_x0_a, dsp_mpyr_m_x1_x0_a, dsp_mac_m_x1_x0_a, dsp_macr_m_x1_x0_a,
618: dsp_mpy_p_x1_x0_b, dsp_mpyr_p_x1_x0_b, dsp_mac_p_x1_x0_b, dsp_macr_p_x1_x0_b, dsp_mpy_m_x1_x0_b, dsp_mpyr_m_x1_x0_b, dsp_mac_m_x1_x0_b, dsp_macr_m_x1_x0_b,
619: dsp_mpy_p_y1_y0_a, dsp_mpyr_p_y1_y0_a, dsp_mac_p_y1_y0_a, dsp_macr_p_y1_y0_a, dsp_mpy_m_y1_y0_a, dsp_mpyr_m_y1_y0_a, dsp_mac_m_y1_y0_a, dsp_macr_m_y1_y0_a,
620: dsp_mpy_p_y1_y0_b, dsp_mpyr_p_y1_y0_b, dsp_mac_p_y1_y0_b, dsp_macr_p_y1_y0_b, dsp_mpy_m_y1_y0_b, dsp_mpyr_m_y1_y0_b, dsp_mac_m_y1_y0_b, dsp_macr_m_y1_y0_b,
621:
622: /* 0xc0_m_ 0xff */
623: dsp_mpy_p_x0_y1_a, dsp_mpyr_p_x0_y1_a, dsp_mac_p_x0_y1_a, dsp_macr_p_x0_y1_a, dsp_mpy_m_x0_y1_a, dsp_mpyr_m_x0_y1_a, dsp_mac_m_x0_y1_a, dsp_macr_m_x0_y1_a,
624: dsp_mpy_p_x0_y1_b, dsp_mpyr_p_x0_y1_b, dsp_mac_p_x0_y1_b, dsp_macr_p_x0_y1_b, dsp_mpy_m_x0_y1_b, dsp_mpyr_m_x0_y1_b, dsp_mac_m_x0_y1_b, dsp_macr_m_x0_y1_b,
625: dsp_mpy_p_y0_x0_a, dsp_mpyr_p_y0_x0_a, dsp_mac_p_y0_x0_a, dsp_macr_p_y0_x0_a, dsp_mpy_m_y0_x0_a, dsp_mpyr_m_y0_x0_a, dsp_mac_m_y0_x0_a, dsp_macr_m_y0_x0_a,
626: dsp_mpy_p_y0_x0_b, dsp_mpyr_p_y0_x0_b, dsp_mac_p_y0_x0_b, dsp_macr_p_y0_x0_b, dsp_mpy_m_y0_x0_b, dsp_mpyr_m_y0_x0_b, dsp_mac_m_y0_x0_b, dsp_macr_m_y0_x0_b,
627: dsp_mpy_p_x1_y0_a, dsp_mpyr_p_x1_y0_a, dsp_mac_p_x1_y0_a, dsp_macr_p_x1_y0_a, dsp_mpy_m_x1_y0_a, dsp_mpyr_m_x1_y0_a, dsp_mac_m_x1_y0_a, dsp_macr_m_x1_y0_a,
628: dsp_mpy_p_x1_y0_b, dsp_mpyr_p_x1_y0_b, dsp_mac_p_x1_y0_b, dsp_macr_p_x1_y0_b, dsp_mpy_m_x1_y0_b, dsp_mpyr_m_x1_y0_b, dsp_mac_m_x1_y0_b, dsp_macr_m_x1_y0_b,
629: dsp_mpy_p_y1_x1_a, dsp_mpyr_p_y1_x1_a, dsp_mac_p_y1_x1_a, dsp_macr_p_y1_x1_a, dsp_mpy_m_y1_x1_a, dsp_mpyr_m_y1_x1_a, dsp_mac_m_y1_x1_a, dsp_macr_m_y1_x1_a,
630: dsp_mpy_p_y1_x1_b, dsp_mpyr_p_y1_x1_b, dsp_mac_p_y1_x1_b, dsp_macr_p_y1_x1_b, dsp_mpy_m_y1_x1_b, dsp_mpyr_m_y1_x1_b, dsp_mac_m_y1_x1_b, dsp_macr_m_y1_x1_b
1.1 root 631: };
632:
1.1.1.6 root 633: static const int registers_tcc[16][2] = {
1.1 root 634: {DSP_REG_B,DSP_REG_A},
635: {DSP_REG_A,DSP_REG_B},
636: {DSP_REG_NULL,DSP_REG_NULL},
637: {DSP_REG_NULL,DSP_REG_NULL},
638:
639: {DSP_REG_NULL,DSP_REG_NULL},
640: {DSP_REG_NULL,DSP_REG_NULL},
641: {DSP_REG_NULL,DSP_REG_NULL},
642: {DSP_REG_NULL,DSP_REG_NULL},
643:
644: {DSP_REG_X0,DSP_REG_A},
645: {DSP_REG_X0,DSP_REG_B},
646: {DSP_REG_Y0,DSP_REG_A},
647: {DSP_REG_Y0,DSP_REG_B},
1.1.1.2 root 648:
649: {DSP_REG_X1,DSP_REG_A},
650: {DSP_REG_X1,DSP_REG_B},
1.1 root 651: {DSP_REG_Y1,DSP_REG_A},
652: {DSP_REG_Y1,DSP_REG_B}
653: };
654:
1.1.1.6 root 655: static const int registers_mask[64] = {
1.1 root 656: 0, 0, 0, 0,
657: 24, 24, 24, 24,
658: 24, 24, 8, 8,
659: 24, 24, 24, 24,
660:
661: 16, 16, 16, 16,
662: 16, 16, 16, 16,
663: 16, 16, 16, 16,
664: 16, 16, 16, 16,
665:
666: 16, 16, 16, 16,
667: 16, 16, 16, 16,
668: 0, 0, 0, 0,
669: 0, 0, 0, 0,
670:
671: 0, 0, 0, 0,
672: 0, 0, 0, 0,
673: 0, 16, 8, 6,
1.1.1.4 root 674: 16, 16, 16, 16
675: };
676:
1.1.1.6 root 677: static const dsp_interrupt_t dsp_interrupt[12] = {
1.1.1.5 root 678: {DSP_INTER_RESET , 0x00, 0, "Reset"},
679: {DSP_INTER_ILLEGAL , 0x3e, 0, "Illegal"},
680: {DSP_INTER_STACK_ERROR , 0x02, 0, "Stack Error"},
681: {DSP_INTER_TRACE , 0x04, 0, "Trace"},
682: {DSP_INTER_SWI , 0x06, 0, "Swi"},
683: {DSP_INTER_HOST_COMMAND , 0xff, 1, "Host Command"},
684: {DSP_INTER_HOST_RCV_DATA, 0x20, 1, "Host receive"},
685: {DSP_INTER_HOST_TRX_DATA, 0x22, 1, "Host transmit"},
686: {DSP_INTER_SSI_RCV_DATA_E, 0x0e, 2, "SSI receive with exception"},
687: {DSP_INTER_SSI_RCV_DATA , 0x0c, 2, "SSI receive"},
688: {DSP_INTER_SSI_TRX_DATA_E, 0x12, 2, "SSI transmit with exception"},
689: {DSP_INTER_SSI_TRX_DATA , 0x10, 2, "SSI tramsmit"}
1.1.1.4 root 690: };
691:
1.1 root 692:
693: /**********************************
694: * Emulator kernel
695: **********************************/
696:
1.1.1.6 root 697: void dsp56k_init_cpu(void)
1.1 root 698: {
1.1.1.6 root 699: dsp56k_disasm_init();
700: isDsp_in_disasm_mode = false;
1.1.1.2 root 701: start_time = SDL_GetTicks();
702: num_inst = 0;
1.1 root 703: }
704:
1.1.1.6 root 705: /**
706: * Execute one instruction in trace mode at a given PC address.
707: * */
708: Uint32 dsp56k_execute_one_disasm_instruction(Uint32 pc)
709: {
710: dsp_core_t *ptr1, *ptr2;
711: static dsp_core_t dsp_core_save;
712: Uint32 instruction_length;
713:
714: ptr1 = &dsp_core;
715: ptr2 = &dsp_core_save;
716:
717: /* Set DSP in disasm mode */
718: isDsp_in_disasm_mode = true;
719:
720: /* Save DSP context before executing instruction */
721: memcpy(ptr2, ptr1, sizeof(dsp_core));
722:
723: /* execute and disasm instruction */
724: dsp_core.pc = pc;
725:
726: /* Disasm instruction */
727: instruction_length = dsp56k_disasm(DSP_DISASM_MODE) - 1;
728:
729: /* Execute instruction at address given in parameter to get the number of cycles it takes */
730: dsp56k_execute_instruction();
731:
732: fprintf(stderr, "%s", dsp56k_getInstructionText());
733:
734: /* Restore DSP context after executing instruction */
735: memcpy(ptr1, ptr2, sizeof(dsp_core));
736:
737: /* Unset DSP in disasm mode */
738: isDsp_in_disasm_mode = false;
739:
740: return instruction_length;
741: }
742:
1.1.1.4 root 743: void dsp56k_execute_instruction(void)
1.1 root 744: {
1.1.1.2 root 745: Uint32 value;
1.1.1.6 root 746: Uint32 disasm_return = 0;
1.1.1.5 root 747: disasm_memory_ptr = 0;
748:
1.1.1.7 ! root 749: /* Initialise the number of access to the external memory for this instruction */
! 750: nb_access_to_extMemory = 0;
! 751:
1.1 root 752: /* Decode and execute current instruction */
1.1.1.6 root 753: cur_inst = read_memory_p(dsp_core.pc);
1.1.1.4 root 754:
1.1.1.7 ! root 755: /* Initialize instruction size and cycle counter */
! 756: cur_inst_len = 1;
1.1.1.6 root 757: dsp_core.instr_cycle = 2;
1.1 root 758:
1.1.1.6 root 759: /* Disasm current instruction ? (trace mode only) */
760: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
761: /* Call dsp56k_disasm only when DSP is called in trace mode */
762: if (isDsp_in_disasm_mode == false) {
763: disasm_return = dsp56k_disasm(DSP_TRACE_MODE);
764:
765: if (disasm_return != 0 && LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG)) {
766: /* DSP regs trace enabled only if DSP DISASM is enabled */
767: dsp56k_disasm_reg_save();
768: }
769: }
770: }
771:
1.1.1.4 root 772: if (cur_inst < 0x100000) {
773: value = (cur_inst >> 11) & (BITMASK(6) << 3);
774: value += (cur_inst >> 5) & BITMASK(3);
1.1 root 775: opcodes8h[value]();
776: } else {
1.1.1.6 root 777: /* Do parallel move read */
778: opcodes_parmove[(cur_inst>>20) & BITMASK(4)]();
779: }
780:
1.1.1.7 ! root 781: /* Add the waitstate due to external memory access */
! 782: if (nb_access_to_extMemory > 1)
! 783: dsp_core.instr_cycle += nb_access_to_extMemory - 1;
! 784:
1.1.1.6 root 785: /* Disasm current instruction ? (trace mode only) */
786: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
787: /* Display only when DSP is called in trace mode */
788: if (isDsp_in_disasm_mode == false) {
789: if (disasm_return != 0) {
790: fprintf(stderr, "%s", dsp56k_getInstructionText());
791:
792: /* DSP regs trace enabled only if DSP DISASM is enabled */
793: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG))
794: dsp56k_disasm_reg_compare();
795:
796: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM)) {
797: /* 1 memory change to display ? */
798: if (disasm_memory_ptr == 1)
799: fprintf(stderr, "\t%s\n", str_disasm_memory[0]);
800: /* 2 memory changes to display ? */
801: else if (disasm_memory_ptr == 2) {
802: fprintf(stderr, "\t%s\n", str_disasm_memory[0]);
803: fprintf(stderr, "\t%s\n", str_disasm_memory[1]);
804: }
805: }
806: }
807: }
1.1 root 808: }
809:
1.1.1.4 root 810: /* Process the PC */
811: dsp_postexecute_update_pc();
1.1 root 812:
1.1.1.4 root 813: /* Process Interrupts */
1.1 root 814: dsp_postexecute_interrupts();
815:
1.1.1.4 root 816: #if DSP_COUNT_IPS
817: ++num_inst;
818: if ((num_inst & 63) == 0) {
819: /* Evaluate time after <N> instructions have been executed to avoid asking too frequently */
820: Uint32 cur_time = SDL_GetTicks();
821: if (cur_time-start_time>1000) {
822: fprintf(stderr, "Dsp: %d i/s\n", (num_inst*1000)/(cur_time-start_time));
823: start_time=cur_time;
824: num_inst=0;
825: }
826: }
827: #endif
1.1 root 828: }
829:
830: /**********************************
831: * Update the PC
832: **********************************/
833:
834: static void dsp_postexecute_update_pc(void)
835: {
836: /* When running a REP, PC must stay on the current instruction */
1.1.1.6 root 837: if (dsp_core.loop_rep) {
1.1 root 838: /* Is PC on the instruction to repeat ? */
1.1.1.6 root 839: if (dsp_core.pc_on_rep==0) {
840: --dsp_core.registers[DSP_REG_LC];
841: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1 root 842:
1.1.1.6 root 843: if (dsp_core.registers[DSP_REG_LC] > 0) {
1.1.1.7 ! root 844: cur_inst_len = 0; /* Stay on this instruction */
1.1 root 845: } else {
1.1.1.6 root 846: dsp_core.loop_rep = 0;
847: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[DSP_REG_LCSAVE];
1.1 root 848: }
849: } else {
850: /* Init LC at right value */
1.1.1.6 root 851: if (dsp_core.registers[DSP_REG_LC] == 0) {
852: dsp_core.registers[DSP_REG_LC] = 0x010000;
1.1 root 853: }
1.1.1.6 root 854: dsp_core.pc_on_rep = 0;
1.1 root 855: }
856: }
857:
858: /* Normal execution, go to next instruction */
1.1.1.6 root 859: dsp_core.pc += cur_inst_len;
1.1 root 860:
861: /* When running a DO loop, we test the end of loop with the */
862: /* updated PC, pointing to last instruction of the loop */
1.1.1.6 root 863: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_LF)) {
1.1 root 864:
865: /* Did we execute the last instruction in loop ? */
1.1.1.7 ! root 866: if (dsp_core.pc == dsp_core.registers[DSP_REG_LA] + 1) {
1.1.1.6 root 867: --dsp_core.registers[DSP_REG_LC];
868: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1 root 869:
1.1.1.7 ! root 870: if (dsp_core.registers[DSP_REG_LC] == 0) {
1.1 root 871: /* end of loop */
1.1.1.4 root 872: Uint32 saved_pc, saved_sr;
873:
874: dsp_stack_pop(&saved_pc, &saved_sr);
1.1.1.6 root 875: dsp_core.registers[DSP_REG_SR] &= 0x7f;
876: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
877: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
1.1 root 878: } else {
879: /* Loop one more time */
1.1.1.6 root 880: dsp_core.pc = dsp_core.registers[DSP_REG_SSH];
1.1 root 881: }
882: }
883: }
884: }
885:
886: /**********************************
887: * Interrupts
888: **********************************/
889:
1.1.1.5 root 890: /* Post a new interrupt to the interrupt table */
891: void dsp_add_interrupt(Uint16 inter)
892: {
893: /* detect if this interrupt is used or not */
1.1.1.6 root 894: if (dsp_core.interrupt_ipl[inter] == -1)
1.1.1.5 root 895: return;
896:
897: /* add this interrupt to the pending interrupts table */
1.1.1.6 root 898: if (dsp_core.interrupt_isPending[inter] == 0) {
899: dsp_core.interrupt_isPending[inter] = 1;
900: dsp_core.interrupt_counter ++;
1.1.1.5 root 901: }
902: }
903:
904: static void dsp_setInterruptIPL(Uint32 value)
905: {
906: Uint32 ipl_ssi, ipl_hi, i;
907:
908: ipl_ssi = ((value >> 12) & 3) - 1;
909: ipl_hi = ((value >> 10) & 3) - 1;
910:
911: /* set IPL_HI */
1.1.1.7 ! root 912: for (i=5; i<8; i++) {
1.1.1.6 root 913: dsp_core.interrupt_ipl[i] = ipl_hi;
1.1.1.5 root 914: }
915:
916: /* set IPL_SSI */
1.1.1.7 ! root 917: for (i=8; i<12; i++) {
1.1.1.6 root 918: dsp_core.interrupt_ipl[i] = ipl_ssi;
1.1.1.5 root 919: }
920: }
921:
1.1 root 922: static void dsp_postexecute_interrupts(void)
923: {
1.1.1.5 root 924: Uint32 index, instr, i;
925: Sint32 ipl_to_raise, ipl_sr;
1.1.1.4 root 926:
927: /* REP is not interruptible */
1.1.1.6 root 928: if (dsp_core.loop_rep) {
1.1.1.4 root 929: return;
930: }
931:
932: /* A fast interrupt can not be interrupted. */
1.1.1.6 root 933: if (dsp_core.interrupt_state == DSP_INTERRUPT_DISABLED) {
1.1.1.5 root 934:
1.1.1.6 root 935: switch (dsp_core.interrupt_pipeline_count) {
1.1.1.5 root 936: case 5:
1.1.1.6 root 937: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 938: return;
939: case 4:
940: /* Prefetch interrupt instruction 1 */
1.1.1.6 root 941: dsp_core.interrupt_save_pc = dsp_core.pc;
942: dsp_core.pc = dsp_core.interrupt_instr_fetch;
1.1.1.5 root 943:
944: /* is it a LONG interrupt ? */
1.1.1.6 root 945: instr = read_memory_p(dsp_core.interrupt_instr_fetch);
1.1.1.5 root 946: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1.1.1.6 root 947: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
948: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
949: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1.1.1.5 root 950: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
951: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1.1.1.6 root 952: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1.1.1.5 root 953: }
1.1.1.6 root 954: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 955: return;
956: case 3:
957: /* Prefetch interrupt instruction 2 */
1.1.1.6 root 958: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+1) {
959: instr = read_memory_p(dsp_core.pc);
1.1.1.5 root 960: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1.1.1.6 root 961: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
962: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
963: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1.1.1.5 root 964: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
965: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1.1.1.6 root 966: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1.1.1.5 root 967: }
968: }
1.1.1.6 root 969: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 970: return;
971: case 2:
972: /* 1 instruction executed after interrupt */
973: /* before re enable interrupts */
974: /* Was it a FAST interrupt ? */
1.1.1.6 root 975: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+2) {
976: dsp_core.pc = dsp_core.interrupt_save_pc;
1.1.1.5 root 977: }
1.1.1.6 root 978: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 979: return;
980: case 1:
981: /* Last instruction executed after interrupt */
982: /* before re enable interrupts */
1.1.1.6 root 983: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 984: return;
985: case 0:
986: /* Re enable interrupts */
1.1.1.6 root 987: /* All 6 instruction are done, Interrupts can be enabled again */
988: dsp_core.interrupt_save_pc = -1;
989: dsp_core.interrupt_instr_fetch = -1;
990: dsp_core.interrupt_state = DSP_INTERRUPT_NONE;
991: break;
1.1.1.4 root 992: }
993: }
1.1 root 994:
1.1.1.4 root 995: /* Trace Interrupt ? */
1.1.1.6 root 996: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_T)) {
1.1.1.5 root 997: dsp_add_interrupt(DSP_INTER_TRACE);
1.1.1.4 root 998: }
999:
1000: /* No interrupt to execute */
1.1.1.6 root 1001: if (dsp_core.interrupt_counter == 0) {
1.1.1.4 root 1002: return;
1.1 root 1003: }
1004:
1.1.1.5 root 1005: /* search for an interrupt */
1.1.1.6 root 1006: ipl_sr = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_I0) & BITMASK(2);
1.1.1.5 root 1007: index = 0xffff;
1008: ipl_to_raise = -1;
1009:
1010: /* Arbitrate between all pending interrupts */
1011: for (i=0; i<12; i++) {
1.1.1.6 root 1012: if (dsp_core.interrupt_isPending[i] == 1) {
1.1.1.5 root 1013:
1014: /* level 3 interrupt ? */
1.1.1.6 root 1015: if (dsp_core.interrupt_ipl[i] == 3) {
1.1.1.5 root 1016: index = i;
1017: break;
1018: }
1.1 root 1019:
1.1.1.5 root 1020: /* level 0, 1 ,2 interrupt ? */
1021: /* if interrupt is masked in SR, don't process it */
1.1.1.6 root 1022: if (dsp_core.interrupt_ipl[i] < ipl_sr)
1.1.1.5 root 1023: continue;
1.1 root 1024:
1.1.1.5 root 1025: /* if interrupt is lower or equal than current arbitrated interrupt */
1.1.1.6 root 1026: if (dsp_core.interrupt_ipl[i] <= ipl_to_raise)
1.1.1.5 root 1027: continue;
1028:
1029: /* save current arbitrated interrupt */
1030: index = i;
1.1.1.6 root 1031: ipl_to_raise = dsp_core.interrupt_ipl[i];
1.1 root 1032: }
1033: }
1.1.1.4 root 1034:
1.1.1.5 root 1035: /* If there's no interrupt to process, return */
1036: if (index == 0xffff) {
1.1.1.4 root 1037: return;
1038: }
1039:
1.1.1.5 root 1040: /* remove this interrupt from the pending interrupts table */
1.1.1.6 root 1041: dsp_core.interrupt_isPending[index] = 0;
1042: dsp_core.interrupt_counter --;
1.1.1.5 root 1043:
1044: /* process arbritrated interrupt */
1.1.1.6 root 1045: ipl_to_raise = dsp_core.interrupt_ipl[index] + 1;
1.1.1.5 root 1046: if (ipl_to_raise > 3) {
1047: ipl_to_raise = 3;
1048: }
1049:
1.1.1.6 root 1050: dsp_core.interrupt_instr_fetch = dsp_interrupt[index].vectorAddr;
1051: dsp_core.interrupt_pipeline_count = 5;
1052: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1053: dsp_core.interrupt_IplToRaise = ipl_to_raise;
1054:
1055: LOG_TRACE(TRACE_DSP_INTERRUPT, "Dsp interrupt: %s\n", dsp_interrupt[index].name);
1.1.1.5 root 1056:
1057: /* SSI receive data with exception ? */
1.1.1.6 root 1058: if (dsp_core.interrupt_instr_fetch == 0xe) {
1059: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_ROE);
1.1.1.4 root 1060: }
1061:
1.1.1.5 root 1062: /* SSI transmit data with exception ? */
1.1.1.6 root 1063: else if (dsp_core.interrupt_instr_fetch == 0x12) {
1064: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_TUE);
1.1.1.4 root 1065: }
1066:
1067: /* host command ? */
1.1.1.6 root 1068: else if (dsp_core.interrupt_instr_fetch == 0xff) {
1.1.1.4 root 1069: /* Clear HC and HCP interrupt */
1.1.1.6 root 1070: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] &= 0xff - (1<<DSP_HOST_HSR_HCP);
1071: dsp_core.hostport[CPU_HOST_CVR] &= 0xff - (1<<CPU_HOST_CVR_HC);
1.1.1.4 root 1072:
1.1.1.6 root 1073: dsp_core.interrupt_instr_fetch = dsp_core.hostport[CPU_HOST_CVR] & BITMASK(5);
1074: dsp_core.interrupt_instr_fetch *= 2;
1.1.1.4 root 1075: }
1.1 root 1076: }
1077:
1078: /**********************************
1079: * Set/clear ccr bits
1080: **********************************/
1081:
1082: /* reg0 has bits 55..48 */
1083: /* reg1 has bits 47..24 */
1084: /* reg2 has bits 23..0 */
1085:
1.1.1.6 root 1086: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2)
1087: {
1088: Uint32 scaling, value_e, value_u;
1.1.1.4 root 1089:
1.1.1.6 root 1090: /* Initialize SR register */
1091: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E) | (1<<DSP_SR_U) | (1<<DSP_SR_N) | (1<<DSP_SR_Z));
1.1.1.4 root 1092:
1.1.1.6 root 1093: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
1.1 root 1094: switch(scaling) {
1095: case 0:
1.1.1.6 root 1096: /* Extension Bit (E) */
1097: value_e = (reg0<<1) + (reg1>>23);
1098: if ((value_e != 0) && (value_e != BITMASK(9)))
1099: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1100:
1101: /* Unnormalized bit (U) */
1102: if ((reg1 & 0xc00000) == 0 || (reg1 & 0xc00000) == 0xc00000)
1103: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1104: break;
1105: case 1:
1.1.1.6 root 1106: /* Extension Bit (E) */
1107: if ((reg0 != 0) && (reg0 != BITMASK(8)))
1108: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1109:
1110: /* Unnormalized bit (U) */
1111: value_u = ((reg0<<1) + (reg1>>23)) & 3;
1112: if (value_u == 0 || value_u == 3)
1113: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1114: break;
1115: case 2:
1.1.1.6 root 1116: /* Extension Bit (E) */
1117: value_e = (reg0<<2) + (reg1>>22);
1118: if ((value_e != 0) && (value_e != BITMASK(10)))
1119: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1120:
1121: /* Unnormalized bit (U) */
1122: if ((reg1 & 0x600000) == 0 || (reg1 & 0x600000) == 0x600000)
1123: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1124: break;
1125: default:
1126: return;
1127: break;
1128: }
1129:
1.1.1.6 root 1130: /* Zero Flag (Z) */
1131: if ((reg1 == 0) && (reg2 == 0) && (reg0 == 0))
1132: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_Z;
1.1.1.4 root 1133:
1.1.1.6 root 1134: /* Negative Flag (N) */
1135: dsp_core.registers[DSP_REG_SR] |= (reg0>>4) & 0x8;
1.1 root 1136: }
1137:
1138: /**********************************
1139: * Read/Write memory functions
1140: **********************************/
1141:
1.1.1.2 root 1142: static Uint32 read_memory_disasm(int space, Uint16 address)
1.1 root 1143: {
1.1.1.4 root 1144: /* Internal RAM ? */
1145: if (address<0x100) {
1.1.1.6 root 1146: return dsp_core.ramint[space][address] & BITMASK(24);
1.1.1.4 root 1147: }
1.1 root 1148:
1.1.1.4 root 1149: if (space==DSP_SPACE_P) {
1150: return read_memory_p(address);
1.1 root 1151: }
1152:
1.1.1.4 root 1153: /* Internal ROM? */
1.1.1.6 root 1154: if ((dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) &&
1.1.1.4 root 1155: (address<0x200)) {
1.1.1.6 root 1156: return dsp_core.rom[space][address] & BITMASK(24);
1.1.1.4 root 1157: }
1158:
1159: /* Peripheral address ? */
1160: if (address >= 0xffc0) {
1.1.1.6 root 1161: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_HOST_HTX)) {
1162: return dsp_core.dsp_host_htx;
1.1.1.4 root 1163: }
1164: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_SSI_TX)) {
1.1.1.6 root 1165: return dsp_core.ssi.transmit_value;
1.1.1.4 root 1166: }
1.1.1.6 root 1167: return dsp_core.periph[space][address-0xffc0] & BITMASK(24);
1.1.1.4 root 1168: }
1169:
1170: /* Falcon: External RAM, map X to upper 16K of matching space in Y,P */
1171: address &= (DSP_RAMSIZE>>1) - 1;
1172: if (space == DSP_SPACE_X) {
1173: address += DSP_RAMSIZE>>1;
1174: }
1175:
1176: /* Falcon: External RAM, finally map X,Y to P */
1.1.1.6 root 1177: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1.1 root 1178: }
1179:
1.1.1.4 root 1180: static inline Uint32 read_memory_p(Uint16 address)
1181: {
1182: /* Internal RAM ? */
1.1.1.7 ! root 1183: if (address < 0x200) {
1.1.1.6 root 1184: return dsp_core.ramint[DSP_SPACE_P][address] & BITMASK(24);
1.1.1.4 root 1185: }
1186:
1.1.1.7 ! root 1187: /* Access to the external memory */
! 1188: nb_access_to_extMemory ++;
! 1189:
1.1.1.4 root 1190: /* External RAM, mask address to available ram size */
1.1.1.6 root 1191: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1.1.1.4 root 1192: }
1193:
1.1.1.2 root 1194: static Uint32 read_memory(int space, Uint16 address)
1.1 root 1195: {
1.1.1.4 root 1196: Uint32 value;
1.1 root 1197:
1.1.1.4 root 1198: /* Internal RAM ? */
1199: if (address < 0x100) {
1.1.1.6 root 1200: return dsp_core.ramint[space][address] & BITMASK(24);
1.1.1.4 root 1201: }
1.1 root 1202:
1.1.1.4 root 1203: if (space == DSP_SPACE_P) {
1204: return read_memory_p(address);
1205: }
1206:
1207: /* Internal ROM ? */
1208: if (address < 0x200) {
1.1.1.6 root 1209: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1210: return dsp_core.rom[space][address] & BITMASK(24);
1.1.1.4 root 1211: }
1212: }
1213:
1214: /* Peripheral address ? */
1215: if (address >= 0xffc0) {
1.1.1.6 root 1216: value = dsp_core.periph[space][address-0xffc0] & BITMASK(24);
1.1.1.4 root 1217: if (space == DSP_SPACE_X) {
1218: if (address == 0xffc0+DSP_HOST_HRX) {
1.1.1.6 root 1219: value = dsp_core.dsp_host_rtx;
1220: dsp_core_hostport_dspread();
1.1.1.4 root 1221: }
1222: else if (address == 0xffc0+DSP_SSI_RX) {
1.1.1.6 root 1223: value = dsp_core_ssi_readRX();
1.1 root 1224: }
1.1.1.4 root 1225: }
1226: return value;
1.1 root 1227: }
1228:
1.1.1.7 ! root 1229: /* Access to the external memory */
! 1230: nb_access_to_extMemory ++;
1.1.1.4 root 1231:
1232: /* Falcon: External RAM, map X to upper 16K of matching space in Y,P */
1233: address &= (DSP_RAMSIZE>>1) - 1;
1234:
1235: if (space == DSP_SPACE_X) {
1236: address += DSP_RAMSIZE>>1;
1237: }
1238:
1239: /* Falcon: External RAM, finally map X,Y to P */
1.1.1.6 root 1240: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1241: }
1242:
1243: static inline void write_memory(int space, Uint16 address, Uint32 value)
1244: {
1.1.1.7 ! root 1245: if (unlikely(LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM)))
1.1.1.6 root 1246: write_memory_disasm(space, address, value);
1247: else
1248: write_memory_raw(space, address, value);
1.1 root 1249: }
1250:
1.1.1.4 root 1251: static void write_memory_raw(int space, Uint16 address, Uint32 value)
1.1 root 1252: {
1253: value &= BITMASK(24);
1254:
1.1.1.4 root 1255: /* Peripheral address ? */
1256: if (address >= 0xffc0) {
1257: if (space == DSP_SPACE_X) {
1258: switch(address-0xffc0) {
1259: case DSP_HOST_HTX:
1.1.1.6 root 1260: dsp_core.dsp_host_htx = value;
1261: dsp_core_hostport_dspwrite();
1.1.1.4 root 1262: break;
1263: case DSP_HOST_HCR:
1.1.1.6 root 1264: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] = value;
1.1.1.4 root 1265: /* Set HF3 and HF2 accordingly on the host side */
1.1.1.6 root 1266: dsp_core.hostport[CPU_HOST_ISR] &=
1.1.1.4 root 1267: BITMASK(8)-((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1.1.1.6 root 1268: dsp_core.hostport[CPU_HOST_ISR] |=
1269: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] & ((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1.1.1.4 root 1270: break;
1271: case DSP_HOST_HSR:
1272: /* Read only */
1273: break;
1274: case DSP_SSI_CRA:
1275: case DSP_SSI_CRB:
1.1.1.6 root 1276: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1277: dsp_core_ssi_configure(address-0xffc0, value);
1.1.1.4 root 1278: break;
1279: case DSP_SSI_TSR:
1.1.1.6 root 1280: dsp_core_ssi_writeTSR();
1.1.1.4 root 1281: break;
1282: case DSP_SSI_TX:
1.1.1.6 root 1283: dsp_core_ssi_writeTX(value);
1.1.1.4 root 1284: break;
1.1.1.5 root 1285: case DSP_IPR:
1.1.1.6 root 1286: dsp_core.periph[DSP_SPACE_X][DSP_IPR] = value;
1.1.1.5 root 1287: dsp_setInterruptIPL(value);
1288: break;
1289: case DSP_PCD:
1.1.1.6 root 1290: dsp_core.periph[DSP_SPACE_X][DSP_PCD] = value;
1291: dsp_core_setPortCDataRegister(value);
1.1.1.5 root 1292: break;
1.1.1.4 root 1293: default:
1.1.1.6 root 1294: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1.1.1.4 root 1295: break;
1.1 root 1296: }
1.1.1.4 root 1297: return;
1298: }
1299: else if (space == DSP_SPACE_Y) {
1.1.1.6 root 1300: dsp_core.periph[DSP_SPACE_Y][address-0xffc0] = value;
1.1.1.4 root 1301: return;
1302: }
1303: }
1304:
1305: /* Internal RAM ? */
1306: if (address < 0x100) {
1.1.1.6 root 1307: dsp_core.ramint[space][address] = value;
1.1.1.4 root 1308: return;
1309: }
1.1.1.2 root 1310:
1.1.1.4 root 1311: /* Internal ROM ? */
1312: if (address < 0x200) {
1313: if (space != DSP_SPACE_P) {
1.1.1.6 root 1314: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1.1.1.2 root 1315: /* Can not write to ROM space */
1.1 root 1316: return;
1317: }
1.1.1.4 root 1318: }
1319: else {
1320: /* Space P RAM */
1.1.1.6 root 1321: dsp_core.ramint[DSP_SPACE_P][address] = value;
1.1.1.4 root 1322: return;
1323: }
1.1 root 1324: }
1325:
1.1.1.7 ! root 1326: /* Access to the external memory */
! 1327: nb_access_to_extMemory ++;
1.1.1.4 root 1328:
1329: /* Falcon: External RAM, map X to upper 16K of matching space in Y,P */
1330: if (space != DSP_SPACE_P) {
1331: address &= (DSP_RAMSIZE>>1) - 1;
1332: }
1333:
1334: if (space == DSP_SPACE_X) {
1335: address += DSP_RAMSIZE>>1;
1336: }
1337:
1338: /* Falcon: External RAM, map X,Y to P */
1.1.1.6 root 1339: dsp_core.ramext[address & (DSP_RAMSIZE-1)] = value;
1.1.1.2 root 1340: }
1341:
1.1.1.4 root 1342: static void write_memory_disasm(int space, Uint16 address, Uint32 value)
1.1.1.2 root 1343: {
1.1.1.4 root 1344: Uint32 oldvalue, curvalue;
1345: Uint8 space_c = 'p';
1346:
1.1.1.2 root 1347: value &= BITMASK(24);
1.1.1.6 root 1348: oldvalue = read_memory_disasm(space, address);
1.1.1.2 root 1349:
1350: write_memory_raw(space,address,value);
1351:
1.1 root 1352: switch(space) {
1353: case DSP_SPACE_X:
1.1.1.4 root 1354: space_c = 'x';
1.1 root 1355: break;
1356: case DSP_SPACE_Y:
1.1.1.4 root 1357: space_c = 'y';
1358: break;
1359: default:
1.1 root 1360: break;
1361: }
1.1.1.4 root 1362:
1.1.1.6 root 1363: curvalue = read_memory_disasm(space, address);
1.1.1.5 root 1364: sprintf(str_disasm_memory[disasm_memory_ptr],"Mem: %c:0x%04x 0x%06x -> 0x%06x", space_c, address, oldvalue, curvalue);
1365: disasm_memory_ptr ++;
1.1 root 1366: }
1367:
1.1.1.4 root 1368: static void dsp_write_reg(Uint32 numreg, Uint32 value)
1369: {
1.1.1.5 root 1370: Uint32 stack_error;
1.1.1.4 root 1371:
1.1.1.7 ! root 1372: switch (numreg) {
! 1373: case DSP_REG_A:
! 1374: dsp_core.registers[DSP_REG_A0] = 0;
! 1375: dsp_core.registers[DSP_REG_A1] = value;
! 1376: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
! 1377: break;
! 1378: case DSP_REG_B:
! 1379: dsp_core.registers[DSP_REG_B0] = 0;
! 1380: dsp_core.registers[DSP_REG_B1] = value;
! 1381: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
! 1382: break;
! 1383: case DSP_REG_OMR:
! 1384: dsp_core.registers[DSP_REG_OMR] = value & 0xc7;
! 1385: break;
! 1386: case DSP_REG_SR:
! 1387: dsp_core.registers[DSP_REG_SR] = value & 0xaf7f;
! 1388: break;
! 1389: case DSP_REG_SP:
! 1390: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
! 1391: if ((stack_error==0) && (value & (1<<DSP_SP_SE))) {
! 1392: /* Stack full, raise interrupt */
! 1393: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
! 1394: if (!isDsp_in_disasm_mode)
! 1395: fprintf(stderr,"Dsp: Stack Overflow\n");
! 1396: }
! 1397: dsp_core.registers[DSP_REG_SP] = value & BITMASK(6);
! 1398: dsp_compute_ssh_ssl();
! 1399: break;
! 1400: case DSP_REG_SSH:
! 1401: dsp_stack_push(value, 0, 1);
! 1402: break;
! 1403: case DSP_REG_SSL:
! 1404: numreg = dsp_core.registers[DSP_REG_SP] & BITMASK(4);
! 1405: if (numreg == 0) {
! 1406: value = 0;
! 1407: }
! 1408: dsp_core.stack[1][numreg] = value & BITMASK(16);
! 1409: dsp_core.registers[DSP_REG_SSL] = value & BITMASK(16);
! 1410: break;
! 1411: default:
! 1412: dsp_core.registers[numreg] = value;
! 1413: dsp_core.registers[numreg] &= BITMASK(registers_mask[numreg]);
! 1414: break;
1.1.1.4 root 1415: }
1416: }
1417:
1.1 root 1418: /**********************************
1419: * Stack push/pop
1420: **********************************/
1421:
1.1.1.4 root 1422: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly)
1.1 root 1423: {
1.1.1.4 root 1424: Uint32 stack_error, underflow, stack;
1425:
1.1.1.6 root 1426: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1427: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1428: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) + 1;
1.1.1.4 root 1429:
1430:
1431: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1.1 root 1432: /* Stack full, raise interrupt */
1.1.1.5 root 1433: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.6 root 1434: if (!isDsp_in_disasm_mode)
1435: fprintf(stderr,"Dsp: Stack Overflow\n");
1.1 root 1436: }
1.1.1.4 root 1437:
1.1.1.6 root 1438: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1.1.1.4 root 1439: stack &= BITMASK(4);
1.1 root 1440:
1.1.1.4 root 1441: if (stack) {
1442: /* SSH part */
1.1.1.6 root 1443: dsp_core.stack[0][stack] = curpc & BITMASK(16);
1.1.1.4 root 1444: /* SSL part, if instruction is not like "MOVEC xx, SSH" */
1445: if (sshOnly == 0) {
1.1.1.6 root 1446: dsp_core.stack[1][stack] = cursr & BITMASK(16);
1.1.1.4 root 1447: }
1448: } else {
1.1.1.6 root 1449: dsp_core.stack[0][0] = 0;
1450: dsp_core.stack[1][0] = 0;
1.1.1.4 root 1451: }
1.1 root 1452:
1.1.1.4 root 1453: /* Update SSH and SSL registers */
1.1.1.6 root 1454: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1455: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1 root 1456: }
1457:
1.1.1.2 root 1458: static void dsp_stack_pop(Uint32 *newpc, Uint32 *newsr)
1.1 root 1459: {
1.1.1.4 root 1460: Uint32 stack_error, underflow, stack;
1461:
1.1.1.6 root 1462: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1463: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1464: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) - 1;
1.1.1.4 root 1465:
1466: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1467: /* Stack empty*/
1.1.1.5 root 1468: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.6 root 1469: if (!isDsp_in_disasm_mode)
1470: fprintf(stderr,"Dsp: Stack underflow\n");
1.1 root 1471: }
1472:
1.1.1.6 root 1473: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1.1.1.4 root 1474: stack &= BITMASK(4);
1.1.1.6 root 1475: *newpc = dsp_core.registers[DSP_REG_SSH];
1476: *newsr = dsp_core.registers[DSP_REG_SSL];
1.1.1.4 root 1477:
1.1.1.6 root 1478: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1479: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1.1.4 root 1480: }
1481:
1482: static void dsp_compute_ssh_ssl(void)
1483: {
1484: Uint32 stack;
1.1 root 1485:
1.1.1.6 root 1486: stack = dsp_core.registers[DSP_REG_SP];
1.1.1.4 root 1487: stack &= BITMASK(4);
1.1.1.6 root 1488: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1489: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1 root 1490: }
1491:
1492: /**********************************
1493: * Effective address calculation
1494: **********************************/
1495:
1.1.1.2 root 1496: static void dsp_update_rn(Uint32 numreg, Sint16 modifier)
1.1 root 1497: {
1.1.1.2 root 1498: Sint16 value;
1499: Uint16 m_reg;
1.1 root 1500:
1.1.1.6 root 1501: m_reg = (Uint16) dsp_core.registers[DSP_REG_M0+numreg];
1.1.1.7 ! root 1502: if (m_reg == 65535) {
! 1503: /* Linear addressing mode */
! 1504: value = (Sint16) dsp_core.registers[DSP_REG_R0+numreg];
! 1505: value += modifier;
! 1506: dsp_core.registers[DSP_REG_R0+numreg] = ((Uint32) value) & BITMASK(16);
! 1507: } else if (m_reg == 0) {
1.1 root 1508: /* Bit reversed carry update */
1509: dsp_update_rn_bitreverse(numreg);
1.1.1.4 root 1510: } else if (m_reg<=32767) {
1.1 root 1511: /* Modulo update */
1512: dsp_update_rn_modulo(numreg, modifier);
1513: } else {
1514: /* Undefined */
1515: }
1516: }
1517:
1.1.1.2 root 1518: static void dsp_update_rn_bitreverse(Uint32 numreg)
1.1 root 1519: {
1520: int revbits, i;
1.1.1.2 root 1521: Uint32 value, r_reg;
1.1 root 1522:
1523: /* Check how many bits to reverse */
1.1.1.6 root 1524: value = dsp_core.registers[DSP_REG_N0+numreg];
1.1 root 1525: for (revbits=0;revbits<16;revbits++) {
1526: if (value & (1<<revbits)) {
1527: break;
1528: }
1529: }
1530: revbits++;
1531:
1532: /* Reverse Rn bits */
1.1.1.6 root 1533: r_reg = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1534: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1535: for (i=0;i<revbits;i++) {
1536: if (r_reg & (1<<i)) {
1537: value |= 1<<(revbits-i-1);
1538: }
1539: }
1540:
1541: /* Increment */
1542: value++;
1543: value &= BITMASK(revbits);
1544:
1545: /* Reverse Rn bits */
1546: r_reg &= (BITMASK(16)-BITMASK(revbits));
1547: r_reg |= value;
1548:
1549: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1550: for (i=0;i<revbits;i++) {
1551: if (r_reg & (1<<i)) {
1552: value |= 1<<(revbits-i-1);
1553: }
1554: }
1555:
1.1.1.6 root 1556: dsp_core.registers[DSP_REG_R0+numreg] = value;
1.1 root 1557: }
1558:
1.1.1.2 root 1559: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier)
1.1 root 1560: {
1.1.1.2 root 1561: Uint16 bufsize, modulo, lobound, hibound, bufmask;
1.1.1.4 root 1562: Sint16 r_reg, orig_modifier=modifier;
1.1 root 1563:
1.1.1.6 root 1564: modulo = dsp_core.registers[DSP_REG_M0+numreg]+1;
1.1 root 1565: bufsize = 1;
1.1.1.2 root 1566: bufmask = BITMASK(16);
1.1 root 1567: while (bufsize < modulo) {
1568: bufsize <<= 1;
1.1.1.2 root 1569: bufmask <<= 1;
1.1 root 1570: }
1571:
1.1.1.6 root 1572: lobound = dsp_core.registers[DSP_REG_R0+numreg] & bufmask;
1.1.1.2 root 1573: hibound = lobound + modulo - 1;
1.1 root 1574:
1.1.1.6 root 1575: r_reg = (Sint16) dsp_core.registers[DSP_REG_R0+numreg];
1.1.1.4 root 1576:
1577: if (orig_modifier>modulo) {
1578: while (modifier>bufsize) {
1579: r_reg += bufsize;
1580: modifier -= bufsize;
1581: }
1582: while (modifier<-bufsize) {
1583: r_reg -= bufsize;
1584: modifier += bufsize;
1585: }
1.1.1.2 root 1586: }
1.1.1.4 root 1587:
1.1 root 1588: r_reg += modifier;
1.1.1.4 root 1589:
1590: if (orig_modifier!=modulo) {
1591: if (r_reg>hibound) {
1592: r_reg -= modulo;
1593: } else if (r_reg<lobound) {
1594: r_reg += modulo;
1595: }
1.1 root 1596: }
1597:
1.1.1.6 root 1598: dsp_core.registers[DSP_REG_R0+numreg] = ((Uint32) r_reg) & BITMASK(16);
1.1 root 1599: }
1600:
1.1.1.2 root 1601: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr)
1.1 root 1602: {
1.1.1.2 root 1603: Uint32 value, numreg, curreg;
1.1 root 1604:
1605: value = (ea_mode >> 3) & BITMASK(3);
1606: numreg = ea_mode & BITMASK(3);
1607: switch (value) {
1608: case 0:
1609: /* (Rx)-Nx */
1.1.1.6 root 1610: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1611: dsp_update_rn(numreg, -dsp_core.registers[DSP_REG_N0+numreg]);
1.1 root 1612: break;
1613: case 1:
1614: /* (Rx)+Nx */
1.1.1.6 root 1615: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1616: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1.1 root 1617: break;
1618: case 2:
1619: /* (Rx)- */
1.1.1.6 root 1620: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1621: dsp_update_rn(numreg, -1);
1622: break;
1623: case 3:
1624: /* (Rx)+ */
1.1.1.6 root 1625: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1626: dsp_update_rn(numreg, +1);
1627: break;
1628: case 4:
1629: /* (Rx) */
1.1.1.6 root 1630: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1631: break;
1632: case 5:
1633: /* (Rx+Nx) */
1.1.1.6 root 1634: dsp_core.instr_cycle += 2;
1635: curreg = dsp_core.registers[DSP_REG_R0+numreg];
1636: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1637: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1638: dsp_core.registers[DSP_REG_R0+numreg] = curreg;
1.1 root 1639: break;
1640: case 6:
1641: /* aa */
1.1.1.6 root 1642: dsp_core.instr_cycle += 2;
1643: *dst_addr = read_memory_p(dsp_core.pc+1);
1.1 root 1644: cur_inst_len++;
1645: if (numreg != 0) {
1646: return 1; /* immediate value */
1647: }
1648: break;
1649: case 7:
1650: /* -(Rx) */
1.1.1.6 root 1651: dsp_core.instr_cycle += 2;
1.1 root 1652: dsp_update_rn(numreg, -1);
1.1.1.6 root 1653: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1654: break;
1655: }
1656: /* address */
1657: return 0;
1658: }
1659:
1660: /**********************************
1661: * Condition code test
1662: **********************************/
1663:
1.1.1.2 root 1664: static int dsp_calc_cc(Uint32 cc_code)
1.1 root 1665: {
1.1.1.4 root 1666: Uint16 value1, value2, value3;
1.1 root 1667:
1.1.1.4 root 1668: switch (cc_code) {
1669: case 0: /* CC (HS) */
1.1.1.6 root 1670: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1.1.1.4 root 1671: return (value1==0);
1672: case 1: /* GE */
1.1.1.6 root 1673: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1674: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1.1.1.4 root 1675: return ((value1 ^ value2) == 0);
1676: case 2: /* NE */
1.1.1.6 root 1677: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_Z);
1.1.1.4 root 1678: return (value1==0);
1679: case 3: /* PL */
1.1.1.6 root 1680: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_N);
1.1.1.4 root 1681: return (value1==0);
1682: case 4: /* NN */
1.1.1.6 root 1683: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1684: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1685: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1.1.1.4 root 1686: return ((value1 | (value2 & value3)) == 0);
1687: case 5: /* EC */
1.1.1.6 root 1688: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_E);
1.1.1.4 root 1689: return (value1==0);
1690: case 6: /* LC */
1.1.1.6 root 1691: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_L);
1.1.1.4 root 1692: return (value1==0);
1693: case 7: /* GT */
1.1.1.6 root 1694: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1695: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1696: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1697: return ((value3 | (value1 ^ value2)) == 0);
1698: case 8: /* CS (LO) */
1.1.1.6 root 1699: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1.1.1.4 root 1700: return (value1==1);
1701: case 9: /* LT */
1.1.1.6 root 1702: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1703: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1.1.1.4 root 1704: return ((value1 ^ value2) == 1);
1705: case 10: /* EQ */
1.1.1.6 root 1706: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1707: return (value1==1);
1708: case 11: /* MI */
1.1.1.6 root 1709: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1.1.1.4 root 1710: return (value1==1);
1711: case 12: /* NR */
1.1.1.6 root 1712: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1713: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1714: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1.1.1.4 root 1715: return ((value1 | (value2 & value3)) == 1);
1716: case 13: /* ES */
1.1.1.6 root 1717: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_E) & 1;
1.1.1.4 root 1718: return (value1==1);
1719: case 14: /* LS */
1.1.1.6 root 1720: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_L) & 1;
1.1.1.4 root 1721: return (value1==1);
1722: case 15: /* LE */
1.1.1.6 root 1723: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1724: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1725: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1726: return ((value3 | (value1 ^ value2)) == 1);
1727: }
1728: return 0;
1.1 root 1729: }
1730:
1731: /**********************************
1732: * Highbyte opcodes dispatchers
1733: **********************************/
1734:
1735: static void opcode8h_0(void)
1736: {
1.1.1.4 root 1737: switch(cur_inst) {
1738: case 0x000000:
1739: dsp_nop();
1.1 root 1740: break;
1.1.1.4 root 1741: case 0x000004:
1742: dsp_rti();
1.1 root 1743: break;
1.1.1.4 root 1744: case 0x000005:
1745: dsp_illegal();
1.1 root 1746: break;
1.1.1.4 root 1747: case 0x000006:
1748: dsp_swi();
1749: break;
1750: case 0x00000c:
1751: dsp_rts();
1752: break;
1753: case 0x000084:
1754: dsp_reset();
1755: break;
1756: case 0x000086:
1757: dsp_wait();
1758: break;
1759: case 0x000087:
1760: dsp_stop();
1761: break;
1762: case 0x00008c:
1763: dsp_enddo();
1.1 root 1764: break;
1765: }
1766: }
1767:
1768: /**********************************
1769: * Non-parallel moves instructions
1770: **********************************/
1771:
1772: static void dsp_undefined(void)
1773: {
1.1.1.6 root 1774: if (isDsp_in_disasm_mode == false) {
1775: cur_inst_len = 0;
1776: fprintf(stderr, "Dsp: 0x%04x: 0x%06x Illegal instruction\n",dsp_core.pc, cur_inst);
1.1.1.7 ! root 1777: /* Add some artificial CPU cycles to avoid being stuck in an infinite loop */
1.1.1.6 root 1778: dsp_core.instr_cycle += 100;
1779: }
1780: else {
1781: cur_inst_len = 1;
1782: dsp_core.instr_cycle = 0;
1783: }
1.1 root 1784: }
1785:
1786: static void dsp_andi(void)
1787: {
1.1.1.2 root 1788: Uint32 regnum, value;
1.1 root 1789:
1790: value = (cur_inst >> 8) & BITMASK(8);
1791: regnum = cur_inst & BITMASK(2);
1792: switch(regnum) {
1793: case 0:
1794: /* mr */
1.1.1.6 root 1795: dsp_core.registers[DSP_REG_SR] &= (value<<8)|BITMASK(8);
1.1 root 1796: break;
1797: case 1:
1798: /* ccr */
1.1.1.6 root 1799: dsp_core.registers[DSP_REG_SR] &= (BITMASK(8)<<8)|value;
1.1 root 1800: break;
1801: case 2:
1802: /* omr */
1.1.1.6 root 1803: dsp_core.registers[DSP_REG_OMR] &= value;
1.1 root 1804: break;
1805: }
1806: }
1807:
1.1.1.4 root 1808: static void dsp_bchg_aa(void)
1.1 root 1809: {
1.1.1.4 root 1810: Uint32 memspace, addr, value, newcarry, numbit;
1.1 root 1811:
1812: memspace = (cur_inst>>6) & 1;
1813: value = (cur_inst>>8) & BITMASK(6);
1814: numbit = cur_inst & BITMASK(5);
1815:
1.1.1.4 root 1816: addr = value;
1817: value = read_memory(memspace, addr);
1818: newcarry = (value>>numbit) & 1;
1819: if (newcarry) {
1820: value -= (1<<numbit);
1821: } else {
1822: value += (1<<numbit);
1.1 root 1823: }
1.1.1.4 root 1824: write_memory(memspace, addr, value);
1.1 root 1825:
1826: /* Set carry */
1.1.1.6 root 1827: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1828: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1829:
1.1.1.6 root 1830: dsp_core.instr_cycle += 2;
1.1 root 1831: }
1832:
1.1.1.4 root 1833: static void dsp_bchg_ea(void)
1.1 root 1834: {
1.1.1.4 root 1835: Uint32 memspace, addr, value, newcarry, numbit;
1.1 root 1836:
1837: memspace = (cur_inst>>6) & 1;
1838: value = (cur_inst>>8) & BITMASK(6);
1839: numbit = cur_inst & BITMASK(5);
1840:
1.1.1.4 root 1841: dsp_calc_ea(value, &addr);
1842: value = read_memory(memspace, addr);
1843: newcarry = (value>>numbit) & 1;
1844: if (newcarry) {
1845: value -= (1<<numbit);
1846: } else {
1847: value += (1<<numbit);
1.1 root 1848: }
1.1.1.4 root 1849: write_memory(memspace, addr, value);
1.1 root 1850:
1851: /* Set carry */
1.1.1.6 root 1852: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1853: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1854:
1.1.1.6 root 1855: dsp_core.instr_cycle += 2;
1.1 root 1856: }
1857:
1.1.1.4 root 1858: static void dsp_bchg_pp(void)
1.1 root 1859: {
1.1.1.4 root 1860: Uint32 memspace, addr, value, newcarry, numbit;
1.1 root 1861:
1862: memspace = (cur_inst>>6) & 1;
1863: value = (cur_inst>>8) & BITMASK(6);
1864: numbit = cur_inst & BITMASK(5);
1865:
1.1.1.4 root 1866: addr = 0xffc0 + value;
1867: value = read_memory(memspace, addr);
1868: newcarry = (value>>numbit) & 1;
1869: if (newcarry) {
1870: value -= (1<<numbit);
1871: } else {
1872: value += (1<<numbit);
1.1 root 1873: }
1.1.1.4 root 1874: write_memory(memspace, addr, value);
1.1 root 1875:
1876: /* Set carry */
1.1.1.6 root 1877: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1878: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1879:
1.1.1.6 root 1880: dsp_core.instr_cycle += 2;
1.1 root 1881: }
1882:
1.1.1.4 root 1883: static void dsp_bchg_reg(void)
1.1 root 1884: {
1.1.1.4 root 1885: Uint32 value, numreg, newcarry, numbit;
1.1 root 1886:
1.1.1.4 root 1887: numreg = (cur_inst>>8) & BITMASK(6);
1.1 root 1888: numbit = cur_inst & BITMASK(5);
1889:
1.1.1.4 root 1890: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
1891: dsp_pm_read_accu24(numreg, &value);
1892: } else {
1.1.1.6 root 1893: value = dsp_core.registers[numreg];
1.1 root 1894: }
1895:
1.1.1.4 root 1896: newcarry = (value>>numbit) & 1;
1897: if (newcarry) {
1898: value -= (1<<numbit);
1899: } else {
1900: value += (1<<numbit);
1901: }
1902:
1903: dsp_write_reg(numreg, value);
1904:
1.1 root 1905: /* Set carry */
1.1.1.6 root 1906: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1907: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1908:
1.1.1.6 root 1909: dsp_core.instr_cycle += 2;
1.1 root 1910: }
1911:
1.1.1.4 root 1912: static void dsp_bclr_aa(void)
1.1 root 1913: {
1.1.1.4 root 1914: Uint32 memspace, addr, value, newcarry, numbit;
1915:
1916: memspace = (cur_inst>>6) & 1;
1917: addr = (cur_inst>>8) & BITMASK(6);
1918: numbit = cur_inst & BITMASK(5);
1.1 root 1919:
1.1.1.4 root 1920: value = read_memory(memspace, addr);
1921: newcarry = (value>>numbit) & 1;
1922: value &= 0xffffffff-(1<<numbit);
1923: write_memory(memspace, addr, value);
1.1.1.2 root 1924:
1.1.1.4 root 1925: /* Set carry */
1.1.1.6 root 1926: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1927: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 1928:
1.1.1.6 root 1929: dsp_core.instr_cycle += 2;
1.1.1.4 root 1930: }
1.1 root 1931:
1.1.1.4 root 1932: static void dsp_bclr_ea(void)
1933: {
1934: Uint32 memspace, addr, value, newcarry, numbit;
1935:
1936: memspace = (cur_inst>>6) & 1;
1937: value = (cur_inst>>8) & BITMASK(6);
1938: numbit = cur_inst & BITMASK(5);
1.1 root 1939:
1.1.1.4 root 1940: dsp_calc_ea(value, &addr);
1941: value = read_memory(memspace, addr);
1942: newcarry = (value>>numbit) & 1;
1943: value &= 0xffffffff-(1<<numbit);
1944: write_memory(memspace, addr, value);
1.1.1.2 root 1945:
1.1.1.4 root 1946: /* Set carry */
1.1.1.6 root 1947: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1948: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1949:
1.1.1.6 root 1950: dsp_core.instr_cycle += 2;
1.1 root 1951: }
1952:
1.1.1.4 root 1953: static void dsp_bclr_pp(void)
1954: {
1955: Uint32 memspace, addr, value, newcarry, numbit;
1956:
1957: memspace = (cur_inst>>6) & 1;
1958: value = (cur_inst>>8) & BITMASK(6);
1959: numbit = cur_inst & BITMASK(5);
1.1.1.3 root 1960:
1.1.1.4 root 1961: addr = 0xffc0 + value;
1962: value = read_memory(memspace, addr);
1963: newcarry = (value>>numbit) & 1;
1964: value &= 0xffffffff-(1<<numbit);
1965: write_memory(memspace, addr, value);
1.1.1.3 root 1966:
1.1.1.4 root 1967: /* Set carry */
1.1.1.6 root 1968: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1969: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 1970:
1.1.1.6 root 1971: dsp_core.instr_cycle += 2;
1.1.1.4 root 1972: }
1.1 root 1973:
1.1.1.4 root 1974: static void dsp_bclr_reg(void)
1975: {
1976: Uint32 value, numreg, newcarry, numbit;
1977:
1978: numreg = (cur_inst>>8) & BITMASK(6);
1979: numbit = cur_inst & BITMASK(5);
1.1 root 1980:
1.1.1.4 root 1981: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
1982: dsp_pm_read_accu24(numreg, &value);
1983: } else {
1.1.1.6 root 1984: value = dsp_core.registers[numreg];
1.1.1.4 root 1985: }
1.1 root 1986:
1.1.1.4 root 1987: newcarry = (value>>numbit) & 1;
1988: value &= 0xffffffff-(1<<numbit);
1.1 root 1989:
1.1.1.4 root 1990: dsp_write_reg(numreg, value);
1991:
1992: /* Set carry */
1.1.1.6 root 1993: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1994: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 1995:
1.1.1.6 root 1996: dsp_core.instr_cycle += 2;
1.1 root 1997: }
1998:
1.1.1.4 root 1999: static void dsp_bset_aa(void)
1.1 root 2000: {
1.1.1.4 root 2001: Uint32 memspace, addr, value, newcarry, numbit;
2002:
2003: memspace = (cur_inst>>6) & 1;
2004: value = (cur_inst>>8) & BITMASK(6);
2005: numbit = cur_inst & BITMASK(5);
1.1 root 2006:
1.1.1.4 root 2007: addr = value;
2008: value = read_memory(memspace, addr);
2009: newcarry = (value>>numbit) & 1;
2010: value |= (1<<numbit);
2011: write_memory(memspace, addr, value);
2012:
2013: /* Set carry */
1.1.1.6 root 2014: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2015: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2016:
1.1.1.6 root 2017: dsp_core.instr_cycle += 2;
1.1.1.4 root 2018: }
2019:
2020: static void dsp_bset_ea(void)
2021: {
2022: Uint32 memspace, addr, value, newcarry, numbit;
2023:
2024: memspace = (cur_inst>>6) & 1;
2025: value = (cur_inst>>8) & BITMASK(6);
2026: numbit = cur_inst & BITMASK(5);
2027:
2028: dsp_calc_ea(value, &addr);
2029: value = read_memory(memspace, addr);
2030: newcarry = (value>>numbit) & 1;
2031: value |= (1<<numbit);
2032: write_memory(memspace, addr, value);
2033:
2034: /* Set carry */
1.1.1.6 root 2035: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2036: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2037:
1.1.1.6 root 2038: dsp_core.instr_cycle += 2;
1.1.1.4 root 2039: }
2040:
2041: static void dsp_bset_pp(void)
2042: {
2043: Uint32 memspace, addr, value, newcarry, numbit;
2044:
2045: memspace = (cur_inst>>6) & 1;
2046: value = (cur_inst>>8) & BITMASK(6);
2047: numbit = cur_inst & BITMASK(5);
2048: addr = 0xffc0 + value;
2049: value = read_memory(memspace, addr);
2050: newcarry = (value>>numbit) & 1;
2051: value |= (1<<numbit);
2052: write_memory(memspace, addr, value);
2053:
2054: /* Set carry */
1.1.1.6 root 2055: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2056: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2057:
1.1.1.6 root 2058: dsp_core.instr_cycle += 2;
1.1.1.4 root 2059: }
2060:
2061: static void dsp_bset_reg(void)
2062: {
2063: Uint32 value, numreg, newcarry, numbit;
2064:
2065: numreg = (cur_inst>>8) & BITMASK(6);
2066: numbit = cur_inst & BITMASK(5);
2067:
2068: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2069: dsp_pm_read_accu24(numreg, &value);
2070: } else {
1.1.1.6 root 2071: value = dsp_core.registers[numreg];
1.1.1.4 root 2072: }
2073:
2074: newcarry = (value>>numbit) & 1;
2075: value |= (1<<numbit);
2076:
2077: dsp_write_reg(numreg, value);
2078:
2079: /* Set carry */
1.1.1.6 root 2080: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2081: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2082:
1.1.1.6 root 2083: dsp_core.instr_cycle += 2;
1.1.1.4 root 2084: }
2085:
2086: static void dsp_btst_aa(void)
2087: {
2088: Uint32 memspace, addr, value, newcarry, numbit;
2089:
2090: memspace = (cur_inst>>6) & 1;
2091: value = (cur_inst>>8) & BITMASK(6);
2092: numbit = cur_inst & BITMASK(5);
2093:
2094: addr = value;
2095: value = read_memory(memspace, addr);
2096: newcarry = (value>>numbit) & 1;
2097:
2098: /* Set carry */
1.1.1.6 root 2099: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2100: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2101:
1.1.1.6 root 2102: dsp_core.instr_cycle += 2;
1.1.1.4 root 2103: }
2104:
2105: static void dsp_btst_ea(void)
2106: {
2107: Uint32 memspace, addr, value, newcarry, numbit;
2108:
2109: memspace = (cur_inst>>6) & 1;
2110: value = (cur_inst>>8) & BITMASK(6);
2111: numbit = cur_inst & BITMASK(5);
2112:
2113: dsp_calc_ea(value, &addr);
2114: value = read_memory(memspace, addr);
2115: newcarry = (value>>numbit) & 1;
2116:
2117: /* Set carry */
1.1.1.6 root 2118: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2119: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2120:
1.1.1.6 root 2121: dsp_core.instr_cycle += 2;
1.1.1.4 root 2122: }
2123:
2124: static void dsp_btst_pp(void)
2125: {
2126: Uint32 memspace, addr, value, newcarry, numbit;
2127:
2128: memspace = (cur_inst>>6) & 1;
2129: value = (cur_inst>>8) & BITMASK(6);
2130: numbit = cur_inst & BITMASK(5);
2131:
2132: addr = 0xffc0 + value;
2133: value = read_memory(memspace, addr);
2134: newcarry = (value>>numbit) & 1;
2135:
2136: /* Set carry */
1.1.1.6 root 2137: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2138: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2139:
1.1.1.6 root 2140: dsp_core.instr_cycle += 2;
1.1.1.4 root 2141: }
2142:
2143: static void dsp_btst_reg(void)
2144: {
2145: Uint32 value, numreg, newcarry, numbit;
2146:
2147: numreg = (cur_inst>>8) & BITMASK(6);
2148: numbit = cur_inst & BITMASK(5);
2149:
2150: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2151: dsp_pm_read_accu24(numreg, &value);
2152: } else {
1.1.1.6 root 2153: value = dsp_core.registers[numreg];
1.1.1.4 root 2154: }
2155:
2156: newcarry = (value>>numbit) & 1;
2157:
2158: /* Set carry */
1.1.1.6 root 2159: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2160: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2161:
1.1.1.6 root 2162: dsp_core.instr_cycle += 2;
1.1.1.4 root 2163: }
2164:
2165: static void dsp_div(void)
2166: {
2167: Uint32 srcreg, destreg, source[3], dest[3];
2168: Uint16 newsr;
2169:
2170: srcreg = DSP_REG_NULL;
2171: switch((cur_inst>>4) & BITMASK(2)) {
2172: case 0: srcreg = DSP_REG_X0; break;
2173: case 1: srcreg = DSP_REG_Y0; break;
2174: case 2: srcreg = DSP_REG_X1; break;
2175: case 3: srcreg = DSP_REG_Y1; break;
2176: }
1.1.1.7 ! root 2177: source[2] = 0;
! 2178: source[1] = dsp_core.registers[srcreg];
! 2179: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.4 root 2180:
1.1.1.7 ! root 2181: destreg = DSP_REG_A + ((cur_inst>>3) & 1);
! 2182: if (destreg == DSP_REG_A) {
! 2183: dest[0] = dsp_core.registers[DSP_REG_A2];
! 2184: dest[1] = dsp_core.registers[DSP_REG_A1];
! 2185: dest[2] = dsp_core.registers[DSP_REG_A0];
! 2186: }
! 2187: else {
! 2188: dest[0] = dsp_core.registers[DSP_REG_B2];
! 2189: dest[1] = dsp_core.registers[DSP_REG_B1];
! 2190: dest[2] = dsp_core.registers[DSP_REG_B0];
! 2191: }
1.1.1.4 root 2192:
2193: if (((dest[0]>>7) & 1) ^ ((source[1]>>23) & 1)) {
2194: /* D += S */
2195: newsr = dsp_asl56(dest);
2196: dsp_add56(source, dest);
2197: } else {
2198: /* D -= S */
2199: newsr = dsp_asl56(dest);
2200: dsp_sub56(source, dest);
2201: }
2202:
1.1.1.6 root 2203: dest[2] |= (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1.1.4 root 2204:
1.1.1.7 ! root 2205: if (destreg == DSP_REG_A) {
! 2206: dsp_core.registers[DSP_REG_A2] = dest[0];
! 2207: dsp_core.registers[DSP_REG_A1] = dest[1];
! 2208: dsp_core.registers[DSP_REG_A0] = dest[2];
! 2209: }
! 2210: else {
! 2211: dsp_core.registers[DSP_REG_B2] = dest[0];
! 2212: dsp_core.registers[DSP_REG_B1] = dest[1];
! 2213: dsp_core.registers[DSP_REG_B0] = dest[2];
! 2214: }
! 2215:
1.1.1.6 root 2216: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
2217: dsp_core.registers[DSP_REG_SR] |= (1-((dest[0]>>7) & 1))<<DSP_SR_C;
2218: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_L);
2219: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_V);
1.1.1.4 root 2220: }
2221:
2222: /*
2223: DO instruction parameter encoding
2224:
2225: xxxxxxxx 00xxxxxx 0xxxxxxx aa
2226: xxxxxxxx 01xxxxxx 0xxxxxxx ea
2227: xxxxxxxx YYxxxxxx 1xxxxxxx imm
2228: xxxxxxxx 11xxxxxx 0xxxxxxx reg
2229: */
2230:
2231: static void dsp_do_aa(void)
2232: {
2233: Uint32 memspace, addr;
2234:
2235: /* x:aa */
2236: /* y:aa */
2237:
1.1.1.6 root 2238: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2239: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2240: cur_inst_len++;
1.1.1.6 root 2241: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2242: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1 root 2243:
2244: memspace = (cur_inst>>6) & 1;
2245: addr = (cur_inst>>8) & BITMASK(6);
1.1.1.6 root 2246: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
1.1.1.4 root 2247:
1.1.1.6 root 2248: dsp_core.instr_cycle += 4;
1.1 root 2249: }
2250:
1.1.1.3 root 2251: static void dsp_do_imm(void)
1.1 root 2252: {
2253: /* #xx */
1.1.1.3 root 2254:
1.1.1.6 root 2255: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2256: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2257: cur_inst_len++;
1.1.1.6 root 2258: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2259: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2260:
1.1.1.6 root 2261: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
1.1.1.3 root 2262: + ((cur_inst & BITMASK(4))<<8);
1.1.1.4 root 2263:
1.1.1.6 root 2264: dsp_core.instr_cycle += 4;
1.1 root 2265: }
2266:
1.1.1.3 root 2267: static void dsp_do_ea(void)
1.1 root 2268: {
1.1.1.2 root 2269: Uint32 memspace, ea_mode, addr;
1.1 root 2270:
2271: /* x:ea */
2272: /* y:ea */
2273:
1.1.1.6 root 2274: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2275: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2276: cur_inst_len++;
1.1.1.6 root 2277: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2278: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2279:
1.1 root 2280: memspace = (cur_inst>>6) & 1;
2281: ea_mode = (cur_inst>>8) & BITMASK(6);
2282: dsp_calc_ea(ea_mode, &addr);
1.1.1.6 root 2283: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
1.1.1.4 root 2284:
1.1.1.6 root 2285: dsp_core.instr_cycle += 4;
1.1 root 2286: }
2287:
1.1.1.3 root 2288: static void dsp_do_reg(void)
1.1 root 2289: {
1.1.1.2 root 2290: Uint32 numreg;
1.1 root 2291:
2292: /* S */
2293:
1.1.1.6 root 2294: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2295: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2296: cur_inst_len++;
2297:
1.1 root 2298: numreg = (cur_inst>>8) & BITMASK(6);
2299: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.6 root 2300: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
1.1 root 2301: } else {
1.1.1.6 root 2302: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
1.1 root 2303: }
1.1.1.6 root 2304: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.4 root 2305:
1.1.1.6 root 2306: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2307: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2308:
1.1.1.6 root 2309: dsp_core.instr_cycle += 4;
1.1 root 2310: }
2311:
2312: static void dsp_enddo(void)
2313: {
1.1.1.4 root 2314: Uint32 saved_pc, saved_sr;
1.1 root 2315:
1.1.1.4 root 2316: dsp_stack_pop(&saved_pc, &saved_sr);
1.1.1.6 root 2317: dsp_core.registers[DSP_REG_SR] &= 0x7f;
2318: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
2319: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
1.1 root 2320: }
2321:
2322: static void dsp_illegal(void)
2323: {
2324: /* Raise interrupt p:0x003e */
1.1.1.5 root 2325: dsp_add_interrupt(DSP_INTER_ILLEGAL);
1.1 root 2326: }
2327:
1.1.1.4 root 2328: static void dsp_jcc_imm(void)
1.1 root 2329: {
1.1.1.4 root 2330: Uint32 cc_code, newpc;
1.1 root 2331:
1.1.1.4 root 2332: newpc = cur_inst & BITMASK(12);
2333: cc_code=(cur_inst>>12) & BITMASK(4);
2334: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2335: dsp_core.pc = newpc;
1.1.1.4 root 2336: cur_inst_len = 0;
2337: }
2338:
1.1.1.6 root 2339: dsp_core.instr_cycle += 2;
1.1.1.4 root 2340: }
2341:
2342: static void dsp_jcc_ea(void)
2343: {
2344: Uint32 newpc, cc_code;
2345:
2346: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2347: cc_code=cur_inst & BITMASK(4);
1.1 root 2348:
2349: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2350: dsp_core.pc = newpc;
1.1 root 2351: cur_inst_len = 0;
2352: }
1.1.1.4 root 2353:
1.1.1.6 root 2354: dsp_core.instr_cycle += 2;
1.1 root 2355: }
2356:
1.1.1.4 root 2357: static void dsp_jclr_aa(void)
1.1 root 2358: {
1.1.1.4 root 2359: Uint32 memspace, addr, value, numbit, newaddr;
1.1 root 2360:
2361: memspace = (cur_inst>>6) & 1;
1.1.1.4 root 2362: addr = (cur_inst>>8) & BITMASK(6);
1.1 root 2363: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2364: value = read_memory(memspace, addr);
1.1.1.6 root 2365: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2366:
1.1.1.6 root 2367: dsp_core.instr_cycle += 4;
1.1 root 2368:
1.1.1.4 root 2369: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2370: dsp_core.pc = newaddr;
1.1.1.4 root 2371: cur_inst_len = 0;
2372: return;
2373: }
1.1.1.2 root 2374: ++cur_inst_len;
1.1.1.4 root 2375: }
2376:
2377: static void dsp_jclr_ea(void)
2378: {
2379: Uint32 memspace, addr, value, numbit, newaddr;
2380:
2381: memspace = (cur_inst>>6) & 1;
2382: value = (cur_inst>>8) & BITMASK(6);
2383: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2384: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2385:
2386: dsp_calc_ea(value, &addr);
2387: value = read_memory(memspace, addr);
2388:
1.1.1.6 root 2389: dsp_core.instr_cycle += 4;
1.1 root 2390:
2391: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2392: dsp_core.pc = newaddr;
1.1.1.4 root 2393: cur_inst_len = 0;
2394: return;
2395: }
2396: ++cur_inst_len;
2397: }
1.1 root 2398:
1.1.1.4 root 2399: static void dsp_jclr_pp(void)
2400: {
2401: Uint32 memspace, addr, value, numbit, newaddr;
2402:
2403: memspace = (cur_inst>>6) & 1;
2404: value = (cur_inst>>8) & BITMASK(6);
2405: numbit = cur_inst & BITMASK(5);
2406: addr = 0xffc0 + value;
2407: value = read_memory(memspace, addr);
1.1.1.6 root 2408: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2409:
1.1.1.6 root 2410: dsp_core.instr_cycle += 4;
1.1 root 2411:
1.1.1.4 root 2412: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2413: dsp_core.pc = newaddr;
1.1.1.4 root 2414: cur_inst_len = 0;
2415: return;
2416: }
2417: ++cur_inst_len;
2418: }
1.1.1.2 root 2419:
1.1.1.4 root 2420: static void dsp_jclr_reg(void)
2421: {
2422: Uint32 value, numreg, numbit, newaddr;
2423:
2424: numreg = (cur_inst>>8) & BITMASK(6);
2425: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2426: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2427:
1.1.1.4 root 2428: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2429: dsp_pm_read_accu24(numreg, &value);
2430: } else {
1.1.1.6 root 2431: value = dsp_core.registers[numreg];
1.1.1.4 root 2432: }
1.1 root 2433:
1.1.1.6 root 2434: dsp_core.instr_cycle += 4;
1.1.1.4 root 2435:
2436: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2437: dsp_core.pc = newaddr;
1.1 root 2438: cur_inst_len = 0;
2439: return;
2440: }
1.1.1.4 root 2441: ++cur_inst_len;
1.1 root 2442: }
2443:
1.1.1.4 root 2444: static void dsp_jmp_ea(void)
1.1 root 2445: {
1.1.1.2 root 2446: Uint32 newpc;
1.1 root 2447:
1.1.1.4 root 2448: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &newpc);
1.1 root 2449: cur_inst_len = 0;
1.1.1.6 root 2450: dsp_core.pc = newpc;
1.1 root 2451:
1.1.1.6 root 2452: dsp_core.instr_cycle += 2;
1.1.1.4 root 2453: }
2454:
2455: static void dsp_jmp_imm(void)
2456: {
2457: Uint32 newpc;
1.1 root 2458:
1.1.1.4 root 2459: newpc = cur_inst & BITMASK(12);
2460: cur_inst_len = 0;
1.1.1.6 root 2461: dsp_core.pc = newpc;
1.1.1.4 root 2462:
1.1.1.6 root 2463: dsp_core.instr_cycle += 2;
1.1 root 2464: }
2465:
1.1.1.4 root 2466: static void dsp_jscc_ea(void)
1.1 root 2467: {
1.1.1.2 root 2468: Uint32 newpc, cc_code;
1.1 root 2469:
1.1.1.4 root 2470: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2471: cc_code=cur_inst & BITMASK(4);
2472:
2473: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2474: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2475: dsp_core.pc = newpc;
1.1.1.4 root 2476: cur_inst_len = 0;
2477: }
2478:
1.1.1.6 root 2479: dsp_core.instr_cycle += 2;
1.1.1.4 root 2480: }
1.1 root 2481:
1.1.1.4 root 2482: static void dsp_jscc_imm(void)
2483: {
2484: Uint32 cc_code, newpc;
2485:
2486: newpc = cur_inst & BITMASK(12);
2487: cc_code=(cur_inst>>12) & BITMASK(4);
1.1 root 2488: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2489: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2490: dsp_core.pc = newpc;
1.1.1.4 root 2491: cur_inst_len = 0;
2492: }
2493:
1.1.1.6 root 2494: dsp_core.instr_cycle += 2;
1.1.1.4 root 2495: }
1.1 root 2496:
1.1.1.4 root 2497: static void dsp_jsclr_aa(void)
2498: {
2499: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2500:
2501: memspace = (cur_inst>>6) & 1;
2502: addr = (cur_inst>>8) & BITMASK(6);
2503: numbit = cur_inst & BITMASK(5);
2504: value = read_memory(memspace, addr);
1.1.1.6 root 2505: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2506:
1.1.1.6 root 2507: dsp_core.instr_cycle += 4;
1.1.1.4 root 2508:
2509: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2510: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2511: newpc = newaddr;
1.1.1.6 root 2512: dsp_core.pc = newpc;
1.1 root 2513: cur_inst_len = 0;
1.1.1.4 root 2514: return;
1.1 root 2515: }
1.1.1.4 root 2516: ++cur_inst_len;
1.1 root 2517: }
2518:
1.1.1.4 root 2519: static void dsp_jsclr_ea(void)
1.1 root 2520: {
1.1.1.4 root 2521: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1 root 2522:
2523: memspace = (cur_inst>>6) & 1;
2524: value = (cur_inst>>8) & BITMASK(6);
2525: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2526: dsp_calc_ea(value, &addr);
2527: value = read_memory(memspace, addr);
1.1.1.6 root 2528: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2529:
1.1.1.6 root 2530: dsp_core.instr_cycle += 4;
1.1.1.4 root 2531:
2532: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2533: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2534: newpc = newaddr;
1.1.1.6 root 2535: dsp_core.pc = newpc;
1.1.1.4 root 2536: cur_inst_len = 0;
2537: return;
2538: }
1.1.1.2 root 2539: ++cur_inst_len;
1.1.1.4 root 2540: }
2541:
2542: static void dsp_jsclr_pp(void)
2543: {
2544: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2545:
2546: memspace = (cur_inst>>6) & 1;
2547: value = (cur_inst>>8) & BITMASK(6);
2548: numbit = cur_inst & BITMASK(5);
2549: addr = 0xffc0 + value;
2550: value = read_memory(memspace, addr);
1.1.1.6 root 2551: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2552:
1.1.1.6 root 2553: dsp_core.instr_cycle += 4;
1.1.1.4 root 2554:
1.1 root 2555: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2556: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2557: newpc = newaddr;
1.1.1.6 root 2558: dsp_core.pc = newpc;
1.1.1.4 root 2559: cur_inst_len = 0;
2560: return;
2561: }
2562: ++cur_inst_len;
2563: }
2564:
2565: static void dsp_jsclr_reg(void)
2566: {
2567: Uint32 value, numreg, newpc, numbit, newaddr;
2568:
2569: numreg = (cur_inst>>8) & BITMASK(6);
2570: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2571: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2572:
1.1.1.4 root 2573: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2574: dsp_pm_read_accu24(numreg, &value);
2575: } else {
1.1.1.6 root 2576: value = dsp_core.registers[numreg];
1.1.1.4 root 2577: }
2578:
1.1.1.6 root 2579: dsp_core.instr_cycle += 4;
1.1.1.4 root 2580:
2581: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2582: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2583: newpc = newaddr;
1.1.1.6 root 2584: dsp_core.pc = newpc;
1.1 root 2585: cur_inst_len = 0;
1.1.1.4 root 2586: return;
1.1 root 2587: }
1.1.1.4 root 2588: ++cur_inst_len;
1.1 root 2589: }
2590:
1.1.1.4 root 2591: static void dsp_jset_aa(void)
1.1 root 2592: {
1.1.1.4 root 2593: Uint32 memspace, addr, value, numbit, newpc, newaddr;
2594:
2595: memspace = (cur_inst>>6) & 1;
2596: addr = (cur_inst>>8) & BITMASK(6);
2597: numbit = cur_inst & BITMASK(5);
2598: value = read_memory(memspace, addr);
1.1.1.6 root 2599: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2600:
1.1.1.6 root 2601: dsp_core.instr_cycle += 4;
1.1.1.4 root 2602:
2603: if (value & (1<<numbit)) {
2604: newpc = newaddr;
1.1.1.6 root 2605: dsp_core.pc = newpc;
1.1.1.4 root 2606: cur_inst_len=0;
2607: return;
2608: }
2609: ++cur_inst_len;
2610: }
2611:
2612: static void dsp_jset_ea(void)
2613: {
2614: Uint32 memspace, addr, value, numbit, newpc, newaddr;
1.1 root 2615:
2616: memspace = (cur_inst>>6) & 1;
2617: value = (cur_inst>>8) & BITMASK(6);
2618: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2619: dsp_calc_ea(value, &addr);
2620: value = read_memory(memspace, addr);
1.1.1.6 root 2621: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2622:
1.1.1.6 root 2623: dsp_core.instr_cycle += 4;
1.1.1.7 ! root 2624:
1.1.1.4 root 2625: if (value & (1<<numbit)) {
2626: newpc = newaddr;
1.1.1.6 root 2627: dsp_core.pc = newpc;
1.1.1.4 root 2628: cur_inst_len=0;
2629: return;
2630: }
2631: ++cur_inst_len;
2632: }
1.1 root 2633:
1.1.1.4 root 2634: static void dsp_jset_pp(void)
2635: {
2636: Uint32 memspace, addr, value, numbit, newpc, newaddr;
2637:
2638: memspace = (cur_inst>>6) & 1;
2639: value = (cur_inst>>8) & BITMASK(6);
2640: numbit = cur_inst & BITMASK(5);
2641: addr = 0xffc0 + value;
2642: value = read_memory(memspace, addr);
1.1.1.6 root 2643: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2644:
1.1.1.6 root 2645: dsp_core.instr_cycle += 4;
1.1.1.4 root 2646:
2647: if (value & (1<<numbit)) {
2648: newpc = newaddr;
1.1.1.6 root 2649: dsp_core.pc = newpc;
1.1.1.4 root 2650: cur_inst_len=0;
2651: return;
2652: }
2653: ++cur_inst_len;
2654: }
2655:
2656: static void dsp_jset_reg(void)
2657: {
2658: Uint32 value, numreg, numbit, newpc, newaddr;
2659:
2660: numreg = (cur_inst>>8) & BITMASK(6);
2661: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2662: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2663:
2664: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2665: dsp_pm_read_accu24(numreg, &value);
2666: } else {
1.1.1.6 root 2667: value = dsp_core.registers[numreg];
1.1.1.4 root 2668: }
2669:
1.1.1.6 root 2670: dsp_core.instr_cycle += 4;
1.1.1.4 root 2671:
2672: if (value & (1<<numbit)) {
2673: newpc = newaddr;
1.1.1.6 root 2674: dsp_core.pc = newpc;
1.1.1.4 root 2675: cur_inst_len=0;
2676: return;
2677: }
2678: ++cur_inst_len;
2679: }
2680:
2681: static void dsp_jsr_imm(void)
2682: {
2683: Uint32 newpc;
2684:
2685: newpc = cur_inst & BITMASK(12);
2686:
1.1.1.6 root 2687: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2688: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2689: }
2690: else {
1.1.1.6 root 2691: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1.1.1.4 root 2692: }
2693:
1.1.1.6 root 2694: dsp_core.pc = newpc;
1.1.1.4 root 2695: cur_inst_len = 0;
2696:
1.1.1.6 root 2697: dsp_core.instr_cycle += 2;
1.1.1.4 root 2698: }
2699:
2700: static void dsp_jsr_ea(void)
2701: {
2702: Uint32 newpc;
2703:
2704: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&newpc);
2705:
1.1.1.6 root 2706: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2707: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2708: }
2709: else {
1.1.1.6 root 2710: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1.1.1.4 root 2711: }
2712:
1.1.1.6 root 2713: dsp_core.pc = newpc;
1.1.1.4 root 2714: cur_inst_len = 0;
2715:
1.1.1.6 root 2716: dsp_core.instr_cycle += 2;
1.1.1.4 root 2717: }
2718:
2719: static void dsp_jsset_aa(void)
2720: {
2721: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2722:
2723: memspace = (cur_inst>>6) & 1;
2724: addr = (cur_inst>>8) & BITMASK(6);
2725: numbit = cur_inst & BITMASK(5);
2726: value = read_memory(memspace, addr);
1.1.1.6 root 2727: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2728:
1.1.1.6 root 2729: dsp_core.instr_cycle += 4;
1.1.1.4 root 2730:
2731: if (value & (1<<numbit)) {
1.1.1.6 root 2732: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2733: newpc = newaddr;
1.1.1.6 root 2734: dsp_core.pc = newpc;
1.1.1.4 root 2735: cur_inst_len = 0;
2736: return;
2737: }
2738: ++cur_inst_len;
2739: }
2740:
2741: static void dsp_jsset_ea(void)
2742: {
2743: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2744:
2745: memspace = (cur_inst>>6) & 1;
2746: value = (cur_inst>>8) & BITMASK(6);
2747: numbit = cur_inst & BITMASK(5);
2748: dsp_calc_ea(value, &addr);
2749: value = read_memory(memspace, addr);
1.1.1.6 root 2750: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2751:
1.1.1.6 root 2752: dsp_core.instr_cycle += 4;
1.1 root 2753:
2754: if (value & (1<<numbit)) {
1.1.1.6 root 2755: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2756: newpc = newaddr;
1.1.1.6 root 2757: dsp_core.pc = newpc;
1.1.1.4 root 2758: cur_inst_len = 0;
2759: return;
1.1 root 2760: }
1.1.1.4 root 2761: ++cur_inst_len;
1.1 root 2762: }
2763:
1.1.1.4 root 2764: static void dsp_jsset_pp(void)
1.1 root 2765: {
1.1.1.4 root 2766: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2767:
2768: memspace = (cur_inst>>6) & 1;
2769: value = (cur_inst>>8) & BITMASK(6);
2770: numbit = cur_inst & BITMASK(5);
2771: addr = 0xffc0 + value;
2772: value = read_memory(memspace, addr);
1.1.1.6 root 2773: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2774:
1.1.1.6 root 2775: dsp_core.instr_cycle += 4;
1.1 root 2776:
1.1.1.4 root 2777: if (value & (1<<numbit)) {
1.1.1.6 root 2778: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2779: newpc = newaddr;
1.1.1.6 root 2780: dsp_core.pc = newpc;
1.1.1.4 root 2781: cur_inst_len = 0;
2782: return;
2783: }
2784: ++cur_inst_len;
1.1 root 2785: }
2786:
1.1.1.4 root 2787: static void dsp_jsset_reg(void)
1.1 root 2788: {
1.1.1.4 root 2789: Uint32 value, numreg, newpc, numbit, newaddr;
1.1 root 2790:
1.1.1.4 root 2791: numreg = (cur_inst>>8) & BITMASK(6);
1.1 root 2792: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2793: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2794:
2795: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2796: dsp_pm_read_accu24(numreg, &value);
2797: } else {
1.1.1.6 root 2798: value = dsp_core.registers[numreg];
1.1.1.4 root 2799: }
1.1 root 2800:
1.1.1.6 root 2801: dsp_core.instr_cycle += 4;
1.1 root 2802:
2803: if (value & (1<<numbit)) {
1.1.1.6 root 2804: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2805: newpc = newaddr;
1.1.1.6 root 2806: dsp_core.pc = newpc;
1.1 root 2807: cur_inst_len = 0;
1.1.1.4 root 2808: return;
1.1 root 2809: }
1.1.1.4 root 2810: ++cur_inst_len;
1.1 root 2811: }
2812:
2813: static void dsp_lua(void)
2814: {
1.1.1.2 root 2815: Uint32 value, srcreg, dstreg, srcsave, srcnew;
2816:
1.1 root 2817: srcreg = (cur_inst>>8) & BITMASK(3);
1.1.1.2 root 2818:
1.1.1.6 root 2819: srcsave = dsp_core.registers[DSP_REG_R0+srcreg];
1.1.1.2 root 2820: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &value);
1.1.1.6 root 2821: srcnew = dsp_core.registers[DSP_REG_R0+srcreg];
2822: dsp_core.registers[DSP_REG_R0+srcreg] = srcsave;
1.1.1.2 root 2823:
1.1 root 2824: dstreg = cur_inst & BITMASK(3);
2825:
2826: if (cur_inst & (1<<3)) {
1.1.1.6 root 2827: dsp_core.registers[DSP_REG_N0+dstreg] = srcnew;
1.1 root 2828: } else {
1.1.1.6 root 2829: dsp_core.registers[DSP_REG_R0+dstreg] = srcnew;
1.1 root 2830: }
2831:
1.1.1.6 root 2832: dsp_core.instr_cycle += 2;
1.1 root 2833: }
2834:
1.1.1.3 root 2835: static void dsp_movec_reg(void)
1.1 root 2836: {
1.1.1.4 root 2837: Uint32 numreg1, numreg2, value, dummy;
1.1 root 2838:
2839: /* S1,D2 */
2840: /* S2,D1 */
2841:
2842: numreg2 = (cur_inst>>8) & BITMASK(6);
1.1.1.4 root 2843: numreg1 = cur_inst & BITMASK(6);
1.1 root 2844:
2845: if (cur_inst & (1<<15)) {
2846: /* Write D1 */
2847:
2848: if ((numreg2 == DSP_REG_A) || (numreg2 == DSP_REG_B)) {
1.1.1.4 root 2849: dsp_pm_read_accu24(numreg2, &value);
1.1 root 2850: } else {
1.1.1.6 root 2851: value = dsp_core.registers[numreg2];
1.1 root 2852: }
1.1.1.4 root 2853: value &= BITMASK(registers_mask[numreg1]);
2854: dsp_write_reg(numreg1, value);
1.1 root 2855: } else {
2856: /* Read S1 */
1.1.1.4 root 2857: if (numreg1 == DSP_REG_SSH) {
2858: dsp_stack_pop(&value, &dummy);
2859: }
2860: else {
1.1.1.6 root 2861: value = dsp_core.registers[numreg1];
1.1.1.4 root 2862: }
1.1 root 2863:
1.1.1.7 ! root 2864: if (numreg2 == DSP_REG_A) {
! 2865: dsp_core.registers[DSP_REG_A0] = 0;
! 2866: dsp_core.registers[DSP_REG_A1] = value & BITMASK(24);
! 2867: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
! 2868: }
! 2869: else if (numreg2 == DSP_REG_B) {
! 2870: dsp_core.registers[DSP_REG_B0] = 0;
! 2871: dsp_core.registers[DSP_REG_B1] = value & BITMASK(24);
! 2872: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
! 2873: }
! 2874: else {
1.1.1.6 root 2875: dsp_core.registers[numreg2] = value & BITMASK(registers_mask[numreg2]);
1.1 root 2876: }
2877: }
2878: }
2879:
1.1.1.3 root 2880: static void dsp_movec_aa(void)
1.1 root 2881: {
1.1.1.4 root 2882: Uint32 numreg, addr, memspace, value, dummy;
1.1 root 2883:
2884: /* x:aa,D1 */
2885: /* S1,x:aa */
2886: /* y:aa,D1 */
2887: /* S1,y:aa */
2888:
1.1.1.4 root 2889: numreg = cur_inst & BITMASK(6);
1.1 root 2890: addr = (cur_inst>>8) & BITMASK(6);
2891: memspace = (cur_inst>>6) & 1;
2892:
2893: if (cur_inst & (1<<15)) {
2894: /* Write D1 */
1.1.1.4 root 2895: value = read_memory(memspace, addr);
2896: value &= BITMASK(registers_mask[numreg]);
2897: dsp_write_reg(numreg, value);
1.1 root 2898: } else {
2899: /* Read S1 */
1.1.1.4 root 2900: if (numreg == DSP_REG_SSH) {
2901: dsp_stack_pop(&value, &dummy);
2902: }
2903: else {
1.1.1.6 root 2904: value = dsp_core.registers[numreg];
1.1.1.4 root 2905: }
2906: write_memory(memspace, addr, value);
1.1 root 2907: }
2908: }
2909:
1.1.1.3 root 2910: static void dsp_movec_imm(void)
1.1 root 2911: {
1.1.1.4 root 2912: Uint32 numreg, value;
1.1 root 2913:
2914: /* #xx,D1 */
1.1.1.4 root 2915: numreg = cur_inst & BITMASK(6);
2916: value = (cur_inst>>8) & BITMASK(8);
2917: value &= BITMASK(registers_mask[numreg]);
2918: dsp_write_reg(numreg, value);
1.1 root 2919: }
2920:
1.1.1.3 root 2921: static void dsp_movec_ea(void)
1.1 root 2922: {
1.1.1.4 root 2923: Uint32 numreg, addr, memspace, ea_mode, value, dummy;
1.1 root 2924: int retour;
2925:
2926: /* x:ea,D1 */
2927: /* S1,x:ea */
2928: /* y:ea,D1 */
2929: /* S1,y:ea */
2930: /* #xxxx,D1 */
2931:
1.1.1.4 root 2932: numreg = cur_inst & BITMASK(6);
1.1 root 2933: ea_mode = (cur_inst>>8) & BITMASK(6);
2934: memspace = (cur_inst>>6) & 1;
2935:
2936: if (cur_inst & (1<<15)) {
2937: /* Write D1 */
2938: retour = dsp_calc_ea(ea_mode, &addr);
2939: if (retour) {
1.1.1.4 root 2940: value = addr;
1.1 root 2941: } else {
1.1.1.4 root 2942: value = read_memory(memspace, addr);
1.1 root 2943: }
1.1.1.4 root 2944: value &= BITMASK(registers_mask[numreg]);
2945: dsp_write_reg(numreg, value);
1.1 root 2946: } else {
2947: /* Read S1 */
1.1.1.4 root 2948: dsp_calc_ea(ea_mode, &addr);
2949: if (numreg == DSP_REG_SSH) {
2950: dsp_stack_pop(&value, &dummy);
2951: }
2952: else {
1.1.1.6 root 2953: value = dsp_core.registers[numreg];
1.1.1.4 root 2954: }
2955: write_memory(memspace, addr, value);
1.1 root 2956: }
2957: }
2958:
1.1.1.4 root 2959: static void dsp_movem_aa(void)
1.1 root 2960: {
1.1.1.4 root 2961: Uint32 numreg, addr, value, dummy;
1.1 root 2962:
2963: numreg = cur_inst & BITMASK(6);
1.1.1.4 root 2964: addr = (cur_inst>>8) & BITMASK(6);
1.1 root 2965:
1.1.1.4 root 2966: if (cur_inst & (1<<15)) {
2967: /* Write D */
2968: value = read_memory_p(addr);
2969: value &= BITMASK(registers_mask[numreg]);
2970: dsp_write_reg(numreg, value);
1.1 root 2971: } else {
1.1.1.4 root 2972: /* Read S */
2973: if (numreg == DSP_REG_SSH) {
2974: dsp_stack_pop(&value, &dummy);
2975: }
2976: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
2977: dsp_pm_read_accu24(numreg, &value);
2978: }
2979: else {
1.1.1.6 root 2980: value = dsp_core.registers[numreg];
1.1.1.4 root 2981: }
2982: write_memory(DSP_SPACE_P, addr, value);
2983: }
1.1 root 2984:
1.1.1.6 root 2985: dsp_core.instr_cycle += 4;
1.1.1.4 root 2986: }
2987:
2988: static void dsp_movem_ea(void)
2989: {
2990: Uint32 numreg, addr, ea_mode, value, dummy;
2991:
2992: numreg = cur_inst & BITMASK(6);
2993: ea_mode = (cur_inst>>8) & BITMASK(6);
2994: dsp_calc_ea(ea_mode, &addr);
1.1 root 2995:
2996: if (cur_inst & (1<<15)) {
2997: /* Write D */
1.1.1.4 root 2998: value = read_memory_p(addr);
2999: value &= BITMASK(registers_mask[numreg]);
3000: dsp_write_reg(numreg, value);
1.1 root 3001: } else {
3002: /* Read S */
1.1.1.4 root 3003: if (numreg == DSP_REG_SSH) {
3004: dsp_stack_pop(&value, &dummy);
3005: }
3006: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1 root 3007: dsp_pm_read_accu24(numreg, &value);
1.1.1.4 root 3008: }
3009: else {
1.1.1.6 root 3010: value = dsp_core.registers[numreg];
1.1 root 3011: }
3012: write_memory(DSP_SPACE_P, addr, value);
3013: }
3014:
1.1.1.6 root 3015: dsp_core.instr_cycle += 4;
1.1 root 3016: }
3017:
3018: static void dsp_movep_0(void)
3019: {
3020: /* S,x:pp */
3021: /* x:pp,D */
3022: /* S,y:pp */
3023: /* y:pp,D */
3024:
1.1.1.4 root 3025: Uint32 addr, memspace, numreg, value, dummy;
1.1 root 3026:
3027: addr = 0xffc0 + (cur_inst & BITMASK(6));
3028: memspace = (cur_inst>>16) & 1;
3029: numreg = (cur_inst>>8) & BITMASK(6);
3030:
3031: if (cur_inst & (1<<15)) {
3032: /* Write pp */
3033: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
3034: dsp_pm_read_accu24(numreg, &value);
1.1.1.4 root 3035: }
3036: else if (numreg == DSP_REG_SSH) {
3037: dsp_stack_pop(&value, &dummy);
3038: }
3039: else {
1.1.1.6 root 3040: value = dsp_core.registers[numreg];
1.1 root 3041: }
3042: write_memory(memspace, addr, value);
3043: } else {
3044: /* Read pp */
3045: value = read_memory(memspace, addr);
1.1.1.4 root 3046: value &= BITMASK(registers_mask[numreg]);
3047: dsp_write_reg(numreg, value);
1.1 root 3048: }
1.1.1.4 root 3049:
1.1.1.6 root 3050: dsp_core.instr_cycle += 2;
1.1 root 3051: }
3052:
3053: static void dsp_movep_1(void)
3054: {
3055: /* p:ea,x:pp */
3056: /* x:pp,p:ea */
3057: /* p:ea,y:pp */
3058: /* y:pp,p:ea */
3059:
1.1.1.2 root 3060: Uint32 xyaddr, memspace, paddr;
1.1 root 3061:
3062: xyaddr = 0xffc0 + (cur_inst & BITMASK(6));
3063: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &paddr);
3064: memspace = (cur_inst>>16) & 1;
3065:
3066: if (cur_inst & (1<<15)) {
3067: /* Write pp */
1.1.1.4 root 3068: write_memory(memspace, xyaddr, read_memory_p(paddr));
1.1 root 3069: } else {
3070: /* Read pp */
3071: write_memory(DSP_SPACE_P, paddr, read_memory(memspace, xyaddr));
3072: }
1.1.1.4 root 3073:
1.1.1.7 ! root 3074: /* Movep is 4 cycles, but according to the motorola doc, */
! 3075: /* movep from p memory to x or y peripheral memory takes */
! 3076: /* 2 more cycles, so +4 cycles at total */
! 3077: dsp_core.instr_cycle += 4;
1.1 root 3078: }
3079:
1.1.1.4 root 3080: static void dsp_movep_23(void)
1.1 root 3081: {
3082: /* x:ea,x:pp */
3083: /* y:ea,x:pp */
3084: /* #xxxxxx,x:pp */
3085: /* x:pp,x:ea */
3086: /* x:pp,y:pp */
3087: /* x:ea,y:pp */
3088: /* y:ea,y:pp */
3089: /* #xxxxxx,y:pp */
3090: /* y:pp,y:ea */
3091: /* y:pp,x:ea */
3092:
1.1.1.2 root 3093: Uint32 addr, peraddr, easpace, perspace, ea_mode;
1.1 root 3094: int retour;
3095:
3096: peraddr = 0xffc0 + (cur_inst & BITMASK(6));
3097: perspace = (cur_inst>>16) & 1;
3098:
3099: ea_mode = (cur_inst>>8) & BITMASK(6);
3100: easpace = (cur_inst>>6) & 1;
3101: retour = dsp_calc_ea(ea_mode, &addr);
3102:
3103: if (cur_inst & (1<<15)) {
3104: /* Write pp */
3105:
3106: if (retour) {
3107: write_memory(perspace, peraddr, addr);
3108: } else {
3109: write_memory(perspace, peraddr, read_memory(easpace, addr));
3110: }
3111: } else {
3112: /* Read pp */
3113: write_memory(easpace, addr, read_memory(perspace, peraddr));
3114: }
1.1.1.4 root 3115:
1.1.1.6 root 3116: dsp_core.instr_cycle += 2;
1.1 root 3117: }
3118:
3119: static void dsp_norm(void)
3120: {
1.1.1.2 root 3121: Uint32 cursr,cur_e, cur_euz, dest[3], numreg, rreg;
3122: Uint16 newsr;
1.1 root 3123:
1.1.1.6 root 3124: cursr = dsp_core.registers[DSP_REG_SR];
1.1 root 3125: cur_e = (cursr>>DSP_SR_E) & 1; /* E */
3126: cur_euz = ~cur_e; /* (not E) and U and (not Z) */
3127: cur_euz &= (cursr>>DSP_SR_U) & 1;
3128: cur_euz &= ~((cursr>>DSP_SR_Z) & 1);
3129: cur_euz &= 1;
3130:
3131: numreg = (cur_inst>>3) & 1;
1.1.1.6 root 3132: dest[0] = dsp_core.registers[DSP_REG_A2+numreg];
3133: dest[1] = dsp_core.registers[DSP_REG_A1+numreg];
3134: dest[2] = dsp_core.registers[DSP_REG_A0+numreg];
1.1 root 3135: rreg = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3136:
3137: if (cur_euz) {
3138: newsr = dsp_asl56(dest);
1.1.1.6 root 3139: --dsp_core.registers[rreg];
3140: dsp_core.registers[rreg] &= BITMASK(16);
1.1 root 3141: } else if (cur_e) {
3142: newsr = dsp_asr56(dest);
1.1.1.6 root 3143: ++dsp_core.registers[rreg];
3144: dsp_core.registers[rreg] &= BITMASK(16);
1.1 root 3145: } else {
3146: newsr = 0;
3147: }
3148:
1.1.1.6 root 3149: dsp_core.registers[DSP_REG_A2+numreg] = dest[0];
3150: dsp_core.registers[DSP_REG_A1+numreg] = dest[1];
3151: dsp_core.registers[DSP_REG_A0+numreg] = dest[2];
1.1.1.2 root 3152:
1.1.1.6 root 3153: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 3154:
1.1.1.6 root 3155: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
3156: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 3157: }
3158:
3159: static void dsp_ori(void)
3160: {
1.1.1.2 root 3161: Uint32 regnum, value;
1.1 root 3162:
3163: value = (cur_inst >> 8) & BITMASK(8);
3164: regnum = cur_inst & BITMASK(2);
3165: switch(regnum) {
3166: case 0:
3167: /* mr */
1.1.1.6 root 3168: dsp_core.registers[DSP_REG_SR] |= value<<8;
1.1 root 3169: break;
3170: case 1:
3171: /* ccr */
1.1.1.6 root 3172: dsp_core.registers[DSP_REG_SR] |= value;
1.1 root 3173: break;
3174: case 2:
3175: /* omr */
1.1.1.6 root 3176: dsp_core.registers[DSP_REG_OMR] |= value;
1.1 root 3177: break;
3178: }
3179: }
3180:
1.1.1.3 root 3181: /*
3182: REP instruction parameter encoding
3183:
3184: xxxxxxxx 00xxxxxx 0xxxxxxx aa
3185: xxxxxxxx 01xxxxxx 0xxxxxxx ea
3186: xxxxxxxx YYxxxxxx 1xxxxxxx imm
3187: xxxxxxxx 11xxxxxx 0xxxxxxx reg
3188: */
3189:
3190: static void dsp_rep_aa(void)
1.1 root 3191: {
3192: /* x:aa */
3193: /* y:aa */
1.1.1.6 root 3194: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3195: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3196: dsp_core.loop_rep = 1; /* We are now running rep */
1.1 root 3197:
1.1.1.6 root 3198: dsp_core.registers[DSP_REG_LC]=read_memory((cur_inst>>6) & 1,(cur_inst>>8) & BITMASK(6));
1.1.1.4 root 3199:
1.1.1.6 root 3200: dsp_core.instr_cycle += 2;
1.1 root 3201: }
3202:
1.1.1.3 root 3203: static void dsp_rep_imm(void)
1.1 root 3204: {
3205: /* #xxx */
3206:
1.1.1.6 root 3207: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3208: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3209: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3210:
1.1.1.6 root 3211: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
1.1.1.3 root 3212: + ((cur_inst & BITMASK(4))<<8);
1.1.1.4 root 3213:
1.1.1.6 root 3214: dsp_core.instr_cycle += 2;
1.1 root 3215: }
3216:
1.1.1.3 root 3217: static void dsp_rep_ea(void)
1.1 root 3218: {
1.1.1.2 root 3219: Uint32 value;
1.1 root 3220:
3221: /* x:ea */
3222: /* y:ea */
3223:
1.1.1.6 root 3224: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3225: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3226: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3227:
1.1 root 3228: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&value);
1.1.1.6 root 3229: dsp_core.registers[DSP_REG_LC]= read_memory((cur_inst>>6) & 1, value);
1.1.1.4 root 3230:
1.1.1.6 root 3231: dsp_core.instr_cycle += 2;
1.1 root 3232: }
3233:
1.1.1.3 root 3234: static void dsp_rep_reg(void)
1.1 root 3235: {
1.1.1.2 root 3236: Uint32 numreg;
1.1 root 3237:
3238: /* R */
3239:
1.1.1.6 root 3240: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3241: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3242: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3243:
1.1 root 3244: numreg = (cur_inst>>8) & BITMASK(6);
3245: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.6 root 3246: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
1.1 root 3247: } else {
1.1.1.6 root 3248: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
1.1 root 3249: }
1.1.1.6 root 3250: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.4 root 3251:
1.1.1.6 root 3252: dsp_core.instr_cycle += 2;
1.1 root 3253: }
3254:
3255: static void dsp_reset(void)
3256: {
3257: /* Reset external peripherals */
1.1.1.6 root 3258: dsp_core.instr_cycle += 2;
1.1 root 3259: }
3260:
3261: static void dsp_rti(void)
3262: {
1.1.1.2 root 3263: Uint32 newpc = 0, newsr = 0;
1.1 root 3264:
3265: dsp_stack_pop(&newpc, &newsr);
1.1.1.6 root 3266: dsp_core.pc = newpc;
3267: dsp_core.registers[DSP_REG_SR] = newsr;
1.1 root 3268: cur_inst_len = 0;
1.1.1.4 root 3269:
1.1.1.6 root 3270: dsp_core.instr_cycle += 2;
1.1 root 3271: }
3272:
3273: static void dsp_rts(void)
3274: {
1.1.1.2 root 3275: Uint32 newpc = 0, newsr;
1.1 root 3276:
3277: dsp_stack_pop(&newpc, &newsr);
1.1.1.6 root 3278: dsp_core.pc = newpc;
1.1 root 3279: cur_inst_len = 0;
1.1.1.4 root 3280:
1.1.1.6 root 3281: dsp_core.instr_cycle += 2;
1.1 root 3282: }
3283:
3284: static void dsp_stop(void)
3285: {
1.1.1.6 root 3286: LOG_TRACE(TRACE_DSP_STATE, "Dsp: STOP instruction\n");
1.1 root 3287: }
3288:
3289: static void dsp_swi(void)
3290: {
3291: /* Raise interrupt p:0x0006 */
1.1.1.6 root 3292: dsp_core.instr_cycle += 6;
1.1 root 3293: }
3294:
3295: static void dsp_tcc(void)
3296: {
1.1.1.6 root 3297: Uint32 cc_code, regsrc1, regdest1;
1.1.1.2 root 3298: Uint32 regsrc2, regdest2;
1.1.1.6 root 3299: Uint32 val0, val1, val2;
3300:
1.1 root 3301: cc_code = (cur_inst>>12) & BITMASK(4);
3302:
3303: if (dsp_calc_cc(cc_code)) {
3304: regsrc1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][0];
1.1.1.2 root 3305: regdest1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][1];
1.1 root 3306:
3307: /* Read S1 */
1.1.1.7 ! root 3308: if (regsrc1 == DSP_REG_A) {
! 3309: val0 = dsp_core.registers[DSP_REG_A0];
! 3310: val1 = dsp_core.registers[DSP_REG_A1];
! 3311: val2 = dsp_core.registers[DSP_REG_A2];
! 3312: }
! 3313: else if (regsrc1 == DSP_REG_B) {
! 3314: val0 = dsp_core.registers[DSP_REG_B0];
! 3315: val1 = dsp_core.registers[DSP_REG_B1];
! 3316: val2 = dsp_core.registers[DSP_REG_B2];
! 3317: }
! 3318: else {
1.1.1.6 root 3319: val0 = 0;
3320: val1 = dsp_core.registers[regsrc1];
1.1.1.7 ! root 3321: val2 = val1 & (1<<23) ? 0xff : 0x0;
1.1 root 3322: }
3323:
3324: /* Write D1 */
1.1.1.7 ! root 3325: if (regdest1 == DSP_REG_A) {
! 3326: dsp_core.registers[DSP_REG_A2] = val2;
! 3327: dsp_core.registers[DSP_REG_A1] = val1;
! 3328: dsp_core.registers[DSP_REG_A0] = val0;
! 3329: }
! 3330: else {
! 3331: dsp_core.registers[DSP_REG_B2] = val2;
! 3332: dsp_core.registers[DSP_REG_B1] = val1;
! 3333: dsp_core.registers[DSP_REG_B0] = val0;
! 3334: }
1.1 root 3335:
3336: /* S2,D2 transfer */
3337: if (cur_inst & (1<<16)) {
1.1.1.2 root 3338: regsrc2 = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3339: regdest2 = DSP_REG_R0+(cur_inst & BITMASK(3));
1.1 root 3340:
1.1.1.6 root 3341: dsp_core.registers[regdest2] = dsp_core.registers[regsrc2];
1.1 root 3342: }
3343: }
3344: }
3345:
3346: static void dsp_wait(void)
3347: {
1.1.1.6 root 3348: LOG_TRACE(TRACE_DSP_STATE, "Dsp: WAIT instruction\n");
1.1 root 3349: }
3350:
1.1.1.2 root 3351: static int dsp_pm_read_accu24(int numreg, Uint32 *dest)
1.1 root 3352: {
1.1.1.4 root 3353: Uint32 scaling, value, reg;
1.1.1.7 ! root 3354: int got_limited = 0;
1.1 root 3355:
3356: /* Read an accumulator, stores it limited */
3357:
1.1.1.6 root 3358: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
1.1.1.4 root 3359: reg = numreg & 1;
1.1 root 3360:
1.1.1.6 root 3361: value = (dsp_core.registers[DSP_REG_A2+reg]) << 24;
3362: value += dsp_core.registers[DSP_REG_A1+reg];
1.1 root 3363:
3364: switch(scaling) {
3365: case 0:
1.1.1.4 root 3366: /* No scaling */
3367: break;
3368: case 1:
3369: /* scaling down */
3370: value >>= 1;
1.1 root 3371: break;
3372: case 2:
1.1.1.4 root 3373: /* scaling up */
3374: value <<= 1;
1.1.1.6 root 3375: value |= (dsp_core.registers[DSP_REG_A0+reg]>>23) & 1;
1.1 root 3376: break;
1.1.1.4 root 3377: /* indeterminate */
3378: case 3:
3379: break;
3380: }
3381:
3382: /* limiting ? */
3383: value &= BITMASK(24);
3384:
1.1.1.6 root 3385: if (dsp_core.registers[DSP_REG_A2+reg] == 0) {
1.1.1.4 root 3386: if (value <= 0x007fffff) {
3387: /* No limiting */
3388: *dest=value;
3389: return 0;
3390: }
3391: }
3392:
1.1.1.6 root 3393: if (dsp_core.registers[DSP_REG_A2+reg] == 0xff) {
1.1.1.4 root 3394: if (value >= 0x00800000) {
3395: /* No limiting */
3396: *dest=value;
3397: return 0;
3398: }
1.1 root 3399: }
3400:
1.1.1.6 root 3401: if (dsp_core.registers[DSP_REG_A2+reg] & (1<<7)) {
1.1 root 3402: /* Limited to maximum negative value */
3403: *dest=0x00800000;
1.1.1.6 root 3404: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
1.1.1.2 root 3405: got_limited=1;
1.1 root 3406: } else {
3407: /* Limited to maximal positive value */
3408: *dest=0x007fffff;
1.1.1.6 root 3409: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
1.1.1.2 root 3410: got_limited=1;
1.1 root 3411: }
1.1.1.2 root 3412:
3413: return got_limited;
1.1 root 3414: }
3415:
3416: static void dsp_pm_0(void)
3417: {
1.1.1.6 root 3418: Uint32 memspace, numreg, addr, save_accu, save_xy0;
1.1 root 3419: /*
3420: 0000 100d 00mm mrrr S,x:ea x0,D
3421: 0000 100d 10mm mrrr S,y:ea y0,D
3422: */
3423: memspace = (cur_inst>>15) & 1;
3424: numreg = (cur_inst>>16) & 1;
1.1.1.6 root 3425: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &addr);
3426:
3427: /* Save A or B */
3428: dsp_pm_read_accu24(numreg, &save_accu);
1.1 root 3429:
1.1.1.6 root 3430: /* Save X0 or Y0 */
3431: save_xy0 = dsp_core.registers[DSP_REG_X0+(memspace<<1)];
3432:
3433: /* Execute parallel instruction */
3434: opcodes_alu[cur_inst & BITMASK(8)]();
3435:
3436: /* Move [A|B] to [x|y]:ea */
3437: write_memory(memspace, addr, save_accu);
3438:
3439: /* Move [x|y]0 to [A|B] */
3440: dsp_core.registers[DSP_REG_A0+numreg] = 0;
3441: dsp_core.registers[DSP_REG_A1+numreg] = save_xy0;
1.1.1.7 ! root 3442: dsp_core.registers[DSP_REG_A2+numreg] = save_xy0 & (1<<23) ? 0xff : 0x0;
1.1 root 3443: }
3444:
3445: static void dsp_pm_1(void)
3446: {
1.1.1.6 root 3447: Uint32 memspace, numreg1, numreg2, value, xy_addr, retour, save_1, save_2;
1.1 root 3448: /*
3449: 0001 ffdf w0mm mrrr x:ea,D1 S2,D2
3450: S1,x:ea S2,D2
3451: #xxxxxx,D1 S2,D2
3452: 0001 deff w1mm mrrr S1,D1 y:ea,D2
3453: S1,D1 S2,y:ea
3454: S1,D1 #xxxxxx,D2
3455: */
3456: value = (cur_inst>>8) & BITMASK(6);
3457: retour = dsp_calc_ea(value, &xy_addr);
3458: memspace = (cur_inst>>14) & 1;
1.1.1.6 root 3459: numreg1 = numreg2 = DSP_REG_NULL;
1.1 root 3460:
3461: if (memspace) {
3462: /* Y: */
3463: switch((cur_inst>>16) & BITMASK(2)) {
1.1.1.6 root 3464: case 0: numreg1 = DSP_REG_Y0; break;
3465: case 1: numreg1 = DSP_REG_Y1; break;
3466: case 2: numreg1 = DSP_REG_A; break;
3467: case 3: numreg1 = DSP_REG_B; break;
1.1 root 3468: }
3469: } else {
3470: /* X: */
3471: switch((cur_inst>>18) & BITMASK(2)) {
1.1.1.6 root 3472: case 0: numreg1 = DSP_REG_X0; break;
3473: case 1: numreg1 = DSP_REG_X1; break;
3474: case 2: numreg1 = DSP_REG_A; break;
3475: case 3: numreg1 = DSP_REG_B; break;
1.1 root 3476: }
3477: }
3478:
3479: if (cur_inst & (1<<15)) {
3480: /* Write D1 */
1.1.1.6 root 3481: if (retour)
3482: save_1 = xy_addr;
3483: else
3484: save_1 = read_memory(memspace, xy_addr);
1.1 root 3485: } else {
3486: /* Read S1 */
1.1.1.6 root 3487: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
3488: dsp_pm_read_accu24(numreg1, &save_1);
3489: else
3490: save_1 = dsp_core.registers[numreg1];
1.1 root 3491: }
1.1.1.6 root 3492:
1.1 root 3493: /* S2 */
3494: if (memspace) {
3495: /* Y: */
1.1.1.6 root 3496: numreg2 = DSP_REG_A + ((cur_inst>>19) & 1);
1.1 root 3497: } else {
3498: /* X: */
1.1.1.6 root 3499: numreg2 = DSP_REG_A + ((cur_inst>>17) & 1);
1.1 root 3500: }
1.1.1.6 root 3501: dsp_pm_read_accu24(numreg2, &save_2);
1.1 root 3502:
1.1.1.6 root 3503:
3504: /* Execute parallel instruction */
3505: opcodes_alu[cur_inst & BITMASK(8)]();
3506:
3507:
3508: /* Write parallel move values */
3509: if (cur_inst & (1<<15)) {
3510: /* Write D1 */
3511: if (numreg1 == DSP_REG_A) {
3512: dsp_core.registers[DSP_REG_A0] = 0x0;
3513: dsp_core.registers[DSP_REG_A1] = save_1;
3514: dsp_core.registers[DSP_REG_A2] = save_1 & (1<<23) ? 0xff : 0x0;
3515: }
3516: else if (numreg1 == DSP_REG_B) {
3517: dsp_core.registers[DSP_REG_B0] = 0x0;
3518: dsp_core.registers[DSP_REG_B1] = save_1;
3519: dsp_core.registers[DSP_REG_B2] = save_1 & (1<<23) ? 0xff : 0x0;
3520: }
3521: else {
3522: } dsp_core.registers[numreg1] = save_1;
3523: } else {
3524: /* Read S1 */
3525: write_memory(memspace, xy_addr, save_1);
3526: }
3527:
3528: /* S2 -> D2 */
1.1 root 3529: if (memspace) {
3530: /* Y: */
1.1.1.6 root 3531: numreg2 = DSP_REG_X0 + ((cur_inst>>18) & 1);
1.1 root 3532: } else {
3533: /* X: */
1.1.1.6 root 3534: numreg2 = DSP_REG_Y0 + ((cur_inst>>16) & 1);
1.1 root 3535: }
1.1.1.6 root 3536: dsp_core.registers[numreg2] = save_2;
1.1 root 3537: }
3538:
3539: static void dsp_pm_2(void)
3540: {
1.1.1.2 root 3541: Uint32 dummy;
1.1 root 3542: /*
3543: 0010 0000 0000 0000 nop
3544: 0010 0000 010m mrrr R update
3545: 0010 00ee eeed dddd S,D
3546: 001d dddd iiii iiii #xx,D
3547: */
1.1.1.4 root 3548: if ((cur_inst & 0xffff00) == 0x200000) {
1.1.1.6 root 3549: /* Execute parallel instruction */
3550: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3551: return;
3552: }
3553:
1.1.1.4 root 3554: if ((cur_inst & 0xffe000) == 0x204000) {
1.1 root 3555: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &dummy);
1.1.1.6 root 3556: /* Execute parallel instruction */
3557: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3558: return;
3559: }
3560:
1.1.1.4 root 3561: if ((cur_inst & 0xfc0000) == 0x200000) {
1.1 root 3562: dsp_pm_2_2();
3563: return;
3564: }
3565:
3566: dsp_pm_3();
3567: }
3568:
3569: static void dsp_pm_2_2(void)
3570: {
3571: /*
3572: 0010 00ee eeed dddd S,D
3573: */
1.1.1.6 root 3574: Uint32 srcreg, dstreg, save_reg;
1.1 root 3575:
3576: srcreg = (cur_inst >> 13) & BITMASK(5);
3577: dstreg = (cur_inst >> 8) & BITMASK(5);
3578:
1.1.1.6 root 3579: if ((srcreg == DSP_REG_A) || (srcreg == DSP_REG_B))
3580: /* Accu to register: limited 24 bits */
3581: dsp_pm_read_accu24(srcreg, &save_reg);
3582: else
3583: save_reg = dsp_core.registers[srcreg];
3584:
3585: /* Execute parallel instruction */
3586: opcodes_alu[cur_inst & BITMASK(8)]();
3587:
3588: /* Write reg */
3589: if (dstreg == DSP_REG_A) {
3590: dsp_core.registers[DSP_REG_A0] = 0x0;
3591: dsp_core.registers[DSP_REG_A1] = save_reg;
3592: dsp_core.registers[DSP_REG_A2] = save_reg & (1<<23) ? 0xff : 0x0;
3593: }
3594: else if (dstreg == DSP_REG_B) {
3595: dsp_core.registers[DSP_REG_B0] = 0x0;
3596: dsp_core.registers[DSP_REG_B1] = save_reg;
3597: dsp_core.registers[DSP_REG_B2] = save_reg & (1<<23) ? 0xff : 0x0;
3598: }
3599: else {
3600: dsp_core.registers[dstreg] = save_reg & BITMASK(registers_mask[dstreg]);
1.1 root 3601: }
3602: }
3603:
3604: static void dsp_pm_3(void)
3605: {
1.1.1.6 root 3606: Uint32 dstreg, srcvalue;
1.1 root 3607: /*
3608: 001d dddd iiii iiii #xx,R
3609: */
1.1.1.6 root 3610:
3611: /* Execute parallel instruction */
3612: opcodes_alu[cur_inst & BITMASK(8)]();
3613:
3614: /* Write reg */
3615: dstreg = (cur_inst >> 16) & BITMASK(5);
1.1 root 3616: srcvalue = (cur_inst >> 8) & BITMASK(8);
3617:
1.1.1.6 root 3618: switch(dstreg) {
1.1 root 3619: case DSP_REG_X0:
3620: case DSP_REG_X1:
3621: case DSP_REG_Y0:
3622: case DSP_REG_Y1:
3623: case DSP_REG_A:
3624: case DSP_REG_B:
3625: srcvalue <<= 16;
3626: break;
3627: }
3628:
1.1.1.6 root 3629: if (dstreg == DSP_REG_A) {
3630: dsp_core.registers[DSP_REG_A0] = 0x0;
3631: dsp_core.registers[DSP_REG_A1] = srcvalue;
3632: dsp_core.registers[DSP_REG_A2] = srcvalue & (1<<23) ? 0xff : 0x0;
3633: }
3634: else if (dstreg == DSP_REG_B) {
3635: dsp_core.registers[DSP_REG_B0] = 0x0;
3636: dsp_core.registers[DSP_REG_B1] = srcvalue;
3637: dsp_core.registers[DSP_REG_B2] = srcvalue & (1<<23) ? 0xff : 0x0;
3638: }
3639: else {
3640: dsp_core.registers[dstreg] = srcvalue & BITMASK(registers_mask[dstreg]);
1.1 root 3641: }
3642: }
3643:
3644: static void dsp_pm_4(void)
3645: {
3646: /*
1.1.1.4 root 3647: 0100 l0ll w0aa aaaa l:aa,D
1.1 root 3648: S,l:aa
1.1.1.4 root 3649: 0100 l0ll w1mm mrrr l:ea,D
1.1 root 3650: S,l:ea
1.1.1.4 root 3651: 01dd 0ddd w0aa aaaa x:aa,D
1.1 root 3652: S,x:aa
1.1.1.4 root 3653: 01dd 0ddd w1mm mrrr x:ea,D
1.1 root 3654: S,x:ea
3655: #xxxxxx,D
1.1.1.4 root 3656: 01dd 1ddd w0aa aaaa y:aa,D
1.1 root 3657: S,y:aa
1.1.1.4 root 3658: 01dd 1ddd w1mm mrrr y:ea,D
1.1 root 3659: S,y:ea
3660: #xxxxxx,D
3661: */
1.1.1.4 root 3662: if ((cur_inst & 0xf40000)==0x400000) {
3663: dsp_pm_4x();
1.1 root 3664: return;
3665: }
3666:
3667: dsp_pm_5();
3668: }
3669:
1.1.1.4 root 3670: static void dsp_pm_4x(void)
1.1 root 3671: {
1.1.1.6 root 3672: Uint32 value, numreg, l_addr, save_lx, save_ly;
1.1 root 3673: /*
1.1.1.4 root 3674: 0100 l0ll w0aa aaaa l:aa,D
3675: S,l:aa
3676: 0100 l0ll w1mm mrrr l:ea,D
3677: S,l:ea
1.1 root 3678: */
1.1.1.4 root 3679: value = (cur_inst>>8) & BITMASK(6);
3680: if (cur_inst & (1<<14)) {
3681: dsp_calc_ea(value, &l_addr);
3682: } else {
3683: l_addr = value;
3684: }
3685:
1.1 root 3686: numreg = (cur_inst>>16) & BITMASK(2);
3687: numreg |= (cur_inst>>17) & (1<<2);
3688:
1.1.1.4 root 3689: /* 2 more cycles are needed if address is in external memory */
3690: if (l_addr>=0x200) {
1.1.1.6 root 3691: dsp_core.instr_cycle += 2;
1.1.1.4 root 3692: }
3693:
1.1 root 3694: if (cur_inst & (1<<15)) {
3695: /* Write D */
1.1.1.6 root 3696: save_lx = read_memory(DSP_SPACE_X,l_addr);
3697: save_ly = read_memory(DSP_SPACE_Y,l_addr);
3698: }
3699: else {
3700: /* Read S */
1.1.1.4 root 3701: switch(numreg) {
3702: case 0:
3703: /* A10 */
1.1.1.6 root 3704: save_lx = dsp_core.registers[DSP_REG_A1];
3705: save_ly = dsp_core.registers[DSP_REG_A0];
1.1.1.4 root 3706: break;
3707: case 1:
3708: /* B10 */
1.1.1.6 root 3709: save_lx = dsp_core.registers[DSP_REG_B1];
3710: save_ly = dsp_core.registers[DSP_REG_B0];
1.1.1.4 root 3711: break;
3712: case 2:
3713: /* X */
1.1.1.6 root 3714: save_lx = dsp_core.registers[DSP_REG_X1];
3715: save_ly = dsp_core.registers[DSP_REG_X0];
1.1.1.4 root 3716: break;
3717: case 3:
3718: /* Y */
1.1.1.6 root 3719: save_lx = dsp_core.registers[DSP_REG_Y1];
3720: save_ly = dsp_core.registers[DSP_REG_Y0];
1.1.1.4 root 3721: break;
3722: case 4:
3723: /* A */
1.1.1.6 root 3724: if (dsp_pm_read_accu24(DSP_REG_A, &save_lx)) {
3725: /* Was limited, set lower part */
3726: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3727: } else {
3728: /* Not limited */
3729: save_ly = dsp_core.registers[DSP_REG_A0];
3730: }
1.1.1.4 root 3731: break;
3732: case 5:
3733: /* B */
1.1.1.6 root 3734: if (dsp_pm_read_accu24(DSP_REG_B, &save_lx)) {
3735: /* Was limited, set lower part */
3736: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3737: } else {
3738: /* Not limited */
3739: save_ly = dsp_core.registers[DSP_REG_B0];
3740: }
1.1.1.4 root 3741: break;
3742: case 6:
3743: /* AB */
1.1.1.6 root 3744: dsp_pm_read_accu24(DSP_REG_A, &save_lx);
3745: dsp_pm_read_accu24(DSP_REG_B, &save_ly);
1.1.1.4 root 3746: break;
3747: case 7:
3748: /* BA */
1.1.1.6 root 3749: dsp_pm_read_accu24(DSP_REG_B, &save_lx);
3750: dsp_pm_read_accu24(DSP_REG_A, &save_ly);
1.1.1.4 root 3751: break;
1.1 root 3752: }
1.1.1.6 root 3753: }
1.1 root 3754:
1.1.1.6 root 3755: /* Execute parallel instruction */
3756: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3757:
1.1.1.6 root 3758:
3759: if (cur_inst & (1<<15)) {
3760: /* Write D */
1.1.1.4 root 3761: switch(numreg) {
1.1.1.6 root 3762: case 0: /* A10 */
3763: dsp_core.registers[DSP_REG_A1] = save_lx;
3764: dsp_core.registers[DSP_REG_A0] = save_ly;
1.1.1.4 root 3765: break;
1.1.1.6 root 3766: case 1: /* B10 */
3767: dsp_core.registers[DSP_REG_B1] = save_lx;
3768: dsp_core.registers[DSP_REG_B0] = save_ly;
1.1.1.4 root 3769: break;
1.1.1.6 root 3770: case 2: /* X */
3771: dsp_core.registers[DSP_REG_X1] = save_lx;
3772: dsp_core.registers[DSP_REG_X0] = save_ly;
1.1.1.4 root 3773: break;
1.1.1.6 root 3774: case 3: /* Y */
3775: dsp_core.registers[DSP_REG_Y1] = save_lx;
3776: dsp_core.registers[DSP_REG_Y0] = save_ly;
1.1.1.4 root 3777: break;
1.1.1.6 root 3778: case 4: /* A */
3779: dsp_core.registers[DSP_REG_A0] = save_ly;
3780: dsp_core.registers[DSP_REG_A1] = save_lx;
3781: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
1.1.1.4 root 3782: break;
1.1.1.6 root 3783: case 5: /* B */
3784: dsp_core.registers[DSP_REG_B0] = save_ly;
3785: dsp_core.registers[DSP_REG_B1] = save_lx;
3786: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
1.1.1.4 root 3787: break;
1.1.1.6 root 3788: case 6: /* AB */
3789: dsp_core.registers[DSP_REG_A0] = 0;
3790: dsp_core.registers[DSP_REG_A1] = save_lx;
3791: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
3792: dsp_core.registers[DSP_REG_B0] = 0;
3793: dsp_core.registers[DSP_REG_B1] = save_ly;
3794: dsp_core.registers[DSP_REG_B2] = save_ly & (1<<23) ? 0xff : 0;
1.1.1.4 root 3795: break;
1.1.1.6 root 3796: case 7: /* BA */
3797: dsp_core.registers[DSP_REG_B0] = 0;
3798: dsp_core.registers[DSP_REG_B1] = save_lx;
3799: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
3800: dsp_core.registers[DSP_REG_A0] = 0;
3801: dsp_core.registers[DSP_REG_A1] = save_ly;
3802: dsp_core.registers[DSP_REG_A2] = save_ly & (1<<23) ? 0xff : 0;
1.1.1.4 root 3803: break;
1.1 root 3804: }
1.1.1.6 root 3805: }
3806: else {
3807: /* Read S */
3808: write_memory(DSP_SPACE_X, l_addr, save_lx);
3809: write_memory(DSP_SPACE_Y, l_addr, save_ly);
1.1 root 3810: }
3811: }
3812:
3813: static void dsp_pm_5(void)
3814: {
1.1.1.2 root 3815: Uint32 memspace, numreg, value, xy_addr, retour;
1.1 root 3816: /*
1.1.1.4 root 3817: 01dd 0ddd w0aa aaaa x:aa,D
1.1 root 3818: S,x:aa
1.1.1.4 root 3819: 01dd 0ddd w1mm mrrr x:ea,D
1.1 root 3820: S,x:ea
3821: #xxxxxx,D
1.1.1.4 root 3822: 01dd 1ddd w0aa aaaa y:aa,D
1.1 root 3823: S,y:aa
1.1.1.4 root 3824: 01dd 1ddd w1mm mrrr y:ea,D
1.1 root 3825: S,y:ea
3826: #xxxxxx,D
3827: */
3828:
3829: value = (cur_inst>>8) & BITMASK(6);
3830:
3831: if (cur_inst & (1<<14)) {
3832: retour = dsp_calc_ea(value, &xy_addr);
3833: } else {
3834: xy_addr = value;
3835: retour = 0;
3836: }
3837:
3838: memspace = (cur_inst>>19) & 1;
3839: numreg = (cur_inst>>16) & BITMASK(3);
3840: numreg |= (cur_inst>>17) & (BITMASK(2)<<3);
3841:
3842: if (cur_inst & (1<<15)) {
3843: /* Write D */
1.1.1.6 root 3844: if (retour)
1.1 root 3845: value = xy_addr;
1.1.1.6 root 3846: else
1.1 root 3847: value = read_memory(memspace, xy_addr);
1.1.1.6 root 3848: }
3849: else {
1.1 root 3850: /* Read S */
1.1.1.6 root 3851: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B))
3852: dsp_pm_read_accu24(numreg, &value);
3853: else
3854: value = dsp_core.registers[numreg];
3855: }
1.1 root 3856:
3857:
1.1.1.6 root 3858: /* Execute parallel instruction */
3859: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3860:
1.1.1.6 root 3861: if (cur_inst & (1<<15)) {
3862: /* Write D */
3863: if (numreg == DSP_REG_A) {
3864: dsp_core.registers[DSP_REG_A0] = 0x0;
3865: dsp_core.registers[DSP_REG_A1] = value;
3866: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
3867: }
3868: else if (numreg == DSP_REG_B) {
3869: dsp_core.registers[DSP_REG_B0] = 0x0;
3870: dsp_core.registers[DSP_REG_B1] = value;
3871: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
3872: }
3873: else {
3874: dsp_core.registers[numreg] = value & BITMASK(registers_mask[numreg]);
3875: }
3876: }
3877: else {
1.1.1.7 ! root 3878: /* Read S */
1.1.1.6 root 3879: write_memory(memspace, xy_addr, value);
1.1 root 3880: }
3881: }
3882:
3883: static void dsp_pm_8(void)
3884: {
1.1.1.2 root 3885: Uint32 ea1, ea2;
3886: Uint32 numreg1, numreg2;
1.1.1.6 root 3887: Uint32 save_reg1, save_reg2, x_addr, y_addr;
1.1 root 3888: /*
1.1.1.4 root 3889: 1wmm eeff WrrM MRRR x:ea,D1 y:ea,D2
1.1 root 3890: x:ea,D1 S2,y:ea
3891: S1,x:ea y:ea,D2
3892: S1,x:ea S2,y:ea
3893: */
3894: numreg1 = numreg2 = DSP_REG_NULL;
3895:
3896: ea1 = (cur_inst>>8) & BITMASK(5);
3897: if ((ea1>>3) == 0) {
3898: ea1 |= (1<<5);
3899: }
3900: ea2 = (cur_inst>>13) & BITMASK(2);
3901: ea2 |= (cur_inst>>17) & (BITMASK(2)<<3);
3902: if ((ea1 & (1<<2))==0) {
3903: ea2 |= 1<<2;
3904: }
3905: if ((ea2>>3) == 0) {
3906: ea2 |= (1<<5);
3907: }
3908:
1.1.1.4 root 3909: dsp_calc_ea(ea1, &x_addr);
3910: dsp_calc_ea(ea2, &y_addr);
3911:
3912: /* 2 more cycles are needed if X:address1 and Y:address2 are both in external memory */
3913: if ((x_addr>=0x200) && (y_addr>=0x200)) {
1.1.1.6 root 3914: dsp_core.instr_cycle += 2;
1.1.1.4 root 3915: }
1.1 root 3916:
3917: switch((cur_inst>>18) & BITMASK(2)) {
3918: case 0: numreg1=DSP_REG_X0; break;
3919: case 1: numreg1=DSP_REG_X1; break;
3920: case 2: numreg1=DSP_REG_A; break;
3921: case 3: numreg1=DSP_REG_B; break;
3922: }
3923: switch((cur_inst>>16) & BITMASK(2)) {
3924: case 0: numreg2=DSP_REG_Y0; break;
3925: case 1: numreg2=DSP_REG_Y1; break;
3926: case 2: numreg2=DSP_REG_A; break;
3927: case 3: numreg2=DSP_REG_B; break;
3928: }
3929:
3930: if (cur_inst & (1<<15)) {
3931: /* Write D1 */
1.1.1.6 root 3932: save_reg1 = read_memory(DSP_SPACE_X, x_addr);
1.1 root 3933: } else {
3934: /* Read S1 */
1.1.1.6 root 3935: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
3936: dsp_pm_read_accu24(numreg1, &save_reg1);
3937: else
3938: save_reg1 = dsp_core.registers[numreg1];
1.1 root 3939: }
3940:
3941: if (cur_inst & (1<<22)) {
3942: /* Write D2 */
1.1.1.6 root 3943: save_reg2 = read_memory(DSP_SPACE_Y, y_addr);
1.1 root 3944: } else {
3945: /* Read S2 */
1.1.1.6 root 3946: if ((numreg2==DSP_REG_A) || (numreg2==DSP_REG_B))
3947: dsp_pm_read_accu24(numreg2, &save_reg2);
3948: else
3949: save_reg2 = dsp_core.registers[numreg2];
1.1 root 3950: }
3951:
3952:
1.1.1.6 root 3953: /* Execute parallel instruction */
3954: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3955:
1.1.1.6 root 3956: /* Write first parallel move */
3957: if (cur_inst & (1<<15)) {
3958: /* Write D1 */
3959: if (numreg1 == DSP_REG_A) {
3960: dsp_core.registers[DSP_REG_A0] = 0x0;
3961: dsp_core.registers[DSP_REG_A1] = save_reg1;
3962: dsp_core.registers[DSP_REG_A2] = save_reg1 & (1<<23) ? 0xff : 0x0;
3963: }
3964: else if (numreg1 == DSP_REG_B) {
3965: dsp_core.registers[DSP_REG_B0] = 0x0;
3966: dsp_core.registers[DSP_REG_B1] = save_reg1;
3967: dsp_core.registers[DSP_REG_B2] = save_reg1 & (1<<23) ? 0xff : 0x0;
3968: }
3969: else {
3970: dsp_core.registers[numreg1] = save_reg1;
3971: }
3972: } else {
3973: /* Read S1 */
3974: write_memory(DSP_SPACE_X, x_addr, save_reg1);
3975: }
3976:
3977: /* Write second parallel move */
3978: if (cur_inst & (1<<22)) {
3979: /* Write D2 */
3980: if (numreg2 == DSP_REG_A) {
3981: dsp_core.registers[DSP_REG_A0] = 0x0;
3982: dsp_core.registers[DSP_REG_A1] = save_reg2;
3983: dsp_core.registers[DSP_REG_A2] = save_reg2 & (1<<23) ? 0xff : 0x0;
3984: }
3985: else if (numreg2 == DSP_REG_B) {
3986: dsp_core.registers[DSP_REG_B0] = 0x0;
3987: dsp_core.registers[DSP_REG_B1] = save_reg2;
3988: dsp_core.registers[DSP_REG_B2] = save_reg2 & (1<<23) ? 0xff : 0x0;
3989: }
3990: else {
3991: dsp_core.registers[numreg2] = save_reg2;
3992: }
3993: } else {
3994: /* Read S2 */
3995: write_memory(DSP_SPACE_Y, y_addr, save_reg2);
3996: }
3997: }
3998:
3999: /**********************************
4000: * 56bit arithmetic
4001: **********************************/
4002:
4003: /* source,dest[0] is 55:48 */
4004: /* source,dest[1] is 47:24 */
4005: /* source,dest[2] is 23:00 */
4006:
4007: static Uint16 dsp_abs56(Uint32 *dest)
1.1 root 4008: {
1.1.1.2 root 4009: Uint32 zerodest[3];
4010: Uint16 newsr;
1.1 root 4011:
4012: /* D=|D| */
4013:
4014: if (dest[0] & (1<<7)) {
4015: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4016:
4017: newsr = dsp_sub56(dest, zerodest);
4018:
4019: dest[0] = zerodest[0];
4020: dest[1] = zerodest[1];
4021: dest[2] = zerodest[2];
4022: } else {
4023: newsr = 0;
4024: }
4025:
4026: return newsr;
4027: }
4028:
1.1.1.2 root 4029: static Uint16 dsp_asl56(Uint32 *dest)
1.1 root 4030: {
1.1.1.2 root 4031: Uint16 overflow, carry;
1.1 root 4032:
4033: /* Shift left dest 1 bit: D<<=1 */
4034:
4035: carry = (dest[0]>>7) & 1;
4036:
4037: dest[0] <<= 1;
4038: dest[0] |= (dest[1]>>23) & 1;
4039: dest[0] &= BITMASK(8);
4040:
4041: dest[1] <<= 1;
4042: dest[1] |= (dest[2]>>23) & 1;
4043: dest[1] &= BITMASK(24);
4044:
4045: dest[2] <<= 1;
4046: dest[2] &= BITMASK(24);
4047:
4048: overflow = (carry != ((dest[0]>>7) & 1));
4049:
4050: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4051: }
4052:
1.1.1.2 root 4053: static Uint16 dsp_asr56(Uint32 *dest)
1.1 root 4054: {
1.1.1.2 root 4055: Uint16 carry;
1.1 root 4056:
4057: /* Shift right dest 1 bit: D>>=1 */
4058:
4059: carry = dest[2] & 1;
4060:
4061: dest[2] >>= 1;
4062: dest[2] |= (dest[1] & 1)<<23;
4063:
4064: dest[1] >>= 1;
4065: dest[1] |= (dest[0] & 1)<<23;
4066:
4067: dest[0] >>= 1;
4068: dest[0] |= (dest[0] & (1<<6))<<1;
4069:
4070: return (carry<<DSP_SR_C);
4071: }
4072:
1.1.1.2 root 4073: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest)
1.1 root 4074: {
1.1.1.4 root 4075: Uint16 overflow, carry, flg_s, flg_d, flg_r;
4076:
4077: flg_s = (source[0]>>7) & 1;
4078: flg_d = (dest[0]>>7) & 1;
4079:
1.1 root 4080: /* Add source to dest: D = D+S */
1.1.1.2 root 4081: dest[2] += source[2];
4082: dest[1] += source[1]+((dest[2]>>24) & 1);
4083: dest[0] += source[0]+((dest[1]>>24) & 1);
1.1 root 4084:
1.1.1.5 root 4085: carry = (dest[0]>>8) & 1;
4086:
1.1 root 4087: dest[2] &= BITMASK(24);
4088: dest[1] &= BITMASK(24);
4089: dest[0] &= BITMASK(8);
4090:
1.1.1.4 root 4091: flg_r = (dest[0]>>7) & 1;
4092:
4093: /*set overflow*/
4094: overflow = (flg_s ^ flg_r) & (flg_d ^ flg_r);
4095:
1.1 root 4096: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4097: }
4098:
1.1.1.2 root 4099: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest)
1.1 root 4100: {
1.1.1.5 root 4101: Uint16 overflow, carry, flg_s, flg_d, flg_r, dest_save;
1.1.1.4 root 4102:
1.1.1.5 root 4103: dest_save = dest[0];
1.1 root 4104:
4105: /* Substract source from dest: D = D-S */
1.1.1.2 root 4106: dest[2] -= source[2];
4107: dest[1] -= source[1]+((dest[2]>>24) & 1);
4108: dest[0] -= source[0]+((dest[1]>>24) & 1);
1.1 root 4109:
1.1.1.5 root 4110: carry = (dest[0]>>8) & 1;
4111:
1.1 root 4112: dest[2] &= BITMASK(24);
4113: dest[1] &= BITMASK(24);
4114: dest[0] &= BITMASK(8);
4115:
1.1.1.4 root 4116: flg_s = (source[0]>>7) & 1;
1.1.1.5 root 4117: flg_d = (dest_save>>7) & 1;
1.1.1.4 root 4118: flg_r = (dest[0]>>7) & 1;
4119:
4120: /* set overflow */
4121: overflow = (flg_s ^ flg_d) & (flg_r ^ flg_d);
4122:
1.1 root 4123: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4124: }
4125:
1.1.1.5 root 4126: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe)
1.1 root 4127: {
1.1.1.2 root 4128: Uint32 part[4], zerodest[3], value;
1.1 root 4129:
4130: /* Multiply: D = S1*S2 */
4131: if (source1 & (1<<23)) {
1.1.1.5 root 4132: signe ^= 1;
1.1.1.6 root 4133: source1 = (1<<24) - source1;
1.1 root 4134: }
4135: if (source2 & (1<<23)) {
1.1.1.5 root 4136: signe ^= 1;
1.1.1.6 root 4137: source2 = (1<<24) - source2;
1.1 root 4138: }
4139:
4140: /* bits 0-11 * bits 0-11 */
4141: part[0]=(source1 & BITMASK(12))*(source2 & BITMASK(12));
4142: /* bits 12-23 * bits 0-11 */
4143: part[1]=((source1>>12) & BITMASK(12))*(source2 & BITMASK(12));
4144: /* bits 0-11 * bits 12-23 */
4145: part[2]=(source1 & BITMASK(12))*((source2>>12) & BITMASK(12));
4146: /* bits 12-23 * bits 12-23 */
4147: part[3]=((source1>>12) & BITMASK(12))*((source2>>12) & BITMASK(12));
4148:
4149: /* Calc dest 2 */
4150: dest[2] = part[0];
4151: dest[2] += (part[1] & BITMASK(12)) << 12;
4152: dest[2] += (part[2] & BITMASK(12)) << 12;
4153:
4154: /* Calc dest 1 */
4155: dest[1] = (part[1]>>12) & BITMASK(12);
4156: dest[1] += (part[2]>>12) & BITMASK(12);
4157: dest[1] += part[3];
4158:
4159: /* Calc dest 0 */
4160: dest[0] = 0;
4161:
4162: /* Add carries */
4163: value = (dest[2]>>24) & BITMASK(8);
4164: if (value) {
4165: dest[1] += value;
4166: dest[2] &= BITMASK(24);
4167: }
4168: value = (dest[1]>>24) & BITMASK(8);
4169: if (value) {
4170: dest[0] += value;
4171: dest[1] &= BITMASK(24);
4172: }
4173:
4174: /* Get rid of extra sign bit */
4175: dsp_asl56(dest);
4176:
1.1.1.5 root 4177: if (signe) {
1.1 root 4178: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4179:
4180: dsp_sub56(dest, zerodest);
4181:
4182: dest[0] = zerodest[0];
4183: dest[1] = zerodest[1];
4184: dest[2] = zerodest[2];
4185: }
4186: }
4187:
1.1.1.2 root 4188: static void dsp_rnd56(Uint32 *dest)
1.1 root 4189: {
1.1.1.4 root 4190: Uint32 rnd_const[3];
1.1 root 4191:
1.1.1.4 root 4192: rnd_const[0] = 0;
1.1 root 4193:
1.1.1.4 root 4194: /* Scaling mode S0 */
1.1.1.6 root 4195: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S0)) {
1.1.1.4 root 4196: rnd_const[1] = 1;
4197: rnd_const[2] = 0;
4198: dsp_add56(rnd_const, dest);
4199:
4200: if ((dest[2]==0) && ((dest[1] & 1) == 0)) {
4201: dest[1] &= (0xffffff - 0x3);
4202: }
4203: dest[1] &= 0xfffffe;
4204: dest[2]=0;
4205: }
4206: /* Scaling mode S1 */
1.1.1.6 root 4207: else if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S1)) {
1.1.1.4 root 4208: rnd_const[1] = 0;
4209: rnd_const[2] = (1<<22);
4210: dsp_add56(rnd_const, dest);
4211:
4212: if ((dest[2] & 0x7fffff) == 0){
4213: dest[2] = 0;
4214: }
4215: dest[2] &= 0x800000;
4216: }
4217: /* No Scaling */
4218: else {
4219: rnd_const[1] = 0;
4220: rnd_const[2] = (1<<23);
4221: dsp_add56(rnd_const, dest);
4222:
4223: if (dest[2] == 0) {
4224: dest[1] &= 0xfffffe;
1.1 root 4225: }
1.1.1.4 root 4226: dest[2]=0;
1.1 root 4227: }
4228: }
4229:
4230: /**********************************
4231: * Parallel moves instructions
4232: **********************************/
4233:
1.1.1.6 root 4234: static void dsp_abs_a(void)
1.1 root 4235: {
1.1.1.6 root 4236: Uint32 dest[3], overflowed;
1.1 root 4237:
1.1.1.6 root 4238: dest[0] = dsp_core.registers[DSP_REG_A2];
4239: dest[1] = dsp_core.registers[DSP_REG_A1];
4240: dest[2] = dsp_core.registers[DSP_REG_A0];
4241:
4242: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4243:
4244: dsp_abs56(dest);
4245:
4246: dsp_core.registers[DSP_REG_A2] = dest[0];
4247: dsp_core.registers[DSP_REG_A1] = dest[1];
4248: dsp_core.registers[DSP_REG_A0] = dest[2];
4249:
4250: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4251: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
4252:
4253: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4254: }
4255:
4256: static void dsp_abs_b(void)
4257: {
4258: Uint32 dest[3], overflowed;
1.1 root 4259:
1.1.1.6 root 4260: dest[0] = dsp_core.registers[DSP_REG_B2];
4261: dest[1] = dsp_core.registers[DSP_REG_B1];
4262: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 4263:
4264: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4265:
4266: dsp_abs56(dest);
4267:
1.1.1.6 root 4268: dsp_core.registers[DSP_REG_B2] = dest[0];
4269: dsp_core.registers[DSP_REG_B1] = dest[1];
4270: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4271:
1.1.1.6 root 4272: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4273: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
1.1.1.2 root 4274:
1.1.1.6 root 4275: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4276: }
4277:
1.1.1.6 root 4278: static void dsp_adc_x_a(void)
1.1 root 4279: {
1.1.1.6 root 4280: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4281: Uint16 newsr;
1.1 root 4282:
1.1.1.6 root 4283: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4284:
1.1.1.6 root 4285: dest[0] = dsp_core.registers[DSP_REG_A2];
4286: dest[1] = dsp_core.registers[DSP_REG_A1];
4287: dest[2] = dsp_core.registers[DSP_REG_A0];
4288:
4289: source[2] = dsp_core.registers[DSP_REG_X0];
4290: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 ! root 4291: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4292:
4293: newsr = dsp_add56(source, dest);
4294:
4295: if (curcarry) {
1.1.1.6 root 4296: source[0]=0; source[1]=0; source[2]=1;
1.1 root 4297: newsr |= dsp_add56(source, dest);
4298: }
4299:
1.1.1.6 root 4300: dsp_core.registers[DSP_REG_A2] = dest[0];
4301: dsp_core.registers[DSP_REG_A1] = dest[1];
4302: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4303:
1.1.1.6 root 4304: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4305:
1.1.1.6 root 4306: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4307: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4308: }
4309:
1.1.1.6 root 4310: static void dsp_adc_x_b(void)
1.1 root 4311: {
1.1.1.6 root 4312: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4313: Uint16 newsr;
1.1 root 4314:
1.1.1.6 root 4315: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
4316:
4317: dest[0] = dsp_core.registers[DSP_REG_B2];
4318: dest[1] = dsp_core.registers[DSP_REG_B1];
4319: dest[2] = dsp_core.registers[DSP_REG_B0];
4320:
4321: source[2] = dsp_core.registers[DSP_REG_X0];
4322: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 ! root 4323: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4324:
4325: newsr = dsp_add56(source, dest);
1.1.1.6 root 4326:
4327: if (curcarry) {
4328: source[0]=0; source[1]=0; source[2]=1;
4329: newsr |= dsp_add56(source, dest);
4330: }
1.1 root 4331:
1.1.1.6 root 4332: dsp_core.registers[DSP_REG_B2] = dest[0];
4333: dsp_core.registers[DSP_REG_B1] = dest[1];
4334: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4335:
1.1.1.6 root 4336: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4337:
1.1.1.6 root 4338: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4339: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4340: }
4341:
1.1.1.6 root 4342: static void dsp_adc_y_a(void)
1.1 root 4343: {
1.1.1.6 root 4344: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4345: Uint16 newsr;
1.1 root 4346:
1.1.1.6 root 4347: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4348:
1.1.1.6 root 4349: dest[0] = dsp_core.registers[DSP_REG_A2];
4350: dest[1] = dsp_core.registers[DSP_REG_A1];
4351: dest[2] = dsp_core.registers[DSP_REG_A0];
4352:
4353: source[2] = dsp_core.registers[DSP_REG_Y0];
4354: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 ! root 4355: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4356:
1.1.1.6 root 4357: newsr = dsp_add56(source, dest);
4358:
4359: if (curcarry) {
4360: source[0]=0; source[1]=0; source[2]=1;
4361: newsr |= dsp_add56(source, dest);
4362: }
1.1 root 4363:
1.1.1.6 root 4364: dsp_core.registers[DSP_REG_A2] = dest[0];
4365: dsp_core.registers[DSP_REG_A1] = dest[1];
4366: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4367:
1.1.1.6 root 4368: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4369:
1.1.1.6 root 4370: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4371: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4372: }
4373:
1.1.1.6 root 4374: static void dsp_adc_y_b(void)
1.1 root 4375: {
1.1.1.6 root 4376: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4377: Uint16 newsr;
1.1 root 4378:
1.1.1.6 root 4379: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4380:
1.1.1.6 root 4381: dest[0] = dsp_core.registers[DSP_REG_B2];
4382: dest[1] = dsp_core.registers[DSP_REG_B1];
4383: dest[2] = dsp_core.registers[DSP_REG_B0];
4384:
4385: source[2] = dsp_core.registers[DSP_REG_Y0];
4386: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 ! root 4387: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4388:
1.1.1.6 root 4389: newsr = dsp_add56(source, dest);
4390:
4391: if (curcarry) {
4392: source[0]=0; source[1]=0; source[2]=1;
4393: newsr |= dsp_add56(source, dest);
4394: }
1.1 root 4395:
1.1.1.6 root 4396: dsp_core.registers[DSP_REG_B2] = dest[0];
4397: dsp_core.registers[DSP_REG_B1] = dest[1];
4398: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4399:
1.1.1.6 root 4400: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4401:
1.1.1.6 root 4402: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4403: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4404: }
4405:
1.1.1.6 root 4406: static void dsp_add_b_a(void)
1.1 root 4407: {
1.1.1.6 root 4408: Uint32 source[3], dest[3];
4409: Uint16 newsr;
1.1 root 4410:
1.1.1.6 root 4411: dest[0] = dsp_core.registers[DSP_REG_A2];
4412: dest[1] = dsp_core.registers[DSP_REG_A1];
4413: dest[2] = dsp_core.registers[DSP_REG_A0];
4414:
4415: source[0] = dsp_core.registers[DSP_REG_B2];
4416: source[1] = dsp_core.registers[DSP_REG_B1];
4417: source[2] = dsp_core.registers[DSP_REG_B0];
4418:
4419: newsr = dsp_add56(source, dest);
4420:
4421: dsp_core.registers[DSP_REG_A2] = dest[0];
4422: dsp_core.registers[DSP_REG_A1] = dest[1];
4423: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4424:
1.1.1.6 root 4425: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4426:
1.1.1.6 root 4427: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4428: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4429: }
4430:
1.1.1.6 root 4431: static void dsp_add_a_b(void)
1.1 root 4432: {
1.1.1.6 root 4433: Uint32 source[3], dest[3];
1.1.1.2 root 4434: Uint16 newsr;
1.1 root 4435:
1.1.1.6 root 4436: dest[0] = dsp_core.registers[DSP_REG_B2];
4437: dest[1] = dsp_core.registers[DSP_REG_B1];
4438: dest[2] = dsp_core.registers[DSP_REG_B0];
4439:
4440: source[0] = dsp_core.registers[DSP_REG_A2];
4441: source[1] = dsp_core.registers[DSP_REG_A1];
4442: source[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 4443:
1.1.1.6 root 4444: newsr = dsp_add56(source, dest);
1.1 root 4445:
1.1.1.6 root 4446: dsp_core.registers[DSP_REG_B2] = dest[0];
4447: dsp_core.registers[DSP_REG_B1] = dest[1];
4448: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4449:
1.1.1.6 root 4450: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4451:
1.1.1.6 root 4452: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4453: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4454: }
4455:
1.1.1.6 root 4456: static void dsp_add_x_a(void)
1.1 root 4457: {
1.1.1.6 root 4458: Uint32 source[3], dest[3];
4459: Uint16 newsr;
1.1 root 4460:
1.1.1.6 root 4461: dest[0] = dsp_core.registers[DSP_REG_A2];
4462: dest[1] = dsp_core.registers[DSP_REG_A1];
4463: dest[2] = dsp_core.registers[DSP_REG_A0];
4464:
4465: source[1] = dsp_core.registers[DSP_REG_X1];
4466: source[2] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 ! root 4467: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4468:
1.1.1.6 root 4469: newsr = dsp_add56(source, dest);
1.1 root 4470:
1.1.1.6 root 4471: dsp_core.registers[DSP_REG_A2] = dest[0];
4472: dsp_core.registers[DSP_REG_A1] = dest[1];
4473: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4474:
1.1.1.6 root 4475: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4476:
1.1.1.6 root 4477: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4478: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4479: }
4480:
1.1.1.6 root 4481: static void dsp_add_x_b(void)
1.1 root 4482: {
1.1.1.6 root 4483: Uint32 source[3], dest[3];
4484: Uint16 newsr;
1.1 root 4485:
1.1.1.6 root 4486: dest[0] = dsp_core.registers[DSP_REG_B2];
4487: dest[1] = dsp_core.registers[DSP_REG_B1];
4488: dest[2] = dsp_core.registers[DSP_REG_B0];
4489:
4490: source[1] = dsp_core.registers[DSP_REG_X1];
4491: source[2] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 ! root 4492: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4493:
4494: newsr = dsp_add56(source, dest);
1.1 root 4495:
1.1.1.6 root 4496: dsp_core.registers[DSP_REG_B2] = dest[0];
4497: dsp_core.registers[DSP_REG_B1] = dest[1];
4498: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4499:
1.1.1.6 root 4500: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4501:
4502: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4503: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4504: }
4505:
1.1.1.6 root 4506: static void dsp_add_y_a(void)
1.1 root 4507: {
1.1.1.6 root 4508: Uint32 source[3], dest[3];
1.1.1.2 root 4509: Uint16 newsr;
1.1 root 4510:
1.1.1.6 root 4511: dest[0] = dsp_core.registers[DSP_REG_A2];
4512: dest[1] = dsp_core.registers[DSP_REG_A1];
4513: dest[2] = dsp_core.registers[DSP_REG_A0];
4514:
4515: source[1] = dsp_core.registers[DSP_REG_Y1];
4516: source[2] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 ! root 4517: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4518:
1.1.1.6 root 4519: newsr = dsp_add56(source, dest);
1.1 root 4520:
1.1.1.6 root 4521: dsp_core.registers[DSP_REG_A2] = dest[0];
4522: dsp_core.registers[DSP_REG_A1] = dest[1];
4523: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4524:
1.1.1.6 root 4525: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4526:
4527: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4528: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4529: }
4530:
1.1.1.6 root 4531: static void dsp_add_y_b(void)
1.1 root 4532: {
1.1.1.6 root 4533: Uint32 source[3], dest[3];
1.1.1.2 root 4534: Uint16 newsr;
1.1 root 4535:
1.1.1.6 root 4536: dest[0] = dsp_core.registers[DSP_REG_B2];
4537: dest[1] = dsp_core.registers[DSP_REG_B1];
4538: dest[2] = dsp_core.registers[DSP_REG_B0];
4539:
4540: source[1] = dsp_core.registers[DSP_REG_Y1];
4541: source[2] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 ! root 4542: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4543:
1.1.1.6 root 4544: newsr = dsp_add56(source, dest);
1.1 root 4545:
1.1.1.6 root 4546: dsp_core.registers[DSP_REG_B2] = dest[0];
4547: dsp_core.registers[DSP_REG_B1] = dest[1];
4548: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4549:
1.1.1.6 root 4550: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4551:
1.1.1.6 root 4552: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4553: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4554: }
4555:
1.1.1.6 root 4556: static void dsp_add_x0_a(void)
1.1 root 4557: {
1.1.1.6 root 4558: Uint32 source[3], dest[3];
4559: Uint16 newsr;
1.1 root 4560:
1.1.1.6 root 4561: dest[0] = dsp_core.registers[DSP_REG_A2];
4562: dest[1] = dsp_core.registers[DSP_REG_A1];
4563: dest[2] = dsp_core.registers[DSP_REG_A0];
4564:
4565: source[2] = 0;
4566: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 ! root 4567: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4568:
4569: newsr = dsp_add56(source, dest);
4570:
4571: dsp_core.registers[DSP_REG_A2] = dest[0];
4572: dsp_core.registers[DSP_REG_A1] = dest[1];
4573: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4574:
1.1.1.6 root 4575: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4576:
1.1.1.6 root 4577: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4578: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4579: }
4580:
1.1.1.6 root 4581: static void dsp_add_x0_b(void)
1.1 root 4582: {
1.1.1.6 root 4583: Uint32 source[3], dest[3];
4584: Uint16 newsr;
4585:
4586: dest[0] = dsp_core.registers[DSP_REG_B2];
4587: dest[1] = dsp_core.registers[DSP_REG_B1];
4588: dest[2] = dsp_core.registers[DSP_REG_B0];
4589:
4590: source[2] = 0;
4591: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 ! root 4592: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4593:
1.1.1.6 root 4594: newsr = dsp_add56(source, dest);
1.1 root 4595:
1.1.1.6 root 4596: dsp_core.registers[DSP_REG_B2] = dest[0];
4597: dsp_core.registers[DSP_REG_B1] = dest[1];
4598: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4599:
1.1.1.6 root 4600: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4601:
1.1.1.6 root 4602: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4603: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4604: }
4605:
1.1.1.6 root 4606: static void dsp_add_y0_a(void)
1.1 root 4607: {
1.1.1.6 root 4608: Uint32 source[3], dest[3];
4609: Uint16 newsr;
1.1 root 4610:
1.1.1.6 root 4611: dest[0] = dsp_core.registers[DSP_REG_A2];
4612: dest[1] = dsp_core.registers[DSP_REG_A1];
4613: dest[2] = dsp_core.registers[DSP_REG_A0];
4614:
4615: source[2] = 0;
4616: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 ! root 4617: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4618:
1.1.1.6 root 4619: newsr = dsp_add56(source, dest);
4620:
4621: dsp_core.registers[DSP_REG_A2] = dest[0];
4622: dsp_core.registers[DSP_REG_A1] = dest[1];
4623: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4624:
1.1.1.6 root 4625: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4626:
1.1.1.6 root 4627: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4628: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4629: }
4630:
1.1.1.6 root 4631: static void dsp_add_y0_b(void)
1.1 root 4632: {
1.1.1.6 root 4633: Uint32 source[3], dest[3];
1.1.1.2 root 4634: Uint16 newsr;
1.1 root 4635:
1.1.1.6 root 4636: dest[0] = dsp_core.registers[DSP_REG_B2];
4637: dest[1] = dsp_core.registers[DSP_REG_B1];
4638: dest[2] = dsp_core.registers[DSP_REG_B0];
4639:
4640: source[2] = 0;
4641: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 ! root 4642: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4643:
4644: newsr = dsp_add56(source, dest);
4645:
1.1.1.6 root 4646: dsp_core.registers[DSP_REG_B2] = dest[0];
4647: dsp_core.registers[DSP_REG_B1] = dest[1];
4648: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4649:
1.1.1.6 root 4650: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4651:
1.1.1.6 root 4652: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4653: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4654: }
4655:
1.1.1.6 root 4656: static void dsp_add_x1_a(void)
1.1 root 4657: {
1.1.1.6 root 4658: Uint32 source[3], dest[3];
1.1.1.2 root 4659: Uint16 newsr;
1.1 root 4660:
1.1.1.6 root 4661: dest[0] = dsp_core.registers[DSP_REG_A2];
4662: dest[1] = dsp_core.registers[DSP_REG_A1];
4663: dest[2] = dsp_core.registers[DSP_REG_A0];
4664:
4665: source[2] = 0;
4666: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 ! root 4667: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4668:
4669: newsr = dsp_add56(source, dest);
4670:
1.1.1.6 root 4671: dsp_core.registers[DSP_REG_A2] = dest[0];
4672: dsp_core.registers[DSP_REG_A1] = dest[1];
4673: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4674:
1.1.1.6 root 4675: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4676:
1.1.1.6 root 4677: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4678: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4679: }
4680:
1.1.1.6 root 4681: static void dsp_add_x1_b(void)
1.1 root 4682: {
1.1.1.6 root 4683: Uint32 source[3], dest[3];
4684: Uint16 newsr;
4685:
4686: dest[0] = dsp_core.registers[DSP_REG_B2];
4687: dest[1] = dsp_core.registers[DSP_REG_B1];
4688: dest[2] = dsp_core.registers[DSP_REG_B0];
4689:
4690: source[2] = 0;
4691: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 ! root 4692: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4693:
4694: newsr = dsp_add56(source, dest);
4695:
4696: dsp_core.registers[DSP_REG_B2] = dest[0];
4697: dsp_core.registers[DSP_REG_B1] = dest[1];
4698: dsp_core.registers[DSP_REG_B0] = dest[2];
4699:
4700: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4701:
4702: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4703: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4704: }
4705:
1.1.1.6 root 4706: static void dsp_add_y1_a(void)
1.1 root 4707: {
1.1.1.6 root 4708: Uint32 source[3], dest[3];
4709: Uint16 newsr;
1.1 root 4710:
1.1.1.6 root 4711: dest[0] = dsp_core.registers[DSP_REG_A2];
4712: dest[1] = dsp_core.registers[DSP_REG_A1];
4713: dest[2] = dsp_core.registers[DSP_REG_A0];
4714:
4715: source[2] = 0;
4716: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 ! root 4717: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4718:
1.1.1.6 root 4719: newsr = dsp_add56(source, dest);
1.1 root 4720:
1.1.1.6 root 4721: dsp_core.registers[DSP_REG_A2] = dest[0];
4722: dsp_core.registers[DSP_REG_A1] = dest[1];
4723: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4724:
1.1.1.6 root 4725: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4726:
1.1.1.6 root 4727: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4728: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4729: }
4730:
1.1.1.6 root 4731: static void dsp_add_y1_b(void)
1.1 root 4732: {
1.1.1.6 root 4733: Uint32 source[3], dest[3];
4734: Uint16 newsr;
1.1 root 4735:
1.1.1.6 root 4736: dest[0] = dsp_core.registers[DSP_REG_B2];
4737: dest[1] = dsp_core.registers[DSP_REG_B1];
4738: dest[2] = dsp_core.registers[DSP_REG_B0];
4739:
4740: source[2] = 0;
4741: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 ! root 4742: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4743:
1.1.1.6 root 4744: newsr = dsp_add56(source, dest);
1.1 root 4745:
1.1.1.6 root 4746: dsp_core.registers[DSP_REG_B2] = dest[0];
4747: dsp_core.registers[DSP_REG_B1] = dest[1];
4748: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4749:
1.1.1.6 root 4750: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4751:
1.1.1.6 root 4752: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4753: dsp_core.registers[DSP_REG_SR] |= newsr;
4754: }
1.1 root 4755:
1.1.1.6 root 4756: static void dsp_addl_b_a(void)
4757: {
4758: Uint32 source[3], dest[3];
4759: Uint16 newsr;
1.1.1.2 root 4760:
1.1.1.6 root 4761: dest[0] = dsp_core.registers[DSP_REG_A2];
4762: dest[1] = dsp_core.registers[DSP_REG_A1];
4763: dest[2] = dsp_core.registers[DSP_REG_A0];
4764: newsr = dsp_asl56(dest);
1.1 root 4765:
1.1.1.6 root 4766: source[0] = dsp_core.registers[DSP_REG_B2];
4767: source[1] = dsp_core.registers[DSP_REG_B1];
4768: source[2] = dsp_core.registers[DSP_REG_B0];
4769: newsr |= dsp_add56(source, dest);
1.1 root 4770:
1.1.1.6 root 4771: dsp_core.registers[DSP_REG_A2] = dest[0];
4772: dsp_core.registers[DSP_REG_A1] = dest[1];
4773: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4774:
1.1.1.6 root 4775: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4776:
1.1.1.6 root 4777: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4778: dsp_core.registers[DSP_REG_SR] |= newsr;
4779: }
1.1 root 4780:
1.1.1.6 root 4781: static void dsp_addl_a_b(void)
4782: {
4783: Uint32 source[3], dest[3];
4784: Uint16 newsr;
1.1 root 4785:
1.1.1.6 root 4786: dest[0] = dsp_core.registers[DSP_REG_B2];
4787: dest[1] = dsp_core.registers[DSP_REG_B1];
4788: dest[2] = dsp_core.registers[DSP_REG_B0];
4789: newsr = dsp_asl56(dest);
1.1 root 4790:
1.1.1.6 root 4791: source[0] = dsp_core.registers[DSP_REG_A2];
4792: source[1] = dsp_core.registers[DSP_REG_A1];
4793: source[2] = dsp_core.registers[DSP_REG_A0];
4794: newsr |= dsp_add56(source, dest);
4795:
4796: dsp_core.registers[DSP_REG_B2] = dest[0];
4797: dsp_core.registers[DSP_REG_B1] = dest[1];
4798: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4799:
1.1.1.6 root 4800: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4801:
1.1.1.6 root 4802: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4803: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4804: }
4805:
1.1.1.6 root 4806: static void dsp_addr_b_a(void)
1.1 root 4807: {
1.1.1.6 root 4808: Uint32 source[3], dest[3];
4809: Uint16 newsr;
4810:
4811: dest[0] = dsp_core.registers[DSP_REG_A2];
4812: dest[1] = dsp_core.registers[DSP_REG_A1];
4813: dest[2] = dsp_core.registers[DSP_REG_A0];
4814: newsr = dsp_asr56(dest);
4815:
4816: source[0] = dsp_core.registers[DSP_REG_B2];
4817: source[1] = dsp_core.registers[DSP_REG_B1];
4818: source[2] = dsp_core.registers[DSP_REG_B0];
4819: newsr |= dsp_add56(source, dest);
4820:
4821: dsp_core.registers[DSP_REG_A2] = dest[0];
4822: dsp_core.registers[DSP_REG_A1] = dest[1];
4823: dsp_core.registers[DSP_REG_A0] = dest[2];
4824:
4825: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4826:
4827: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4828: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4829: }
4830:
1.1.1.6 root 4831: static void dsp_addr_a_b(void)
1.1 root 4832: {
1.1.1.6 root 4833: Uint32 source[3], dest[3];
4834: Uint16 newsr;
4835:
4836: dest[0] = dsp_core.registers[DSP_REG_B2];
4837: dest[1] = dsp_core.registers[DSP_REG_B1];
4838: dest[2] = dsp_core.registers[DSP_REG_B0];
4839: newsr = dsp_asr56(dest);
4840:
4841: source[0] = dsp_core.registers[DSP_REG_A2];
4842: source[1] = dsp_core.registers[DSP_REG_A1];
4843: source[2] = dsp_core.registers[DSP_REG_A0];
4844: newsr |= dsp_add56(source, dest);
1.1 root 4845:
1.1.1.6 root 4846: dsp_core.registers[DSP_REG_B2] = dest[0];
4847: dsp_core.registers[DSP_REG_B1] = dest[1];
4848: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4849:
1.1.1.6 root 4850: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4851:
1.1.1.6 root 4852: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4853: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4854: }
4855:
1.1.1.6 root 4856: static void dsp_and_x0_a(void)
1.1 root 4857: {
1.1.1.6 root 4858: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X0];
1.1 root 4859:
1.1.1.6 root 4860: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4861: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4862: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4863: }
1.1 root 4864:
1.1.1.6 root 4865: static void dsp_and_x0_b(void)
4866: {
4867: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X0];
1.1 root 4868:
1.1.1.6 root 4869: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4870: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4871: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
1.1 root 4872: }
4873:
1.1.1.6 root 4874: static void dsp_and_y0_a(void)
1.1 root 4875: {
1.1.1.6 root 4876: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y0];
1.1 root 4877:
1.1.1.6 root 4878: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4879: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4880: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4881: }
1.1 root 4882:
1.1.1.6 root 4883: static void dsp_and_y0_b(void)
4884: {
4885: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y0];
1.1 root 4886:
1.1.1.6 root 4887: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4888: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4889: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
4890: }
1.1 root 4891:
1.1.1.6 root 4892: static void dsp_and_x1_a(void)
4893: {
4894: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X1];
1.1.1.2 root 4895:
1.1.1.6 root 4896: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4897: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4898: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
1.1 root 4899: }
4900:
1.1.1.6 root 4901: static void dsp_and_x1_b(void)
1.1 root 4902: {
1.1.1.6 root 4903: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X1];
4904:
4905: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4906: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4907: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
4908: }
1.1 root 4909:
1.1.1.6 root 4910: static void dsp_and_y1_a(void)
4911: {
4912: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y1];
1.1 root 4913:
1.1.1.6 root 4914: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4915: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4916: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4917: }
1.1 root 4918:
1.1.1.6 root 4919: static void dsp_and_y1_b(void)
4920: {
4921: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y1];
1.1.1.2 root 4922:
1.1.1.6 root 4923: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4924: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4925: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
1.1 root 4926: }
4927:
1.1.1.7 ! root 4928: static void dsp_asl_a(void)
1.1 root 4929: {
1.1.1.6 root 4930: Uint32 dest[3];
4931: Uint16 newsr;
1.1 root 4932:
1.1.1.6 root 4933: dest[0] = dsp_core.registers[DSP_REG_A2];
4934: dest[1] = dsp_core.registers[DSP_REG_A1];
4935: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 4936:
1.1.1.6 root 4937: newsr = dsp_asl56(dest);
4938:
4939: dsp_core.registers[DSP_REG_A2] = dest[0];
4940: dsp_core.registers[DSP_REG_A1] = dest[1];
4941: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4942:
1.1.1.6 root 4943: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
4944: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1.1.2 root 4945:
1.1.1.6 root 4946: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4947: }
4948:
1.1.1.7 ! root 4949: static void dsp_asl_b(void)
1.1 root 4950: {
1.1.1.6 root 4951: Uint32 dest[3];
1.1.1.2 root 4952: Uint16 newsr;
1.1 root 4953:
1.1.1.6 root 4954: dest[0] = dsp_core.registers[DSP_REG_B2];
4955: dest[1] = dsp_core.registers[DSP_REG_B1];
4956: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 4957:
1.1.1.6 root 4958: newsr = dsp_asl56(dest);
1.1 root 4959:
1.1.1.6 root 4960: dsp_core.registers[DSP_REG_B2] = dest[0];
4961: dsp_core.registers[DSP_REG_B1] = dest[1];
4962: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4963:
1.1.1.6 root 4964: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
4965: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4966:
1.1.1.6 root 4967: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4968: }
4969:
1.1.1.7 ! root 4970: static void dsp_asr_a(void)
1.1 root 4971: {
1.1.1.6 root 4972: Uint32 dest[3];
4973: Uint16 newsr;
4974:
4975: dest[0] = dsp_core.registers[DSP_REG_A2];
4976: dest[1] = dsp_core.registers[DSP_REG_A1];
4977: dest[2] = dsp_core.registers[DSP_REG_A0];
4978:
4979: newsr = dsp_asr56(dest);
4980:
4981: dsp_core.registers[DSP_REG_A2] = dest[0];
4982: dsp_core.registers[DSP_REG_A1] = dest[1];
4983: dsp_core.registers[DSP_REG_A0] = dest[2];
4984:
4985: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
4986: dsp_core.registers[DSP_REG_SR] |= newsr;
4987:
4988: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4989: }
4990:
1.1.1.7 ! root 4991: static void dsp_asr_b(void)
1.1.1.6 root 4992: {
4993: Uint32 dest[3];
4994: Uint16 newsr;
4995:
4996: dest[0] = dsp_core.registers[DSP_REG_B2];
4997: dest[1] = dsp_core.registers[DSP_REG_B1];
4998: dest[2] = dsp_core.registers[DSP_REG_B0];
4999:
5000: newsr = dsp_asr56(dest);
5001:
5002: dsp_core.registers[DSP_REG_B2] = dest[0];
5003: dsp_core.registers[DSP_REG_B1] = dest[1];
5004: dsp_core.registers[DSP_REG_B0] = dest[2];
5005:
5006: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5007: dsp_core.registers[DSP_REG_SR] |= newsr;
5008:
5009: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5010: }
5011:
5012: static void dsp_clr_a(void)
5013: {
1.1.1.7 ! root 5014: dsp_core.registers[DSP_REG_A2] = 0;
! 5015: dsp_core.registers[DSP_REG_A1] = 0;
! 5016: dsp_core.registers[DSP_REG_A0] = 0;
1.1.1.6 root 5017:
5018: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5019: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5020: }
5021:
5022: static void dsp_clr_b(void)
5023: {
1.1.1.7 ! root 5024: dsp_core.registers[DSP_REG_B2] = 0;
! 5025: dsp_core.registers[DSP_REG_B1] = 0;
! 5026: dsp_core.registers[DSP_REG_B0] = 0;
1.1.1.6 root 5027:
5028: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5029: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5030: }
5031:
5032: static void dsp_cmp_b_a(void)
5033: {
5034: Uint32 source[3], dest[3];
5035: Uint16 newsr;
5036:
5037: dest[0] = dsp_core.registers[DSP_REG_A2];
5038: dest[1] = dsp_core.registers[DSP_REG_A1];
5039: dest[2] = dsp_core.registers[DSP_REG_A0];
5040:
5041: source[0] = dsp_core.registers[DSP_REG_B2];
5042: source[1] = dsp_core.registers[DSP_REG_B1];
5043: source[2] = dsp_core.registers[DSP_REG_B0];
5044:
5045: newsr = dsp_sub56(source, dest);
5046:
5047: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5048:
5049: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5050: dsp_core.registers[DSP_REG_SR] |= newsr;
5051: }
5052:
5053: static void dsp_cmp_a_b(void)
5054: {
5055: Uint32 source[3], dest[3];
5056: Uint16 newsr;
5057:
5058: dest[0] = dsp_core.registers[DSP_REG_B2];
5059: dest[1] = dsp_core.registers[DSP_REG_B1];
5060: dest[2] = dsp_core.registers[DSP_REG_B0];
5061:
5062: source[0] = dsp_core.registers[DSP_REG_A2];
5063: source[1] = dsp_core.registers[DSP_REG_A1];
5064: source[2] = dsp_core.registers[DSP_REG_A0];
5065:
5066: newsr = dsp_sub56(source, dest);
5067:
5068: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5069:
5070: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5071: dsp_core.registers[DSP_REG_SR] |= newsr;
5072: }
5073:
5074: static void dsp_cmp_x0_a(void)
5075: {
5076: Uint32 source[3], dest[3];
5077: Uint16 newsr;
5078:
5079: dest[2] = dsp_core.registers[DSP_REG_A0];
5080: dest[1] = dsp_core.registers[DSP_REG_A1];
5081: dest[0] = dsp_core.registers[DSP_REG_A2];
5082:
5083: source[2] = 0;
5084: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 ! root 5085: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5086:
5087: newsr = dsp_sub56(source, dest);
5088:
5089: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5090:
5091: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5092: dsp_core.registers[DSP_REG_SR] |= newsr;
5093: }
5094:
5095: static void dsp_cmp_x0_b(void)
5096: {
5097: Uint32 source[3], dest[3];
5098: Uint16 newsr;
5099:
5100: dest[0] = dsp_core.registers[DSP_REG_B2];
5101: dest[1] = dsp_core.registers[DSP_REG_B1];
5102: dest[2] = dsp_core.registers[DSP_REG_B0];
5103:
5104: source[2] = 0;
5105: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 ! root 5106: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5107:
5108: newsr = dsp_sub56(source, dest);
5109:
5110: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5111:
5112: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5113: dsp_core.registers[DSP_REG_SR] |= newsr;
5114: }
5115:
5116: static void dsp_cmp_y0_a(void)
5117: {
5118: Uint32 source[3], dest[3];
5119: Uint16 newsr;
5120:
5121: dest[2] = dsp_core.registers[DSP_REG_A0];
5122: dest[1] = dsp_core.registers[DSP_REG_A1];
5123: dest[0] = dsp_core.registers[DSP_REG_A2];
5124:
5125: source[2] = 0;
5126: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 ! root 5127: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5128:
5129: newsr = dsp_sub56(source, dest);
5130:
5131: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5132:
5133: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5134: dsp_core.registers[DSP_REG_SR] |= newsr;
5135: }
5136:
5137: static void dsp_cmp_y0_b(void)
5138: {
5139: Uint32 source[3], dest[3];
5140: Uint16 newsr;
5141:
5142: dest[0] = dsp_core.registers[DSP_REG_B2];
5143: dest[1] = dsp_core.registers[DSP_REG_B1];
5144: dest[2] = dsp_core.registers[DSP_REG_B0];
5145:
5146: source[2] = 0;
5147: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 ! root 5148: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5149:
5150: newsr = dsp_sub56(source, dest);
5151:
5152: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5153:
5154: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5155: dsp_core.registers[DSP_REG_SR] |= newsr;
5156: }
5157: static void dsp_cmp_x1_a(void)
5158: {
5159: Uint32 source[3], dest[3];
5160: Uint16 newsr;
5161:
5162: dest[2] = dsp_core.registers[DSP_REG_A0];
5163: dest[1] = dsp_core.registers[DSP_REG_A1];
5164: dest[0] = dsp_core.registers[DSP_REG_A2];
5165:
5166: source[2] = 0;
5167: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 ! root 5168: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5169:
5170: newsr = dsp_sub56(source, dest);
5171:
5172: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5173:
5174: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5175: dsp_core.registers[DSP_REG_SR] |= newsr;
5176: }
5177:
5178: static void dsp_cmp_x1_b(void)
5179: {
5180: Uint32 source[3], dest[3];
5181: Uint16 newsr;
5182:
5183: dest[0] = dsp_core.registers[DSP_REG_B2];
5184: dest[1] = dsp_core.registers[DSP_REG_B1];
5185: dest[2] = dsp_core.registers[DSP_REG_B0];
5186:
5187: source[2] = 0;
5188: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 ! root 5189: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5190:
5191: newsr = dsp_sub56(source, dest);
5192:
5193: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5194:
5195: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5196: dsp_core.registers[DSP_REG_SR] |= newsr;
5197: }
5198:
5199: static void dsp_cmp_y1_a(void)
5200: {
5201: Uint32 source[3], dest[3];
5202: Uint16 newsr;
5203:
5204: dest[2] = dsp_core.registers[DSP_REG_A0];
5205: dest[1] = dsp_core.registers[DSP_REG_A1];
5206: dest[0] = dsp_core.registers[DSP_REG_A2];
5207:
5208: source[2] = 0;
5209: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 ! root 5210: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5211:
5212: newsr = dsp_sub56(source, dest);
5213:
5214: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5215:
5216: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5217: dsp_core.registers[DSP_REG_SR] |= newsr;
5218: }
5219:
5220: static void dsp_cmp_y1_b(void)
5221: {
5222: Uint32 source[3], dest[3];
5223: Uint16 newsr;
5224:
5225: dest[0] = dsp_core.registers[DSP_REG_B2];
5226: dest[1] = dsp_core.registers[DSP_REG_B1];
5227: dest[2] = dsp_core.registers[DSP_REG_B0];
5228:
5229: source[2] = 0;
5230: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 ! root 5231: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5232:
5233: newsr = dsp_sub56(source, dest);
5234:
5235: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5236:
5237: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5238: dsp_core.registers[DSP_REG_SR] |= newsr;
5239: }
5240:
5241: static void dsp_cmpm_b_a(void)
5242: {
5243: Uint32 source[3], dest[3];
5244: Uint16 newsr;
5245:
5246: dest[0] = dsp_core.registers[DSP_REG_A2];
5247: dest[1] = dsp_core.registers[DSP_REG_A1];
5248: dest[2] = dsp_core.registers[DSP_REG_A0];
5249: dsp_abs56(dest);
5250:
5251: source[0] = dsp_core.registers[DSP_REG_B2];
5252: source[1] = dsp_core.registers[DSP_REG_B1];
5253: source[2] = dsp_core.registers[DSP_REG_B0];
5254: dsp_abs56(source);
5255:
5256: newsr = dsp_sub56(source, dest);
5257:
5258: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5259:
5260: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5261: dsp_core.registers[DSP_REG_SR] |= newsr;
5262: }
5263:
5264: static void dsp_cmpm_a_b(void)
5265: {
5266: Uint32 source[3], dest[3];
5267: Uint16 newsr;
5268:
5269: dest[0] = dsp_core.registers[DSP_REG_B2];
5270: dest[1] = dsp_core.registers[DSP_REG_B1];
5271: dest[2] = dsp_core.registers[DSP_REG_B0];
5272: dsp_abs56(dest);
5273:
5274: source[0] = dsp_core.registers[DSP_REG_A2];
5275: source[1] = dsp_core.registers[DSP_REG_A1];
5276: source[2] = dsp_core.registers[DSP_REG_A0];
5277: dsp_abs56(source);
5278:
5279: newsr = dsp_sub56(source, dest);
5280:
5281: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5282:
5283: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5284: dsp_core.registers[DSP_REG_SR] |= newsr;
5285: }
5286:
5287: static void dsp_cmpm_x0_a(void)
5288: {
5289: Uint32 source[3], dest[3];
5290: Uint16 newsr;
5291:
5292: dest[2] = dsp_core.registers[DSP_REG_A0];
5293: dest[1] = dsp_core.registers[DSP_REG_A1];
5294: dest[0] = dsp_core.registers[DSP_REG_A2];
5295: dsp_abs56(dest);
5296:
5297: source[2] = 0;
5298: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 ! root 5299: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5300: dsp_abs56(source);
5301:
5302: newsr = dsp_sub56(source, dest);
5303:
5304: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5305:
5306: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5307: dsp_core.registers[DSP_REG_SR] |= newsr;
5308: }
5309:
5310: static void dsp_cmpm_x0_b(void)
5311: {
5312: Uint32 source[3], dest[3];
5313: Uint16 newsr;
5314:
5315: dest[0] = dsp_core.registers[DSP_REG_B2];
5316: dest[1] = dsp_core.registers[DSP_REG_B1];
5317: dest[2] = dsp_core.registers[DSP_REG_B0];
5318: dsp_abs56(dest);
5319:
5320: source[2] = 0;
5321: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 ! root 5322: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5323: dsp_abs56(source);
5324:
5325: newsr = dsp_sub56(source, dest);
5326:
5327: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5328:
5329: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5330: dsp_core.registers[DSP_REG_SR] |= newsr;
5331: }
5332:
5333: static void dsp_cmpm_y0_a(void)
5334: {
5335: Uint32 source[3], dest[3];
5336: Uint16 newsr;
5337:
5338: dest[2] = dsp_core.registers[DSP_REG_A0];
5339: dest[1] = dsp_core.registers[DSP_REG_A1];
5340: dest[0] = dsp_core.registers[DSP_REG_A2];
5341: dsp_abs56(dest);
5342:
5343: source[2] = 0;
5344: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 ! root 5345: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5346: dsp_abs56(source);
5347:
5348: newsr = dsp_sub56(source, dest);
5349:
5350: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5351:
5352: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5353: dsp_core.registers[DSP_REG_SR] |= newsr;
5354: }
5355:
5356: static void dsp_cmpm_y0_b(void)
5357: {
5358: Uint32 source[3], dest[3];
5359: Uint16 newsr;
5360:
5361: dest[0] = dsp_core.registers[DSP_REG_B2];
5362: dest[1] = dsp_core.registers[DSP_REG_B1];
5363: dest[2] = dsp_core.registers[DSP_REG_B0];
5364: dsp_abs56(dest);
5365:
5366: source[2] = 0;
5367: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 ! root 5368: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5369: dsp_abs56(source);
5370:
5371: newsr = dsp_sub56(source, dest);
5372:
5373: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5374:
5375: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5376: dsp_core.registers[DSP_REG_SR] |= newsr;
5377: }
5378:
5379: static void dsp_cmpm_x1_a(void)
5380: {
5381: Uint32 source[3], dest[3];
5382: Uint16 newsr;
5383:
5384: dest[2] = dsp_core.registers[DSP_REG_A0];
5385: dest[1] = dsp_core.registers[DSP_REG_A1];
5386: dest[0] = dsp_core.registers[DSP_REG_A2];
5387: dsp_abs56(dest);
5388:
5389: source[2] = 0;
5390: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 ! root 5391: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5392: dsp_abs56(source);
5393:
5394: newsr = dsp_sub56(source, dest);
5395:
5396: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5397:
5398: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5399: dsp_core.registers[DSP_REG_SR] |= newsr;
5400: }
5401:
5402: static void dsp_cmpm_x1_b(void)
5403: {
5404: Uint32 source[3], dest[3];
5405: Uint16 newsr;
5406:
5407: dest[0] = dsp_core.registers[DSP_REG_B2];
5408: dest[1] = dsp_core.registers[DSP_REG_B1];
5409: dest[2] = dsp_core.registers[DSP_REG_B0];
5410: dsp_abs56(dest);
5411:
5412: source[2] = 0;
5413: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 ! root 5414: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5415: dsp_abs56(source);
5416:
5417: newsr = dsp_sub56(source, dest);
5418:
5419: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5420:
5421: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5422: dsp_core.registers[DSP_REG_SR] |= newsr;
5423: }
5424:
5425: static void dsp_cmpm_y1_a(void)
5426: {
5427: Uint32 source[3], dest[3];
5428: Uint16 newsr;
5429:
5430: dest[2] = dsp_core.registers[DSP_REG_A0];
5431: dest[1] = dsp_core.registers[DSP_REG_A1];
5432: dest[0] = dsp_core.registers[DSP_REG_A2];
5433: dsp_abs56(dest);
5434:
5435: source[2] = 0;
5436: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 ! root 5437: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5438: dsp_abs56(source);
5439:
5440: newsr = dsp_sub56(source, dest);
5441:
5442: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5443:
5444: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5445: dsp_core.registers[DSP_REG_SR] |= newsr;
5446: }
5447:
5448: static void dsp_cmpm_y1_b(void)
5449: {
5450: Uint32 source[3], dest[3];
5451: Uint16 newsr;
5452:
5453: dest[0] = dsp_core.registers[DSP_REG_B2];
5454: dest[1] = dsp_core.registers[DSP_REG_B1];
5455: dest[2] = dsp_core.registers[DSP_REG_B0];
5456: dsp_abs56(dest);
5457:
5458: source[2] = 0;
5459: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 ! root 5460: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5461: dsp_abs56(source);
5462:
5463: newsr = dsp_sub56(source, dest);
5464:
5465: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5466:
5467: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5468: dsp_core.registers[DSP_REG_SR] |= newsr;
5469: }
5470:
5471: static void dsp_eor_x0_a(void)
5472: {
5473: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X0];
5474: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5475:
5476: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5477: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5478: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5479: }
5480:
5481: static void dsp_eor_x0_b(void)
5482: {
5483: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X0];
5484: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5485:
5486: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5487: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5488: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5489: }
5490:
5491: static void dsp_eor_y0_a(void)
5492: {
5493: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y0];
5494: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5495:
5496: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5497: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5498: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5499: }
5500:
5501: static void dsp_eor_y0_b(void)
5502: {
5503: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y0];
5504: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5505:
5506: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5507: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5508: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5509: }
5510:
5511: static void dsp_eor_x1_a(void)
5512: {
5513: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X1];
5514: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5515:
5516: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5517: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5518: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5519: }
5520:
5521: static void dsp_eor_x1_b(void)
5522: {
5523: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X1];
5524: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5525:
5526: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5527: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5528: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5529: }
5530:
5531: static void dsp_eor_y1_a(void)
5532: {
5533: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y1];
5534: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5535:
5536: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5537: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5538: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5539: }
5540:
5541: static void dsp_eor_y1_b(void)
5542: {
5543: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y1];
5544: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5545:
5546: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5547: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5548: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5549: }
5550:
5551: static void dsp_lsl_a(void)
5552: {
5553: Uint32 newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
5554:
5555: dsp_core.registers[DSP_REG_A1] <<= 1;
5556: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
5557:
5558: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5559: dsp_core.registers[DSP_REG_SR] |= newcarry;
5560: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5561: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5562: }
5563:
5564: static void dsp_lsl_b(void)
5565: {
5566: Uint32 newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
5567:
5568: dsp_core.registers[DSP_REG_B1] <<= 1;
5569: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
5570:
5571: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5572: dsp_core.registers[DSP_REG_SR] |= newcarry;
5573: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5574: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5575: }
5576:
5577: static void dsp_lsr_a(void)
5578: {
5579: Uint32 newcarry = dsp_core.registers[DSP_REG_A1] & 1;
5580: dsp_core.registers[DSP_REG_A1] >>= 1;
5581:
5582: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5583: dsp_core.registers[DSP_REG_SR] |= newcarry;
5584: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5585: }
5586:
5587: static void dsp_lsr_b(void)
5588: {
5589: Uint32 newcarry = dsp_core.registers[DSP_REG_B1] & 1;
5590: dsp_core.registers[DSP_REG_B1] >>= 1;
5591:
5592: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5593: dsp_core.registers[DSP_REG_SR] |= newcarry;
5594: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5595: }
5596:
5597: static void dsp_mac_p_x0_x0_a(void)
5598: {
5599: Uint32 source[3], dest[3];
5600: Uint16 newsr;
5601:
5602: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5603:
5604: dest[0] = dsp_core.registers[DSP_REG_A2];
5605: dest[1] = dsp_core.registers[DSP_REG_A1];
5606: dest[2] = dsp_core.registers[DSP_REG_A0];
5607: newsr = dsp_add56(source, dest);
5608:
5609: dsp_core.registers[DSP_REG_A2] = dest[0];
5610: dsp_core.registers[DSP_REG_A1] = dest[1];
5611: dsp_core.registers[DSP_REG_A0] = dest[2];
5612:
5613: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5614:
5615: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5616: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5617: }
5618:
5619: static void dsp_mac_m_x0_x0_a(void)
5620: {
5621: Uint32 source[3], dest[3];
5622: Uint16 newsr;
5623:
5624: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5625:
5626: dest[0] = dsp_core.registers[DSP_REG_A2];
5627: dest[1] = dsp_core.registers[DSP_REG_A1];
5628: dest[2] = dsp_core.registers[DSP_REG_A0];
5629: newsr = dsp_add56(source, dest);
5630:
5631: dsp_core.registers[DSP_REG_A2] = dest[0];
5632: dsp_core.registers[DSP_REG_A1] = dest[1];
5633: dsp_core.registers[DSP_REG_A0] = dest[2];
5634:
5635: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5636:
5637: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5638: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5639: }
5640: static void dsp_mac_p_x0_x0_b(void)
5641: {
5642: Uint32 source[3], dest[3];
5643: Uint16 newsr;
5644:
5645: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5646:
5647: dest[0] = dsp_core.registers[DSP_REG_B2];
5648: dest[1] = dsp_core.registers[DSP_REG_B1];
5649: dest[2] = dsp_core.registers[DSP_REG_B0];
5650: newsr = dsp_add56(source, dest);
5651:
5652: dsp_core.registers[DSP_REG_B2] = dest[0];
5653: dsp_core.registers[DSP_REG_B1] = dest[1];
5654: dsp_core.registers[DSP_REG_B0] = dest[2];
5655:
5656: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5657:
5658: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5659: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5660: }
5661:
5662: static void dsp_mac_m_x0_x0_b(void)
5663: {
5664: Uint32 source[3], dest[3];
5665: Uint16 newsr;
5666:
5667: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5668:
5669: dest[0] = dsp_core.registers[DSP_REG_B2];
5670: dest[1] = dsp_core.registers[DSP_REG_B1];
5671: dest[2] = dsp_core.registers[DSP_REG_B0];
5672: newsr = dsp_add56(source, dest);
5673:
5674: dsp_core.registers[DSP_REG_B2] = dest[0];
5675: dsp_core.registers[DSP_REG_B1] = dest[1];
5676: dsp_core.registers[DSP_REG_B0] = dest[2];
5677:
5678: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5679:
5680: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5681: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5682: }
5683:
5684: static void dsp_mac_p_y0_y0_a(void)
5685: {
5686: Uint32 source[3], dest[3];
5687: Uint16 newsr;
5688:
5689: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5690:
5691: dest[0] = dsp_core.registers[DSP_REG_A2];
5692: dest[1] = dsp_core.registers[DSP_REG_A1];
5693: dest[2] = dsp_core.registers[DSP_REG_A0];
5694: newsr = dsp_add56(source, dest);
5695:
5696: dsp_core.registers[DSP_REG_A2] = dest[0];
5697: dsp_core.registers[DSP_REG_A1] = dest[1];
5698: dsp_core.registers[DSP_REG_A0] = dest[2];
5699:
5700: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5701:
5702: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5703: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5704: }
5705:
5706: static void dsp_mac_m_y0_y0_a(void)
5707: {
5708: Uint32 source[3], dest[3];
5709: Uint16 newsr;
5710:
5711: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5712:
5713: dest[0] = dsp_core.registers[DSP_REG_A2];
5714: dest[1] = dsp_core.registers[DSP_REG_A1];
5715: dest[2] = dsp_core.registers[DSP_REG_A0];
5716: newsr = dsp_add56(source, dest);
5717:
5718: dsp_core.registers[DSP_REG_A2] = dest[0];
5719: dsp_core.registers[DSP_REG_A1] = dest[1];
5720: dsp_core.registers[DSP_REG_A0] = dest[2];
5721:
5722: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5723:
5724: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5725: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5726: }
5727: static void dsp_mac_p_y0_y0_b(void)
5728: {
5729: Uint32 source[3], dest[3];
5730: Uint16 newsr;
5731:
5732: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5733:
5734: dest[0] = dsp_core.registers[DSP_REG_B2];
5735: dest[1] = dsp_core.registers[DSP_REG_B1];
5736: dest[2] = dsp_core.registers[DSP_REG_B0];
5737: newsr = dsp_add56(source, dest);
5738:
5739: dsp_core.registers[DSP_REG_B2] = dest[0];
5740: dsp_core.registers[DSP_REG_B1] = dest[1];
5741: dsp_core.registers[DSP_REG_B0] = dest[2];
5742:
5743: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5744:
5745: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5746: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5747: }
5748:
5749: static void dsp_mac_m_y0_y0_b(void)
5750: {
5751: Uint32 source[3], dest[3];
5752: Uint16 newsr;
5753:
5754: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5755:
5756: dest[0] = dsp_core.registers[DSP_REG_B2];
5757: dest[1] = dsp_core.registers[DSP_REG_B1];
5758: dest[2] = dsp_core.registers[DSP_REG_B0];
5759: newsr = dsp_add56(source, dest);
5760:
5761: dsp_core.registers[DSP_REG_B2] = dest[0];
5762: dsp_core.registers[DSP_REG_B1] = dest[1];
5763: dsp_core.registers[DSP_REG_B0] = dest[2];
5764:
5765: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5766:
5767: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5768: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5769: }
5770:
5771: static void dsp_mac_p_x1_x0_a(void)
5772: {
5773: Uint32 source[3], dest[3];
5774: Uint16 newsr;
5775:
5776: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5777:
5778: dest[0] = dsp_core.registers[DSP_REG_A2];
5779: dest[1] = dsp_core.registers[DSP_REG_A1];
5780: dest[2] = dsp_core.registers[DSP_REG_A0];
5781: newsr = dsp_add56(source, dest);
5782:
5783: dsp_core.registers[DSP_REG_A2] = dest[0];
5784: dsp_core.registers[DSP_REG_A1] = dest[1];
5785: dsp_core.registers[DSP_REG_A0] = dest[2];
5786:
5787: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5788:
5789: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5790: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5791: }
5792:
5793: static void dsp_mac_m_x1_x0_a(void)
5794: {
5795: Uint32 source[3], dest[3];
5796: Uint16 newsr;
5797:
5798: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5799:
5800: dest[0] = dsp_core.registers[DSP_REG_A2];
5801: dest[1] = dsp_core.registers[DSP_REG_A1];
5802: dest[2] = dsp_core.registers[DSP_REG_A0];
5803: newsr = dsp_add56(source, dest);
5804:
5805: dsp_core.registers[DSP_REG_A2] = dest[0];
5806: dsp_core.registers[DSP_REG_A1] = dest[1];
5807: dsp_core.registers[DSP_REG_A0] = dest[2];
5808:
5809: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5810:
5811: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5812: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5813: }
5814:
5815: static void dsp_mac_p_x1_x0_b(void)
5816: {
5817: Uint32 source[3], dest[3];
5818: Uint16 newsr;
5819:
5820: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5821:
5822: dest[0] = dsp_core.registers[DSP_REG_B2];
5823: dest[1] = dsp_core.registers[DSP_REG_B1];
5824: dest[2] = dsp_core.registers[DSP_REG_B0];
5825: newsr = dsp_add56(source, dest);
5826:
5827: dsp_core.registers[DSP_REG_B2] = dest[0];
5828: dsp_core.registers[DSP_REG_B1] = dest[1];
5829: dsp_core.registers[DSP_REG_B0] = dest[2];
5830:
5831: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5832:
5833: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5834: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5835: }
5836:
5837: static void dsp_mac_m_x1_x0_b(void)
5838: {
5839: Uint32 source[3], dest[3];
5840: Uint16 newsr;
5841:
5842: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5843:
5844: dest[0] = dsp_core.registers[DSP_REG_B2];
5845: dest[1] = dsp_core.registers[DSP_REG_B1];
5846: dest[2] = dsp_core.registers[DSP_REG_B0];
5847: newsr = dsp_add56(source, dest);
5848:
5849: dsp_core.registers[DSP_REG_B2] = dest[0];
5850: dsp_core.registers[DSP_REG_B1] = dest[1];
5851: dsp_core.registers[DSP_REG_B0] = dest[2];
5852:
5853: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5854:
5855: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5856: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5857: }
5858:
5859: static void dsp_mac_p_y1_y0_a(void)
5860: {
5861: Uint32 source[3], dest[3];
5862: Uint16 newsr;
5863:
5864: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5865:
5866: dest[0] = dsp_core.registers[DSP_REG_A2];
5867: dest[1] = dsp_core.registers[DSP_REG_A1];
5868: dest[2] = dsp_core.registers[DSP_REG_A0];
5869: newsr = dsp_add56(source, dest);
5870:
5871: dsp_core.registers[DSP_REG_A2] = dest[0];
5872: dsp_core.registers[DSP_REG_A1] = dest[1];
5873: dsp_core.registers[DSP_REG_A0] = dest[2];
5874:
5875: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5876:
5877: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5878: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5879: }
5880:
5881: static void dsp_mac_m_y1_y0_a(void)
5882: {
5883: Uint32 source[3], dest[3];
5884: Uint16 newsr;
5885:
5886: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5887:
5888: dest[0] = dsp_core.registers[DSP_REG_A2];
5889: dest[1] = dsp_core.registers[DSP_REG_A1];
5890: dest[2] = dsp_core.registers[DSP_REG_A0];
5891: newsr = dsp_add56(source, dest);
5892:
5893: dsp_core.registers[DSP_REG_A2] = dest[0];
5894: dsp_core.registers[DSP_REG_A1] = dest[1];
5895: dsp_core.registers[DSP_REG_A0] = dest[2];
5896:
5897: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5898:
5899: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5900: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5901: }
5902:
5903: static void dsp_mac_p_y1_y0_b(void)
5904: {
5905: Uint32 source[3], dest[3];
5906: Uint16 newsr;
5907:
5908: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5909:
5910: dest[0] = dsp_core.registers[DSP_REG_B2];
5911: dest[1] = dsp_core.registers[DSP_REG_B1];
5912: dest[2] = dsp_core.registers[DSP_REG_B0];
5913: newsr = dsp_add56(source, dest);
5914:
5915: dsp_core.registers[DSP_REG_B2] = dest[0];
5916: dsp_core.registers[DSP_REG_B1] = dest[1];
5917: dsp_core.registers[DSP_REG_B0] = dest[2];
5918:
5919: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5920:
5921: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5922: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5923: }
5924:
5925: static void dsp_mac_m_y1_y0_b(void)
5926: {
5927: Uint32 source[3], dest[3];
5928: Uint16 newsr;
5929:
5930: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5931:
5932: dest[0] = dsp_core.registers[DSP_REG_B2];
5933: dest[1] = dsp_core.registers[DSP_REG_B1];
5934: dest[2] = dsp_core.registers[DSP_REG_B0];
5935: newsr = dsp_add56(source, dest);
5936:
5937: dsp_core.registers[DSP_REG_B2] = dest[0];
5938: dsp_core.registers[DSP_REG_B1] = dest[1];
5939: dsp_core.registers[DSP_REG_B0] = dest[2];
5940:
5941: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5942:
5943: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5944: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5945: }
5946:
5947: static void dsp_mac_p_x0_y1_a(void)
5948: {
5949: Uint32 source[3], dest[3];
5950: Uint16 newsr;
5951:
5952: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
5953:
5954: dest[0] = dsp_core.registers[DSP_REG_A2];
5955: dest[1] = dsp_core.registers[DSP_REG_A1];
5956: dest[2] = dsp_core.registers[DSP_REG_A0];
5957: newsr = dsp_add56(source, dest);
5958:
5959: dsp_core.registers[DSP_REG_A2] = dest[0];
5960: dsp_core.registers[DSP_REG_A1] = dest[1];
5961: dsp_core.registers[DSP_REG_A0] = dest[2];
5962:
5963: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5964:
5965: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5966: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5967: }
5968:
5969: static void dsp_mac_m_x0_y1_a(void)
5970: {
5971: Uint32 source[3], dest[3];
5972: Uint16 newsr;
5973:
5974: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
5975:
5976: dest[0] = dsp_core.registers[DSP_REG_A2];
5977: dest[1] = dsp_core.registers[DSP_REG_A1];
5978: dest[2] = dsp_core.registers[DSP_REG_A0];
5979: newsr = dsp_add56(source, dest);
5980:
5981: dsp_core.registers[DSP_REG_A2] = dest[0];
5982: dsp_core.registers[DSP_REG_A1] = dest[1];
5983: dsp_core.registers[DSP_REG_A0] = dest[2];
5984:
5985: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5986:
5987: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5988: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5989: }
5990:
5991: static void dsp_mac_p_x0_y1_b(void)
5992: {
5993: Uint32 source[3], dest[3];
5994: Uint16 newsr;
5995:
5996: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
5997:
5998: dest[0] = dsp_core.registers[DSP_REG_B2];
5999: dest[1] = dsp_core.registers[DSP_REG_B1];
6000: dest[2] = dsp_core.registers[DSP_REG_B0];
6001: newsr = dsp_add56(source, dest);
6002:
6003: dsp_core.registers[DSP_REG_B2] = dest[0];
6004: dsp_core.registers[DSP_REG_B1] = dest[1];
6005: dsp_core.registers[DSP_REG_B0] = dest[2];
6006:
6007: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6008:
6009: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6010: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6011: }
6012:
6013: static void dsp_mac_m_x0_y1_b(void)
6014: {
6015: Uint32 source[3], dest[3];
6016: Uint16 newsr;
6017:
6018: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6019:
6020: dest[0] = dsp_core.registers[DSP_REG_B2];
6021: dest[1] = dsp_core.registers[DSP_REG_B1];
6022: dest[2] = dsp_core.registers[DSP_REG_B0];
6023: newsr = dsp_add56(source, dest);
6024:
6025: dsp_core.registers[DSP_REG_B2] = dest[0];
6026: dsp_core.registers[DSP_REG_B1] = dest[1];
6027: dsp_core.registers[DSP_REG_B0] = dest[2];
6028:
6029: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6030:
6031: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6032: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6033: }
6034:
6035: static void dsp_mac_p_y0_x0_a(void)
6036: {
6037: Uint32 source[3], dest[3];
6038: Uint16 newsr;
6039:
6040: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6041:
6042: dest[0] = dsp_core.registers[DSP_REG_A2];
6043: dest[1] = dsp_core.registers[DSP_REG_A1];
6044: dest[2] = dsp_core.registers[DSP_REG_A0];
6045: newsr = dsp_add56(source, dest);
6046:
6047: dsp_core.registers[DSP_REG_A2] = dest[0];
6048: dsp_core.registers[DSP_REG_A1] = dest[1];
6049: dsp_core.registers[DSP_REG_A0] = dest[2];
6050:
6051: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6052:
6053: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6054: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6055: }
6056:
6057: static void dsp_mac_m_y0_x0_a(void)
6058: {
6059: Uint32 source[3], dest[3];
6060: Uint16 newsr;
6061:
6062: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6063:
6064: dest[0] = dsp_core.registers[DSP_REG_A2];
6065: dest[1] = dsp_core.registers[DSP_REG_A1];
6066: dest[2] = dsp_core.registers[DSP_REG_A0];
6067: newsr = dsp_add56(source, dest);
6068:
6069: dsp_core.registers[DSP_REG_A2] = dest[0];
6070: dsp_core.registers[DSP_REG_A1] = dest[1];
6071: dsp_core.registers[DSP_REG_A0] = dest[2];
6072:
6073: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6074:
6075: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6076: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6077: }
6078:
6079: static void dsp_mac_p_y0_x0_b(void)
6080: {
6081: Uint32 source[3], dest[3];
6082: Uint16 newsr;
6083:
6084: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6085:
6086: dest[0] = dsp_core.registers[DSP_REG_B2];
6087: dest[1] = dsp_core.registers[DSP_REG_B1];
6088: dest[2] = dsp_core.registers[DSP_REG_B0];
6089: newsr = dsp_add56(source, dest);
6090:
6091: dsp_core.registers[DSP_REG_B2] = dest[0];
6092: dsp_core.registers[DSP_REG_B1] = dest[1];
6093: dsp_core.registers[DSP_REG_B0] = dest[2];
6094:
6095: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6096:
6097: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6098: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6099: }
6100:
6101: static void dsp_mac_m_y0_x0_b(void)
6102: {
6103: Uint32 source[3], dest[3];
6104: Uint16 newsr;
6105:
6106: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6107:
6108: dest[0] = dsp_core.registers[DSP_REG_B2];
6109: dest[1] = dsp_core.registers[DSP_REG_B1];
6110: dest[2] = dsp_core.registers[DSP_REG_B0];
6111: newsr = dsp_add56(source, dest);
6112:
6113: dsp_core.registers[DSP_REG_B2] = dest[0];
6114: dsp_core.registers[DSP_REG_B1] = dest[1];
6115: dsp_core.registers[DSP_REG_B0] = dest[2];
6116:
6117: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6118:
6119: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6120: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6121: }
6122:
6123: static void dsp_mac_p_x1_y0_a(void)
6124: {
6125: Uint32 source[3], dest[3];
6126: Uint16 newsr;
6127:
6128: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6129:
6130: dest[0] = dsp_core.registers[DSP_REG_A2];
6131: dest[1] = dsp_core.registers[DSP_REG_A1];
6132: dest[2] = dsp_core.registers[DSP_REG_A0];
6133: newsr = dsp_add56(source, dest);
6134:
6135: dsp_core.registers[DSP_REG_A2] = dest[0];
6136: dsp_core.registers[DSP_REG_A1] = dest[1];
6137: dsp_core.registers[DSP_REG_A0] = dest[2];
6138:
6139: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6140:
6141: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6142: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6143: }
6144:
6145: static void dsp_mac_m_x1_y0_a(void)
6146: {
6147: Uint32 source[3], dest[3];
6148: Uint16 newsr;
6149:
6150: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6151:
6152: dest[0] = dsp_core.registers[DSP_REG_A2];
6153: dest[1] = dsp_core.registers[DSP_REG_A1];
6154: dest[2] = dsp_core.registers[DSP_REG_A0];
6155: newsr = dsp_add56(source, dest);
6156:
6157: dsp_core.registers[DSP_REG_A2] = dest[0];
6158: dsp_core.registers[DSP_REG_A1] = dest[1];
6159: dsp_core.registers[DSP_REG_A0] = dest[2];
6160:
6161: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6162:
6163: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6164: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6165: }
6166:
6167: static void dsp_mac_p_x1_y0_b(void)
6168: {
6169: Uint32 source[3], dest[3];
6170: Uint16 newsr;
6171:
6172: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6173:
6174: dest[0] = dsp_core.registers[DSP_REG_B2];
6175: dest[1] = dsp_core.registers[DSP_REG_B1];
6176: dest[2] = dsp_core.registers[DSP_REG_B0];
6177: newsr = dsp_add56(source, dest);
6178:
6179: dsp_core.registers[DSP_REG_B2] = dest[0];
6180: dsp_core.registers[DSP_REG_B1] = dest[1];
6181: dsp_core.registers[DSP_REG_B0] = dest[2];
6182:
6183: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6184:
6185: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6186: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6187: }
6188:
6189: static void dsp_mac_m_x1_y0_b(void)
6190: {
6191: Uint32 source[3], dest[3];
6192: Uint16 newsr;
6193:
6194: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6195:
6196: dest[0] = dsp_core.registers[DSP_REG_B2];
6197: dest[1] = dsp_core.registers[DSP_REG_B1];
6198: dest[2] = dsp_core.registers[DSP_REG_B0];
6199: newsr = dsp_add56(source, dest);
6200:
6201: dsp_core.registers[DSP_REG_B2] = dest[0];
6202: dsp_core.registers[DSP_REG_B1] = dest[1];
6203: dsp_core.registers[DSP_REG_B0] = dest[2];
6204:
6205: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6206:
6207: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6208: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6209: }
6210:
6211: static void dsp_mac_p_y1_x1_a(void)
6212: {
6213: Uint32 source[3], dest[3];
6214: Uint16 newsr;
6215:
6216: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6217:
6218: dest[0] = dsp_core.registers[DSP_REG_A2];
6219: dest[1] = dsp_core.registers[DSP_REG_A1];
6220: dest[2] = dsp_core.registers[DSP_REG_A0];
6221: newsr = dsp_add56(source, dest);
6222:
6223: dsp_core.registers[DSP_REG_A2] = dest[0];
6224: dsp_core.registers[DSP_REG_A1] = dest[1];
6225: dsp_core.registers[DSP_REG_A0] = dest[2];
6226:
6227: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6228:
6229: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6230: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6231: }
6232:
6233: static void dsp_mac_m_y1_x1_a(void)
6234: {
6235: Uint32 source[3], dest[3];
6236: Uint16 newsr;
6237:
6238: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6239:
6240: dest[0] = dsp_core.registers[DSP_REG_A2];
6241: dest[1] = dsp_core.registers[DSP_REG_A1];
6242: dest[2] = dsp_core.registers[DSP_REG_A0];
6243: newsr = dsp_add56(source, dest);
6244:
6245: dsp_core.registers[DSP_REG_A2] = dest[0];
6246: dsp_core.registers[DSP_REG_A1] = dest[1];
6247: dsp_core.registers[DSP_REG_A0] = dest[2];
6248:
6249: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6250:
6251: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6252: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6253: }
6254:
6255: static void dsp_mac_p_y1_x1_b(void)
6256: {
6257: Uint32 source[3], dest[3];
6258: Uint16 newsr;
6259:
6260: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6261:
6262: dest[0] = dsp_core.registers[DSP_REG_B2];
6263: dest[1] = dsp_core.registers[DSP_REG_B1];
6264: dest[2] = dsp_core.registers[DSP_REG_B0];
6265: newsr = dsp_add56(source, dest);
6266:
6267: dsp_core.registers[DSP_REG_B2] = dest[0];
6268: dsp_core.registers[DSP_REG_B1] = dest[1];
6269: dsp_core.registers[DSP_REG_B0] = dest[2];
6270:
6271: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6272:
6273: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6274: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6275: }
6276:
6277: static void dsp_mac_m_y1_x1_b(void)
6278: {
6279: Uint32 source[3], dest[3];
6280: Uint16 newsr;
6281:
6282: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6283:
6284: dest[0] = dsp_core.registers[DSP_REG_B2];
6285: dest[1] = dsp_core.registers[DSP_REG_B1];
6286: dest[2] = dsp_core.registers[DSP_REG_B0];
6287: newsr = dsp_add56(source, dest);
6288:
6289: dsp_core.registers[DSP_REG_B2] = dest[0];
6290: dsp_core.registers[DSP_REG_B1] = dest[1];
6291: dsp_core.registers[DSP_REG_B0] = dest[2];
6292:
6293: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6294:
6295: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6296: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6297: }
6298:
6299: static void dsp_macr_p_x0_x0_a(void)
6300: {
6301: Uint32 source[3], dest[3];
6302: Uint16 newsr;
6303:
6304: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6305:
6306: dest[0] = dsp_core.registers[DSP_REG_A2];
6307: dest[1] = dsp_core.registers[DSP_REG_A1];
6308: dest[2] = dsp_core.registers[DSP_REG_A0];
6309: newsr = dsp_add56(source, dest);
6310:
6311: dsp_rnd56(dest);
6312:
6313: dsp_core.registers[DSP_REG_A2] = dest[0];
6314: dsp_core.registers[DSP_REG_A1] = dest[1];
6315: dsp_core.registers[DSP_REG_A0] = dest[2];
6316:
6317: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6318:
6319: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6320: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6321: }
6322:
6323: static void dsp_macr_m_x0_x0_a(void)
6324: {
6325: Uint32 source[3], dest[3];
6326: Uint16 newsr;
6327:
6328: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6329:
6330: dest[0] = dsp_core.registers[DSP_REG_A2];
6331: dest[1] = dsp_core.registers[DSP_REG_A1];
6332: dest[2] = dsp_core.registers[DSP_REG_A0];
6333: newsr = dsp_add56(source, dest);
6334:
6335: dsp_rnd56(dest);
6336:
6337: dsp_core.registers[DSP_REG_A2] = dest[0];
6338: dsp_core.registers[DSP_REG_A1] = dest[1];
6339: dsp_core.registers[DSP_REG_A0] = dest[2];
6340:
6341: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6342:
6343: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6344: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6345: }
6346: static void dsp_macr_p_x0_x0_b(void)
6347: {
6348: Uint32 source[3], dest[3];
6349: Uint16 newsr;
6350:
6351: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6352:
6353: dest[0] = dsp_core.registers[DSP_REG_B2];
6354: dest[1] = dsp_core.registers[DSP_REG_B1];
6355: dest[2] = dsp_core.registers[DSP_REG_B0];
6356: newsr = dsp_add56(source, dest);
6357:
6358: dsp_rnd56(dest);
6359:
6360: dsp_core.registers[DSP_REG_B2] = dest[0];
6361: dsp_core.registers[DSP_REG_B1] = dest[1];
6362: dsp_core.registers[DSP_REG_B0] = dest[2];
6363:
6364: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6365:
6366: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6367: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6368: }
6369:
6370: static void dsp_macr_m_x0_x0_b(void)
6371: {
6372: Uint32 source[3], dest[3];
6373: Uint16 newsr;
6374:
6375: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6376:
6377: dest[0] = dsp_core.registers[DSP_REG_B2];
6378: dest[1] = dsp_core.registers[DSP_REG_B1];
6379: dest[2] = dsp_core.registers[DSP_REG_B0];
6380: newsr = dsp_add56(source, dest);
6381:
6382: dsp_rnd56(dest);
6383:
6384: dsp_core.registers[DSP_REG_B2] = dest[0];
6385: dsp_core.registers[DSP_REG_B1] = dest[1];
6386: dsp_core.registers[DSP_REG_B0] = dest[2];
6387:
6388: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6389:
6390: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6391: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6392: }
6393:
6394: static void dsp_macr_p_y0_y0_a(void)
6395: {
6396: Uint32 source[3], dest[3];
6397: Uint16 newsr;
6398:
6399: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6400:
6401: dest[0] = dsp_core.registers[DSP_REG_A2];
6402: dest[1] = dsp_core.registers[DSP_REG_A1];
6403: dest[2] = dsp_core.registers[DSP_REG_A0];
6404: newsr = dsp_add56(source, dest);
6405:
6406: dsp_rnd56(dest);
6407:
6408: dsp_core.registers[DSP_REG_A2] = dest[0];
6409: dsp_core.registers[DSP_REG_A1] = dest[1];
6410: dsp_core.registers[DSP_REG_A0] = dest[2];
6411:
6412: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6413:
6414: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6415: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6416: }
6417:
6418: static void dsp_macr_m_y0_y0_a(void)
6419: {
6420: Uint32 source[3], dest[3];
6421: Uint16 newsr;
6422:
6423: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6424:
6425: dest[0] = dsp_core.registers[DSP_REG_A2];
6426: dest[1] = dsp_core.registers[DSP_REG_A1];
6427: dest[2] = dsp_core.registers[DSP_REG_A0];
6428: newsr = dsp_add56(source, dest);
6429:
6430: dsp_rnd56(dest);
6431:
6432: dsp_core.registers[DSP_REG_A2] = dest[0];
6433: dsp_core.registers[DSP_REG_A1] = dest[1];
6434: dsp_core.registers[DSP_REG_A0] = dest[2];
6435:
6436: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6437:
6438: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6439: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6440: }
6441: static void dsp_macr_p_y0_y0_b(void)
6442: {
6443: Uint32 source[3], dest[3];
6444: Uint16 newsr;
6445:
6446: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6447:
6448: dest[0] = dsp_core.registers[DSP_REG_B2];
6449: dest[1] = dsp_core.registers[DSP_REG_B1];
6450: dest[2] = dsp_core.registers[DSP_REG_B0];
6451: newsr = dsp_add56(source, dest);
6452:
6453: dsp_rnd56(dest);
6454:
6455: dsp_core.registers[DSP_REG_B2] = dest[0];
6456: dsp_core.registers[DSP_REG_B1] = dest[1];
6457: dsp_core.registers[DSP_REG_B0] = dest[2];
6458:
6459: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6460:
6461: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6462: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6463: }
6464:
6465: static void dsp_macr_m_y0_y0_b(void)
6466: {
6467: Uint32 source[3], dest[3];
6468: Uint16 newsr;
6469:
6470: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6471:
6472: dest[0] = dsp_core.registers[DSP_REG_B2];
6473: dest[1] = dsp_core.registers[DSP_REG_B1];
6474: dest[2] = dsp_core.registers[DSP_REG_B0];
6475: newsr = dsp_add56(source, dest);
6476:
6477: dsp_rnd56(dest);
6478:
6479: dsp_core.registers[DSP_REG_B2] = dest[0];
6480: dsp_core.registers[DSP_REG_B1] = dest[1];
6481: dsp_core.registers[DSP_REG_B0] = dest[2];
6482:
6483: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6484:
6485: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6486: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6487: }
6488:
6489: static void dsp_macr_p_x1_x0_a(void)
6490: {
6491: Uint32 source[3], dest[3];
6492: Uint16 newsr;
6493:
6494: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6495:
6496: dest[0] = dsp_core.registers[DSP_REG_A2];
6497: dest[1] = dsp_core.registers[DSP_REG_A1];
6498: dest[2] = dsp_core.registers[DSP_REG_A0];
6499: newsr = dsp_add56(source, dest);
6500:
6501: dsp_rnd56(dest);
6502:
6503: dsp_core.registers[DSP_REG_A2] = dest[0];
6504: dsp_core.registers[DSP_REG_A1] = dest[1];
6505: dsp_core.registers[DSP_REG_A0] = dest[2];
6506:
6507: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6508:
6509: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6510: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6511: }
6512:
6513: static void dsp_macr_m_x1_x0_a(void)
6514: {
6515: Uint32 source[3], dest[3];
6516: Uint16 newsr;
6517:
6518: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6519:
6520: dest[0] = dsp_core.registers[DSP_REG_A2];
6521: dest[1] = dsp_core.registers[DSP_REG_A1];
6522: dest[2] = dsp_core.registers[DSP_REG_A0];
6523: newsr = dsp_add56(source, dest);
6524:
6525: dsp_rnd56(dest);
6526:
6527: dsp_core.registers[DSP_REG_A2] = dest[0];
6528: dsp_core.registers[DSP_REG_A1] = dest[1];
6529: dsp_core.registers[DSP_REG_A0] = dest[2];
6530:
6531: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6532:
6533: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6534: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6535: }
6536:
6537: static void dsp_macr_p_x1_x0_b(void)
6538: {
6539: Uint32 source[3], dest[3];
6540: Uint16 newsr;
6541:
6542: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6543:
6544: dest[0] = dsp_core.registers[DSP_REG_B2];
6545: dest[1] = dsp_core.registers[DSP_REG_B1];
6546: dest[2] = dsp_core.registers[DSP_REG_B0];
6547: newsr = dsp_add56(source, dest);
6548:
6549: dsp_rnd56(dest);
6550:
6551: dsp_core.registers[DSP_REG_B2] = dest[0];
6552: dsp_core.registers[DSP_REG_B1] = dest[1];
6553: dsp_core.registers[DSP_REG_B0] = dest[2];
6554:
6555: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6556:
6557: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6558: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6559: }
6560:
6561: static void dsp_macr_m_x1_x0_b(void)
6562: {
6563: Uint32 source[3], dest[3];
6564: Uint16 newsr;
6565:
6566: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6567:
6568: dest[0] = dsp_core.registers[DSP_REG_B2];
6569: dest[1] = dsp_core.registers[DSP_REG_B1];
6570: dest[2] = dsp_core.registers[DSP_REG_B0];
6571: newsr = dsp_add56(source, dest);
6572:
6573: dsp_rnd56(dest);
6574:
6575: dsp_core.registers[DSP_REG_B2] = dest[0];
6576: dsp_core.registers[DSP_REG_B1] = dest[1];
6577: dsp_core.registers[DSP_REG_B0] = dest[2];
6578:
6579: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6580:
6581: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6582: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6583: }
6584:
6585: static void dsp_macr_p_y1_y0_a(void)
6586: {
6587: Uint32 source[3], dest[3];
6588: Uint16 newsr;
6589:
6590: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6591:
6592: dest[0] = dsp_core.registers[DSP_REG_A2];
6593: dest[1] = dsp_core.registers[DSP_REG_A1];
6594: dest[2] = dsp_core.registers[DSP_REG_A0];
6595: newsr = dsp_add56(source, dest);
6596:
6597: dsp_rnd56(dest);
6598:
6599: dsp_core.registers[DSP_REG_A2] = dest[0];
6600: dsp_core.registers[DSP_REG_A1] = dest[1];
6601: dsp_core.registers[DSP_REG_A0] = dest[2];
6602:
6603: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6604:
6605: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6606: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6607: }
6608:
6609: static void dsp_macr_m_y1_y0_a(void)
6610: {
6611: Uint32 source[3], dest[3];
6612: Uint16 newsr;
6613:
6614: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6615:
6616: dest[0] = dsp_core.registers[DSP_REG_A2];
6617: dest[1] = dsp_core.registers[DSP_REG_A1];
6618: dest[2] = dsp_core.registers[DSP_REG_A0];
6619: newsr = dsp_add56(source, dest);
6620:
6621: dsp_rnd56(dest);
6622:
6623: dsp_core.registers[DSP_REG_A2] = dest[0];
6624: dsp_core.registers[DSP_REG_A1] = dest[1];
6625: dsp_core.registers[DSP_REG_A0] = dest[2];
6626:
6627: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6628:
6629: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6630: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6631: }
6632:
6633: static void dsp_macr_p_y1_y0_b(void)
6634: {
6635: Uint32 source[3], dest[3];
6636: Uint16 newsr;
6637:
6638: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6639:
6640: dest[0] = dsp_core.registers[DSP_REG_B2];
6641: dest[1] = dsp_core.registers[DSP_REG_B1];
6642: dest[2] = dsp_core.registers[DSP_REG_B0];
6643: newsr = dsp_add56(source, dest);
6644:
6645: dsp_rnd56(dest);
6646:
6647: dsp_core.registers[DSP_REG_B2] = dest[0];
6648: dsp_core.registers[DSP_REG_B1] = dest[1];
6649: dsp_core.registers[DSP_REG_B0] = dest[2];
6650:
6651: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6652:
6653: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6654: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6655: }
6656:
6657: static void dsp_macr_m_y1_y0_b(void)
6658: {
6659: Uint32 source[3], dest[3];
6660: Uint16 newsr;
6661:
6662: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6663:
6664: dest[0] = dsp_core.registers[DSP_REG_B2];
6665: dest[1] = dsp_core.registers[DSP_REG_B1];
6666: dest[2] = dsp_core.registers[DSP_REG_B0];
6667: newsr = dsp_add56(source, dest);
6668:
6669: dsp_rnd56(dest);
6670:
6671: dsp_core.registers[DSP_REG_B2] = dest[0];
6672: dsp_core.registers[DSP_REG_B1] = dest[1];
6673: dsp_core.registers[DSP_REG_B0] = dest[2];
6674:
6675: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6676:
6677: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6678: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6679: }
6680:
6681: static void dsp_macr_p_x0_y1_a(void)
6682: {
6683: Uint32 source[3], dest[3];
6684: Uint16 newsr;
6685:
6686: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6687:
6688: dest[0] = dsp_core.registers[DSP_REG_A2];
6689: dest[1] = dsp_core.registers[DSP_REG_A1];
6690: dest[2] = dsp_core.registers[DSP_REG_A0];
6691: newsr = dsp_add56(source, dest);
6692:
6693: dsp_rnd56(dest);
6694:
6695: dsp_core.registers[DSP_REG_A2] = dest[0];
6696: dsp_core.registers[DSP_REG_A1] = dest[1];
6697: dsp_core.registers[DSP_REG_A0] = dest[2];
6698:
6699: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6700:
6701: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6702: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6703: }
6704:
6705: static void dsp_macr_m_x0_y1_a(void)
6706: {
6707: Uint32 source[3], dest[3];
6708: Uint16 newsr;
6709:
6710: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6711:
6712: dest[0] = dsp_core.registers[DSP_REG_A2];
6713: dest[1] = dsp_core.registers[DSP_REG_A1];
6714: dest[2] = dsp_core.registers[DSP_REG_A0];
6715: newsr = dsp_add56(source, dest);
6716:
6717: dsp_rnd56(dest);
6718:
6719: dsp_core.registers[DSP_REG_A2] = dest[0];
6720: dsp_core.registers[DSP_REG_A1] = dest[1];
6721: dsp_core.registers[DSP_REG_A0] = dest[2];
6722:
6723: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6724:
6725: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6726: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6727: }
6728:
6729: static void dsp_macr_p_x0_y1_b(void)
6730: {
6731: Uint32 source[3], dest[3];
6732: Uint16 newsr;
6733:
6734: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6735:
6736: dest[0] = dsp_core.registers[DSP_REG_B2];
6737: dest[1] = dsp_core.registers[DSP_REG_B1];
6738: dest[2] = dsp_core.registers[DSP_REG_B0];
6739: newsr = dsp_add56(source, dest);
6740:
6741: dsp_rnd56(dest);
6742:
6743: dsp_core.registers[DSP_REG_B2] = dest[0];
6744: dsp_core.registers[DSP_REG_B1] = dest[1];
6745: dsp_core.registers[DSP_REG_B0] = dest[2];
6746:
6747: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6748:
6749: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6750: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6751: }
6752:
6753: static void dsp_macr_m_x0_y1_b(void)
6754: {
6755: Uint32 source[3], dest[3];
6756: Uint16 newsr;
6757:
6758: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6759:
6760: dest[0] = dsp_core.registers[DSP_REG_B2];
6761: dest[1] = dsp_core.registers[DSP_REG_B1];
6762: dest[2] = dsp_core.registers[DSP_REG_B0];
6763: newsr = dsp_add56(source, dest);
6764:
6765: dsp_rnd56(dest);
6766:
6767: dsp_core.registers[DSP_REG_B2] = dest[0];
6768: dsp_core.registers[DSP_REG_B1] = dest[1];
6769: dsp_core.registers[DSP_REG_B0] = dest[2];
6770:
6771: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6772:
6773: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6774: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6775: }
6776:
6777: static void dsp_macr_p_y0_x0_a(void)
6778: {
6779: Uint32 source[3], dest[3];
6780: Uint16 newsr;
6781:
6782: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6783:
6784: dest[0] = dsp_core.registers[DSP_REG_A2];
6785: dest[1] = dsp_core.registers[DSP_REG_A1];
6786: dest[2] = dsp_core.registers[DSP_REG_A0];
6787: newsr = dsp_add56(source, dest);
6788:
6789: dsp_rnd56(dest);
6790:
6791: dsp_core.registers[DSP_REG_A2] = dest[0];
6792: dsp_core.registers[DSP_REG_A1] = dest[1];
6793: dsp_core.registers[DSP_REG_A0] = dest[2];
6794:
6795: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6796:
6797: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6798: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6799: }
6800:
6801: static void dsp_macr_m_y0_x0_a(void)
6802: {
6803: Uint32 source[3], dest[3];
6804: Uint16 newsr;
6805:
6806: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6807:
6808: dest[0] = dsp_core.registers[DSP_REG_A2];
6809: dest[1] = dsp_core.registers[DSP_REG_A1];
6810: dest[2] = dsp_core.registers[DSP_REG_A0];
6811: newsr = dsp_add56(source, dest);
6812:
6813: dsp_rnd56(dest);
6814:
6815: dsp_core.registers[DSP_REG_A2] = dest[0];
6816: dsp_core.registers[DSP_REG_A1] = dest[1];
6817: dsp_core.registers[DSP_REG_A0] = dest[2];
6818:
6819: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6820:
6821: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6822: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6823: }
6824:
6825: static void dsp_macr_p_y0_x0_b(void)
6826: {
6827: Uint32 source[3], dest[3];
6828: Uint16 newsr;
6829:
6830: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6831:
6832: dest[0] = dsp_core.registers[DSP_REG_B2];
6833: dest[1] = dsp_core.registers[DSP_REG_B1];
6834: dest[2] = dsp_core.registers[DSP_REG_B0];
6835: newsr = dsp_add56(source, dest);
6836:
6837: dsp_rnd56(dest);
6838:
6839: dsp_core.registers[DSP_REG_B2] = dest[0];
6840: dsp_core.registers[DSP_REG_B1] = dest[1];
6841: dsp_core.registers[DSP_REG_B0] = dest[2];
6842:
6843: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6844:
6845: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6846: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6847: }
6848:
6849: static void dsp_macr_m_y0_x0_b(void)
6850: {
6851: Uint32 source[3], dest[3];
6852: Uint16 newsr;
6853:
6854: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6855:
6856: dest[0] = dsp_core.registers[DSP_REG_B2];
6857: dest[1] = dsp_core.registers[DSP_REG_B1];
6858: dest[2] = dsp_core.registers[DSP_REG_B0];
6859: newsr = dsp_add56(source, dest);
6860:
6861: dsp_rnd56(dest);
6862:
6863: dsp_core.registers[DSP_REG_B2] = dest[0];
6864: dsp_core.registers[DSP_REG_B1] = dest[1];
6865: dsp_core.registers[DSP_REG_B0] = dest[2];
6866:
6867: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6868:
6869: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6870: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6871: }
6872:
6873: static void dsp_macr_p_x1_y0_a(void)
6874: {
6875: Uint32 source[3], dest[3];
6876: Uint16 newsr;
6877:
6878: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6879:
6880: dest[0] = dsp_core.registers[DSP_REG_A2];
6881: dest[1] = dsp_core.registers[DSP_REG_A1];
6882: dest[2] = dsp_core.registers[DSP_REG_A0];
6883: newsr = dsp_add56(source, dest);
6884:
6885: dsp_rnd56(dest);
6886:
6887: dsp_core.registers[DSP_REG_A2] = dest[0];
6888: dsp_core.registers[DSP_REG_A1] = dest[1];
6889: dsp_core.registers[DSP_REG_A0] = dest[2];
6890:
6891: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6892:
6893: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6894: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6895: }
6896:
6897: static void dsp_macr_m_x1_y0_a(void)
6898: {
6899: Uint32 source[3], dest[3];
6900: Uint16 newsr;
6901:
6902: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6903:
6904: dest[0] = dsp_core.registers[DSP_REG_A2];
6905: dest[1] = dsp_core.registers[DSP_REG_A1];
6906: dest[2] = dsp_core.registers[DSP_REG_A0];
6907: newsr = dsp_add56(source, dest);
6908:
6909: dsp_rnd56(dest);
6910:
6911: dsp_core.registers[DSP_REG_A2] = dest[0];
6912: dsp_core.registers[DSP_REG_A1] = dest[1];
6913: dsp_core.registers[DSP_REG_A0] = dest[2];
6914:
6915: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6916:
6917: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6918: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6919: }
6920:
6921: static void dsp_macr_p_x1_y0_b(void)
6922: {
6923: Uint32 source[3], dest[3];
6924: Uint16 newsr;
6925:
6926: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6927:
6928: dsp_rnd56(dest);
6929:
6930: dest[0] = dsp_core.registers[DSP_REG_B2];
6931: dest[1] = dsp_core.registers[DSP_REG_B1];
6932: dest[2] = dsp_core.registers[DSP_REG_B0];
6933: newsr = dsp_add56(source, dest);
6934:
6935: dsp_core.registers[DSP_REG_B2] = dest[0];
6936: dsp_core.registers[DSP_REG_B1] = dest[1];
6937: dsp_core.registers[DSP_REG_B0] = dest[2];
6938:
6939: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6940:
6941: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6942: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6943: }
6944:
6945: static void dsp_macr_m_x1_y0_b(void)
6946: {
6947: Uint32 source[3], dest[3];
6948: Uint16 newsr;
6949:
6950: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6951:
6952: dest[0] = dsp_core.registers[DSP_REG_B2];
6953: dest[1] = dsp_core.registers[DSP_REG_B1];
6954: dest[2] = dsp_core.registers[DSP_REG_B0];
6955: newsr = dsp_add56(source, dest);
6956:
6957: dsp_rnd56(dest);
6958:
6959: dsp_core.registers[DSP_REG_B2] = dest[0];
6960: dsp_core.registers[DSP_REG_B1] = dest[1];
6961: dsp_core.registers[DSP_REG_B0] = dest[2];
6962:
6963: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6964:
6965: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6966: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6967: }
6968:
6969: static void dsp_macr_p_y1_x1_a(void)
6970: {
6971: Uint32 source[3], dest[3];
6972: Uint16 newsr;
6973:
6974: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6975:
6976: dest[0] = dsp_core.registers[DSP_REG_A2];
6977: dest[1] = dsp_core.registers[DSP_REG_A1];
6978: dest[2] = dsp_core.registers[DSP_REG_A0];
6979: newsr = dsp_add56(source, dest);
6980:
6981: dsp_rnd56(dest);
6982:
6983: dsp_core.registers[DSP_REG_A2] = dest[0];
6984: dsp_core.registers[DSP_REG_A1] = dest[1];
6985: dsp_core.registers[DSP_REG_A0] = dest[2];
6986:
6987: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6988:
6989: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6990: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6991: }
6992:
6993: static void dsp_macr_m_y1_x1_a(void)
6994: {
6995: Uint32 source[3], dest[3];
6996: Uint16 newsr;
6997:
6998: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6999:
7000: dest[0] = dsp_core.registers[DSP_REG_A2];
7001: dest[1] = dsp_core.registers[DSP_REG_A1];
7002: dest[2] = dsp_core.registers[DSP_REG_A0];
7003: newsr = dsp_add56(source, dest);
7004:
7005: dsp_rnd56(dest);
7006:
7007: dsp_core.registers[DSP_REG_A2] = dest[0];
7008: dsp_core.registers[DSP_REG_A1] = dest[1];
7009: dsp_core.registers[DSP_REG_A0] = dest[2];
7010:
7011: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7012:
7013: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7014: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7015: }
7016:
7017: static void dsp_macr_p_y1_x1_b(void)
7018: {
7019: Uint32 source[3], dest[3];
7020: Uint16 newsr;
7021:
7022: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7023:
7024: dest[0] = dsp_core.registers[DSP_REG_B2];
7025: dest[1] = dsp_core.registers[DSP_REG_B1];
7026: dest[2] = dsp_core.registers[DSP_REG_B0];
7027: newsr = dsp_add56(source, dest);
7028:
7029: dsp_rnd56(dest);
7030:
7031: dsp_core.registers[DSP_REG_B2] = dest[0];
7032: dsp_core.registers[DSP_REG_B1] = dest[1];
7033: dsp_core.registers[DSP_REG_B0] = dest[2];
7034:
7035: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7036:
7037: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7038: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7039: }
7040:
7041: static void dsp_macr_m_y1_x1_b(void)
7042: {
7043: Uint32 source[3], dest[3];
7044: Uint16 newsr;
7045:
7046: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7047:
7048: dest[0] = dsp_core.registers[DSP_REG_B2];
7049: dest[1] = dsp_core.registers[DSP_REG_B1];
7050: dest[2] = dsp_core.registers[DSP_REG_B0];
7051: newsr = dsp_add56(source, dest);
7052:
7053: dsp_rnd56(dest);
7054:
7055: dsp_core.registers[DSP_REG_B2] = dest[0];
7056: dsp_core.registers[DSP_REG_B1] = dest[1];
7057: dsp_core.registers[DSP_REG_B0] = dest[2];
7058:
7059: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7060:
7061: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7062: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7063: }
7064:
7065:
7066: static void dsp_move(void)
7067: {
7068: /* move instruction inside alu opcodes
7069: taken care of by parallel move dispatcher */
7070: }
7071:
7072: static void dsp_mpy_p_x0_x0_a(void)
7073: {
7074: Uint32 source[3];
7075:
7076: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7077:
7078: dsp_core.registers[DSP_REG_A2] = source[0];
7079: dsp_core.registers[DSP_REG_A1] = source[1];
7080: dsp_core.registers[DSP_REG_A0] = source[2];
7081:
7082: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7083: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7084: }
7085:
7086: static void dsp_mpy_m_x0_x0_a(void)
7087: {
7088: Uint32 source[3];
7089:
7090: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7091:
7092: dsp_core.registers[DSP_REG_A2] = source[0];
7093: dsp_core.registers[DSP_REG_A1] = source[1];
7094: dsp_core.registers[DSP_REG_A0] = source[2];
7095:
7096: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7097: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7098: }
7099:
7100: static void dsp_mpy_p_x0_x0_b(void)
7101: {
7102: Uint32 source[3];
7103:
7104: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7105:
7106: dsp_core.registers[DSP_REG_B2] = source[0];
7107: dsp_core.registers[DSP_REG_B1] = source[1];
7108: dsp_core.registers[DSP_REG_B0] = source[2];
7109:
7110: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7111: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7112: }
7113:
7114: static void dsp_mpy_m_x0_x0_b(void)
7115: {
7116: Uint32 source[3];
7117:
7118:
7119: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7120:
7121: dsp_core.registers[DSP_REG_B2] = source[0];
7122: dsp_core.registers[DSP_REG_B1] = source[1];
7123: dsp_core.registers[DSP_REG_B0] = source[2];
7124:
7125: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7126: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7127: }
7128:
7129: static void dsp_mpy_p_y0_y0_a(void)
7130: {
7131: Uint32 source[3];
7132:
7133: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7134:
7135: dsp_core.registers[DSP_REG_A2] = source[0];
7136: dsp_core.registers[DSP_REG_A1] = source[1];
7137: dsp_core.registers[DSP_REG_A0] = source[2];
7138:
7139: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7140: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7141: }
7142:
7143: static void dsp_mpy_m_y0_y0_a(void)
7144: {
7145: Uint32 source[3];
7146:
7147: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7148:
7149: dsp_core.registers[DSP_REG_A2] = source[0];
7150: dsp_core.registers[DSP_REG_A1] = source[1];
7151: dsp_core.registers[DSP_REG_A0] = source[2];
7152:
7153: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7154: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7155: }
7156:
7157: static void dsp_mpy_p_y0_y0_b(void)
7158: {
7159: Uint32 source[3];
7160:
7161: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7162:
7163: dsp_core.registers[DSP_REG_B2] = source[0];
7164: dsp_core.registers[DSP_REG_B1] = source[1];
7165: dsp_core.registers[DSP_REG_B0] = source[2];
7166:
7167: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7168: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7169: }
7170:
7171: static void dsp_mpy_m_y0_y0_b(void)
7172: {
7173: Uint32 source[3];
7174:
7175: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7176:
7177: dsp_core.registers[DSP_REG_B2] = source[0];
7178: dsp_core.registers[DSP_REG_B1] = source[1];
7179: dsp_core.registers[DSP_REG_B0] = source[2];
7180:
7181: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7182: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7183: }
7184:
7185: static void dsp_mpy_p_x1_x0_a(void)
7186: {
7187: Uint32 source[3];
7188:
7189: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7190:
7191: dsp_core.registers[DSP_REG_A2] = source[0];
7192: dsp_core.registers[DSP_REG_A1] = source[1];
7193: dsp_core.registers[DSP_REG_A0] = source[2];
7194:
7195: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7196: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7197: }
7198:
7199: static void dsp_mpy_m_x1_x0_a(void)
7200: {
7201: Uint32 source[3];
7202:
7203: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7204:
7205: dsp_core.registers[DSP_REG_A2] = source[0];
7206: dsp_core.registers[DSP_REG_A1] = source[1];
7207: dsp_core.registers[DSP_REG_A0] = source[2];
7208:
7209: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7210: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7211: }
7212:
7213: static void dsp_mpy_p_x1_x0_b(void)
7214: {
7215: Uint32 source[3];
7216:
7217: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7218:
7219: dsp_core.registers[DSP_REG_B2] = source[0];
7220: dsp_core.registers[DSP_REG_B1] = source[1];
7221: dsp_core.registers[DSP_REG_B0] = source[2];
7222:
7223: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7224: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7225: }
7226:
7227: static void dsp_mpy_m_x1_x0_b(void)
7228: {
7229: Uint32 source[3];
7230:
7231: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7232:
7233: dsp_core.registers[DSP_REG_B2] = source[0];
7234: dsp_core.registers[DSP_REG_B1] = source[1];
7235: dsp_core.registers[DSP_REG_B0] = source[2];
7236:
7237: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7238: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7239: }
7240:
7241: static void dsp_mpy_p_y1_y0_a(void)
7242: {
7243: Uint32 source[3];
7244:
7245: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7246:
7247: dsp_core.registers[DSP_REG_A2] = source[0];
7248: dsp_core.registers[DSP_REG_A1] = source[1];
7249: dsp_core.registers[DSP_REG_A0] = source[2];
7250:
7251: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7252: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7253: }
7254:
7255: static void dsp_mpy_m_y1_y0_a(void)
7256: {
7257: Uint32 source[3];
7258:
7259: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7260:
7261: dsp_core.registers[DSP_REG_A2] = source[0];
7262: dsp_core.registers[DSP_REG_A1] = source[1];
7263: dsp_core.registers[DSP_REG_A0] = source[2];
7264:
7265: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7266: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7267: }
7268:
7269: static void dsp_mpy_p_y1_y0_b(void)
7270: {
7271: Uint32 source[3];
7272:
7273: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7274:
7275: dsp_core.registers[DSP_REG_B2] = source[0];
7276: dsp_core.registers[DSP_REG_B1] = source[1];
7277: dsp_core.registers[DSP_REG_B0] = source[2];
7278:
7279: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7280: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7281: }
7282:
7283: static void dsp_mpy_m_y1_y0_b(void)
7284: {
7285: Uint32 source[3];
7286:
7287: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7288:
7289: dsp_core.registers[DSP_REG_B2] = source[0];
7290: dsp_core.registers[DSP_REG_B1] = source[1];
7291: dsp_core.registers[DSP_REG_B0] = source[2];
7292:
7293: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7294: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7295: }
7296:
7297: static void dsp_mpy_p_x0_y1_a(void)
7298: {
7299: Uint32 source[3];
7300:
7301: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7302:
7303: dsp_core.registers[DSP_REG_A2] = source[0];
7304: dsp_core.registers[DSP_REG_A1] = source[1];
7305: dsp_core.registers[DSP_REG_A0] = source[2];
7306:
7307: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7308: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7309: }
7310:
7311: static void dsp_mpy_m_x0_y1_a(void)
7312: {
7313: Uint32 source[3];
7314:
7315: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7316:
7317: dsp_core.registers[DSP_REG_A2] = source[0];
7318: dsp_core.registers[DSP_REG_A1] = source[1];
7319: dsp_core.registers[DSP_REG_A0] = source[2];
7320:
7321: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7322: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7323: }
7324:
7325: static void dsp_mpy_p_x0_y1_b(void)
7326: {
7327: Uint32 source[3];
7328:
7329: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7330:
7331: dsp_core.registers[DSP_REG_B2] = source[0];
7332: dsp_core.registers[DSP_REG_B1] = source[1];
7333: dsp_core.registers[DSP_REG_B0] = source[2];
7334:
7335: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7336: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7337: }
7338:
7339: static void dsp_mpy_m_x0_y1_b(void)
7340: {
7341: Uint32 source[3];
7342:
7343: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7344:
7345: dsp_core.registers[DSP_REG_B2] = source[0];
7346: dsp_core.registers[DSP_REG_B1] = source[1];
7347: dsp_core.registers[DSP_REG_B0] = source[2];
7348:
7349: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7350: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7351: }
7352:
7353: static void dsp_mpy_p_y0_x0_a(void)
7354: {
7355: Uint32 source[3];
7356:
7357: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7358:
7359: dsp_core.registers[DSP_REG_A2] = source[0];
7360: dsp_core.registers[DSP_REG_A1] = source[1];
7361: dsp_core.registers[DSP_REG_A0] = source[2];
7362:
7363: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7364: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7365: }
7366:
7367: static void dsp_mpy_m_y0_x0_a(void)
7368: {
7369: Uint32 source[3];
7370:
7371: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7372:
7373: dsp_core.registers[DSP_REG_A2] = source[0];
7374: dsp_core.registers[DSP_REG_A1] = source[1];
7375: dsp_core.registers[DSP_REG_A0] = source[2];
7376:
7377: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7378: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7379: }
7380:
7381: static void dsp_mpy_p_y0_x0_b(void)
7382: {
7383: Uint32 source[3];
7384:
7385: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7386:
7387: dsp_core.registers[DSP_REG_B2] = source[0];
7388: dsp_core.registers[DSP_REG_B1] = source[1];
7389: dsp_core.registers[DSP_REG_B0] = source[2];
7390:
7391: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7392: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7393: }
7394:
7395: static void dsp_mpy_m_y0_x0_b(void)
7396: {
7397: Uint32 source[3];
7398:
7399: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7400:
7401: dsp_core.registers[DSP_REG_B2] = source[0];
7402: dsp_core.registers[DSP_REG_B1] = source[1];
7403: dsp_core.registers[DSP_REG_B0] = source[2];
7404:
7405: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7406: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7407: }
7408:
7409: static void dsp_mpy_p_x1_y0_a(void)
7410: {
7411: Uint32 source[3];
7412:
7413: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7414:
7415: dsp_core.registers[DSP_REG_A2] = source[0];
7416: dsp_core.registers[DSP_REG_A1] = source[1];
7417: dsp_core.registers[DSP_REG_A0] = source[2];
7418:
7419: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7420: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7421: }
7422:
7423: static void dsp_mpy_m_x1_y0_a(void)
7424: {
7425: Uint32 source[3];
7426:
7427: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7428:
7429: dsp_core.registers[DSP_REG_A2] = source[0];
7430: dsp_core.registers[DSP_REG_A1] = source[1];
7431: dsp_core.registers[DSP_REG_A0] = source[2];
7432:
7433: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7434: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7435: }
7436:
7437: static void dsp_mpy_p_x1_y0_b(void)
7438: {
7439: Uint32 source[3];
7440:
7441: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7442:
7443: dsp_core.registers[DSP_REG_B2] = source[0];
7444: dsp_core.registers[DSP_REG_B1] = source[1];
7445: dsp_core.registers[DSP_REG_B0] = source[2];
7446:
7447: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7448: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7449: }
7450:
7451: static void dsp_mpy_m_x1_y0_b(void)
7452: {
7453: Uint32 source[3];
7454:
7455: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7456:
7457: dsp_core.registers[DSP_REG_B2] = source[0];
7458: dsp_core.registers[DSP_REG_B1] = source[1];
7459: dsp_core.registers[DSP_REG_B0] = source[2];
7460:
7461: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7462: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7463: }
7464:
7465: static void dsp_mpy_p_y1_x1_a(void)
7466: {
7467: Uint32 source[3];
7468:
7469: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7470:
7471: dsp_core.registers[DSP_REG_A2] = source[0];
7472: dsp_core.registers[DSP_REG_A1] = source[1];
7473: dsp_core.registers[DSP_REG_A0] = source[2];
7474:
7475: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7476: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7477: }
7478:
7479: static void dsp_mpy_m_y1_x1_a(void)
7480: {
7481: Uint32 source[3];
7482:
7483: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7484:
7485: dsp_core.registers[DSP_REG_A2] = source[0];
7486: dsp_core.registers[DSP_REG_A1] = source[1];
7487: dsp_core.registers[DSP_REG_A0] = source[2];
7488:
7489: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7490: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7491: }
7492:
7493: static void dsp_mpy_p_y1_x1_b(void)
7494: {
7495: Uint32 source[3];
7496:
7497: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7498:
7499: dsp_core.registers[DSP_REG_B2] = source[0];
7500: dsp_core.registers[DSP_REG_B1] = source[1];
7501: dsp_core.registers[DSP_REG_B0] = source[2];
7502:
7503: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7504: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7505: }
7506:
7507: static void dsp_mpy_m_y1_x1_b(void)
7508: {
7509: Uint32 source[3];
7510:
7511: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7512:
7513: dsp_core.registers[DSP_REG_B2] = source[0];
7514: dsp_core.registers[DSP_REG_B1] = source[1];
7515: dsp_core.registers[DSP_REG_B0] = source[2];
7516:
7517: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7518: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7519: }
7520:
7521: static void dsp_mpyr_p_x0_x0_a(void)
7522: {
7523: Uint32 source[3];
7524:
7525: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7526: dsp_rnd56(source);
7527:
7528: dsp_core.registers[DSP_REG_A2] = source[0];
7529: dsp_core.registers[DSP_REG_A1] = source[1];
7530: dsp_core.registers[DSP_REG_A0] = source[2];
7531:
7532: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7533: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7534: }
7535:
7536: static void dsp_mpyr_m_x0_x0_a(void)
7537: {
7538: Uint32 source[3];
7539:
7540: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7541: dsp_rnd56(source);
7542:
7543: dsp_core.registers[DSP_REG_A2] = source[0];
7544: dsp_core.registers[DSP_REG_A1] = source[1];
7545: dsp_core.registers[DSP_REG_A0] = source[2];
7546:
7547: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7548: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7549: }
7550:
7551: static void dsp_mpyr_p_x0_x0_b(void)
7552: {
7553: Uint32 source[3];
7554:
7555: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7556: dsp_rnd56(source);
7557:
7558: dsp_core.registers[DSP_REG_B2] = source[0];
7559: dsp_core.registers[DSP_REG_B1] = source[1];
7560: dsp_core.registers[DSP_REG_B0] = source[2];
7561:
7562: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7563: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7564: }
7565:
7566: static void dsp_mpyr_m_x0_x0_b(void)
7567: {
7568: Uint32 source[3];
7569:
7570:
7571: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7572: dsp_rnd56(source);
7573:
7574: dsp_core.registers[DSP_REG_B2] = source[0];
7575: dsp_core.registers[DSP_REG_B1] = source[1];
7576: dsp_core.registers[DSP_REG_B0] = source[2];
7577:
7578: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7579: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7580: }
7581:
7582: static void dsp_mpyr_p_y0_y0_a(void)
7583: {
7584: Uint32 source[3];
7585:
7586: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7587: dsp_rnd56(source);
7588:
7589: dsp_core.registers[DSP_REG_A2] = source[0];
7590: dsp_core.registers[DSP_REG_A1] = source[1];
7591: dsp_core.registers[DSP_REG_A0] = source[2];
7592:
7593: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7594: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7595: }
7596:
7597: static void dsp_mpyr_m_y0_y0_a(void)
7598: {
7599: Uint32 source[3];
7600:
7601: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7602: dsp_rnd56(source);
7603:
7604: dsp_core.registers[DSP_REG_A2] = source[0];
7605: dsp_core.registers[DSP_REG_A1] = source[1];
7606: dsp_core.registers[DSP_REG_A0] = source[2];
7607:
7608: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7609: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7610: }
7611:
7612: static void dsp_mpyr_p_y0_y0_b(void)
7613: {
7614: Uint32 source[3];
7615:
7616: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7617: dsp_rnd56(source);
7618:
7619: dsp_core.registers[DSP_REG_B2] = source[0];
7620: dsp_core.registers[DSP_REG_B1] = source[1];
7621: dsp_core.registers[DSP_REG_B0] = source[2];
7622:
7623: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7624: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7625: }
7626:
7627: static void dsp_mpyr_m_y0_y0_b(void)
7628: {
7629: Uint32 source[3];
7630:
7631: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7632: dsp_rnd56(source);
7633:
7634: dsp_core.registers[DSP_REG_B2] = source[0];
7635: dsp_core.registers[DSP_REG_B1] = source[1];
7636: dsp_core.registers[DSP_REG_B0] = source[2];
7637:
7638: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7639: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7640: }
7641:
7642: static void dsp_mpyr_p_x1_x0_a(void)
7643: {
7644: Uint32 source[3];
7645:
7646: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7647: dsp_rnd56(source);
7648:
7649: dsp_core.registers[DSP_REG_A2] = source[0];
7650: dsp_core.registers[DSP_REG_A1] = source[1];
7651: dsp_core.registers[DSP_REG_A0] = source[2];
7652:
7653: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7654: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7655: }
7656:
7657: static void dsp_mpyr_m_x1_x0_a(void)
7658: {
7659: Uint32 source[3];
7660:
7661: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7662: dsp_rnd56(source);
7663:
7664: dsp_core.registers[DSP_REG_A2] = source[0];
7665: dsp_core.registers[DSP_REG_A1] = source[1];
7666: dsp_core.registers[DSP_REG_A0] = source[2];
7667:
7668: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7669: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7670: }
7671:
7672: static void dsp_mpyr_p_x1_x0_b(void)
7673: {
7674: Uint32 source[3];
7675:
7676: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7677: dsp_rnd56(source);
7678:
7679: dsp_core.registers[DSP_REG_B2] = source[0];
7680: dsp_core.registers[DSP_REG_B1] = source[1];
7681: dsp_core.registers[DSP_REG_B0] = source[2];
7682:
7683: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7684: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7685: }
7686:
7687: static void dsp_mpyr_m_x1_x0_b(void)
7688: {
7689: Uint32 source[3];
7690:
7691: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7692: dsp_rnd56(source);
7693:
7694: dsp_core.registers[DSP_REG_B2] = source[0];
7695: dsp_core.registers[DSP_REG_B1] = source[1];
7696: dsp_core.registers[DSP_REG_B0] = source[2];
7697:
7698: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7699: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7700: }
7701:
7702: static void dsp_mpyr_p_y1_y0_a(void)
7703: {
7704: Uint32 source[3];
7705:
7706: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7707: dsp_rnd56(source);
7708:
7709: dsp_core.registers[DSP_REG_A2] = source[0];
7710: dsp_core.registers[DSP_REG_A1] = source[1];
7711: dsp_core.registers[DSP_REG_A0] = source[2];
7712:
7713: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7714: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7715: }
7716:
7717: static void dsp_mpyr_m_y1_y0_a(void)
7718: {
7719: Uint32 source[3];
7720:
7721: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7722: dsp_rnd56(source);
7723:
7724: dsp_core.registers[DSP_REG_A2] = source[0];
7725: dsp_core.registers[DSP_REG_A1] = source[1];
7726: dsp_core.registers[DSP_REG_A0] = source[2];
7727:
7728: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7729: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7730: }
7731:
7732: static void dsp_mpyr_p_y1_y0_b(void)
7733: {
7734: Uint32 source[3];
7735:
7736: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7737: dsp_rnd56(source);
7738:
7739: dsp_core.registers[DSP_REG_B2] = source[0];
7740: dsp_core.registers[DSP_REG_B1] = source[1];
7741: dsp_core.registers[DSP_REG_B0] = source[2];
7742:
7743: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7744: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7745: }
7746:
7747: static void dsp_mpyr_m_y1_y0_b(void)
7748: {
7749: Uint32 source[3];
7750:
7751: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7752: dsp_rnd56(source);
7753:
7754: dsp_core.registers[DSP_REG_B2] = source[0];
7755: dsp_core.registers[DSP_REG_B1] = source[1];
7756: dsp_core.registers[DSP_REG_B0] = source[2];
7757:
7758: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7759: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7760: }
7761:
7762: static void dsp_mpyr_p_x0_y1_a(void)
7763: {
7764: Uint32 source[3];
7765:
7766: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7767: dsp_rnd56(source);
7768:
7769: dsp_core.registers[DSP_REG_A2] = source[0];
7770: dsp_core.registers[DSP_REG_A1] = source[1];
7771: dsp_core.registers[DSP_REG_A0] = source[2];
7772:
7773: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7774: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7775: }
7776:
7777: static void dsp_mpyr_m_x0_y1_a(void)
7778: {
7779: Uint32 source[3];
7780:
7781: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7782: dsp_rnd56(source);
7783:
7784: dsp_core.registers[DSP_REG_A2] = source[0];
7785: dsp_core.registers[DSP_REG_A1] = source[1];
7786: dsp_core.registers[DSP_REG_A0] = source[2];
7787:
7788: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7789: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7790: }
7791:
7792: static void dsp_mpyr_p_x0_y1_b(void)
7793: {
7794: Uint32 source[3];
7795:
7796: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7797: dsp_rnd56(source);
7798:
7799: dsp_core.registers[DSP_REG_B2] = source[0];
7800: dsp_core.registers[DSP_REG_B1] = source[1];
7801: dsp_core.registers[DSP_REG_B0] = source[2];
7802:
7803: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7804: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7805: }
7806:
7807: static void dsp_mpyr_m_x0_y1_b(void)
7808: {
7809: Uint32 source[3];
7810:
7811: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7812: dsp_rnd56(source);
7813:
7814: dsp_core.registers[DSP_REG_B2] = source[0];
7815: dsp_core.registers[DSP_REG_B1] = source[1];
7816: dsp_core.registers[DSP_REG_B0] = source[2];
7817:
7818: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7819: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7820: }
7821:
7822: static void dsp_mpyr_p_y0_x0_a(void)
7823: {
7824: Uint32 source[3];
7825:
7826: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7827: dsp_rnd56(source);
7828:
7829: dsp_core.registers[DSP_REG_A2] = source[0];
7830: dsp_core.registers[DSP_REG_A1] = source[1];
7831: dsp_core.registers[DSP_REG_A0] = source[2];
7832:
7833: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7834: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7835: }
7836:
7837: static void dsp_mpyr_m_y0_x0_a(void)
7838: {
7839: Uint32 source[3];
7840:
7841: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7842: dsp_rnd56(source);
7843:
7844: dsp_core.registers[DSP_REG_A2] = source[0];
7845: dsp_core.registers[DSP_REG_A1] = source[1];
7846: dsp_core.registers[DSP_REG_A0] = source[2];
7847:
7848: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7849: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7850: }
7851:
7852: static void dsp_mpyr_p_y0_x0_b(void)
7853: {
7854: Uint32 source[3];
7855:
7856: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7857: dsp_rnd56(source);
7858:
7859: dsp_core.registers[DSP_REG_B2] = source[0];
7860: dsp_core.registers[DSP_REG_B1] = source[1];
7861: dsp_core.registers[DSP_REG_B0] = source[2];
7862:
7863: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7864: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7865: }
7866:
7867: static void dsp_mpyr_m_y0_x0_b(void)
7868: {
7869: Uint32 source[3];
7870:
7871: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7872: dsp_rnd56(source);
7873:
7874: dsp_core.registers[DSP_REG_B2] = source[0];
7875: dsp_core.registers[DSP_REG_B1] = source[1];
7876: dsp_core.registers[DSP_REG_B0] = source[2];
7877:
7878: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7879: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7880: }
7881:
7882: static void dsp_mpyr_p_x1_y0_a(void)
7883: {
7884: Uint32 source[3];
7885:
7886: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7887: dsp_rnd56(source);
7888:
7889: dsp_core.registers[DSP_REG_A2] = source[0];
7890: dsp_core.registers[DSP_REG_A1] = source[1];
7891: dsp_core.registers[DSP_REG_A0] = source[2];
7892:
7893: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7894: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7895: }
7896:
7897: static void dsp_mpyr_m_x1_y0_a(void)
7898: {
7899: Uint32 source[3];
7900:
7901: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7902: dsp_rnd56(source);
7903:
7904: dsp_core.registers[DSP_REG_A2] = source[0];
7905: dsp_core.registers[DSP_REG_A1] = source[1];
7906: dsp_core.registers[DSP_REG_A0] = source[2];
7907:
7908: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7909: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7910: }
7911:
7912: static void dsp_mpyr_p_x1_y0_b(void)
7913: {
7914: Uint32 source[3];
7915:
7916: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7917: dsp_rnd56(source);
7918:
7919: dsp_core.registers[DSP_REG_B2] = source[0];
7920: dsp_core.registers[DSP_REG_B1] = source[1];
7921: dsp_core.registers[DSP_REG_B0] = source[2];
7922:
7923: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7924: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7925: }
7926:
7927: static void dsp_mpyr_m_x1_y0_b(void)
7928: {
7929: Uint32 source[3];
7930:
7931: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7932: dsp_rnd56(source);
7933:
7934: dsp_core.registers[DSP_REG_B2] = source[0];
7935: dsp_core.registers[DSP_REG_B1] = source[1];
7936: dsp_core.registers[DSP_REG_B0] = source[2];
7937:
7938: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7939: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7940: }
7941:
7942: static void dsp_mpyr_p_y1_x1_a(void)
7943: {
7944: Uint32 source[3];
7945:
7946: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7947: dsp_rnd56(source);
7948:
7949: dsp_core.registers[DSP_REG_A2] = source[0];
7950: dsp_core.registers[DSP_REG_A1] = source[1];
7951: dsp_core.registers[DSP_REG_A0] = source[2];
7952:
7953: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7954: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7955: }
7956:
7957: static void dsp_mpyr_m_y1_x1_a(void)
7958: {
7959: Uint32 source[3];
7960:
7961: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7962: dsp_rnd56(source);
7963:
7964: dsp_core.registers[DSP_REG_A2] = source[0];
7965: dsp_core.registers[DSP_REG_A1] = source[1];
7966: dsp_core.registers[DSP_REG_A0] = source[2];
7967:
7968: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7969: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7970: }
7971:
7972: static void dsp_mpyr_p_y1_x1_b(void)
7973: {
7974: Uint32 source[3];
7975:
7976: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7977: dsp_rnd56(source);
7978:
7979: dsp_core.registers[DSP_REG_B2] = source[0];
7980: dsp_core.registers[DSP_REG_B1] = source[1];
7981: dsp_core.registers[DSP_REG_B0] = source[2];
7982:
7983: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7984: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7985: }
7986:
7987: static void dsp_mpyr_m_y1_x1_b(void)
7988: {
7989: Uint32 source[3];
7990:
7991: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7992: dsp_rnd56(source);
7993:
7994: dsp_core.registers[DSP_REG_B2] = source[0];
7995: dsp_core.registers[DSP_REG_B1] = source[1];
7996: dsp_core.registers[DSP_REG_B0] = source[2];
7997:
7998: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7999: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8000: }
8001:
8002: static void dsp_neg_a(void)
8003: {
8004: Uint32 source[3], dest[3], overflowed;
8005:
8006: source[0] = dsp_core.registers[DSP_REG_A2];
8007: source[1] = dsp_core.registers[DSP_REG_A1];
8008: source[2] = dsp_core.registers[DSP_REG_A0];
8009:
8010: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8011:
8012: dest[0] = dest[1] = dest[2] = 0;
8013:
8014: dsp_sub56(source, dest);
8015:
8016: dsp_core.registers[DSP_REG_A2] = dest[0];
8017: dsp_core.registers[DSP_REG_A1] = dest[1];
8018: dsp_core.registers[DSP_REG_A0] = dest[2];
8019:
8020: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8021: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8022:
8023: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8024: }
8025:
8026: static void dsp_neg_b(void)
8027: {
8028: Uint32 source[3], dest[3], overflowed;
8029:
8030: source[0] = dsp_core.registers[DSP_REG_B2];
8031: source[1] = dsp_core.registers[DSP_REG_B1];
8032: source[2] = dsp_core.registers[DSP_REG_B0];
8033:
8034: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8035:
8036: dest[0] = dest[1] = dest[2] = 0;
8037:
8038: dsp_sub56(source, dest);
8039:
8040: dsp_core.registers[DSP_REG_B2] = dest[0];
8041: dsp_core.registers[DSP_REG_B1] = dest[1];
8042: dsp_core.registers[DSP_REG_B0] = dest[2];
8043:
8044: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8045: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8046:
8047: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8048: }
8049:
8050: static void dsp_nop(void)
8051: {
8052: }
8053:
8054: static void dsp_not_a(void)
8055: {
8056: dsp_core.registers[DSP_REG_A1] = ~dsp_core.registers[DSP_REG_A1];
8057: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8058:
8059: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8060: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8061: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8062: }
8063:
8064: static void dsp_not_b(void)
8065: {
8066: dsp_core.registers[DSP_REG_B1] = ~dsp_core.registers[DSP_REG_B1];
8067: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8068:
8069: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8070: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8071: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8072: }
8073:
8074: static void dsp_or_x0_a(void)
8075: {
8076: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X0];
8077: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8078:
8079: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8080: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8081: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8082: }
8083:
8084: static void dsp_or_x0_b(void)
8085: {
8086: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X0];
8087: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8088:
8089: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8090: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8091: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8092: }
8093:
8094: static void dsp_or_y0_a(void)
8095: {
8096: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y0];
8097: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8098:
8099: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8100: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8101: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8102: }
8103:
8104: static void dsp_or_y0_b(void)
8105: {
8106: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y0];
8107: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8108:
8109: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8110: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8111: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8112: }
8113:
8114: static void dsp_or_x1_a(void)
8115: {
8116: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X1];
8117: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8118:
8119: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8120: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8121: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8122: }
8123:
8124: static void dsp_or_x1_b(void)
8125: {
8126: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X1];
8127: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8128:
8129: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8130: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8131: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8132: }
8133:
8134: static void dsp_or_y1_a(void)
8135: {
8136: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y1];
8137: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8138:
8139: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8140: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8141: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8142: }
8143:
8144: static void dsp_or_y1_b(void)
8145: {
8146: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y1];
8147: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8148:
8149: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8150: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8151: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8152: }
8153:
8154: static void dsp_rnd_a(void)
8155: {
8156: Uint32 dest[3];
8157:
8158: dest[0] = dsp_core.registers[DSP_REG_A2];
8159: dest[1] = dsp_core.registers[DSP_REG_A1];
8160: dest[2] = dsp_core.registers[DSP_REG_A0];
8161:
8162: dsp_rnd56(dest);
8163:
8164: dsp_core.registers[DSP_REG_A2] = dest[0];
8165: dsp_core.registers[DSP_REG_A1] = dest[1];
8166: dsp_core.registers[DSP_REG_A0] = dest[2];
8167:
8168: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8169: }
8170:
8171: static void dsp_rnd_b(void)
8172: {
8173: Uint32 dest[3];
8174:
8175: dest[0] = dsp_core.registers[DSP_REG_B2];
8176: dest[1] = dsp_core.registers[DSP_REG_B1];
8177: dest[2] = dsp_core.registers[DSP_REG_B0];
8178:
8179: dsp_rnd56(dest);
8180:
8181: dsp_core.registers[DSP_REG_B2] = dest[0];
8182: dsp_core.registers[DSP_REG_B1] = dest[1];
8183: dsp_core.registers[DSP_REG_B0] = dest[2];
8184:
8185: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8186: }
8187:
8188: static void dsp_rol_a(void)
8189: {
8190: Uint32 newcarry;
8191:
8192: newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
8193:
8194: dsp_core.registers[DSP_REG_A1] <<= 1;
8195: dsp_core.registers[DSP_REG_A1] |= newcarry;
8196: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
8197:
8198: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8199: dsp_core.registers[DSP_REG_SR] |= newcarry;
8200: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8201: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8202: }
8203:
8204: static void dsp_rol_b(void)
8205: {
8206: Uint32 newcarry;
8207:
8208: newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
8209:
8210: dsp_core.registers[DSP_REG_B1] <<= 1;
8211: dsp_core.registers[DSP_REG_B1] |= newcarry;
8212: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
8213:
8214: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8215: dsp_core.registers[DSP_REG_SR] |= newcarry;
8216: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8217: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8218: }
8219:
8220: static void dsp_ror_a(void)
8221: {
8222: Uint32 newcarry;
8223:
8224: newcarry = dsp_core.registers[DSP_REG_A1] & 1;
8225:
8226: dsp_core.registers[DSP_REG_A1] >>= 1;
8227: dsp_core.registers[DSP_REG_A1] |= newcarry<<23;
8228:
8229: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8230: dsp_core.registers[DSP_REG_SR] |= newcarry;
8231: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8232: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8233: }
8234:
8235: static void dsp_ror_b(void)
8236: {
8237: Uint32 newcarry;
8238:
8239: newcarry = dsp_core.registers[DSP_REG_B1] & 1;
8240:
8241: dsp_core.registers[DSP_REG_B1] >>= 1;
8242: dsp_core.registers[DSP_REG_B1] |= newcarry<<23;
8243:
8244: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8245: dsp_core.registers[DSP_REG_SR] |= newcarry;
8246: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8247: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8248: }
8249:
8250: static void dsp_sbc_x_a(void)
8251: {
8252: Uint32 source[3], dest[3], curcarry;
8253: Uint16 newsr;
8254:
8255: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8256:
8257: dest[2] = dsp_core.registers[DSP_REG_A0];
8258: dest[1] = dsp_core.registers[DSP_REG_A1];
8259: dest[0] = dsp_core.registers[DSP_REG_A2];
8260:
8261: source[2] = dsp_core.registers[DSP_REG_X0];
8262: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 ! root 8263: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8264:
8265: newsr = dsp_sub56(source, dest);
8266:
8267: if (curcarry) {
8268: source[0]=0; source[1]=0; source[2]=1;
8269: newsr |= dsp_sub56(source, dest);
8270: }
8271:
8272: dsp_core.registers[DSP_REG_A2] = dest[0];
8273: dsp_core.registers[DSP_REG_A1] = dest[1];
8274: dsp_core.registers[DSP_REG_A0] = dest[2];
8275:
8276: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8277:
8278: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8279: dsp_core.registers[DSP_REG_SR] |= newsr;
8280: }
8281:
8282: static void dsp_sbc_x_b(void)
8283: {
8284: Uint32 source[3], dest[3], curcarry;
8285: Uint16 newsr;
8286:
8287: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8288:
8289: dest[2] = dsp_core.registers[DSP_REG_B0];
8290: dest[1] = dsp_core.registers[DSP_REG_B1];
8291: dest[0] = dsp_core.registers[DSP_REG_B2];
8292:
8293: source[2] = dsp_core.registers[DSP_REG_X0];
8294: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 ! root 8295: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8296:
8297: newsr = dsp_sub56(source, dest);
8298:
8299: if (curcarry) {
8300: source[0]=0; source[1]=0; source[2]=1;
8301: newsr |= dsp_sub56(source, dest);
8302: }
8303:
8304: dsp_core.registers[DSP_REG_B2] = dest[0];
8305: dsp_core.registers[DSP_REG_B1] = dest[1];
8306: dsp_core.registers[DSP_REG_B0] = dest[2];
8307:
8308: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8309:
8310: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8311: dsp_core.registers[DSP_REG_SR] |= newsr;
8312: }
8313:
8314: static void dsp_sbc_y_a(void)
8315: {
8316: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 8317: Uint16 newsr;
1.1 root 8318:
1.1.1.6 root 8319: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8320:
8321: dest[2] = dsp_core.registers[DSP_REG_A0];
8322: dest[1] = dsp_core.registers[DSP_REG_A1];
8323: dest[0] = dsp_core.registers[DSP_REG_A2];
8324:
8325: source[2] = dsp_core.registers[DSP_REG_Y0];
8326: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 ! root 8327: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8328:
8329: newsr = dsp_sub56(source, dest);
8330:
8331: if (curcarry) {
8332: source[0]=0; source[1]=0; source[2]=1;
8333: newsr |= dsp_sub56(source, dest);
8334: }
8335:
8336: dsp_core.registers[DSP_REG_A2] = dest[0];
8337: dsp_core.registers[DSP_REG_A1] = dest[1];
8338: dsp_core.registers[DSP_REG_A0] = dest[2];
8339:
8340: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8341:
8342: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8343: dsp_core.registers[DSP_REG_SR] |= newsr;
8344: }
8345:
8346: static void dsp_sbc_y_b(void)
8347: {
8348: Uint32 source[3], dest[3], curcarry;
8349: Uint16 newsr;
8350:
8351: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8352:
8353: dest[2] = dsp_core.registers[DSP_REG_B0];
8354: dest[1] = dsp_core.registers[DSP_REG_B1];
8355: dest[0] = dsp_core.registers[DSP_REG_B2];
8356:
8357: source[2] = dsp_core.registers[DSP_REG_Y0];
8358: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 ! root 8359: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8360:
8361: newsr = dsp_sub56(source, dest);
8362:
8363: if (curcarry) {
8364: source[0]=0; source[1]=0; source[2]=1;
8365: newsr |= dsp_sub56(source, dest);
1.1 root 8366: }
8367:
1.1.1.6 root 8368: dsp_core.registers[DSP_REG_B2] = dest[0];
8369: dsp_core.registers[DSP_REG_B1] = dest[1];
8370: dsp_core.registers[DSP_REG_B0] = dest[2];
8371:
8372: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8373:
8374: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8375: dsp_core.registers[DSP_REG_SR] |= newsr;
8376: }
8377:
8378: static void dsp_sub_b_a(void)
8379: {
8380: Uint32 source[3], dest[3];
8381: Uint16 newsr;
8382:
8383: dest[2] = dsp_core.registers[DSP_REG_A0];
8384: dest[1] = dsp_core.registers[DSP_REG_A1];
8385: dest[0] = dsp_core.registers[DSP_REG_A2];
8386:
8387: source[2] = dsp_core.registers[DSP_REG_B0];
8388: source[1] = dsp_core.registers[DSP_REG_B1];
8389: source[0] = dsp_core.registers[DSP_REG_B2];
8390:
1.1 root 8391: newsr = dsp_sub56(source, dest);
8392:
1.1.1.6 root 8393: dsp_core.registers[DSP_REG_A2] = dest[0];
8394: dsp_core.registers[DSP_REG_A1] = dest[1];
8395: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8396:
1.1.1.6 root 8397: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8398:
1.1.1.6 root 8399: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8400: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8401: }
8402:
1.1.1.6 root 8403: static void dsp_sub_a_b(void)
1.1 root 8404: {
1.1.1.6 root 8405: Uint32 source[3], dest[3];
1.1.1.2 root 8406: Uint16 newsr;
1.1 root 8407:
1.1.1.6 root 8408: dest[2] = dsp_core.registers[DSP_REG_B0];
8409: dest[1] = dsp_core.registers[DSP_REG_B1];
8410: dest[0] = dsp_core.registers[DSP_REG_B2];
8411:
8412: source[2] = dsp_core.registers[DSP_REG_A0];
8413: source[1] = dsp_core.registers[DSP_REG_A1];
8414: source[0] = dsp_core.registers[DSP_REG_A2];
8415:
8416: newsr = dsp_sub56(source, dest);
8417:
8418: dsp_core.registers[DSP_REG_B2] = dest[0];
8419: dsp_core.registers[DSP_REG_B1] = dest[1];
8420: dsp_core.registers[DSP_REG_B0] = dest[2];
8421:
8422: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8423:
8424: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8425: dsp_core.registers[DSP_REG_SR] |= newsr;
8426: }
8427:
8428: static void dsp_sub_x_a(void)
8429: {
8430: Uint32 source[3], dest[3];
8431: Uint16 newsr;
8432:
8433: dest[2] = dsp_core.registers[DSP_REG_A0];
8434: dest[1] = dsp_core.registers[DSP_REG_A1];
8435: dest[0] = dsp_core.registers[DSP_REG_A2];
8436:
8437: source[2] = dsp_core.registers[DSP_REG_X0];
8438: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 ! root 8439: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8440:
8441: newsr = dsp_sub56(source, dest);
8442:
8443: dsp_core.registers[DSP_REG_A2] = dest[0];
8444: dsp_core.registers[DSP_REG_A1] = dest[1];
8445: dsp_core.registers[DSP_REG_A0] = dest[2];
8446:
8447: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8448:
8449: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8450: dsp_core.registers[DSP_REG_SR] |= newsr;
8451: }
8452:
8453: static void dsp_sub_x_b(void)
8454: {
8455: Uint32 source[3], dest[3];
8456: Uint16 newsr;
8457:
8458: dest[2] = dsp_core.registers[DSP_REG_B0];
8459: dest[1] = dsp_core.registers[DSP_REG_B1];
8460: dest[0] = dsp_core.registers[DSP_REG_B2];
8461:
8462: source[2] = dsp_core.registers[DSP_REG_X0];
8463: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 ! root 8464: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8465:
8466: newsr = dsp_sub56(source, dest);
8467:
8468: dsp_core.registers[DSP_REG_B2] = dest[0];
8469: dsp_core.registers[DSP_REG_B1] = dest[1];
8470: dsp_core.registers[DSP_REG_B0] = dest[2];
8471:
8472: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8473:
8474: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8475: dsp_core.registers[DSP_REG_SR] |= newsr;
8476: }
8477:
8478: static void dsp_sub_y_a(void)
8479: {
8480: Uint32 source[3], dest[3];
8481: Uint16 newsr;
8482:
8483: dest[2] = dsp_core.registers[DSP_REG_A0];
8484: dest[1] = dsp_core.registers[DSP_REG_A1];
8485: dest[0] = dsp_core.registers[DSP_REG_A2];
8486:
8487: source[2] = dsp_core.registers[DSP_REG_Y0];
8488: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 ! root 8489: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8490:
8491: newsr = dsp_sub56(source, dest);
8492:
8493: dsp_core.registers[DSP_REG_A2] = dest[0];
8494: dsp_core.registers[DSP_REG_A1] = dest[1];
8495: dsp_core.registers[DSP_REG_A0] = dest[2];
8496:
8497: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8498:
8499: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8500: dsp_core.registers[DSP_REG_SR] |= newsr;
8501: }
8502:
8503: static void dsp_sub_y_b(void)
8504: {
8505: Uint32 source[3], dest[3];
8506: Uint16 newsr;
8507:
8508: dest[2] = dsp_core.registers[DSP_REG_B0];
8509: dest[1] = dsp_core.registers[DSP_REG_B1];
8510: dest[0] = dsp_core.registers[DSP_REG_B2];
8511:
8512: source[2] = dsp_core.registers[DSP_REG_Y0];
8513: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 ! root 8514: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8515:
8516: newsr = dsp_sub56(source, dest);
8517:
8518: dsp_core.registers[DSP_REG_B2] = dest[0];
8519: dsp_core.registers[DSP_REG_B1] = dest[1];
8520: dsp_core.registers[DSP_REG_B0] = dest[2];
8521:
8522: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8523:
8524: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8525: dsp_core.registers[DSP_REG_SR] |= newsr;
8526: }
8527:
8528: static void dsp_sub_x0_a(void)
8529: {
8530: Uint32 source[3], dest[3];
8531: Uint16 newsr;
8532:
8533: dest[2] = dsp_core.registers[DSP_REG_A0];
8534: dest[1] = dsp_core.registers[DSP_REG_A1];
8535: dest[0] = dsp_core.registers[DSP_REG_A2];
8536:
8537: source[2] = 0;
8538: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 ! root 8539: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8540:
8541: newsr = dsp_sub56(source, dest);
8542:
8543: dsp_core.registers[DSP_REG_A2] = dest[0];
8544: dsp_core.registers[DSP_REG_A1] = dest[1];
8545: dsp_core.registers[DSP_REG_A0] = dest[2];
8546:
8547: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8548:
8549: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8550: dsp_core.registers[DSP_REG_SR] |= newsr;
8551: }
8552:
8553: static void dsp_sub_x0_b(void)
8554: {
8555: Uint32 source[3], dest[3];
8556: Uint16 newsr;
8557:
8558: dest[2] = dsp_core.registers[DSP_REG_B0];
8559: dest[1] = dsp_core.registers[DSP_REG_B1];
8560: dest[0] = dsp_core.registers[DSP_REG_B2];
8561:
8562: source[2] = 0;
8563: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 ! root 8564: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8565:
8566: newsr = dsp_sub56(source, dest);
8567:
8568: dsp_core.registers[DSP_REG_B2] = dest[0];
8569: dsp_core.registers[DSP_REG_B1] = dest[1];
8570: dsp_core.registers[DSP_REG_B0] = dest[2];
8571:
8572: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8573:
8574: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8575: dsp_core.registers[DSP_REG_SR] |= newsr;
8576: }
8577:
8578: static void dsp_sub_y0_a(void)
8579: {
8580: Uint32 source[3], dest[3];
8581: Uint16 newsr;
8582:
8583: dest[2] = dsp_core.registers[DSP_REG_A0];
8584: dest[1] = dsp_core.registers[DSP_REG_A1];
8585: dest[0] = dsp_core.registers[DSP_REG_A2];
8586:
8587: source[2] = 0;
8588: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 ! root 8589: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8590:
8591: newsr = dsp_sub56(source, dest);
1.1 root 8592:
1.1.1.6 root 8593: dsp_core.registers[DSP_REG_A2] = dest[0];
8594: dsp_core.registers[DSP_REG_A1] = dest[1];
8595: dsp_core.registers[DSP_REG_A0] = dest[2];
8596:
8597: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8598:
8599: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8600: dsp_core.registers[DSP_REG_SR] |= newsr;
8601: }
8602:
8603: static void dsp_sub_y0_b(void)
8604: {
8605: Uint32 source[3], dest[3];
8606: Uint16 newsr;
8607:
8608: dest[2] = dsp_core.registers[DSP_REG_B0];
8609: dest[1] = dsp_core.registers[DSP_REG_B1];
8610: dest[0] = dsp_core.registers[DSP_REG_B2];
8611:
8612: source[2] = 0;
8613: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 ! root 8614: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8615:
8616: newsr = dsp_sub56(source, dest);
8617:
8618: dsp_core.registers[DSP_REG_B2] = dest[0];
8619: dsp_core.registers[DSP_REG_B1] = dest[1];
8620: dsp_core.registers[DSP_REG_B0] = dest[2];
8621:
8622: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8623:
8624: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8625: dsp_core.registers[DSP_REG_SR] |= newsr;
8626: }
8627:
8628: static void dsp_sub_x1_a(void)
8629: {
8630: Uint32 source[3], dest[3];
8631: Uint16 newsr;
8632:
8633: dest[2] = dsp_core.registers[DSP_REG_A0];
8634: dest[1] = dsp_core.registers[DSP_REG_A1];
8635: dest[0] = dsp_core.registers[DSP_REG_A2];
8636:
8637: source[2] = 0;
8638: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 ! root 8639: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8640:
8641: newsr = dsp_sub56(source, dest);
8642:
8643: dsp_core.registers[DSP_REG_A2] = dest[0];
8644: dsp_core.registers[DSP_REG_A1] = dest[1];
8645: dsp_core.registers[DSP_REG_A0] = dest[2];
8646:
8647: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8648:
8649: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8650: dsp_core.registers[DSP_REG_SR] |= newsr;
8651: }
8652:
8653: static void dsp_sub_x1_b(void)
8654: {
8655: Uint32 source[3], dest[3];
8656: Uint16 newsr;
8657:
8658: dest[2] = dsp_core.registers[DSP_REG_B0];
8659: dest[1] = dsp_core.registers[DSP_REG_B1];
8660: dest[0] = dsp_core.registers[DSP_REG_B2];
8661:
8662: source[2] = 0;
8663: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 ! root 8664: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8665:
8666: newsr = dsp_sub56(source, dest);
8667:
8668: dsp_core.registers[DSP_REG_B2] = dest[0];
8669: dsp_core.registers[DSP_REG_B1] = dest[1];
8670: dsp_core.registers[DSP_REG_B0] = dest[2];
8671:
8672: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8673:
8674: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8675: dsp_core.registers[DSP_REG_SR] |= newsr;
8676: }
8677:
8678: static void dsp_sub_y1_a(void)
8679: {
8680: Uint32 source[3], dest[3];
8681: Uint16 newsr;
8682:
8683: dest[2] = dsp_core.registers[DSP_REG_A0];
8684: dest[1] = dsp_core.registers[DSP_REG_A1];
8685: dest[0] = dsp_core.registers[DSP_REG_A2];
8686:
8687: source[2] = 0;
8688: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 ! root 8689: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8690:
8691: newsr = dsp_sub56(source, dest);
8692:
8693: dsp_core.registers[DSP_REG_A2] = dest[0];
8694: dsp_core.registers[DSP_REG_A1] = dest[1];
8695: dsp_core.registers[DSP_REG_A0] = dest[2];
8696:
8697: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8698:
8699: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8700: dsp_core.registers[DSP_REG_SR] |= newsr;
8701: }
8702:
8703: static void dsp_sub_y1_b(void)
8704: {
8705: Uint32 source[3], dest[3];
8706: Uint16 newsr;
8707:
8708: dest[2] = dsp_core.registers[DSP_REG_B0];
8709: dest[1] = dsp_core.registers[DSP_REG_B1];
8710: dest[0] = dsp_core.registers[DSP_REG_B2];
8711:
8712: source[2] = 0;
8713: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 ! root 8714: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8715:
8716: newsr = dsp_sub56(source, dest);
8717:
8718: dsp_core.registers[DSP_REG_B2] = dest[0];
8719: dsp_core.registers[DSP_REG_B1] = dest[1];
8720: dsp_core.registers[DSP_REG_B0] = dest[2];
8721:
8722: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8723:
8724: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8725: dsp_core.registers[DSP_REG_SR] |= newsr;
8726: }
8727:
8728: static void dsp_subl_a(void)
8729: {
8730: Uint32 source[3], dest[3];
8731: Uint16 newsr;
8732:
8733: dest[0] = dsp_core.registers[DSP_REG_A2];
8734: dest[1] = dsp_core.registers[DSP_REG_A1];
8735: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 8736: newsr = dsp_asl56(dest);
8737:
1.1.1.6 root 8738: source[0] = dsp_core.registers[DSP_REG_B2];
8739: source[1] = dsp_core.registers[DSP_REG_B1];
8740: source[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 8741: newsr |= dsp_sub56(source, dest);
8742:
1.1.1.6 root 8743: dsp_core.registers[DSP_REG_A2] = dest[0];
8744: dsp_core.registers[DSP_REG_A1] = dest[1];
8745: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8746:
1.1.1.6 root 8747: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8748:
1.1.1.6 root 8749: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8750: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8751: }
8752:
1.1.1.6 root 8753: static void dsp_subl_b(void)
1.1 root 8754: {
1.1.1.6 root 8755: Uint32 source[3], dest[3];
1.1.1.2 root 8756: Uint16 newsr;
1.1 root 8757:
1.1.1.6 root 8758: dest[0] = dsp_core.registers[DSP_REG_B2];
8759: dest[1] = dsp_core.registers[DSP_REG_B1];
8760: dest[2] = dsp_core.registers[DSP_REG_B0];
8761: newsr = dsp_asl56(dest);
1.1 root 8762:
1.1.1.6 root 8763: source[0] = dsp_core.registers[DSP_REG_A2];
8764: source[1] = dsp_core.registers[DSP_REG_A1];
8765: source[2] = dsp_core.registers[DSP_REG_A0];
8766: newsr |= dsp_sub56(source, dest);
8767:
8768: dsp_core.registers[DSP_REG_B2] = dest[0];
8769: dsp_core.registers[DSP_REG_B1] = dest[1];
8770: dsp_core.registers[DSP_REG_B0] = dest[2];
8771:
8772: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8773:
8774: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8775: dsp_core.registers[DSP_REG_SR] |= newsr;
8776: }
8777:
8778: static void dsp_subr_a(void)
8779: {
8780: Uint32 source[3], dest[3];
8781: Uint16 newsr;
8782:
8783: dest[0] = dsp_core.registers[DSP_REG_A2];
8784: dest[1] = dsp_core.registers[DSP_REG_A1];
8785: dest[2] = dsp_core.registers[DSP_REG_A0];
8786:
1.1 root 8787: newsr = dsp_asr56(dest);
8788:
1.1.1.6 root 8789: source[0] = dsp_core.registers[DSP_REG_B2];
8790: source[1] = dsp_core.registers[DSP_REG_B1];
8791: source[2] = dsp_core.registers[DSP_REG_B0];
8792:
1.1 root 8793: newsr |= dsp_sub56(source, dest);
8794:
1.1.1.6 root 8795: dsp_core.registers[DSP_REG_A2] = dest[0];
8796: dsp_core.registers[DSP_REG_A1] = dest[1];
8797: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8798:
1.1.1.6 root 8799: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8800:
1.1.1.6 root 8801: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8802: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8803: }
8804:
1.1.1.6 root 8805: static void dsp_subr_b(void)
1.1 root 8806: {
1.1.1.6 root 8807: Uint32 source[3], dest[3];
8808: Uint16 newsr;
1.1 root 8809:
1.1.1.6 root 8810: dest[0] = dsp_core.registers[DSP_REG_B2];
8811: dest[1] = dsp_core.registers[DSP_REG_B1];
8812: dest[2] = dsp_core.registers[DSP_REG_B0];
8813:
8814: newsr = dsp_asr56(dest);
1.1 root 8815:
1.1.1.6 root 8816: source[0] = dsp_core.registers[DSP_REG_A2];
8817: source[1] = dsp_core.registers[DSP_REG_A1];
8818: source[2] = dsp_core.registers[DSP_REG_A0];
8819:
8820: newsr |= dsp_sub56(source, dest);
1.1 root 8821:
1.1.1.6 root 8822: dsp_core.registers[DSP_REG_B2] = dest[0];
8823: dsp_core.registers[DSP_REG_B1] = dest[1];
8824: dsp_core.registers[DSP_REG_B0] = dest[2];
8825:
8826: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8827:
8828: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8829: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8830: }
8831:
1.1.1.6 root 8832: static void dsp_tfr_b_a(void)
1.1 root 8833: {
1.1.1.6 root 8834: dsp_core.registers[DSP_REG_A0] = dsp_core.registers[DSP_REG_B0];
8835: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_B1];
8836: dsp_core.registers[DSP_REG_A2] = dsp_core.registers[DSP_REG_B2];
8837: }
1.1 root 8838:
1.1.1.6 root 8839: static void dsp_tfr_a_b(void)
8840: {
8841: dsp_core.registers[DSP_REG_B0] = dsp_core.registers[DSP_REG_A0];
8842: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_A1];
8843: dsp_core.registers[DSP_REG_B2] = dsp_core.registers[DSP_REG_A2];
8844: }
8845:
8846: static void dsp_tfr_x0_a(void)
8847: {
8848: dsp_core.registers[DSP_REG_A0] = 0;
8849: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_X0];
8850: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
8851: dsp_core.registers[DSP_REG_A2] = 0xff;
8852: else
8853: dsp_core.registers[DSP_REG_A2] = 0x0;
8854: }
8855:
8856: static void dsp_tfr_x0_b(void)
8857: {
8858: dsp_core.registers[DSP_REG_B0] = 0;
8859: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_X0];
8860: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
8861: dsp_core.registers[DSP_REG_B2] = 0xff;
8862: else
8863: dsp_core.registers[DSP_REG_B2] = 0x0;
8864: }
8865:
8866: static void dsp_tfr_y0_a(void)
8867: {
8868: dsp_core.registers[DSP_REG_A0] = 0;
8869: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_Y0];
8870: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
8871: dsp_core.registers[DSP_REG_A2] = 0xff;
8872: else
8873: dsp_core.registers[DSP_REG_A2] = 0x0;
8874: }
8875:
8876: static void dsp_tfr_y0_b(void)
8877: {
8878: dsp_core.registers[DSP_REG_B0] = 0;
8879: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_Y0];
8880: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
8881: dsp_core.registers[DSP_REG_B2] = 0xff;
8882: else
8883: dsp_core.registers[DSP_REG_B2] = 0x0;
8884: }
8885:
8886: static void dsp_tfr_x1_a(void)
8887: {
8888: dsp_core.registers[DSP_REG_A0] = 0;
8889: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_X1];
8890: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
8891: dsp_core.registers[DSP_REG_A2] = 0xff;
8892: else
8893: dsp_core.registers[DSP_REG_A2] = 0x0;
8894: }
8895:
8896: static void dsp_tfr_x1_b(void)
8897: {
8898: dsp_core.registers[DSP_REG_B0] = 0;
8899: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_X1];
8900: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
8901: dsp_core.registers[DSP_REG_B2] = 0xff;
8902: else
8903: dsp_core.registers[DSP_REG_B2] = 0x0;
8904: }
8905:
8906: static void dsp_tfr_y1_a(void)
8907: {
8908: dsp_core.registers[DSP_REG_A0] = 0;
8909: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_Y1];
8910: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
8911: dsp_core.registers[DSP_REG_A2] = 0xff;
8912: else
8913: dsp_core.registers[DSP_REG_A2] = 0x0;
8914: }
8915:
8916: static void dsp_tfr_y1_b(void)
8917: {
8918: dsp_core.registers[DSP_REG_B0] = 0;
8919: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_Y1];
8920: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
8921: dsp_core.registers[DSP_REG_B2] = 0xff;
8922: else
8923: dsp_core.registers[DSP_REG_B2] = 0x0;
8924: }
8925:
8926: static void dsp_tst_a(void)
8927: {
8928: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_A2],
1.1.1.7 ! root 8929: dsp_core.registers[DSP_REG_A1],
! 8930: dsp_core.registers[DSP_REG_A0]);
1.1.1.6 root 8931:
8932: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8933: }
8934:
8935: static void dsp_tst_b(void)
8936: {
8937: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_B2],
1.1.1.7 ! root 8938: dsp_core.registers[DSP_REG_B1],
! 8939: dsp_core.registers[DSP_REG_B0]);
1.1 root 8940:
1.1.1.6 root 8941: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
1.1 root 8942: }
8943:
1.1.1.2 root 8944: /*
8945: vim:ts=4:sw=4:
8946: */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.