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1.1 root 1: /*
1.1.1.2 root 2: DSP M56001 emulation
1.1.1.4 root 3: Instructions interpreter
1.1.1.2 root 4:
5: (C) 2003-2008 ARAnyM developer team
6:
7: This program is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2 of the License, or
10: (at your option) any later version.
11:
12: This program is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
18: along with this program; if not, write to the Free Software
19: Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20: */
21:
1.1.1.7 root 22: /*
23: DSP memory mapping
24: ------------------
25:
26: The memory map is configured as follows :
27: Program space P is one contiguous block of 32K dsp Words
28: X and Y data space are each separate 16K dsp Word blocks.
29: Both X and Y can be accessed as blocks starting at 0 or 16K.
30: Program space physically overlaps both X and Y data spaces.
31: Y: memory is mapped at address $0 in P memory
32: X: memory is mapped at address $4000 in P memory
33:
34: The DSP external RAM is zero waitstate, but there is a penalty for
35: accessing it twice in a single instruction, because there is only
36: one external data bus.
37: The internal buses are all separate (0 waitstate)
38:
39:
40: X: Y: P:
41: $ffff |--------------+--------------+--------------|
42: | Int. I/O | Ext. I/O | |
43: $ffc0 |--------------+--------------+ |
44: | | | |
45: | Reserved | Reserved | Reserved |
46: | | | |
47: | | | |
48: | | | |
49: $8000 |--------------+--------------+--------------|
50: | | | |
51: | 16k Shadow | 16k Shadow | |
52: | | | 32K |
53: $4000 |--------------+--------------| Program |
54: | 16K | 16K | RAM |
55: | External | External | |
56: | RAM | RAM | |
57: $0200 |--------------+--------------+--------------|
58: | Log table or | Sin table or | |
59: | external mem | external mem | Internal |
60: $0100 |--------------+--------------+ program |
61: | Internal X | Internal Y | memory |
62: | memory | memory | |
63: $0000 |--------------+--------------+--------------|
64:
65:
66: Special Note : As the Falcon DSP is a 0 waitstate access memory, I've simplified a little the cycle counting.
67: If this DSP emulator code is used in another project, one should take into account the bus control register (BCR) waitstates.
68: */
69:
1.1.1.2 root 70: #ifdef HAVE_CONFIG_H
71: #include "config.h"
72: #endif
73:
1.1.1.6 root 74: #include <stdbool.h>
75:
1.1.1.2 root 76: #include "dsp_core.h"
1.1 root 77: #include "dsp_cpu.h"
78: #include "dsp_disasm.h"
1.1.1.6 root 79: #include "log.h"
80: # include "main.h"
1.1 root 81:
82:
1.1.1.2 root 83: #define DSP_COUNT_IPS 0 /* Count instruction per seconds */
84:
1.1 root 85:
86: /**********************************
87: * Defines
88: **********************************/
89:
1.1.1.6 root 90: #define SIGN_PLUS 0
91: #define SIGN_MINUS 1
1.1.1.4 root 92:
1.1 root 93: /**********************************
94: * Variables
95: **********************************/
96:
1.1.1.4 root 97: /* Instructions per second */
98: static Uint32 start_time;
99: static Uint32 num_inst;
100:
1.1 root 101: /* Length of current instruction */
1.1.1.2 root 102: static Uint32 cur_inst_len; /* =0:jump, >0:increment */
1.1 root 103:
104: /* Current instruction */
1.1.1.4 root 105: static Uint32 cur_inst;
1.1 root 106:
1.1.1.7 root 107: /* Counts the number of access to the external memory for one instruction */
108: static Uint16 nb_access_to_extMemory;
109:
1.1.1.6 root 110: /* DSP is in disasm mode ? */
111: /* If yes, stack overflow, underflow and illegal instructions messages are not displayed */
112: static bool isDsp_in_disasm_mode;
1.1 root 113:
1.1.1.7 root 114: static char str_disasm_memory[2][50]; /* Buffer for memory change text in disasm mode */
1.1.1.5 root 115: static Uint16 disasm_memory_ptr; /* Pointer for memory change in disasm mode */
1.1 root 116:
117: /**********************************
118: * Functions
119: **********************************/
120:
121: typedef void (*dsp_emul_t)(void);
122:
123: static void dsp_postexecute_update_pc(void);
124: static void dsp_postexecute_interrupts(void);
125:
1.1.1.5 root 126: static void dsp_setInterruptIPL(Uint32 value);
127:
1.1.1.6 root 128: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2);
1.1.1.2 root 129:
130: static Uint32 read_memory(int space, Uint16 address);
1.1.1.6 root 131: static inline Uint32 read_memory_p(Uint16 address);
1.1.1.2 root 132: static Uint32 read_memory_disasm(int space, Uint16 address);
1.1.1.6 root 133:
134: static inline void write_memory(int space, Uint16 address, Uint32 value);
135: static void write_memory_raw(int space, Uint16 address, Uint32 value);
1.1.1.4 root 136: static void write_memory_disasm(int space, Uint16 address, Uint32 value);
1.1.1.6 root 137:
1.1.1.4 root 138: static void dsp_write_reg(Uint32 numreg, Uint32 value);
1.1 root 139:
1.1.1.4 root 140: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly);
1.1.1.2 root 141: static void dsp_stack_pop(Uint32 *curpc, Uint32 *cursr);
1.1.1.4 root 142: static void dsp_compute_ssh_ssl(void);
1.1 root 143:
144: static void opcode8h_0(void);
145:
1.1.1.2 root 146: static void dsp_update_rn(Uint32 numreg, Sint16 modifier);
147: static void dsp_update_rn_bitreverse(Uint32 numreg);
148: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier);
149: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr);
150: static int dsp_calc_cc(Uint32 cc_code);
1.1 root 151:
152: static void dsp_undefined(void);
153:
154: /* Instructions without parallel moves */
155: static void dsp_andi(void);
1.1.1.4 root 156: static void dsp_bchg_aa(void);
157: static void dsp_bchg_ea(void);
158: static void dsp_bchg_pp(void);
159: static void dsp_bchg_reg(void);
160: static void dsp_bclr_aa(void);
161: static void dsp_bclr_ea(void);
162: static void dsp_bclr_pp(void);
163: static void dsp_bclr_reg(void);
164: static void dsp_bset_aa(void);
165: static void dsp_bset_ea(void);
166: static void dsp_bset_pp(void);
167: static void dsp_bset_reg(void);
168: static void dsp_btst_aa(void);
169: static void dsp_btst_ea(void);
170: static void dsp_btst_pp(void);
171: static void dsp_btst_reg(void);
1.1 root 172: static void dsp_div(void);
173: static void dsp_enddo(void);
174: static void dsp_illegal(void);
1.1.1.4 root 175: static void dsp_jcc_imm(void);
176: static void dsp_jcc_ea(void);
177: static void dsp_jclr_aa(void);
178: static void dsp_jclr_ea(void);
179: static void dsp_jclr_pp(void);
180: static void dsp_jclr_reg(void);
181: static void dsp_jmp_ea(void);
182: static void dsp_jmp_imm(void);
183: static void dsp_jscc_ea(void);
184: static void dsp_jscc_imm(void);
185: static void dsp_jsclr_aa(void);
186: static void dsp_jsclr_ea(void);
187: static void dsp_jsclr_pp(void);
188: static void dsp_jsclr_reg(void);
189: static void dsp_jset_aa(void);
190: static void dsp_jset_ea(void);
191: static void dsp_jset_pp(void);
192: static void dsp_jset_reg(void);
193: static void dsp_jsr_ea(void);
194: static void dsp_jsr_imm(void);
195: static void dsp_jsset_aa(void);
196: static void dsp_jsset_ea(void);
197: static void dsp_jsset_pp(void);
198: static void dsp_jsset_reg(void);
1.1 root 199: static void dsp_lua(void);
1.1.1.4 root 200: static void dsp_movem_ea(void);
201: static void dsp_movem_aa(void);
1.1 root 202: static void dsp_nop(void);
203: static void dsp_norm(void);
204: static void dsp_ori(void);
205: static void dsp_reset(void);
206: static void dsp_rti(void);
207: static void dsp_rts(void);
208: static void dsp_stop(void);
209: static void dsp_swi(void);
210: static void dsp_tcc(void);
211: static void dsp_wait(void);
212:
1.1.1.3 root 213: static void dsp_do_ea(void);
214: static void dsp_do_aa(void);
215: static void dsp_do_imm(void);
216: static void dsp_do_reg(void);
217: static void dsp_rep_aa(void);
218: static void dsp_rep_ea(void);
219: static void dsp_rep_imm(void);
220: static void dsp_rep_reg(void);
221: static void dsp_movec_aa(void);
222: static void dsp_movec_ea(void);
223: static void dsp_movec_imm(void);
224: static void dsp_movec_reg(void);
1.1 root 225: static void dsp_movep_0(void);
226: static void dsp_movep_1(void);
1.1.1.4 root 227: static void dsp_movep_23(void);
1.1 root 228:
229: /* Parallel move analyzer */
1.1.1.2 root 230: static int dsp_pm_read_accu24(int numreg, Uint32 *dest);
1.1 root 231: static void dsp_pm_0(void);
232: static void dsp_pm_1(void);
233: static void dsp_pm_2(void);
234: static void dsp_pm_2_2(void);
235: static void dsp_pm_3(void);
236: static void dsp_pm_4(void);
1.1.1.4 root 237: static void dsp_pm_4x(void);
1.1 root 238: static void dsp_pm_5(void);
239: static void dsp_pm_8(void);
240:
241: /* 56bits arithmetic */
1.1.1.2 root 242: static Uint16 dsp_abs56(Uint32 *dest);
243: static Uint16 dsp_asl56(Uint32 *dest);
244: static Uint16 dsp_asr56(Uint32 *dest);
245: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest);
246: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest);
1.1.1.5 root 247: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe);
1.1.1.2 root 248: static void dsp_rnd56(Uint32 *dest);
1.1 root 249:
250: /* Instructions with parallel moves */
1.1.1.6 root 251: static void dsp_abs_a(void);
252: static void dsp_abs_b(void);
253: static void dsp_adc_x_a(void);
254: static void dsp_adc_x_b(void);
255: static void dsp_adc_y_a(void);
256: static void dsp_adc_y_b(void);
257: static void dsp_add_b_a(void);
258: static void dsp_add_a_b(void);
259: static void dsp_add_x_a(void);
260: static void dsp_add_x_b(void);
261: static void dsp_add_y_a(void);
262: static void dsp_add_y_b(void);
263: static void dsp_add_x0_a(void);
264: static void dsp_add_x0_b(void);
265: static void dsp_add_y0_a(void);
266: static void dsp_add_y0_b(void);
267: static void dsp_add_x1_a(void);
268: static void dsp_add_x1_b(void);
269: static void dsp_add_y1_a(void);
270: static void dsp_add_y1_b(void);
271: static void dsp_addl_b_a(void);
272: static void dsp_addl_b_a(void);
273: static void dsp_addl_a_b(void);
274: static void dsp_addr_b_a(void);
275: static void dsp_addr_a_b(void);
276: static void dsp_and_x0_a(void);
277: static void dsp_and_x0_b(void);
278: static void dsp_and_y0_a(void);
279: static void dsp_and_y0_b(void);
280: static void dsp_and_x1_a(void);
281: static void dsp_and_x1_b(void);
282: static void dsp_and_y1_a(void);
283: static void dsp_and_y1_b(void);
1.1.1.7 root 284: static void dsp_asl_a(void);
285: static void dsp_asl_b(void);
286: static void dsp_asr_a(void);
287: static void dsp_asr_b(void);
1.1.1.6 root 288: static void dsp_clr_a(void);
289: static void dsp_clr_b(void);
290: static void dsp_cmp_b_a(void);
291: static void dsp_cmp_a_b(void);
292: static void dsp_cmp_x0_a(void);
293: static void dsp_cmp_x0_b(void);
294: static void dsp_cmp_y0_a(void);
295: static void dsp_cmp_y0_b(void);
296: static void dsp_cmp_x1_a(void);
297: static void dsp_cmp_x1_b(void);
298: static void dsp_cmp_y1_a(void);
299: static void dsp_cmp_y1_b(void);
300: static void dsp_cmpm_b_a(void);
301: static void dsp_cmpm_a_b(void);
302: static void dsp_cmpm_x0_a(void);
303: static void dsp_cmpm_x0_b(void);
304: static void dsp_cmpm_y0_a(void);
305: static void dsp_cmpm_y0_b(void);
306: static void dsp_cmpm_x1_a(void);
307: static void dsp_cmpm_x1_b(void);
308: static void dsp_cmpm_y1_a(void);
309: static void dsp_cmpm_y1_b(void);
310: static void dsp_eor_x0_a(void);
311: static void dsp_eor_x0_b(void);
312: static void dsp_eor_y0_a(void);
313: static void dsp_eor_y0_b(void);
314: static void dsp_eor_x1_a(void);
315: static void dsp_eor_x1_b(void);
316: static void dsp_eor_y1_a(void);
317: static void dsp_eor_y1_b(void);
318: static void dsp_lsl_a(void);
319: static void dsp_lsl_b(void);
320: static void dsp_lsr_a(void);
321: static void dsp_lsr_b(void);
322: static void dsp_mac_p_x0_x0_a(void);
323: static void dsp_mac_m_x0_x0_a(void);
324: static void dsp_mac_p_x0_x0_b(void);
325: static void dsp_mac_m_x0_x0_b(void);
326: static void dsp_mac_p_y0_y0_a(void);
327: static void dsp_mac_m_y0_y0_a(void);
328: static void dsp_mac_p_y0_y0_b(void);
329: static void dsp_mac_m_y0_y0_b(void);
330: static void dsp_mac_p_x1_x0_a(void);
331: static void dsp_mac_m_x1_x0_a(void);
332: static void dsp_mac_p_x1_x0_b(void);
333: static void dsp_mac_m_x1_x0_b(void);
334: static void dsp_mac_p_y1_y0_a(void);
335: static void dsp_mac_m_y1_y0_a(void);
336: static void dsp_mac_p_y1_y0_b(void);
337: static void dsp_mac_m_y1_y0_b(void);
338: static void dsp_mac_p_x0_y1_a(void);
339: static void dsp_mac_m_x0_y1_a(void);
340: static void dsp_mac_p_x0_y1_b(void);
341: static void dsp_mac_m_x0_y1_b(void);
342: static void dsp_mac_p_y0_x0_a(void);
343: static void dsp_mac_m_y0_x0_a(void);
344: static void dsp_mac_p_y0_x0_b(void);
345: static void dsp_mac_m_y0_x0_b(void);
346: static void dsp_mac_p_x1_y0_a(void);
347: static void dsp_mac_m_x1_y0_a(void);
348: static void dsp_mac_p_x1_y0_b(void);
349: static void dsp_mac_m_x1_y0_b(void);
350: static void dsp_mac_p_y1_x1_a(void);
351: static void dsp_mac_m_y1_x1_a(void);
352: static void dsp_mac_p_y1_x1_b(void);
353: static void dsp_mac_m_y1_x1_b(void);
354: static void dsp_macr_p_x0_x0_a(void);
355: static void dsp_macr_m_x0_x0_a(void);
356: static void dsp_macr_p_x0_x0_b(void);
357: static void dsp_macr_m_x0_x0_b(void);
358: static void dsp_macr_p_y0_y0_a(void);
359: static void dsp_macr_m_y0_y0_a(void);
360: static void dsp_macr_p_y0_y0_b(void);
361: static void dsp_macr_m_y0_y0_b(void);
362: static void dsp_macr_p_x1_x0_a(void);
363: static void dsp_macr_m_x1_x0_a(void);
364: static void dsp_macr_p_x1_x0_b(void);
365: static void dsp_macr_m_x1_x0_b(void);
366: static void dsp_macr_p_y1_y0_a(void);
367: static void dsp_macr_m_y1_y0_a(void);
368: static void dsp_macr_p_y1_y0_b(void);
369: static void dsp_macr_m_y1_y0_b(void);
370: static void dsp_macr_p_x0_y1_a(void);
371: static void dsp_macr_m_x0_y1_a(void);
372: static void dsp_macr_p_x0_y1_b(void);
373: static void dsp_macr_m_x0_y1_b(void);
374: static void dsp_macr_p_y0_x0_a(void);
375: static void dsp_macr_m_y0_x0_a(void);
376: static void dsp_macr_p_y0_x0_b(void);
377: static void dsp_macr_m_y0_x0_b(void);
378: static void dsp_macr_p_x1_y0_a(void);
379: static void dsp_macr_m_x1_y0_a(void);
380: static void dsp_macr_p_x1_y0_b(void);
381: static void dsp_macr_m_x1_y0_b(void);
382: static void dsp_macr_p_y1_x1_a(void);
383: static void dsp_macr_m_y1_x1_a(void);
384: static void dsp_macr_p_y1_x1_b(void);
385: static void dsp_macr_m_y1_x1_b(void);
1.1 root 386: static void dsp_move(void);
1.1.1.6 root 387: static void dsp_mpy_p_x0_x0_a(void);
388: static void dsp_mpy_m_x0_x0_a(void);
389: static void dsp_mpy_p_x0_x0_b(void);
390: static void dsp_mpy_m_x0_x0_b(void);
391: static void dsp_mpy_p_y0_y0_a(void);
392: static void dsp_mpy_m_y0_y0_a(void);
393: static void dsp_mpy_p_y0_y0_b(void);
394: static void dsp_mpy_m_y0_y0_b(void);
395: static void dsp_mpy_p_x1_x0_a(void);
396: static void dsp_mpy_m_x1_x0_a(void);
397: static void dsp_mpy_p_x1_x0_b(void);
398: static void dsp_mpy_m_x1_x0_b(void);
399: static void dsp_mpy_p_y1_y0_a(void);
400: static void dsp_mpy_m_y1_y0_a(void);
401: static void dsp_mpy_p_y1_y0_b(void);
402: static void dsp_mpy_m_y1_y0_b(void);
403: static void dsp_mpy_p_x0_y1_a(void);
404: static void dsp_mpy_m_x0_y1_a(void);
405: static void dsp_mpy_p_x0_y1_b(void);
406: static void dsp_mpy_m_x0_y1_b(void);
407: static void dsp_mpy_p_y0_x0_a(void);
408: static void dsp_mpy_m_y0_x0_a(void);
409: static void dsp_mpy_p_y0_x0_b(void);
410: static void dsp_mpy_m_y0_x0_b(void);
411: static void dsp_mpy_p_x1_y0_a(void);
412: static void dsp_mpy_m_x1_y0_a(void);
413: static void dsp_mpy_p_x1_y0_b(void);
414: static void dsp_mpy_m_x1_y0_b(void);
415: static void dsp_mpy_p_y1_x1_a(void);
416: static void dsp_mpy_m_y1_x1_a(void);
417: static void dsp_mpy_p_y1_x1_b(void);
418: static void dsp_mpy_m_y1_x1_b(void);
419: static void dsp_mpyr_p_x0_x0_a(void);
420: static void dsp_mpyr_m_x0_x0_a(void);
421: static void dsp_mpyr_p_x0_x0_b(void);
422: static void dsp_mpyr_m_x0_x0_b(void);
423: static void dsp_mpyr_p_y0_y0_a(void);
424: static void dsp_mpyr_m_y0_y0_a(void);
425: static void dsp_mpyr_p_y0_y0_b(void);
426: static void dsp_mpyr_m_y0_y0_b(void);
427: static void dsp_mpyr_p_x1_x0_a(void);
428: static void dsp_mpyr_m_x1_x0_a(void);
429: static void dsp_mpyr_p_x1_x0_b(void);
430: static void dsp_mpyr_m_x1_x0_b(void);
431: static void dsp_mpyr_p_y1_y0_a(void);
432: static void dsp_mpyr_m_y1_y0_a(void);
433: static void dsp_mpyr_p_y1_y0_b(void);
434: static void dsp_mpyr_m_y1_y0_b(void);
435: static void dsp_mpyr_p_x0_y1_a(void);
436: static void dsp_mpyr_m_x0_y1_a(void);
437: static void dsp_mpyr_p_x0_y1_b(void);
438: static void dsp_mpyr_m_x0_y1_b(void);
439: static void dsp_mpyr_p_y0_x0_a(void);
440: static void dsp_mpyr_m_y0_x0_a(void);
441: static void dsp_mpyr_p_y0_x0_b(void);
442: static void dsp_mpyr_m_y0_x0_b(void);
443: static void dsp_mpyr_p_x1_y0_a(void);
444: static void dsp_mpyr_m_x1_y0_a(void);
445: static void dsp_mpyr_p_x1_y0_b(void);
446: static void dsp_mpyr_m_x1_y0_b(void);
447: static void dsp_mpyr_p_y1_x1_a(void);
448: static void dsp_mpyr_m_y1_x1_a(void);
449: static void dsp_mpyr_p_y1_x1_b(void);
450: static void dsp_mpyr_m_y1_x1_b(void);
451: static void dsp_neg_a(void);
452: static void dsp_neg_b(void);
453: static void dsp_not_a(void);
454: static void dsp_not_b(void);
455: static void dsp_or_x0_a(void);
456: static void dsp_or_x0_b(void);
457: static void dsp_or_y0_a(void);
458: static void dsp_or_y0_b(void);
459: static void dsp_or_x1_a(void);
460: static void dsp_or_x1_b(void);
461: static void dsp_or_y1_a(void);
462: static void dsp_or_y1_b(void);
463: static void dsp_rnd_a(void);
464: static void dsp_rnd_b(void);
465: static void dsp_rol_a(void);
466: static void dsp_rol_b(void);
467: static void dsp_ror_a(void);
468: static void dsp_ror_b(void);
469: static void dsp_sbc_x_a(void);
470: static void dsp_sbc_x_b(void);
471: static void dsp_sbc_y_a(void);
472: static void dsp_sbc_y_b(void);
473: static void dsp_sub_b_a(void);
474: static void dsp_sub_a_b(void);
475: static void dsp_sub_x_a(void);
476: static void dsp_sub_x_b(void);
477: static void dsp_sub_y_a(void);
478: static void dsp_sub_y_b(void);
479: static void dsp_sub_x0_a(void);
480: static void dsp_sub_x0_b(void);
481: static void dsp_sub_y0_a(void);
482: static void dsp_sub_y0_b(void);
483: static void dsp_sub_x1_a(void);
484: static void dsp_sub_x1_b(void);
485: static void dsp_sub_y1_a(void);
486: static void dsp_sub_y1_b(void);
487: static void dsp_subl_a(void);
488: static void dsp_subl_b(void);
489: static void dsp_subr_a(void);
490: static void dsp_subr_b(void);
491: static void dsp_tfr_b_a(void);
492: static void dsp_tfr_a_b(void);
493: static void dsp_tfr_x0_a(void);
494: static void dsp_tfr_x0_b(void);
495: static void dsp_tfr_y0_a(void);
496: static void dsp_tfr_y0_b(void);
497: static void dsp_tfr_x1_a(void);
498: static void dsp_tfr_x1_b(void);
499: static void dsp_tfr_y1_a(void);
500: static void dsp_tfr_y1_b(void);
501: static void dsp_tst_a(void);
502: static void dsp_tst_b(void);
1.1 root 503:
1.1.1.6 root 504: static const dsp_emul_t opcodes8h[512] = {
1.1.1.4 root 505: /* 0x00 - 0x3f */
506: opcode8h_0, dsp_undefined, dsp_undefined, dsp_undefined, opcode8h_0, dsp_andi, dsp_undefined, dsp_ori,
507: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
508: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
509: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
510: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
511: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
512: dsp_undefined, dsp_undefined, dsp_div, dsp_div, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
513: dsp_norm, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
514:
515: /* 0x40 - 0x7f */
516: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
517: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
518: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
519: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
520: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
521: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
522: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
523: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
524:
525: /* 0x80 - 0xbf */
526: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
527: dsp_lua, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
528: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
529: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
530: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
531: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
532: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
533: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
534:
535: /* 0xc0 - 0xff */
536: dsp_do_aa, dsp_rep_aa, dsp_do_aa, dsp_rep_aa, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
537: dsp_do_ea, dsp_rep_ea, dsp_do_ea, dsp_rep_ea, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
538: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
539: dsp_do_reg, dsp_rep_reg, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
540: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
541: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
542: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
543: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
544:
545: /* 0x100 - 0x13f */
1.1.1.6 root 546: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 547: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 548: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 549: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 550: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 551: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 552: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 553: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
554:
555: /* 0x140 - 0x17f */
556: dsp_bclr_aa, dsp_bset_aa, dsp_bclr_aa, dsp_bset_aa, dsp_jclr_aa, dsp_jset_aa, dsp_jclr_aa, dsp_jset_aa,
557: dsp_bclr_ea, dsp_bset_ea, dsp_bclr_ea, dsp_bset_ea, dsp_jclr_ea, dsp_jset_ea, dsp_jclr_ea, dsp_jset_ea,
558: dsp_bclr_pp, dsp_bset_pp, dsp_bclr_pp, dsp_bset_pp, dsp_jclr_pp, dsp_jset_pp, dsp_jclr_pp, dsp_jset_pp,
559: dsp_jclr_reg, dsp_jset_reg, dsp_bclr_reg, dsp_bset_reg, dsp_jmp_ea, dsp_jcc_ea, dsp_undefined, dsp_undefined,
560: dsp_bchg_aa, dsp_btst_aa, dsp_bchg_aa, dsp_btst_aa, dsp_jsclr_aa, dsp_jsset_aa, dsp_jsclr_aa, dsp_jsset_aa,
561: dsp_bchg_ea, dsp_btst_ea, dsp_bchg_ea, dsp_btst_ea, dsp_jsclr_ea, dsp_jsset_ea, dsp_jsclr_ea, dsp_jsset_ea,
562: dsp_bchg_pp, dsp_btst_pp, dsp_bchg_pp, dsp_btst_pp, dsp_jsclr_pp, dsp_jsset_pp, dsp_jsclr_pp, dsp_jsset_pp,
563: dsp_jsclr_reg, dsp_jsset_reg, dsp_bchg_reg, dsp_btst_reg, dsp_jsr_ea, dsp_jscc_ea, dsp_undefined, dsp_undefined,
564:
565: /* 0x180 - 0x1bf */
566: dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm,
567: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
568: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
569: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
570: dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm,
571: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
572: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
573: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
574:
575: /* 0x1c0 - 0x1ff */
576: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
577: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
578: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
579: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
580: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
581: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
582: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
583: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
1.1 root 584: };
585:
1.1.1.6 root 586: static const dsp_emul_t opcodes_parmove[16] = {
587: dsp_pm_0, dsp_pm_1, dsp_pm_2, dsp_pm_3, dsp_pm_4, dsp_pm_5, dsp_pm_5, dsp_pm_5,
588: dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8
1.1 root 589: };
590:
1.1.1.6 root 591: static const dsp_emul_t opcodes_alu[256] = {
1.1.1.4 root 592: /* 0x00 - 0x3f */
1.1.1.6 root 593: dsp_move , dsp_tfr_b_a, dsp_addr_b_a, dsp_tst_a, dsp_undefined, dsp_cmp_b_a, dsp_subr_a, dsp_cmpm_b_a,
594: dsp_undefined, dsp_tfr_a_b, dsp_addr_a_b, dsp_tst_b, dsp_undefined, dsp_cmp_a_b, dsp_subr_b, dsp_cmpm_a_b,
595: dsp_add_b_a, dsp_rnd_a, dsp_addl_b_a, dsp_clr_a, dsp_sub_b_a, dsp_undefined, dsp_subl_a, dsp_not_a,
596: dsp_add_a_b, dsp_rnd_b, dsp_addl_a_b, dsp_clr_b, dsp_sub_a_b, dsp_undefined, dsp_subl_b, dsp_not_b,
1.1.1.7 root 597: dsp_add_x_a, dsp_adc_x_a, dsp_asr_a, dsp_lsr_a, dsp_sub_x_a, dsp_sbc_x_a, dsp_abs_a, dsp_ror_a,
598: dsp_add_x_b, dsp_adc_x_b, dsp_asr_b, dsp_lsr_b, dsp_sub_x_b, dsp_sbc_x_b, dsp_abs_b, dsp_ror_b,
599: dsp_add_y_a, dsp_adc_y_a, dsp_asl_a, dsp_lsl_a, dsp_sub_y_a, dsp_sbc_y_a, dsp_neg_a, dsp_rol_a,
600: dsp_add_y_b, dsp_adc_y_b, dsp_asl_b, dsp_lsl_b, dsp_sub_y_b, dsp_sbc_y_b, dsp_neg_b, dsp_rol_b,
1.1.1.4 root 601:
602: /* 0x40 - 0x7f */
1.1.1.6 root 603: dsp_add_x0_a, dsp_tfr_x0_a, dsp_or_x0_a, dsp_eor_x0_a, dsp_sub_x0_a, dsp_cmp_x0_a, dsp_and_x0_a, dsp_cmpm_x0_a,
604: dsp_add_x0_b, dsp_tfr_x0_b, dsp_or_x0_b, dsp_eor_x0_b, dsp_sub_x0_b, dsp_cmp_x0_b, dsp_and_x0_b, dsp_cmpm_x0_b,
605: dsp_add_y0_a, dsp_tfr_y0_a, dsp_or_y0_a, dsp_eor_y0_a, dsp_sub_y0_a, dsp_cmp_y0_a, dsp_and_y0_a, dsp_cmpm_y0_a,
606: dsp_add_y0_b, dsp_tfr_y0_b, dsp_or_y0_b, dsp_eor_y0_b, dsp_sub_y0_b, dsp_cmp_y0_b, dsp_and_y0_b, dsp_cmpm_y0_b,
607: dsp_add_x1_a, dsp_tfr_x1_a, dsp_or_x1_a, dsp_eor_x1_a, dsp_sub_x1_a, dsp_cmp_x1_a, dsp_and_x1_a, dsp_cmpm_x1_a,
608: dsp_add_x1_b, dsp_tfr_x1_b, dsp_or_x1_b, dsp_eor_x1_b, dsp_sub_x1_b, dsp_cmp_x1_b, dsp_and_x1_b, dsp_cmpm_x1_b,
609: dsp_add_y1_a, dsp_tfr_y1_a, dsp_or_y1_a, dsp_eor_y1_a, dsp_sub_y1_a, dsp_cmp_y1_a, dsp_and_y1_a, dsp_cmpm_y1_a,
610: dsp_add_y1_b, dsp_tfr_y1_b, dsp_or_y1_b, dsp_eor_y1_b, dsp_sub_y1_b, dsp_cmp_y1_b, dsp_and_y1_b, dsp_cmpm_y1_b,
1.1.1.4 root 611:
612: /* 0x80 - 0xbf */
1.1.1.6 root 613: dsp_mpy_p_x0_x0_a, dsp_mpyr_p_x0_x0_a, dsp_mac_p_x0_x0_a, dsp_macr_p_x0_x0_a, dsp_mpy_m_x0_x0_a, dsp_mpyr_m_x0_x0_a, dsp_mac_m_x0_x0_a, dsp_macr_m_x0_x0_a,
614: dsp_mpy_p_x0_x0_b, dsp_mpyr_p_x0_x0_b, dsp_mac_p_x0_x0_b, dsp_macr_p_x0_x0_b, dsp_mpy_m_x0_x0_b, dsp_mpyr_m_x0_x0_b, dsp_mac_m_x0_x0_b, dsp_macr_m_x0_x0_b,
615: dsp_mpy_p_y0_y0_a, dsp_mpyr_p_y0_y0_a, dsp_mac_p_y0_y0_a, dsp_macr_p_y0_y0_a, dsp_mpy_m_y0_y0_a, dsp_mpyr_m_y0_y0_a, dsp_mac_m_y0_y0_a, dsp_macr_m_y0_y0_a,
616: dsp_mpy_p_y0_y0_b, dsp_mpyr_p_y0_y0_b, dsp_mac_p_y0_y0_b, dsp_macr_p_y0_y0_b, dsp_mpy_m_y0_y0_b, dsp_mpyr_m_y0_y0_b, dsp_mac_m_y0_y0_b, dsp_macr_m_y0_y0_b,
617: dsp_mpy_p_x1_x0_a, dsp_mpyr_p_x1_x0_a, dsp_mac_p_x1_x0_a, dsp_macr_p_x1_x0_a, dsp_mpy_m_x1_x0_a, dsp_mpyr_m_x1_x0_a, dsp_mac_m_x1_x0_a, dsp_macr_m_x1_x0_a,
618: dsp_mpy_p_x1_x0_b, dsp_mpyr_p_x1_x0_b, dsp_mac_p_x1_x0_b, dsp_macr_p_x1_x0_b, dsp_mpy_m_x1_x0_b, dsp_mpyr_m_x1_x0_b, dsp_mac_m_x1_x0_b, dsp_macr_m_x1_x0_b,
619: dsp_mpy_p_y1_y0_a, dsp_mpyr_p_y1_y0_a, dsp_mac_p_y1_y0_a, dsp_macr_p_y1_y0_a, dsp_mpy_m_y1_y0_a, dsp_mpyr_m_y1_y0_a, dsp_mac_m_y1_y0_a, dsp_macr_m_y1_y0_a,
620: dsp_mpy_p_y1_y0_b, dsp_mpyr_p_y1_y0_b, dsp_mac_p_y1_y0_b, dsp_macr_p_y1_y0_b, dsp_mpy_m_y1_y0_b, dsp_mpyr_m_y1_y0_b, dsp_mac_m_y1_y0_b, dsp_macr_m_y1_y0_b,
621:
622: /* 0xc0_m_ 0xff */
623: dsp_mpy_p_x0_y1_a, dsp_mpyr_p_x0_y1_a, dsp_mac_p_x0_y1_a, dsp_macr_p_x0_y1_a, dsp_mpy_m_x0_y1_a, dsp_mpyr_m_x0_y1_a, dsp_mac_m_x0_y1_a, dsp_macr_m_x0_y1_a,
624: dsp_mpy_p_x0_y1_b, dsp_mpyr_p_x0_y1_b, dsp_mac_p_x0_y1_b, dsp_macr_p_x0_y1_b, dsp_mpy_m_x0_y1_b, dsp_mpyr_m_x0_y1_b, dsp_mac_m_x0_y1_b, dsp_macr_m_x0_y1_b,
625: dsp_mpy_p_y0_x0_a, dsp_mpyr_p_y0_x0_a, dsp_mac_p_y0_x0_a, dsp_macr_p_y0_x0_a, dsp_mpy_m_y0_x0_a, dsp_mpyr_m_y0_x0_a, dsp_mac_m_y0_x0_a, dsp_macr_m_y0_x0_a,
626: dsp_mpy_p_y0_x0_b, dsp_mpyr_p_y0_x0_b, dsp_mac_p_y0_x0_b, dsp_macr_p_y0_x0_b, dsp_mpy_m_y0_x0_b, dsp_mpyr_m_y0_x0_b, dsp_mac_m_y0_x0_b, dsp_macr_m_y0_x0_b,
627: dsp_mpy_p_x1_y0_a, dsp_mpyr_p_x1_y0_a, dsp_mac_p_x1_y0_a, dsp_macr_p_x1_y0_a, dsp_mpy_m_x1_y0_a, dsp_mpyr_m_x1_y0_a, dsp_mac_m_x1_y0_a, dsp_macr_m_x1_y0_a,
628: dsp_mpy_p_x1_y0_b, dsp_mpyr_p_x1_y0_b, dsp_mac_p_x1_y0_b, dsp_macr_p_x1_y0_b, dsp_mpy_m_x1_y0_b, dsp_mpyr_m_x1_y0_b, dsp_mac_m_x1_y0_b, dsp_macr_m_x1_y0_b,
629: dsp_mpy_p_y1_x1_a, dsp_mpyr_p_y1_x1_a, dsp_mac_p_y1_x1_a, dsp_macr_p_y1_x1_a, dsp_mpy_m_y1_x1_a, dsp_mpyr_m_y1_x1_a, dsp_mac_m_y1_x1_a, dsp_macr_m_y1_x1_a,
630: dsp_mpy_p_y1_x1_b, dsp_mpyr_p_y1_x1_b, dsp_mac_p_y1_x1_b, dsp_macr_p_y1_x1_b, dsp_mpy_m_y1_x1_b, dsp_mpyr_m_y1_x1_b, dsp_mac_m_y1_x1_b, dsp_macr_m_y1_x1_b
1.1 root 631: };
632:
1.1.1.6 root 633: static const int registers_tcc[16][2] = {
1.1 root 634: {DSP_REG_B,DSP_REG_A},
635: {DSP_REG_A,DSP_REG_B},
636: {DSP_REG_NULL,DSP_REG_NULL},
637: {DSP_REG_NULL,DSP_REG_NULL},
638:
639: {DSP_REG_NULL,DSP_REG_NULL},
640: {DSP_REG_NULL,DSP_REG_NULL},
641: {DSP_REG_NULL,DSP_REG_NULL},
642: {DSP_REG_NULL,DSP_REG_NULL},
643:
644: {DSP_REG_X0,DSP_REG_A},
645: {DSP_REG_X0,DSP_REG_B},
646: {DSP_REG_Y0,DSP_REG_A},
647: {DSP_REG_Y0,DSP_REG_B},
1.1.1.2 root 648:
649: {DSP_REG_X1,DSP_REG_A},
650: {DSP_REG_X1,DSP_REG_B},
1.1 root 651: {DSP_REG_Y1,DSP_REG_A},
652: {DSP_REG_Y1,DSP_REG_B}
653: };
654:
1.1.1.6 root 655: static const int registers_mask[64] = {
1.1 root 656: 0, 0, 0, 0,
657: 24, 24, 24, 24,
658: 24, 24, 8, 8,
659: 24, 24, 24, 24,
660:
661: 16, 16, 16, 16,
662: 16, 16, 16, 16,
663: 16, 16, 16, 16,
664: 16, 16, 16, 16,
665:
666: 16, 16, 16, 16,
667: 16, 16, 16, 16,
668: 0, 0, 0, 0,
669: 0, 0, 0, 0,
670:
671: 0, 0, 0, 0,
672: 0, 0, 0, 0,
673: 0, 16, 8, 6,
1.1.1.4 root 674: 16, 16, 16, 16
675: };
676:
1.1.1.6 root 677: static const dsp_interrupt_t dsp_interrupt[12] = {
1.1.1.5 root 678: {DSP_INTER_RESET , 0x00, 0, "Reset"},
679: {DSP_INTER_ILLEGAL , 0x3e, 0, "Illegal"},
680: {DSP_INTER_STACK_ERROR , 0x02, 0, "Stack Error"},
681: {DSP_INTER_TRACE , 0x04, 0, "Trace"},
682: {DSP_INTER_SWI , 0x06, 0, "Swi"},
683: {DSP_INTER_HOST_COMMAND , 0xff, 1, "Host Command"},
684: {DSP_INTER_HOST_RCV_DATA, 0x20, 1, "Host receive"},
685: {DSP_INTER_HOST_TRX_DATA, 0x22, 1, "Host transmit"},
686: {DSP_INTER_SSI_RCV_DATA_E, 0x0e, 2, "SSI receive with exception"},
687: {DSP_INTER_SSI_RCV_DATA , 0x0c, 2, "SSI receive"},
688: {DSP_INTER_SSI_TRX_DATA_E, 0x12, 2, "SSI transmit with exception"},
689: {DSP_INTER_SSI_TRX_DATA , 0x10, 2, "SSI tramsmit"}
1.1.1.4 root 690: };
691:
1.1 root 692:
693: /**********************************
694: * Emulator kernel
695: **********************************/
696:
1.1.1.6 root 697: void dsp56k_init_cpu(void)
1.1 root 698: {
1.1.1.6 root 699: dsp56k_disasm_init();
700: isDsp_in_disasm_mode = false;
1.1.1.2 root 701: start_time = SDL_GetTicks();
702: num_inst = 0;
1.1 root 703: }
704:
1.1.1.6 root 705: /**
706: * Execute one instruction in trace mode at a given PC address.
707: * */
1.1.1.8 ! root 708: Uint16 dsp56k_execute_one_disasm_instruction(Uint16 pc)
1.1.1.6 root 709: {
710: dsp_core_t *ptr1, *ptr2;
711: static dsp_core_t dsp_core_save;
1.1.1.8 ! root 712: Uint16 instruction_length;
1.1.1.6 root 713:
714: ptr1 = &dsp_core;
715: ptr2 = &dsp_core_save;
716:
717: /* Set DSP in disasm mode */
718: isDsp_in_disasm_mode = true;
719:
720: /* Save DSP context before executing instruction */
721: memcpy(ptr2, ptr1, sizeof(dsp_core));
722:
723: /* execute and disasm instruction */
724: dsp_core.pc = pc;
725:
726: /* Disasm instruction */
727: instruction_length = dsp56k_disasm(DSP_DISASM_MODE) - 1;
728:
729: /* Execute instruction at address given in parameter to get the number of cycles it takes */
730: dsp56k_execute_instruction();
731:
732: fprintf(stderr, "%s", dsp56k_getInstructionText());
733:
734: /* Restore DSP context after executing instruction */
735: memcpy(ptr1, ptr2, sizeof(dsp_core));
736:
737: /* Unset DSP in disasm mode */
738: isDsp_in_disasm_mode = false;
739:
740: return instruction_length;
741: }
742:
1.1.1.4 root 743: void dsp56k_execute_instruction(void)
1.1 root 744: {
1.1.1.2 root 745: Uint32 value;
1.1.1.6 root 746: Uint32 disasm_return = 0;
1.1.1.5 root 747: disasm_memory_ptr = 0;
748:
1.1.1.7 root 749: /* Initialise the number of access to the external memory for this instruction */
750: nb_access_to_extMemory = 0;
751:
1.1 root 752: /* Decode and execute current instruction */
1.1.1.6 root 753: cur_inst = read_memory_p(dsp_core.pc);
1.1.1.4 root 754:
1.1.1.7 root 755: /* Initialize instruction size and cycle counter */
756: cur_inst_len = 1;
1.1.1.6 root 757: dsp_core.instr_cycle = 2;
1.1 root 758:
1.1.1.6 root 759: /* Disasm current instruction ? (trace mode only) */
760: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
761: /* Call dsp56k_disasm only when DSP is called in trace mode */
762: if (isDsp_in_disasm_mode == false) {
763: disasm_return = dsp56k_disasm(DSP_TRACE_MODE);
764:
765: if (disasm_return != 0 && LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG)) {
766: /* DSP regs trace enabled only if DSP DISASM is enabled */
767: dsp56k_disasm_reg_save();
768: }
769: }
770: }
771:
1.1.1.4 root 772: if (cur_inst < 0x100000) {
773: value = (cur_inst >> 11) & (BITMASK(6) << 3);
774: value += (cur_inst >> 5) & BITMASK(3);
1.1 root 775: opcodes8h[value]();
776: } else {
1.1.1.6 root 777: /* Do parallel move read */
778: opcodes_parmove[(cur_inst>>20) & BITMASK(4)]();
779: }
780:
1.1.1.7 root 781: /* Add the waitstate due to external memory access */
782: if (nb_access_to_extMemory > 1)
783: dsp_core.instr_cycle += nb_access_to_extMemory - 1;
784:
1.1.1.6 root 785: /* Disasm current instruction ? (trace mode only) */
786: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
787: /* Display only when DSP is called in trace mode */
788: if (isDsp_in_disasm_mode == false) {
789: if (disasm_return != 0) {
790: fprintf(stderr, "%s", dsp56k_getInstructionText());
791:
792: /* DSP regs trace enabled only if DSP DISASM is enabled */
793: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG))
794: dsp56k_disasm_reg_compare();
795:
796: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM)) {
797: /* 1 memory change to display ? */
798: if (disasm_memory_ptr == 1)
799: fprintf(stderr, "\t%s\n", str_disasm_memory[0]);
800: /* 2 memory changes to display ? */
801: else if (disasm_memory_ptr == 2) {
802: fprintf(stderr, "\t%s\n", str_disasm_memory[0]);
803: fprintf(stderr, "\t%s\n", str_disasm_memory[1]);
804: }
805: }
806: }
807: }
1.1 root 808: }
809:
1.1.1.4 root 810: /* Process the PC */
811: dsp_postexecute_update_pc();
1.1 root 812:
1.1.1.4 root 813: /* Process Interrupts */
1.1 root 814: dsp_postexecute_interrupts();
815:
1.1.1.4 root 816: #if DSP_COUNT_IPS
817: ++num_inst;
818: if ((num_inst & 63) == 0) {
819: /* Evaluate time after <N> instructions have been executed to avoid asking too frequently */
820: Uint32 cur_time = SDL_GetTicks();
821: if (cur_time-start_time>1000) {
822: fprintf(stderr, "Dsp: %d i/s\n", (num_inst*1000)/(cur_time-start_time));
823: start_time=cur_time;
824: num_inst=0;
825: }
826: }
827: #endif
1.1 root 828: }
829:
830: /**********************************
831: * Update the PC
832: **********************************/
833:
834: static void dsp_postexecute_update_pc(void)
835: {
836: /* When running a REP, PC must stay on the current instruction */
1.1.1.6 root 837: if (dsp_core.loop_rep) {
1.1 root 838: /* Is PC on the instruction to repeat ? */
1.1.1.6 root 839: if (dsp_core.pc_on_rep==0) {
840: --dsp_core.registers[DSP_REG_LC];
841: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1 root 842:
1.1.1.6 root 843: if (dsp_core.registers[DSP_REG_LC] > 0) {
1.1.1.7 root 844: cur_inst_len = 0; /* Stay on this instruction */
1.1 root 845: } else {
1.1.1.6 root 846: dsp_core.loop_rep = 0;
847: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[DSP_REG_LCSAVE];
1.1 root 848: }
849: } else {
850: /* Init LC at right value */
1.1.1.6 root 851: if (dsp_core.registers[DSP_REG_LC] == 0) {
852: dsp_core.registers[DSP_REG_LC] = 0x010000;
1.1 root 853: }
1.1.1.6 root 854: dsp_core.pc_on_rep = 0;
1.1 root 855: }
856: }
857:
858: /* Normal execution, go to next instruction */
1.1.1.6 root 859: dsp_core.pc += cur_inst_len;
1.1 root 860:
861: /* When running a DO loop, we test the end of loop with the */
862: /* updated PC, pointing to last instruction of the loop */
1.1.1.6 root 863: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_LF)) {
1.1 root 864:
865: /* Did we execute the last instruction in loop ? */
1.1.1.7 root 866: if (dsp_core.pc == dsp_core.registers[DSP_REG_LA] + 1) {
1.1.1.6 root 867: --dsp_core.registers[DSP_REG_LC];
868: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1 root 869:
1.1.1.7 root 870: if (dsp_core.registers[DSP_REG_LC] == 0) {
1.1 root 871: /* end of loop */
1.1.1.4 root 872: Uint32 saved_pc, saved_sr;
873:
874: dsp_stack_pop(&saved_pc, &saved_sr);
1.1.1.6 root 875: dsp_core.registers[DSP_REG_SR] &= 0x7f;
876: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
877: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
1.1 root 878: } else {
879: /* Loop one more time */
1.1.1.6 root 880: dsp_core.pc = dsp_core.registers[DSP_REG_SSH];
1.1 root 881: }
882: }
883: }
884: }
885:
886: /**********************************
887: * Interrupts
888: **********************************/
889:
1.1.1.5 root 890: /* Post a new interrupt to the interrupt table */
891: void dsp_add_interrupt(Uint16 inter)
892: {
893: /* detect if this interrupt is used or not */
1.1.1.6 root 894: if (dsp_core.interrupt_ipl[inter] == -1)
1.1.1.5 root 895: return;
896:
897: /* add this interrupt to the pending interrupts table */
1.1.1.6 root 898: if (dsp_core.interrupt_isPending[inter] == 0) {
899: dsp_core.interrupt_isPending[inter] = 1;
900: dsp_core.interrupt_counter ++;
1.1.1.5 root 901: }
902: }
903:
904: static void dsp_setInterruptIPL(Uint32 value)
905: {
906: Uint32 ipl_ssi, ipl_hi, i;
907:
908: ipl_ssi = ((value >> 12) & 3) - 1;
909: ipl_hi = ((value >> 10) & 3) - 1;
910:
911: /* set IPL_HI */
1.1.1.7 root 912: for (i=5; i<8; i++) {
1.1.1.6 root 913: dsp_core.interrupt_ipl[i] = ipl_hi;
1.1.1.5 root 914: }
915:
916: /* set IPL_SSI */
1.1.1.7 root 917: for (i=8; i<12; i++) {
1.1.1.6 root 918: dsp_core.interrupt_ipl[i] = ipl_ssi;
1.1.1.5 root 919: }
920: }
921:
1.1 root 922: static void dsp_postexecute_interrupts(void)
923: {
1.1.1.5 root 924: Uint32 index, instr, i;
925: Sint32 ipl_to_raise, ipl_sr;
1.1.1.4 root 926:
927: /* REP is not interruptible */
1.1.1.6 root 928: if (dsp_core.loop_rep) {
1.1.1.4 root 929: return;
930: }
931:
932: /* A fast interrupt can not be interrupted. */
1.1.1.6 root 933: if (dsp_core.interrupt_state == DSP_INTERRUPT_DISABLED) {
1.1.1.5 root 934:
1.1.1.6 root 935: switch (dsp_core.interrupt_pipeline_count) {
1.1.1.5 root 936: case 5:
1.1.1.6 root 937: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 938: return;
939: case 4:
940: /* Prefetch interrupt instruction 1 */
1.1.1.6 root 941: dsp_core.interrupt_save_pc = dsp_core.pc;
942: dsp_core.pc = dsp_core.interrupt_instr_fetch;
1.1.1.5 root 943:
944: /* is it a LONG interrupt ? */
1.1.1.6 root 945: instr = read_memory_p(dsp_core.interrupt_instr_fetch);
1.1.1.5 root 946: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1.1.1.6 root 947: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
948: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
949: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1.1.1.5 root 950: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
951: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1.1.1.6 root 952: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1.1.1.5 root 953: }
1.1.1.6 root 954: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 955: return;
956: case 3:
957: /* Prefetch interrupt instruction 2 */
1.1.1.6 root 958: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+1) {
959: instr = read_memory_p(dsp_core.pc);
1.1.1.5 root 960: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1.1.1.6 root 961: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
962: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
963: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1.1.1.5 root 964: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
965: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1.1.1.6 root 966: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1.1.1.5 root 967: }
968: }
1.1.1.6 root 969: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 970: return;
971: case 2:
972: /* 1 instruction executed after interrupt */
973: /* before re enable interrupts */
974: /* Was it a FAST interrupt ? */
1.1.1.6 root 975: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+2) {
976: dsp_core.pc = dsp_core.interrupt_save_pc;
1.1.1.5 root 977: }
1.1.1.6 root 978: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 979: return;
980: case 1:
981: /* Last instruction executed after interrupt */
982: /* before re enable interrupts */
1.1.1.6 root 983: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 984: return;
985: case 0:
986: /* Re enable interrupts */
1.1.1.6 root 987: /* All 6 instruction are done, Interrupts can be enabled again */
988: dsp_core.interrupt_save_pc = -1;
989: dsp_core.interrupt_instr_fetch = -1;
990: dsp_core.interrupt_state = DSP_INTERRUPT_NONE;
991: break;
1.1.1.4 root 992: }
993: }
1.1 root 994:
1.1.1.4 root 995: /* Trace Interrupt ? */
1.1.1.6 root 996: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_T)) {
1.1.1.5 root 997: dsp_add_interrupt(DSP_INTER_TRACE);
1.1.1.4 root 998: }
999:
1000: /* No interrupt to execute */
1.1.1.6 root 1001: if (dsp_core.interrupt_counter == 0) {
1.1.1.4 root 1002: return;
1.1 root 1003: }
1004:
1.1.1.5 root 1005: /* search for an interrupt */
1.1.1.6 root 1006: ipl_sr = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_I0) & BITMASK(2);
1.1.1.5 root 1007: index = 0xffff;
1008: ipl_to_raise = -1;
1009:
1010: /* Arbitrate between all pending interrupts */
1011: for (i=0; i<12; i++) {
1.1.1.6 root 1012: if (dsp_core.interrupt_isPending[i] == 1) {
1.1.1.5 root 1013:
1014: /* level 3 interrupt ? */
1.1.1.6 root 1015: if (dsp_core.interrupt_ipl[i] == 3) {
1.1.1.5 root 1016: index = i;
1017: break;
1018: }
1.1 root 1019:
1.1.1.5 root 1020: /* level 0, 1 ,2 interrupt ? */
1021: /* if interrupt is masked in SR, don't process it */
1.1.1.6 root 1022: if (dsp_core.interrupt_ipl[i] < ipl_sr)
1.1.1.5 root 1023: continue;
1.1 root 1024:
1.1.1.5 root 1025: /* if interrupt is lower or equal than current arbitrated interrupt */
1.1.1.6 root 1026: if (dsp_core.interrupt_ipl[i] <= ipl_to_raise)
1.1.1.5 root 1027: continue;
1028:
1029: /* save current arbitrated interrupt */
1030: index = i;
1.1.1.6 root 1031: ipl_to_raise = dsp_core.interrupt_ipl[i];
1.1 root 1032: }
1033: }
1.1.1.4 root 1034:
1.1.1.5 root 1035: /* If there's no interrupt to process, return */
1036: if (index == 0xffff) {
1.1.1.4 root 1037: return;
1038: }
1039:
1.1.1.5 root 1040: /* remove this interrupt from the pending interrupts table */
1.1.1.6 root 1041: dsp_core.interrupt_isPending[index] = 0;
1042: dsp_core.interrupt_counter --;
1.1.1.5 root 1043:
1044: /* process arbritrated interrupt */
1.1.1.6 root 1045: ipl_to_raise = dsp_core.interrupt_ipl[index] + 1;
1.1.1.5 root 1046: if (ipl_to_raise > 3) {
1047: ipl_to_raise = 3;
1048: }
1049:
1.1.1.6 root 1050: dsp_core.interrupt_instr_fetch = dsp_interrupt[index].vectorAddr;
1051: dsp_core.interrupt_pipeline_count = 5;
1052: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1053: dsp_core.interrupt_IplToRaise = ipl_to_raise;
1054:
1055: LOG_TRACE(TRACE_DSP_INTERRUPT, "Dsp interrupt: %s\n", dsp_interrupt[index].name);
1.1.1.5 root 1056:
1057: /* SSI receive data with exception ? */
1.1.1.6 root 1058: if (dsp_core.interrupt_instr_fetch == 0xe) {
1059: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_ROE);
1.1.1.4 root 1060: }
1061:
1.1.1.5 root 1062: /* SSI transmit data with exception ? */
1.1.1.6 root 1063: else if (dsp_core.interrupt_instr_fetch == 0x12) {
1064: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_TUE);
1.1.1.4 root 1065: }
1066:
1067: /* host command ? */
1.1.1.6 root 1068: else if (dsp_core.interrupt_instr_fetch == 0xff) {
1.1.1.4 root 1069: /* Clear HC and HCP interrupt */
1.1.1.6 root 1070: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] &= 0xff - (1<<DSP_HOST_HSR_HCP);
1071: dsp_core.hostport[CPU_HOST_CVR] &= 0xff - (1<<CPU_HOST_CVR_HC);
1.1.1.4 root 1072:
1.1.1.6 root 1073: dsp_core.interrupt_instr_fetch = dsp_core.hostport[CPU_HOST_CVR] & BITMASK(5);
1074: dsp_core.interrupt_instr_fetch *= 2;
1.1.1.4 root 1075: }
1.1 root 1076: }
1077:
1078: /**********************************
1079: * Set/clear ccr bits
1080: **********************************/
1081:
1082: /* reg0 has bits 55..48 */
1083: /* reg1 has bits 47..24 */
1084: /* reg2 has bits 23..0 */
1085:
1.1.1.6 root 1086: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2)
1087: {
1088: Uint32 scaling, value_e, value_u;
1.1.1.4 root 1089:
1.1.1.6 root 1090: /* Initialize SR register */
1091: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E) | (1<<DSP_SR_U) | (1<<DSP_SR_N) | (1<<DSP_SR_Z));
1.1.1.4 root 1092:
1.1.1.6 root 1093: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
1.1 root 1094: switch(scaling) {
1095: case 0:
1.1.1.6 root 1096: /* Extension Bit (E) */
1097: value_e = (reg0<<1) + (reg1>>23);
1098: if ((value_e != 0) && (value_e != BITMASK(9)))
1099: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1100:
1101: /* Unnormalized bit (U) */
1102: if ((reg1 & 0xc00000) == 0 || (reg1 & 0xc00000) == 0xc00000)
1103: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1104: break;
1105: case 1:
1.1.1.6 root 1106: /* Extension Bit (E) */
1107: if ((reg0 != 0) && (reg0 != BITMASK(8)))
1108: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1109:
1110: /* Unnormalized bit (U) */
1111: value_u = ((reg0<<1) + (reg1>>23)) & 3;
1112: if (value_u == 0 || value_u == 3)
1113: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1114: break;
1115: case 2:
1.1.1.6 root 1116: /* Extension Bit (E) */
1117: value_e = (reg0<<2) + (reg1>>22);
1118: if ((value_e != 0) && (value_e != BITMASK(10)))
1119: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1120:
1121: /* Unnormalized bit (U) */
1122: if ((reg1 & 0x600000) == 0 || (reg1 & 0x600000) == 0x600000)
1123: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1124: break;
1125: default:
1126: return;
1127: break;
1128: }
1129:
1.1.1.6 root 1130: /* Zero Flag (Z) */
1131: if ((reg1 == 0) && (reg2 == 0) && (reg0 == 0))
1132: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_Z;
1.1.1.4 root 1133:
1.1.1.6 root 1134: /* Negative Flag (N) */
1135: dsp_core.registers[DSP_REG_SR] |= (reg0>>4) & 0x8;
1.1 root 1136: }
1137:
1138: /**********************************
1139: * Read/Write memory functions
1140: **********************************/
1141:
1.1.1.2 root 1142: static Uint32 read_memory_disasm(int space, Uint16 address)
1.1 root 1143: {
1.1.1.4 root 1144: /* Internal RAM ? */
1145: if (address<0x100) {
1.1.1.6 root 1146: return dsp_core.ramint[space][address] & BITMASK(24);
1.1.1.4 root 1147: }
1.1 root 1148:
1.1.1.4 root 1149: if (space==DSP_SPACE_P) {
1150: return read_memory_p(address);
1.1 root 1151: }
1152:
1.1.1.4 root 1153: /* Internal ROM? */
1.1.1.6 root 1154: if ((dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) &&
1.1.1.4 root 1155: (address<0x200)) {
1.1.1.6 root 1156: return dsp_core.rom[space][address] & BITMASK(24);
1.1.1.4 root 1157: }
1158:
1159: /* Peripheral address ? */
1160: if (address >= 0xffc0) {
1.1.1.6 root 1161: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_HOST_HTX)) {
1162: return dsp_core.dsp_host_htx;
1.1.1.4 root 1163: }
1164: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_SSI_TX)) {
1.1.1.6 root 1165: return dsp_core.ssi.transmit_value;
1.1.1.4 root 1166: }
1.1.1.6 root 1167: return dsp_core.periph[space][address-0xffc0] & BITMASK(24);
1.1.1.4 root 1168: }
1169:
1170: /* Falcon: External RAM, map X to upper 16K of matching space in Y,P */
1171: address &= (DSP_RAMSIZE>>1) - 1;
1172: if (space == DSP_SPACE_X) {
1173: address += DSP_RAMSIZE>>1;
1174: }
1175:
1176: /* Falcon: External RAM, finally map X,Y to P */
1.1.1.6 root 1177: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1.1 root 1178: }
1179:
1.1.1.4 root 1180: static inline Uint32 read_memory_p(Uint16 address)
1181: {
1182: /* Internal RAM ? */
1.1.1.7 root 1183: if (address < 0x200) {
1.1.1.6 root 1184: return dsp_core.ramint[DSP_SPACE_P][address] & BITMASK(24);
1.1.1.4 root 1185: }
1186:
1.1.1.7 root 1187: /* Access to the external memory */
1188: nb_access_to_extMemory ++;
1189:
1.1.1.4 root 1190: /* External RAM, mask address to available ram size */
1.1.1.6 root 1191: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1.1.1.4 root 1192: }
1193:
1.1.1.2 root 1194: static Uint32 read_memory(int space, Uint16 address)
1.1 root 1195: {
1.1.1.4 root 1196: Uint32 value;
1.1 root 1197:
1.1.1.4 root 1198: /* Internal RAM ? */
1199: if (address < 0x100) {
1.1.1.6 root 1200: return dsp_core.ramint[space][address] & BITMASK(24);
1.1.1.4 root 1201: }
1.1 root 1202:
1.1.1.4 root 1203: if (space == DSP_SPACE_P) {
1204: return read_memory_p(address);
1205: }
1206:
1207: /* Internal ROM ? */
1208: if (address < 0x200) {
1.1.1.6 root 1209: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1210: return dsp_core.rom[space][address] & BITMASK(24);
1.1.1.4 root 1211: }
1212: }
1213:
1214: /* Peripheral address ? */
1215: if (address >= 0xffc0) {
1.1.1.6 root 1216: value = dsp_core.periph[space][address-0xffc0] & BITMASK(24);
1.1.1.4 root 1217: if (space == DSP_SPACE_X) {
1218: if (address == 0xffc0+DSP_HOST_HRX) {
1.1.1.6 root 1219: value = dsp_core.dsp_host_rtx;
1220: dsp_core_hostport_dspread();
1.1.1.4 root 1221: }
1222: else if (address == 0xffc0+DSP_SSI_RX) {
1.1.1.6 root 1223: value = dsp_core_ssi_readRX();
1.1 root 1224: }
1.1.1.4 root 1225: }
1226: return value;
1.1 root 1227: }
1228:
1.1.1.7 root 1229: /* Access to the external memory */
1230: nb_access_to_extMemory ++;
1.1.1.4 root 1231:
1232: /* Falcon: External RAM, map X to upper 16K of matching space in Y,P */
1233: address &= (DSP_RAMSIZE>>1) - 1;
1234:
1235: if (space == DSP_SPACE_X) {
1236: address += DSP_RAMSIZE>>1;
1237: }
1238:
1239: /* Falcon: External RAM, finally map X,Y to P */
1.1.1.6 root 1240: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1241: }
1242:
1243: static inline void write_memory(int space, Uint16 address, Uint32 value)
1244: {
1.1.1.7 root 1245: if (unlikely(LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM)))
1.1.1.6 root 1246: write_memory_disasm(space, address, value);
1247: else
1248: write_memory_raw(space, address, value);
1.1 root 1249: }
1250:
1.1.1.4 root 1251: static void write_memory_raw(int space, Uint16 address, Uint32 value)
1.1 root 1252: {
1253: value &= BITMASK(24);
1254:
1.1.1.4 root 1255: /* Peripheral address ? */
1256: if (address >= 0xffc0) {
1257: if (space == DSP_SPACE_X) {
1258: switch(address-0xffc0) {
1259: case DSP_HOST_HTX:
1.1.1.6 root 1260: dsp_core.dsp_host_htx = value;
1261: dsp_core_hostport_dspwrite();
1.1.1.4 root 1262: break;
1263: case DSP_HOST_HCR:
1.1.1.6 root 1264: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] = value;
1.1.1.4 root 1265: /* Set HF3 and HF2 accordingly on the host side */
1.1.1.6 root 1266: dsp_core.hostport[CPU_HOST_ISR] &=
1.1.1.4 root 1267: BITMASK(8)-((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1.1.1.6 root 1268: dsp_core.hostport[CPU_HOST_ISR] |=
1269: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] & ((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1.1.1.4 root 1270: break;
1271: case DSP_HOST_HSR:
1272: /* Read only */
1273: break;
1274: case DSP_SSI_CRA:
1275: case DSP_SSI_CRB:
1.1.1.6 root 1276: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1277: dsp_core_ssi_configure(address-0xffc0, value);
1.1.1.4 root 1278: break;
1279: case DSP_SSI_TSR:
1.1.1.6 root 1280: dsp_core_ssi_writeTSR();
1.1.1.4 root 1281: break;
1282: case DSP_SSI_TX:
1.1.1.6 root 1283: dsp_core_ssi_writeTX(value);
1.1.1.4 root 1284: break;
1.1.1.5 root 1285: case DSP_IPR:
1.1.1.6 root 1286: dsp_core.periph[DSP_SPACE_X][DSP_IPR] = value;
1.1.1.5 root 1287: dsp_setInterruptIPL(value);
1288: break;
1289: case DSP_PCD:
1.1.1.6 root 1290: dsp_core.periph[DSP_SPACE_X][DSP_PCD] = value;
1291: dsp_core_setPortCDataRegister(value);
1.1.1.5 root 1292: break;
1.1.1.4 root 1293: default:
1.1.1.6 root 1294: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1.1.1.4 root 1295: break;
1.1 root 1296: }
1.1.1.4 root 1297: return;
1298: }
1299: else if (space == DSP_SPACE_Y) {
1.1.1.6 root 1300: dsp_core.periph[DSP_SPACE_Y][address-0xffc0] = value;
1.1.1.4 root 1301: return;
1302: }
1303: }
1304:
1305: /* Internal RAM ? */
1306: if (address < 0x100) {
1.1.1.6 root 1307: dsp_core.ramint[space][address] = value;
1.1.1.4 root 1308: return;
1309: }
1.1.1.2 root 1310:
1.1.1.4 root 1311: /* Internal ROM ? */
1312: if (address < 0x200) {
1313: if (space != DSP_SPACE_P) {
1.1.1.6 root 1314: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1.1.1.2 root 1315: /* Can not write to ROM space */
1.1 root 1316: return;
1317: }
1.1.1.4 root 1318: }
1319: else {
1320: /* Space P RAM */
1.1.1.6 root 1321: dsp_core.ramint[DSP_SPACE_P][address] = value;
1.1.1.4 root 1322: return;
1323: }
1.1 root 1324: }
1325:
1.1.1.7 root 1326: /* Access to the external memory */
1327: nb_access_to_extMemory ++;
1.1.1.4 root 1328:
1329: /* Falcon: External RAM, map X to upper 16K of matching space in Y,P */
1330: if (space != DSP_SPACE_P) {
1331: address &= (DSP_RAMSIZE>>1) - 1;
1332: }
1333:
1334: if (space == DSP_SPACE_X) {
1335: address += DSP_RAMSIZE>>1;
1336: }
1337:
1338: /* Falcon: External RAM, map X,Y to P */
1.1.1.6 root 1339: dsp_core.ramext[address & (DSP_RAMSIZE-1)] = value;
1.1.1.2 root 1340: }
1341:
1.1.1.4 root 1342: static void write_memory_disasm(int space, Uint16 address, Uint32 value)
1.1.1.2 root 1343: {
1.1.1.4 root 1344: Uint32 oldvalue, curvalue;
1345: Uint8 space_c = 'p';
1346:
1.1.1.2 root 1347: value &= BITMASK(24);
1.1.1.6 root 1348: oldvalue = read_memory_disasm(space, address);
1.1.1.2 root 1349:
1350: write_memory_raw(space,address,value);
1351:
1.1 root 1352: switch(space) {
1353: case DSP_SPACE_X:
1.1.1.4 root 1354: space_c = 'x';
1.1 root 1355: break;
1356: case DSP_SPACE_Y:
1.1.1.4 root 1357: space_c = 'y';
1358: break;
1359: default:
1.1 root 1360: break;
1361: }
1.1.1.4 root 1362:
1.1.1.6 root 1363: curvalue = read_memory_disasm(space, address);
1.1.1.5 root 1364: sprintf(str_disasm_memory[disasm_memory_ptr],"Mem: %c:0x%04x 0x%06x -> 0x%06x", space_c, address, oldvalue, curvalue);
1365: disasm_memory_ptr ++;
1.1 root 1366: }
1367:
1.1.1.4 root 1368: static void dsp_write_reg(Uint32 numreg, Uint32 value)
1369: {
1.1.1.5 root 1370: Uint32 stack_error;
1.1.1.4 root 1371:
1.1.1.7 root 1372: switch (numreg) {
1373: case DSP_REG_A:
1374: dsp_core.registers[DSP_REG_A0] = 0;
1375: dsp_core.registers[DSP_REG_A1] = value;
1376: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
1377: break;
1378: case DSP_REG_B:
1379: dsp_core.registers[DSP_REG_B0] = 0;
1380: dsp_core.registers[DSP_REG_B1] = value;
1381: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
1382: break;
1383: case DSP_REG_OMR:
1384: dsp_core.registers[DSP_REG_OMR] = value & 0xc7;
1385: break;
1386: case DSP_REG_SR:
1387: dsp_core.registers[DSP_REG_SR] = value & 0xaf7f;
1388: break;
1389: case DSP_REG_SP:
1.1.1.8 ! root 1390: stack_error = dsp_core.registers[DSP_REG_SP] & (3<<DSP_SP_SE);
! 1391: if ((stack_error==0) && (value & (3<<DSP_SP_SE))) {
! 1392: /* Stack underflow or overflow detected, raise interrupt */
1.1.1.7 root 1393: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1394: if (!isDsp_in_disasm_mode)
1.1.1.8 ! root 1395: fprintf(stderr,"Dsp: Stack Overflow or Underflow\n");
! 1396: dsp_core.registers[DSP_REG_SP] = value & (3<<DSP_SP_SE);
1.1.1.7 root 1397: }
1.1.1.8 ! root 1398: else
! 1399: dsp_core.registers[DSP_REG_SP] = value & BITMASK(6);
1.1.1.7 root 1400: dsp_compute_ssh_ssl();
1401: break;
1402: case DSP_REG_SSH:
1403: dsp_stack_push(value, 0, 1);
1404: break;
1405: case DSP_REG_SSL:
1406: numreg = dsp_core.registers[DSP_REG_SP] & BITMASK(4);
1407: if (numreg == 0) {
1408: value = 0;
1409: }
1410: dsp_core.stack[1][numreg] = value & BITMASK(16);
1411: dsp_core.registers[DSP_REG_SSL] = value & BITMASK(16);
1412: break;
1413: default:
1414: dsp_core.registers[numreg] = value;
1415: dsp_core.registers[numreg] &= BITMASK(registers_mask[numreg]);
1416: break;
1.1.1.4 root 1417: }
1418: }
1419:
1.1 root 1420: /**********************************
1421: * Stack push/pop
1422: **********************************/
1423:
1.1.1.4 root 1424: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly)
1.1 root 1425: {
1.1.1.4 root 1426: Uint32 stack_error, underflow, stack;
1427:
1.1.1.6 root 1428: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1429: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1430: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) + 1;
1.1.1.4 root 1431:
1432:
1433: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1.1 root 1434: /* Stack full, raise interrupt */
1.1.1.5 root 1435: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.6 root 1436: if (!isDsp_in_disasm_mode)
1437: fprintf(stderr,"Dsp: Stack Overflow\n");
1.1 root 1438: }
1.1.1.4 root 1439:
1.1.1.6 root 1440: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1.1.1.4 root 1441: stack &= BITMASK(4);
1.1 root 1442:
1.1.1.4 root 1443: if (stack) {
1444: /* SSH part */
1.1.1.6 root 1445: dsp_core.stack[0][stack] = curpc & BITMASK(16);
1.1.1.4 root 1446: /* SSL part, if instruction is not like "MOVEC xx, SSH" */
1447: if (sshOnly == 0) {
1.1.1.6 root 1448: dsp_core.stack[1][stack] = cursr & BITMASK(16);
1.1.1.4 root 1449: }
1450: } else {
1.1.1.6 root 1451: dsp_core.stack[0][0] = 0;
1452: dsp_core.stack[1][0] = 0;
1.1.1.4 root 1453: }
1.1 root 1454:
1.1.1.4 root 1455: /* Update SSH and SSL registers */
1.1.1.6 root 1456: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1457: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1 root 1458: }
1459:
1.1.1.2 root 1460: static void dsp_stack_pop(Uint32 *newpc, Uint32 *newsr)
1.1 root 1461: {
1.1.1.4 root 1462: Uint32 stack_error, underflow, stack;
1463:
1.1.1.6 root 1464: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1465: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1466: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) - 1;
1.1.1.4 root 1467:
1468: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1469: /* Stack empty*/
1.1.1.5 root 1470: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.6 root 1471: if (!isDsp_in_disasm_mode)
1472: fprintf(stderr,"Dsp: Stack underflow\n");
1.1 root 1473: }
1474:
1.1.1.6 root 1475: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1.1.1.4 root 1476: stack &= BITMASK(4);
1.1.1.6 root 1477: *newpc = dsp_core.registers[DSP_REG_SSH];
1478: *newsr = dsp_core.registers[DSP_REG_SSL];
1.1.1.4 root 1479:
1.1.1.6 root 1480: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1481: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1.1.4 root 1482: }
1483:
1484: static void dsp_compute_ssh_ssl(void)
1485: {
1486: Uint32 stack;
1.1 root 1487:
1.1.1.6 root 1488: stack = dsp_core.registers[DSP_REG_SP];
1.1.1.4 root 1489: stack &= BITMASK(4);
1.1.1.6 root 1490: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1491: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1 root 1492: }
1493:
1494: /**********************************
1495: * Effective address calculation
1496: **********************************/
1497:
1.1.1.2 root 1498: static void dsp_update_rn(Uint32 numreg, Sint16 modifier)
1.1 root 1499: {
1.1.1.2 root 1500: Sint16 value;
1501: Uint16 m_reg;
1.1 root 1502:
1.1.1.6 root 1503: m_reg = (Uint16) dsp_core.registers[DSP_REG_M0+numreg];
1.1.1.7 root 1504: if (m_reg == 65535) {
1505: /* Linear addressing mode */
1506: value = (Sint16) dsp_core.registers[DSP_REG_R0+numreg];
1507: value += modifier;
1508: dsp_core.registers[DSP_REG_R0+numreg] = ((Uint32) value) & BITMASK(16);
1509: } else if (m_reg == 0) {
1.1 root 1510: /* Bit reversed carry update */
1511: dsp_update_rn_bitreverse(numreg);
1.1.1.4 root 1512: } else if (m_reg<=32767) {
1.1 root 1513: /* Modulo update */
1514: dsp_update_rn_modulo(numreg, modifier);
1515: } else {
1516: /* Undefined */
1517: }
1518: }
1519:
1.1.1.2 root 1520: static void dsp_update_rn_bitreverse(Uint32 numreg)
1.1 root 1521: {
1522: int revbits, i;
1.1.1.2 root 1523: Uint32 value, r_reg;
1.1 root 1524:
1525: /* Check how many bits to reverse */
1.1.1.6 root 1526: value = dsp_core.registers[DSP_REG_N0+numreg];
1.1 root 1527: for (revbits=0;revbits<16;revbits++) {
1528: if (value & (1<<revbits)) {
1529: break;
1530: }
1531: }
1532: revbits++;
1533:
1534: /* Reverse Rn bits */
1.1.1.6 root 1535: r_reg = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1536: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1537: for (i=0;i<revbits;i++) {
1538: if (r_reg & (1<<i)) {
1539: value |= 1<<(revbits-i-1);
1540: }
1541: }
1542:
1543: /* Increment */
1544: value++;
1545: value &= BITMASK(revbits);
1546:
1547: /* Reverse Rn bits */
1548: r_reg &= (BITMASK(16)-BITMASK(revbits));
1549: r_reg |= value;
1550:
1551: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1552: for (i=0;i<revbits;i++) {
1553: if (r_reg & (1<<i)) {
1554: value |= 1<<(revbits-i-1);
1555: }
1556: }
1557:
1.1.1.6 root 1558: dsp_core.registers[DSP_REG_R0+numreg] = value;
1.1 root 1559: }
1560:
1.1.1.2 root 1561: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier)
1.1 root 1562: {
1.1.1.2 root 1563: Uint16 bufsize, modulo, lobound, hibound, bufmask;
1.1.1.4 root 1564: Sint16 r_reg, orig_modifier=modifier;
1.1 root 1565:
1.1.1.6 root 1566: modulo = dsp_core.registers[DSP_REG_M0+numreg]+1;
1.1 root 1567: bufsize = 1;
1.1.1.2 root 1568: bufmask = BITMASK(16);
1.1 root 1569: while (bufsize < modulo) {
1570: bufsize <<= 1;
1.1.1.2 root 1571: bufmask <<= 1;
1.1 root 1572: }
1573:
1.1.1.6 root 1574: lobound = dsp_core.registers[DSP_REG_R0+numreg] & bufmask;
1.1.1.2 root 1575: hibound = lobound + modulo - 1;
1.1 root 1576:
1.1.1.6 root 1577: r_reg = (Sint16) dsp_core.registers[DSP_REG_R0+numreg];
1.1.1.4 root 1578:
1579: if (orig_modifier>modulo) {
1580: while (modifier>bufsize) {
1581: r_reg += bufsize;
1582: modifier -= bufsize;
1583: }
1584: while (modifier<-bufsize) {
1585: r_reg -= bufsize;
1586: modifier += bufsize;
1587: }
1.1.1.2 root 1588: }
1.1.1.4 root 1589:
1.1 root 1590: r_reg += modifier;
1.1.1.4 root 1591:
1592: if (orig_modifier!=modulo) {
1593: if (r_reg>hibound) {
1594: r_reg -= modulo;
1595: } else if (r_reg<lobound) {
1596: r_reg += modulo;
1597: }
1.1 root 1598: }
1599:
1.1.1.6 root 1600: dsp_core.registers[DSP_REG_R0+numreg] = ((Uint32) r_reg) & BITMASK(16);
1.1 root 1601: }
1602:
1.1.1.2 root 1603: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr)
1.1 root 1604: {
1.1.1.2 root 1605: Uint32 value, numreg, curreg;
1.1 root 1606:
1607: value = (ea_mode >> 3) & BITMASK(3);
1608: numreg = ea_mode & BITMASK(3);
1609: switch (value) {
1610: case 0:
1611: /* (Rx)-Nx */
1.1.1.6 root 1612: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1613: dsp_update_rn(numreg, -dsp_core.registers[DSP_REG_N0+numreg]);
1.1 root 1614: break;
1615: case 1:
1616: /* (Rx)+Nx */
1.1.1.6 root 1617: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1618: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1.1 root 1619: break;
1620: case 2:
1621: /* (Rx)- */
1.1.1.6 root 1622: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1623: dsp_update_rn(numreg, -1);
1624: break;
1625: case 3:
1626: /* (Rx)+ */
1.1.1.6 root 1627: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1628: dsp_update_rn(numreg, +1);
1629: break;
1630: case 4:
1631: /* (Rx) */
1.1.1.6 root 1632: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1633: break;
1634: case 5:
1635: /* (Rx+Nx) */
1.1.1.6 root 1636: dsp_core.instr_cycle += 2;
1637: curreg = dsp_core.registers[DSP_REG_R0+numreg];
1638: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1639: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1640: dsp_core.registers[DSP_REG_R0+numreg] = curreg;
1.1 root 1641: break;
1642: case 6:
1643: /* aa */
1.1.1.6 root 1644: dsp_core.instr_cycle += 2;
1645: *dst_addr = read_memory_p(dsp_core.pc+1);
1.1 root 1646: cur_inst_len++;
1647: if (numreg != 0) {
1648: return 1; /* immediate value */
1649: }
1650: break;
1651: case 7:
1652: /* -(Rx) */
1.1.1.6 root 1653: dsp_core.instr_cycle += 2;
1.1 root 1654: dsp_update_rn(numreg, -1);
1.1.1.6 root 1655: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1656: break;
1657: }
1658: /* address */
1659: return 0;
1660: }
1661:
1662: /**********************************
1663: * Condition code test
1664: **********************************/
1665:
1.1.1.2 root 1666: static int dsp_calc_cc(Uint32 cc_code)
1.1 root 1667: {
1.1.1.4 root 1668: Uint16 value1, value2, value3;
1.1 root 1669:
1.1.1.4 root 1670: switch (cc_code) {
1671: case 0: /* CC (HS) */
1.1.1.6 root 1672: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1.1.1.4 root 1673: return (value1==0);
1674: case 1: /* GE */
1.1.1.6 root 1675: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1676: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1.1.1.4 root 1677: return ((value1 ^ value2) == 0);
1678: case 2: /* NE */
1.1.1.6 root 1679: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_Z);
1.1.1.4 root 1680: return (value1==0);
1681: case 3: /* PL */
1.1.1.6 root 1682: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_N);
1.1.1.4 root 1683: return (value1==0);
1684: case 4: /* NN */
1.1.1.6 root 1685: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1686: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1687: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1.1.1.4 root 1688: return ((value1 | (value2 & value3)) == 0);
1689: case 5: /* EC */
1.1.1.6 root 1690: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_E);
1.1.1.4 root 1691: return (value1==0);
1692: case 6: /* LC */
1.1.1.6 root 1693: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_L);
1.1.1.4 root 1694: return (value1==0);
1695: case 7: /* GT */
1.1.1.6 root 1696: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1697: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1698: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1699: return ((value3 | (value1 ^ value2)) == 0);
1700: case 8: /* CS (LO) */
1.1.1.6 root 1701: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1.1.1.4 root 1702: return (value1==1);
1703: case 9: /* LT */
1.1.1.6 root 1704: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1705: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1.1.1.4 root 1706: return ((value1 ^ value2) == 1);
1707: case 10: /* EQ */
1.1.1.6 root 1708: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1709: return (value1==1);
1710: case 11: /* MI */
1.1.1.6 root 1711: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1.1.1.4 root 1712: return (value1==1);
1713: case 12: /* NR */
1.1.1.6 root 1714: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1715: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1716: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1.1.1.4 root 1717: return ((value1 | (value2 & value3)) == 1);
1718: case 13: /* ES */
1.1.1.6 root 1719: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_E) & 1;
1.1.1.4 root 1720: return (value1==1);
1721: case 14: /* LS */
1.1.1.6 root 1722: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_L) & 1;
1.1.1.4 root 1723: return (value1==1);
1724: case 15: /* LE */
1.1.1.6 root 1725: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1726: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1727: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1728: return ((value3 | (value1 ^ value2)) == 1);
1729: }
1730: return 0;
1.1 root 1731: }
1732:
1733: /**********************************
1734: * Highbyte opcodes dispatchers
1735: **********************************/
1736:
1737: static void opcode8h_0(void)
1738: {
1.1.1.4 root 1739: switch(cur_inst) {
1740: case 0x000000:
1741: dsp_nop();
1.1 root 1742: break;
1.1.1.4 root 1743: case 0x000004:
1744: dsp_rti();
1.1 root 1745: break;
1.1.1.4 root 1746: case 0x000005:
1747: dsp_illegal();
1.1 root 1748: break;
1.1.1.4 root 1749: case 0x000006:
1750: dsp_swi();
1751: break;
1752: case 0x00000c:
1753: dsp_rts();
1754: break;
1755: case 0x000084:
1756: dsp_reset();
1757: break;
1758: case 0x000086:
1759: dsp_wait();
1760: break;
1761: case 0x000087:
1762: dsp_stop();
1763: break;
1764: case 0x00008c:
1765: dsp_enddo();
1.1 root 1766: break;
1767: }
1768: }
1769:
1770: /**********************************
1771: * Non-parallel moves instructions
1772: **********************************/
1773:
1774: static void dsp_undefined(void)
1775: {
1.1.1.6 root 1776: if (isDsp_in_disasm_mode == false) {
1777: cur_inst_len = 0;
1778: fprintf(stderr, "Dsp: 0x%04x: 0x%06x Illegal instruction\n",dsp_core.pc, cur_inst);
1.1.1.7 root 1779: /* Add some artificial CPU cycles to avoid being stuck in an infinite loop */
1.1.1.6 root 1780: dsp_core.instr_cycle += 100;
1781: }
1782: else {
1783: cur_inst_len = 1;
1784: dsp_core.instr_cycle = 0;
1785: }
1.1 root 1786: }
1787:
1788: static void dsp_andi(void)
1789: {
1.1.1.2 root 1790: Uint32 regnum, value;
1.1 root 1791:
1792: value = (cur_inst >> 8) & BITMASK(8);
1793: regnum = cur_inst & BITMASK(2);
1794: switch(regnum) {
1795: case 0:
1796: /* mr */
1.1.1.6 root 1797: dsp_core.registers[DSP_REG_SR] &= (value<<8)|BITMASK(8);
1.1 root 1798: break;
1799: case 1:
1800: /* ccr */
1.1.1.6 root 1801: dsp_core.registers[DSP_REG_SR] &= (BITMASK(8)<<8)|value;
1.1 root 1802: break;
1803: case 2:
1804: /* omr */
1.1.1.6 root 1805: dsp_core.registers[DSP_REG_OMR] &= value;
1.1 root 1806: break;
1807: }
1808: }
1809:
1.1.1.4 root 1810: static void dsp_bchg_aa(void)
1.1 root 1811: {
1.1.1.4 root 1812: Uint32 memspace, addr, value, newcarry, numbit;
1.1 root 1813:
1814: memspace = (cur_inst>>6) & 1;
1815: value = (cur_inst>>8) & BITMASK(6);
1816: numbit = cur_inst & BITMASK(5);
1817:
1.1.1.4 root 1818: addr = value;
1819: value = read_memory(memspace, addr);
1820: newcarry = (value>>numbit) & 1;
1821: if (newcarry) {
1822: value -= (1<<numbit);
1823: } else {
1824: value += (1<<numbit);
1.1 root 1825: }
1.1.1.4 root 1826: write_memory(memspace, addr, value);
1.1 root 1827:
1828: /* Set carry */
1.1.1.6 root 1829: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1830: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1831:
1.1.1.6 root 1832: dsp_core.instr_cycle += 2;
1.1 root 1833: }
1834:
1.1.1.4 root 1835: static void dsp_bchg_ea(void)
1.1 root 1836: {
1.1.1.4 root 1837: Uint32 memspace, addr, value, newcarry, numbit;
1.1 root 1838:
1839: memspace = (cur_inst>>6) & 1;
1840: value = (cur_inst>>8) & BITMASK(6);
1841: numbit = cur_inst & BITMASK(5);
1842:
1.1.1.4 root 1843: dsp_calc_ea(value, &addr);
1844: value = read_memory(memspace, addr);
1845: newcarry = (value>>numbit) & 1;
1846: if (newcarry) {
1847: value -= (1<<numbit);
1848: } else {
1849: value += (1<<numbit);
1.1 root 1850: }
1.1.1.4 root 1851: write_memory(memspace, addr, value);
1.1 root 1852:
1853: /* Set carry */
1.1.1.6 root 1854: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1855: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1856:
1.1.1.6 root 1857: dsp_core.instr_cycle += 2;
1.1 root 1858: }
1859:
1.1.1.4 root 1860: static void dsp_bchg_pp(void)
1.1 root 1861: {
1.1.1.4 root 1862: Uint32 memspace, addr, value, newcarry, numbit;
1.1 root 1863:
1864: memspace = (cur_inst>>6) & 1;
1865: value = (cur_inst>>8) & BITMASK(6);
1866: numbit = cur_inst & BITMASK(5);
1867:
1.1.1.4 root 1868: addr = 0xffc0 + value;
1869: value = read_memory(memspace, addr);
1870: newcarry = (value>>numbit) & 1;
1871: if (newcarry) {
1872: value -= (1<<numbit);
1873: } else {
1874: value += (1<<numbit);
1.1 root 1875: }
1.1.1.4 root 1876: write_memory(memspace, addr, value);
1.1 root 1877:
1878: /* Set carry */
1.1.1.6 root 1879: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1880: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1881:
1.1.1.6 root 1882: dsp_core.instr_cycle += 2;
1.1 root 1883: }
1884:
1.1.1.4 root 1885: static void dsp_bchg_reg(void)
1.1 root 1886: {
1.1.1.4 root 1887: Uint32 value, numreg, newcarry, numbit;
1.1 root 1888:
1.1.1.4 root 1889: numreg = (cur_inst>>8) & BITMASK(6);
1.1 root 1890: numbit = cur_inst & BITMASK(5);
1891:
1.1.1.4 root 1892: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
1893: dsp_pm_read_accu24(numreg, &value);
1894: } else {
1.1.1.6 root 1895: value = dsp_core.registers[numreg];
1.1 root 1896: }
1897:
1.1.1.4 root 1898: newcarry = (value>>numbit) & 1;
1899: if (newcarry) {
1900: value -= (1<<numbit);
1901: } else {
1902: value += (1<<numbit);
1903: }
1904:
1905: dsp_write_reg(numreg, value);
1906:
1.1 root 1907: /* Set carry */
1.1.1.6 root 1908: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1909: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1910:
1.1.1.6 root 1911: dsp_core.instr_cycle += 2;
1.1 root 1912: }
1913:
1.1.1.4 root 1914: static void dsp_bclr_aa(void)
1.1 root 1915: {
1.1.1.4 root 1916: Uint32 memspace, addr, value, newcarry, numbit;
1917:
1918: memspace = (cur_inst>>6) & 1;
1919: addr = (cur_inst>>8) & BITMASK(6);
1920: numbit = cur_inst & BITMASK(5);
1.1 root 1921:
1.1.1.4 root 1922: value = read_memory(memspace, addr);
1923: newcarry = (value>>numbit) & 1;
1924: value &= 0xffffffff-(1<<numbit);
1925: write_memory(memspace, addr, value);
1.1.1.2 root 1926:
1.1.1.4 root 1927: /* Set carry */
1.1.1.6 root 1928: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1929: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 1930:
1.1.1.6 root 1931: dsp_core.instr_cycle += 2;
1.1.1.4 root 1932: }
1.1 root 1933:
1.1.1.4 root 1934: static void dsp_bclr_ea(void)
1935: {
1936: Uint32 memspace, addr, value, newcarry, numbit;
1937:
1938: memspace = (cur_inst>>6) & 1;
1939: value = (cur_inst>>8) & BITMASK(6);
1940: numbit = cur_inst & BITMASK(5);
1.1 root 1941:
1.1.1.4 root 1942: dsp_calc_ea(value, &addr);
1943: value = read_memory(memspace, addr);
1944: newcarry = (value>>numbit) & 1;
1945: value &= 0xffffffff-(1<<numbit);
1946: write_memory(memspace, addr, value);
1.1.1.2 root 1947:
1.1.1.4 root 1948: /* Set carry */
1.1.1.6 root 1949: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1950: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1951:
1.1.1.6 root 1952: dsp_core.instr_cycle += 2;
1.1 root 1953: }
1954:
1.1.1.4 root 1955: static void dsp_bclr_pp(void)
1956: {
1957: Uint32 memspace, addr, value, newcarry, numbit;
1958:
1959: memspace = (cur_inst>>6) & 1;
1960: value = (cur_inst>>8) & BITMASK(6);
1961: numbit = cur_inst & BITMASK(5);
1.1.1.3 root 1962:
1.1.1.4 root 1963: addr = 0xffc0 + value;
1964: value = read_memory(memspace, addr);
1965: newcarry = (value>>numbit) & 1;
1966: value &= 0xffffffff-(1<<numbit);
1967: write_memory(memspace, addr, value);
1.1.1.3 root 1968:
1.1.1.4 root 1969: /* Set carry */
1.1.1.6 root 1970: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1971: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 1972:
1.1.1.6 root 1973: dsp_core.instr_cycle += 2;
1.1.1.4 root 1974: }
1.1 root 1975:
1.1.1.4 root 1976: static void dsp_bclr_reg(void)
1977: {
1978: Uint32 value, numreg, newcarry, numbit;
1979:
1980: numreg = (cur_inst>>8) & BITMASK(6);
1981: numbit = cur_inst & BITMASK(5);
1.1 root 1982:
1.1.1.4 root 1983: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
1984: dsp_pm_read_accu24(numreg, &value);
1985: } else {
1.1.1.6 root 1986: value = dsp_core.registers[numreg];
1.1.1.4 root 1987: }
1.1 root 1988:
1.1.1.4 root 1989: newcarry = (value>>numbit) & 1;
1990: value &= 0xffffffff-(1<<numbit);
1.1 root 1991:
1.1.1.4 root 1992: dsp_write_reg(numreg, value);
1993:
1994: /* Set carry */
1.1.1.6 root 1995: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1996: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 1997:
1.1.1.6 root 1998: dsp_core.instr_cycle += 2;
1.1 root 1999: }
2000:
1.1.1.4 root 2001: static void dsp_bset_aa(void)
1.1 root 2002: {
1.1.1.4 root 2003: Uint32 memspace, addr, value, newcarry, numbit;
2004:
2005: memspace = (cur_inst>>6) & 1;
2006: value = (cur_inst>>8) & BITMASK(6);
2007: numbit = cur_inst & BITMASK(5);
1.1 root 2008:
1.1.1.4 root 2009: addr = value;
2010: value = read_memory(memspace, addr);
2011: newcarry = (value>>numbit) & 1;
2012: value |= (1<<numbit);
2013: write_memory(memspace, addr, value);
2014:
2015: /* Set carry */
1.1.1.6 root 2016: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2017: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2018:
1.1.1.6 root 2019: dsp_core.instr_cycle += 2;
1.1.1.4 root 2020: }
2021:
2022: static void dsp_bset_ea(void)
2023: {
2024: Uint32 memspace, addr, value, newcarry, numbit;
2025:
2026: memspace = (cur_inst>>6) & 1;
2027: value = (cur_inst>>8) & BITMASK(6);
2028: numbit = cur_inst & BITMASK(5);
2029:
2030: dsp_calc_ea(value, &addr);
2031: value = read_memory(memspace, addr);
2032: newcarry = (value>>numbit) & 1;
2033: value |= (1<<numbit);
2034: write_memory(memspace, addr, value);
2035:
2036: /* Set carry */
1.1.1.6 root 2037: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2038: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2039:
1.1.1.6 root 2040: dsp_core.instr_cycle += 2;
1.1.1.4 root 2041: }
2042:
2043: static void dsp_bset_pp(void)
2044: {
2045: Uint32 memspace, addr, value, newcarry, numbit;
2046:
2047: memspace = (cur_inst>>6) & 1;
2048: value = (cur_inst>>8) & BITMASK(6);
2049: numbit = cur_inst & BITMASK(5);
2050: addr = 0xffc0 + value;
2051: value = read_memory(memspace, addr);
2052: newcarry = (value>>numbit) & 1;
2053: value |= (1<<numbit);
2054: write_memory(memspace, addr, value);
2055:
2056: /* Set carry */
1.1.1.6 root 2057: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2058: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2059:
1.1.1.6 root 2060: dsp_core.instr_cycle += 2;
1.1.1.4 root 2061: }
2062:
2063: static void dsp_bset_reg(void)
2064: {
2065: Uint32 value, numreg, newcarry, numbit;
2066:
2067: numreg = (cur_inst>>8) & BITMASK(6);
2068: numbit = cur_inst & BITMASK(5);
2069:
2070: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2071: dsp_pm_read_accu24(numreg, &value);
2072: } else {
1.1.1.6 root 2073: value = dsp_core.registers[numreg];
1.1.1.4 root 2074: }
2075:
2076: newcarry = (value>>numbit) & 1;
2077: value |= (1<<numbit);
2078:
2079: dsp_write_reg(numreg, value);
2080:
2081: /* Set carry */
1.1.1.6 root 2082: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2083: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2084:
1.1.1.6 root 2085: dsp_core.instr_cycle += 2;
1.1.1.4 root 2086: }
2087:
2088: static void dsp_btst_aa(void)
2089: {
2090: Uint32 memspace, addr, value, newcarry, numbit;
2091:
2092: memspace = (cur_inst>>6) & 1;
2093: value = (cur_inst>>8) & BITMASK(6);
2094: numbit = cur_inst & BITMASK(5);
2095:
2096: addr = value;
2097: value = read_memory(memspace, addr);
2098: newcarry = (value>>numbit) & 1;
2099:
2100: /* Set carry */
1.1.1.6 root 2101: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2102: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2103:
1.1.1.6 root 2104: dsp_core.instr_cycle += 2;
1.1.1.4 root 2105: }
2106:
2107: static void dsp_btst_ea(void)
2108: {
2109: Uint32 memspace, addr, value, newcarry, numbit;
2110:
2111: memspace = (cur_inst>>6) & 1;
2112: value = (cur_inst>>8) & BITMASK(6);
2113: numbit = cur_inst & BITMASK(5);
2114:
2115: dsp_calc_ea(value, &addr);
2116: value = read_memory(memspace, addr);
2117: newcarry = (value>>numbit) & 1;
2118:
2119: /* Set carry */
1.1.1.6 root 2120: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2121: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2122:
1.1.1.6 root 2123: dsp_core.instr_cycle += 2;
1.1.1.4 root 2124: }
2125:
2126: static void dsp_btst_pp(void)
2127: {
2128: Uint32 memspace, addr, value, newcarry, numbit;
2129:
2130: memspace = (cur_inst>>6) & 1;
2131: value = (cur_inst>>8) & BITMASK(6);
2132: numbit = cur_inst & BITMASK(5);
2133:
2134: addr = 0xffc0 + value;
2135: value = read_memory(memspace, addr);
2136: newcarry = (value>>numbit) & 1;
2137:
2138: /* Set carry */
1.1.1.6 root 2139: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2140: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2141:
1.1.1.6 root 2142: dsp_core.instr_cycle += 2;
1.1.1.4 root 2143: }
2144:
2145: static void dsp_btst_reg(void)
2146: {
2147: Uint32 value, numreg, newcarry, numbit;
2148:
2149: numreg = (cur_inst>>8) & BITMASK(6);
2150: numbit = cur_inst & BITMASK(5);
2151:
2152: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2153: dsp_pm_read_accu24(numreg, &value);
2154: } else {
1.1.1.6 root 2155: value = dsp_core.registers[numreg];
1.1.1.4 root 2156: }
2157:
2158: newcarry = (value>>numbit) & 1;
2159:
2160: /* Set carry */
1.1.1.6 root 2161: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2162: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2163:
1.1.1.6 root 2164: dsp_core.instr_cycle += 2;
1.1.1.4 root 2165: }
2166:
2167: static void dsp_div(void)
2168: {
2169: Uint32 srcreg, destreg, source[3], dest[3];
2170: Uint16 newsr;
2171:
2172: srcreg = DSP_REG_NULL;
2173: switch((cur_inst>>4) & BITMASK(2)) {
2174: case 0: srcreg = DSP_REG_X0; break;
2175: case 1: srcreg = DSP_REG_Y0; break;
2176: case 2: srcreg = DSP_REG_X1; break;
2177: case 3: srcreg = DSP_REG_Y1; break;
2178: }
1.1.1.7 root 2179: source[2] = 0;
2180: source[1] = dsp_core.registers[srcreg];
2181: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.4 root 2182:
1.1.1.7 root 2183: destreg = DSP_REG_A + ((cur_inst>>3) & 1);
2184: if (destreg == DSP_REG_A) {
2185: dest[0] = dsp_core.registers[DSP_REG_A2];
2186: dest[1] = dsp_core.registers[DSP_REG_A1];
2187: dest[2] = dsp_core.registers[DSP_REG_A0];
2188: }
2189: else {
2190: dest[0] = dsp_core.registers[DSP_REG_B2];
2191: dest[1] = dsp_core.registers[DSP_REG_B1];
2192: dest[2] = dsp_core.registers[DSP_REG_B0];
2193: }
1.1.1.4 root 2194:
2195: if (((dest[0]>>7) & 1) ^ ((source[1]>>23) & 1)) {
2196: /* D += S */
2197: newsr = dsp_asl56(dest);
2198: dsp_add56(source, dest);
2199: } else {
2200: /* D -= S */
2201: newsr = dsp_asl56(dest);
2202: dsp_sub56(source, dest);
2203: }
2204:
1.1.1.6 root 2205: dest[2] |= (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1.1.4 root 2206:
1.1.1.7 root 2207: if (destreg == DSP_REG_A) {
2208: dsp_core.registers[DSP_REG_A2] = dest[0];
2209: dsp_core.registers[DSP_REG_A1] = dest[1];
2210: dsp_core.registers[DSP_REG_A0] = dest[2];
2211: }
2212: else {
2213: dsp_core.registers[DSP_REG_B2] = dest[0];
2214: dsp_core.registers[DSP_REG_B1] = dest[1];
2215: dsp_core.registers[DSP_REG_B0] = dest[2];
2216: }
2217:
1.1.1.6 root 2218: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
2219: dsp_core.registers[DSP_REG_SR] |= (1-((dest[0]>>7) & 1))<<DSP_SR_C;
2220: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_L);
2221: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_V);
1.1.1.4 root 2222: }
2223:
2224: /*
2225: DO instruction parameter encoding
2226:
2227: xxxxxxxx 00xxxxxx 0xxxxxxx aa
2228: xxxxxxxx 01xxxxxx 0xxxxxxx ea
2229: xxxxxxxx YYxxxxxx 1xxxxxxx imm
2230: xxxxxxxx 11xxxxxx 0xxxxxxx reg
2231: */
2232:
2233: static void dsp_do_aa(void)
2234: {
2235: Uint32 memspace, addr;
2236:
2237: /* x:aa */
2238: /* y:aa */
2239:
1.1.1.6 root 2240: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2241: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2242: cur_inst_len++;
1.1.1.6 root 2243: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2244: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1 root 2245:
2246: memspace = (cur_inst>>6) & 1;
2247: addr = (cur_inst>>8) & BITMASK(6);
1.1.1.6 root 2248: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
1.1.1.4 root 2249:
1.1.1.6 root 2250: dsp_core.instr_cycle += 4;
1.1 root 2251: }
2252:
1.1.1.3 root 2253: static void dsp_do_imm(void)
1.1 root 2254: {
2255: /* #xx */
1.1.1.3 root 2256:
1.1.1.6 root 2257: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2258: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2259: cur_inst_len++;
1.1.1.6 root 2260: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2261: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2262:
1.1.1.6 root 2263: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
1.1.1.3 root 2264: + ((cur_inst & BITMASK(4))<<8);
1.1.1.4 root 2265:
1.1.1.6 root 2266: dsp_core.instr_cycle += 4;
1.1 root 2267: }
2268:
1.1.1.3 root 2269: static void dsp_do_ea(void)
1.1 root 2270: {
1.1.1.2 root 2271: Uint32 memspace, ea_mode, addr;
1.1 root 2272:
2273: /* x:ea */
2274: /* y:ea */
2275:
1.1.1.6 root 2276: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2277: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2278: cur_inst_len++;
1.1.1.6 root 2279: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2280: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2281:
1.1 root 2282: memspace = (cur_inst>>6) & 1;
2283: ea_mode = (cur_inst>>8) & BITMASK(6);
2284: dsp_calc_ea(ea_mode, &addr);
1.1.1.6 root 2285: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
1.1.1.4 root 2286:
1.1.1.6 root 2287: dsp_core.instr_cycle += 4;
1.1 root 2288: }
2289:
1.1.1.3 root 2290: static void dsp_do_reg(void)
1.1 root 2291: {
1.1.1.2 root 2292: Uint32 numreg;
1.1 root 2293:
2294: /* S */
2295:
1.1.1.6 root 2296: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2297: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2298: cur_inst_len++;
2299:
1.1 root 2300: numreg = (cur_inst>>8) & BITMASK(6);
2301: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.6 root 2302: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
1.1 root 2303: } else {
1.1.1.6 root 2304: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
1.1 root 2305: }
1.1.1.6 root 2306: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.4 root 2307:
1.1.1.6 root 2308: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2309: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2310:
1.1.1.6 root 2311: dsp_core.instr_cycle += 4;
1.1 root 2312: }
2313:
2314: static void dsp_enddo(void)
2315: {
1.1.1.4 root 2316: Uint32 saved_pc, saved_sr;
1.1 root 2317:
1.1.1.4 root 2318: dsp_stack_pop(&saved_pc, &saved_sr);
1.1.1.6 root 2319: dsp_core.registers[DSP_REG_SR] &= 0x7f;
2320: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
2321: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
1.1 root 2322: }
2323:
2324: static void dsp_illegal(void)
2325: {
2326: /* Raise interrupt p:0x003e */
1.1.1.5 root 2327: dsp_add_interrupt(DSP_INTER_ILLEGAL);
1.1 root 2328: }
2329:
1.1.1.4 root 2330: static void dsp_jcc_imm(void)
1.1 root 2331: {
1.1.1.4 root 2332: Uint32 cc_code, newpc;
1.1 root 2333:
1.1.1.4 root 2334: newpc = cur_inst & BITMASK(12);
2335: cc_code=(cur_inst>>12) & BITMASK(4);
2336: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2337: dsp_core.pc = newpc;
1.1.1.4 root 2338: cur_inst_len = 0;
2339: }
2340:
1.1.1.6 root 2341: dsp_core.instr_cycle += 2;
1.1.1.4 root 2342: }
2343:
2344: static void dsp_jcc_ea(void)
2345: {
2346: Uint32 newpc, cc_code;
2347:
2348: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2349: cc_code=cur_inst & BITMASK(4);
1.1 root 2350:
2351: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2352: dsp_core.pc = newpc;
1.1 root 2353: cur_inst_len = 0;
2354: }
1.1.1.4 root 2355:
1.1.1.6 root 2356: dsp_core.instr_cycle += 2;
1.1 root 2357: }
2358:
1.1.1.4 root 2359: static void dsp_jclr_aa(void)
1.1 root 2360: {
1.1.1.4 root 2361: Uint32 memspace, addr, value, numbit, newaddr;
1.1 root 2362:
2363: memspace = (cur_inst>>6) & 1;
1.1.1.4 root 2364: addr = (cur_inst>>8) & BITMASK(6);
1.1 root 2365: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2366: value = read_memory(memspace, addr);
1.1.1.6 root 2367: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2368:
1.1.1.6 root 2369: dsp_core.instr_cycle += 4;
1.1 root 2370:
1.1.1.4 root 2371: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2372: dsp_core.pc = newaddr;
1.1.1.4 root 2373: cur_inst_len = 0;
2374: return;
2375: }
1.1.1.2 root 2376: ++cur_inst_len;
1.1.1.4 root 2377: }
2378:
2379: static void dsp_jclr_ea(void)
2380: {
2381: Uint32 memspace, addr, value, numbit, newaddr;
2382:
2383: memspace = (cur_inst>>6) & 1;
2384: value = (cur_inst>>8) & BITMASK(6);
2385: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2386: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2387:
2388: dsp_calc_ea(value, &addr);
2389: value = read_memory(memspace, addr);
2390:
1.1.1.6 root 2391: dsp_core.instr_cycle += 4;
1.1 root 2392:
2393: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2394: dsp_core.pc = newaddr;
1.1.1.4 root 2395: cur_inst_len = 0;
2396: return;
2397: }
2398: ++cur_inst_len;
2399: }
1.1 root 2400:
1.1.1.4 root 2401: static void dsp_jclr_pp(void)
2402: {
2403: Uint32 memspace, addr, value, numbit, newaddr;
2404:
2405: memspace = (cur_inst>>6) & 1;
2406: value = (cur_inst>>8) & BITMASK(6);
2407: numbit = cur_inst & BITMASK(5);
2408: addr = 0xffc0 + value;
2409: value = read_memory(memspace, addr);
1.1.1.6 root 2410: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2411:
1.1.1.6 root 2412: dsp_core.instr_cycle += 4;
1.1 root 2413:
1.1.1.4 root 2414: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2415: dsp_core.pc = newaddr;
1.1.1.4 root 2416: cur_inst_len = 0;
2417: return;
2418: }
2419: ++cur_inst_len;
2420: }
1.1.1.2 root 2421:
1.1.1.4 root 2422: static void dsp_jclr_reg(void)
2423: {
2424: Uint32 value, numreg, numbit, newaddr;
2425:
2426: numreg = (cur_inst>>8) & BITMASK(6);
2427: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2428: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2429:
1.1.1.4 root 2430: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2431: dsp_pm_read_accu24(numreg, &value);
2432: } else {
1.1.1.6 root 2433: value = dsp_core.registers[numreg];
1.1.1.4 root 2434: }
1.1 root 2435:
1.1.1.6 root 2436: dsp_core.instr_cycle += 4;
1.1.1.4 root 2437:
2438: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2439: dsp_core.pc = newaddr;
1.1 root 2440: cur_inst_len = 0;
2441: return;
2442: }
1.1.1.4 root 2443: ++cur_inst_len;
1.1 root 2444: }
2445:
1.1.1.4 root 2446: static void dsp_jmp_ea(void)
1.1 root 2447: {
1.1.1.2 root 2448: Uint32 newpc;
1.1 root 2449:
1.1.1.4 root 2450: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &newpc);
1.1 root 2451: cur_inst_len = 0;
1.1.1.6 root 2452: dsp_core.pc = newpc;
1.1 root 2453:
1.1.1.6 root 2454: dsp_core.instr_cycle += 2;
1.1.1.4 root 2455: }
2456:
2457: static void dsp_jmp_imm(void)
2458: {
2459: Uint32 newpc;
1.1 root 2460:
1.1.1.4 root 2461: newpc = cur_inst & BITMASK(12);
2462: cur_inst_len = 0;
1.1.1.6 root 2463: dsp_core.pc = newpc;
1.1.1.4 root 2464:
1.1.1.6 root 2465: dsp_core.instr_cycle += 2;
1.1 root 2466: }
2467:
1.1.1.4 root 2468: static void dsp_jscc_ea(void)
1.1 root 2469: {
1.1.1.2 root 2470: Uint32 newpc, cc_code;
1.1 root 2471:
1.1.1.4 root 2472: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2473: cc_code=cur_inst & BITMASK(4);
2474:
2475: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2476: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2477: dsp_core.pc = newpc;
1.1.1.4 root 2478: cur_inst_len = 0;
2479: }
2480:
1.1.1.6 root 2481: dsp_core.instr_cycle += 2;
1.1.1.4 root 2482: }
1.1 root 2483:
1.1.1.4 root 2484: static void dsp_jscc_imm(void)
2485: {
2486: Uint32 cc_code, newpc;
2487:
2488: newpc = cur_inst & BITMASK(12);
2489: cc_code=(cur_inst>>12) & BITMASK(4);
1.1 root 2490: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2491: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2492: dsp_core.pc = newpc;
1.1.1.4 root 2493: cur_inst_len = 0;
2494: }
2495:
1.1.1.6 root 2496: dsp_core.instr_cycle += 2;
1.1.1.4 root 2497: }
1.1 root 2498:
1.1.1.4 root 2499: static void dsp_jsclr_aa(void)
2500: {
2501: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2502:
2503: memspace = (cur_inst>>6) & 1;
2504: addr = (cur_inst>>8) & BITMASK(6);
2505: numbit = cur_inst & BITMASK(5);
2506: value = read_memory(memspace, addr);
1.1.1.6 root 2507: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2508:
1.1.1.6 root 2509: dsp_core.instr_cycle += 4;
1.1.1.4 root 2510:
2511: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2512: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2513: newpc = newaddr;
1.1.1.6 root 2514: dsp_core.pc = newpc;
1.1 root 2515: cur_inst_len = 0;
1.1.1.4 root 2516: return;
1.1 root 2517: }
1.1.1.4 root 2518: ++cur_inst_len;
1.1 root 2519: }
2520:
1.1.1.4 root 2521: static void dsp_jsclr_ea(void)
1.1 root 2522: {
1.1.1.4 root 2523: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1 root 2524:
2525: memspace = (cur_inst>>6) & 1;
2526: value = (cur_inst>>8) & BITMASK(6);
2527: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2528: dsp_calc_ea(value, &addr);
2529: value = read_memory(memspace, addr);
1.1.1.6 root 2530: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2531:
1.1.1.6 root 2532: dsp_core.instr_cycle += 4;
1.1.1.4 root 2533:
2534: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2535: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2536: newpc = newaddr;
1.1.1.6 root 2537: dsp_core.pc = newpc;
1.1.1.4 root 2538: cur_inst_len = 0;
2539: return;
2540: }
1.1.1.2 root 2541: ++cur_inst_len;
1.1.1.4 root 2542: }
2543:
2544: static void dsp_jsclr_pp(void)
2545: {
2546: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2547:
2548: memspace = (cur_inst>>6) & 1;
2549: value = (cur_inst>>8) & BITMASK(6);
2550: numbit = cur_inst & BITMASK(5);
2551: addr = 0xffc0 + value;
2552: value = read_memory(memspace, addr);
1.1.1.6 root 2553: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2554:
1.1.1.6 root 2555: dsp_core.instr_cycle += 4;
1.1.1.4 root 2556:
1.1 root 2557: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2558: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2559: newpc = newaddr;
1.1.1.6 root 2560: dsp_core.pc = newpc;
1.1.1.4 root 2561: cur_inst_len = 0;
2562: return;
2563: }
2564: ++cur_inst_len;
2565: }
2566:
2567: static void dsp_jsclr_reg(void)
2568: {
2569: Uint32 value, numreg, newpc, numbit, newaddr;
2570:
2571: numreg = (cur_inst>>8) & BITMASK(6);
2572: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2573: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2574:
1.1.1.4 root 2575: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2576: dsp_pm_read_accu24(numreg, &value);
2577: } else {
1.1.1.6 root 2578: value = dsp_core.registers[numreg];
1.1.1.4 root 2579: }
2580:
1.1.1.6 root 2581: dsp_core.instr_cycle += 4;
1.1.1.4 root 2582:
2583: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2584: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2585: newpc = newaddr;
1.1.1.6 root 2586: dsp_core.pc = newpc;
1.1 root 2587: cur_inst_len = 0;
1.1.1.4 root 2588: return;
1.1 root 2589: }
1.1.1.4 root 2590: ++cur_inst_len;
1.1 root 2591: }
2592:
1.1.1.4 root 2593: static void dsp_jset_aa(void)
1.1 root 2594: {
1.1.1.4 root 2595: Uint32 memspace, addr, value, numbit, newpc, newaddr;
2596:
2597: memspace = (cur_inst>>6) & 1;
2598: addr = (cur_inst>>8) & BITMASK(6);
2599: numbit = cur_inst & BITMASK(5);
2600: value = read_memory(memspace, addr);
1.1.1.6 root 2601: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2602:
1.1.1.6 root 2603: dsp_core.instr_cycle += 4;
1.1.1.4 root 2604:
2605: if (value & (1<<numbit)) {
2606: newpc = newaddr;
1.1.1.6 root 2607: dsp_core.pc = newpc;
1.1.1.4 root 2608: cur_inst_len=0;
2609: return;
2610: }
2611: ++cur_inst_len;
2612: }
2613:
2614: static void dsp_jset_ea(void)
2615: {
2616: Uint32 memspace, addr, value, numbit, newpc, newaddr;
1.1 root 2617:
2618: memspace = (cur_inst>>6) & 1;
2619: value = (cur_inst>>8) & BITMASK(6);
2620: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2621: dsp_calc_ea(value, &addr);
2622: value = read_memory(memspace, addr);
1.1.1.6 root 2623: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2624:
1.1.1.6 root 2625: dsp_core.instr_cycle += 4;
1.1.1.7 root 2626:
1.1.1.4 root 2627: if (value & (1<<numbit)) {
2628: newpc = newaddr;
1.1.1.6 root 2629: dsp_core.pc = newpc;
1.1.1.4 root 2630: cur_inst_len=0;
2631: return;
2632: }
2633: ++cur_inst_len;
2634: }
1.1 root 2635:
1.1.1.4 root 2636: static void dsp_jset_pp(void)
2637: {
2638: Uint32 memspace, addr, value, numbit, newpc, newaddr;
2639:
2640: memspace = (cur_inst>>6) & 1;
2641: value = (cur_inst>>8) & BITMASK(6);
2642: numbit = cur_inst & BITMASK(5);
2643: addr = 0xffc0 + value;
2644: value = read_memory(memspace, addr);
1.1.1.6 root 2645: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2646:
1.1.1.6 root 2647: dsp_core.instr_cycle += 4;
1.1.1.4 root 2648:
2649: if (value & (1<<numbit)) {
2650: newpc = newaddr;
1.1.1.6 root 2651: dsp_core.pc = newpc;
1.1.1.4 root 2652: cur_inst_len=0;
2653: return;
2654: }
2655: ++cur_inst_len;
2656: }
2657:
2658: static void dsp_jset_reg(void)
2659: {
2660: Uint32 value, numreg, numbit, newpc, newaddr;
2661:
2662: numreg = (cur_inst>>8) & BITMASK(6);
2663: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2664: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2665:
2666: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2667: dsp_pm_read_accu24(numreg, &value);
2668: } else {
1.1.1.6 root 2669: value = dsp_core.registers[numreg];
1.1.1.4 root 2670: }
2671:
1.1.1.6 root 2672: dsp_core.instr_cycle += 4;
1.1.1.4 root 2673:
2674: if (value & (1<<numbit)) {
2675: newpc = newaddr;
1.1.1.6 root 2676: dsp_core.pc = newpc;
1.1.1.4 root 2677: cur_inst_len=0;
2678: return;
2679: }
2680: ++cur_inst_len;
2681: }
2682:
2683: static void dsp_jsr_imm(void)
2684: {
2685: Uint32 newpc;
2686:
2687: newpc = cur_inst & BITMASK(12);
2688:
1.1.1.6 root 2689: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2690: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2691: }
2692: else {
1.1.1.6 root 2693: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1.1.1.4 root 2694: }
2695:
1.1.1.6 root 2696: dsp_core.pc = newpc;
1.1.1.4 root 2697: cur_inst_len = 0;
2698:
1.1.1.6 root 2699: dsp_core.instr_cycle += 2;
1.1.1.4 root 2700: }
2701:
2702: static void dsp_jsr_ea(void)
2703: {
2704: Uint32 newpc;
2705:
2706: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&newpc);
2707:
1.1.1.6 root 2708: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2709: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2710: }
2711: else {
1.1.1.6 root 2712: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1.1.1.4 root 2713: }
2714:
1.1.1.6 root 2715: dsp_core.pc = newpc;
1.1.1.4 root 2716: cur_inst_len = 0;
2717:
1.1.1.6 root 2718: dsp_core.instr_cycle += 2;
1.1.1.4 root 2719: }
2720:
2721: static void dsp_jsset_aa(void)
2722: {
2723: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2724:
2725: memspace = (cur_inst>>6) & 1;
2726: addr = (cur_inst>>8) & BITMASK(6);
2727: numbit = cur_inst & BITMASK(5);
2728: value = read_memory(memspace, addr);
1.1.1.6 root 2729: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2730:
1.1.1.6 root 2731: dsp_core.instr_cycle += 4;
1.1.1.4 root 2732:
2733: if (value & (1<<numbit)) {
1.1.1.6 root 2734: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2735: newpc = newaddr;
1.1.1.6 root 2736: dsp_core.pc = newpc;
1.1.1.4 root 2737: cur_inst_len = 0;
2738: return;
2739: }
2740: ++cur_inst_len;
2741: }
2742:
2743: static void dsp_jsset_ea(void)
2744: {
2745: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2746:
2747: memspace = (cur_inst>>6) & 1;
2748: value = (cur_inst>>8) & BITMASK(6);
2749: numbit = cur_inst & BITMASK(5);
2750: dsp_calc_ea(value, &addr);
2751: value = read_memory(memspace, addr);
1.1.1.6 root 2752: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2753:
1.1.1.6 root 2754: dsp_core.instr_cycle += 4;
1.1 root 2755:
2756: if (value & (1<<numbit)) {
1.1.1.6 root 2757: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2758: newpc = newaddr;
1.1.1.6 root 2759: dsp_core.pc = newpc;
1.1.1.4 root 2760: cur_inst_len = 0;
2761: return;
1.1 root 2762: }
1.1.1.4 root 2763: ++cur_inst_len;
1.1 root 2764: }
2765:
1.1.1.4 root 2766: static void dsp_jsset_pp(void)
1.1 root 2767: {
1.1.1.4 root 2768: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2769:
2770: memspace = (cur_inst>>6) & 1;
2771: value = (cur_inst>>8) & BITMASK(6);
2772: numbit = cur_inst & BITMASK(5);
2773: addr = 0xffc0 + value;
2774: value = read_memory(memspace, addr);
1.1.1.6 root 2775: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2776:
1.1.1.6 root 2777: dsp_core.instr_cycle += 4;
1.1 root 2778:
1.1.1.4 root 2779: if (value & (1<<numbit)) {
1.1.1.6 root 2780: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2781: newpc = newaddr;
1.1.1.6 root 2782: dsp_core.pc = newpc;
1.1.1.4 root 2783: cur_inst_len = 0;
2784: return;
2785: }
2786: ++cur_inst_len;
1.1 root 2787: }
2788:
1.1.1.4 root 2789: static void dsp_jsset_reg(void)
1.1 root 2790: {
1.1.1.4 root 2791: Uint32 value, numreg, newpc, numbit, newaddr;
1.1 root 2792:
1.1.1.4 root 2793: numreg = (cur_inst>>8) & BITMASK(6);
1.1 root 2794: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2795: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2796:
2797: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2798: dsp_pm_read_accu24(numreg, &value);
2799: } else {
1.1.1.6 root 2800: value = dsp_core.registers[numreg];
1.1.1.4 root 2801: }
1.1 root 2802:
1.1.1.6 root 2803: dsp_core.instr_cycle += 4;
1.1 root 2804:
2805: if (value & (1<<numbit)) {
1.1.1.6 root 2806: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2807: newpc = newaddr;
1.1.1.6 root 2808: dsp_core.pc = newpc;
1.1 root 2809: cur_inst_len = 0;
1.1.1.4 root 2810: return;
1.1 root 2811: }
1.1.1.4 root 2812: ++cur_inst_len;
1.1 root 2813: }
2814:
2815: static void dsp_lua(void)
2816: {
1.1.1.2 root 2817: Uint32 value, srcreg, dstreg, srcsave, srcnew;
2818:
1.1 root 2819: srcreg = (cur_inst>>8) & BITMASK(3);
1.1.1.2 root 2820:
1.1.1.6 root 2821: srcsave = dsp_core.registers[DSP_REG_R0+srcreg];
1.1.1.2 root 2822: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &value);
1.1.1.6 root 2823: srcnew = dsp_core.registers[DSP_REG_R0+srcreg];
2824: dsp_core.registers[DSP_REG_R0+srcreg] = srcsave;
1.1.1.2 root 2825:
1.1 root 2826: dstreg = cur_inst & BITMASK(3);
2827:
2828: if (cur_inst & (1<<3)) {
1.1.1.6 root 2829: dsp_core.registers[DSP_REG_N0+dstreg] = srcnew;
1.1 root 2830: } else {
1.1.1.6 root 2831: dsp_core.registers[DSP_REG_R0+dstreg] = srcnew;
1.1 root 2832: }
2833:
1.1.1.6 root 2834: dsp_core.instr_cycle += 2;
1.1 root 2835: }
2836:
1.1.1.3 root 2837: static void dsp_movec_reg(void)
1.1 root 2838: {
1.1.1.4 root 2839: Uint32 numreg1, numreg2, value, dummy;
1.1 root 2840:
2841: /* S1,D2 */
2842: /* S2,D1 */
2843:
2844: numreg2 = (cur_inst>>8) & BITMASK(6);
1.1.1.4 root 2845: numreg1 = cur_inst & BITMASK(6);
1.1 root 2846:
2847: if (cur_inst & (1<<15)) {
2848: /* Write D1 */
2849:
2850: if ((numreg2 == DSP_REG_A) || (numreg2 == DSP_REG_B)) {
1.1.1.4 root 2851: dsp_pm_read_accu24(numreg2, &value);
1.1 root 2852: } else {
1.1.1.6 root 2853: value = dsp_core.registers[numreg2];
1.1 root 2854: }
1.1.1.4 root 2855: value &= BITMASK(registers_mask[numreg1]);
2856: dsp_write_reg(numreg1, value);
1.1 root 2857: } else {
2858: /* Read S1 */
1.1.1.4 root 2859: if (numreg1 == DSP_REG_SSH) {
2860: dsp_stack_pop(&value, &dummy);
2861: }
2862: else {
1.1.1.6 root 2863: value = dsp_core.registers[numreg1];
1.1.1.4 root 2864: }
1.1 root 2865:
1.1.1.7 root 2866: if (numreg2 == DSP_REG_A) {
2867: dsp_core.registers[DSP_REG_A0] = 0;
2868: dsp_core.registers[DSP_REG_A1] = value & BITMASK(24);
2869: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
2870: }
2871: else if (numreg2 == DSP_REG_B) {
2872: dsp_core.registers[DSP_REG_B0] = 0;
2873: dsp_core.registers[DSP_REG_B1] = value & BITMASK(24);
2874: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
2875: }
2876: else {
1.1.1.6 root 2877: dsp_core.registers[numreg2] = value & BITMASK(registers_mask[numreg2]);
1.1 root 2878: }
2879: }
2880: }
2881:
1.1.1.3 root 2882: static void dsp_movec_aa(void)
1.1 root 2883: {
1.1.1.4 root 2884: Uint32 numreg, addr, memspace, value, dummy;
1.1 root 2885:
2886: /* x:aa,D1 */
2887: /* S1,x:aa */
2888: /* y:aa,D1 */
2889: /* S1,y:aa */
2890:
1.1.1.4 root 2891: numreg = cur_inst & BITMASK(6);
1.1 root 2892: addr = (cur_inst>>8) & BITMASK(6);
2893: memspace = (cur_inst>>6) & 1;
2894:
2895: if (cur_inst & (1<<15)) {
2896: /* Write D1 */
1.1.1.4 root 2897: value = read_memory(memspace, addr);
2898: value &= BITMASK(registers_mask[numreg]);
2899: dsp_write_reg(numreg, value);
1.1 root 2900: } else {
2901: /* Read S1 */
1.1.1.4 root 2902: if (numreg == DSP_REG_SSH) {
2903: dsp_stack_pop(&value, &dummy);
2904: }
2905: else {
1.1.1.6 root 2906: value = dsp_core.registers[numreg];
1.1.1.4 root 2907: }
2908: write_memory(memspace, addr, value);
1.1 root 2909: }
2910: }
2911:
1.1.1.3 root 2912: static void dsp_movec_imm(void)
1.1 root 2913: {
1.1.1.4 root 2914: Uint32 numreg, value;
1.1 root 2915:
2916: /* #xx,D1 */
1.1.1.4 root 2917: numreg = cur_inst & BITMASK(6);
2918: value = (cur_inst>>8) & BITMASK(8);
2919: value &= BITMASK(registers_mask[numreg]);
2920: dsp_write_reg(numreg, value);
1.1 root 2921: }
2922:
1.1.1.3 root 2923: static void dsp_movec_ea(void)
1.1 root 2924: {
1.1.1.4 root 2925: Uint32 numreg, addr, memspace, ea_mode, value, dummy;
1.1 root 2926: int retour;
2927:
2928: /* x:ea,D1 */
2929: /* S1,x:ea */
2930: /* y:ea,D1 */
2931: /* S1,y:ea */
2932: /* #xxxx,D1 */
2933:
1.1.1.4 root 2934: numreg = cur_inst & BITMASK(6);
1.1 root 2935: ea_mode = (cur_inst>>8) & BITMASK(6);
2936: memspace = (cur_inst>>6) & 1;
2937:
2938: if (cur_inst & (1<<15)) {
2939: /* Write D1 */
2940: retour = dsp_calc_ea(ea_mode, &addr);
2941: if (retour) {
1.1.1.4 root 2942: value = addr;
1.1 root 2943: } else {
1.1.1.4 root 2944: value = read_memory(memspace, addr);
1.1 root 2945: }
1.1.1.4 root 2946: value &= BITMASK(registers_mask[numreg]);
2947: dsp_write_reg(numreg, value);
1.1 root 2948: } else {
2949: /* Read S1 */
1.1.1.4 root 2950: dsp_calc_ea(ea_mode, &addr);
2951: if (numreg == DSP_REG_SSH) {
2952: dsp_stack_pop(&value, &dummy);
2953: }
2954: else {
1.1.1.6 root 2955: value = dsp_core.registers[numreg];
1.1.1.4 root 2956: }
2957: write_memory(memspace, addr, value);
1.1 root 2958: }
2959: }
2960:
1.1.1.4 root 2961: static void dsp_movem_aa(void)
1.1 root 2962: {
1.1.1.4 root 2963: Uint32 numreg, addr, value, dummy;
1.1 root 2964:
2965: numreg = cur_inst & BITMASK(6);
1.1.1.4 root 2966: addr = (cur_inst>>8) & BITMASK(6);
1.1 root 2967:
1.1.1.4 root 2968: if (cur_inst & (1<<15)) {
2969: /* Write D */
2970: value = read_memory_p(addr);
2971: value &= BITMASK(registers_mask[numreg]);
2972: dsp_write_reg(numreg, value);
1.1 root 2973: } else {
1.1.1.4 root 2974: /* Read S */
2975: if (numreg == DSP_REG_SSH) {
2976: dsp_stack_pop(&value, &dummy);
2977: }
2978: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
2979: dsp_pm_read_accu24(numreg, &value);
2980: }
2981: else {
1.1.1.6 root 2982: value = dsp_core.registers[numreg];
1.1.1.4 root 2983: }
2984: write_memory(DSP_SPACE_P, addr, value);
2985: }
1.1 root 2986:
1.1.1.6 root 2987: dsp_core.instr_cycle += 4;
1.1.1.4 root 2988: }
2989:
2990: static void dsp_movem_ea(void)
2991: {
2992: Uint32 numreg, addr, ea_mode, value, dummy;
2993:
2994: numreg = cur_inst & BITMASK(6);
2995: ea_mode = (cur_inst>>8) & BITMASK(6);
2996: dsp_calc_ea(ea_mode, &addr);
1.1 root 2997:
2998: if (cur_inst & (1<<15)) {
2999: /* Write D */
1.1.1.4 root 3000: value = read_memory_p(addr);
3001: value &= BITMASK(registers_mask[numreg]);
3002: dsp_write_reg(numreg, value);
1.1 root 3003: } else {
3004: /* Read S */
1.1.1.4 root 3005: if (numreg == DSP_REG_SSH) {
3006: dsp_stack_pop(&value, &dummy);
3007: }
3008: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1 root 3009: dsp_pm_read_accu24(numreg, &value);
1.1.1.4 root 3010: }
3011: else {
1.1.1.6 root 3012: value = dsp_core.registers[numreg];
1.1 root 3013: }
3014: write_memory(DSP_SPACE_P, addr, value);
3015: }
3016:
1.1.1.6 root 3017: dsp_core.instr_cycle += 4;
1.1 root 3018: }
3019:
3020: static void dsp_movep_0(void)
3021: {
3022: /* S,x:pp */
3023: /* x:pp,D */
3024: /* S,y:pp */
3025: /* y:pp,D */
3026:
1.1.1.4 root 3027: Uint32 addr, memspace, numreg, value, dummy;
1.1 root 3028:
3029: addr = 0xffc0 + (cur_inst & BITMASK(6));
3030: memspace = (cur_inst>>16) & 1;
3031: numreg = (cur_inst>>8) & BITMASK(6);
3032:
3033: if (cur_inst & (1<<15)) {
3034: /* Write pp */
3035: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
3036: dsp_pm_read_accu24(numreg, &value);
1.1.1.4 root 3037: }
3038: else if (numreg == DSP_REG_SSH) {
3039: dsp_stack_pop(&value, &dummy);
3040: }
3041: else {
1.1.1.6 root 3042: value = dsp_core.registers[numreg];
1.1 root 3043: }
3044: write_memory(memspace, addr, value);
3045: } else {
3046: /* Read pp */
3047: value = read_memory(memspace, addr);
1.1.1.4 root 3048: value &= BITMASK(registers_mask[numreg]);
3049: dsp_write_reg(numreg, value);
1.1 root 3050: }
1.1.1.4 root 3051:
1.1.1.6 root 3052: dsp_core.instr_cycle += 2;
1.1 root 3053: }
3054:
3055: static void dsp_movep_1(void)
3056: {
3057: /* p:ea,x:pp */
3058: /* x:pp,p:ea */
3059: /* p:ea,y:pp */
3060: /* y:pp,p:ea */
3061:
1.1.1.2 root 3062: Uint32 xyaddr, memspace, paddr;
1.1 root 3063:
3064: xyaddr = 0xffc0 + (cur_inst & BITMASK(6));
3065: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &paddr);
3066: memspace = (cur_inst>>16) & 1;
3067:
3068: if (cur_inst & (1<<15)) {
3069: /* Write pp */
1.1.1.4 root 3070: write_memory(memspace, xyaddr, read_memory_p(paddr));
1.1 root 3071: } else {
3072: /* Read pp */
3073: write_memory(DSP_SPACE_P, paddr, read_memory(memspace, xyaddr));
3074: }
1.1.1.4 root 3075:
1.1.1.7 root 3076: /* Movep is 4 cycles, but according to the motorola doc, */
3077: /* movep from p memory to x or y peripheral memory takes */
3078: /* 2 more cycles, so +4 cycles at total */
3079: dsp_core.instr_cycle += 4;
1.1 root 3080: }
3081:
1.1.1.4 root 3082: static void dsp_movep_23(void)
1.1 root 3083: {
3084: /* x:ea,x:pp */
3085: /* y:ea,x:pp */
3086: /* #xxxxxx,x:pp */
3087: /* x:pp,x:ea */
3088: /* x:pp,y:pp */
3089: /* x:ea,y:pp */
3090: /* y:ea,y:pp */
3091: /* #xxxxxx,y:pp */
3092: /* y:pp,y:ea */
3093: /* y:pp,x:ea */
3094:
1.1.1.2 root 3095: Uint32 addr, peraddr, easpace, perspace, ea_mode;
1.1 root 3096: int retour;
3097:
3098: peraddr = 0xffc0 + (cur_inst & BITMASK(6));
3099: perspace = (cur_inst>>16) & 1;
3100:
3101: ea_mode = (cur_inst>>8) & BITMASK(6);
3102: easpace = (cur_inst>>6) & 1;
3103: retour = dsp_calc_ea(ea_mode, &addr);
3104:
3105: if (cur_inst & (1<<15)) {
3106: /* Write pp */
3107:
3108: if (retour) {
3109: write_memory(perspace, peraddr, addr);
3110: } else {
3111: write_memory(perspace, peraddr, read_memory(easpace, addr));
3112: }
3113: } else {
3114: /* Read pp */
3115: write_memory(easpace, addr, read_memory(perspace, peraddr));
3116: }
1.1.1.4 root 3117:
1.1.1.6 root 3118: dsp_core.instr_cycle += 2;
1.1 root 3119: }
3120:
3121: static void dsp_norm(void)
3122: {
1.1.1.2 root 3123: Uint32 cursr,cur_e, cur_euz, dest[3], numreg, rreg;
3124: Uint16 newsr;
1.1 root 3125:
1.1.1.6 root 3126: cursr = dsp_core.registers[DSP_REG_SR];
1.1 root 3127: cur_e = (cursr>>DSP_SR_E) & 1; /* E */
3128: cur_euz = ~cur_e; /* (not E) and U and (not Z) */
3129: cur_euz &= (cursr>>DSP_SR_U) & 1;
3130: cur_euz &= ~((cursr>>DSP_SR_Z) & 1);
3131: cur_euz &= 1;
3132:
3133: numreg = (cur_inst>>3) & 1;
1.1.1.6 root 3134: dest[0] = dsp_core.registers[DSP_REG_A2+numreg];
3135: dest[1] = dsp_core.registers[DSP_REG_A1+numreg];
3136: dest[2] = dsp_core.registers[DSP_REG_A0+numreg];
1.1 root 3137: rreg = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3138:
3139: if (cur_euz) {
3140: newsr = dsp_asl56(dest);
1.1.1.6 root 3141: --dsp_core.registers[rreg];
3142: dsp_core.registers[rreg] &= BITMASK(16);
1.1 root 3143: } else if (cur_e) {
3144: newsr = dsp_asr56(dest);
1.1.1.6 root 3145: ++dsp_core.registers[rreg];
3146: dsp_core.registers[rreg] &= BITMASK(16);
1.1 root 3147: } else {
3148: newsr = 0;
3149: }
3150:
1.1.1.6 root 3151: dsp_core.registers[DSP_REG_A2+numreg] = dest[0];
3152: dsp_core.registers[DSP_REG_A1+numreg] = dest[1];
3153: dsp_core.registers[DSP_REG_A0+numreg] = dest[2];
1.1.1.2 root 3154:
1.1.1.6 root 3155: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 3156:
1.1.1.6 root 3157: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
3158: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 3159: }
3160:
3161: static void dsp_ori(void)
3162: {
1.1.1.2 root 3163: Uint32 regnum, value;
1.1 root 3164:
3165: value = (cur_inst >> 8) & BITMASK(8);
3166: regnum = cur_inst & BITMASK(2);
3167: switch(regnum) {
3168: case 0:
3169: /* mr */
1.1.1.6 root 3170: dsp_core.registers[DSP_REG_SR] |= value<<8;
1.1 root 3171: break;
3172: case 1:
3173: /* ccr */
1.1.1.6 root 3174: dsp_core.registers[DSP_REG_SR] |= value;
1.1 root 3175: break;
3176: case 2:
3177: /* omr */
1.1.1.6 root 3178: dsp_core.registers[DSP_REG_OMR] |= value;
1.1 root 3179: break;
3180: }
3181: }
3182:
1.1.1.3 root 3183: /*
3184: REP instruction parameter encoding
3185:
3186: xxxxxxxx 00xxxxxx 0xxxxxxx aa
3187: xxxxxxxx 01xxxxxx 0xxxxxxx ea
3188: xxxxxxxx YYxxxxxx 1xxxxxxx imm
3189: xxxxxxxx 11xxxxxx 0xxxxxxx reg
3190: */
3191:
3192: static void dsp_rep_aa(void)
1.1 root 3193: {
3194: /* x:aa */
3195: /* y:aa */
1.1.1.6 root 3196: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3197: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3198: dsp_core.loop_rep = 1; /* We are now running rep */
1.1 root 3199:
1.1.1.6 root 3200: dsp_core.registers[DSP_REG_LC]=read_memory((cur_inst>>6) & 1,(cur_inst>>8) & BITMASK(6));
1.1.1.4 root 3201:
1.1.1.6 root 3202: dsp_core.instr_cycle += 2;
1.1 root 3203: }
3204:
1.1.1.3 root 3205: static void dsp_rep_imm(void)
1.1 root 3206: {
3207: /* #xxx */
3208:
1.1.1.6 root 3209: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3210: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3211: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3212:
1.1.1.6 root 3213: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
1.1.1.3 root 3214: + ((cur_inst & BITMASK(4))<<8);
1.1.1.4 root 3215:
1.1.1.6 root 3216: dsp_core.instr_cycle += 2;
1.1 root 3217: }
3218:
1.1.1.3 root 3219: static void dsp_rep_ea(void)
1.1 root 3220: {
1.1.1.2 root 3221: Uint32 value;
1.1 root 3222:
3223: /* x:ea */
3224: /* y:ea */
3225:
1.1.1.6 root 3226: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3227: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3228: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3229:
1.1 root 3230: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&value);
1.1.1.6 root 3231: dsp_core.registers[DSP_REG_LC]= read_memory((cur_inst>>6) & 1, value);
1.1.1.4 root 3232:
1.1.1.6 root 3233: dsp_core.instr_cycle += 2;
1.1 root 3234: }
3235:
1.1.1.3 root 3236: static void dsp_rep_reg(void)
1.1 root 3237: {
1.1.1.2 root 3238: Uint32 numreg;
1.1 root 3239:
3240: /* R */
3241:
1.1.1.6 root 3242: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3243: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3244: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3245:
1.1 root 3246: numreg = (cur_inst>>8) & BITMASK(6);
3247: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.6 root 3248: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
1.1 root 3249: } else {
1.1.1.6 root 3250: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
1.1 root 3251: }
1.1.1.6 root 3252: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.4 root 3253:
1.1.1.6 root 3254: dsp_core.instr_cycle += 2;
1.1 root 3255: }
3256:
3257: static void dsp_reset(void)
3258: {
3259: /* Reset external peripherals */
1.1.1.6 root 3260: dsp_core.instr_cycle += 2;
1.1 root 3261: }
3262:
3263: static void dsp_rti(void)
3264: {
1.1.1.2 root 3265: Uint32 newpc = 0, newsr = 0;
1.1 root 3266:
3267: dsp_stack_pop(&newpc, &newsr);
1.1.1.6 root 3268: dsp_core.pc = newpc;
3269: dsp_core.registers[DSP_REG_SR] = newsr;
1.1 root 3270: cur_inst_len = 0;
1.1.1.4 root 3271:
1.1.1.6 root 3272: dsp_core.instr_cycle += 2;
1.1 root 3273: }
3274:
3275: static void dsp_rts(void)
3276: {
1.1.1.2 root 3277: Uint32 newpc = 0, newsr;
1.1 root 3278:
3279: dsp_stack_pop(&newpc, &newsr);
1.1.1.6 root 3280: dsp_core.pc = newpc;
1.1 root 3281: cur_inst_len = 0;
1.1.1.4 root 3282:
1.1.1.6 root 3283: dsp_core.instr_cycle += 2;
1.1 root 3284: }
3285:
3286: static void dsp_stop(void)
3287: {
1.1.1.6 root 3288: LOG_TRACE(TRACE_DSP_STATE, "Dsp: STOP instruction\n");
1.1 root 3289: }
3290:
3291: static void dsp_swi(void)
3292: {
3293: /* Raise interrupt p:0x0006 */
1.1.1.6 root 3294: dsp_core.instr_cycle += 6;
1.1 root 3295: }
3296:
3297: static void dsp_tcc(void)
3298: {
1.1.1.6 root 3299: Uint32 cc_code, regsrc1, regdest1;
1.1.1.2 root 3300: Uint32 regsrc2, regdest2;
1.1.1.6 root 3301: Uint32 val0, val1, val2;
3302:
1.1 root 3303: cc_code = (cur_inst>>12) & BITMASK(4);
3304:
3305: if (dsp_calc_cc(cc_code)) {
3306: regsrc1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][0];
1.1.1.2 root 3307: regdest1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][1];
1.1 root 3308:
3309: /* Read S1 */
1.1.1.7 root 3310: if (regsrc1 == DSP_REG_A) {
3311: val0 = dsp_core.registers[DSP_REG_A0];
3312: val1 = dsp_core.registers[DSP_REG_A1];
3313: val2 = dsp_core.registers[DSP_REG_A2];
3314: }
3315: else if (regsrc1 == DSP_REG_B) {
3316: val0 = dsp_core.registers[DSP_REG_B0];
3317: val1 = dsp_core.registers[DSP_REG_B1];
3318: val2 = dsp_core.registers[DSP_REG_B2];
3319: }
3320: else {
1.1.1.6 root 3321: val0 = 0;
3322: val1 = dsp_core.registers[regsrc1];
1.1.1.7 root 3323: val2 = val1 & (1<<23) ? 0xff : 0x0;
1.1 root 3324: }
3325:
3326: /* Write D1 */
1.1.1.7 root 3327: if (regdest1 == DSP_REG_A) {
3328: dsp_core.registers[DSP_REG_A2] = val2;
3329: dsp_core.registers[DSP_REG_A1] = val1;
3330: dsp_core.registers[DSP_REG_A0] = val0;
3331: }
3332: else {
3333: dsp_core.registers[DSP_REG_B2] = val2;
3334: dsp_core.registers[DSP_REG_B1] = val1;
3335: dsp_core.registers[DSP_REG_B0] = val0;
3336: }
1.1 root 3337:
3338: /* S2,D2 transfer */
3339: if (cur_inst & (1<<16)) {
1.1.1.2 root 3340: regsrc2 = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3341: regdest2 = DSP_REG_R0+(cur_inst & BITMASK(3));
1.1 root 3342:
1.1.1.6 root 3343: dsp_core.registers[regdest2] = dsp_core.registers[regsrc2];
1.1 root 3344: }
3345: }
3346: }
3347:
3348: static void dsp_wait(void)
3349: {
1.1.1.6 root 3350: LOG_TRACE(TRACE_DSP_STATE, "Dsp: WAIT instruction\n");
1.1 root 3351: }
3352:
1.1.1.2 root 3353: static int dsp_pm_read_accu24(int numreg, Uint32 *dest)
1.1 root 3354: {
1.1.1.4 root 3355: Uint32 scaling, value, reg;
1.1.1.7 root 3356: int got_limited = 0;
1.1 root 3357:
3358: /* Read an accumulator, stores it limited */
3359:
1.1.1.6 root 3360: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
1.1.1.4 root 3361: reg = numreg & 1;
1.1 root 3362:
1.1.1.6 root 3363: value = (dsp_core.registers[DSP_REG_A2+reg]) << 24;
3364: value += dsp_core.registers[DSP_REG_A1+reg];
1.1 root 3365:
3366: switch(scaling) {
3367: case 0:
1.1.1.4 root 3368: /* No scaling */
3369: break;
3370: case 1:
3371: /* scaling down */
3372: value >>= 1;
1.1 root 3373: break;
3374: case 2:
1.1.1.4 root 3375: /* scaling up */
3376: value <<= 1;
1.1.1.6 root 3377: value |= (dsp_core.registers[DSP_REG_A0+reg]>>23) & 1;
1.1 root 3378: break;
1.1.1.4 root 3379: /* indeterminate */
3380: case 3:
3381: break;
3382: }
3383:
3384: /* limiting ? */
3385: value &= BITMASK(24);
3386:
1.1.1.6 root 3387: if (dsp_core.registers[DSP_REG_A2+reg] == 0) {
1.1.1.4 root 3388: if (value <= 0x007fffff) {
3389: /* No limiting */
3390: *dest=value;
3391: return 0;
3392: }
3393: }
3394:
1.1.1.6 root 3395: if (dsp_core.registers[DSP_REG_A2+reg] == 0xff) {
1.1.1.4 root 3396: if (value >= 0x00800000) {
3397: /* No limiting */
3398: *dest=value;
3399: return 0;
3400: }
1.1 root 3401: }
3402:
1.1.1.6 root 3403: if (dsp_core.registers[DSP_REG_A2+reg] & (1<<7)) {
1.1 root 3404: /* Limited to maximum negative value */
3405: *dest=0x00800000;
1.1.1.6 root 3406: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
1.1.1.2 root 3407: got_limited=1;
1.1 root 3408: } else {
3409: /* Limited to maximal positive value */
3410: *dest=0x007fffff;
1.1.1.6 root 3411: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
1.1.1.2 root 3412: got_limited=1;
1.1 root 3413: }
1.1.1.2 root 3414:
3415: return got_limited;
1.1 root 3416: }
3417:
3418: static void dsp_pm_0(void)
3419: {
1.1.1.6 root 3420: Uint32 memspace, numreg, addr, save_accu, save_xy0;
1.1 root 3421: /*
3422: 0000 100d 00mm mrrr S,x:ea x0,D
3423: 0000 100d 10mm mrrr S,y:ea y0,D
3424: */
3425: memspace = (cur_inst>>15) & 1;
3426: numreg = (cur_inst>>16) & 1;
1.1.1.6 root 3427: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &addr);
3428:
3429: /* Save A or B */
3430: dsp_pm_read_accu24(numreg, &save_accu);
1.1 root 3431:
1.1.1.6 root 3432: /* Save X0 or Y0 */
3433: save_xy0 = dsp_core.registers[DSP_REG_X0+(memspace<<1)];
3434:
3435: /* Execute parallel instruction */
3436: opcodes_alu[cur_inst & BITMASK(8)]();
3437:
3438: /* Move [A|B] to [x|y]:ea */
3439: write_memory(memspace, addr, save_accu);
3440:
3441: /* Move [x|y]0 to [A|B] */
3442: dsp_core.registers[DSP_REG_A0+numreg] = 0;
3443: dsp_core.registers[DSP_REG_A1+numreg] = save_xy0;
1.1.1.7 root 3444: dsp_core.registers[DSP_REG_A2+numreg] = save_xy0 & (1<<23) ? 0xff : 0x0;
1.1 root 3445: }
3446:
3447: static void dsp_pm_1(void)
3448: {
1.1.1.6 root 3449: Uint32 memspace, numreg1, numreg2, value, xy_addr, retour, save_1, save_2;
1.1 root 3450: /*
3451: 0001 ffdf w0mm mrrr x:ea,D1 S2,D2
3452: S1,x:ea S2,D2
3453: #xxxxxx,D1 S2,D2
3454: 0001 deff w1mm mrrr S1,D1 y:ea,D2
3455: S1,D1 S2,y:ea
3456: S1,D1 #xxxxxx,D2
3457: */
3458: value = (cur_inst>>8) & BITMASK(6);
3459: retour = dsp_calc_ea(value, &xy_addr);
3460: memspace = (cur_inst>>14) & 1;
1.1.1.6 root 3461: numreg1 = numreg2 = DSP_REG_NULL;
1.1 root 3462:
3463: if (memspace) {
3464: /* Y: */
3465: switch((cur_inst>>16) & BITMASK(2)) {
1.1.1.6 root 3466: case 0: numreg1 = DSP_REG_Y0; break;
3467: case 1: numreg1 = DSP_REG_Y1; break;
3468: case 2: numreg1 = DSP_REG_A; break;
3469: case 3: numreg1 = DSP_REG_B; break;
1.1 root 3470: }
3471: } else {
3472: /* X: */
3473: switch((cur_inst>>18) & BITMASK(2)) {
1.1.1.6 root 3474: case 0: numreg1 = DSP_REG_X0; break;
3475: case 1: numreg1 = DSP_REG_X1; break;
3476: case 2: numreg1 = DSP_REG_A; break;
3477: case 3: numreg1 = DSP_REG_B; break;
1.1 root 3478: }
3479: }
3480:
3481: if (cur_inst & (1<<15)) {
3482: /* Write D1 */
1.1.1.6 root 3483: if (retour)
3484: save_1 = xy_addr;
3485: else
3486: save_1 = read_memory(memspace, xy_addr);
1.1 root 3487: } else {
3488: /* Read S1 */
1.1.1.6 root 3489: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
3490: dsp_pm_read_accu24(numreg1, &save_1);
3491: else
3492: save_1 = dsp_core.registers[numreg1];
1.1 root 3493: }
1.1.1.6 root 3494:
1.1 root 3495: /* S2 */
3496: if (memspace) {
3497: /* Y: */
1.1.1.6 root 3498: numreg2 = DSP_REG_A + ((cur_inst>>19) & 1);
1.1 root 3499: } else {
3500: /* X: */
1.1.1.6 root 3501: numreg2 = DSP_REG_A + ((cur_inst>>17) & 1);
1.1 root 3502: }
1.1.1.6 root 3503: dsp_pm_read_accu24(numreg2, &save_2);
1.1 root 3504:
1.1.1.6 root 3505:
3506: /* Execute parallel instruction */
3507: opcodes_alu[cur_inst & BITMASK(8)]();
3508:
3509:
3510: /* Write parallel move values */
3511: if (cur_inst & (1<<15)) {
3512: /* Write D1 */
3513: if (numreg1 == DSP_REG_A) {
3514: dsp_core.registers[DSP_REG_A0] = 0x0;
3515: dsp_core.registers[DSP_REG_A1] = save_1;
3516: dsp_core.registers[DSP_REG_A2] = save_1 & (1<<23) ? 0xff : 0x0;
3517: }
3518: else if (numreg1 == DSP_REG_B) {
3519: dsp_core.registers[DSP_REG_B0] = 0x0;
3520: dsp_core.registers[DSP_REG_B1] = save_1;
3521: dsp_core.registers[DSP_REG_B2] = save_1 & (1<<23) ? 0xff : 0x0;
3522: }
3523: else {
3524: } dsp_core.registers[numreg1] = save_1;
3525: } else {
3526: /* Read S1 */
3527: write_memory(memspace, xy_addr, save_1);
3528: }
3529:
3530: /* S2 -> D2 */
1.1 root 3531: if (memspace) {
3532: /* Y: */
1.1.1.6 root 3533: numreg2 = DSP_REG_X0 + ((cur_inst>>18) & 1);
1.1 root 3534: } else {
3535: /* X: */
1.1.1.6 root 3536: numreg2 = DSP_REG_Y0 + ((cur_inst>>16) & 1);
1.1 root 3537: }
1.1.1.6 root 3538: dsp_core.registers[numreg2] = save_2;
1.1 root 3539: }
3540:
3541: static void dsp_pm_2(void)
3542: {
1.1.1.2 root 3543: Uint32 dummy;
1.1 root 3544: /*
3545: 0010 0000 0000 0000 nop
3546: 0010 0000 010m mrrr R update
3547: 0010 00ee eeed dddd S,D
3548: 001d dddd iiii iiii #xx,D
3549: */
1.1.1.4 root 3550: if ((cur_inst & 0xffff00) == 0x200000) {
1.1.1.6 root 3551: /* Execute parallel instruction */
3552: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3553: return;
3554: }
3555:
1.1.1.4 root 3556: if ((cur_inst & 0xffe000) == 0x204000) {
1.1 root 3557: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &dummy);
1.1.1.6 root 3558: /* Execute parallel instruction */
3559: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3560: return;
3561: }
3562:
1.1.1.4 root 3563: if ((cur_inst & 0xfc0000) == 0x200000) {
1.1 root 3564: dsp_pm_2_2();
3565: return;
3566: }
3567:
3568: dsp_pm_3();
3569: }
3570:
3571: static void dsp_pm_2_2(void)
3572: {
3573: /*
3574: 0010 00ee eeed dddd S,D
3575: */
1.1.1.6 root 3576: Uint32 srcreg, dstreg, save_reg;
1.1 root 3577:
3578: srcreg = (cur_inst >> 13) & BITMASK(5);
3579: dstreg = (cur_inst >> 8) & BITMASK(5);
3580:
1.1.1.6 root 3581: if ((srcreg == DSP_REG_A) || (srcreg == DSP_REG_B))
3582: /* Accu to register: limited 24 bits */
3583: dsp_pm_read_accu24(srcreg, &save_reg);
3584: else
3585: save_reg = dsp_core.registers[srcreg];
3586:
3587: /* Execute parallel instruction */
3588: opcodes_alu[cur_inst & BITMASK(8)]();
3589:
3590: /* Write reg */
3591: if (dstreg == DSP_REG_A) {
3592: dsp_core.registers[DSP_REG_A0] = 0x0;
3593: dsp_core.registers[DSP_REG_A1] = save_reg;
3594: dsp_core.registers[DSP_REG_A2] = save_reg & (1<<23) ? 0xff : 0x0;
3595: }
3596: else if (dstreg == DSP_REG_B) {
3597: dsp_core.registers[DSP_REG_B0] = 0x0;
3598: dsp_core.registers[DSP_REG_B1] = save_reg;
3599: dsp_core.registers[DSP_REG_B2] = save_reg & (1<<23) ? 0xff : 0x0;
3600: }
3601: else {
3602: dsp_core.registers[dstreg] = save_reg & BITMASK(registers_mask[dstreg]);
1.1 root 3603: }
3604: }
3605:
3606: static void dsp_pm_3(void)
3607: {
1.1.1.6 root 3608: Uint32 dstreg, srcvalue;
1.1 root 3609: /*
3610: 001d dddd iiii iiii #xx,R
3611: */
1.1.1.6 root 3612:
3613: /* Execute parallel instruction */
3614: opcodes_alu[cur_inst & BITMASK(8)]();
3615:
3616: /* Write reg */
3617: dstreg = (cur_inst >> 16) & BITMASK(5);
1.1 root 3618: srcvalue = (cur_inst >> 8) & BITMASK(8);
3619:
1.1.1.6 root 3620: switch(dstreg) {
1.1 root 3621: case DSP_REG_X0:
3622: case DSP_REG_X1:
3623: case DSP_REG_Y0:
3624: case DSP_REG_Y1:
3625: case DSP_REG_A:
3626: case DSP_REG_B:
3627: srcvalue <<= 16;
3628: break;
3629: }
3630:
1.1.1.6 root 3631: if (dstreg == DSP_REG_A) {
3632: dsp_core.registers[DSP_REG_A0] = 0x0;
3633: dsp_core.registers[DSP_REG_A1] = srcvalue;
3634: dsp_core.registers[DSP_REG_A2] = srcvalue & (1<<23) ? 0xff : 0x0;
3635: }
3636: else if (dstreg == DSP_REG_B) {
3637: dsp_core.registers[DSP_REG_B0] = 0x0;
3638: dsp_core.registers[DSP_REG_B1] = srcvalue;
3639: dsp_core.registers[DSP_REG_B2] = srcvalue & (1<<23) ? 0xff : 0x0;
3640: }
3641: else {
3642: dsp_core.registers[dstreg] = srcvalue & BITMASK(registers_mask[dstreg]);
1.1 root 3643: }
3644: }
3645:
3646: static void dsp_pm_4(void)
3647: {
3648: /*
1.1.1.4 root 3649: 0100 l0ll w0aa aaaa l:aa,D
1.1 root 3650: S,l:aa
1.1.1.4 root 3651: 0100 l0ll w1mm mrrr l:ea,D
1.1 root 3652: S,l:ea
1.1.1.4 root 3653: 01dd 0ddd w0aa aaaa x:aa,D
1.1 root 3654: S,x:aa
1.1.1.4 root 3655: 01dd 0ddd w1mm mrrr x:ea,D
1.1 root 3656: S,x:ea
3657: #xxxxxx,D
1.1.1.4 root 3658: 01dd 1ddd w0aa aaaa y:aa,D
1.1 root 3659: S,y:aa
1.1.1.4 root 3660: 01dd 1ddd w1mm mrrr y:ea,D
1.1 root 3661: S,y:ea
3662: #xxxxxx,D
3663: */
1.1.1.4 root 3664: if ((cur_inst & 0xf40000)==0x400000) {
3665: dsp_pm_4x();
1.1 root 3666: return;
3667: }
3668:
3669: dsp_pm_5();
3670: }
3671:
1.1.1.4 root 3672: static void dsp_pm_4x(void)
1.1 root 3673: {
1.1.1.6 root 3674: Uint32 value, numreg, l_addr, save_lx, save_ly;
1.1 root 3675: /*
1.1.1.4 root 3676: 0100 l0ll w0aa aaaa l:aa,D
3677: S,l:aa
3678: 0100 l0ll w1mm mrrr l:ea,D
3679: S,l:ea
1.1 root 3680: */
1.1.1.4 root 3681: value = (cur_inst>>8) & BITMASK(6);
3682: if (cur_inst & (1<<14)) {
3683: dsp_calc_ea(value, &l_addr);
3684: } else {
3685: l_addr = value;
3686: }
3687:
1.1 root 3688: numreg = (cur_inst>>16) & BITMASK(2);
3689: numreg |= (cur_inst>>17) & (1<<2);
3690:
1.1.1.4 root 3691: /* 2 more cycles are needed if address is in external memory */
3692: if (l_addr>=0x200) {
1.1.1.6 root 3693: dsp_core.instr_cycle += 2;
1.1.1.4 root 3694: }
3695:
1.1 root 3696: if (cur_inst & (1<<15)) {
3697: /* Write D */
1.1.1.6 root 3698: save_lx = read_memory(DSP_SPACE_X,l_addr);
3699: save_ly = read_memory(DSP_SPACE_Y,l_addr);
3700: }
3701: else {
3702: /* Read S */
1.1.1.4 root 3703: switch(numreg) {
3704: case 0:
3705: /* A10 */
1.1.1.6 root 3706: save_lx = dsp_core.registers[DSP_REG_A1];
3707: save_ly = dsp_core.registers[DSP_REG_A0];
1.1.1.4 root 3708: break;
3709: case 1:
3710: /* B10 */
1.1.1.6 root 3711: save_lx = dsp_core.registers[DSP_REG_B1];
3712: save_ly = dsp_core.registers[DSP_REG_B0];
1.1.1.4 root 3713: break;
3714: case 2:
3715: /* X */
1.1.1.6 root 3716: save_lx = dsp_core.registers[DSP_REG_X1];
3717: save_ly = dsp_core.registers[DSP_REG_X0];
1.1.1.4 root 3718: break;
3719: case 3:
3720: /* Y */
1.1.1.6 root 3721: save_lx = dsp_core.registers[DSP_REG_Y1];
3722: save_ly = dsp_core.registers[DSP_REG_Y0];
1.1.1.4 root 3723: break;
3724: case 4:
3725: /* A */
1.1.1.6 root 3726: if (dsp_pm_read_accu24(DSP_REG_A, &save_lx)) {
3727: /* Was limited, set lower part */
3728: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3729: } else {
3730: /* Not limited */
3731: save_ly = dsp_core.registers[DSP_REG_A0];
3732: }
1.1.1.4 root 3733: break;
3734: case 5:
3735: /* B */
1.1.1.6 root 3736: if (dsp_pm_read_accu24(DSP_REG_B, &save_lx)) {
3737: /* Was limited, set lower part */
3738: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3739: } else {
3740: /* Not limited */
3741: save_ly = dsp_core.registers[DSP_REG_B0];
3742: }
1.1.1.4 root 3743: break;
3744: case 6:
3745: /* AB */
1.1.1.6 root 3746: dsp_pm_read_accu24(DSP_REG_A, &save_lx);
3747: dsp_pm_read_accu24(DSP_REG_B, &save_ly);
1.1.1.4 root 3748: break;
3749: case 7:
3750: /* BA */
1.1.1.6 root 3751: dsp_pm_read_accu24(DSP_REG_B, &save_lx);
3752: dsp_pm_read_accu24(DSP_REG_A, &save_ly);
1.1.1.4 root 3753: break;
1.1 root 3754: }
1.1.1.6 root 3755: }
1.1 root 3756:
1.1.1.6 root 3757: /* Execute parallel instruction */
3758: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3759:
1.1.1.6 root 3760:
3761: if (cur_inst & (1<<15)) {
3762: /* Write D */
1.1.1.4 root 3763: switch(numreg) {
1.1.1.6 root 3764: case 0: /* A10 */
3765: dsp_core.registers[DSP_REG_A1] = save_lx;
3766: dsp_core.registers[DSP_REG_A0] = save_ly;
1.1.1.4 root 3767: break;
1.1.1.6 root 3768: case 1: /* B10 */
3769: dsp_core.registers[DSP_REG_B1] = save_lx;
3770: dsp_core.registers[DSP_REG_B0] = save_ly;
1.1.1.4 root 3771: break;
1.1.1.6 root 3772: case 2: /* X */
3773: dsp_core.registers[DSP_REG_X1] = save_lx;
3774: dsp_core.registers[DSP_REG_X0] = save_ly;
1.1.1.4 root 3775: break;
1.1.1.6 root 3776: case 3: /* Y */
3777: dsp_core.registers[DSP_REG_Y1] = save_lx;
3778: dsp_core.registers[DSP_REG_Y0] = save_ly;
1.1.1.4 root 3779: break;
1.1.1.6 root 3780: case 4: /* A */
3781: dsp_core.registers[DSP_REG_A0] = save_ly;
3782: dsp_core.registers[DSP_REG_A1] = save_lx;
3783: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
1.1.1.4 root 3784: break;
1.1.1.6 root 3785: case 5: /* B */
3786: dsp_core.registers[DSP_REG_B0] = save_ly;
3787: dsp_core.registers[DSP_REG_B1] = save_lx;
3788: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
1.1.1.4 root 3789: break;
1.1.1.6 root 3790: case 6: /* AB */
3791: dsp_core.registers[DSP_REG_A0] = 0;
3792: dsp_core.registers[DSP_REG_A1] = save_lx;
3793: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
3794: dsp_core.registers[DSP_REG_B0] = 0;
3795: dsp_core.registers[DSP_REG_B1] = save_ly;
3796: dsp_core.registers[DSP_REG_B2] = save_ly & (1<<23) ? 0xff : 0;
1.1.1.4 root 3797: break;
1.1.1.6 root 3798: case 7: /* BA */
3799: dsp_core.registers[DSP_REG_B0] = 0;
3800: dsp_core.registers[DSP_REG_B1] = save_lx;
3801: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
3802: dsp_core.registers[DSP_REG_A0] = 0;
3803: dsp_core.registers[DSP_REG_A1] = save_ly;
3804: dsp_core.registers[DSP_REG_A2] = save_ly & (1<<23) ? 0xff : 0;
1.1.1.4 root 3805: break;
1.1 root 3806: }
1.1.1.6 root 3807: }
3808: else {
3809: /* Read S */
3810: write_memory(DSP_SPACE_X, l_addr, save_lx);
3811: write_memory(DSP_SPACE_Y, l_addr, save_ly);
1.1 root 3812: }
3813: }
3814:
3815: static void dsp_pm_5(void)
3816: {
1.1.1.2 root 3817: Uint32 memspace, numreg, value, xy_addr, retour;
1.1 root 3818: /*
1.1.1.4 root 3819: 01dd 0ddd w0aa aaaa x:aa,D
1.1 root 3820: S,x:aa
1.1.1.4 root 3821: 01dd 0ddd w1mm mrrr x:ea,D
1.1 root 3822: S,x:ea
3823: #xxxxxx,D
1.1.1.4 root 3824: 01dd 1ddd w0aa aaaa y:aa,D
1.1 root 3825: S,y:aa
1.1.1.4 root 3826: 01dd 1ddd w1mm mrrr y:ea,D
1.1 root 3827: S,y:ea
3828: #xxxxxx,D
3829: */
3830:
3831: value = (cur_inst>>8) & BITMASK(6);
3832:
3833: if (cur_inst & (1<<14)) {
3834: retour = dsp_calc_ea(value, &xy_addr);
3835: } else {
3836: xy_addr = value;
3837: retour = 0;
3838: }
3839:
3840: memspace = (cur_inst>>19) & 1;
3841: numreg = (cur_inst>>16) & BITMASK(3);
3842: numreg |= (cur_inst>>17) & (BITMASK(2)<<3);
3843:
3844: if (cur_inst & (1<<15)) {
3845: /* Write D */
1.1.1.6 root 3846: if (retour)
1.1 root 3847: value = xy_addr;
1.1.1.6 root 3848: else
1.1 root 3849: value = read_memory(memspace, xy_addr);
1.1.1.6 root 3850: }
3851: else {
1.1 root 3852: /* Read S */
1.1.1.6 root 3853: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B))
3854: dsp_pm_read_accu24(numreg, &value);
3855: else
3856: value = dsp_core.registers[numreg];
3857: }
1.1 root 3858:
3859:
1.1.1.6 root 3860: /* Execute parallel instruction */
3861: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3862:
1.1.1.6 root 3863: if (cur_inst & (1<<15)) {
3864: /* Write D */
3865: if (numreg == DSP_REG_A) {
3866: dsp_core.registers[DSP_REG_A0] = 0x0;
3867: dsp_core.registers[DSP_REG_A1] = value;
3868: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
3869: }
3870: else if (numreg == DSP_REG_B) {
3871: dsp_core.registers[DSP_REG_B0] = 0x0;
3872: dsp_core.registers[DSP_REG_B1] = value;
3873: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
3874: }
3875: else {
3876: dsp_core.registers[numreg] = value & BITMASK(registers_mask[numreg]);
3877: }
3878: }
3879: else {
1.1.1.7 root 3880: /* Read S */
1.1.1.6 root 3881: write_memory(memspace, xy_addr, value);
1.1 root 3882: }
3883: }
3884:
3885: static void dsp_pm_8(void)
3886: {
1.1.1.2 root 3887: Uint32 ea1, ea2;
3888: Uint32 numreg1, numreg2;
1.1.1.6 root 3889: Uint32 save_reg1, save_reg2, x_addr, y_addr;
1.1 root 3890: /*
1.1.1.4 root 3891: 1wmm eeff WrrM MRRR x:ea,D1 y:ea,D2
1.1 root 3892: x:ea,D1 S2,y:ea
3893: S1,x:ea y:ea,D2
3894: S1,x:ea S2,y:ea
3895: */
3896: numreg1 = numreg2 = DSP_REG_NULL;
3897:
3898: ea1 = (cur_inst>>8) & BITMASK(5);
3899: if ((ea1>>3) == 0) {
3900: ea1 |= (1<<5);
3901: }
3902: ea2 = (cur_inst>>13) & BITMASK(2);
3903: ea2 |= (cur_inst>>17) & (BITMASK(2)<<3);
3904: if ((ea1 & (1<<2))==0) {
3905: ea2 |= 1<<2;
3906: }
3907: if ((ea2>>3) == 0) {
3908: ea2 |= (1<<5);
3909: }
3910:
1.1.1.4 root 3911: dsp_calc_ea(ea1, &x_addr);
3912: dsp_calc_ea(ea2, &y_addr);
3913:
3914: /* 2 more cycles are needed if X:address1 and Y:address2 are both in external memory */
3915: if ((x_addr>=0x200) && (y_addr>=0x200)) {
1.1.1.6 root 3916: dsp_core.instr_cycle += 2;
1.1.1.4 root 3917: }
1.1 root 3918:
3919: switch((cur_inst>>18) & BITMASK(2)) {
3920: case 0: numreg1=DSP_REG_X0; break;
3921: case 1: numreg1=DSP_REG_X1; break;
3922: case 2: numreg1=DSP_REG_A; break;
3923: case 3: numreg1=DSP_REG_B; break;
3924: }
3925: switch((cur_inst>>16) & BITMASK(2)) {
3926: case 0: numreg2=DSP_REG_Y0; break;
3927: case 1: numreg2=DSP_REG_Y1; break;
3928: case 2: numreg2=DSP_REG_A; break;
3929: case 3: numreg2=DSP_REG_B; break;
3930: }
3931:
3932: if (cur_inst & (1<<15)) {
3933: /* Write D1 */
1.1.1.6 root 3934: save_reg1 = read_memory(DSP_SPACE_X, x_addr);
1.1 root 3935: } else {
3936: /* Read S1 */
1.1.1.6 root 3937: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
3938: dsp_pm_read_accu24(numreg1, &save_reg1);
3939: else
3940: save_reg1 = dsp_core.registers[numreg1];
1.1 root 3941: }
3942:
3943: if (cur_inst & (1<<22)) {
3944: /* Write D2 */
1.1.1.6 root 3945: save_reg2 = read_memory(DSP_SPACE_Y, y_addr);
1.1 root 3946: } else {
3947: /* Read S2 */
1.1.1.6 root 3948: if ((numreg2==DSP_REG_A) || (numreg2==DSP_REG_B))
3949: dsp_pm_read_accu24(numreg2, &save_reg2);
3950: else
3951: save_reg2 = dsp_core.registers[numreg2];
1.1 root 3952: }
3953:
3954:
1.1.1.6 root 3955: /* Execute parallel instruction */
3956: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3957:
1.1.1.6 root 3958: /* Write first parallel move */
3959: if (cur_inst & (1<<15)) {
3960: /* Write D1 */
3961: if (numreg1 == DSP_REG_A) {
3962: dsp_core.registers[DSP_REG_A0] = 0x0;
3963: dsp_core.registers[DSP_REG_A1] = save_reg1;
3964: dsp_core.registers[DSP_REG_A2] = save_reg1 & (1<<23) ? 0xff : 0x0;
3965: }
3966: else if (numreg1 == DSP_REG_B) {
3967: dsp_core.registers[DSP_REG_B0] = 0x0;
3968: dsp_core.registers[DSP_REG_B1] = save_reg1;
3969: dsp_core.registers[DSP_REG_B2] = save_reg1 & (1<<23) ? 0xff : 0x0;
3970: }
3971: else {
3972: dsp_core.registers[numreg1] = save_reg1;
3973: }
3974: } else {
3975: /* Read S1 */
3976: write_memory(DSP_SPACE_X, x_addr, save_reg1);
3977: }
3978:
3979: /* Write second parallel move */
3980: if (cur_inst & (1<<22)) {
3981: /* Write D2 */
3982: if (numreg2 == DSP_REG_A) {
3983: dsp_core.registers[DSP_REG_A0] = 0x0;
3984: dsp_core.registers[DSP_REG_A1] = save_reg2;
3985: dsp_core.registers[DSP_REG_A2] = save_reg2 & (1<<23) ? 0xff : 0x0;
3986: }
3987: else if (numreg2 == DSP_REG_B) {
3988: dsp_core.registers[DSP_REG_B0] = 0x0;
3989: dsp_core.registers[DSP_REG_B1] = save_reg2;
3990: dsp_core.registers[DSP_REG_B2] = save_reg2 & (1<<23) ? 0xff : 0x0;
3991: }
3992: else {
3993: dsp_core.registers[numreg2] = save_reg2;
3994: }
3995: } else {
3996: /* Read S2 */
3997: write_memory(DSP_SPACE_Y, y_addr, save_reg2);
3998: }
3999: }
4000:
4001: /**********************************
4002: * 56bit arithmetic
4003: **********************************/
4004:
4005: /* source,dest[0] is 55:48 */
4006: /* source,dest[1] is 47:24 */
4007: /* source,dest[2] is 23:00 */
4008:
4009: static Uint16 dsp_abs56(Uint32 *dest)
1.1 root 4010: {
1.1.1.2 root 4011: Uint32 zerodest[3];
4012: Uint16 newsr;
1.1 root 4013:
4014: /* D=|D| */
4015:
4016: if (dest[0] & (1<<7)) {
4017: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4018:
4019: newsr = dsp_sub56(dest, zerodest);
4020:
4021: dest[0] = zerodest[0];
4022: dest[1] = zerodest[1];
4023: dest[2] = zerodest[2];
4024: } else {
4025: newsr = 0;
4026: }
4027:
4028: return newsr;
4029: }
4030:
1.1.1.2 root 4031: static Uint16 dsp_asl56(Uint32 *dest)
1.1 root 4032: {
1.1.1.2 root 4033: Uint16 overflow, carry;
1.1 root 4034:
4035: /* Shift left dest 1 bit: D<<=1 */
4036:
4037: carry = (dest[0]>>7) & 1;
4038:
4039: dest[0] <<= 1;
4040: dest[0] |= (dest[1]>>23) & 1;
4041: dest[0] &= BITMASK(8);
4042:
4043: dest[1] <<= 1;
4044: dest[1] |= (dest[2]>>23) & 1;
4045: dest[1] &= BITMASK(24);
4046:
4047: dest[2] <<= 1;
4048: dest[2] &= BITMASK(24);
4049:
4050: overflow = (carry != ((dest[0]>>7) & 1));
4051:
4052: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4053: }
4054:
1.1.1.2 root 4055: static Uint16 dsp_asr56(Uint32 *dest)
1.1 root 4056: {
1.1.1.2 root 4057: Uint16 carry;
1.1 root 4058:
4059: /* Shift right dest 1 bit: D>>=1 */
4060:
4061: carry = dest[2] & 1;
4062:
4063: dest[2] >>= 1;
4064: dest[2] |= (dest[1] & 1)<<23;
4065:
4066: dest[1] >>= 1;
4067: dest[1] |= (dest[0] & 1)<<23;
4068:
4069: dest[0] >>= 1;
4070: dest[0] |= (dest[0] & (1<<6))<<1;
4071:
4072: return (carry<<DSP_SR_C);
4073: }
4074:
1.1.1.2 root 4075: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest)
1.1 root 4076: {
1.1.1.4 root 4077: Uint16 overflow, carry, flg_s, flg_d, flg_r;
4078:
4079: flg_s = (source[0]>>7) & 1;
4080: flg_d = (dest[0]>>7) & 1;
4081:
1.1 root 4082: /* Add source to dest: D = D+S */
1.1.1.2 root 4083: dest[2] += source[2];
4084: dest[1] += source[1]+((dest[2]>>24) & 1);
4085: dest[0] += source[0]+((dest[1]>>24) & 1);
1.1 root 4086:
1.1.1.5 root 4087: carry = (dest[0]>>8) & 1;
4088:
1.1 root 4089: dest[2] &= BITMASK(24);
4090: dest[1] &= BITMASK(24);
4091: dest[0] &= BITMASK(8);
4092:
1.1.1.4 root 4093: flg_r = (dest[0]>>7) & 1;
4094:
4095: /*set overflow*/
4096: overflow = (flg_s ^ flg_r) & (flg_d ^ flg_r);
4097:
1.1 root 4098: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4099: }
4100:
1.1.1.2 root 4101: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest)
1.1 root 4102: {
1.1.1.5 root 4103: Uint16 overflow, carry, flg_s, flg_d, flg_r, dest_save;
1.1.1.4 root 4104:
1.1.1.5 root 4105: dest_save = dest[0];
1.1 root 4106:
4107: /* Substract source from dest: D = D-S */
1.1.1.2 root 4108: dest[2] -= source[2];
4109: dest[1] -= source[1]+((dest[2]>>24) & 1);
4110: dest[0] -= source[0]+((dest[1]>>24) & 1);
1.1 root 4111:
1.1.1.5 root 4112: carry = (dest[0]>>8) & 1;
4113:
1.1 root 4114: dest[2] &= BITMASK(24);
4115: dest[1] &= BITMASK(24);
4116: dest[0] &= BITMASK(8);
4117:
1.1.1.4 root 4118: flg_s = (source[0]>>7) & 1;
1.1.1.5 root 4119: flg_d = (dest_save>>7) & 1;
1.1.1.4 root 4120: flg_r = (dest[0]>>7) & 1;
4121:
4122: /* set overflow */
4123: overflow = (flg_s ^ flg_d) & (flg_r ^ flg_d);
4124:
1.1 root 4125: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4126: }
4127:
1.1.1.5 root 4128: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe)
1.1 root 4129: {
1.1.1.2 root 4130: Uint32 part[4], zerodest[3], value;
1.1 root 4131:
4132: /* Multiply: D = S1*S2 */
4133: if (source1 & (1<<23)) {
1.1.1.5 root 4134: signe ^= 1;
1.1.1.6 root 4135: source1 = (1<<24) - source1;
1.1 root 4136: }
4137: if (source2 & (1<<23)) {
1.1.1.5 root 4138: signe ^= 1;
1.1.1.6 root 4139: source2 = (1<<24) - source2;
1.1 root 4140: }
4141:
4142: /* bits 0-11 * bits 0-11 */
4143: part[0]=(source1 & BITMASK(12))*(source2 & BITMASK(12));
4144: /* bits 12-23 * bits 0-11 */
4145: part[1]=((source1>>12) & BITMASK(12))*(source2 & BITMASK(12));
4146: /* bits 0-11 * bits 12-23 */
4147: part[2]=(source1 & BITMASK(12))*((source2>>12) & BITMASK(12));
4148: /* bits 12-23 * bits 12-23 */
4149: part[3]=((source1>>12) & BITMASK(12))*((source2>>12) & BITMASK(12));
4150:
4151: /* Calc dest 2 */
4152: dest[2] = part[0];
4153: dest[2] += (part[1] & BITMASK(12)) << 12;
4154: dest[2] += (part[2] & BITMASK(12)) << 12;
4155:
4156: /* Calc dest 1 */
4157: dest[1] = (part[1]>>12) & BITMASK(12);
4158: dest[1] += (part[2]>>12) & BITMASK(12);
4159: dest[1] += part[3];
4160:
4161: /* Calc dest 0 */
4162: dest[0] = 0;
4163:
4164: /* Add carries */
4165: value = (dest[2]>>24) & BITMASK(8);
4166: if (value) {
4167: dest[1] += value;
4168: dest[2] &= BITMASK(24);
4169: }
4170: value = (dest[1]>>24) & BITMASK(8);
4171: if (value) {
4172: dest[0] += value;
4173: dest[1] &= BITMASK(24);
4174: }
4175:
4176: /* Get rid of extra sign bit */
4177: dsp_asl56(dest);
4178:
1.1.1.5 root 4179: if (signe) {
1.1 root 4180: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4181:
4182: dsp_sub56(dest, zerodest);
4183:
4184: dest[0] = zerodest[0];
4185: dest[1] = zerodest[1];
4186: dest[2] = zerodest[2];
4187: }
4188: }
4189:
1.1.1.2 root 4190: static void dsp_rnd56(Uint32 *dest)
1.1 root 4191: {
1.1.1.4 root 4192: Uint32 rnd_const[3];
1.1 root 4193:
1.1.1.4 root 4194: rnd_const[0] = 0;
1.1 root 4195:
1.1.1.4 root 4196: /* Scaling mode S0 */
1.1.1.6 root 4197: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S0)) {
1.1.1.4 root 4198: rnd_const[1] = 1;
4199: rnd_const[2] = 0;
4200: dsp_add56(rnd_const, dest);
4201:
4202: if ((dest[2]==0) && ((dest[1] & 1) == 0)) {
4203: dest[1] &= (0xffffff - 0x3);
4204: }
4205: dest[1] &= 0xfffffe;
4206: dest[2]=0;
4207: }
4208: /* Scaling mode S1 */
1.1.1.6 root 4209: else if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S1)) {
1.1.1.4 root 4210: rnd_const[1] = 0;
4211: rnd_const[2] = (1<<22);
4212: dsp_add56(rnd_const, dest);
4213:
4214: if ((dest[2] & 0x7fffff) == 0){
4215: dest[2] = 0;
4216: }
4217: dest[2] &= 0x800000;
4218: }
4219: /* No Scaling */
4220: else {
4221: rnd_const[1] = 0;
4222: rnd_const[2] = (1<<23);
4223: dsp_add56(rnd_const, dest);
4224:
4225: if (dest[2] == 0) {
4226: dest[1] &= 0xfffffe;
1.1 root 4227: }
1.1.1.4 root 4228: dest[2]=0;
1.1 root 4229: }
4230: }
4231:
4232: /**********************************
4233: * Parallel moves instructions
4234: **********************************/
4235:
1.1.1.6 root 4236: static void dsp_abs_a(void)
1.1 root 4237: {
1.1.1.6 root 4238: Uint32 dest[3], overflowed;
1.1 root 4239:
1.1.1.6 root 4240: dest[0] = dsp_core.registers[DSP_REG_A2];
4241: dest[1] = dsp_core.registers[DSP_REG_A1];
4242: dest[2] = dsp_core.registers[DSP_REG_A0];
4243:
4244: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4245:
4246: dsp_abs56(dest);
4247:
4248: dsp_core.registers[DSP_REG_A2] = dest[0];
4249: dsp_core.registers[DSP_REG_A1] = dest[1];
4250: dsp_core.registers[DSP_REG_A0] = dest[2];
4251:
4252: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4253: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
4254:
4255: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4256: }
4257:
4258: static void dsp_abs_b(void)
4259: {
4260: Uint32 dest[3], overflowed;
1.1 root 4261:
1.1.1.6 root 4262: dest[0] = dsp_core.registers[DSP_REG_B2];
4263: dest[1] = dsp_core.registers[DSP_REG_B1];
4264: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 4265:
4266: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4267:
4268: dsp_abs56(dest);
4269:
1.1.1.6 root 4270: dsp_core.registers[DSP_REG_B2] = dest[0];
4271: dsp_core.registers[DSP_REG_B1] = dest[1];
4272: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4273:
1.1.1.6 root 4274: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4275: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
1.1.1.2 root 4276:
1.1.1.6 root 4277: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4278: }
4279:
1.1.1.6 root 4280: static void dsp_adc_x_a(void)
1.1 root 4281: {
1.1.1.6 root 4282: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4283: Uint16 newsr;
1.1 root 4284:
1.1.1.6 root 4285: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4286:
1.1.1.6 root 4287: dest[0] = dsp_core.registers[DSP_REG_A2];
4288: dest[1] = dsp_core.registers[DSP_REG_A1];
4289: dest[2] = dsp_core.registers[DSP_REG_A0];
4290:
4291: source[2] = dsp_core.registers[DSP_REG_X0];
4292: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4293: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4294:
4295: newsr = dsp_add56(source, dest);
4296:
4297: if (curcarry) {
1.1.1.6 root 4298: source[0]=0; source[1]=0; source[2]=1;
1.1 root 4299: newsr |= dsp_add56(source, dest);
4300: }
4301:
1.1.1.6 root 4302: dsp_core.registers[DSP_REG_A2] = dest[0];
4303: dsp_core.registers[DSP_REG_A1] = dest[1];
4304: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4305:
1.1.1.6 root 4306: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4307:
1.1.1.6 root 4308: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4309: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4310: }
4311:
1.1.1.6 root 4312: static void dsp_adc_x_b(void)
1.1 root 4313: {
1.1.1.6 root 4314: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4315: Uint16 newsr;
1.1 root 4316:
1.1.1.6 root 4317: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
4318:
4319: dest[0] = dsp_core.registers[DSP_REG_B2];
4320: dest[1] = dsp_core.registers[DSP_REG_B1];
4321: dest[2] = dsp_core.registers[DSP_REG_B0];
4322:
4323: source[2] = dsp_core.registers[DSP_REG_X0];
4324: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4325: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4326:
4327: newsr = dsp_add56(source, dest);
1.1.1.6 root 4328:
4329: if (curcarry) {
4330: source[0]=0; source[1]=0; source[2]=1;
4331: newsr |= dsp_add56(source, dest);
4332: }
1.1 root 4333:
1.1.1.6 root 4334: dsp_core.registers[DSP_REG_B2] = dest[0];
4335: dsp_core.registers[DSP_REG_B1] = dest[1];
4336: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4337:
1.1.1.6 root 4338: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4339:
1.1.1.6 root 4340: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4341: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4342: }
4343:
1.1.1.6 root 4344: static void dsp_adc_y_a(void)
1.1 root 4345: {
1.1.1.6 root 4346: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4347: Uint16 newsr;
1.1 root 4348:
1.1.1.6 root 4349: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4350:
1.1.1.6 root 4351: dest[0] = dsp_core.registers[DSP_REG_A2];
4352: dest[1] = dsp_core.registers[DSP_REG_A1];
4353: dest[2] = dsp_core.registers[DSP_REG_A0];
4354:
4355: source[2] = dsp_core.registers[DSP_REG_Y0];
4356: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4357: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4358:
1.1.1.6 root 4359: newsr = dsp_add56(source, dest);
4360:
4361: if (curcarry) {
4362: source[0]=0; source[1]=0; source[2]=1;
4363: newsr |= dsp_add56(source, dest);
4364: }
1.1 root 4365:
1.1.1.6 root 4366: dsp_core.registers[DSP_REG_A2] = dest[0];
4367: dsp_core.registers[DSP_REG_A1] = dest[1];
4368: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4369:
1.1.1.6 root 4370: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4371:
1.1.1.6 root 4372: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4373: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4374: }
4375:
1.1.1.6 root 4376: static void dsp_adc_y_b(void)
1.1 root 4377: {
1.1.1.6 root 4378: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4379: Uint16 newsr;
1.1 root 4380:
1.1.1.6 root 4381: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4382:
1.1.1.6 root 4383: dest[0] = dsp_core.registers[DSP_REG_B2];
4384: dest[1] = dsp_core.registers[DSP_REG_B1];
4385: dest[2] = dsp_core.registers[DSP_REG_B0];
4386:
4387: source[2] = dsp_core.registers[DSP_REG_Y0];
4388: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4389: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4390:
1.1.1.6 root 4391: newsr = dsp_add56(source, dest);
4392:
4393: if (curcarry) {
4394: source[0]=0; source[1]=0; source[2]=1;
4395: newsr |= dsp_add56(source, dest);
4396: }
1.1 root 4397:
1.1.1.6 root 4398: dsp_core.registers[DSP_REG_B2] = dest[0];
4399: dsp_core.registers[DSP_REG_B1] = dest[1];
4400: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4401:
1.1.1.6 root 4402: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4403:
1.1.1.6 root 4404: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4405: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4406: }
4407:
1.1.1.6 root 4408: static void dsp_add_b_a(void)
1.1 root 4409: {
1.1.1.6 root 4410: Uint32 source[3], dest[3];
4411: Uint16 newsr;
1.1 root 4412:
1.1.1.6 root 4413: dest[0] = dsp_core.registers[DSP_REG_A2];
4414: dest[1] = dsp_core.registers[DSP_REG_A1];
4415: dest[2] = dsp_core.registers[DSP_REG_A0];
4416:
4417: source[0] = dsp_core.registers[DSP_REG_B2];
4418: source[1] = dsp_core.registers[DSP_REG_B1];
4419: source[2] = dsp_core.registers[DSP_REG_B0];
4420:
4421: newsr = dsp_add56(source, dest);
4422:
4423: dsp_core.registers[DSP_REG_A2] = dest[0];
4424: dsp_core.registers[DSP_REG_A1] = dest[1];
4425: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4426:
1.1.1.6 root 4427: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4428:
1.1.1.6 root 4429: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4430: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4431: }
4432:
1.1.1.6 root 4433: static void dsp_add_a_b(void)
1.1 root 4434: {
1.1.1.6 root 4435: Uint32 source[3], dest[3];
1.1.1.2 root 4436: Uint16 newsr;
1.1 root 4437:
1.1.1.6 root 4438: dest[0] = dsp_core.registers[DSP_REG_B2];
4439: dest[1] = dsp_core.registers[DSP_REG_B1];
4440: dest[2] = dsp_core.registers[DSP_REG_B0];
4441:
4442: source[0] = dsp_core.registers[DSP_REG_A2];
4443: source[1] = dsp_core.registers[DSP_REG_A1];
4444: source[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 4445:
1.1.1.6 root 4446: newsr = dsp_add56(source, dest);
1.1 root 4447:
1.1.1.6 root 4448: dsp_core.registers[DSP_REG_B2] = dest[0];
4449: dsp_core.registers[DSP_REG_B1] = dest[1];
4450: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4451:
1.1.1.6 root 4452: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4453:
1.1.1.6 root 4454: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4455: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4456: }
4457:
1.1.1.6 root 4458: static void dsp_add_x_a(void)
1.1 root 4459: {
1.1.1.6 root 4460: Uint32 source[3], dest[3];
4461: Uint16 newsr;
1.1 root 4462:
1.1.1.6 root 4463: dest[0] = dsp_core.registers[DSP_REG_A2];
4464: dest[1] = dsp_core.registers[DSP_REG_A1];
4465: dest[2] = dsp_core.registers[DSP_REG_A0];
4466:
4467: source[1] = dsp_core.registers[DSP_REG_X1];
4468: source[2] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4469: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4470:
1.1.1.6 root 4471: newsr = dsp_add56(source, dest);
1.1 root 4472:
1.1.1.6 root 4473: dsp_core.registers[DSP_REG_A2] = dest[0];
4474: dsp_core.registers[DSP_REG_A1] = dest[1];
4475: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4476:
1.1.1.6 root 4477: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4478:
1.1.1.6 root 4479: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4480: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4481: }
4482:
1.1.1.6 root 4483: static void dsp_add_x_b(void)
1.1 root 4484: {
1.1.1.6 root 4485: Uint32 source[3], dest[3];
4486: Uint16 newsr;
1.1 root 4487:
1.1.1.6 root 4488: dest[0] = dsp_core.registers[DSP_REG_B2];
4489: dest[1] = dsp_core.registers[DSP_REG_B1];
4490: dest[2] = dsp_core.registers[DSP_REG_B0];
4491:
4492: source[1] = dsp_core.registers[DSP_REG_X1];
4493: source[2] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4494: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4495:
4496: newsr = dsp_add56(source, dest);
1.1 root 4497:
1.1.1.6 root 4498: dsp_core.registers[DSP_REG_B2] = dest[0];
4499: dsp_core.registers[DSP_REG_B1] = dest[1];
4500: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4501:
1.1.1.6 root 4502: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4503:
4504: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4505: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4506: }
4507:
1.1.1.6 root 4508: static void dsp_add_y_a(void)
1.1 root 4509: {
1.1.1.6 root 4510: Uint32 source[3], dest[3];
1.1.1.2 root 4511: Uint16 newsr;
1.1 root 4512:
1.1.1.6 root 4513: dest[0] = dsp_core.registers[DSP_REG_A2];
4514: dest[1] = dsp_core.registers[DSP_REG_A1];
4515: dest[2] = dsp_core.registers[DSP_REG_A0];
4516:
4517: source[1] = dsp_core.registers[DSP_REG_Y1];
4518: source[2] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4519: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4520:
1.1.1.6 root 4521: newsr = dsp_add56(source, dest);
1.1 root 4522:
1.1.1.6 root 4523: dsp_core.registers[DSP_REG_A2] = dest[0];
4524: dsp_core.registers[DSP_REG_A1] = dest[1];
4525: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4526:
1.1.1.6 root 4527: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4528:
4529: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4530: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4531: }
4532:
1.1.1.6 root 4533: static void dsp_add_y_b(void)
1.1 root 4534: {
1.1.1.6 root 4535: Uint32 source[3], dest[3];
1.1.1.2 root 4536: Uint16 newsr;
1.1 root 4537:
1.1.1.6 root 4538: dest[0] = dsp_core.registers[DSP_REG_B2];
4539: dest[1] = dsp_core.registers[DSP_REG_B1];
4540: dest[2] = dsp_core.registers[DSP_REG_B0];
4541:
4542: source[1] = dsp_core.registers[DSP_REG_Y1];
4543: source[2] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4544: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4545:
1.1.1.6 root 4546: newsr = dsp_add56(source, dest);
1.1 root 4547:
1.1.1.6 root 4548: dsp_core.registers[DSP_REG_B2] = dest[0];
4549: dsp_core.registers[DSP_REG_B1] = dest[1];
4550: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4551:
1.1.1.6 root 4552: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4553:
1.1.1.6 root 4554: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4555: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4556: }
4557:
1.1.1.6 root 4558: static void dsp_add_x0_a(void)
1.1 root 4559: {
1.1.1.6 root 4560: Uint32 source[3], dest[3];
4561: Uint16 newsr;
1.1 root 4562:
1.1.1.6 root 4563: dest[0] = dsp_core.registers[DSP_REG_A2];
4564: dest[1] = dsp_core.registers[DSP_REG_A1];
4565: dest[2] = dsp_core.registers[DSP_REG_A0];
4566:
4567: source[2] = 0;
4568: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4569: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4570:
4571: newsr = dsp_add56(source, dest);
4572:
4573: dsp_core.registers[DSP_REG_A2] = dest[0];
4574: dsp_core.registers[DSP_REG_A1] = dest[1];
4575: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4576:
1.1.1.6 root 4577: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4578:
1.1.1.6 root 4579: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4580: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4581: }
4582:
1.1.1.6 root 4583: static void dsp_add_x0_b(void)
1.1 root 4584: {
1.1.1.6 root 4585: Uint32 source[3], dest[3];
4586: Uint16 newsr;
4587:
4588: dest[0] = dsp_core.registers[DSP_REG_B2];
4589: dest[1] = dsp_core.registers[DSP_REG_B1];
4590: dest[2] = dsp_core.registers[DSP_REG_B0];
4591:
4592: source[2] = 0;
4593: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4594: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4595:
1.1.1.6 root 4596: newsr = dsp_add56(source, dest);
1.1 root 4597:
1.1.1.6 root 4598: dsp_core.registers[DSP_REG_B2] = dest[0];
4599: dsp_core.registers[DSP_REG_B1] = dest[1];
4600: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4601:
1.1.1.6 root 4602: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4603:
1.1.1.6 root 4604: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4605: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4606: }
4607:
1.1.1.6 root 4608: static void dsp_add_y0_a(void)
1.1 root 4609: {
1.1.1.6 root 4610: Uint32 source[3], dest[3];
4611: Uint16 newsr;
1.1 root 4612:
1.1.1.6 root 4613: dest[0] = dsp_core.registers[DSP_REG_A2];
4614: dest[1] = dsp_core.registers[DSP_REG_A1];
4615: dest[2] = dsp_core.registers[DSP_REG_A0];
4616:
4617: source[2] = 0;
4618: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4619: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4620:
1.1.1.6 root 4621: newsr = dsp_add56(source, dest);
4622:
4623: dsp_core.registers[DSP_REG_A2] = dest[0];
4624: dsp_core.registers[DSP_REG_A1] = dest[1];
4625: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4626:
1.1.1.6 root 4627: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4628:
1.1.1.6 root 4629: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4630: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4631: }
4632:
1.1.1.6 root 4633: static void dsp_add_y0_b(void)
1.1 root 4634: {
1.1.1.6 root 4635: Uint32 source[3], dest[3];
1.1.1.2 root 4636: Uint16 newsr;
1.1 root 4637:
1.1.1.6 root 4638: dest[0] = dsp_core.registers[DSP_REG_B2];
4639: dest[1] = dsp_core.registers[DSP_REG_B1];
4640: dest[2] = dsp_core.registers[DSP_REG_B0];
4641:
4642: source[2] = 0;
4643: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4644: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4645:
4646: newsr = dsp_add56(source, dest);
4647:
1.1.1.6 root 4648: dsp_core.registers[DSP_REG_B2] = dest[0];
4649: dsp_core.registers[DSP_REG_B1] = dest[1];
4650: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4651:
1.1.1.6 root 4652: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4653:
1.1.1.6 root 4654: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4655: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4656: }
4657:
1.1.1.6 root 4658: static void dsp_add_x1_a(void)
1.1 root 4659: {
1.1.1.6 root 4660: Uint32 source[3], dest[3];
1.1.1.2 root 4661: Uint16 newsr;
1.1 root 4662:
1.1.1.6 root 4663: dest[0] = dsp_core.registers[DSP_REG_A2];
4664: dest[1] = dsp_core.registers[DSP_REG_A1];
4665: dest[2] = dsp_core.registers[DSP_REG_A0];
4666:
4667: source[2] = 0;
4668: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4669: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4670:
4671: newsr = dsp_add56(source, dest);
4672:
1.1.1.6 root 4673: dsp_core.registers[DSP_REG_A2] = dest[0];
4674: dsp_core.registers[DSP_REG_A1] = dest[1];
4675: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4676:
1.1.1.6 root 4677: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4678:
1.1.1.6 root 4679: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4680: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4681: }
4682:
1.1.1.6 root 4683: static void dsp_add_x1_b(void)
1.1 root 4684: {
1.1.1.6 root 4685: Uint32 source[3], dest[3];
4686: Uint16 newsr;
4687:
4688: dest[0] = dsp_core.registers[DSP_REG_B2];
4689: dest[1] = dsp_core.registers[DSP_REG_B1];
4690: dest[2] = dsp_core.registers[DSP_REG_B0];
4691:
4692: source[2] = 0;
4693: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4694: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4695:
4696: newsr = dsp_add56(source, dest);
4697:
4698: dsp_core.registers[DSP_REG_B2] = dest[0];
4699: dsp_core.registers[DSP_REG_B1] = dest[1];
4700: dsp_core.registers[DSP_REG_B0] = dest[2];
4701:
4702: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4703:
4704: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4705: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4706: }
4707:
1.1.1.6 root 4708: static void dsp_add_y1_a(void)
1.1 root 4709: {
1.1.1.6 root 4710: Uint32 source[3], dest[3];
4711: Uint16 newsr;
1.1 root 4712:
1.1.1.6 root 4713: dest[0] = dsp_core.registers[DSP_REG_A2];
4714: dest[1] = dsp_core.registers[DSP_REG_A1];
4715: dest[2] = dsp_core.registers[DSP_REG_A0];
4716:
4717: source[2] = 0;
4718: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4719: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4720:
1.1.1.6 root 4721: newsr = dsp_add56(source, dest);
1.1 root 4722:
1.1.1.6 root 4723: dsp_core.registers[DSP_REG_A2] = dest[0];
4724: dsp_core.registers[DSP_REG_A1] = dest[1];
4725: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4726:
1.1.1.6 root 4727: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4728:
1.1.1.6 root 4729: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4730: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4731: }
4732:
1.1.1.6 root 4733: static void dsp_add_y1_b(void)
1.1 root 4734: {
1.1.1.6 root 4735: Uint32 source[3], dest[3];
4736: Uint16 newsr;
1.1 root 4737:
1.1.1.6 root 4738: dest[0] = dsp_core.registers[DSP_REG_B2];
4739: dest[1] = dsp_core.registers[DSP_REG_B1];
4740: dest[2] = dsp_core.registers[DSP_REG_B0];
4741:
4742: source[2] = 0;
4743: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4744: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4745:
1.1.1.6 root 4746: newsr = dsp_add56(source, dest);
1.1 root 4747:
1.1.1.6 root 4748: dsp_core.registers[DSP_REG_B2] = dest[0];
4749: dsp_core.registers[DSP_REG_B1] = dest[1];
4750: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4751:
1.1.1.6 root 4752: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4753:
1.1.1.6 root 4754: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4755: dsp_core.registers[DSP_REG_SR] |= newsr;
4756: }
1.1 root 4757:
1.1.1.6 root 4758: static void dsp_addl_b_a(void)
4759: {
4760: Uint32 source[3], dest[3];
4761: Uint16 newsr;
1.1.1.2 root 4762:
1.1.1.6 root 4763: dest[0] = dsp_core.registers[DSP_REG_A2];
4764: dest[1] = dsp_core.registers[DSP_REG_A1];
4765: dest[2] = dsp_core.registers[DSP_REG_A0];
4766: newsr = dsp_asl56(dest);
1.1 root 4767:
1.1.1.6 root 4768: source[0] = dsp_core.registers[DSP_REG_B2];
4769: source[1] = dsp_core.registers[DSP_REG_B1];
4770: source[2] = dsp_core.registers[DSP_REG_B0];
4771: newsr |= dsp_add56(source, dest);
1.1 root 4772:
1.1.1.6 root 4773: dsp_core.registers[DSP_REG_A2] = dest[0];
4774: dsp_core.registers[DSP_REG_A1] = dest[1];
4775: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4776:
1.1.1.6 root 4777: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4778:
1.1.1.6 root 4779: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4780: dsp_core.registers[DSP_REG_SR] |= newsr;
4781: }
1.1 root 4782:
1.1.1.6 root 4783: static void dsp_addl_a_b(void)
4784: {
4785: Uint32 source[3], dest[3];
4786: Uint16 newsr;
1.1 root 4787:
1.1.1.6 root 4788: dest[0] = dsp_core.registers[DSP_REG_B2];
4789: dest[1] = dsp_core.registers[DSP_REG_B1];
4790: dest[2] = dsp_core.registers[DSP_REG_B0];
4791: newsr = dsp_asl56(dest);
1.1 root 4792:
1.1.1.6 root 4793: source[0] = dsp_core.registers[DSP_REG_A2];
4794: source[1] = dsp_core.registers[DSP_REG_A1];
4795: source[2] = dsp_core.registers[DSP_REG_A0];
4796: newsr |= dsp_add56(source, dest);
4797:
4798: dsp_core.registers[DSP_REG_B2] = dest[0];
4799: dsp_core.registers[DSP_REG_B1] = dest[1];
4800: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4801:
1.1.1.6 root 4802: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4803:
1.1.1.6 root 4804: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4805: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4806: }
4807:
1.1.1.6 root 4808: static void dsp_addr_b_a(void)
1.1 root 4809: {
1.1.1.6 root 4810: Uint32 source[3], dest[3];
4811: Uint16 newsr;
4812:
4813: dest[0] = dsp_core.registers[DSP_REG_A2];
4814: dest[1] = dsp_core.registers[DSP_REG_A1];
4815: dest[2] = dsp_core.registers[DSP_REG_A0];
4816: newsr = dsp_asr56(dest);
4817:
4818: source[0] = dsp_core.registers[DSP_REG_B2];
4819: source[1] = dsp_core.registers[DSP_REG_B1];
4820: source[2] = dsp_core.registers[DSP_REG_B0];
4821: newsr |= dsp_add56(source, dest);
4822:
4823: dsp_core.registers[DSP_REG_A2] = dest[0];
4824: dsp_core.registers[DSP_REG_A1] = dest[1];
4825: dsp_core.registers[DSP_REG_A0] = dest[2];
4826:
4827: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4828:
4829: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4830: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4831: }
4832:
1.1.1.6 root 4833: static void dsp_addr_a_b(void)
1.1 root 4834: {
1.1.1.6 root 4835: Uint32 source[3], dest[3];
4836: Uint16 newsr;
4837:
4838: dest[0] = dsp_core.registers[DSP_REG_B2];
4839: dest[1] = dsp_core.registers[DSP_REG_B1];
4840: dest[2] = dsp_core.registers[DSP_REG_B0];
4841: newsr = dsp_asr56(dest);
4842:
4843: source[0] = dsp_core.registers[DSP_REG_A2];
4844: source[1] = dsp_core.registers[DSP_REG_A1];
4845: source[2] = dsp_core.registers[DSP_REG_A0];
4846: newsr |= dsp_add56(source, dest);
1.1 root 4847:
1.1.1.6 root 4848: dsp_core.registers[DSP_REG_B2] = dest[0];
4849: dsp_core.registers[DSP_REG_B1] = dest[1];
4850: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4851:
1.1.1.6 root 4852: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4853:
1.1.1.6 root 4854: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4855: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4856: }
4857:
1.1.1.6 root 4858: static void dsp_and_x0_a(void)
1.1 root 4859: {
1.1.1.6 root 4860: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X0];
1.1 root 4861:
1.1.1.6 root 4862: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4863: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4864: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4865: }
1.1 root 4866:
1.1.1.6 root 4867: static void dsp_and_x0_b(void)
4868: {
4869: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X0];
1.1 root 4870:
1.1.1.6 root 4871: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4872: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4873: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
1.1 root 4874: }
4875:
1.1.1.6 root 4876: static void dsp_and_y0_a(void)
1.1 root 4877: {
1.1.1.6 root 4878: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y0];
1.1 root 4879:
1.1.1.6 root 4880: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4881: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4882: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4883: }
1.1 root 4884:
1.1.1.6 root 4885: static void dsp_and_y0_b(void)
4886: {
4887: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y0];
1.1 root 4888:
1.1.1.6 root 4889: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4890: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4891: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
4892: }
1.1 root 4893:
1.1.1.6 root 4894: static void dsp_and_x1_a(void)
4895: {
4896: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X1];
1.1.1.2 root 4897:
1.1.1.6 root 4898: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4899: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4900: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
1.1 root 4901: }
4902:
1.1.1.6 root 4903: static void dsp_and_x1_b(void)
1.1 root 4904: {
1.1.1.6 root 4905: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X1];
4906:
4907: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4908: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4909: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
4910: }
1.1 root 4911:
1.1.1.6 root 4912: static void dsp_and_y1_a(void)
4913: {
4914: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y1];
1.1 root 4915:
1.1.1.6 root 4916: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4917: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4918: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4919: }
1.1 root 4920:
1.1.1.6 root 4921: static void dsp_and_y1_b(void)
4922: {
4923: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y1];
1.1.1.2 root 4924:
1.1.1.6 root 4925: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4926: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4927: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
1.1 root 4928: }
4929:
1.1.1.7 root 4930: static void dsp_asl_a(void)
1.1 root 4931: {
1.1.1.6 root 4932: Uint32 dest[3];
4933: Uint16 newsr;
1.1 root 4934:
1.1.1.6 root 4935: dest[0] = dsp_core.registers[DSP_REG_A2];
4936: dest[1] = dsp_core.registers[DSP_REG_A1];
4937: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 4938:
1.1.1.6 root 4939: newsr = dsp_asl56(dest);
4940:
4941: dsp_core.registers[DSP_REG_A2] = dest[0];
4942: dsp_core.registers[DSP_REG_A1] = dest[1];
4943: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4944:
1.1.1.6 root 4945: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
4946: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1.1.2 root 4947:
1.1.1.6 root 4948: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4949: }
4950:
1.1.1.7 root 4951: static void dsp_asl_b(void)
1.1 root 4952: {
1.1.1.6 root 4953: Uint32 dest[3];
1.1.1.2 root 4954: Uint16 newsr;
1.1 root 4955:
1.1.1.6 root 4956: dest[0] = dsp_core.registers[DSP_REG_B2];
4957: dest[1] = dsp_core.registers[DSP_REG_B1];
4958: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 4959:
1.1.1.6 root 4960: newsr = dsp_asl56(dest);
1.1 root 4961:
1.1.1.6 root 4962: dsp_core.registers[DSP_REG_B2] = dest[0];
4963: dsp_core.registers[DSP_REG_B1] = dest[1];
4964: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4965:
1.1.1.6 root 4966: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
4967: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4968:
1.1.1.6 root 4969: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4970: }
4971:
1.1.1.7 root 4972: static void dsp_asr_a(void)
1.1 root 4973: {
1.1.1.6 root 4974: Uint32 dest[3];
4975: Uint16 newsr;
4976:
4977: dest[0] = dsp_core.registers[DSP_REG_A2];
4978: dest[1] = dsp_core.registers[DSP_REG_A1];
4979: dest[2] = dsp_core.registers[DSP_REG_A0];
4980:
4981: newsr = dsp_asr56(dest);
4982:
4983: dsp_core.registers[DSP_REG_A2] = dest[0];
4984: dsp_core.registers[DSP_REG_A1] = dest[1];
4985: dsp_core.registers[DSP_REG_A0] = dest[2];
4986:
4987: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
4988: dsp_core.registers[DSP_REG_SR] |= newsr;
4989:
4990: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4991: }
4992:
1.1.1.7 root 4993: static void dsp_asr_b(void)
1.1.1.6 root 4994: {
4995: Uint32 dest[3];
4996: Uint16 newsr;
4997:
4998: dest[0] = dsp_core.registers[DSP_REG_B2];
4999: dest[1] = dsp_core.registers[DSP_REG_B1];
5000: dest[2] = dsp_core.registers[DSP_REG_B0];
5001:
5002: newsr = dsp_asr56(dest);
5003:
5004: dsp_core.registers[DSP_REG_B2] = dest[0];
5005: dsp_core.registers[DSP_REG_B1] = dest[1];
5006: dsp_core.registers[DSP_REG_B0] = dest[2];
5007:
5008: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5009: dsp_core.registers[DSP_REG_SR] |= newsr;
5010:
5011: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5012: }
5013:
5014: static void dsp_clr_a(void)
5015: {
1.1.1.7 root 5016: dsp_core.registers[DSP_REG_A2] = 0;
5017: dsp_core.registers[DSP_REG_A1] = 0;
5018: dsp_core.registers[DSP_REG_A0] = 0;
1.1.1.6 root 5019:
5020: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5021: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5022: }
5023:
5024: static void dsp_clr_b(void)
5025: {
1.1.1.7 root 5026: dsp_core.registers[DSP_REG_B2] = 0;
5027: dsp_core.registers[DSP_REG_B1] = 0;
5028: dsp_core.registers[DSP_REG_B0] = 0;
1.1.1.6 root 5029:
5030: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5031: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5032: }
5033:
5034: static void dsp_cmp_b_a(void)
5035: {
5036: Uint32 source[3], dest[3];
5037: Uint16 newsr;
5038:
5039: dest[0] = dsp_core.registers[DSP_REG_A2];
5040: dest[1] = dsp_core.registers[DSP_REG_A1];
5041: dest[2] = dsp_core.registers[DSP_REG_A0];
5042:
5043: source[0] = dsp_core.registers[DSP_REG_B2];
5044: source[1] = dsp_core.registers[DSP_REG_B1];
5045: source[2] = dsp_core.registers[DSP_REG_B0];
5046:
5047: newsr = dsp_sub56(source, dest);
5048:
5049: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5050:
5051: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5052: dsp_core.registers[DSP_REG_SR] |= newsr;
5053: }
5054:
5055: static void dsp_cmp_a_b(void)
5056: {
5057: Uint32 source[3], dest[3];
5058: Uint16 newsr;
5059:
5060: dest[0] = dsp_core.registers[DSP_REG_B2];
5061: dest[1] = dsp_core.registers[DSP_REG_B1];
5062: dest[2] = dsp_core.registers[DSP_REG_B0];
5063:
5064: source[0] = dsp_core.registers[DSP_REG_A2];
5065: source[1] = dsp_core.registers[DSP_REG_A1];
5066: source[2] = dsp_core.registers[DSP_REG_A0];
5067:
5068: newsr = dsp_sub56(source, dest);
5069:
5070: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5071:
5072: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5073: dsp_core.registers[DSP_REG_SR] |= newsr;
5074: }
5075:
5076: static void dsp_cmp_x0_a(void)
5077: {
5078: Uint32 source[3], dest[3];
5079: Uint16 newsr;
5080:
5081: dest[2] = dsp_core.registers[DSP_REG_A0];
5082: dest[1] = dsp_core.registers[DSP_REG_A1];
5083: dest[0] = dsp_core.registers[DSP_REG_A2];
5084:
5085: source[2] = 0;
5086: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5087: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5088:
5089: newsr = dsp_sub56(source, dest);
5090:
5091: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5092:
5093: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5094: dsp_core.registers[DSP_REG_SR] |= newsr;
5095: }
5096:
5097: static void dsp_cmp_x0_b(void)
5098: {
5099: Uint32 source[3], dest[3];
5100: Uint16 newsr;
5101:
5102: dest[0] = dsp_core.registers[DSP_REG_B2];
5103: dest[1] = dsp_core.registers[DSP_REG_B1];
5104: dest[2] = dsp_core.registers[DSP_REG_B0];
5105:
5106: source[2] = 0;
5107: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5108: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5109:
5110: newsr = dsp_sub56(source, dest);
5111:
5112: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5113:
5114: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5115: dsp_core.registers[DSP_REG_SR] |= newsr;
5116: }
5117:
5118: static void dsp_cmp_y0_a(void)
5119: {
5120: Uint32 source[3], dest[3];
5121: Uint16 newsr;
5122:
5123: dest[2] = dsp_core.registers[DSP_REG_A0];
5124: dest[1] = dsp_core.registers[DSP_REG_A1];
5125: dest[0] = dsp_core.registers[DSP_REG_A2];
5126:
5127: source[2] = 0;
5128: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5129: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5130:
5131: newsr = dsp_sub56(source, dest);
5132:
5133: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5134:
5135: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5136: dsp_core.registers[DSP_REG_SR] |= newsr;
5137: }
5138:
5139: static void dsp_cmp_y0_b(void)
5140: {
5141: Uint32 source[3], dest[3];
5142: Uint16 newsr;
5143:
5144: dest[0] = dsp_core.registers[DSP_REG_B2];
5145: dest[1] = dsp_core.registers[DSP_REG_B1];
5146: dest[2] = dsp_core.registers[DSP_REG_B0];
5147:
5148: source[2] = 0;
5149: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5150: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5151:
5152: newsr = dsp_sub56(source, dest);
5153:
5154: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5155:
5156: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5157: dsp_core.registers[DSP_REG_SR] |= newsr;
5158: }
5159: static void dsp_cmp_x1_a(void)
5160: {
5161: Uint32 source[3], dest[3];
5162: Uint16 newsr;
5163:
5164: dest[2] = dsp_core.registers[DSP_REG_A0];
5165: dest[1] = dsp_core.registers[DSP_REG_A1];
5166: dest[0] = dsp_core.registers[DSP_REG_A2];
5167:
5168: source[2] = 0;
5169: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5170: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5171:
5172: newsr = dsp_sub56(source, dest);
5173:
5174: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5175:
5176: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5177: dsp_core.registers[DSP_REG_SR] |= newsr;
5178: }
5179:
5180: static void dsp_cmp_x1_b(void)
5181: {
5182: Uint32 source[3], dest[3];
5183: Uint16 newsr;
5184:
5185: dest[0] = dsp_core.registers[DSP_REG_B2];
5186: dest[1] = dsp_core.registers[DSP_REG_B1];
5187: dest[2] = dsp_core.registers[DSP_REG_B0];
5188:
5189: source[2] = 0;
5190: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5191: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5192:
5193: newsr = dsp_sub56(source, dest);
5194:
5195: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5196:
5197: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5198: dsp_core.registers[DSP_REG_SR] |= newsr;
5199: }
5200:
5201: static void dsp_cmp_y1_a(void)
5202: {
5203: Uint32 source[3], dest[3];
5204: Uint16 newsr;
5205:
5206: dest[2] = dsp_core.registers[DSP_REG_A0];
5207: dest[1] = dsp_core.registers[DSP_REG_A1];
5208: dest[0] = dsp_core.registers[DSP_REG_A2];
5209:
5210: source[2] = 0;
5211: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5212: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5213:
5214: newsr = dsp_sub56(source, dest);
5215:
5216: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5217:
5218: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5219: dsp_core.registers[DSP_REG_SR] |= newsr;
5220: }
5221:
5222: static void dsp_cmp_y1_b(void)
5223: {
5224: Uint32 source[3], dest[3];
5225: Uint16 newsr;
5226:
5227: dest[0] = dsp_core.registers[DSP_REG_B2];
5228: dest[1] = dsp_core.registers[DSP_REG_B1];
5229: dest[2] = dsp_core.registers[DSP_REG_B0];
5230:
5231: source[2] = 0;
5232: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5233: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5234:
5235: newsr = dsp_sub56(source, dest);
5236:
5237: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5238:
5239: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5240: dsp_core.registers[DSP_REG_SR] |= newsr;
5241: }
5242:
5243: static void dsp_cmpm_b_a(void)
5244: {
5245: Uint32 source[3], dest[3];
5246: Uint16 newsr;
5247:
5248: dest[0] = dsp_core.registers[DSP_REG_A2];
5249: dest[1] = dsp_core.registers[DSP_REG_A1];
5250: dest[2] = dsp_core.registers[DSP_REG_A0];
5251: dsp_abs56(dest);
5252:
5253: source[0] = dsp_core.registers[DSP_REG_B2];
5254: source[1] = dsp_core.registers[DSP_REG_B1];
5255: source[2] = dsp_core.registers[DSP_REG_B0];
5256: dsp_abs56(source);
5257:
5258: newsr = dsp_sub56(source, dest);
5259:
5260: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5261:
5262: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5263: dsp_core.registers[DSP_REG_SR] |= newsr;
5264: }
5265:
5266: static void dsp_cmpm_a_b(void)
5267: {
5268: Uint32 source[3], dest[3];
5269: Uint16 newsr;
5270:
5271: dest[0] = dsp_core.registers[DSP_REG_B2];
5272: dest[1] = dsp_core.registers[DSP_REG_B1];
5273: dest[2] = dsp_core.registers[DSP_REG_B0];
5274: dsp_abs56(dest);
5275:
5276: source[0] = dsp_core.registers[DSP_REG_A2];
5277: source[1] = dsp_core.registers[DSP_REG_A1];
5278: source[2] = dsp_core.registers[DSP_REG_A0];
5279: dsp_abs56(source);
5280:
5281: newsr = dsp_sub56(source, dest);
5282:
5283: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5284:
5285: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5286: dsp_core.registers[DSP_REG_SR] |= newsr;
5287: }
5288:
5289: static void dsp_cmpm_x0_a(void)
5290: {
5291: Uint32 source[3], dest[3];
5292: Uint16 newsr;
5293:
5294: dest[2] = dsp_core.registers[DSP_REG_A0];
5295: dest[1] = dsp_core.registers[DSP_REG_A1];
5296: dest[0] = dsp_core.registers[DSP_REG_A2];
5297: dsp_abs56(dest);
5298:
5299: source[2] = 0;
5300: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5301: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5302: dsp_abs56(source);
5303:
5304: newsr = dsp_sub56(source, dest);
5305:
5306: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5307:
5308: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5309: dsp_core.registers[DSP_REG_SR] |= newsr;
5310: }
5311:
5312: static void dsp_cmpm_x0_b(void)
5313: {
5314: Uint32 source[3], dest[3];
5315: Uint16 newsr;
5316:
5317: dest[0] = dsp_core.registers[DSP_REG_B2];
5318: dest[1] = dsp_core.registers[DSP_REG_B1];
5319: dest[2] = dsp_core.registers[DSP_REG_B0];
5320: dsp_abs56(dest);
5321:
5322: source[2] = 0;
5323: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5324: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5325: dsp_abs56(source);
5326:
5327: newsr = dsp_sub56(source, dest);
5328:
5329: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5330:
5331: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5332: dsp_core.registers[DSP_REG_SR] |= newsr;
5333: }
5334:
5335: static void dsp_cmpm_y0_a(void)
5336: {
5337: Uint32 source[3], dest[3];
5338: Uint16 newsr;
5339:
5340: dest[2] = dsp_core.registers[DSP_REG_A0];
5341: dest[1] = dsp_core.registers[DSP_REG_A1];
5342: dest[0] = dsp_core.registers[DSP_REG_A2];
5343: dsp_abs56(dest);
5344:
5345: source[2] = 0;
5346: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5347: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5348: dsp_abs56(source);
5349:
5350: newsr = dsp_sub56(source, dest);
5351:
5352: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5353:
5354: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5355: dsp_core.registers[DSP_REG_SR] |= newsr;
5356: }
5357:
5358: static void dsp_cmpm_y0_b(void)
5359: {
5360: Uint32 source[3], dest[3];
5361: Uint16 newsr;
5362:
5363: dest[0] = dsp_core.registers[DSP_REG_B2];
5364: dest[1] = dsp_core.registers[DSP_REG_B1];
5365: dest[2] = dsp_core.registers[DSP_REG_B0];
5366: dsp_abs56(dest);
5367:
5368: source[2] = 0;
5369: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5370: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5371: dsp_abs56(source);
5372:
5373: newsr = dsp_sub56(source, dest);
5374:
5375: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5376:
5377: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5378: dsp_core.registers[DSP_REG_SR] |= newsr;
5379: }
5380:
5381: static void dsp_cmpm_x1_a(void)
5382: {
5383: Uint32 source[3], dest[3];
5384: Uint16 newsr;
5385:
5386: dest[2] = dsp_core.registers[DSP_REG_A0];
5387: dest[1] = dsp_core.registers[DSP_REG_A1];
5388: dest[0] = dsp_core.registers[DSP_REG_A2];
5389: dsp_abs56(dest);
5390:
5391: source[2] = 0;
5392: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5393: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5394: dsp_abs56(source);
5395:
5396: newsr = dsp_sub56(source, dest);
5397:
5398: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5399:
5400: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5401: dsp_core.registers[DSP_REG_SR] |= newsr;
5402: }
5403:
5404: static void dsp_cmpm_x1_b(void)
5405: {
5406: Uint32 source[3], dest[3];
5407: Uint16 newsr;
5408:
5409: dest[0] = dsp_core.registers[DSP_REG_B2];
5410: dest[1] = dsp_core.registers[DSP_REG_B1];
5411: dest[2] = dsp_core.registers[DSP_REG_B0];
5412: dsp_abs56(dest);
5413:
5414: source[2] = 0;
5415: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5416: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5417: dsp_abs56(source);
5418:
5419: newsr = dsp_sub56(source, dest);
5420:
5421: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5422:
5423: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5424: dsp_core.registers[DSP_REG_SR] |= newsr;
5425: }
5426:
5427: static void dsp_cmpm_y1_a(void)
5428: {
5429: Uint32 source[3], dest[3];
5430: Uint16 newsr;
5431:
5432: dest[2] = dsp_core.registers[DSP_REG_A0];
5433: dest[1] = dsp_core.registers[DSP_REG_A1];
5434: dest[0] = dsp_core.registers[DSP_REG_A2];
5435: dsp_abs56(dest);
5436:
5437: source[2] = 0;
5438: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5439: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5440: dsp_abs56(source);
5441:
5442: newsr = dsp_sub56(source, dest);
5443:
5444: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5445:
5446: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5447: dsp_core.registers[DSP_REG_SR] |= newsr;
5448: }
5449:
5450: static void dsp_cmpm_y1_b(void)
5451: {
5452: Uint32 source[3], dest[3];
5453: Uint16 newsr;
5454:
5455: dest[0] = dsp_core.registers[DSP_REG_B2];
5456: dest[1] = dsp_core.registers[DSP_REG_B1];
5457: dest[2] = dsp_core.registers[DSP_REG_B0];
5458: dsp_abs56(dest);
5459:
5460: source[2] = 0;
5461: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5462: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5463: dsp_abs56(source);
5464:
5465: newsr = dsp_sub56(source, dest);
5466:
5467: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5468:
5469: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5470: dsp_core.registers[DSP_REG_SR] |= newsr;
5471: }
5472:
5473: static void dsp_eor_x0_a(void)
5474: {
5475: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X0];
5476: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5477:
5478: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5479: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5480: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5481: }
5482:
5483: static void dsp_eor_x0_b(void)
5484: {
5485: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X0];
5486: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5487:
5488: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5489: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5490: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5491: }
5492:
5493: static void dsp_eor_y0_a(void)
5494: {
5495: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y0];
5496: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5497:
5498: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5499: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5500: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5501: }
5502:
5503: static void dsp_eor_y0_b(void)
5504: {
5505: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y0];
5506: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5507:
5508: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5509: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5510: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5511: }
5512:
5513: static void dsp_eor_x1_a(void)
5514: {
5515: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X1];
5516: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5517:
5518: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5519: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5520: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5521: }
5522:
5523: static void dsp_eor_x1_b(void)
5524: {
5525: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X1];
5526: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5527:
5528: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5529: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5530: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5531: }
5532:
5533: static void dsp_eor_y1_a(void)
5534: {
5535: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y1];
5536: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5537:
5538: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5539: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5540: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5541: }
5542:
5543: static void dsp_eor_y1_b(void)
5544: {
5545: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y1];
5546: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5547:
5548: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5549: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5550: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5551: }
5552:
5553: static void dsp_lsl_a(void)
5554: {
5555: Uint32 newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
5556:
5557: dsp_core.registers[DSP_REG_A1] <<= 1;
5558: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
5559:
5560: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5561: dsp_core.registers[DSP_REG_SR] |= newcarry;
5562: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5563: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5564: }
5565:
5566: static void dsp_lsl_b(void)
5567: {
5568: Uint32 newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
5569:
5570: dsp_core.registers[DSP_REG_B1] <<= 1;
5571: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
5572:
5573: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5574: dsp_core.registers[DSP_REG_SR] |= newcarry;
5575: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5576: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5577: }
5578:
5579: static void dsp_lsr_a(void)
5580: {
5581: Uint32 newcarry = dsp_core.registers[DSP_REG_A1] & 1;
5582: dsp_core.registers[DSP_REG_A1] >>= 1;
5583:
5584: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5585: dsp_core.registers[DSP_REG_SR] |= newcarry;
5586: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5587: }
5588:
5589: static void dsp_lsr_b(void)
5590: {
5591: Uint32 newcarry = dsp_core.registers[DSP_REG_B1] & 1;
5592: dsp_core.registers[DSP_REG_B1] >>= 1;
5593:
5594: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5595: dsp_core.registers[DSP_REG_SR] |= newcarry;
5596: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5597: }
5598:
5599: static void dsp_mac_p_x0_x0_a(void)
5600: {
5601: Uint32 source[3], dest[3];
5602: Uint16 newsr;
5603:
5604: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5605:
5606: dest[0] = dsp_core.registers[DSP_REG_A2];
5607: dest[1] = dsp_core.registers[DSP_REG_A1];
5608: dest[2] = dsp_core.registers[DSP_REG_A0];
5609: newsr = dsp_add56(source, dest);
5610:
5611: dsp_core.registers[DSP_REG_A2] = dest[0];
5612: dsp_core.registers[DSP_REG_A1] = dest[1];
5613: dsp_core.registers[DSP_REG_A0] = dest[2];
5614:
5615: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5616:
5617: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5618: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5619: }
5620:
5621: static void dsp_mac_m_x0_x0_a(void)
5622: {
5623: Uint32 source[3], dest[3];
5624: Uint16 newsr;
5625:
5626: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5627:
5628: dest[0] = dsp_core.registers[DSP_REG_A2];
5629: dest[1] = dsp_core.registers[DSP_REG_A1];
5630: dest[2] = dsp_core.registers[DSP_REG_A0];
5631: newsr = dsp_add56(source, dest);
5632:
5633: dsp_core.registers[DSP_REG_A2] = dest[0];
5634: dsp_core.registers[DSP_REG_A1] = dest[1];
5635: dsp_core.registers[DSP_REG_A0] = dest[2];
5636:
5637: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5638:
5639: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5640: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5641: }
5642: static void dsp_mac_p_x0_x0_b(void)
5643: {
5644: Uint32 source[3], dest[3];
5645: Uint16 newsr;
5646:
5647: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5648:
5649: dest[0] = dsp_core.registers[DSP_REG_B2];
5650: dest[1] = dsp_core.registers[DSP_REG_B1];
5651: dest[2] = dsp_core.registers[DSP_REG_B0];
5652: newsr = dsp_add56(source, dest);
5653:
5654: dsp_core.registers[DSP_REG_B2] = dest[0];
5655: dsp_core.registers[DSP_REG_B1] = dest[1];
5656: dsp_core.registers[DSP_REG_B0] = dest[2];
5657:
5658: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5659:
5660: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5661: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5662: }
5663:
5664: static void dsp_mac_m_x0_x0_b(void)
5665: {
5666: Uint32 source[3], dest[3];
5667: Uint16 newsr;
5668:
5669: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5670:
5671: dest[0] = dsp_core.registers[DSP_REG_B2];
5672: dest[1] = dsp_core.registers[DSP_REG_B1];
5673: dest[2] = dsp_core.registers[DSP_REG_B0];
5674: newsr = dsp_add56(source, dest);
5675:
5676: dsp_core.registers[DSP_REG_B2] = dest[0];
5677: dsp_core.registers[DSP_REG_B1] = dest[1];
5678: dsp_core.registers[DSP_REG_B0] = dest[2];
5679:
5680: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5681:
5682: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5683: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5684: }
5685:
5686: static void dsp_mac_p_y0_y0_a(void)
5687: {
5688: Uint32 source[3], dest[3];
5689: Uint16 newsr;
5690:
5691: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5692:
5693: dest[0] = dsp_core.registers[DSP_REG_A2];
5694: dest[1] = dsp_core.registers[DSP_REG_A1];
5695: dest[2] = dsp_core.registers[DSP_REG_A0];
5696: newsr = dsp_add56(source, dest);
5697:
5698: dsp_core.registers[DSP_REG_A2] = dest[0];
5699: dsp_core.registers[DSP_REG_A1] = dest[1];
5700: dsp_core.registers[DSP_REG_A0] = dest[2];
5701:
5702: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5703:
5704: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5705: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5706: }
5707:
5708: static void dsp_mac_m_y0_y0_a(void)
5709: {
5710: Uint32 source[3], dest[3];
5711: Uint16 newsr;
5712:
5713: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5714:
5715: dest[0] = dsp_core.registers[DSP_REG_A2];
5716: dest[1] = dsp_core.registers[DSP_REG_A1];
5717: dest[2] = dsp_core.registers[DSP_REG_A0];
5718: newsr = dsp_add56(source, dest);
5719:
5720: dsp_core.registers[DSP_REG_A2] = dest[0];
5721: dsp_core.registers[DSP_REG_A1] = dest[1];
5722: dsp_core.registers[DSP_REG_A0] = dest[2];
5723:
5724: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5725:
5726: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5727: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5728: }
5729: static void dsp_mac_p_y0_y0_b(void)
5730: {
5731: Uint32 source[3], dest[3];
5732: Uint16 newsr;
5733:
5734: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5735:
5736: dest[0] = dsp_core.registers[DSP_REG_B2];
5737: dest[1] = dsp_core.registers[DSP_REG_B1];
5738: dest[2] = dsp_core.registers[DSP_REG_B0];
5739: newsr = dsp_add56(source, dest);
5740:
5741: dsp_core.registers[DSP_REG_B2] = dest[0];
5742: dsp_core.registers[DSP_REG_B1] = dest[1];
5743: dsp_core.registers[DSP_REG_B0] = dest[2];
5744:
5745: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5746:
5747: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5748: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5749: }
5750:
5751: static void dsp_mac_m_y0_y0_b(void)
5752: {
5753: Uint32 source[3], dest[3];
5754: Uint16 newsr;
5755:
5756: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5757:
5758: dest[0] = dsp_core.registers[DSP_REG_B2];
5759: dest[1] = dsp_core.registers[DSP_REG_B1];
5760: dest[2] = dsp_core.registers[DSP_REG_B0];
5761: newsr = dsp_add56(source, dest);
5762:
5763: dsp_core.registers[DSP_REG_B2] = dest[0];
5764: dsp_core.registers[DSP_REG_B1] = dest[1];
5765: dsp_core.registers[DSP_REG_B0] = dest[2];
5766:
5767: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5768:
5769: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5770: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5771: }
5772:
5773: static void dsp_mac_p_x1_x0_a(void)
5774: {
5775: Uint32 source[3], dest[3];
5776: Uint16 newsr;
5777:
5778: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5779:
5780: dest[0] = dsp_core.registers[DSP_REG_A2];
5781: dest[1] = dsp_core.registers[DSP_REG_A1];
5782: dest[2] = dsp_core.registers[DSP_REG_A0];
5783: newsr = dsp_add56(source, dest);
5784:
5785: dsp_core.registers[DSP_REG_A2] = dest[0];
5786: dsp_core.registers[DSP_REG_A1] = dest[1];
5787: dsp_core.registers[DSP_REG_A0] = dest[2];
5788:
5789: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5790:
5791: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5792: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5793: }
5794:
5795: static void dsp_mac_m_x1_x0_a(void)
5796: {
5797: Uint32 source[3], dest[3];
5798: Uint16 newsr;
5799:
5800: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5801:
5802: dest[0] = dsp_core.registers[DSP_REG_A2];
5803: dest[1] = dsp_core.registers[DSP_REG_A1];
5804: dest[2] = dsp_core.registers[DSP_REG_A0];
5805: newsr = dsp_add56(source, dest);
5806:
5807: dsp_core.registers[DSP_REG_A2] = dest[0];
5808: dsp_core.registers[DSP_REG_A1] = dest[1];
5809: dsp_core.registers[DSP_REG_A0] = dest[2];
5810:
5811: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5812:
5813: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5814: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5815: }
5816:
5817: static void dsp_mac_p_x1_x0_b(void)
5818: {
5819: Uint32 source[3], dest[3];
5820: Uint16 newsr;
5821:
5822: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5823:
5824: dest[0] = dsp_core.registers[DSP_REG_B2];
5825: dest[1] = dsp_core.registers[DSP_REG_B1];
5826: dest[2] = dsp_core.registers[DSP_REG_B0];
5827: newsr = dsp_add56(source, dest);
5828:
5829: dsp_core.registers[DSP_REG_B2] = dest[0];
5830: dsp_core.registers[DSP_REG_B1] = dest[1];
5831: dsp_core.registers[DSP_REG_B0] = dest[2];
5832:
5833: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5834:
5835: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5836: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5837: }
5838:
5839: static void dsp_mac_m_x1_x0_b(void)
5840: {
5841: Uint32 source[3], dest[3];
5842: Uint16 newsr;
5843:
5844: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5845:
5846: dest[0] = dsp_core.registers[DSP_REG_B2];
5847: dest[1] = dsp_core.registers[DSP_REG_B1];
5848: dest[2] = dsp_core.registers[DSP_REG_B0];
5849: newsr = dsp_add56(source, dest);
5850:
5851: dsp_core.registers[DSP_REG_B2] = dest[0];
5852: dsp_core.registers[DSP_REG_B1] = dest[1];
5853: dsp_core.registers[DSP_REG_B0] = dest[2];
5854:
5855: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5856:
5857: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5858: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5859: }
5860:
5861: static void dsp_mac_p_y1_y0_a(void)
5862: {
5863: Uint32 source[3], dest[3];
5864: Uint16 newsr;
5865:
5866: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5867:
5868: dest[0] = dsp_core.registers[DSP_REG_A2];
5869: dest[1] = dsp_core.registers[DSP_REG_A1];
5870: dest[2] = dsp_core.registers[DSP_REG_A0];
5871: newsr = dsp_add56(source, dest);
5872:
5873: dsp_core.registers[DSP_REG_A2] = dest[0];
5874: dsp_core.registers[DSP_REG_A1] = dest[1];
5875: dsp_core.registers[DSP_REG_A0] = dest[2];
5876:
5877: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5878:
5879: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5880: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5881: }
5882:
5883: static void dsp_mac_m_y1_y0_a(void)
5884: {
5885: Uint32 source[3], dest[3];
5886: Uint16 newsr;
5887:
5888: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5889:
5890: dest[0] = dsp_core.registers[DSP_REG_A2];
5891: dest[1] = dsp_core.registers[DSP_REG_A1];
5892: dest[2] = dsp_core.registers[DSP_REG_A0];
5893: newsr = dsp_add56(source, dest);
5894:
5895: dsp_core.registers[DSP_REG_A2] = dest[0];
5896: dsp_core.registers[DSP_REG_A1] = dest[1];
5897: dsp_core.registers[DSP_REG_A0] = dest[2];
5898:
5899: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5900:
5901: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5902: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5903: }
5904:
5905: static void dsp_mac_p_y1_y0_b(void)
5906: {
5907: Uint32 source[3], dest[3];
5908: Uint16 newsr;
5909:
5910: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5911:
5912: dest[0] = dsp_core.registers[DSP_REG_B2];
5913: dest[1] = dsp_core.registers[DSP_REG_B1];
5914: dest[2] = dsp_core.registers[DSP_REG_B0];
5915: newsr = dsp_add56(source, dest);
5916:
5917: dsp_core.registers[DSP_REG_B2] = dest[0];
5918: dsp_core.registers[DSP_REG_B1] = dest[1];
5919: dsp_core.registers[DSP_REG_B0] = dest[2];
5920:
5921: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5922:
5923: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5924: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5925: }
5926:
5927: static void dsp_mac_m_y1_y0_b(void)
5928: {
5929: Uint32 source[3], dest[3];
5930: Uint16 newsr;
5931:
5932: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5933:
5934: dest[0] = dsp_core.registers[DSP_REG_B2];
5935: dest[1] = dsp_core.registers[DSP_REG_B1];
5936: dest[2] = dsp_core.registers[DSP_REG_B0];
5937: newsr = dsp_add56(source, dest);
5938:
5939: dsp_core.registers[DSP_REG_B2] = dest[0];
5940: dsp_core.registers[DSP_REG_B1] = dest[1];
5941: dsp_core.registers[DSP_REG_B0] = dest[2];
5942:
5943: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5944:
5945: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5946: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5947: }
5948:
5949: static void dsp_mac_p_x0_y1_a(void)
5950: {
5951: Uint32 source[3], dest[3];
5952: Uint16 newsr;
5953:
5954: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
5955:
5956: dest[0] = dsp_core.registers[DSP_REG_A2];
5957: dest[1] = dsp_core.registers[DSP_REG_A1];
5958: dest[2] = dsp_core.registers[DSP_REG_A0];
5959: newsr = dsp_add56(source, dest);
5960:
5961: dsp_core.registers[DSP_REG_A2] = dest[0];
5962: dsp_core.registers[DSP_REG_A1] = dest[1];
5963: dsp_core.registers[DSP_REG_A0] = dest[2];
5964:
5965: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5966:
5967: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5968: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5969: }
5970:
5971: static void dsp_mac_m_x0_y1_a(void)
5972: {
5973: Uint32 source[3], dest[3];
5974: Uint16 newsr;
5975:
5976: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
5977:
5978: dest[0] = dsp_core.registers[DSP_REG_A2];
5979: dest[1] = dsp_core.registers[DSP_REG_A1];
5980: dest[2] = dsp_core.registers[DSP_REG_A0];
5981: newsr = dsp_add56(source, dest);
5982:
5983: dsp_core.registers[DSP_REG_A2] = dest[0];
5984: dsp_core.registers[DSP_REG_A1] = dest[1];
5985: dsp_core.registers[DSP_REG_A0] = dest[2];
5986:
5987: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5988:
5989: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5990: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5991: }
5992:
5993: static void dsp_mac_p_x0_y1_b(void)
5994: {
5995: Uint32 source[3], dest[3];
5996: Uint16 newsr;
5997:
5998: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
5999:
6000: dest[0] = dsp_core.registers[DSP_REG_B2];
6001: dest[1] = dsp_core.registers[DSP_REG_B1];
6002: dest[2] = dsp_core.registers[DSP_REG_B0];
6003: newsr = dsp_add56(source, dest);
6004:
6005: dsp_core.registers[DSP_REG_B2] = dest[0];
6006: dsp_core.registers[DSP_REG_B1] = dest[1];
6007: dsp_core.registers[DSP_REG_B0] = dest[2];
6008:
6009: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6010:
6011: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6012: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6013: }
6014:
6015: static void dsp_mac_m_x0_y1_b(void)
6016: {
6017: Uint32 source[3], dest[3];
6018: Uint16 newsr;
6019:
6020: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6021:
6022: dest[0] = dsp_core.registers[DSP_REG_B2];
6023: dest[1] = dsp_core.registers[DSP_REG_B1];
6024: dest[2] = dsp_core.registers[DSP_REG_B0];
6025: newsr = dsp_add56(source, dest);
6026:
6027: dsp_core.registers[DSP_REG_B2] = dest[0];
6028: dsp_core.registers[DSP_REG_B1] = dest[1];
6029: dsp_core.registers[DSP_REG_B0] = dest[2];
6030:
6031: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6032:
6033: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6034: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6035: }
6036:
6037: static void dsp_mac_p_y0_x0_a(void)
6038: {
6039: Uint32 source[3], dest[3];
6040: Uint16 newsr;
6041:
6042: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6043:
6044: dest[0] = dsp_core.registers[DSP_REG_A2];
6045: dest[1] = dsp_core.registers[DSP_REG_A1];
6046: dest[2] = dsp_core.registers[DSP_REG_A0];
6047: newsr = dsp_add56(source, dest);
6048:
6049: dsp_core.registers[DSP_REG_A2] = dest[0];
6050: dsp_core.registers[DSP_REG_A1] = dest[1];
6051: dsp_core.registers[DSP_REG_A0] = dest[2];
6052:
6053: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6054:
6055: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6056: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6057: }
6058:
6059: static void dsp_mac_m_y0_x0_a(void)
6060: {
6061: Uint32 source[3], dest[3];
6062: Uint16 newsr;
6063:
6064: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6065:
6066: dest[0] = dsp_core.registers[DSP_REG_A2];
6067: dest[1] = dsp_core.registers[DSP_REG_A1];
6068: dest[2] = dsp_core.registers[DSP_REG_A0];
6069: newsr = dsp_add56(source, dest);
6070:
6071: dsp_core.registers[DSP_REG_A2] = dest[0];
6072: dsp_core.registers[DSP_REG_A1] = dest[1];
6073: dsp_core.registers[DSP_REG_A0] = dest[2];
6074:
6075: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6076:
6077: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6078: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6079: }
6080:
6081: static void dsp_mac_p_y0_x0_b(void)
6082: {
6083: Uint32 source[3], dest[3];
6084: Uint16 newsr;
6085:
6086: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6087:
6088: dest[0] = dsp_core.registers[DSP_REG_B2];
6089: dest[1] = dsp_core.registers[DSP_REG_B1];
6090: dest[2] = dsp_core.registers[DSP_REG_B0];
6091: newsr = dsp_add56(source, dest);
6092:
6093: dsp_core.registers[DSP_REG_B2] = dest[0];
6094: dsp_core.registers[DSP_REG_B1] = dest[1];
6095: dsp_core.registers[DSP_REG_B0] = dest[2];
6096:
6097: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6098:
6099: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6100: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6101: }
6102:
6103: static void dsp_mac_m_y0_x0_b(void)
6104: {
6105: Uint32 source[3], dest[3];
6106: Uint16 newsr;
6107:
6108: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6109:
6110: dest[0] = dsp_core.registers[DSP_REG_B2];
6111: dest[1] = dsp_core.registers[DSP_REG_B1];
6112: dest[2] = dsp_core.registers[DSP_REG_B0];
6113: newsr = dsp_add56(source, dest);
6114:
6115: dsp_core.registers[DSP_REG_B2] = dest[0];
6116: dsp_core.registers[DSP_REG_B1] = dest[1];
6117: dsp_core.registers[DSP_REG_B0] = dest[2];
6118:
6119: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6120:
6121: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6122: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6123: }
6124:
6125: static void dsp_mac_p_x1_y0_a(void)
6126: {
6127: Uint32 source[3], dest[3];
6128: Uint16 newsr;
6129:
6130: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6131:
6132: dest[0] = dsp_core.registers[DSP_REG_A2];
6133: dest[1] = dsp_core.registers[DSP_REG_A1];
6134: dest[2] = dsp_core.registers[DSP_REG_A0];
6135: newsr = dsp_add56(source, dest);
6136:
6137: dsp_core.registers[DSP_REG_A2] = dest[0];
6138: dsp_core.registers[DSP_REG_A1] = dest[1];
6139: dsp_core.registers[DSP_REG_A0] = dest[2];
6140:
6141: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6142:
6143: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6144: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6145: }
6146:
6147: static void dsp_mac_m_x1_y0_a(void)
6148: {
6149: Uint32 source[3], dest[3];
6150: Uint16 newsr;
6151:
6152: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6153:
6154: dest[0] = dsp_core.registers[DSP_REG_A2];
6155: dest[1] = dsp_core.registers[DSP_REG_A1];
6156: dest[2] = dsp_core.registers[DSP_REG_A0];
6157: newsr = dsp_add56(source, dest);
6158:
6159: dsp_core.registers[DSP_REG_A2] = dest[0];
6160: dsp_core.registers[DSP_REG_A1] = dest[1];
6161: dsp_core.registers[DSP_REG_A0] = dest[2];
6162:
6163: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6164:
6165: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6166: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6167: }
6168:
6169: static void dsp_mac_p_x1_y0_b(void)
6170: {
6171: Uint32 source[3], dest[3];
6172: Uint16 newsr;
6173:
6174: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6175:
6176: dest[0] = dsp_core.registers[DSP_REG_B2];
6177: dest[1] = dsp_core.registers[DSP_REG_B1];
6178: dest[2] = dsp_core.registers[DSP_REG_B0];
6179: newsr = dsp_add56(source, dest);
6180:
6181: dsp_core.registers[DSP_REG_B2] = dest[0];
6182: dsp_core.registers[DSP_REG_B1] = dest[1];
6183: dsp_core.registers[DSP_REG_B0] = dest[2];
6184:
6185: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6186:
6187: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6188: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6189: }
6190:
6191: static void dsp_mac_m_x1_y0_b(void)
6192: {
6193: Uint32 source[3], dest[3];
6194: Uint16 newsr;
6195:
6196: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6197:
6198: dest[0] = dsp_core.registers[DSP_REG_B2];
6199: dest[1] = dsp_core.registers[DSP_REG_B1];
6200: dest[2] = dsp_core.registers[DSP_REG_B0];
6201: newsr = dsp_add56(source, dest);
6202:
6203: dsp_core.registers[DSP_REG_B2] = dest[0];
6204: dsp_core.registers[DSP_REG_B1] = dest[1];
6205: dsp_core.registers[DSP_REG_B0] = dest[2];
6206:
6207: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6208:
6209: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6210: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6211: }
6212:
6213: static void dsp_mac_p_y1_x1_a(void)
6214: {
6215: Uint32 source[3], dest[3];
6216: Uint16 newsr;
6217:
6218: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6219:
6220: dest[0] = dsp_core.registers[DSP_REG_A2];
6221: dest[1] = dsp_core.registers[DSP_REG_A1];
6222: dest[2] = dsp_core.registers[DSP_REG_A0];
6223: newsr = dsp_add56(source, dest);
6224:
6225: dsp_core.registers[DSP_REG_A2] = dest[0];
6226: dsp_core.registers[DSP_REG_A1] = dest[1];
6227: dsp_core.registers[DSP_REG_A0] = dest[2];
6228:
6229: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6230:
6231: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6232: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6233: }
6234:
6235: static void dsp_mac_m_y1_x1_a(void)
6236: {
6237: Uint32 source[3], dest[3];
6238: Uint16 newsr;
6239:
6240: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6241:
6242: dest[0] = dsp_core.registers[DSP_REG_A2];
6243: dest[1] = dsp_core.registers[DSP_REG_A1];
6244: dest[2] = dsp_core.registers[DSP_REG_A0];
6245: newsr = dsp_add56(source, dest);
6246:
6247: dsp_core.registers[DSP_REG_A2] = dest[0];
6248: dsp_core.registers[DSP_REG_A1] = dest[1];
6249: dsp_core.registers[DSP_REG_A0] = dest[2];
6250:
6251: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6252:
6253: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6254: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6255: }
6256:
6257: static void dsp_mac_p_y1_x1_b(void)
6258: {
6259: Uint32 source[3], dest[3];
6260: Uint16 newsr;
6261:
6262: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6263:
6264: dest[0] = dsp_core.registers[DSP_REG_B2];
6265: dest[1] = dsp_core.registers[DSP_REG_B1];
6266: dest[2] = dsp_core.registers[DSP_REG_B0];
6267: newsr = dsp_add56(source, dest);
6268:
6269: dsp_core.registers[DSP_REG_B2] = dest[0];
6270: dsp_core.registers[DSP_REG_B1] = dest[1];
6271: dsp_core.registers[DSP_REG_B0] = dest[2];
6272:
6273: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6274:
6275: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6276: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6277: }
6278:
6279: static void dsp_mac_m_y1_x1_b(void)
6280: {
6281: Uint32 source[3], dest[3];
6282: Uint16 newsr;
6283:
6284: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6285:
6286: dest[0] = dsp_core.registers[DSP_REG_B2];
6287: dest[1] = dsp_core.registers[DSP_REG_B1];
6288: dest[2] = dsp_core.registers[DSP_REG_B0];
6289: newsr = dsp_add56(source, dest);
6290:
6291: dsp_core.registers[DSP_REG_B2] = dest[0];
6292: dsp_core.registers[DSP_REG_B1] = dest[1];
6293: dsp_core.registers[DSP_REG_B0] = dest[2];
6294:
6295: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6296:
6297: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6298: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6299: }
6300:
6301: static void dsp_macr_p_x0_x0_a(void)
6302: {
6303: Uint32 source[3], dest[3];
6304: Uint16 newsr;
6305:
6306: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6307:
6308: dest[0] = dsp_core.registers[DSP_REG_A2];
6309: dest[1] = dsp_core.registers[DSP_REG_A1];
6310: dest[2] = dsp_core.registers[DSP_REG_A0];
6311: newsr = dsp_add56(source, dest);
6312:
6313: dsp_rnd56(dest);
6314:
6315: dsp_core.registers[DSP_REG_A2] = dest[0];
6316: dsp_core.registers[DSP_REG_A1] = dest[1];
6317: dsp_core.registers[DSP_REG_A0] = dest[2];
6318:
6319: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6320:
6321: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6322: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6323: }
6324:
6325: static void dsp_macr_m_x0_x0_a(void)
6326: {
6327: Uint32 source[3], dest[3];
6328: Uint16 newsr;
6329:
6330: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6331:
6332: dest[0] = dsp_core.registers[DSP_REG_A2];
6333: dest[1] = dsp_core.registers[DSP_REG_A1];
6334: dest[2] = dsp_core.registers[DSP_REG_A0];
6335: newsr = dsp_add56(source, dest);
6336:
6337: dsp_rnd56(dest);
6338:
6339: dsp_core.registers[DSP_REG_A2] = dest[0];
6340: dsp_core.registers[DSP_REG_A1] = dest[1];
6341: dsp_core.registers[DSP_REG_A0] = dest[2];
6342:
6343: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6344:
6345: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6346: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6347: }
6348: static void dsp_macr_p_x0_x0_b(void)
6349: {
6350: Uint32 source[3], dest[3];
6351: Uint16 newsr;
6352:
6353: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6354:
6355: dest[0] = dsp_core.registers[DSP_REG_B2];
6356: dest[1] = dsp_core.registers[DSP_REG_B1];
6357: dest[2] = dsp_core.registers[DSP_REG_B0];
6358: newsr = dsp_add56(source, dest);
6359:
6360: dsp_rnd56(dest);
6361:
6362: dsp_core.registers[DSP_REG_B2] = dest[0];
6363: dsp_core.registers[DSP_REG_B1] = dest[1];
6364: dsp_core.registers[DSP_REG_B0] = dest[2];
6365:
6366: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6367:
6368: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6369: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6370: }
6371:
6372: static void dsp_macr_m_x0_x0_b(void)
6373: {
6374: Uint32 source[3], dest[3];
6375: Uint16 newsr;
6376:
6377: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6378:
6379: dest[0] = dsp_core.registers[DSP_REG_B2];
6380: dest[1] = dsp_core.registers[DSP_REG_B1];
6381: dest[2] = dsp_core.registers[DSP_REG_B0];
6382: newsr = dsp_add56(source, dest);
6383:
6384: dsp_rnd56(dest);
6385:
6386: dsp_core.registers[DSP_REG_B2] = dest[0];
6387: dsp_core.registers[DSP_REG_B1] = dest[1];
6388: dsp_core.registers[DSP_REG_B0] = dest[2];
6389:
6390: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6391:
6392: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6393: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6394: }
6395:
6396: static void dsp_macr_p_y0_y0_a(void)
6397: {
6398: Uint32 source[3], dest[3];
6399: Uint16 newsr;
6400:
6401: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6402:
6403: dest[0] = dsp_core.registers[DSP_REG_A2];
6404: dest[1] = dsp_core.registers[DSP_REG_A1];
6405: dest[2] = dsp_core.registers[DSP_REG_A0];
6406: newsr = dsp_add56(source, dest);
6407:
6408: dsp_rnd56(dest);
6409:
6410: dsp_core.registers[DSP_REG_A2] = dest[0];
6411: dsp_core.registers[DSP_REG_A1] = dest[1];
6412: dsp_core.registers[DSP_REG_A0] = dest[2];
6413:
6414: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6415:
6416: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6417: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6418: }
6419:
6420: static void dsp_macr_m_y0_y0_a(void)
6421: {
6422: Uint32 source[3], dest[3];
6423: Uint16 newsr;
6424:
6425: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6426:
6427: dest[0] = dsp_core.registers[DSP_REG_A2];
6428: dest[1] = dsp_core.registers[DSP_REG_A1];
6429: dest[2] = dsp_core.registers[DSP_REG_A0];
6430: newsr = dsp_add56(source, dest);
6431:
6432: dsp_rnd56(dest);
6433:
6434: dsp_core.registers[DSP_REG_A2] = dest[0];
6435: dsp_core.registers[DSP_REG_A1] = dest[1];
6436: dsp_core.registers[DSP_REG_A0] = dest[2];
6437:
6438: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6439:
6440: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6441: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6442: }
6443: static void dsp_macr_p_y0_y0_b(void)
6444: {
6445: Uint32 source[3], dest[3];
6446: Uint16 newsr;
6447:
6448: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6449:
6450: dest[0] = dsp_core.registers[DSP_REG_B2];
6451: dest[1] = dsp_core.registers[DSP_REG_B1];
6452: dest[2] = dsp_core.registers[DSP_REG_B0];
6453: newsr = dsp_add56(source, dest);
6454:
6455: dsp_rnd56(dest);
6456:
6457: dsp_core.registers[DSP_REG_B2] = dest[0];
6458: dsp_core.registers[DSP_REG_B1] = dest[1];
6459: dsp_core.registers[DSP_REG_B0] = dest[2];
6460:
6461: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6462:
6463: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6464: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6465: }
6466:
6467: static void dsp_macr_m_y0_y0_b(void)
6468: {
6469: Uint32 source[3], dest[3];
6470: Uint16 newsr;
6471:
6472: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6473:
6474: dest[0] = dsp_core.registers[DSP_REG_B2];
6475: dest[1] = dsp_core.registers[DSP_REG_B1];
6476: dest[2] = dsp_core.registers[DSP_REG_B0];
6477: newsr = dsp_add56(source, dest);
6478:
6479: dsp_rnd56(dest);
6480:
6481: dsp_core.registers[DSP_REG_B2] = dest[0];
6482: dsp_core.registers[DSP_REG_B1] = dest[1];
6483: dsp_core.registers[DSP_REG_B0] = dest[2];
6484:
6485: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6486:
6487: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6488: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6489: }
6490:
6491: static void dsp_macr_p_x1_x0_a(void)
6492: {
6493: Uint32 source[3], dest[3];
6494: Uint16 newsr;
6495:
6496: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6497:
6498: dest[0] = dsp_core.registers[DSP_REG_A2];
6499: dest[1] = dsp_core.registers[DSP_REG_A1];
6500: dest[2] = dsp_core.registers[DSP_REG_A0];
6501: newsr = dsp_add56(source, dest);
6502:
6503: dsp_rnd56(dest);
6504:
6505: dsp_core.registers[DSP_REG_A2] = dest[0];
6506: dsp_core.registers[DSP_REG_A1] = dest[1];
6507: dsp_core.registers[DSP_REG_A0] = dest[2];
6508:
6509: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6510:
6511: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6512: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6513: }
6514:
6515: static void dsp_macr_m_x1_x0_a(void)
6516: {
6517: Uint32 source[3], dest[3];
6518: Uint16 newsr;
6519:
6520: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6521:
6522: dest[0] = dsp_core.registers[DSP_REG_A2];
6523: dest[1] = dsp_core.registers[DSP_REG_A1];
6524: dest[2] = dsp_core.registers[DSP_REG_A0];
6525: newsr = dsp_add56(source, dest);
6526:
6527: dsp_rnd56(dest);
6528:
6529: dsp_core.registers[DSP_REG_A2] = dest[0];
6530: dsp_core.registers[DSP_REG_A1] = dest[1];
6531: dsp_core.registers[DSP_REG_A0] = dest[2];
6532:
6533: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6534:
6535: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6536: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6537: }
6538:
6539: static void dsp_macr_p_x1_x0_b(void)
6540: {
6541: Uint32 source[3], dest[3];
6542: Uint16 newsr;
6543:
6544: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6545:
6546: dest[0] = dsp_core.registers[DSP_REG_B2];
6547: dest[1] = dsp_core.registers[DSP_REG_B1];
6548: dest[2] = dsp_core.registers[DSP_REG_B0];
6549: newsr = dsp_add56(source, dest);
6550:
6551: dsp_rnd56(dest);
6552:
6553: dsp_core.registers[DSP_REG_B2] = dest[0];
6554: dsp_core.registers[DSP_REG_B1] = dest[1];
6555: dsp_core.registers[DSP_REG_B0] = dest[2];
6556:
6557: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6558:
6559: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6560: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6561: }
6562:
6563: static void dsp_macr_m_x1_x0_b(void)
6564: {
6565: Uint32 source[3], dest[3];
6566: Uint16 newsr;
6567:
6568: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6569:
6570: dest[0] = dsp_core.registers[DSP_REG_B2];
6571: dest[1] = dsp_core.registers[DSP_REG_B1];
6572: dest[2] = dsp_core.registers[DSP_REG_B0];
6573: newsr = dsp_add56(source, dest);
6574:
6575: dsp_rnd56(dest);
6576:
6577: dsp_core.registers[DSP_REG_B2] = dest[0];
6578: dsp_core.registers[DSP_REG_B1] = dest[1];
6579: dsp_core.registers[DSP_REG_B0] = dest[2];
6580:
6581: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6582:
6583: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6584: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6585: }
6586:
6587: static void dsp_macr_p_y1_y0_a(void)
6588: {
6589: Uint32 source[3], dest[3];
6590: Uint16 newsr;
6591:
6592: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6593:
6594: dest[0] = dsp_core.registers[DSP_REG_A2];
6595: dest[1] = dsp_core.registers[DSP_REG_A1];
6596: dest[2] = dsp_core.registers[DSP_REG_A0];
6597: newsr = dsp_add56(source, dest);
6598:
6599: dsp_rnd56(dest);
6600:
6601: dsp_core.registers[DSP_REG_A2] = dest[0];
6602: dsp_core.registers[DSP_REG_A1] = dest[1];
6603: dsp_core.registers[DSP_REG_A0] = dest[2];
6604:
6605: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6606:
6607: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6608: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6609: }
6610:
6611: static void dsp_macr_m_y1_y0_a(void)
6612: {
6613: Uint32 source[3], dest[3];
6614: Uint16 newsr;
6615:
6616: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6617:
6618: dest[0] = dsp_core.registers[DSP_REG_A2];
6619: dest[1] = dsp_core.registers[DSP_REG_A1];
6620: dest[2] = dsp_core.registers[DSP_REG_A0];
6621: newsr = dsp_add56(source, dest);
6622:
6623: dsp_rnd56(dest);
6624:
6625: dsp_core.registers[DSP_REG_A2] = dest[0];
6626: dsp_core.registers[DSP_REG_A1] = dest[1];
6627: dsp_core.registers[DSP_REG_A0] = dest[2];
6628:
6629: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6630:
6631: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6632: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6633: }
6634:
6635: static void dsp_macr_p_y1_y0_b(void)
6636: {
6637: Uint32 source[3], dest[3];
6638: Uint16 newsr;
6639:
6640: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6641:
6642: dest[0] = dsp_core.registers[DSP_REG_B2];
6643: dest[1] = dsp_core.registers[DSP_REG_B1];
6644: dest[2] = dsp_core.registers[DSP_REG_B0];
6645: newsr = dsp_add56(source, dest);
6646:
6647: dsp_rnd56(dest);
6648:
6649: dsp_core.registers[DSP_REG_B2] = dest[0];
6650: dsp_core.registers[DSP_REG_B1] = dest[1];
6651: dsp_core.registers[DSP_REG_B0] = dest[2];
6652:
6653: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6654:
6655: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6656: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6657: }
6658:
6659: static void dsp_macr_m_y1_y0_b(void)
6660: {
6661: Uint32 source[3], dest[3];
6662: Uint16 newsr;
6663:
6664: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6665:
6666: dest[0] = dsp_core.registers[DSP_REG_B2];
6667: dest[1] = dsp_core.registers[DSP_REG_B1];
6668: dest[2] = dsp_core.registers[DSP_REG_B0];
6669: newsr = dsp_add56(source, dest);
6670:
6671: dsp_rnd56(dest);
6672:
6673: dsp_core.registers[DSP_REG_B2] = dest[0];
6674: dsp_core.registers[DSP_REG_B1] = dest[1];
6675: dsp_core.registers[DSP_REG_B0] = dest[2];
6676:
6677: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6678:
6679: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6680: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6681: }
6682:
6683: static void dsp_macr_p_x0_y1_a(void)
6684: {
6685: Uint32 source[3], dest[3];
6686: Uint16 newsr;
6687:
6688: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6689:
6690: dest[0] = dsp_core.registers[DSP_REG_A2];
6691: dest[1] = dsp_core.registers[DSP_REG_A1];
6692: dest[2] = dsp_core.registers[DSP_REG_A0];
6693: newsr = dsp_add56(source, dest);
6694:
6695: dsp_rnd56(dest);
6696:
6697: dsp_core.registers[DSP_REG_A2] = dest[0];
6698: dsp_core.registers[DSP_REG_A1] = dest[1];
6699: dsp_core.registers[DSP_REG_A0] = dest[2];
6700:
6701: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6702:
6703: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6704: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6705: }
6706:
6707: static void dsp_macr_m_x0_y1_a(void)
6708: {
6709: Uint32 source[3], dest[3];
6710: Uint16 newsr;
6711:
6712: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6713:
6714: dest[0] = dsp_core.registers[DSP_REG_A2];
6715: dest[1] = dsp_core.registers[DSP_REG_A1];
6716: dest[2] = dsp_core.registers[DSP_REG_A0];
6717: newsr = dsp_add56(source, dest);
6718:
6719: dsp_rnd56(dest);
6720:
6721: dsp_core.registers[DSP_REG_A2] = dest[0];
6722: dsp_core.registers[DSP_REG_A1] = dest[1];
6723: dsp_core.registers[DSP_REG_A0] = dest[2];
6724:
6725: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6726:
6727: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6728: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6729: }
6730:
6731: static void dsp_macr_p_x0_y1_b(void)
6732: {
6733: Uint32 source[3], dest[3];
6734: Uint16 newsr;
6735:
6736: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6737:
6738: dest[0] = dsp_core.registers[DSP_REG_B2];
6739: dest[1] = dsp_core.registers[DSP_REG_B1];
6740: dest[2] = dsp_core.registers[DSP_REG_B0];
6741: newsr = dsp_add56(source, dest);
6742:
6743: dsp_rnd56(dest);
6744:
6745: dsp_core.registers[DSP_REG_B2] = dest[0];
6746: dsp_core.registers[DSP_REG_B1] = dest[1];
6747: dsp_core.registers[DSP_REG_B0] = dest[2];
6748:
6749: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6750:
6751: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6752: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6753: }
6754:
6755: static void dsp_macr_m_x0_y1_b(void)
6756: {
6757: Uint32 source[3], dest[3];
6758: Uint16 newsr;
6759:
6760: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6761:
6762: dest[0] = dsp_core.registers[DSP_REG_B2];
6763: dest[1] = dsp_core.registers[DSP_REG_B1];
6764: dest[2] = dsp_core.registers[DSP_REG_B0];
6765: newsr = dsp_add56(source, dest);
6766:
6767: dsp_rnd56(dest);
6768:
6769: dsp_core.registers[DSP_REG_B2] = dest[0];
6770: dsp_core.registers[DSP_REG_B1] = dest[1];
6771: dsp_core.registers[DSP_REG_B0] = dest[2];
6772:
6773: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6774:
6775: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6776: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6777: }
6778:
6779: static void dsp_macr_p_y0_x0_a(void)
6780: {
6781: Uint32 source[3], dest[3];
6782: Uint16 newsr;
6783:
6784: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6785:
6786: dest[0] = dsp_core.registers[DSP_REG_A2];
6787: dest[1] = dsp_core.registers[DSP_REG_A1];
6788: dest[2] = dsp_core.registers[DSP_REG_A0];
6789: newsr = dsp_add56(source, dest);
6790:
6791: dsp_rnd56(dest);
6792:
6793: dsp_core.registers[DSP_REG_A2] = dest[0];
6794: dsp_core.registers[DSP_REG_A1] = dest[1];
6795: dsp_core.registers[DSP_REG_A0] = dest[2];
6796:
6797: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6798:
6799: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6800: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6801: }
6802:
6803: static void dsp_macr_m_y0_x0_a(void)
6804: {
6805: Uint32 source[3], dest[3];
6806: Uint16 newsr;
6807:
6808: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6809:
6810: dest[0] = dsp_core.registers[DSP_REG_A2];
6811: dest[1] = dsp_core.registers[DSP_REG_A1];
6812: dest[2] = dsp_core.registers[DSP_REG_A0];
6813: newsr = dsp_add56(source, dest);
6814:
6815: dsp_rnd56(dest);
6816:
6817: dsp_core.registers[DSP_REG_A2] = dest[0];
6818: dsp_core.registers[DSP_REG_A1] = dest[1];
6819: dsp_core.registers[DSP_REG_A0] = dest[2];
6820:
6821: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6822:
6823: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6824: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6825: }
6826:
6827: static void dsp_macr_p_y0_x0_b(void)
6828: {
6829: Uint32 source[3], dest[3];
6830: Uint16 newsr;
6831:
6832: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6833:
6834: dest[0] = dsp_core.registers[DSP_REG_B2];
6835: dest[1] = dsp_core.registers[DSP_REG_B1];
6836: dest[2] = dsp_core.registers[DSP_REG_B0];
6837: newsr = dsp_add56(source, dest);
6838:
6839: dsp_rnd56(dest);
6840:
6841: dsp_core.registers[DSP_REG_B2] = dest[0];
6842: dsp_core.registers[DSP_REG_B1] = dest[1];
6843: dsp_core.registers[DSP_REG_B0] = dest[2];
6844:
6845: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6846:
6847: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6848: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6849: }
6850:
6851: static void dsp_macr_m_y0_x0_b(void)
6852: {
6853: Uint32 source[3], dest[3];
6854: Uint16 newsr;
6855:
6856: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6857:
6858: dest[0] = dsp_core.registers[DSP_REG_B2];
6859: dest[1] = dsp_core.registers[DSP_REG_B1];
6860: dest[2] = dsp_core.registers[DSP_REG_B0];
6861: newsr = dsp_add56(source, dest);
6862:
6863: dsp_rnd56(dest);
6864:
6865: dsp_core.registers[DSP_REG_B2] = dest[0];
6866: dsp_core.registers[DSP_REG_B1] = dest[1];
6867: dsp_core.registers[DSP_REG_B0] = dest[2];
6868:
6869: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6870:
6871: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6872: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6873: }
6874:
6875: static void dsp_macr_p_x1_y0_a(void)
6876: {
6877: Uint32 source[3], dest[3];
6878: Uint16 newsr;
6879:
6880: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6881:
6882: dest[0] = dsp_core.registers[DSP_REG_A2];
6883: dest[1] = dsp_core.registers[DSP_REG_A1];
6884: dest[2] = dsp_core.registers[DSP_REG_A0];
6885: newsr = dsp_add56(source, dest);
6886:
6887: dsp_rnd56(dest);
6888:
6889: dsp_core.registers[DSP_REG_A2] = dest[0];
6890: dsp_core.registers[DSP_REG_A1] = dest[1];
6891: dsp_core.registers[DSP_REG_A0] = dest[2];
6892:
6893: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6894:
6895: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6896: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6897: }
6898:
6899: static void dsp_macr_m_x1_y0_a(void)
6900: {
6901: Uint32 source[3], dest[3];
6902: Uint16 newsr;
6903:
6904: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6905:
6906: dest[0] = dsp_core.registers[DSP_REG_A2];
6907: dest[1] = dsp_core.registers[DSP_REG_A1];
6908: dest[2] = dsp_core.registers[DSP_REG_A0];
6909: newsr = dsp_add56(source, dest);
6910:
6911: dsp_rnd56(dest);
6912:
6913: dsp_core.registers[DSP_REG_A2] = dest[0];
6914: dsp_core.registers[DSP_REG_A1] = dest[1];
6915: dsp_core.registers[DSP_REG_A0] = dest[2];
6916:
6917: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6918:
6919: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6920: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6921: }
6922:
6923: static void dsp_macr_p_x1_y0_b(void)
6924: {
6925: Uint32 source[3], dest[3];
6926: Uint16 newsr;
6927:
6928: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6929:
6930: dsp_rnd56(dest);
6931:
6932: dest[0] = dsp_core.registers[DSP_REG_B2];
6933: dest[1] = dsp_core.registers[DSP_REG_B1];
6934: dest[2] = dsp_core.registers[DSP_REG_B0];
6935: newsr = dsp_add56(source, dest);
6936:
6937: dsp_core.registers[DSP_REG_B2] = dest[0];
6938: dsp_core.registers[DSP_REG_B1] = dest[1];
6939: dsp_core.registers[DSP_REG_B0] = dest[2];
6940:
6941: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6942:
6943: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6944: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6945: }
6946:
6947: static void dsp_macr_m_x1_y0_b(void)
6948: {
6949: Uint32 source[3], dest[3];
6950: Uint16 newsr;
6951:
6952: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6953:
6954: dest[0] = dsp_core.registers[DSP_REG_B2];
6955: dest[1] = dsp_core.registers[DSP_REG_B1];
6956: dest[2] = dsp_core.registers[DSP_REG_B0];
6957: newsr = dsp_add56(source, dest);
6958:
6959: dsp_rnd56(dest);
6960:
6961: dsp_core.registers[DSP_REG_B2] = dest[0];
6962: dsp_core.registers[DSP_REG_B1] = dest[1];
6963: dsp_core.registers[DSP_REG_B0] = dest[2];
6964:
6965: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6966:
6967: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6968: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6969: }
6970:
6971: static void dsp_macr_p_y1_x1_a(void)
6972: {
6973: Uint32 source[3], dest[3];
6974: Uint16 newsr;
6975:
6976: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6977:
6978: dest[0] = dsp_core.registers[DSP_REG_A2];
6979: dest[1] = dsp_core.registers[DSP_REG_A1];
6980: dest[2] = dsp_core.registers[DSP_REG_A0];
6981: newsr = dsp_add56(source, dest);
6982:
6983: dsp_rnd56(dest);
6984:
6985: dsp_core.registers[DSP_REG_A2] = dest[0];
6986: dsp_core.registers[DSP_REG_A1] = dest[1];
6987: dsp_core.registers[DSP_REG_A0] = dest[2];
6988:
6989: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6990:
6991: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6992: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6993: }
6994:
6995: static void dsp_macr_m_y1_x1_a(void)
6996: {
6997: Uint32 source[3], dest[3];
6998: Uint16 newsr;
6999:
7000: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7001:
7002: dest[0] = dsp_core.registers[DSP_REG_A2];
7003: dest[1] = dsp_core.registers[DSP_REG_A1];
7004: dest[2] = dsp_core.registers[DSP_REG_A0];
7005: newsr = dsp_add56(source, dest);
7006:
7007: dsp_rnd56(dest);
7008:
7009: dsp_core.registers[DSP_REG_A2] = dest[0];
7010: dsp_core.registers[DSP_REG_A1] = dest[1];
7011: dsp_core.registers[DSP_REG_A0] = dest[2];
7012:
7013: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7014:
7015: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7016: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7017: }
7018:
7019: static void dsp_macr_p_y1_x1_b(void)
7020: {
7021: Uint32 source[3], dest[3];
7022: Uint16 newsr;
7023:
7024: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7025:
7026: dest[0] = dsp_core.registers[DSP_REG_B2];
7027: dest[1] = dsp_core.registers[DSP_REG_B1];
7028: dest[2] = dsp_core.registers[DSP_REG_B0];
7029: newsr = dsp_add56(source, dest);
7030:
7031: dsp_rnd56(dest);
7032:
7033: dsp_core.registers[DSP_REG_B2] = dest[0];
7034: dsp_core.registers[DSP_REG_B1] = dest[1];
7035: dsp_core.registers[DSP_REG_B0] = dest[2];
7036:
7037: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7038:
7039: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7040: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7041: }
7042:
7043: static void dsp_macr_m_y1_x1_b(void)
7044: {
7045: Uint32 source[3], dest[3];
7046: Uint16 newsr;
7047:
7048: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7049:
7050: dest[0] = dsp_core.registers[DSP_REG_B2];
7051: dest[1] = dsp_core.registers[DSP_REG_B1];
7052: dest[2] = dsp_core.registers[DSP_REG_B0];
7053: newsr = dsp_add56(source, dest);
7054:
7055: dsp_rnd56(dest);
7056:
7057: dsp_core.registers[DSP_REG_B2] = dest[0];
7058: dsp_core.registers[DSP_REG_B1] = dest[1];
7059: dsp_core.registers[DSP_REG_B0] = dest[2];
7060:
7061: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7062:
7063: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7064: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7065: }
7066:
7067:
7068: static void dsp_move(void)
7069: {
7070: /* move instruction inside alu opcodes
7071: taken care of by parallel move dispatcher */
7072: }
7073:
7074: static void dsp_mpy_p_x0_x0_a(void)
7075: {
7076: Uint32 source[3];
7077:
7078: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7079:
7080: dsp_core.registers[DSP_REG_A2] = source[0];
7081: dsp_core.registers[DSP_REG_A1] = source[1];
7082: dsp_core.registers[DSP_REG_A0] = source[2];
7083:
7084: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7085: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7086: }
7087:
7088: static void dsp_mpy_m_x0_x0_a(void)
7089: {
7090: Uint32 source[3];
7091:
7092: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7093:
7094: dsp_core.registers[DSP_REG_A2] = source[0];
7095: dsp_core.registers[DSP_REG_A1] = source[1];
7096: dsp_core.registers[DSP_REG_A0] = source[2];
7097:
7098: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7099: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7100: }
7101:
7102: static void dsp_mpy_p_x0_x0_b(void)
7103: {
7104: Uint32 source[3];
7105:
7106: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7107:
7108: dsp_core.registers[DSP_REG_B2] = source[0];
7109: dsp_core.registers[DSP_REG_B1] = source[1];
7110: dsp_core.registers[DSP_REG_B0] = source[2];
7111:
7112: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7113: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7114: }
7115:
7116: static void dsp_mpy_m_x0_x0_b(void)
7117: {
7118: Uint32 source[3];
7119:
7120:
7121: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7122:
7123: dsp_core.registers[DSP_REG_B2] = source[0];
7124: dsp_core.registers[DSP_REG_B1] = source[1];
7125: dsp_core.registers[DSP_REG_B0] = source[2];
7126:
7127: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7128: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7129: }
7130:
7131: static void dsp_mpy_p_y0_y0_a(void)
7132: {
7133: Uint32 source[3];
7134:
7135: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7136:
7137: dsp_core.registers[DSP_REG_A2] = source[0];
7138: dsp_core.registers[DSP_REG_A1] = source[1];
7139: dsp_core.registers[DSP_REG_A0] = source[2];
7140:
7141: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7142: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7143: }
7144:
7145: static void dsp_mpy_m_y0_y0_a(void)
7146: {
7147: Uint32 source[3];
7148:
7149: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7150:
7151: dsp_core.registers[DSP_REG_A2] = source[0];
7152: dsp_core.registers[DSP_REG_A1] = source[1];
7153: dsp_core.registers[DSP_REG_A0] = source[2];
7154:
7155: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7156: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7157: }
7158:
7159: static void dsp_mpy_p_y0_y0_b(void)
7160: {
7161: Uint32 source[3];
7162:
7163: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7164:
7165: dsp_core.registers[DSP_REG_B2] = source[0];
7166: dsp_core.registers[DSP_REG_B1] = source[1];
7167: dsp_core.registers[DSP_REG_B0] = source[2];
7168:
7169: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7170: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7171: }
7172:
7173: static void dsp_mpy_m_y0_y0_b(void)
7174: {
7175: Uint32 source[3];
7176:
7177: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7178:
7179: dsp_core.registers[DSP_REG_B2] = source[0];
7180: dsp_core.registers[DSP_REG_B1] = source[1];
7181: dsp_core.registers[DSP_REG_B0] = source[2];
7182:
7183: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7184: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7185: }
7186:
7187: static void dsp_mpy_p_x1_x0_a(void)
7188: {
7189: Uint32 source[3];
7190:
7191: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7192:
7193: dsp_core.registers[DSP_REG_A2] = source[0];
7194: dsp_core.registers[DSP_REG_A1] = source[1];
7195: dsp_core.registers[DSP_REG_A0] = source[2];
7196:
7197: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7198: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7199: }
7200:
7201: static void dsp_mpy_m_x1_x0_a(void)
7202: {
7203: Uint32 source[3];
7204:
7205: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7206:
7207: dsp_core.registers[DSP_REG_A2] = source[0];
7208: dsp_core.registers[DSP_REG_A1] = source[1];
7209: dsp_core.registers[DSP_REG_A0] = source[2];
7210:
7211: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7212: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7213: }
7214:
7215: static void dsp_mpy_p_x1_x0_b(void)
7216: {
7217: Uint32 source[3];
7218:
7219: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7220:
7221: dsp_core.registers[DSP_REG_B2] = source[0];
7222: dsp_core.registers[DSP_REG_B1] = source[1];
7223: dsp_core.registers[DSP_REG_B0] = source[2];
7224:
7225: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7226: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7227: }
7228:
7229: static void dsp_mpy_m_x1_x0_b(void)
7230: {
7231: Uint32 source[3];
7232:
7233: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7234:
7235: dsp_core.registers[DSP_REG_B2] = source[0];
7236: dsp_core.registers[DSP_REG_B1] = source[1];
7237: dsp_core.registers[DSP_REG_B0] = source[2];
7238:
7239: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7240: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7241: }
7242:
7243: static void dsp_mpy_p_y1_y0_a(void)
7244: {
7245: Uint32 source[3];
7246:
7247: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7248:
7249: dsp_core.registers[DSP_REG_A2] = source[0];
7250: dsp_core.registers[DSP_REG_A1] = source[1];
7251: dsp_core.registers[DSP_REG_A0] = source[2];
7252:
7253: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7254: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7255: }
7256:
7257: static void dsp_mpy_m_y1_y0_a(void)
7258: {
7259: Uint32 source[3];
7260:
7261: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7262:
7263: dsp_core.registers[DSP_REG_A2] = source[0];
7264: dsp_core.registers[DSP_REG_A1] = source[1];
7265: dsp_core.registers[DSP_REG_A0] = source[2];
7266:
7267: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7268: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7269: }
7270:
7271: static void dsp_mpy_p_y1_y0_b(void)
7272: {
7273: Uint32 source[3];
7274:
7275: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7276:
7277: dsp_core.registers[DSP_REG_B2] = source[0];
7278: dsp_core.registers[DSP_REG_B1] = source[1];
7279: dsp_core.registers[DSP_REG_B0] = source[2];
7280:
7281: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7282: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7283: }
7284:
7285: static void dsp_mpy_m_y1_y0_b(void)
7286: {
7287: Uint32 source[3];
7288:
7289: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7290:
7291: dsp_core.registers[DSP_REG_B2] = source[0];
7292: dsp_core.registers[DSP_REG_B1] = source[1];
7293: dsp_core.registers[DSP_REG_B0] = source[2];
7294:
7295: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7296: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7297: }
7298:
7299: static void dsp_mpy_p_x0_y1_a(void)
7300: {
7301: Uint32 source[3];
7302:
7303: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7304:
7305: dsp_core.registers[DSP_REG_A2] = source[0];
7306: dsp_core.registers[DSP_REG_A1] = source[1];
7307: dsp_core.registers[DSP_REG_A0] = source[2];
7308:
7309: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7310: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7311: }
7312:
7313: static void dsp_mpy_m_x0_y1_a(void)
7314: {
7315: Uint32 source[3];
7316:
7317: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7318:
7319: dsp_core.registers[DSP_REG_A2] = source[0];
7320: dsp_core.registers[DSP_REG_A1] = source[1];
7321: dsp_core.registers[DSP_REG_A0] = source[2];
7322:
7323: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7324: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7325: }
7326:
7327: static void dsp_mpy_p_x0_y1_b(void)
7328: {
7329: Uint32 source[3];
7330:
7331: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7332:
7333: dsp_core.registers[DSP_REG_B2] = source[0];
7334: dsp_core.registers[DSP_REG_B1] = source[1];
7335: dsp_core.registers[DSP_REG_B0] = source[2];
7336:
7337: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7338: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7339: }
7340:
7341: static void dsp_mpy_m_x0_y1_b(void)
7342: {
7343: Uint32 source[3];
7344:
7345: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7346:
7347: dsp_core.registers[DSP_REG_B2] = source[0];
7348: dsp_core.registers[DSP_REG_B1] = source[1];
7349: dsp_core.registers[DSP_REG_B0] = source[2];
7350:
7351: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7352: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7353: }
7354:
7355: static void dsp_mpy_p_y0_x0_a(void)
7356: {
7357: Uint32 source[3];
7358:
7359: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7360:
7361: dsp_core.registers[DSP_REG_A2] = source[0];
7362: dsp_core.registers[DSP_REG_A1] = source[1];
7363: dsp_core.registers[DSP_REG_A0] = source[2];
7364:
7365: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7366: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7367: }
7368:
7369: static void dsp_mpy_m_y0_x0_a(void)
7370: {
7371: Uint32 source[3];
7372:
7373: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7374:
7375: dsp_core.registers[DSP_REG_A2] = source[0];
7376: dsp_core.registers[DSP_REG_A1] = source[1];
7377: dsp_core.registers[DSP_REG_A0] = source[2];
7378:
7379: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7380: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7381: }
7382:
7383: static void dsp_mpy_p_y0_x0_b(void)
7384: {
7385: Uint32 source[3];
7386:
7387: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7388:
7389: dsp_core.registers[DSP_REG_B2] = source[0];
7390: dsp_core.registers[DSP_REG_B1] = source[1];
7391: dsp_core.registers[DSP_REG_B0] = source[2];
7392:
7393: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7394: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7395: }
7396:
7397: static void dsp_mpy_m_y0_x0_b(void)
7398: {
7399: Uint32 source[3];
7400:
7401: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7402:
7403: dsp_core.registers[DSP_REG_B2] = source[0];
7404: dsp_core.registers[DSP_REG_B1] = source[1];
7405: dsp_core.registers[DSP_REG_B0] = source[2];
7406:
7407: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7408: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7409: }
7410:
7411: static void dsp_mpy_p_x1_y0_a(void)
7412: {
7413: Uint32 source[3];
7414:
7415: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7416:
7417: dsp_core.registers[DSP_REG_A2] = source[0];
7418: dsp_core.registers[DSP_REG_A1] = source[1];
7419: dsp_core.registers[DSP_REG_A0] = source[2];
7420:
7421: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7422: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7423: }
7424:
7425: static void dsp_mpy_m_x1_y0_a(void)
7426: {
7427: Uint32 source[3];
7428:
7429: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7430:
7431: dsp_core.registers[DSP_REG_A2] = source[0];
7432: dsp_core.registers[DSP_REG_A1] = source[1];
7433: dsp_core.registers[DSP_REG_A0] = source[2];
7434:
7435: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7436: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7437: }
7438:
7439: static void dsp_mpy_p_x1_y0_b(void)
7440: {
7441: Uint32 source[3];
7442:
7443: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7444:
7445: dsp_core.registers[DSP_REG_B2] = source[0];
7446: dsp_core.registers[DSP_REG_B1] = source[1];
7447: dsp_core.registers[DSP_REG_B0] = source[2];
7448:
7449: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7450: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7451: }
7452:
7453: static void dsp_mpy_m_x1_y0_b(void)
7454: {
7455: Uint32 source[3];
7456:
7457: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7458:
7459: dsp_core.registers[DSP_REG_B2] = source[0];
7460: dsp_core.registers[DSP_REG_B1] = source[1];
7461: dsp_core.registers[DSP_REG_B0] = source[2];
7462:
7463: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7464: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7465: }
7466:
7467: static void dsp_mpy_p_y1_x1_a(void)
7468: {
7469: Uint32 source[3];
7470:
7471: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7472:
7473: dsp_core.registers[DSP_REG_A2] = source[0];
7474: dsp_core.registers[DSP_REG_A1] = source[1];
7475: dsp_core.registers[DSP_REG_A0] = source[2];
7476:
7477: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7478: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7479: }
7480:
7481: static void dsp_mpy_m_y1_x1_a(void)
7482: {
7483: Uint32 source[3];
7484:
7485: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7486:
7487: dsp_core.registers[DSP_REG_A2] = source[0];
7488: dsp_core.registers[DSP_REG_A1] = source[1];
7489: dsp_core.registers[DSP_REG_A0] = source[2];
7490:
7491: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7492: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7493: }
7494:
7495: static void dsp_mpy_p_y1_x1_b(void)
7496: {
7497: Uint32 source[3];
7498:
7499: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7500:
7501: dsp_core.registers[DSP_REG_B2] = source[0];
7502: dsp_core.registers[DSP_REG_B1] = source[1];
7503: dsp_core.registers[DSP_REG_B0] = source[2];
7504:
7505: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7506: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7507: }
7508:
7509: static void dsp_mpy_m_y1_x1_b(void)
7510: {
7511: Uint32 source[3];
7512:
7513: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7514:
7515: dsp_core.registers[DSP_REG_B2] = source[0];
7516: dsp_core.registers[DSP_REG_B1] = source[1];
7517: dsp_core.registers[DSP_REG_B0] = source[2];
7518:
7519: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7520: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7521: }
7522:
7523: static void dsp_mpyr_p_x0_x0_a(void)
7524: {
7525: Uint32 source[3];
7526:
7527: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7528: dsp_rnd56(source);
7529:
7530: dsp_core.registers[DSP_REG_A2] = source[0];
7531: dsp_core.registers[DSP_REG_A1] = source[1];
7532: dsp_core.registers[DSP_REG_A0] = source[2];
7533:
7534: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7535: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7536: }
7537:
7538: static void dsp_mpyr_m_x0_x0_a(void)
7539: {
7540: Uint32 source[3];
7541:
7542: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7543: dsp_rnd56(source);
7544:
7545: dsp_core.registers[DSP_REG_A2] = source[0];
7546: dsp_core.registers[DSP_REG_A1] = source[1];
7547: dsp_core.registers[DSP_REG_A0] = source[2];
7548:
7549: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7550: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7551: }
7552:
7553: static void dsp_mpyr_p_x0_x0_b(void)
7554: {
7555: Uint32 source[3];
7556:
7557: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7558: dsp_rnd56(source);
7559:
7560: dsp_core.registers[DSP_REG_B2] = source[0];
7561: dsp_core.registers[DSP_REG_B1] = source[1];
7562: dsp_core.registers[DSP_REG_B0] = source[2];
7563:
7564: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7565: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7566: }
7567:
7568: static void dsp_mpyr_m_x0_x0_b(void)
7569: {
7570: Uint32 source[3];
7571:
7572:
7573: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7574: dsp_rnd56(source);
7575:
7576: dsp_core.registers[DSP_REG_B2] = source[0];
7577: dsp_core.registers[DSP_REG_B1] = source[1];
7578: dsp_core.registers[DSP_REG_B0] = source[2];
7579:
7580: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7581: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7582: }
7583:
7584: static void dsp_mpyr_p_y0_y0_a(void)
7585: {
7586: Uint32 source[3];
7587:
7588: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7589: dsp_rnd56(source);
7590:
7591: dsp_core.registers[DSP_REG_A2] = source[0];
7592: dsp_core.registers[DSP_REG_A1] = source[1];
7593: dsp_core.registers[DSP_REG_A0] = source[2];
7594:
7595: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7596: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7597: }
7598:
7599: static void dsp_mpyr_m_y0_y0_a(void)
7600: {
7601: Uint32 source[3];
7602:
7603: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7604: dsp_rnd56(source);
7605:
7606: dsp_core.registers[DSP_REG_A2] = source[0];
7607: dsp_core.registers[DSP_REG_A1] = source[1];
7608: dsp_core.registers[DSP_REG_A0] = source[2];
7609:
7610: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7611: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7612: }
7613:
7614: static void dsp_mpyr_p_y0_y0_b(void)
7615: {
7616: Uint32 source[3];
7617:
7618: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7619: dsp_rnd56(source);
7620:
7621: dsp_core.registers[DSP_REG_B2] = source[0];
7622: dsp_core.registers[DSP_REG_B1] = source[1];
7623: dsp_core.registers[DSP_REG_B0] = source[2];
7624:
7625: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7626: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7627: }
7628:
7629: static void dsp_mpyr_m_y0_y0_b(void)
7630: {
7631: Uint32 source[3];
7632:
7633: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7634: dsp_rnd56(source);
7635:
7636: dsp_core.registers[DSP_REG_B2] = source[0];
7637: dsp_core.registers[DSP_REG_B1] = source[1];
7638: dsp_core.registers[DSP_REG_B0] = source[2];
7639:
7640: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7641: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7642: }
7643:
7644: static void dsp_mpyr_p_x1_x0_a(void)
7645: {
7646: Uint32 source[3];
7647:
7648: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7649: dsp_rnd56(source);
7650:
7651: dsp_core.registers[DSP_REG_A2] = source[0];
7652: dsp_core.registers[DSP_REG_A1] = source[1];
7653: dsp_core.registers[DSP_REG_A0] = source[2];
7654:
7655: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7656: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7657: }
7658:
7659: static void dsp_mpyr_m_x1_x0_a(void)
7660: {
7661: Uint32 source[3];
7662:
7663: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7664: dsp_rnd56(source);
7665:
7666: dsp_core.registers[DSP_REG_A2] = source[0];
7667: dsp_core.registers[DSP_REG_A1] = source[1];
7668: dsp_core.registers[DSP_REG_A0] = source[2];
7669:
7670: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7671: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7672: }
7673:
7674: static void dsp_mpyr_p_x1_x0_b(void)
7675: {
7676: Uint32 source[3];
7677:
7678: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7679: dsp_rnd56(source);
7680:
7681: dsp_core.registers[DSP_REG_B2] = source[0];
7682: dsp_core.registers[DSP_REG_B1] = source[1];
7683: dsp_core.registers[DSP_REG_B0] = source[2];
7684:
7685: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7686: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7687: }
7688:
7689: static void dsp_mpyr_m_x1_x0_b(void)
7690: {
7691: Uint32 source[3];
7692:
7693: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7694: dsp_rnd56(source);
7695:
7696: dsp_core.registers[DSP_REG_B2] = source[0];
7697: dsp_core.registers[DSP_REG_B1] = source[1];
7698: dsp_core.registers[DSP_REG_B0] = source[2];
7699:
7700: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7701: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7702: }
7703:
7704: static void dsp_mpyr_p_y1_y0_a(void)
7705: {
7706: Uint32 source[3];
7707:
7708: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7709: dsp_rnd56(source);
7710:
7711: dsp_core.registers[DSP_REG_A2] = source[0];
7712: dsp_core.registers[DSP_REG_A1] = source[1];
7713: dsp_core.registers[DSP_REG_A0] = source[2];
7714:
7715: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7716: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7717: }
7718:
7719: static void dsp_mpyr_m_y1_y0_a(void)
7720: {
7721: Uint32 source[3];
7722:
7723: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7724: dsp_rnd56(source);
7725:
7726: dsp_core.registers[DSP_REG_A2] = source[0];
7727: dsp_core.registers[DSP_REG_A1] = source[1];
7728: dsp_core.registers[DSP_REG_A0] = source[2];
7729:
7730: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7731: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7732: }
7733:
7734: static void dsp_mpyr_p_y1_y0_b(void)
7735: {
7736: Uint32 source[3];
7737:
7738: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7739: dsp_rnd56(source);
7740:
7741: dsp_core.registers[DSP_REG_B2] = source[0];
7742: dsp_core.registers[DSP_REG_B1] = source[1];
7743: dsp_core.registers[DSP_REG_B0] = source[2];
7744:
7745: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7746: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7747: }
7748:
7749: static void dsp_mpyr_m_y1_y0_b(void)
7750: {
7751: Uint32 source[3];
7752:
7753: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7754: dsp_rnd56(source);
7755:
7756: dsp_core.registers[DSP_REG_B2] = source[0];
7757: dsp_core.registers[DSP_REG_B1] = source[1];
7758: dsp_core.registers[DSP_REG_B0] = source[2];
7759:
7760: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7761: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7762: }
7763:
7764: static void dsp_mpyr_p_x0_y1_a(void)
7765: {
7766: Uint32 source[3];
7767:
7768: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7769: dsp_rnd56(source);
7770:
7771: dsp_core.registers[DSP_REG_A2] = source[0];
7772: dsp_core.registers[DSP_REG_A1] = source[1];
7773: dsp_core.registers[DSP_REG_A0] = source[2];
7774:
7775: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7776: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7777: }
7778:
7779: static void dsp_mpyr_m_x0_y1_a(void)
7780: {
7781: Uint32 source[3];
7782:
7783: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7784: dsp_rnd56(source);
7785:
7786: dsp_core.registers[DSP_REG_A2] = source[0];
7787: dsp_core.registers[DSP_REG_A1] = source[1];
7788: dsp_core.registers[DSP_REG_A0] = source[2];
7789:
7790: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7791: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7792: }
7793:
7794: static void dsp_mpyr_p_x0_y1_b(void)
7795: {
7796: Uint32 source[3];
7797:
7798: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7799: dsp_rnd56(source);
7800:
7801: dsp_core.registers[DSP_REG_B2] = source[0];
7802: dsp_core.registers[DSP_REG_B1] = source[1];
7803: dsp_core.registers[DSP_REG_B0] = source[2];
7804:
7805: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7806: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7807: }
7808:
7809: static void dsp_mpyr_m_x0_y1_b(void)
7810: {
7811: Uint32 source[3];
7812:
7813: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7814: dsp_rnd56(source);
7815:
7816: dsp_core.registers[DSP_REG_B2] = source[0];
7817: dsp_core.registers[DSP_REG_B1] = source[1];
7818: dsp_core.registers[DSP_REG_B0] = source[2];
7819:
7820: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7821: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7822: }
7823:
7824: static void dsp_mpyr_p_y0_x0_a(void)
7825: {
7826: Uint32 source[3];
7827:
7828: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7829: dsp_rnd56(source);
7830:
7831: dsp_core.registers[DSP_REG_A2] = source[0];
7832: dsp_core.registers[DSP_REG_A1] = source[1];
7833: dsp_core.registers[DSP_REG_A0] = source[2];
7834:
7835: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7836: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7837: }
7838:
7839: static void dsp_mpyr_m_y0_x0_a(void)
7840: {
7841: Uint32 source[3];
7842:
7843: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7844: dsp_rnd56(source);
7845:
7846: dsp_core.registers[DSP_REG_A2] = source[0];
7847: dsp_core.registers[DSP_REG_A1] = source[1];
7848: dsp_core.registers[DSP_REG_A0] = source[2];
7849:
7850: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7851: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7852: }
7853:
7854: static void dsp_mpyr_p_y0_x0_b(void)
7855: {
7856: Uint32 source[3];
7857:
7858: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7859: dsp_rnd56(source);
7860:
7861: dsp_core.registers[DSP_REG_B2] = source[0];
7862: dsp_core.registers[DSP_REG_B1] = source[1];
7863: dsp_core.registers[DSP_REG_B0] = source[2];
7864:
7865: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7866: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7867: }
7868:
7869: static void dsp_mpyr_m_y0_x0_b(void)
7870: {
7871: Uint32 source[3];
7872:
7873: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7874: dsp_rnd56(source);
7875:
7876: dsp_core.registers[DSP_REG_B2] = source[0];
7877: dsp_core.registers[DSP_REG_B1] = source[1];
7878: dsp_core.registers[DSP_REG_B0] = source[2];
7879:
7880: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7881: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7882: }
7883:
7884: static void dsp_mpyr_p_x1_y0_a(void)
7885: {
7886: Uint32 source[3];
7887:
7888: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7889: dsp_rnd56(source);
7890:
7891: dsp_core.registers[DSP_REG_A2] = source[0];
7892: dsp_core.registers[DSP_REG_A1] = source[1];
7893: dsp_core.registers[DSP_REG_A0] = source[2];
7894:
7895: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7896: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7897: }
7898:
7899: static void dsp_mpyr_m_x1_y0_a(void)
7900: {
7901: Uint32 source[3];
7902:
7903: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7904: dsp_rnd56(source);
7905:
7906: dsp_core.registers[DSP_REG_A2] = source[0];
7907: dsp_core.registers[DSP_REG_A1] = source[1];
7908: dsp_core.registers[DSP_REG_A0] = source[2];
7909:
7910: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7911: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7912: }
7913:
7914: static void dsp_mpyr_p_x1_y0_b(void)
7915: {
7916: Uint32 source[3];
7917:
7918: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7919: dsp_rnd56(source);
7920:
7921: dsp_core.registers[DSP_REG_B2] = source[0];
7922: dsp_core.registers[DSP_REG_B1] = source[1];
7923: dsp_core.registers[DSP_REG_B0] = source[2];
7924:
7925: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7926: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7927: }
7928:
7929: static void dsp_mpyr_m_x1_y0_b(void)
7930: {
7931: Uint32 source[3];
7932:
7933: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7934: dsp_rnd56(source);
7935:
7936: dsp_core.registers[DSP_REG_B2] = source[0];
7937: dsp_core.registers[DSP_REG_B1] = source[1];
7938: dsp_core.registers[DSP_REG_B0] = source[2];
7939:
7940: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7941: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7942: }
7943:
7944: static void dsp_mpyr_p_y1_x1_a(void)
7945: {
7946: Uint32 source[3];
7947:
7948: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7949: dsp_rnd56(source);
7950:
7951: dsp_core.registers[DSP_REG_A2] = source[0];
7952: dsp_core.registers[DSP_REG_A1] = source[1];
7953: dsp_core.registers[DSP_REG_A0] = source[2];
7954:
7955: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7956: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7957: }
7958:
7959: static void dsp_mpyr_m_y1_x1_a(void)
7960: {
7961: Uint32 source[3];
7962:
7963: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7964: dsp_rnd56(source);
7965:
7966: dsp_core.registers[DSP_REG_A2] = source[0];
7967: dsp_core.registers[DSP_REG_A1] = source[1];
7968: dsp_core.registers[DSP_REG_A0] = source[2];
7969:
7970: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7971: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7972: }
7973:
7974: static void dsp_mpyr_p_y1_x1_b(void)
7975: {
7976: Uint32 source[3];
7977:
7978: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7979: dsp_rnd56(source);
7980:
7981: dsp_core.registers[DSP_REG_B2] = source[0];
7982: dsp_core.registers[DSP_REG_B1] = source[1];
7983: dsp_core.registers[DSP_REG_B0] = source[2];
7984:
7985: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7986: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7987: }
7988:
7989: static void dsp_mpyr_m_y1_x1_b(void)
7990: {
7991: Uint32 source[3];
7992:
7993: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7994: dsp_rnd56(source);
7995:
7996: dsp_core.registers[DSP_REG_B2] = source[0];
7997: dsp_core.registers[DSP_REG_B1] = source[1];
7998: dsp_core.registers[DSP_REG_B0] = source[2];
7999:
8000: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8001: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8002: }
8003:
8004: static void dsp_neg_a(void)
8005: {
8006: Uint32 source[3], dest[3], overflowed;
8007:
8008: source[0] = dsp_core.registers[DSP_REG_A2];
8009: source[1] = dsp_core.registers[DSP_REG_A1];
8010: source[2] = dsp_core.registers[DSP_REG_A0];
8011:
8012: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8013:
8014: dest[0] = dest[1] = dest[2] = 0;
8015:
8016: dsp_sub56(source, dest);
8017:
8018: dsp_core.registers[DSP_REG_A2] = dest[0];
8019: dsp_core.registers[DSP_REG_A1] = dest[1];
8020: dsp_core.registers[DSP_REG_A0] = dest[2];
8021:
8022: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8023: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8024:
8025: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8026: }
8027:
8028: static void dsp_neg_b(void)
8029: {
8030: Uint32 source[3], dest[3], overflowed;
8031:
8032: source[0] = dsp_core.registers[DSP_REG_B2];
8033: source[1] = dsp_core.registers[DSP_REG_B1];
8034: source[2] = dsp_core.registers[DSP_REG_B0];
8035:
8036: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8037:
8038: dest[0] = dest[1] = dest[2] = 0;
8039:
8040: dsp_sub56(source, dest);
8041:
8042: dsp_core.registers[DSP_REG_B2] = dest[0];
8043: dsp_core.registers[DSP_REG_B1] = dest[1];
8044: dsp_core.registers[DSP_REG_B0] = dest[2];
8045:
8046: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8047: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8048:
8049: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8050: }
8051:
8052: static void dsp_nop(void)
8053: {
8054: }
8055:
8056: static void dsp_not_a(void)
8057: {
8058: dsp_core.registers[DSP_REG_A1] = ~dsp_core.registers[DSP_REG_A1];
8059: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8060:
8061: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8062: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8063: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8064: }
8065:
8066: static void dsp_not_b(void)
8067: {
8068: dsp_core.registers[DSP_REG_B1] = ~dsp_core.registers[DSP_REG_B1];
8069: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8070:
8071: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8072: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8073: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8074: }
8075:
8076: static void dsp_or_x0_a(void)
8077: {
8078: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X0];
8079: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8080:
8081: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8082: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8083: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8084: }
8085:
8086: static void dsp_or_x0_b(void)
8087: {
8088: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X0];
8089: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8090:
8091: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8092: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8093: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8094: }
8095:
8096: static void dsp_or_y0_a(void)
8097: {
8098: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y0];
8099: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8100:
8101: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8102: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8103: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8104: }
8105:
8106: static void dsp_or_y0_b(void)
8107: {
8108: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y0];
8109: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8110:
8111: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8112: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8113: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8114: }
8115:
8116: static void dsp_or_x1_a(void)
8117: {
8118: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X1];
8119: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8120:
8121: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8122: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8123: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8124: }
8125:
8126: static void dsp_or_x1_b(void)
8127: {
8128: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X1];
8129: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8130:
8131: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8132: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8133: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8134: }
8135:
8136: static void dsp_or_y1_a(void)
8137: {
8138: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y1];
8139: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8140:
8141: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8142: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8143: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8144: }
8145:
8146: static void dsp_or_y1_b(void)
8147: {
8148: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y1];
8149: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8150:
8151: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8152: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8153: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8154: }
8155:
8156: static void dsp_rnd_a(void)
8157: {
8158: Uint32 dest[3];
8159:
8160: dest[0] = dsp_core.registers[DSP_REG_A2];
8161: dest[1] = dsp_core.registers[DSP_REG_A1];
8162: dest[2] = dsp_core.registers[DSP_REG_A0];
8163:
8164: dsp_rnd56(dest);
8165:
8166: dsp_core.registers[DSP_REG_A2] = dest[0];
8167: dsp_core.registers[DSP_REG_A1] = dest[1];
8168: dsp_core.registers[DSP_REG_A0] = dest[2];
8169:
8170: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8171: }
8172:
8173: static void dsp_rnd_b(void)
8174: {
8175: Uint32 dest[3];
8176:
8177: dest[0] = dsp_core.registers[DSP_REG_B2];
8178: dest[1] = dsp_core.registers[DSP_REG_B1];
8179: dest[2] = dsp_core.registers[DSP_REG_B0];
8180:
8181: dsp_rnd56(dest);
8182:
8183: dsp_core.registers[DSP_REG_B2] = dest[0];
8184: dsp_core.registers[DSP_REG_B1] = dest[1];
8185: dsp_core.registers[DSP_REG_B0] = dest[2];
8186:
8187: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8188: }
8189:
8190: static void dsp_rol_a(void)
8191: {
8192: Uint32 newcarry;
8193:
8194: newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
8195:
8196: dsp_core.registers[DSP_REG_A1] <<= 1;
8197: dsp_core.registers[DSP_REG_A1] |= newcarry;
8198: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
8199:
8200: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8201: dsp_core.registers[DSP_REG_SR] |= newcarry;
8202: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8203: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8204: }
8205:
8206: static void dsp_rol_b(void)
8207: {
8208: Uint32 newcarry;
8209:
8210: newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
8211:
8212: dsp_core.registers[DSP_REG_B1] <<= 1;
8213: dsp_core.registers[DSP_REG_B1] |= newcarry;
8214: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
8215:
8216: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8217: dsp_core.registers[DSP_REG_SR] |= newcarry;
8218: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8219: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8220: }
8221:
8222: static void dsp_ror_a(void)
8223: {
8224: Uint32 newcarry;
8225:
8226: newcarry = dsp_core.registers[DSP_REG_A1] & 1;
8227:
8228: dsp_core.registers[DSP_REG_A1] >>= 1;
8229: dsp_core.registers[DSP_REG_A1] |= newcarry<<23;
8230:
8231: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8232: dsp_core.registers[DSP_REG_SR] |= newcarry;
8233: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8234: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8235: }
8236:
8237: static void dsp_ror_b(void)
8238: {
8239: Uint32 newcarry;
8240:
8241: newcarry = dsp_core.registers[DSP_REG_B1] & 1;
8242:
8243: dsp_core.registers[DSP_REG_B1] >>= 1;
8244: dsp_core.registers[DSP_REG_B1] |= newcarry<<23;
8245:
8246: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8247: dsp_core.registers[DSP_REG_SR] |= newcarry;
8248: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8249: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8250: }
8251:
8252: static void dsp_sbc_x_a(void)
8253: {
8254: Uint32 source[3], dest[3], curcarry;
8255: Uint16 newsr;
8256:
8257: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8258:
8259: dest[2] = dsp_core.registers[DSP_REG_A0];
8260: dest[1] = dsp_core.registers[DSP_REG_A1];
8261: dest[0] = dsp_core.registers[DSP_REG_A2];
8262:
8263: source[2] = dsp_core.registers[DSP_REG_X0];
8264: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8265: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8266:
8267: newsr = dsp_sub56(source, dest);
8268:
8269: if (curcarry) {
8270: source[0]=0; source[1]=0; source[2]=1;
8271: newsr |= dsp_sub56(source, dest);
8272: }
8273:
8274: dsp_core.registers[DSP_REG_A2] = dest[0];
8275: dsp_core.registers[DSP_REG_A1] = dest[1];
8276: dsp_core.registers[DSP_REG_A0] = dest[2];
8277:
8278: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8279:
8280: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8281: dsp_core.registers[DSP_REG_SR] |= newsr;
8282: }
8283:
8284: static void dsp_sbc_x_b(void)
8285: {
8286: Uint32 source[3], dest[3], curcarry;
8287: Uint16 newsr;
8288:
8289: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8290:
8291: dest[2] = dsp_core.registers[DSP_REG_B0];
8292: dest[1] = dsp_core.registers[DSP_REG_B1];
8293: dest[0] = dsp_core.registers[DSP_REG_B2];
8294:
8295: source[2] = dsp_core.registers[DSP_REG_X0];
8296: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8297: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8298:
8299: newsr = dsp_sub56(source, dest);
8300:
8301: if (curcarry) {
8302: source[0]=0; source[1]=0; source[2]=1;
8303: newsr |= dsp_sub56(source, dest);
8304: }
8305:
8306: dsp_core.registers[DSP_REG_B2] = dest[0];
8307: dsp_core.registers[DSP_REG_B1] = dest[1];
8308: dsp_core.registers[DSP_REG_B0] = dest[2];
8309:
8310: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8311:
8312: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8313: dsp_core.registers[DSP_REG_SR] |= newsr;
8314: }
8315:
8316: static void dsp_sbc_y_a(void)
8317: {
8318: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 8319: Uint16 newsr;
1.1 root 8320:
1.1.1.6 root 8321: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8322:
8323: dest[2] = dsp_core.registers[DSP_REG_A0];
8324: dest[1] = dsp_core.registers[DSP_REG_A1];
8325: dest[0] = dsp_core.registers[DSP_REG_A2];
8326:
8327: source[2] = dsp_core.registers[DSP_REG_Y0];
8328: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8329: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8330:
8331: newsr = dsp_sub56(source, dest);
8332:
8333: if (curcarry) {
8334: source[0]=0; source[1]=0; source[2]=1;
8335: newsr |= dsp_sub56(source, dest);
8336: }
8337:
8338: dsp_core.registers[DSP_REG_A2] = dest[0];
8339: dsp_core.registers[DSP_REG_A1] = dest[1];
8340: dsp_core.registers[DSP_REG_A0] = dest[2];
8341:
8342: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8343:
8344: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8345: dsp_core.registers[DSP_REG_SR] |= newsr;
8346: }
8347:
8348: static void dsp_sbc_y_b(void)
8349: {
8350: Uint32 source[3], dest[3], curcarry;
8351: Uint16 newsr;
8352:
8353: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8354:
8355: dest[2] = dsp_core.registers[DSP_REG_B0];
8356: dest[1] = dsp_core.registers[DSP_REG_B1];
8357: dest[0] = dsp_core.registers[DSP_REG_B2];
8358:
8359: source[2] = dsp_core.registers[DSP_REG_Y0];
8360: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8361: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8362:
8363: newsr = dsp_sub56(source, dest);
8364:
8365: if (curcarry) {
8366: source[0]=0; source[1]=0; source[2]=1;
8367: newsr |= dsp_sub56(source, dest);
1.1 root 8368: }
8369:
1.1.1.6 root 8370: dsp_core.registers[DSP_REG_B2] = dest[0];
8371: dsp_core.registers[DSP_REG_B1] = dest[1];
8372: dsp_core.registers[DSP_REG_B0] = dest[2];
8373:
8374: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8375:
8376: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8377: dsp_core.registers[DSP_REG_SR] |= newsr;
8378: }
8379:
8380: static void dsp_sub_b_a(void)
8381: {
8382: Uint32 source[3], dest[3];
8383: Uint16 newsr;
8384:
8385: dest[2] = dsp_core.registers[DSP_REG_A0];
8386: dest[1] = dsp_core.registers[DSP_REG_A1];
8387: dest[0] = dsp_core.registers[DSP_REG_A2];
8388:
8389: source[2] = dsp_core.registers[DSP_REG_B0];
8390: source[1] = dsp_core.registers[DSP_REG_B1];
8391: source[0] = dsp_core.registers[DSP_REG_B2];
8392:
1.1 root 8393: newsr = dsp_sub56(source, dest);
8394:
1.1.1.6 root 8395: dsp_core.registers[DSP_REG_A2] = dest[0];
8396: dsp_core.registers[DSP_REG_A1] = dest[1];
8397: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8398:
1.1.1.6 root 8399: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8400:
1.1.1.6 root 8401: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8402: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8403: }
8404:
1.1.1.6 root 8405: static void dsp_sub_a_b(void)
1.1 root 8406: {
1.1.1.6 root 8407: Uint32 source[3], dest[3];
1.1.1.2 root 8408: Uint16 newsr;
1.1 root 8409:
1.1.1.6 root 8410: dest[2] = dsp_core.registers[DSP_REG_B0];
8411: dest[1] = dsp_core.registers[DSP_REG_B1];
8412: dest[0] = dsp_core.registers[DSP_REG_B2];
8413:
8414: source[2] = dsp_core.registers[DSP_REG_A0];
8415: source[1] = dsp_core.registers[DSP_REG_A1];
8416: source[0] = dsp_core.registers[DSP_REG_A2];
8417:
8418: newsr = dsp_sub56(source, dest);
8419:
8420: dsp_core.registers[DSP_REG_B2] = dest[0];
8421: dsp_core.registers[DSP_REG_B1] = dest[1];
8422: dsp_core.registers[DSP_REG_B0] = dest[2];
8423:
8424: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8425:
8426: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8427: dsp_core.registers[DSP_REG_SR] |= newsr;
8428: }
8429:
8430: static void dsp_sub_x_a(void)
8431: {
8432: Uint32 source[3], dest[3];
8433: Uint16 newsr;
8434:
8435: dest[2] = dsp_core.registers[DSP_REG_A0];
8436: dest[1] = dsp_core.registers[DSP_REG_A1];
8437: dest[0] = dsp_core.registers[DSP_REG_A2];
8438:
8439: source[2] = dsp_core.registers[DSP_REG_X0];
8440: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8441: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8442:
8443: newsr = dsp_sub56(source, dest);
8444:
8445: dsp_core.registers[DSP_REG_A2] = dest[0];
8446: dsp_core.registers[DSP_REG_A1] = dest[1];
8447: dsp_core.registers[DSP_REG_A0] = dest[2];
8448:
8449: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8450:
8451: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8452: dsp_core.registers[DSP_REG_SR] |= newsr;
8453: }
8454:
8455: static void dsp_sub_x_b(void)
8456: {
8457: Uint32 source[3], dest[3];
8458: Uint16 newsr;
8459:
8460: dest[2] = dsp_core.registers[DSP_REG_B0];
8461: dest[1] = dsp_core.registers[DSP_REG_B1];
8462: dest[0] = dsp_core.registers[DSP_REG_B2];
8463:
8464: source[2] = dsp_core.registers[DSP_REG_X0];
8465: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8466: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8467:
8468: newsr = dsp_sub56(source, dest);
8469:
8470: dsp_core.registers[DSP_REG_B2] = dest[0];
8471: dsp_core.registers[DSP_REG_B1] = dest[1];
8472: dsp_core.registers[DSP_REG_B0] = dest[2];
8473:
8474: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8475:
8476: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8477: dsp_core.registers[DSP_REG_SR] |= newsr;
8478: }
8479:
8480: static void dsp_sub_y_a(void)
8481: {
8482: Uint32 source[3], dest[3];
8483: Uint16 newsr;
8484:
8485: dest[2] = dsp_core.registers[DSP_REG_A0];
8486: dest[1] = dsp_core.registers[DSP_REG_A1];
8487: dest[0] = dsp_core.registers[DSP_REG_A2];
8488:
8489: source[2] = dsp_core.registers[DSP_REG_Y0];
8490: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8491: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8492:
8493: newsr = dsp_sub56(source, dest);
8494:
8495: dsp_core.registers[DSP_REG_A2] = dest[0];
8496: dsp_core.registers[DSP_REG_A1] = dest[1];
8497: dsp_core.registers[DSP_REG_A0] = dest[2];
8498:
8499: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8500:
8501: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8502: dsp_core.registers[DSP_REG_SR] |= newsr;
8503: }
8504:
8505: static void dsp_sub_y_b(void)
8506: {
8507: Uint32 source[3], dest[3];
8508: Uint16 newsr;
8509:
8510: dest[2] = dsp_core.registers[DSP_REG_B0];
8511: dest[1] = dsp_core.registers[DSP_REG_B1];
8512: dest[0] = dsp_core.registers[DSP_REG_B2];
8513:
8514: source[2] = dsp_core.registers[DSP_REG_Y0];
8515: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8516: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8517:
8518: newsr = dsp_sub56(source, dest);
8519:
8520: dsp_core.registers[DSP_REG_B2] = dest[0];
8521: dsp_core.registers[DSP_REG_B1] = dest[1];
8522: dsp_core.registers[DSP_REG_B0] = dest[2];
8523:
8524: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8525:
8526: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8527: dsp_core.registers[DSP_REG_SR] |= newsr;
8528: }
8529:
8530: static void dsp_sub_x0_a(void)
8531: {
8532: Uint32 source[3], dest[3];
8533: Uint16 newsr;
8534:
8535: dest[2] = dsp_core.registers[DSP_REG_A0];
8536: dest[1] = dsp_core.registers[DSP_REG_A1];
8537: dest[0] = dsp_core.registers[DSP_REG_A2];
8538:
8539: source[2] = 0;
8540: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 8541: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8542:
8543: newsr = dsp_sub56(source, dest);
8544:
8545: dsp_core.registers[DSP_REG_A2] = dest[0];
8546: dsp_core.registers[DSP_REG_A1] = dest[1];
8547: dsp_core.registers[DSP_REG_A0] = dest[2];
8548:
8549: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8550:
8551: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8552: dsp_core.registers[DSP_REG_SR] |= newsr;
8553: }
8554:
8555: static void dsp_sub_x0_b(void)
8556: {
8557: Uint32 source[3], dest[3];
8558: Uint16 newsr;
8559:
8560: dest[2] = dsp_core.registers[DSP_REG_B0];
8561: dest[1] = dsp_core.registers[DSP_REG_B1];
8562: dest[0] = dsp_core.registers[DSP_REG_B2];
8563:
8564: source[2] = 0;
8565: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 8566: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8567:
8568: newsr = dsp_sub56(source, dest);
8569:
8570: dsp_core.registers[DSP_REG_B2] = dest[0];
8571: dsp_core.registers[DSP_REG_B1] = dest[1];
8572: dsp_core.registers[DSP_REG_B0] = dest[2];
8573:
8574: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8575:
8576: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8577: dsp_core.registers[DSP_REG_SR] |= newsr;
8578: }
8579:
8580: static void dsp_sub_y0_a(void)
8581: {
8582: Uint32 source[3], dest[3];
8583: Uint16 newsr;
8584:
8585: dest[2] = dsp_core.registers[DSP_REG_A0];
8586: dest[1] = dsp_core.registers[DSP_REG_A1];
8587: dest[0] = dsp_core.registers[DSP_REG_A2];
8588:
8589: source[2] = 0;
8590: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 8591: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8592:
8593: newsr = dsp_sub56(source, dest);
1.1 root 8594:
1.1.1.6 root 8595: dsp_core.registers[DSP_REG_A2] = dest[0];
8596: dsp_core.registers[DSP_REG_A1] = dest[1];
8597: dsp_core.registers[DSP_REG_A0] = dest[2];
8598:
8599: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8600:
8601: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8602: dsp_core.registers[DSP_REG_SR] |= newsr;
8603: }
8604:
8605: static void dsp_sub_y0_b(void)
8606: {
8607: Uint32 source[3], dest[3];
8608: Uint16 newsr;
8609:
8610: dest[2] = dsp_core.registers[DSP_REG_B0];
8611: dest[1] = dsp_core.registers[DSP_REG_B1];
8612: dest[0] = dsp_core.registers[DSP_REG_B2];
8613:
8614: source[2] = 0;
8615: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 8616: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8617:
8618: newsr = dsp_sub56(source, dest);
8619:
8620: dsp_core.registers[DSP_REG_B2] = dest[0];
8621: dsp_core.registers[DSP_REG_B1] = dest[1];
8622: dsp_core.registers[DSP_REG_B0] = dest[2];
8623:
8624: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8625:
8626: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8627: dsp_core.registers[DSP_REG_SR] |= newsr;
8628: }
8629:
8630: static void dsp_sub_x1_a(void)
8631: {
8632: Uint32 source[3], dest[3];
8633: Uint16 newsr;
8634:
8635: dest[2] = dsp_core.registers[DSP_REG_A0];
8636: dest[1] = dsp_core.registers[DSP_REG_A1];
8637: dest[0] = dsp_core.registers[DSP_REG_A2];
8638:
8639: source[2] = 0;
8640: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8641: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8642:
8643: newsr = dsp_sub56(source, dest);
8644:
8645: dsp_core.registers[DSP_REG_A2] = dest[0];
8646: dsp_core.registers[DSP_REG_A1] = dest[1];
8647: dsp_core.registers[DSP_REG_A0] = dest[2];
8648:
8649: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8650:
8651: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8652: dsp_core.registers[DSP_REG_SR] |= newsr;
8653: }
8654:
8655: static void dsp_sub_x1_b(void)
8656: {
8657: Uint32 source[3], dest[3];
8658: Uint16 newsr;
8659:
8660: dest[2] = dsp_core.registers[DSP_REG_B0];
8661: dest[1] = dsp_core.registers[DSP_REG_B1];
8662: dest[0] = dsp_core.registers[DSP_REG_B2];
8663:
8664: source[2] = 0;
8665: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8666: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8667:
8668: newsr = dsp_sub56(source, dest);
8669:
8670: dsp_core.registers[DSP_REG_B2] = dest[0];
8671: dsp_core.registers[DSP_REG_B1] = dest[1];
8672: dsp_core.registers[DSP_REG_B0] = dest[2];
8673:
8674: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8675:
8676: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8677: dsp_core.registers[DSP_REG_SR] |= newsr;
8678: }
8679:
8680: static void dsp_sub_y1_a(void)
8681: {
8682: Uint32 source[3], dest[3];
8683: Uint16 newsr;
8684:
8685: dest[2] = dsp_core.registers[DSP_REG_A0];
8686: dest[1] = dsp_core.registers[DSP_REG_A1];
8687: dest[0] = dsp_core.registers[DSP_REG_A2];
8688:
8689: source[2] = 0;
8690: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8691: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8692:
8693: newsr = dsp_sub56(source, dest);
8694:
8695: dsp_core.registers[DSP_REG_A2] = dest[0];
8696: dsp_core.registers[DSP_REG_A1] = dest[1];
8697: dsp_core.registers[DSP_REG_A0] = dest[2];
8698:
8699: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8700:
8701: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8702: dsp_core.registers[DSP_REG_SR] |= newsr;
8703: }
8704:
8705: static void dsp_sub_y1_b(void)
8706: {
8707: Uint32 source[3], dest[3];
8708: Uint16 newsr;
8709:
8710: dest[2] = dsp_core.registers[DSP_REG_B0];
8711: dest[1] = dsp_core.registers[DSP_REG_B1];
8712: dest[0] = dsp_core.registers[DSP_REG_B2];
8713:
8714: source[2] = 0;
8715: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8716: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8717:
8718: newsr = dsp_sub56(source, dest);
8719:
8720: dsp_core.registers[DSP_REG_B2] = dest[0];
8721: dsp_core.registers[DSP_REG_B1] = dest[1];
8722: dsp_core.registers[DSP_REG_B0] = dest[2];
8723:
8724: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8725:
8726: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8727: dsp_core.registers[DSP_REG_SR] |= newsr;
8728: }
8729:
8730: static void dsp_subl_a(void)
8731: {
8732: Uint32 source[3], dest[3];
8733: Uint16 newsr;
8734:
8735: dest[0] = dsp_core.registers[DSP_REG_A2];
8736: dest[1] = dsp_core.registers[DSP_REG_A1];
8737: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 8738: newsr = dsp_asl56(dest);
8739:
1.1.1.6 root 8740: source[0] = dsp_core.registers[DSP_REG_B2];
8741: source[1] = dsp_core.registers[DSP_REG_B1];
8742: source[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 8743: newsr |= dsp_sub56(source, dest);
8744:
1.1.1.6 root 8745: dsp_core.registers[DSP_REG_A2] = dest[0];
8746: dsp_core.registers[DSP_REG_A1] = dest[1];
8747: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8748:
1.1.1.6 root 8749: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8750:
1.1.1.6 root 8751: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8752: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8753: }
8754:
1.1.1.6 root 8755: static void dsp_subl_b(void)
1.1 root 8756: {
1.1.1.6 root 8757: Uint32 source[3], dest[3];
1.1.1.2 root 8758: Uint16 newsr;
1.1 root 8759:
1.1.1.6 root 8760: dest[0] = dsp_core.registers[DSP_REG_B2];
8761: dest[1] = dsp_core.registers[DSP_REG_B1];
8762: dest[2] = dsp_core.registers[DSP_REG_B0];
8763: newsr = dsp_asl56(dest);
1.1 root 8764:
1.1.1.6 root 8765: source[0] = dsp_core.registers[DSP_REG_A2];
8766: source[1] = dsp_core.registers[DSP_REG_A1];
8767: source[2] = dsp_core.registers[DSP_REG_A0];
8768: newsr |= dsp_sub56(source, dest);
8769:
8770: dsp_core.registers[DSP_REG_B2] = dest[0];
8771: dsp_core.registers[DSP_REG_B1] = dest[1];
8772: dsp_core.registers[DSP_REG_B0] = dest[2];
8773:
8774: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8775:
8776: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8777: dsp_core.registers[DSP_REG_SR] |= newsr;
8778: }
8779:
8780: static void dsp_subr_a(void)
8781: {
8782: Uint32 source[3], dest[3];
8783: Uint16 newsr;
8784:
8785: dest[0] = dsp_core.registers[DSP_REG_A2];
8786: dest[1] = dsp_core.registers[DSP_REG_A1];
8787: dest[2] = dsp_core.registers[DSP_REG_A0];
8788:
1.1 root 8789: newsr = dsp_asr56(dest);
8790:
1.1.1.6 root 8791: source[0] = dsp_core.registers[DSP_REG_B2];
8792: source[1] = dsp_core.registers[DSP_REG_B1];
8793: source[2] = dsp_core.registers[DSP_REG_B0];
8794:
1.1 root 8795: newsr |= dsp_sub56(source, dest);
8796:
1.1.1.6 root 8797: dsp_core.registers[DSP_REG_A2] = dest[0];
8798: dsp_core.registers[DSP_REG_A1] = dest[1];
8799: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8800:
1.1.1.6 root 8801: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8802:
1.1.1.6 root 8803: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8804: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8805: }
8806:
1.1.1.6 root 8807: static void dsp_subr_b(void)
1.1 root 8808: {
1.1.1.6 root 8809: Uint32 source[3], dest[3];
8810: Uint16 newsr;
1.1 root 8811:
1.1.1.6 root 8812: dest[0] = dsp_core.registers[DSP_REG_B2];
8813: dest[1] = dsp_core.registers[DSP_REG_B1];
8814: dest[2] = dsp_core.registers[DSP_REG_B0];
8815:
8816: newsr = dsp_asr56(dest);
1.1 root 8817:
1.1.1.6 root 8818: source[0] = dsp_core.registers[DSP_REG_A2];
8819: source[1] = dsp_core.registers[DSP_REG_A1];
8820: source[2] = dsp_core.registers[DSP_REG_A0];
8821:
8822: newsr |= dsp_sub56(source, dest);
1.1 root 8823:
1.1.1.6 root 8824: dsp_core.registers[DSP_REG_B2] = dest[0];
8825: dsp_core.registers[DSP_REG_B1] = dest[1];
8826: dsp_core.registers[DSP_REG_B0] = dest[2];
8827:
8828: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8829:
8830: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8831: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8832: }
8833:
1.1.1.6 root 8834: static void dsp_tfr_b_a(void)
1.1 root 8835: {
1.1.1.6 root 8836: dsp_core.registers[DSP_REG_A0] = dsp_core.registers[DSP_REG_B0];
8837: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_B1];
8838: dsp_core.registers[DSP_REG_A2] = dsp_core.registers[DSP_REG_B2];
8839: }
1.1 root 8840:
1.1.1.6 root 8841: static void dsp_tfr_a_b(void)
8842: {
8843: dsp_core.registers[DSP_REG_B0] = dsp_core.registers[DSP_REG_A0];
8844: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_A1];
8845: dsp_core.registers[DSP_REG_B2] = dsp_core.registers[DSP_REG_A2];
8846: }
8847:
8848: static void dsp_tfr_x0_a(void)
8849: {
8850: dsp_core.registers[DSP_REG_A0] = 0;
8851: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_X0];
8852: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
8853: dsp_core.registers[DSP_REG_A2] = 0xff;
8854: else
8855: dsp_core.registers[DSP_REG_A2] = 0x0;
8856: }
8857:
8858: static void dsp_tfr_x0_b(void)
8859: {
8860: dsp_core.registers[DSP_REG_B0] = 0;
8861: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_X0];
8862: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
8863: dsp_core.registers[DSP_REG_B2] = 0xff;
8864: else
8865: dsp_core.registers[DSP_REG_B2] = 0x0;
8866: }
8867:
8868: static void dsp_tfr_y0_a(void)
8869: {
8870: dsp_core.registers[DSP_REG_A0] = 0;
8871: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_Y0];
8872: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
8873: dsp_core.registers[DSP_REG_A2] = 0xff;
8874: else
8875: dsp_core.registers[DSP_REG_A2] = 0x0;
8876: }
8877:
8878: static void dsp_tfr_y0_b(void)
8879: {
8880: dsp_core.registers[DSP_REG_B0] = 0;
8881: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_Y0];
8882: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
8883: dsp_core.registers[DSP_REG_B2] = 0xff;
8884: else
8885: dsp_core.registers[DSP_REG_B2] = 0x0;
8886: }
8887:
8888: static void dsp_tfr_x1_a(void)
8889: {
8890: dsp_core.registers[DSP_REG_A0] = 0;
8891: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_X1];
8892: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
8893: dsp_core.registers[DSP_REG_A2] = 0xff;
8894: else
8895: dsp_core.registers[DSP_REG_A2] = 0x0;
8896: }
8897:
8898: static void dsp_tfr_x1_b(void)
8899: {
8900: dsp_core.registers[DSP_REG_B0] = 0;
8901: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_X1];
8902: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
8903: dsp_core.registers[DSP_REG_B2] = 0xff;
8904: else
8905: dsp_core.registers[DSP_REG_B2] = 0x0;
8906: }
8907:
8908: static void dsp_tfr_y1_a(void)
8909: {
8910: dsp_core.registers[DSP_REG_A0] = 0;
8911: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_Y1];
8912: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
8913: dsp_core.registers[DSP_REG_A2] = 0xff;
8914: else
8915: dsp_core.registers[DSP_REG_A2] = 0x0;
8916: }
8917:
8918: static void dsp_tfr_y1_b(void)
8919: {
8920: dsp_core.registers[DSP_REG_B0] = 0;
8921: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_Y1];
8922: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
8923: dsp_core.registers[DSP_REG_B2] = 0xff;
8924: else
8925: dsp_core.registers[DSP_REG_B2] = 0x0;
8926: }
8927:
8928: static void dsp_tst_a(void)
8929: {
8930: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_A2],
1.1.1.7 root 8931: dsp_core.registers[DSP_REG_A1],
8932: dsp_core.registers[DSP_REG_A0]);
1.1.1.6 root 8933:
8934: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8935: }
8936:
8937: static void dsp_tst_b(void)
8938: {
8939: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_B2],
1.1.1.7 root 8940: dsp_core.registers[DSP_REG_B1],
8941: dsp_core.registers[DSP_REG_B0]);
1.1 root 8942:
1.1.1.6 root 8943: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
1.1 root 8944: }
8945:
1.1.1.2 root 8946: /*
8947: vim:ts=4:sw=4:
8948: */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.