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1.1 root 1: /*
1.1.1.2 root 2: DSP M56001 emulation
1.1.1.4 root 3: Instructions interpreter
1.1.1.2 root 4:
5: (C) 2003-2008 ARAnyM developer team
6:
7: This program is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2 of the License, or
10: (at your option) any later version.
11:
12: This program is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
18: along with this program; if not, write to the Free Software
19: Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20: */
21:
1.1.1.7 root 22: /*
23: DSP memory mapping
24: ------------------
25:
26: The memory map is configured as follows :
27: Program space P is one contiguous block of 32K dsp Words
28: X and Y data space are each separate 16K dsp Word blocks.
29: Both X and Y can be accessed as blocks starting at 0 or 16K.
30: Program space physically overlaps both X and Y data spaces.
31: Y: memory is mapped at address $0 in P memory
32: X: memory is mapped at address $4000 in P memory
33:
34: The DSP external RAM is zero waitstate, but there is a penalty for
1.1.1.9 ! root 35: accessing it twice or more in a single instruction, because there is only
! 36: one external data bus. The extra access costs 2 cycles penalty.
! 37:
1.1.1.7 root 38: The internal buses are all separate (0 waitstate)
39:
40:
41: X: Y: P:
42: $ffff |--------------+--------------+--------------|
43: | Int. I/O | Ext. I/O | |
44: $ffc0 |--------------+--------------+ |
45: | | | |
46: | Reserved | Reserved | Reserved |
47: | | | |
48: | | | |
49: | | | |
50: $8000 |--------------+--------------+--------------|
51: | | | |
52: | 16k Shadow | 16k Shadow | |
53: | | | 32K |
54: $4000 |--------------+--------------| Program |
55: | 16K | 16K | RAM |
56: | External | External | |
57: | RAM | RAM | |
58: $0200 |--------------+--------------+--------------|
59: | Log table or | Sin table or | |
60: | external mem | external mem | Internal |
61: $0100 |--------------+--------------+ program |
62: | Internal X | Internal Y | memory |
63: | memory | memory | |
64: $0000 |--------------+--------------+--------------|
65:
66:
67: Special Note : As the Falcon DSP is a 0 waitstate access memory, I've simplified a little the cycle counting.
68: If this DSP emulator code is used in another project, one should take into account the bus control register (BCR) waitstates.
69: */
70:
1.1.1.2 root 71: #ifdef HAVE_CONFIG_H
72: #include "config.h"
73: #endif
74:
1.1.1.6 root 75: #include <stdbool.h>
76:
1.1.1.2 root 77: #include "dsp_core.h"
1.1 root 78: #include "dsp_cpu.h"
79: #include "dsp_disasm.h"
1.1.1.6 root 80: #include "log.h"
1.1.1.9 ! root 81: #include "main.h"
! 82: #include "debugui.h"
1.1 root 83:
1.1.1.2 root 84: #define DSP_COUNT_IPS 0 /* Count instruction per seconds */
85:
1.1 root 86:
87: /**********************************
88: * Defines
89: **********************************/
90:
1.1.1.6 root 91: #define SIGN_PLUS 0
92: #define SIGN_MINUS 1
1.1.1.4 root 93:
1.1.1.9 ! root 94: /* Defines some bits values for access to external memory (X, Y, P) */
! 95: /* These values will set/unset the corresponding bits in the variable access_to_ext_memory */
! 96: /* to detect how many access to the external memory were done for a single instruction */
! 97: #define EXT_X_MEMORY 0
! 98: #define EXT_Y_MEMORY 1
! 99: #define EXT_P_MEMORY 2
! 100:
! 101:
1.1 root 102: /**********************************
103: * Variables
104: **********************************/
105:
1.1.1.4 root 106: /* Instructions per second */
107: static Uint32 start_time;
108: static Uint32 num_inst;
109:
1.1 root 110: /* Length of current instruction */
1.1.1.2 root 111: static Uint32 cur_inst_len; /* =0:jump, >0:increment */
1.1 root 112:
113: /* Current instruction */
1.1.1.4 root 114: static Uint32 cur_inst;
1.1 root 115:
1.1.1.7 root 116: /* Counts the number of access to the external memory for one instruction */
1.1.1.9 ! root 117: static Uint16 access_to_ext_memory;
1.1.1.7 root 118:
1.1.1.6 root 119: /* DSP is in disasm mode ? */
120: /* If yes, stack overflow, underflow and illegal instructions messages are not displayed */
121: static bool isDsp_in_disasm_mode;
1.1 root 122:
1.1.1.7 root 123: static char str_disasm_memory[2][50]; /* Buffer for memory change text in disasm mode */
1.1.1.5 root 124: static Uint16 disasm_memory_ptr; /* Pointer for memory change in disasm mode */
1.1 root 125:
126: /**********************************
127: * Functions
128: **********************************/
129:
130: typedef void (*dsp_emul_t)(void);
131:
132: static void dsp_postexecute_update_pc(void);
133: static void dsp_postexecute_interrupts(void);
134:
1.1.1.5 root 135: static void dsp_setInterruptIPL(Uint32 value);
136:
1.1.1.6 root 137: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2);
1.1.1.2 root 138:
139: static Uint32 read_memory(int space, Uint16 address);
1.1.1.6 root 140: static inline Uint32 read_memory_p(Uint16 address);
1.1.1.2 root 141: static Uint32 read_memory_disasm(int space, Uint16 address);
1.1.1.6 root 142:
143: static inline void write_memory(int space, Uint16 address, Uint32 value);
144: static void write_memory_raw(int space, Uint16 address, Uint32 value);
1.1.1.4 root 145: static void write_memory_disasm(int space, Uint16 address, Uint32 value);
1.1.1.6 root 146:
1.1.1.4 root 147: static void dsp_write_reg(Uint32 numreg, Uint32 value);
1.1 root 148:
1.1.1.4 root 149: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly);
1.1.1.2 root 150: static void dsp_stack_pop(Uint32 *curpc, Uint32 *cursr);
1.1.1.4 root 151: static void dsp_compute_ssh_ssl(void);
1.1 root 152:
153: static void opcode8h_0(void);
154:
1.1.1.2 root 155: static void dsp_update_rn(Uint32 numreg, Sint16 modifier);
156: static void dsp_update_rn_bitreverse(Uint32 numreg);
157: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier);
158: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr);
159: static int dsp_calc_cc(Uint32 cc_code);
1.1 root 160:
161: static void dsp_undefined(void);
162:
163: /* Instructions without parallel moves */
164: static void dsp_andi(void);
1.1.1.4 root 165: static void dsp_bchg_aa(void);
166: static void dsp_bchg_ea(void);
167: static void dsp_bchg_pp(void);
168: static void dsp_bchg_reg(void);
169: static void dsp_bclr_aa(void);
170: static void dsp_bclr_ea(void);
171: static void dsp_bclr_pp(void);
172: static void dsp_bclr_reg(void);
173: static void dsp_bset_aa(void);
174: static void dsp_bset_ea(void);
175: static void dsp_bset_pp(void);
176: static void dsp_bset_reg(void);
177: static void dsp_btst_aa(void);
178: static void dsp_btst_ea(void);
179: static void dsp_btst_pp(void);
180: static void dsp_btst_reg(void);
1.1 root 181: static void dsp_div(void);
182: static void dsp_enddo(void);
183: static void dsp_illegal(void);
1.1.1.4 root 184: static void dsp_jcc_imm(void);
185: static void dsp_jcc_ea(void);
186: static void dsp_jclr_aa(void);
187: static void dsp_jclr_ea(void);
188: static void dsp_jclr_pp(void);
189: static void dsp_jclr_reg(void);
190: static void dsp_jmp_ea(void);
191: static void dsp_jmp_imm(void);
192: static void dsp_jscc_ea(void);
193: static void dsp_jscc_imm(void);
194: static void dsp_jsclr_aa(void);
195: static void dsp_jsclr_ea(void);
196: static void dsp_jsclr_pp(void);
197: static void dsp_jsclr_reg(void);
198: static void dsp_jset_aa(void);
199: static void dsp_jset_ea(void);
200: static void dsp_jset_pp(void);
201: static void dsp_jset_reg(void);
202: static void dsp_jsr_ea(void);
203: static void dsp_jsr_imm(void);
204: static void dsp_jsset_aa(void);
205: static void dsp_jsset_ea(void);
206: static void dsp_jsset_pp(void);
207: static void dsp_jsset_reg(void);
1.1 root 208: static void dsp_lua(void);
1.1.1.4 root 209: static void dsp_movem_ea(void);
210: static void dsp_movem_aa(void);
1.1 root 211: static void dsp_nop(void);
212: static void dsp_norm(void);
213: static void dsp_ori(void);
214: static void dsp_reset(void);
215: static void dsp_rti(void);
216: static void dsp_rts(void);
217: static void dsp_stop(void);
218: static void dsp_swi(void);
219: static void dsp_tcc(void);
220: static void dsp_wait(void);
221:
1.1.1.3 root 222: static void dsp_do_ea(void);
223: static void dsp_do_aa(void);
224: static void dsp_do_imm(void);
225: static void dsp_do_reg(void);
226: static void dsp_rep_aa(void);
227: static void dsp_rep_ea(void);
228: static void dsp_rep_imm(void);
229: static void dsp_rep_reg(void);
230: static void dsp_movec_aa(void);
231: static void dsp_movec_ea(void);
232: static void dsp_movec_imm(void);
233: static void dsp_movec_reg(void);
1.1 root 234: static void dsp_movep_0(void);
235: static void dsp_movep_1(void);
1.1.1.4 root 236: static void dsp_movep_23(void);
1.1 root 237:
238: /* Parallel move analyzer */
1.1.1.2 root 239: static int dsp_pm_read_accu24(int numreg, Uint32 *dest);
1.1 root 240: static void dsp_pm_0(void);
241: static void dsp_pm_1(void);
242: static void dsp_pm_2(void);
243: static void dsp_pm_2_2(void);
244: static void dsp_pm_3(void);
245: static void dsp_pm_4(void);
1.1.1.4 root 246: static void dsp_pm_4x(void);
1.1 root 247: static void dsp_pm_5(void);
248: static void dsp_pm_8(void);
249:
250: /* 56bits arithmetic */
1.1.1.2 root 251: static Uint16 dsp_abs56(Uint32 *dest);
252: static Uint16 dsp_asl56(Uint32 *dest);
253: static Uint16 dsp_asr56(Uint32 *dest);
254: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest);
255: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest);
1.1.1.5 root 256: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe);
1.1.1.2 root 257: static void dsp_rnd56(Uint32 *dest);
1.1 root 258:
259: /* Instructions with parallel moves */
1.1.1.6 root 260: static void dsp_abs_a(void);
261: static void dsp_abs_b(void);
262: static void dsp_adc_x_a(void);
263: static void dsp_adc_x_b(void);
264: static void dsp_adc_y_a(void);
265: static void dsp_adc_y_b(void);
266: static void dsp_add_b_a(void);
267: static void dsp_add_a_b(void);
268: static void dsp_add_x_a(void);
269: static void dsp_add_x_b(void);
270: static void dsp_add_y_a(void);
271: static void dsp_add_y_b(void);
272: static void dsp_add_x0_a(void);
273: static void dsp_add_x0_b(void);
274: static void dsp_add_y0_a(void);
275: static void dsp_add_y0_b(void);
276: static void dsp_add_x1_a(void);
277: static void dsp_add_x1_b(void);
278: static void dsp_add_y1_a(void);
279: static void dsp_add_y1_b(void);
280: static void dsp_addl_b_a(void);
281: static void dsp_addl_b_a(void);
282: static void dsp_addl_a_b(void);
283: static void dsp_addr_b_a(void);
284: static void dsp_addr_a_b(void);
285: static void dsp_and_x0_a(void);
286: static void dsp_and_x0_b(void);
287: static void dsp_and_y0_a(void);
288: static void dsp_and_y0_b(void);
289: static void dsp_and_x1_a(void);
290: static void dsp_and_x1_b(void);
291: static void dsp_and_y1_a(void);
292: static void dsp_and_y1_b(void);
1.1.1.7 root 293: static void dsp_asl_a(void);
294: static void dsp_asl_b(void);
295: static void dsp_asr_a(void);
296: static void dsp_asr_b(void);
1.1.1.6 root 297: static void dsp_clr_a(void);
298: static void dsp_clr_b(void);
299: static void dsp_cmp_b_a(void);
300: static void dsp_cmp_a_b(void);
301: static void dsp_cmp_x0_a(void);
302: static void dsp_cmp_x0_b(void);
303: static void dsp_cmp_y0_a(void);
304: static void dsp_cmp_y0_b(void);
305: static void dsp_cmp_x1_a(void);
306: static void dsp_cmp_x1_b(void);
307: static void dsp_cmp_y1_a(void);
308: static void dsp_cmp_y1_b(void);
309: static void dsp_cmpm_b_a(void);
310: static void dsp_cmpm_a_b(void);
311: static void dsp_cmpm_x0_a(void);
312: static void dsp_cmpm_x0_b(void);
313: static void dsp_cmpm_y0_a(void);
314: static void dsp_cmpm_y0_b(void);
315: static void dsp_cmpm_x1_a(void);
316: static void dsp_cmpm_x1_b(void);
317: static void dsp_cmpm_y1_a(void);
318: static void dsp_cmpm_y1_b(void);
319: static void dsp_eor_x0_a(void);
320: static void dsp_eor_x0_b(void);
321: static void dsp_eor_y0_a(void);
322: static void dsp_eor_y0_b(void);
323: static void dsp_eor_x1_a(void);
324: static void dsp_eor_x1_b(void);
325: static void dsp_eor_y1_a(void);
326: static void dsp_eor_y1_b(void);
327: static void dsp_lsl_a(void);
328: static void dsp_lsl_b(void);
329: static void dsp_lsr_a(void);
330: static void dsp_lsr_b(void);
331: static void dsp_mac_p_x0_x0_a(void);
332: static void dsp_mac_m_x0_x0_a(void);
333: static void dsp_mac_p_x0_x0_b(void);
334: static void dsp_mac_m_x0_x0_b(void);
335: static void dsp_mac_p_y0_y0_a(void);
336: static void dsp_mac_m_y0_y0_a(void);
337: static void dsp_mac_p_y0_y0_b(void);
338: static void dsp_mac_m_y0_y0_b(void);
339: static void dsp_mac_p_x1_x0_a(void);
340: static void dsp_mac_m_x1_x0_a(void);
341: static void dsp_mac_p_x1_x0_b(void);
342: static void dsp_mac_m_x1_x0_b(void);
343: static void dsp_mac_p_y1_y0_a(void);
344: static void dsp_mac_m_y1_y0_a(void);
345: static void dsp_mac_p_y1_y0_b(void);
346: static void dsp_mac_m_y1_y0_b(void);
347: static void dsp_mac_p_x0_y1_a(void);
348: static void dsp_mac_m_x0_y1_a(void);
349: static void dsp_mac_p_x0_y1_b(void);
350: static void dsp_mac_m_x0_y1_b(void);
351: static void dsp_mac_p_y0_x0_a(void);
352: static void dsp_mac_m_y0_x0_a(void);
353: static void dsp_mac_p_y0_x0_b(void);
354: static void dsp_mac_m_y0_x0_b(void);
355: static void dsp_mac_p_x1_y0_a(void);
356: static void dsp_mac_m_x1_y0_a(void);
357: static void dsp_mac_p_x1_y0_b(void);
358: static void dsp_mac_m_x1_y0_b(void);
359: static void dsp_mac_p_y1_x1_a(void);
360: static void dsp_mac_m_y1_x1_a(void);
361: static void dsp_mac_p_y1_x1_b(void);
362: static void dsp_mac_m_y1_x1_b(void);
363: static void dsp_macr_p_x0_x0_a(void);
364: static void dsp_macr_m_x0_x0_a(void);
365: static void dsp_macr_p_x0_x0_b(void);
366: static void dsp_macr_m_x0_x0_b(void);
367: static void dsp_macr_p_y0_y0_a(void);
368: static void dsp_macr_m_y0_y0_a(void);
369: static void dsp_macr_p_y0_y0_b(void);
370: static void dsp_macr_m_y0_y0_b(void);
371: static void dsp_macr_p_x1_x0_a(void);
372: static void dsp_macr_m_x1_x0_a(void);
373: static void dsp_macr_p_x1_x0_b(void);
374: static void dsp_macr_m_x1_x0_b(void);
375: static void dsp_macr_p_y1_y0_a(void);
376: static void dsp_macr_m_y1_y0_a(void);
377: static void dsp_macr_p_y1_y0_b(void);
378: static void dsp_macr_m_y1_y0_b(void);
379: static void dsp_macr_p_x0_y1_a(void);
380: static void dsp_macr_m_x0_y1_a(void);
381: static void dsp_macr_p_x0_y1_b(void);
382: static void dsp_macr_m_x0_y1_b(void);
383: static void dsp_macr_p_y0_x0_a(void);
384: static void dsp_macr_m_y0_x0_a(void);
385: static void dsp_macr_p_y0_x0_b(void);
386: static void dsp_macr_m_y0_x0_b(void);
387: static void dsp_macr_p_x1_y0_a(void);
388: static void dsp_macr_m_x1_y0_a(void);
389: static void dsp_macr_p_x1_y0_b(void);
390: static void dsp_macr_m_x1_y0_b(void);
391: static void dsp_macr_p_y1_x1_a(void);
392: static void dsp_macr_m_y1_x1_a(void);
393: static void dsp_macr_p_y1_x1_b(void);
394: static void dsp_macr_m_y1_x1_b(void);
1.1 root 395: static void dsp_move(void);
1.1.1.6 root 396: static void dsp_mpy_p_x0_x0_a(void);
397: static void dsp_mpy_m_x0_x0_a(void);
398: static void dsp_mpy_p_x0_x0_b(void);
399: static void dsp_mpy_m_x0_x0_b(void);
400: static void dsp_mpy_p_y0_y0_a(void);
401: static void dsp_mpy_m_y0_y0_a(void);
402: static void dsp_mpy_p_y0_y0_b(void);
403: static void dsp_mpy_m_y0_y0_b(void);
404: static void dsp_mpy_p_x1_x0_a(void);
405: static void dsp_mpy_m_x1_x0_a(void);
406: static void dsp_mpy_p_x1_x0_b(void);
407: static void dsp_mpy_m_x1_x0_b(void);
408: static void dsp_mpy_p_y1_y0_a(void);
409: static void dsp_mpy_m_y1_y0_a(void);
410: static void dsp_mpy_p_y1_y0_b(void);
411: static void dsp_mpy_m_y1_y0_b(void);
412: static void dsp_mpy_p_x0_y1_a(void);
413: static void dsp_mpy_m_x0_y1_a(void);
414: static void dsp_mpy_p_x0_y1_b(void);
415: static void dsp_mpy_m_x0_y1_b(void);
416: static void dsp_mpy_p_y0_x0_a(void);
417: static void dsp_mpy_m_y0_x0_a(void);
418: static void dsp_mpy_p_y0_x0_b(void);
419: static void dsp_mpy_m_y0_x0_b(void);
420: static void dsp_mpy_p_x1_y0_a(void);
421: static void dsp_mpy_m_x1_y0_a(void);
422: static void dsp_mpy_p_x1_y0_b(void);
423: static void dsp_mpy_m_x1_y0_b(void);
424: static void dsp_mpy_p_y1_x1_a(void);
425: static void dsp_mpy_m_y1_x1_a(void);
426: static void dsp_mpy_p_y1_x1_b(void);
427: static void dsp_mpy_m_y1_x1_b(void);
428: static void dsp_mpyr_p_x0_x0_a(void);
429: static void dsp_mpyr_m_x0_x0_a(void);
430: static void dsp_mpyr_p_x0_x0_b(void);
431: static void dsp_mpyr_m_x0_x0_b(void);
432: static void dsp_mpyr_p_y0_y0_a(void);
433: static void dsp_mpyr_m_y0_y0_a(void);
434: static void dsp_mpyr_p_y0_y0_b(void);
435: static void dsp_mpyr_m_y0_y0_b(void);
436: static void dsp_mpyr_p_x1_x0_a(void);
437: static void dsp_mpyr_m_x1_x0_a(void);
438: static void dsp_mpyr_p_x1_x0_b(void);
439: static void dsp_mpyr_m_x1_x0_b(void);
440: static void dsp_mpyr_p_y1_y0_a(void);
441: static void dsp_mpyr_m_y1_y0_a(void);
442: static void dsp_mpyr_p_y1_y0_b(void);
443: static void dsp_mpyr_m_y1_y0_b(void);
444: static void dsp_mpyr_p_x0_y1_a(void);
445: static void dsp_mpyr_m_x0_y1_a(void);
446: static void dsp_mpyr_p_x0_y1_b(void);
447: static void dsp_mpyr_m_x0_y1_b(void);
448: static void dsp_mpyr_p_y0_x0_a(void);
449: static void dsp_mpyr_m_y0_x0_a(void);
450: static void dsp_mpyr_p_y0_x0_b(void);
451: static void dsp_mpyr_m_y0_x0_b(void);
452: static void dsp_mpyr_p_x1_y0_a(void);
453: static void dsp_mpyr_m_x1_y0_a(void);
454: static void dsp_mpyr_p_x1_y0_b(void);
455: static void dsp_mpyr_m_x1_y0_b(void);
456: static void dsp_mpyr_p_y1_x1_a(void);
457: static void dsp_mpyr_m_y1_x1_a(void);
458: static void dsp_mpyr_p_y1_x1_b(void);
459: static void dsp_mpyr_m_y1_x1_b(void);
460: static void dsp_neg_a(void);
461: static void dsp_neg_b(void);
462: static void dsp_not_a(void);
463: static void dsp_not_b(void);
464: static void dsp_or_x0_a(void);
465: static void dsp_or_x0_b(void);
466: static void dsp_or_y0_a(void);
467: static void dsp_or_y0_b(void);
468: static void dsp_or_x1_a(void);
469: static void dsp_or_x1_b(void);
470: static void dsp_or_y1_a(void);
471: static void dsp_or_y1_b(void);
472: static void dsp_rnd_a(void);
473: static void dsp_rnd_b(void);
474: static void dsp_rol_a(void);
475: static void dsp_rol_b(void);
476: static void dsp_ror_a(void);
477: static void dsp_ror_b(void);
478: static void dsp_sbc_x_a(void);
479: static void dsp_sbc_x_b(void);
480: static void dsp_sbc_y_a(void);
481: static void dsp_sbc_y_b(void);
482: static void dsp_sub_b_a(void);
483: static void dsp_sub_a_b(void);
484: static void dsp_sub_x_a(void);
485: static void dsp_sub_x_b(void);
486: static void dsp_sub_y_a(void);
487: static void dsp_sub_y_b(void);
488: static void dsp_sub_x0_a(void);
489: static void dsp_sub_x0_b(void);
490: static void dsp_sub_y0_a(void);
491: static void dsp_sub_y0_b(void);
492: static void dsp_sub_x1_a(void);
493: static void dsp_sub_x1_b(void);
494: static void dsp_sub_y1_a(void);
495: static void dsp_sub_y1_b(void);
496: static void dsp_subl_a(void);
497: static void dsp_subl_b(void);
498: static void dsp_subr_a(void);
499: static void dsp_subr_b(void);
500: static void dsp_tfr_b_a(void);
501: static void dsp_tfr_a_b(void);
502: static void dsp_tfr_x0_a(void);
503: static void dsp_tfr_x0_b(void);
504: static void dsp_tfr_y0_a(void);
505: static void dsp_tfr_y0_b(void);
506: static void dsp_tfr_x1_a(void);
507: static void dsp_tfr_x1_b(void);
508: static void dsp_tfr_y1_a(void);
509: static void dsp_tfr_y1_b(void);
510: static void dsp_tst_a(void);
511: static void dsp_tst_b(void);
1.1 root 512:
1.1.1.6 root 513: static const dsp_emul_t opcodes8h[512] = {
1.1.1.4 root 514: /* 0x00 - 0x3f */
515: opcode8h_0, dsp_undefined, dsp_undefined, dsp_undefined, opcode8h_0, dsp_andi, dsp_undefined, dsp_ori,
516: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
517: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
518: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_andi, dsp_undefined, dsp_ori,
519: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
520: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
521: dsp_undefined, dsp_undefined, dsp_div, dsp_div, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
522: dsp_norm, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
523:
524: /* 0x40 - 0x7f */
525: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
526: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
527: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
528: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
529: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
530: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
531: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
532: dsp_tcc, dsp_tcc, dsp_tcc, dsp_tcc, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
533:
534: /* 0x80 - 0xbf */
535: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
536: dsp_lua, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
537: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
538: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movec_reg, dsp_undefined, dsp_undefined,
539: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
540: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
541: dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_aa, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
542: dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_ea, dsp_undefined, dsp_movec_imm, dsp_undefined, dsp_undefined,
543:
544: /* 0xc0 - 0xff */
545: dsp_do_aa, dsp_rep_aa, dsp_do_aa, dsp_rep_aa, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
546: dsp_do_ea, dsp_rep_ea, dsp_do_ea, dsp_rep_ea, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
547: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
548: dsp_do_reg, dsp_rep_reg, dsp_undefined, dsp_undefined, dsp_do_imm, dsp_rep_imm, dsp_undefined, dsp_undefined,
549: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
550: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
551: dsp_movem_aa, dsp_movem_aa, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
552: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_movem_ea, dsp_movem_ea, dsp_undefined, dsp_undefined,
553:
554: /* 0x100 - 0x13f */
1.1.1.6 root 555: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 556: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 557: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 558: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 559: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 560: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
1.1.1.6 root 561: dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0, dsp_pm_0,
1.1.1.4 root 562: dsp_movep_0, dsp_movep_0, dsp_movep_1, dsp_movep_1, dsp_movep_23, dsp_movep_23, dsp_movep_23, dsp_movep_23,
563:
564: /* 0x140 - 0x17f */
565: dsp_bclr_aa, dsp_bset_aa, dsp_bclr_aa, dsp_bset_aa, dsp_jclr_aa, dsp_jset_aa, dsp_jclr_aa, dsp_jset_aa,
566: dsp_bclr_ea, dsp_bset_ea, dsp_bclr_ea, dsp_bset_ea, dsp_jclr_ea, dsp_jset_ea, dsp_jclr_ea, dsp_jset_ea,
567: dsp_bclr_pp, dsp_bset_pp, dsp_bclr_pp, dsp_bset_pp, dsp_jclr_pp, dsp_jset_pp, dsp_jclr_pp, dsp_jset_pp,
568: dsp_jclr_reg, dsp_jset_reg, dsp_bclr_reg, dsp_bset_reg, dsp_jmp_ea, dsp_jcc_ea, dsp_undefined, dsp_undefined,
569: dsp_bchg_aa, dsp_btst_aa, dsp_bchg_aa, dsp_btst_aa, dsp_jsclr_aa, dsp_jsset_aa, dsp_jsclr_aa, dsp_jsset_aa,
570: dsp_bchg_ea, dsp_btst_ea, dsp_bchg_ea, dsp_btst_ea, dsp_jsclr_ea, dsp_jsset_ea, dsp_jsclr_ea, dsp_jsset_ea,
571: dsp_bchg_pp, dsp_btst_pp, dsp_bchg_pp, dsp_btst_pp, dsp_jsclr_pp, dsp_jsset_pp, dsp_jsclr_pp, dsp_jsset_pp,
572: dsp_jsclr_reg, dsp_jsset_reg, dsp_bchg_reg, dsp_btst_reg, dsp_jsr_ea, dsp_jscc_ea, dsp_undefined, dsp_undefined,
573:
574: /* 0x180 - 0x1bf */
575: dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm, dsp_jmp_imm,
576: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
577: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
578: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
579: dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm, dsp_jsr_imm,
580: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
581: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
582: dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined, dsp_undefined,
583:
584: /* 0x1c0 - 0x1ff */
585: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
586: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
587: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
588: dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm, dsp_jcc_imm,
589: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
590: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
591: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
592: dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm, dsp_jscc_imm,
1.1 root 593: };
594:
1.1.1.6 root 595: static const dsp_emul_t opcodes_parmove[16] = {
596: dsp_pm_0, dsp_pm_1, dsp_pm_2, dsp_pm_3, dsp_pm_4, dsp_pm_5, dsp_pm_5, dsp_pm_5,
597: dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8, dsp_pm_8
1.1 root 598: };
599:
1.1.1.6 root 600: static const dsp_emul_t opcodes_alu[256] = {
1.1.1.4 root 601: /* 0x00 - 0x3f */
1.1.1.6 root 602: dsp_move , dsp_tfr_b_a, dsp_addr_b_a, dsp_tst_a, dsp_undefined, dsp_cmp_b_a, dsp_subr_a, dsp_cmpm_b_a,
603: dsp_undefined, dsp_tfr_a_b, dsp_addr_a_b, dsp_tst_b, dsp_undefined, dsp_cmp_a_b, dsp_subr_b, dsp_cmpm_a_b,
604: dsp_add_b_a, dsp_rnd_a, dsp_addl_b_a, dsp_clr_a, dsp_sub_b_a, dsp_undefined, dsp_subl_a, dsp_not_a,
605: dsp_add_a_b, dsp_rnd_b, dsp_addl_a_b, dsp_clr_b, dsp_sub_a_b, dsp_undefined, dsp_subl_b, dsp_not_b,
1.1.1.7 root 606: dsp_add_x_a, dsp_adc_x_a, dsp_asr_a, dsp_lsr_a, dsp_sub_x_a, dsp_sbc_x_a, dsp_abs_a, dsp_ror_a,
607: dsp_add_x_b, dsp_adc_x_b, dsp_asr_b, dsp_lsr_b, dsp_sub_x_b, dsp_sbc_x_b, dsp_abs_b, dsp_ror_b,
608: dsp_add_y_a, dsp_adc_y_a, dsp_asl_a, dsp_lsl_a, dsp_sub_y_a, dsp_sbc_y_a, dsp_neg_a, dsp_rol_a,
609: dsp_add_y_b, dsp_adc_y_b, dsp_asl_b, dsp_lsl_b, dsp_sub_y_b, dsp_sbc_y_b, dsp_neg_b, dsp_rol_b,
1.1.1.4 root 610:
611: /* 0x40 - 0x7f */
1.1.1.6 root 612: dsp_add_x0_a, dsp_tfr_x0_a, dsp_or_x0_a, dsp_eor_x0_a, dsp_sub_x0_a, dsp_cmp_x0_a, dsp_and_x0_a, dsp_cmpm_x0_a,
613: dsp_add_x0_b, dsp_tfr_x0_b, dsp_or_x0_b, dsp_eor_x0_b, dsp_sub_x0_b, dsp_cmp_x0_b, dsp_and_x0_b, dsp_cmpm_x0_b,
614: dsp_add_y0_a, dsp_tfr_y0_a, dsp_or_y0_a, dsp_eor_y0_a, dsp_sub_y0_a, dsp_cmp_y0_a, dsp_and_y0_a, dsp_cmpm_y0_a,
615: dsp_add_y0_b, dsp_tfr_y0_b, dsp_or_y0_b, dsp_eor_y0_b, dsp_sub_y0_b, dsp_cmp_y0_b, dsp_and_y0_b, dsp_cmpm_y0_b,
616: dsp_add_x1_a, dsp_tfr_x1_a, dsp_or_x1_a, dsp_eor_x1_a, dsp_sub_x1_a, dsp_cmp_x1_a, dsp_and_x1_a, dsp_cmpm_x1_a,
617: dsp_add_x1_b, dsp_tfr_x1_b, dsp_or_x1_b, dsp_eor_x1_b, dsp_sub_x1_b, dsp_cmp_x1_b, dsp_and_x1_b, dsp_cmpm_x1_b,
618: dsp_add_y1_a, dsp_tfr_y1_a, dsp_or_y1_a, dsp_eor_y1_a, dsp_sub_y1_a, dsp_cmp_y1_a, dsp_and_y1_a, dsp_cmpm_y1_a,
619: dsp_add_y1_b, dsp_tfr_y1_b, dsp_or_y1_b, dsp_eor_y1_b, dsp_sub_y1_b, dsp_cmp_y1_b, dsp_and_y1_b, dsp_cmpm_y1_b,
1.1.1.4 root 620:
621: /* 0x80 - 0xbf */
1.1.1.6 root 622: dsp_mpy_p_x0_x0_a, dsp_mpyr_p_x0_x0_a, dsp_mac_p_x0_x0_a, dsp_macr_p_x0_x0_a, dsp_mpy_m_x0_x0_a, dsp_mpyr_m_x0_x0_a, dsp_mac_m_x0_x0_a, dsp_macr_m_x0_x0_a,
623: dsp_mpy_p_x0_x0_b, dsp_mpyr_p_x0_x0_b, dsp_mac_p_x0_x0_b, dsp_macr_p_x0_x0_b, dsp_mpy_m_x0_x0_b, dsp_mpyr_m_x0_x0_b, dsp_mac_m_x0_x0_b, dsp_macr_m_x0_x0_b,
624: dsp_mpy_p_y0_y0_a, dsp_mpyr_p_y0_y0_a, dsp_mac_p_y0_y0_a, dsp_macr_p_y0_y0_a, dsp_mpy_m_y0_y0_a, dsp_mpyr_m_y0_y0_a, dsp_mac_m_y0_y0_a, dsp_macr_m_y0_y0_a,
625: dsp_mpy_p_y0_y0_b, dsp_mpyr_p_y0_y0_b, dsp_mac_p_y0_y0_b, dsp_macr_p_y0_y0_b, dsp_mpy_m_y0_y0_b, dsp_mpyr_m_y0_y0_b, dsp_mac_m_y0_y0_b, dsp_macr_m_y0_y0_b,
626: dsp_mpy_p_x1_x0_a, dsp_mpyr_p_x1_x0_a, dsp_mac_p_x1_x0_a, dsp_macr_p_x1_x0_a, dsp_mpy_m_x1_x0_a, dsp_mpyr_m_x1_x0_a, dsp_mac_m_x1_x0_a, dsp_macr_m_x1_x0_a,
627: dsp_mpy_p_x1_x0_b, dsp_mpyr_p_x1_x0_b, dsp_mac_p_x1_x0_b, dsp_macr_p_x1_x0_b, dsp_mpy_m_x1_x0_b, dsp_mpyr_m_x1_x0_b, dsp_mac_m_x1_x0_b, dsp_macr_m_x1_x0_b,
628: dsp_mpy_p_y1_y0_a, dsp_mpyr_p_y1_y0_a, dsp_mac_p_y1_y0_a, dsp_macr_p_y1_y0_a, dsp_mpy_m_y1_y0_a, dsp_mpyr_m_y1_y0_a, dsp_mac_m_y1_y0_a, dsp_macr_m_y1_y0_a,
629: dsp_mpy_p_y1_y0_b, dsp_mpyr_p_y1_y0_b, dsp_mac_p_y1_y0_b, dsp_macr_p_y1_y0_b, dsp_mpy_m_y1_y0_b, dsp_mpyr_m_y1_y0_b, dsp_mac_m_y1_y0_b, dsp_macr_m_y1_y0_b,
630:
631: /* 0xc0_m_ 0xff */
632: dsp_mpy_p_x0_y1_a, dsp_mpyr_p_x0_y1_a, dsp_mac_p_x0_y1_a, dsp_macr_p_x0_y1_a, dsp_mpy_m_x0_y1_a, dsp_mpyr_m_x0_y1_a, dsp_mac_m_x0_y1_a, dsp_macr_m_x0_y1_a,
633: dsp_mpy_p_x0_y1_b, dsp_mpyr_p_x0_y1_b, dsp_mac_p_x0_y1_b, dsp_macr_p_x0_y1_b, dsp_mpy_m_x0_y1_b, dsp_mpyr_m_x0_y1_b, dsp_mac_m_x0_y1_b, dsp_macr_m_x0_y1_b,
634: dsp_mpy_p_y0_x0_a, dsp_mpyr_p_y0_x0_a, dsp_mac_p_y0_x0_a, dsp_macr_p_y0_x0_a, dsp_mpy_m_y0_x0_a, dsp_mpyr_m_y0_x0_a, dsp_mac_m_y0_x0_a, dsp_macr_m_y0_x0_a,
635: dsp_mpy_p_y0_x0_b, dsp_mpyr_p_y0_x0_b, dsp_mac_p_y0_x0_b, dsp_macr_p_y0_x0_b, dsp_mpy_m_y0_x0_b, dsp_mpyr_m_y0_x0_b, dsp_mac_m_y0_x0_b, dsp_macr_m_y0_x0_b,
636: dsp_mpy_p_x1_y0_a, dsp_mpyr_p_x1_y0_a, dsp_mac_p_x1_y0_a, dsp_macr_p_x1_y0_a, dsp_mpy_m_x1_y0_a, dsp_mpyr_m_x1_y0_a, dsp_mac_m_x1_y0_a, dsp_macr_m_x1_y0_a,
637: dsp_mpy_p_x1_y0_b, dsp_mpyr_p_x1_y0_b, dsp_mac_p_x1_y0_b, dsp_macr_p_x1_y0_b, dsp_mpy_m_x1_y0_b, dsp_mpyr_m_x1_y0_b, dsp_mac_m_x1_y0_b, dsp_macr_m_x1_y0_b,
638: dsp_mpy_p_y1_x1_a, dsp_mpyr_p_y1_x1_a, dsp_mac_p_y1_x1_a, dsp_macr_p_y1_x1_a, dsp_mpy_m_y1_x1_a, dsp_mpyr_m_y1_x1_a, dsp_mac_m_y1_x1_a, dsp_macr_m_y1_x1_a,
639: dsp_mpy_p_y1_x1_b, dsp_mpyr_p_y1_x1_b, dsp_mac_p_y1_x1_b, dsp_macr_p_y1_x1_b, dsp_mpy_m_y1_x1_b, dsp_mpyr_m_y1_x1_b, dsp_mac_m_y1_x1_b, dsp_macr_m_y1_x1_b
1.1 root 640: };
641:
1.1.1.6 root 642: static const int registers_tcc[16][2] = {
1.1 root 643: {DSP_REG_B,DSP_REG_A},
644: {DSP_REG_A,DSP_REG_B},
645: {DSP_REG_NULL,DSP_REG_NULL},
646: {DSP_REG_NULL,DSP_REG_NULL},
647:
648: {DSP_REG_NULL,DSP_REG_NULL},
649: {DSP_REG_NULL,DSP_REG_NULL},
650: {DSP_REG_NULL,DSP_REG_NULL},
651: {DSP_REG_NULL,DSP_REG_NULL},
652:
653: {DSP_REG_X0,DSP_REG_A},
654: {DSP_REG_X0,DSP_REG_B},
655: {DSP_REG_Y0,DSP_REG_A},
656: {DSP_REG_Y0,DSP_REG_B},
1.1.1.2 root 657:
658: {DSP_REG_X1,DSP_REG_A},
659: {DSP_REG_X1,DSP_REG_B},
1.1 root 660: {DSP_REG_Y1,DSP_REG_A},
661: {DSP_REG_Y1,DSP_REG_B}
662: };
663:
1.1.1.6 root 664: static const int registers_mask[64] = {
1.1 root 665: 0, 0, 0, 0,
666: 24, 24, 24, 24,
667: 24, 24, 8, 8,
668: 24, 24, 24, 24,
669:
670: 16, 16, 16, 16,
671: 16, 16, 16, 16,
672: 16, 16, 16, 16,
673: 16, 16, 16, 16,
674:
675: 16, 16, 16, 16,
676: 16, 16, 16, 16,
677: 0, 0, 0, 0,
678: 0, 0, 0, 0,
679:
680: 0, 0, 0, 0,
681: 0, 0, 0, 0,
682: 0, 16, 8, 6,
1.1.1.4 root 683: 16, 16, 16, 16
684: };
685:
1.1.1.6 root 686: static const dsp_interrupt_t dsp_interrupt[12] = {
1.1.1.5 root 687: {DSP_INTER_RESET , 0x00, 0, "Reset"},
688: {DSP_INTER_ILLEGAL , 0x3e, 0, "Illegal"},
689: {DSP_INTER_STACK_ERROR , 0x02, 0, "Stack Error"},
690: {DSP_INTER_TRACE , 0x04, 0, "Trace"},
691: {DSP_INTER_SWI , 0x06, 0, "Swi"},
692: {DSP_INTER_HOST_COMMAND , 0xff, 1, "Host Command"},
693: {DSP_INTER_HOST_RCV_DATA, 0x20, 1, "Host receive"},
694: {DSP_INTER_HOST_TRX_DATA, 0x22, 1, "Host transmit"},
695: {DSP_INTER_SSI_RCV_DATA_E, 0x0e, 2, "SSI receive with exception"},
696: {DSP_INTER_SSI_RCV_DATA , 0x0c, 2, "SSI receive"},
697: {DSP_INTER_SSI_TRX_DATA_E, 0x12, 2, "SSI transmit with exception"},
698: {DSP_INTER_SSI_TRX_DATA , 0x10, 2, "SSI tramsmit"}
1.1.1.4 root 699: };
700:
1.1 root 701:
702: /**********************************
703: * Emulator kernel
704: **********************************/
705:
1.1.1.6 root 706: void dsp56k_init_cpu(void)
1.1 root 707: {
1.1.1.6 root 708: dsp56k_disasm_init();
709: isDsp_in_disasm_mode = false;
1.1.1.2 root 710: start_time = SDL_GetTicks();
711: num_inst = 0;
1.1 root 712: }
713:
1.1.1.6 root 714: /**
715: * Execute one instruction in trace mode at a given PC address.
716: * */
1.1.1.9 ! root 717: Uint16 dsp56k_execute_one_disasm_instruction(FILE *out, Uint16 pc)
1.1.1.6 root 718: {
719: dsp_core_t *ptr1, *ptr2;
720: static dsp_core_t dsp_core_save;
1.1.1.8 root 721: Uint16 instruction_length;
1.1.1.6 root 722:
723: ptr1 = &dsp_core;
724: ptr2 = &dsp_core_save;
725:
726: /* Set DSP in disasm mode */
727: isDsp_in_disasm_mode = true;
728:
729: /* Save DSP context before executing instruction */
730: memcpy(ptr2, ptr1, sizeof(dsp_core));
731:
732: /* execute and disasm instruction */
733: dsp_core.pc = pc;
734:
735: /* Disasm instruction */
736: instruction_length = dsp56k_disasm(DSP_DISASM_MODE) - 1;
737:
738: /* Execute instruction at address given in parameter to get the number of cycles it takes */
739: dsp56k_execute_instruction();
740:
1.1.1.9 ! root 741: fprintf(out, "%s", dsp56k_getInstructionText());
1.1.1.6 root 742:
743: /* Restore DSP context after executing instruction */
744: memcpy(ptr1, ptr2, sizeof(dsp_core));
745:
746: /* Unset DSP in disasm mode */
747: isDsp_in_disasm_mode = false;
748:
749: return instruction_length;
750: }
751:
1.1.1.4 root 752: void dsp56k_execute_instruction(void)
1.1 root 753: {
1.1.1.2 root 754: Uint32 value;
1.1.1.6 root 755: Uint32 disasm_return = 0;
1.1.1.5 root 756: disasm_memory_ptr = 0;
757:
1.1.1.7 root 758: /* Initialise the number of access to the external memory for this instruction */
1.1.1.9 ! root 759: access_to_ext_memory = 0;
1.1.1.7 root 760:
1.1 root 761: /* Decode and execute current instruction */
1.1.1.6 root 762: cur_inst = read_memory_p(dsp_core.pc);
1.1.1.4 root 763:
1.1.1.7 root 764: /* Initialize instruction size and cycle counter */
765: cur_inst_len = 1;
1.1.1.6 root 766: dsp_core.instr_cycle = 2;
1.1 root 767:
1.1.1.6 root 768: /* Disasm current instruction ? (trace mode only) */
769: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
770: /* Call dsp56k_disasm only when DSP is called in trace mode */
771: if (isDsp_in_disasm_mode == false) {
772: disasm_return = dsp56k_disasm(DSP_TRACE_MODE);
773:
774: if (disasm_return != 0 && LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG)) {
775: /* DSP regs trace enabled only if DSP DISASM is enabled */
776: dsp56k_disasm_reg_save();
777: }
778: }
779: }
780:
1.1.1.4 root 781: if (cur_inst < 0x100000) {
782: value = (cur_inst >> 11) & (BITMASK(6) << 3);
783: value += (cur_inst >> 5) & BITMASK(3);
1.1 root 784: opcodes8h[value]();
785: } else {
1.1.1.6 root 786: /* Do parallel move read */
787: opcodes_parmove[(cur_inst>>20) & BITMASK(4)]();
788: }
789:
1.1.1.7 root 790: /* Add the waitstate due to external memory access */
1.1.1.9 ! root 791: /* (2 extra cycles per extra access to the external memory after the first one */
! 792: if (access_to_ext_memory != 0) {
! 793: value = access_to_ext_memory & 1;
! 794: value += (access_to_ext_memory & 2) >> 1;
! 795: value += (access_to_ext_memory & 4) >> 2;
! 796:
! 797: if (value > 1)
! 798: dsp_core.instr_cycle += (value - 1) * 2;
! 799: }
! 800:
1.1.1.6 root 801: /* Disasm current instruction ? (trace mode only) */
802: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM)) {
803: /* Display only when DSP is called in trace mode */
804: if (isDsp_in_disasm_mode == false) {
805: if (disasm_return != 0) {
806: fprintf(stderr, "%s", dsp56k_getInstructionText());
807:
808: /* DSP regs trace enabled only if DSP DISASM is enabled */
809: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_REG))
810: dsp56k_disasm_reg_compare();
811:
812: if (LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM)) {
813: /* 1 memory change to display ? */
814: if (disasm_memory_ptr == 1)
815: fprintf(stderr, "\t%s\n", str_disasm_memory[0]);
816: /* 2 memory changes to display ? */
817: else if (disasm_memory_ptr == 2) {
818: fprintf(stderr, "\t%s\n", str_disasm_memory[0]);
819: fprintf(stderr, "\t%s\n", str_disasm_memory[1]);
820: }
821: }
822: }
823: }
1.1 root 824: }
825:
1.1.1.4 root 826: /* Process the PC */
827: dsp_postexecute_update_pc();
1.1 root 828:
1.1.1.4 root 829: /* Process Interrupts */
1.1 root 830: dsp_postexecute_interrupts();
831:
1.1.1.4 root 832: #if DSP_COUNT_IPS
833: ++num_inst;
834: if ((num_inst & 63) == 0) {
835: /* Evaluate time after <N> instructions have been executed to avoid asking too frequently */
836: Uint32 cur_time = SDL_GetTicks();
837: if (cur_time-start_time>1000) {
838: fprintf(stderr, "Dsp: %d i/s\n", (num_inst*1000)/(cur_time-start_time));
839: start_time=cur_time;
840: num_inst=0;
841: }
842: }
843: #endif
1.1 root 844: }
845:
846: /**********************************
847: * Update the PC
848: **********************************/
849:
850: static void dsp_postexecute_update_pc(void)
851: {
852: /* When running a REP, PC must stay on the current instruction */
1.1.1.6 root 853: if (dsp_core.loop_rep) {
1.1 root 854: /* Is PC on the instruction to repeat ? */
1.1.1.6 root 855: if (dsp_core.pc_on_rep==0) {
856: --dsp_core.registers[DSP_REG_LC];
857: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1 root 858:
1.1.1.6 root 859: if (dsp_core.registers[DSP_REG_LC] > 0) {
1.1.1.7 root 860: cur_inst_len = 0; /* Stay on this instruction */
1.1 root 861: } else {
1.1.1.6 root 862: dsp_core.loop_rep = 0;
863: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[DSP_REG_LCSAVE];
1.1 root 864: }
865: } else {
866: /* Init LC at right value */
1.1.1.6 root 867: if (dsp_core.registers[DSP_REG_LC] == 0) {
868: dsp_core.registers[DSP_REG_LC] = 0x010000;
1.1 root 869: }
1.1.1.6 root 870: dsp_core.pc_on_rep = 0;
1.1 root 871: }
872: }
873:
874: /* Normal execution, go to next instruction */
1.1.1.6 root 875: dsp_core.pc += cur_inst_len;
1.1 root 876:
877: /* When running a DO loop, we test the end of loop with the */
878: /* updated PC, pointing to last instruction of the loop */
1.1.1.6 root 879: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_LF)) {
1.1 root 880:
881: /* Did we execute the last instruction in loop ? */
1.1.1.7 root 882: if (dsp_core.pc == dsp_core.registers[DSP_REG_LA] + 1) {
1.1.1.6 root 883: --dsp_core.registers[DSP_REG_LC];
884: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1 root 885:
1.1.1.7 root 886: if (dsp_core.registers[DSP_REG_LC] == 0) {
1.1 root 887: /* end of loop */
1.1.1.4 root 888: Uint32 saved_pc, saved_sr;
889:
890: dsp_stack_pop(&saved_pc, &saved_sr);
1.1.1.6 root 891: dsp_core.registers[DSP_REG_SR] &= 0x7f;
892: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
893: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
1.1 root 894: } else {
895: /* Loop one more time */
1.1.1.6 root 896: dsp_core.pc = dsp_core.registers[DSP_REG_SSH];
1.1 root 897: }
898: }
899: }
900: }
901:
902: /**********************************
903: * Interrupts
904: **********************************/
905:
1.1.1.5 root 906: /* Post a new interrupt to the interrupt table */
907: void dsp_add_interrupt(Uint16 inter)
908: {
909: /* detect if this interrupt is used or not */
1.1.1.6 root 910: if (dsp_core.interrupt_ipl[inter] == -1)
1.1.1.5 root 911: return;
912:
913: /* add this interrupt to the pending interrupts table */
1.1.1.6 root 914: if (dsp_core.interrupt_isPending[inter] == 0) {
915: dsp_core.interrupt_isPending[inter] = 1;
916: dsp_core.interrupt_counter ++;
1.1.1.5 root 917: }
918: }
919:
920: static void dsp_setInterruptIPL(Uint32 value)
921: {
922: Uint32 ipl_ssi, ipl_hi, i;
923:
924: ipl_ssi = ((value >> 12) & 3) - 1;
925: ipl_hi = ((value >> 10) & 3) - 1;
926:
927: /* set IPL_HI */
1.1.1.7 root 928: for (i=5; i<8; i++) {
1.1.1.6 root 929: dsp_core.interrupt_ipl[i] = ipl_hi;
1.1.1.5 root 930: }
931:
932: /* set IPL_SSI */
1.1.1.7 root 933: for (i=8; i<12; i++) {
1.1.1.6 root 934: dsp_core.interrupt_ipl[i] = ipl_ssi;
1.1.1.5 root 935: }
936: }
937:
1.1 root 938: static void dsp_postexecute_interrupts(void)
939: {
1.1.1.5 root 940: Uint32 index, instr, i;
941: Sint32 ipl_to_raise, ipl_sr;
1.1.1.4 root 942:
943: /* REP is not interruptible */
1.1.1.6 root 944: if (dsp_core.loop_rep) {
1.1.1.4 root 945: return;
946: }
947:
948: /* A fast interrupt can not be interrupted. */
1.1.1.6 root 949: if (dsp_core.interrupt_state == DSP_INTERRUPT_DISABLED) {
1.1.1.5 root 950:
1.1.1.6 root 951: switch (dsp_core.interrupt_pipeline_count) {
1.1.1.5 root 952: case 5:
1.1.1.6 root 953: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 954: return;
955: case 4:
956: /* Prefetch interrupt instruction 1 */
1.1.1.6 root 957: dsp_core.interrupt_save_pc = dsp_core.pc;
958: dsp_core.pc = dsp_core.interrupt_instr_fetch;
1.1.1.5 root 959:
960: /* is it a LONG interrupt ? */
1.1.1.6 root 961: instr = read_memory_p(dsp_core.interrupt_instr_fetch);
1.1.1.5 root 962: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1.1.1.6 root 963: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
964: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
965: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1.1.1.5 root 966: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
967: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1.1.1.6 root 968: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1.1.1.5 root 969: }
1.1.1.6 root 970: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 971: return;
972: case 3:
973: /* Prefetch interrupt instruction 2 */
1.1.1.6 root 974: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+1) {
975: instr = read_memory_p(dsp_core.pc);
1.1.1.5 root 976: if ( ((instr & 0xfff000) == 0x0d0000) || ((instr & 0xffc0ff) == 0x0bc080) ) {
1.1.1.6 root 977: dsp_core.interrupt_state = DSP_INTERRUPT_LONG;
978: dsp_stack_push(dsp_core.interrupt_save_pc, dsp_core.registers[DSP_REG_SR], 0);
979: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_LF)|(1<<DSP_SR_T) |
1.1.1.5 root 980: (1<<DSP_SR_S1)|(1<<DSP_SR_S0) |
981: (1<<DSP_SR_I0)|(1<<DSP_SR_I1));
1.1.1.6 root 982: dsp_core.registers[DSP_REG_SR] |= dsp_core.interrupt_IplToRaise<<DSP_SR_I0;
1.1.1.5 root 983: }
984: }
1.1.1.6 root 985: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 986: return;
987: case 2:
988: /* 1 instruction executed after interrupt */
989: /* before re enable interrupts */
990: /* Was it a FAST interrupt ? */
1.1.1.6 root 991: if (dsp_core.pc == dsp_core.interrupt_instr_fetch+2) {
992: dsp_core.pc = dsp_core.interrupt_save_pc;
1.1.1.5 root 993: }
1.1.1.6 root 994: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 995: return;
996: case 1:
997: /* Last instruction executed after interrupt */
998: /* before re enable interrupts */
1.1.1.6 root 999: dsp_core.interrupt_pipeline_count --;
1.1.1.5 root 1000: return;
1001: case 0:
1002: /* Re enable interrupts */
1.1.1.6 root 1003: /* All 6 instruction are done, Interrupts can be enabled again */
1004: dsp_core.interrupt_save_pc = -1;
1005: dsp_core.interrupt_instr_fetch = -1;
1006: dsp_core.interrupt_state = DSP_INTERRUPT_NONE;
1007: break;
1.1.1.4 root 1008: }
1009: }
1.1 root 1010:
1.1.1.4 root 1011: /* Trace Interrupt ? */
1.1.1.6 root 1012: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_T)) {
1.1.1.5 root 1013: dsp_add_interrupt(DSP_INTER_TRACE);
1.1.1.4 root 1014: }
1015:
1016: /* No interrupt to execute */
1.1.1.6 root 1017: if (dsp_core.interrupt_counter == 0) {
1.1.1.4 root 1018: return;
1.1 root 1019: }
1020:
1.1.1.5 root 1021: /* search for an interrupt */
1.1.1.6 root 1022: ipl_sr = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_I0) & BITMASK(2);
1.1.1.5 root 1023: index = 0xffff;
1024: ipl_to_raise = -1;
1025:
1026: /* Arbitrate between all pending interrupts */
1027: for (i=0; i<12; i++) {
1.1.1.6 root 1028: if (dsp_core.interrupt_isPending[i] == 1) {
1.1.1.5 root 1029:
1030: /* level 3 interrupt ? */
1.1.1.6 root 1031: if (dsp_core.interrupt_ipl[i] == 3) {
1.1.1.5 root 1032: index = i;
1033: break;
1034: }
1.1 root 1035:
1.1.1.5 root 1036: /* level 0, 1 ,2 interrupt ? */
1037: /* if interrupt is masked in SR, don't process it */
1.1.1.6 root 1038: if (dsp_core.interrupt_ipl[i] < ipl_sr)
1.1.1.5 root 1039: continue;
1.1 root 1040:
1.1.1.5 root 1041: /* if interrupt is lower or equal than current arbitrated interrupt */
1.1.1.6 root 1042: if (dsp_core.interrupt_ipl[i] <= ipl_to_raise)
1.1.1.5 root 1043: continue;
1044:
1045: /* save current arbitrated interrupt */
1046: index = i;
1.1.1.6 root 1047: ipl_to_raise = dsp_core.interrupt_ipl[i];
1.1 root 1048: }
1049: }
1.1.1.4 root 1050:
1.1.1.5 root 1051: /* If there's no interrupt to process, return */
1052: if (index == 0xffff) {
1.1.1.4 root 1053: return;
1054: }
1055:
1.1.1.5 root 1056: /* remove this interrupt from the pending interrupts table */
1.1.1.6 root 1057: dsp_core.interrupt_isPending[index] = 0;
1058: dsp_core.interrupt_counter --;
1.1.1.5 root 1059:
1060: /* process arbritrated interrupt */
1.1.1.6 root 1061: ipl_to_raise = dsp_core.interrupt_ipl[index] + 1;
1.1.1.5 root 1062: if (ipl_to_raise > 3) {
1063: ipl_to_raise = 3;
1064: }
1065:
1.1.1.6 root 1066: dsp_core.interrupt_instr_fetch = dsp_interrupt[index].vectorAddr;
1067: dsp_core.interrupt_pipeline_count = 5;
1068: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1069: dsp_core.interrupt_IplToRaise = ipl_to_raise;
1070:
1071: LOG_TRACE(TRACE_DSP_INTERRUPT, "Dsp interrupt: %s\n", dsp_interrupt[index].name);
1.1.1.5 root 1072:
1073: /* SSI receive data with exception ? */
1.1.1.6 root 1074: if (dsp_core.interrupt_instr_fetch == 0xe) {
1075: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_ROE);
1.1.1.4 root 1076: }
1077:
1.1.1.5 root 1078: /* SSI transmit data with exception ? */
1.1.1.6 root 1079: else if (dsp_core.interrupt_instr_fetch == 0x12) {
1080: dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR] &= 0xff-(1<<DSP_SSI_SR_TUE);
1.1.1.4 root 1081: }
1082:
1083: /* host command ? */
1.1.1.6 root 1084: else if (dsp_core.interrupt_instr_fetch == 0xff) {
1.1.1.4 root 1085: /* Clear HC and HCP interrupt */
1.1.1.6 root 1086: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR] &= 0xff - (1<<DSP_HOST_HSR_HCP);
1087: dsp_core.hostport[CPU_HOST_CVR] &= 0xff - (1<<CPU_HOST_CVR_HC);
1.1.1.4 root 1088:
1.1.1.6 root 1089: dsp_core.interrupt_instr_fetch = dsp_core.hostport[CPU_HOST_CVR] & BITMASK(5);
1090: dsp_core.interrupt_instr_fetch *= 2;
1.1.1.4 root 1091: }
1.1 root 1092: }
1093:
1094: /**********************************
1095: * Set/clear ccr bits
1096: **********************************/
1097:
1098: /* reg0 has bits 55..48 */
1099: /* reg1 has bits 47..24 */
1100: /* reg2 has bits 23..0 */
1101:
1.1.1.6 root 1102: static void dsp_ccr_update_e_u_n_z(Uint32 reg0, Uint32 reg1, Uint32 reg2)
1103: {
1104: Uint32 scaling, value_e, value_u;
1.1.1.4 root 1105:
1.1.1.6 root 1106: /* Initialize SR register */
1107: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E) | (1<<DSP_SR_U) | (1<<DSP_SR_N) | (1<<DSP_SR_Z));
1.1.1.4 root 1108:
1.1.1.6 root 1109: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
1.1 root 1110: switch(scaling) {
1111: case 0:
1.1.1.6 root 1112: /* Extension Bit (E) */
1113: value_e = (reg0<<1) + (reg1>>23);
1114: if ((value_e != 0) && (value_e != BITMASK(9)))
1115: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1116:
1117: /* Unnormalized bit (U) */
1118: if ((reg1 & 0xc00000) == 0 || (reg1 & 0xc00000) == 0xc00000)
1119: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1120: break;
1121: case 1:
1.1.1.6 root 1122: /* Extension Bit (E) */
1123: if ((reg0 != 0) && (reg0 != BITMASK(8)))
1124: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1125:
1126: /* Unnormalized bit (U) */
1127: value_u = ((reg0<<1) + (reg1>>23)) & 3;
1128: if (value_u == 0 || value_u == 3)
1129: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1130: break;
1131: case 2:
1.1.1.6 root 1132: /* Extension Bit (E) */
1133: value_e = (reg0<<2) + (reg1>>22);
1134: if ((value_e != 0) && (value_e != BITMASK(10)))
1135: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_E;
1136:
1137: /* Unnormalized bit (U) */
1138: if ((reg1 & 0x600000) == 0 || (reg1 & 0x600000) == 0x600000)
1139: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_U;
1.1 root 1140: break;
1141: default:
1142: return;
1143: break;
1144: }
1145:
1.1.1.6 root 1146: /* Zero Flag (Z) */
1147: if ((reg1 == 0) && (reg2 == 0) && (reg0 == 0))
1148: dsp_core.registers[DSP_REG_SR] |= 1 << DSP_SR_Z;
1.1.1.4 root 1149:
1.1.1.6 root 1150: /* Negative Flag (N) */
1151: dsp_core.registers[DSP_REG_SR] |= (reg0>>4) & 0x8;
1.1 root 1152: }
1153:
1154: /**********************************
1155: * Read/Write memory functions
1156: **********************************/
1157:
1.1.1.2 root 1158: static Uint32 read_memory_disasm(int space, Uint16 address)
1.1 root 1159: {
1.1.1.4 root 1160: /* Internal RAM ? */
1161: if (address<0x100) {
1.1.1.6 root 1162: return dsp_core.ramint[space][address] & BITMASK(24);
1.1.1.4 root 1163: }
1.1 root 1164:
1.1.1.4 root 1165: if (space==DSP_SPACE_P) {
1166: return read_memory_p(address);
1.1 root 1167: }
1168:
1.1.1.4 root 1169: /* Internal ROM? */
1.1.1.6 root 1170: if ((dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) &&
1.1.1.4 root 1171: (address<0x200)) {
1.1.1.6 root 1172: return dsp_core.rom[space][address] & BITMASK(24);
1.1.1.4 root 1173: }
1174:
1175: /* Peripheral address ? */
1176: if (address >= 0xffc0) {
1.1.1.6 root 1177: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_HOST_HTX)) {
1178: return dsp_core.dsp_host_htx;
1.1.1.4 root 1179: }
1180: if ((space==DSP_SPACE_X) && (address==0xffc0+DSP_SSI_TX)) {
1.1.1.6 root 1181: return dsp_core.ssi.transmit_value;
1.1.1.4 root 1182: }
1.1.1.6 root 1183: return dsp_core.periph[space][address-0xffc0] & BITMASK(24);
1.1.1.4 root 1184: }
1185:
1186: /* Falcon: External RAM, map X to upper 16K of matching space in Y,P */
1187: address &= (DSP_RAMSIZE>>1) - 1;
1188: if (space == DSP_SPACE_X) {
1189: address += DSP_RAMSIZE>>1;
1190: }
1191:
1192: /* Falcon: External RAM, finally map X,Y to P */
1.1.1.6 root 1193: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1.1 root 1194: }
1195:
1.1.1.4 root 1196: static inline Uint32 read_memory_p(Uint16 address)
1197: {
1198: /* Internal RAM ? */
1.1.1.7 root 1199: if (address < 0x200) {
1.1.1.6 root 1200: return dsp_core.ramint[DSP_SPACE_P][address] & BITMASK(24);
1.1.1.4 root 1201: }
1202:
1.1.1.9 ! root 1203: /* Access to the external P memory */
! 1204: access_to_ext_memory |= 1 << EXT_P_MEMORY;
1.1.1.7 root 1205:
1.1.1.4 root 1206: /* External RAM, mask address to available ram size */
1.1.1.6 root 1207: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1.1.1.4 root 1208: }
1209:
1.1.1.2 root 1210: static Uint32 read_memory(int space, Uint16 address)
1.1 root 1211: {
1.1.1.4 root 1212: Uint32 value;
1.1 root 1213:
1.1.1.4 root 1214: /* Internal RAM ? */
1215: if (address < 0x100) {
1.1.1.6 root 1216: return dsp_core.ramint[space][address] & BITMASK(24);
1.1.1.4 root 1217: }
1.1 root 1218:
1.1.1.4 root 1219: if (space == DSP_SPACE_P) {
1220: return read_memory_p(address);
1221: }
1222:
1223: /* Internal ROM ? */
1224: if (address < 0x200) {
1.1.1.6 root 1225: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1226: return dsp_core.rom[space][address] & BITMASK(24);
1.1.1.4 root 1227: }
1228: }
1229:
1230: /* Peripheral address ? */
1231: if (address >= 0xffc0) {
1.1.1.6 root 1232: value = dsp_core.periph[space][address-0xffc0] & BITMASK(24);
1.1.1.4 root 1233: if (space == DSP_SPACE_X) {
1234: if (address == 0xffc0+DSP_HOST_HRX) {
1.1.1.6 root 1235: value = dsp_core.dsp_host_rtx;
1236: dsp_core_hostport_dspread();
1.1.1.4 root 1237: }
1238: else if (address == 0xffc0+DSP_SSI_RX) {
1.1.1.6 root 1239: value = dsp_core_ssi_readRX();
1.1 root 1240: }
1.1.1.4 root 1241: }
1242: return value;
1.1 root 1243: }
1244:
1.1.1.9 ! root 1245: /* Falcon: External X or Y RAM access */
1.1.1.4 root 1246: address &= (DSP_RAMSIZE>>1) - 1;
1247:
1248: if (space == DSP_SPACE_X) {
1.1.1.9 ! root 1249: /* Map X to upper 16K of matching space in Y,P */
1.1.1.4 root 1250: address += DSP_RAMSIZE>>1;
1.1.1.9 ! root 1251:
! 1252: /* Set one access to the X external memory */
! 1253: access_to_ext_memory |= 1 << EXT_X_MEMORY;
! 1254: }
! 1255: else {
! 1256: /* Access to the Y external memory */
! 1257: access_to_ext_memory |= 1 << EXT_Y_MEMORY;
1.1.1.4 root 1258: }
1259:
1.1.1.9 ! root 1260:
1.1.1.4 root 1261: /* Falcon: External RAM, finally map X,Y to P */
1.1.1.6 root 1262: return dsp_core.ramext[address & (DSP_RAMSIZE-1)] & BITMASK(24);
1263: }
1264:
1265: static inline void write_memory(int space, Uint16 address, Uint32 value)
1266: {
1.1.1.7 root 1267: if (unlikely(LOG_TRACE_LEVEL(TRACE_DSP_DISASM_MEM)))
1.1.1.6 root 1268: write_memory_disasm(space, address, value);
1269: else
1270: write_memory_raw(space, address, value);
1.1 root 1271: }
1272:
1.1.1.4 root 1273: static void write_memory_raw(int space, Uint16 address, Uint32 value)
1.1 root 1274: {
1275: value &= BITMASK(24);
1276:
1.1.1.4 root 1277: /* Peripheral address ? */
1278: if (address >= 0xffc0) {
1279: if (space == DSP_SPACE_X) {
1280: switch(address-0xffc0) {
1281: case DSP_HOST_HTX:
1.1.1.6 root 1282: dsp_core.dsp_host_htx = value;
1283: dsp_core_hostport_dspwrite();
1.1.1.4 root 1284: break;
1285: case DSP_HOST_HCR:
1.1.1.6 root 1286: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] = value;
1.1.1.4 root 1287: /* Set HF3 and HF2 accordingly on the host side */
1.1.1.6 root 1288: dsp_core.hostport[CPU_HOST_ISR] &=
1.1.1.4 root 1289: BITMASK(8)-((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1.1.1.6 root 1290: dsp_core.hostport[CPU_HOST_ISR] |=
1291: dsp_core.periph[DSP_SPACE_X][DSP_HOST_HCR] & ((1<<CPU_HOST_ISR_HF3)|(1<<CPU_HOST_ISR_HF2));
1.1.1.4 root 1292: break;
1293: case DSP_HOST_HSR:
1294: /* Read only */
1295: break;
1296: case DSP_SSI_CRA:
1297: case DSP_SSI_CRB:
1.1.1.6 root 1298: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1299: dsp_core_ssi_configure(address-0xffc0, value);
1.1.1.4 root 1300: break;
1301: case DSP_SSI_TSR:
1.1.1.6 root 1302: dsp_core_ssi_writeTSR();
1.1.1.4 root 1303: break;
1304: case DSP_SSI_TX:
1.1.1.6 root 1305: dsp_core_ssi_writeTX(value);
1.1.1.4 root 1306: break;
1.1.1.5 root 1307: case DSP_IPR:
1.1.1.6 root 1308: dsp_core.periph[DSP_SPACE_X][DSP_IPR] = value;
1.1.1.5 root 1309: dsp_setInterruptIPL(value);
1310: break;
1311: case DSP_PCD:
1.1.1.6 root 1312: dsp_core.periph[DSP_SPACE_X][DSP_PCD] = value;
1313: dsp_core_setPortCDataRegister(value);
1.1.1.5 root 1314: break;
1.1.1.4 root 1315: default:
1.1.1.6 root 1316: dsp_core.periph[DSP_SPACE_X][address-0xffc0] = value;
1.1.1.4 root 1317: break;
1.1 root 1318: }
1.1.1.4 root 1319: return;
1320: }
1321: else if (space == DSP_SPACE_Y) {
1.1.1.6 root 1322: dsp_core.periph[DSP_SPACE_Y][address-0xffc0] = value;
1.1.1.4 root 1323: return;
1324: }
1325: }
1326:
1327: /* Internal RAM ? */
1328: if (address < 0x100) {
1.1.1.6 root 1329: dsp_core.ramint[space][address] = value;
1.1.1.4 root 1330: return;
1331: }
1.1.1.2 root 1332:
1.1.1.4 root 1333: /* Internal ROM ? */
1334: if (address < 0x200) {
1335: if (space != DSP_SPACE_P) {
1.1.1.6 root 1336: if (dsp_core.registers[DSP_REG_OMR] & (1<<DSP_OMR_DE)) {
1.1.1.2 root 1337: /* Can not write to ROM space */
1.1 root 1338: return;
1339: }
1.1.1.4 root 1340: }
1341: else {
1342: /* Space P RAM */
1.1.1.6 root 1343: dsp_core.ramint[DSP_SPACE_P][address] = value;
1.1.1.4 root 1344: return;
1345: }
1.1 root 1346: }
1347:
1.1.1.9 ! root 1348: /* Access to X, Y or P external RAM */
1.1.1.4 root 1349:
1.1.1.9 ! root 1350: if (space == DSP_SPACE_P) {
! 1351: /* Access to the P external RAM */
! 1352: access_to_ext_memory |= 1 << EXT_P_MEMORY;
! 1353: }
! 1354: else {
1.1.1.4 root 1355: address &= (DSP_RAMSIZE>>1) - 1;
1356:
1.1.1.9 ! root 1357: if (space == DSP_SPACE_X) {
! 1358: /* Access to the X external RAM */
! 1359: /* map X to upper 16K of matching space in Y,P */
! 1360: address += DSP_RAMSIZE>>1;
! 1361: access_to_ext_memory |= 1;
! 1362: }
! 1363: else {
! 1364: /* Access to the Y external RAM */
! 1365: access_to_ext_memory |= 1 << EXT_Y_MEMORY;
! 1366: }
1.1.1.4 root 1367: }
1368:
1369: /* Falcon: External RAM, map X,Y to P */
1.1.1.6 root 1370: dsp_core.ramext[address & (DSP_RAMSIZE-1)] = value;
1.1.1.2 root 1371: }
1372:
1.1.1.4 root 1373: static void write_memory_disasm(int space, Uint16 address, Uint32 value)
1.1.1.2 root 1374: {
1.1.1.4 root 1375: Uint32 oldvalue, curvalue;
1376: Uint8 space_c = 'p';
1377:
1.1.1.2 root 1378: value &= BITMASK(24);
1.1.1.6 root 1379: oldvalue = read_memory_disasm(space, address);
1.1.1.2 root 1380:
1381: write_memory_raw(space,address,value);
1382:
1.1 root 1383: switch(space) {
1384: case DSP_SPACE_X:
1.1.1.4 root 1385: space_c = 'x';
1.1 root 1386: break;
1387: case DSP_SPACE_Y:
1.1.1.4 root 1388: space_c = 'y';
1389: break;
1390: default:
1.1 root 1391: break;
1392: }
1.1.1.4 root 1393:
1.1.1.6 root 1394: curvalue = read_memory_disasm(space, address);
1.1.1.5 root 1395: sprintf(str_disasm_memory[disasm_memory_ptr],"Mem: %c:0x%04x 0x%06x -> 0x%06x", space_c, address, oldvalue, curvalue);
1396: disasm_memory_ptr ++;
1.1 root 1397: }
1398:
1.1.1.4 root 1399: static void dsp_write_reg(Uint32 numreg, Uint32 value)
1400: {
1.1.1.5 root 1401: Uint32 stack_error;
1.1.1.4 root 1402:
1.1.1.7 root 1403: switch (numreg) {
1404: case DSP_REG_A:
1405: dsp_core.registers[DSP_REG_A0] = 0;
1406: dsp_core.registers[DSP_REG_A1] = value;
1407: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
1408: break;
1409: case DSP_REG_B:
1410: dsp_core.registers[DSP_REG_B0] = 0;
1411: dsp_core.registers[DSP_REG_B1] = value;
1412: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
1413: break;
1414: case DSP_REG_OMR:
1415: dsp_core.registers[DSP_REG_OMR] = value & 0xc7;
1416: break;
1417: case DSP_REG_SR:
1418: dsp_core.registers[DSP_REG_SR] = value & 0xaf7f;
1419: break;
1420: case DSP_REG_SP:
1.1.1.8 root 1421: stack_error = dsp_core.registers[DSP_REG_SP] & (3<<DSP_SP_SE);
1422: if ((stack_error==0) && (value & (3<<DSP_SP_SE))) {
1423: /* Stack underflow or overflow detected, raise interrupt */
1.1.1.7 root 1424: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.9 ! root 1425: dsp_core.registers[DSP_REG_SP] = value & (3<<DSP_SP_SE);
1.1.1.7 root 1426: if (!isDsp_in_disasm_mode)
1.1.1.8 root 1427: fprintf(stderr,"Dsp: Stack Overflow or Underflow\n");
1.1.1.9 ! root 1428: if (bExceptionDebugging)
! 1429: DebugUI(REASON_DSP_EXCEPTION);
1.1.1.7 root 1430: }
1.1.1.8 root 1431: else
1432: dsp_core.registers[DSP_REG_SP] = value & BITMASK(6);
1.1.1.7 root 1433: dsp_compute_ssh_ssl();
1434: break;
1435: case DSP_REG_SSH:
1436: dsp_stack_push(value, 0, 1);
1437: break;
1438: case DSP_REG_SSL:
1439: numreg = dsp_core.registers[DSP_REG_SP] & BITMASK(4);
1440: if (numreg == 0) {
1441: value = 0;
1442: }
1443: dsp_core.stack[1][numreg] = value & BITMASK(16);
1444: dsp_core.registers[DSP_REG_SSL] = value & BITMASK(16);
1445: break;
1446: default:
1447: dsp_core.registers[numreg] = value;
1448: dsp_core.registers[numreg] &= BITMASK(registers_mask[numreg]);
1449: break;
1.1.1.4 root 1450: }
1451: }
1452:
1.1 root 1453: /**********************************
1454: * Stack push/pop
1455: **********************************/
1456:
1.1.1.4 root 1457: static void dsp_stack_push(Uint32 curpc, Uint32 cursr, Uint16 sshOnly)
1.1 root 1458: {
1.1.1.4 root 1459: Uint32 stack_error, underflow, stack;
1460:
1.1.1.6 root 1461: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1462: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1463: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) + 1;
1.1.1.4 root 1464:
1465:
1466: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1.1 root 1467: /* Stack full, raise interrupt */
1.1.1.5 root 1468: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.6 root 1469: if (!isDsp_in_disasm_mode)
1470: fprintf(stderr,"Dsp: Stack Overflow\n");
1.1.1.9 ! root 1471: if (bExceptionDebugging)
! 1472: DebugUI(REASON_DSP_EXCEPTION);
1.1 root 1473: }
1.1.1.4 root 1474:
1.1.1.6 root 1475: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1.1.1.4 root 1476: stack &= BITMASK(4);
1.1 root 1477:
1.1.1.4 root 1478: if (stack) {
1479: /* SSH part */
1.1.1.6 root 1480: dsp_core.stack[0][stack] = curpc & BITMASK(16);
1.1.1.4 root 1481: /* SSL part, if instruction is not like "MOVEC xx, SSH" */
1482: if (sshOnly == 0) {
1.1.1.6 root 1483: dsp_core.stack[1][stack] = cursr & BITMASK(16);
1.1.1.4 root 1484: }
1485: } else {
1.1.1.6 root 1486: dsp_core.stack[0][0] = 0;
1487: dsp_core.stack[1][0] = 0;
1.1.1.4 root 1488: }
1.1 root 1489:
1.1.1.4 root 1490: /* Update SSH and SSL registers */
1.1.1.6 root 1491: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1492: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1 root 1493: }
1494:
1.1.1.2 root 1495: static void dsp_stack_pop(Uint32 *newpc, Uint32 *newsr)
1.1 root 1496: {
1.1.1.4 root 1497: Uint32 stack_error, underflow, stack;
1498:
1.1.1.6 root 1499: stack_error = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_SE);
1500: underflow = dsp_core.registers[DSP_REG_SP] & (1<<DSP_SP_UF);
1501: stack = (dsp_core.registers[DSP_REG_SP] & BITMASK(4)) - 1;
1.1.1.4 root 1502:
1503: if ((stack_error==0) && (stack & (1<<DSP_SP_SE))) {
1504: /* Stack empty*/
1.1.1.5 root 1505: dsp_add_interrupt(DSP_INTER_STACK_ERROR);
1.1.1.6 root 1506: if (!isDsp_in_disasm_mode)
1507: fprintf(stderr,"Dsp: Stack underflow\n");
1.1.1.9 ! root 1508: if (bExceptionDebugging)
! 1509: DebugUI(REASON_DSP_EXCEPTION);
1.1 root 1510: }
1511:
1.1.1.6 root 1512: dsp_core.registers[DSP_REG_SP] = (underflow | stack_error | stack) & BITMASK(6);
1.1.1.4 root 1513: stack &= BITMASK(4);
1.1.1.6 root 1514: *newpc = dsp_core.registers[DSP_REG_SSH];
1515: *newsr = dsp_core.registers[DSP_REG_SSL];
1.1.1.4 root 1516:
1.1.1.6 root 1517: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1518: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1.1.4 root 1519: }
1520:
1521: static void dsp_compute_ssh_ssl(void)
1522: {
1523: Uint32 stack;
1.1 root 1524:
1.1.1.6 root 1525: stack = dsp_core.registers[DSP_REG_SP];
1.1.1.4 root 1526: stack &= BITMASK(4);
1.1.1.6 root 1527: dsp_core.registers[DSP_REG_SSH] = dsp_core.stack[0][stack];
1528: dsp_core.registers[DSP_REG_SSL] = dsp_core.stack[1][stack];
1.1 root 1529: }
1530:
1531: /**********************************
1532: * Effective address calculation
1533: **********************************/
1534:
1.1.1.2 root 1535: static void dsp_update_rn(Uint32 numreg, Sint16 modifier)
1.1 root 1536: {
1.1.1.2 root 1537: Sint16 value;
1538: Uint16 m_reg;
1.1 root 1539:
1.1.1.6 root 1540: m_reg = (Uint16) dsp_core.registers[DSP_REG_M0+numreg];
1.1.1.7 root 1541: if (m_reg == 65535) {
1542: /* Linear addressing mode */
1543: value = (Sint16) dsp_core.registers[DSP_REG_R0+numreg];
1544: value += modifier;
1545: dsp_core.registers[DSP_REG_R0+numreg] = ((Uint32) value) & BITMASK(16);
1546: } else if (m_reg == 0) {
1.1 root 1547: /* Bit reversed carry update */
1548: dsp_update_rn_bitreverse(numreg);
1.1.1.4 root 1549: } else if (m_reg<=32767) {
1.1 root 1550: /* Modulo update */
1551: dsp_update_rn_modulo(numreg, modifier);
1552: } else {
1553: /* Undefined */
1554: }
1555: }
1556:
1.1.1.2 root 1557: static void dsp_update_rn_bitreverse(Uint32 numreg)
1.1 root 1558: {
1559: int revbits, i;
1.1.1.2 root 1560: Uint32 value, r_reg;
1.1 root 1561:
1562: /* Check how many bits to reverse */
1.1.1.6 root 1563: value = dsp_core.registers[DSP_REG_N0+numreg];
1.1 root 1564: for (revbits=0;revbits<16;revbits++) {
1565: if (value & (1<<revbits)) {
1566: break;
1567: }
1568: }
1569: revbits++;
1570:
1571: /* Reverse Rn bits */
1.1.1.6 root 1572: r_reg = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1573: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1574: for (i=0;i<revbits;i++) {
1575: if (r_reg & (1<<i)) {
1576: value |= 1<<(revbits-i-1);
1577: }
1578: }
1579:
1580: /* Increment */
1581: value++;
1582: value &= BITMASK(revbits);
1583:
1584: /* Reverse Rn bits */
1585: r_reg &= (BITMASK(16)-BITMASK(revbits));
1586: r_reg |= value;
1587:
1588: value = r_reg & (BITMASK(16)-BITMASK(revbits));
1589: for (i=0;i<revbits;i++) {
1590: if (r_reg & (1<<i)) {
1591: value |= 1<<(revbits-i-1);
1592: }
1593: }
1594:
1.1.1.6 root 1595: dsp_core.registers[DSP_REG_R0+numreg] = value;
1.1 root 1596: }
1597:
1.1.1.2 root 1598: static void dsp_update_rn_modulo(Uint32 numreg, Sint16 modifier)
1.1 root 1599: {
1.1.1.2 root 1600: Uint16 bufsize, modulo, lobound, hibound, bufmask;
1.1.1.4 root 1601: Sint16 r_reg, orig_modifier=modifier;
1.1 root 1602:
1.1.1.6 root 1603: modulo = dsp_core.registers[DSP_REG_M0+numreg]+1;
1.1 root 1604: bufsize = 1;
1.1.1.2 root 1605: bufmask = BITMASK(16);
1.1 root 1606: while (bufsize < modulo) {
1607: bufsize <<= 1;
1.1.1.2 root 1608: bufmask <<= 1;
1.1 root 1609: }
1610:
1.1.1.6 root 1611: lobound = dsp_core.registers[DSP_REG_R0+numreg] & bufmask;
1.1.1.2 root 1612: hibound = lobound + modulo - 1;
1.1 root 1613:
1.1.1.6 root 1614: r_reg = (Sint16) dsp_core.registers[DSP_REG_R0+numreg];
1.1.1.4 root 1615:
1616: if (orig_modifier>modulo) {
1617: while (modifier>bufsize) {
1618: r_reg += bufsize;
1619: modifier -= bufsize;
1620: }
1621: while (modifier<-bufsize) {
1622: r_reg -= bufsize;
1623: modifier += bufsize;
1624: }
1.1.1.2 root 1625: }
1.1.1.4 root 1626:
1.1 root 1627: r_reg += modifier;
1.1.1.4 root 1628:
1629: if (orig_modifier!=modulo) {
1630: if (r_reg>hibound) {
1631: r_reg -= modulo;
1632: } else if (r_reg<lobound) {
1633: r_reg += modulo;
1634: }
1.1 root 1635: }
1636:
1.1.1.6 root 1637: dsp_core.registers[DSP_REG_R0+numreg] = ((Uint32) r_reg) & BITMASK(16);
1.1 root 1638: }
1639:
1.1.1.2 root 1640: static int dsp_calc_ea(Uint32 ea_mode, Uint32 *dst_addr)
1.1 root 1641: {
1.1.1.2 root 1642: Uint32 value, numreg, curreg;
1.1 root 1643:
1644: value = (ea_mode >> 3) & BITMASK(3);
1645: numreg = ea_mode & BITMASK(3);
1646: switch (value) {
1647: case 0:
1648: /* (Rx)-Nx */
1.1.1.6 root 1649: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1650: dsp_update_rn(numreg, -dsp_core.registers[DSP_REG_N0+numreg]);
1.1 root 1651: break;
1652: case 1:
1653: /* (Rx)+Nx */
1.1.1.6 root 1654: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1655: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1.1 root 1656: break;
1657: case 2:
1658: /* (Rx)- */
1.1.1.6 root 1659: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1660: dsp_update_rn(numreg, -1);
1661: break;
1662: case 3:
1663: /* (Rx)+ */
1.1.1.6 root 1664: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1665: dsp_update_rn(numreg, +1);
1666: break;
1667: case 4:
1668: /* (Rx) */
1.1.1.6 root 1669: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1670: break;
1671: case 5:
1672: /* (Rx+Nx) */
1.1.1.6 root 1673: dsp_core.instr_cycle += 2;
1674: curreg = dsp_core.registers[DSP_REG_R0+numreg];
1675: dsp_update_rn(numreg, dsp_core.registers[DSP_REG_N0+numreg]);
1676: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1677: dsp_core.registers[DSP_REG_R0+numreg] = curreg;
1.1 root 1678: break;
1679: case 6:
1680: /* aa */
1.1.1.6 root 1681: dsp_core.instr_cycle += 2;
1682: *dst_addr = read_memory_p(dsp_core.pc+1);
1.1 root 1683: cur_inst_len++;
1684: if (numreg != 0) {
1685: return 1; /* immediate value */
1686: }
1687: break;
1688: case 7:
1689: /* -(Rx) */
1.1.1.6 root 1690: dsp_core.instr_cycle += 2;
1.1 root 1691: dsp_update_rn(numreg, -1);
1.1.1.6 root 1692: *dst_addr = dsp_core.registers[DSP_REG_R0+numreg];
1.1 root 1693: break;
1694: }
1695: /* address */
1696: return 0;
1697: }
1698:
1699: /**********************************
1700: * Condition code test
1701: **********************************/
1702:
1.1.1.2 root 1703: static int dsp_calc_cc(Uint32 cc_code)
1.1 root 1704: {
1.1.1.4 root 1705: Uint16 value1, value2, value3;
1.1 root 1706:
1.1.1.4 root 1707: switch (cc_code) {
1708: case 0: /* CC (HS) */
1.1.1.6 root 1709: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1.1.1.4 root 1710: return (value1==0);
1711: case 1: /* GE */
1.1.1.6 root 1712: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1713: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1.1.1.4 root 1714: return ((value1 ^ value2) == 0);
1715: case 2: /* NE */
1.1.1.6 root 1716: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_Z);
1.1.1.4 root 1717: return (value1==0);
1718: case 3: /* PL */
1.1.1.6 root 1719: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_N);
1.1.1.4 root 1720: return (value1==0);
1721: case 4: /* NN */
1.1.1.6 root 1722: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1723: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1724: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1.1.1.4 root 1725: return ((value1 | (value2 & value3)) == 0);
1726: case 5: /* EC */
1.1.1.6 root 1727: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_E);
1.1.1.4 root 1728: return (value1==0);
1729: case 6: /* LC */
1.1.1.6 root 1730: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_L);
1.1.1.4 root 1731: return (value1==0);
1732: case 7: /* GT */
1.1.1.6 root 1733: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1734: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1735: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1736: return ((value3 | (value1 ^ value2)) == 0);
1737: case 8: /* CS (LO) */
1.1.1.6 root 1738: value1 = dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_C);
1.1.1.4 root 1739: return (value1==1);
1740: case 9: /* LT */
1.1.1.6 root 1741: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1742: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1.1.1.4 root 1743: return ((value1 ^ value2) == 1);
1744: case 10: /* EQ */
1.1.1.6 root 1745: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1746: return (value1==1);
1747: case 11: /* MI */
1.1.1.6 root 1748: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1.1.1.4 root 1749: return (value1==1);
1750: case 12: /* NR */
1.1.1.6 root 1751: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1752: value2 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_U)) & 1;
1753: value3 = (~(dsp_core.registers[DSP_REG_SR] >> DSP_SR_E)) & 1;
1.1.1.4 root 1754: return ((value1 | (value2 & value3)) == 1);
1755: case 13: /* ES */
1.1.1.6 root 1756: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_E) & 1;
1.1.1.4 root 1757: return (value1==1);
1758: case 14: /* LS */
1.1.1.6 root 1759: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_L) & 1;
1.1.1.4 root 1760: return (value1==1);
1761: case 15: /* LE */
1.1.1.6 root 1762: value1 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_N) & 1;
1763: value2 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_V) & 1;
1764: value3 = (dsp_core.registers[DSP_REG_SR] >> DSP_SR_Z) & 1;
1.1.1.4 root 1765: return ((value3 | (value1 ^ value2)) == 1);
1766: }
1767: return 0;
1.1 root 1768: }
1769:
1770: /**********************************
1771: * Highbyte opcodes dispatchers
1772: **********************************/
1773:
1774: static void opcode8h_0(void)
1775: {
1.1.1.4 root 1776: switch(cur_inst) {
1777: case 0x000000:
1778: dsp_nop();
1.1 root 1779: break;
1.1.1.4 root 1780: case 0x000004:
1781: dsp_rti();
1.1 root 1782: break;
1.1.1.4 root 1783: case 0x000005:
1784: dsp_illegal();
1.1 root 1785: break;
1.1.1.4 root 1786: case 0x000006:
1787: dsp_swi();
1788: break;
1789: case 0x00000c:
1790: dsp_rts();
1791: break;
1792: case 0x000084:
1793: dsp_reset();
1794: break;
1795: case 0x000086:
1796: dsp_wait();
1797: break;
1798: case 0x000087:
1799: dsp_stop();
1800: break;
1801: case 0x00008c:
1802: dsp_enddo();
1.1 root 1803: break;
1804: }
1805: }
1806:
1807: /**********************************
1808: * Non-parallel moves instructions
1809: **********************************/
1810:
1811: static void dsp_undefined(void)
1812: {
1.1.1.6 root 1813: if (isDsp_in_disasm_mode == false) {
1814: cur_inst_len = 0;
1815: fprintf(stderr, "Dsp: 0x%04x: 0x%06x Illegal instruction\n",dsp_core.pc, cur_inst);
1.1.1.7 root 1816: /* Add some artificial CPU cycles to avoid being stuck in an infinite loop */
1.1.1.6 root 1817: dsp_core.instr_cycle += 100;
1818: }
1819: else {
1820: cur_inst_len = 1;
1821: dsp_core.instr_cycle = 0;
1822: }
1.1.1.9 ! root 1823: if (bExceptionDebugging) {
! 1824: DebugUI(REASON_DSP_EXCEPTION);
! 1825: }
1.1 root 1826: }
1827:
1828: static void dsp_andi(void)
1829: {
1.1.1.2 root 1830: Uint32 regnum, value;
1.1 root 1831:
1832: value = (cur_inst >> 8) & BITMASK(8);
1833: regnum = cur_inst & BITMASK(2);
1834: switch(regnum) {
1835: case 0:
1836: /* mr */
1.1.1.6 root 1837: dsp_core.registers[DSP_REG_SR] &= (value<<8)|BITMASK(8);
1.1 root 1838: break;
1839: case 1:
1840: /* ccr */
1.1.1.6 root 1841: dsp_core.registers[DSP_REG_SR] &= (BITMASK(8)<<8)|value;
1.1 root 1842: break;
1843: case 2:
1844: /* omr */
1.1.1.6 root 1845: dsp_core.registers[DSP_REG_OMR] &= value;
1.1 root 1846: break;
1847: }
1848: }
1849:
1.1.1.4 root 1850: static void dsp_bchg_aa(void)
1.1 root 1851: {
1.1.1.4 root 1852: Uint32 memspace, addr, value, newcarry, numbit;
1.1 root 1853:
1854: memspace = (cur_inst>>6) & 1;
1855: value = (cur_inst>>8) & BITMASK(6);
1856: numbit = cur_inst & BITMASK(5);
1857:
1.1.1.4 root 1858: addr = value;
1859: value = read_memory(memspace, addr);
1860: newcarry = (value>>numbit) & 1;
1861: if (newcarry) {
1862: value -= (1<<numbit);
1863: } else {
1864: value += (1<<numbit);
1.1 root 1865: }
1.1.1.4 root 1866: write_memory(memspace, addr, value);
1.1 root 1867:
1868: /* Set carry */
1.1.1.6 root 1869: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1870: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1871:
1.1.1.6 root 1872: dsp_core.instr_cycle += 2;
1.1 root 1873: }
1874:
1.1.1.4 root 1875: static void dsp_bchg_ea(void)
1.1 root 1876: {
1.1.1.4 root 1877: Uint32 memspace, addr, value, newcarry, numbit;
1.1 root 1878:
1879: memspace = (cur_inst>>6) & 1;
1880: value = (cur_inst>>8) & BITMASK(6);
1881: numbit = cur_inst & BITMASK(5);
1882:
1.1.1.4 root 1883: dsp_calc_ea(value, &addr);
1884: value = read_memory(memspace, addr);
1885: newcarry = (value>>numbit) & 1;
1886: if (newcarry) {
1887: value -= (1<<numbit);
1888: } else {
1889: value += (1<<numbit);
1.1 root 1890: }
1.1.1.4 root 1891: write_memory(memspace, addr, value);
1.1 root 1892:
1893: /* Set carry */
1.1.1.6 root 1894: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1895: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1896:
1.1.1.6 root 1897: dsp_core.instr_cycle += 2;
1.1 root 1898: }
1899:
1.1.1.4 root 1900: static void dsp_bchg_pp(void)
1.1 root 1901: {
1.1.1.4 root 1902: Uint32 memspace, addr, value, newcarry, numbit;
1.1 root 1903:
1904: memspace = (cur_inst>>6) & 1;
1905: value = (cur_inst>>8) & BITMASK(6);
1906: numbit = cur_inst & BITMASK(5);
1907:
1.1.1.4 root 1908: addr = 0xffc0 + value;
1909: value = read_memory(memspace, addr);
1910: newcarry = (value>>numbit) & 1;
1911: if (newcarry) {
1912: value -= (1<<numbit);
1913: } else {
1914: value += (1<<numbit);
1.1 root 1915: }
1.1.1.4 root 1916: write_memory(memspace, addr, value);
1.1 root 1917:
1918: /* Set carry */
1.1.1.6 root 1919: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1920: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1921:
1.1.1.6 root 1922: dsp_core.instr_cycle += 2;
1.1 root 1923: }
1924:
1.1.1.4 root 1925: static void dsp_bchg_reg(void)
1.1 root 1926: {
1.1.1.4 root 1927: Uint32 value, numreg, newcarry, numbit;
1.1 root 1928:
1.1.1.4 root 1929: numreg = (cur_inst>>8) & BITMASK(6);
1.1 root 1930: numbit = cur_inst & BITMASK(5);
1931:
1.1.1.4 root 1932: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
1933: dsp_pm_read_accu24(numreg, &value);
1934: } else {
1.1.1.6 root 1935: value = dsp_core.registers[numreg];
1.1 root 1936: }
1937:
1.1.1.4 root 1938: newcarry = (value>>numbit) & 1;
1939: if (newcarry) {
1940: value -= (1<<numbit);
1941: } else {
1942: value += (1<<numbit);
1943: }
1944:
1945: dsp_write_reg(numreg, value);
1946:
1.1 root 1947: /* Set carry */
1.1.1.6 root 1948: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1949: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1950:
1.1.1.6 root 1951: dsp_core.instr_cycle += 2;
1.1 root 1952: }
1953:
1.1.1.4 root 1954: static void dsp_bclr_aa(void)
1.1 root 1955: {
1.1.1.4 root 1956: Uint32 memspace, addr, value, newcarry, numbit;
1957:
1958: memspace = (cur_inst>>6) & 1;
1959: addr = (cur_inst>>8) & BITMASK(6);
1960: numbit = cur_inst & BITMASK(5);
1.1 root 1961:
1.1.1.4 root 1962: value = read_memory(memspace, addr);
1963: newcarry = (value>>numbit) & 1;
1964: value &= 0xffffffff-(1<<numbit);
1965: write_memory(memspace, addr, value);
1.1.1.2 root 1966:
1.1.1.4 root 1967: /* Set carry */
1.1.1.6 root 1968: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1969: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 1970:
1.1.1.6 root 1971: dsp_core.instr_cycle += 2;
1.1.1.4 root 1972: }
1.1 root 1973:
1.1.1.4 root 1974: static void dsp_bclr_ea(void)
1975: {
1976: Uint32 memspace, addr, value, newcarry, numbit;
1977:
1978: memspace = (cur_inst>>6) & 1;
1979: value = (cur_inst>>8) & BITMASK(6);
1980: numbit = cur_inst & BITMASK(5);
1.1 root 1981:
1.1.1.4 root 1982: dsp_calc_ea(value, &addr);
1983: value = read_memory(memspace, addr);
1984: newcarry = (value>>numbit) & 1;
1985: value &= 0xffffffff-(1<<numbit);
1986: write_memory(memspace, addr, value);
1.1.1.2 root 1987:
1.1.1.4 root 1988: /* Set carry */
1.1.1.6 root 1989: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
1990: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 1991:
1.1.1.6 root 1992: dsp_core.instr_cycle += 2;
1.1 root 1993: }
1994:
1.1.1.4 root 1995: static void dsp_bclr_pp(void)
1996: {
1997: Uint32 memspace, addr, value, newcarry, numbit;
1998:
1999: memspace = (cur_inst>>6) & 1;
2000: value = (cur_inst>>8) & BITMASK(6);
2001: numbit = cur_inst & BITMASK(5);
1.1.1.3 root 2002:
1.1.1.4 root 2003: addr = 0xffc0 + value;
2004: value = read_memory(memspace, addr);
2005: newcarry = (value>>numbit) & 1;
2006: value &= 0xffffffff-(1<<numbit);
2007: write_memory(memspace, addr, value);
1.1.1.3 root 2008:
1.1.1.4 root 2009: /* Set carry */
1.1.1.6 root 2010: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2011: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 2012:
1.1.1.6 root 2013: dsp_core.instr_cycle += 2;
1.1.1.4 root 2014: }
1.1 root 2015:
1.1.1.4 root 2016: static void dsp_bclr_reg(void)
2017: {
2018: Uint32 value, numreg, newcarry, numbit;
2019:
2020: numreg = (cur_inst>>8) & BITMASK(6);
2021: numbit = cur_inst & BITMASK(5);
1.1 root 2022:
1.1.1.4 root 2023: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2024: dsp_pm_read_accu24(numreg, &value);
2025: } else {
1.1.1.6 root 2026: value = dsp_core.registers[numreg];
1.1.1.4 root 2027: }
1.1 root 2028:
1.1.1.4 root 2029: newcarry = (value>>numbit) & 1;
2030: value &= 0xffffffff-(1<<numbit);
1.1 root 2031:
1.1.1.4 root 2032: dsp_write_reg(numreg, value);
2033:
2034: /* Set carry */
1.1.1.6 root 2035: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2036: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1 root 2037:
1.1.1.6 root 2038: dsp_core.instr_cycle += 2;
1.1 root 2039: }
2040:
1.1.1.4 root 2041: static void dsp_bset_aa(void)
1.1 root 2042: {
1.1.1.4 root 2043: Uint32 memspace, addr, value, newcarry, numbit;
2044:
2045: memspace = (cur_inst>>6) & 1;
2046: value = (cur_inst>>8) & BITMASK(6);
2047: numbit = cur_inst & BITMASK(5);
1.1 root 2048:
1.1.1.4 root 2049: addr = value;
2050: value = read_memory(memspace, addr);
2051: newcarry = (value>>numbit) & 1;
2052: value |= (1<<numbit);
2053: write_memory(memspace, addr, value);
2054:
2055: /* Set carry */
1.1.1.6 root 2056: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2057: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2058:
1.1.1.6 root 2059: dsp_core.instr_cycle += 2;
1.1.1.4 root 2060: }
2061:
2062: static void dsp_bset_ea(void)
2063: {
2064: Uint32 memspace, addr, value, newcarry, numbit;
2065:
2066: memspace = (cur_inst>>6) & 1;
2067: value = (cur_inst>>8) & BITMASK(6);
2068: numbit = cur_inst & BITMASK(5);
2069:
2070: dsp_calc_ea(value, &addr);
2071: value = read_memory(memspace, addr);
2072: newcarry = (value>>numbit) & 1;
2073: value |= (1<<numbit);
2074: write_memory(memspace, addr, value);
2075:
2076: /* Set carry */
1.1.1.6 root 2077: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2078: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2079:
1.1.1.6 root 2080: dsp_core.instr_cycle += 2;
1.1.1.4 root 2081: }
2082:
2083: static void dsp_bset_pp(void)
2084: {
2085: Uint32 memspace, addr, value, newcarry, numbit;
2086:
2087: memspace = (cur_inst>>6) & 1;
2088: value = (cur_inst>>8) & BITMASK(6);
2089: numbit = cur_inst & BITMASK(5);
2090: addr = 0xffc0 + value;
2091: value = read_memory(memspace, addr);
2092: newcarry = (value>>numbit) & 1;
2093: value |= (1<<numbit);
2094: write_memory(memspace, addr, value);
2095:
2096: /* Set carry */
1.1.1.6 root 2097: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2098: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2099:
1.1.1.6 root 2100: dsp_core.instr_cycle += 2;
1.1.1.4 root 2101: }
2102:
2103: static void dsp_bset_reg(void)
2104: {
2105: Uint32 value, numreg, newcarry, numbit;
2106:
2107: numreg = (cur_inst>>8) & BITMASK(6);
2108: numbit = cur_inst & BITMASK(5);
2109:
2110: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2111: dsp_pm_read_accu24(numreg, &value);
2112: } else {
1.1.1.6 root 2113: value = dsp_core.registers[numreg];
1.1.1.4 root 2114: }
2115:
2116: newcarry = (value>>numbit) & 1;
2117: value |= (1<<numbit);
2118:
2119: dsp_write_reg(numreg, value);
2120:
2121: /* Set carry */
1.1.1.6 root 2122: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2123: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2124:
1.1.1.6 root 2125: dsp_core.instr_cycle += 2;
1.1.1.4 root 2126: }
2127:
2128: static void dsp_btst_aa(void)
2129: {
2130: Uint32 memspace, addr, value, newcarry, numbit;
2131:
2132: memspace = (cur_inst>>6) & 1;
2133: value = (cur_inst>>8) & BITMASK(6);
2134: numbit = cur_inst & BITMASK(5);
2135:
2136: addr = value;
2137: value = read_memory(memspace, addr);
2138: newcarry = (value>>numbit) & 1;
2139:
2140: /* Set carry */
1.1.1.6 root 2141: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2142: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2143:
1.1.1.6 root 2144: dsp_core.instr_cycle += 2;
1.1.1.4 root 2145: }
2146:
2147: static void dsp_btst_ea(void)
2148: {
2149: Uint32 memspace, addr, value, newcarry, numbit;
2150:
2151: memspace = (cur_inst>>6) & 1;
2152: value = (cur_inst>>8) & BITMASK(6);
2153: numbit = cur_inst & BITMASK(5);
2154:
2155: dsp_calc_ea(value, &addr);
2156: value = read_memory(memspace, addr);
2157: newcarry = (value>>numbit) & 1;
2158:
2159: /* Set carry */
1.1.1.6 root 2160: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2161: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2162:
1.1.1.6 root 2163: dsp_core.instr_cycle += 2;
1.1.1.4 root 2164: }
2165:
2166: static void dsp_btst_pp(void)
2167: {
2168: Uint32 memspace, addr, value, newcarry, numbit;
2169:
2170: memspace = (cur_inst>>6) & 1;
2171: value = (cur_inst>>8) & BITMASK(6);
2172: numbit = cur_inst & BITMASK(5);
2173:
2174: addr = 0xffc0 + value;
2175: value = read_memory(memspace, addr);
2176: newcarry = (value>>numbit) & 1;
2177:
2178: /* Set carry */
1.1.1.6 root 2179: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2180: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2181:
1.1.1.6 root 2182: dsp_core.instr_cycle += 2;
1.1.1.4 root 2183: }
2184:
2185: static void dsp_btst_reg(void)
2186: {
2187: Uint32 value, numreg, newcarry, numbit;
2188:
2189: numreg = (cur_inst>>8) & BITMASK(6);
2190: numbit = cur_inst & BITMASK(5);
2191:
2192: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2193: dsp_pm_read_accu24(numreg, &value);
2194: } else {
1.1.1.6 root 2195: value = dsp_core.registers[numreg];
1.1.1.4 root 2196: }
2197:
2198: newcarry = (value>>numbit) & 1;
2199:
2200: /* Set carry */
1.1.1.6 root 2201: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_C);
2202: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_C;
1.1.1.4 root 2203:
1.1.1.6 root 2204: dsp_core.instr_cycle += 2;
1.1.1.4 root 2205: }
2206:
2207: static void dsp_div(void)
2208: {
2209: Uint32 srcreg, destreg, source[3], dest[3];
2210: Uint16 newsr;
2211:
2212: srcreg = DSP_REG_NULL;
2213: switch((cur_inst>>4) & BITMASK(2)) {
2214: case 0: srcreg = DSP_REG_X0; break;
2215: case 1: srcreg = DSP_REG_Y0; break;
2216: case 2: srcreg = DSP_REG_X1; break;
2217: case 3: srcreg = DSP_REG_Y1; break;
2218: }
1.1.1.7 root 2219: source[2] = 0;
2220: source[1] = dsp_core.registers[srcreg];
2221: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.4 root 2222:
1.1.1.7 root 2223: destreg = DSP_REG_A + ((cur_inst>>3) & 1);
2224: if (destreg == DSP_REG_A) {
2225: dest[0] = dsp_core.registers[DSP_REG_A2];
2226: dest[1] = dsp_core.registers[DSP_REG_A1];
2227: dest[2] = dsp_core.registers[DSP_REG_A0];
2228: }
2229: else {
2230: dest[0] = dsp_core.registers[DSP_REG_B2];
2231: dest[1] = dsp_core.registers[DSP_REG_B1];
2232: dest[2] = dsp_core.registers[DSP_REG_B0];
2233: }
1.1.1.4 root 2234:
2235: if (((dest[0]>>7) & 1) ^ ((source[1]>>23) & 1)) {
2236: /* D += S */
2237: newsr = dsp_asl56(dest);
2238: dsp_add56(source, dest);
2239: } else {
2240: /* D -= S */
2241: newsr = dsp_asl56(dest);
2242: dsp_sub56(source, dest);
2243: }
2244:
1.1.1.6 root 2245: dest[2] |= (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1.1.4 root 2246:
1.1.1.7 root 2247: if (destreg == DSP_REG_A) {
2248: dsp_core.registers[DSP_REG_A2] = dest[0];
2249: dsp_core.registers[DSP_REG_A1] = dest[1];
2250: dsp_core.registers[DSP_REG_A0] = dest[2];
2251: }
2252: else {
2253: dsp_core.registers[DSP_REG_B2] = dest[0];
2254: dsp_core.registers[DSP_REG_B1] = dest[1];
2255: dsp_core.registers[DSP_REG_B0] = dest[2];
2256: }
2257:
1.1.1.6 root 2258: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
2259: dsp_core.registers[DSP_REG_SR] |= (1-((dest[0]>>7) & 1))<<DSP_SR_C;
2260: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_L);
2261: dsp_core.registers[DSP_REG_SR] |= newsr & (1<<DSP_SR_V);
1.1.1.4 root 2262: }
2263:
2264: /*
2265: DO instruction parameter encoding
2266:
2267: xxxxxxxx 00xxxxxx 0xxxxxxx aa
2268: xxxxxxxx 01xxxxxx 0xxxxxxx ea
2269: xxxxxxxx YYxxxxxx 1xxxxxxx imm
2270: xxxxxxxx 11xxxxxx 0xxxxxxx reg
2271: */
2272:
2273: static void dsp_do_aa(void)
2274: {
2275: Uint32 memspace, addr;
2276:
2277: /* x:aa */
2278: /* y:aa */
2279:
1.1.1.6 root 2280: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2281: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2282: cur_inst_len++;
1.1.1.6 root 2283: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2284: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1 root 2285:
2286: memspace = (cur_inst>>6) & 1;
2287: addr = (cur_inst>>8) & BITMASK(6);
1.1.1.6 root 2288: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
1.1.1.4 root 2289:
1.1.1.6 root 2290: dsp_core.instr_cycle += 4;
1.1 root 2291: }
2292:
1.1.1.3 root 2293: static void dsp_do_imm(void)
1.1 root 2294: {
2295: /* #xx */
1.1.1.3 root 2296:
1.1.1.6 root 2297: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2298: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2299: cur_inst_len++;
1.1.1.6 root 2300: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2301: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2302:
1.1.1.6 root 2303: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
1.1.1.3 root 2304: + ((cur_inst & BITMASK(4))<<8);
1.1.1.4 root 2305:
1.1.1.6 root 2306: dsp_core.instr_cycle += 4;
1.1 root 2307: }
2308:
1.1.1.3 root 2309: static void dsp_do_ea(void)
1.1 root 2310: {
1.1.1.2 root 2311: Uint32 memspace, ea_mode, addr;
1.1 root 2312:
2313: /* x:ea */
2314: /* y:ea */
2315:
1.1.1.6 root 2316: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2317: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2318: cur_inst_len++;
1.1.1.6 root 2319: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2320: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2321:
1.1 root 2322: memspace = (cur_inst>>6) & 1;
2323: ea_mode = (cur_inst>>8) & BITMASK(6);
2324: dsp_calc_ea(ea_mode, &addr);
1.1.1.6 root 2325: dsp_core.registers[DSP_REG_LC] = read_memory(memspace, addr) & BITMASK(16);
1.1.1.4 root 2326:
1.1.1.6 root 2327: dsp_core.instr_cycle += 4;
1.1 root 2328: }
2329:
1.1.1.3 root 2330: static void dsp_do_reg(void)
1.1 root 2331: {
1.1.1.2 root 2332: Uint32 numreg;
1.1 root 2333:
2334: /* S */
2335:
1.1.1.6 root 2336: dsp_stack_push(dsp_core.registers[DSP_REG_LA], dsp_core.registers[DSP_REG_LC], 0);
2337: dsp_core.registers[DSP_REG_LA] = read_memory_p(dsp_core.pc+1) & BITMASK(16);
1.1.1.4 root 2338: cur_inst_len++;
2339:
1.1 root 2340: numreg = (cur_inst>>8) & BITMASK(6);
2341: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.6 root 2342: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
1.1 root 2343: } else {
1.1.1.6 root 2344: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
1.1 root 2345: }
1.1.1.6 root 2346: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.4 root 2347:
1.1.1.6 root 2348: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2349: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_LF);
1.1.1.4 root 2350:
1.1.1.6 root 2351: dsp_core.instr_cycle += 4;
1.1 root 2352: }
2353:
2354: static void dsp_enddo(void)
2355: {
1.1.1.4 root 2356: Uint32 saved_pc, saved_sr;
1.1 root 2357:
1.1.1.4 root 2358: dsp_stack_pop(&saved_pc, &saved_sr);
1.1.1.6 root 2359: dsp_core.registers[DSP_REG_SR] &= 0x7f;
2360: dsp_core.registers[DSP_REG_SR] |= saved_sr & (1<<DSP_SR_LF);
2361: dsp_stack_pop(&dsp_core.registers[DSP_REG_LA], &dsp_core.registers[DSP_REG_LC]);
1.1 root 2362: }
2363:
2364: static void dsp_illegal(void)
2365: {
2366: /* Raise interrupt p:0x003e */
1.1.1.5 root 2367: dsp_add_interrupt(DSP_INTER_ILLEGAL);
1.1.1.9 ! root 2368: if (bExceptionDebugging) {
! 2369: DebugUI(REASON_DSP_EXCEPTION);
! 2370: }
1.1 root 2371: }
2372:
1.1.1.4 root 2373: static void dsp_jcc_imm(void)
1.1 root 2374: {
1.1.1.4 root 2375: Uint32 cc_code, newpc;
1.1 root 2376:
1.1.1.4 root 2377: newpc = cur_inst & BITMASK(12);
2378: cc_code=(cur_inst>>12) & BITMASK(4);
2379: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2380: dsp_core.pc = newpc;
1.1.1.4 root 2381: cur_inst_len = 0;
2382: }
2383:
1.1.1.6 root 2384: dsp_core.instr_cycle += 2;
1.1.1.4 root 2385: }
2386:
2387: static void dsp_jcc_ea(void)
2388: {
2389: Uint32 newpc, cc_code;
2390:
2391: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2392: cc_code=cur_inst & BITMASK(4);
1.1 root 2393:
2394: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2395: dsp_core.pc = newpc;
1.1 root 2396: cur_inst_len = 0;
2397: }
1.1.1.4 root 2398:
1.1.1.6 root 2399: dsp_core.instr_cycle += 2;
1.1 root 2400: }
2401:
1.1.1.4 root 2402: static void dsp_jclr_aa(void)
1.1 root 2403: {
1.1.1.4 root 2404: Uint32 memspace, addr, value, numbit, newaddr;
1.1 root 2405:
2406: memspace = (cur_inst>>6) & 1;
1.1.1.4 root 2407: addr = (cur_inst>>8) & BITMASK(6);
1.1 root 2408: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2409: value = read_memory(memspace, addr);
1.1.1.6 root 2410: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2411:
1.1.1.6 root 2412: dsp_core.instr_cycle += 4;
1.1 root 2413:
1.1.1.4 root 2414: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2415: dsp_core.pc = newaddr;
1.1.1.4 root 2416: cur_inst_len = 0;
2417: return;
2418: }
1.1.1.2 root 2419: ++cur_inst_len;
1.1.1.4 root 2420: }
2421:
2422: static void dsp_jclr_ea(void)
2423: {
2424: Uint32 memspace, addr, value, numbit, newaddr;
2425:
2426: memspace = (cur_inst>>6) & 1;
2427: value = (cur_inst>>8) & BITMASK(6);
2428: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2429: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2430:
2431: dsp_calc_ea(value, &addr);
2432: value = read_memory(memspace, addr);
2433:
1.1.1.6 root 2434: dsp_core.instr_cycle += 4;
1.1 root 2435:
2436: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2437: dsp_core.pc = newaddr;
1.1.1.4 root 2438: cur_inst_len = 0;
2439: return;
2440: }
2441: ++cur_inst_len;
2442: }
1.1 root 2443:
1.1.1.4 root 2444: static void dsp_jclr_pp(void)
2445: {
2446: Uint32 memspace, addr, value, numbit, newaddr;
2447:
2448: memspace = (cur_inst>>6) & 1;
2449: value = (cur_inst>>8) & BITMASK(6);
2450: numbit = cur_inst & BITMASK(5);
2451: addr = 0xffc0 + value;
2452: value = read_memory(memspace, addr);
1.1.1.6 root 2453: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2454:
1.1.1.6 root 2455: dsp_core.instr_cycle += 4;
1.1 root 2456:
1.1.1.4 root 2457: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2458: dsp_core.pc = newaddr;
1.1.1.4 root 2459: cur_inst_len = 0;
2460: return;
2461: }
2462: ++cur_inst_len;
2463: }
1.1.1.2 root 2464:
1.1.1.4 root 2465: static void dsp_jclr_reg(void)
2466: {
2467: Uint32 value, numreg, numbit, newaddr;
2468:
2469: numreg = (cur_inst>>8) & BITMASK(6);
2470: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2471: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2472:
1.1.1.4 root 2473: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2474: dsp_pm_read_accu24(numreg, &value);
2475: } else {
1.1.1.6 root 2476: value = dsp_core.registers[numreg];
1.1.1.4 root 2477: }
1.1 root 2478:
1.1.1.6 root 2479: dsp_core.instr_cycle += 4;
1.1.1.4 root 2480:
2481: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2482: dsp_core.pc = newaddr;
1.1 root 2483: cur_inst_len = 0;
2484: return;
2485: }
1.1.1.4 root 2486: ++cur_inst_len;
1.1 root 2487: }
2488:
1.1.1.4 root 2489: static void dsp_jmp_ea(void)
1.1 root 2490: {
1.1.1.2 root 2491: Uint32 newpc;
1.1 root 2492:
1.1.1.4 root 2493: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &newpc);
1.1 root 2494: cur_inst_len = 0;
1.1.1.6 root 2495: dsp_core.pc = newpc;
1.1 root 2496:
1.1.1.6 root 2497: dsp_core.instr_cycle += 2;
1.1.1.4 root 2498: }
2499:
2500: static void dsp_jmp_imm(void)
2501: {
2502: Uint32 newpc;
1.1 root 2503:
1.1.1.4 root 2504: newpc = cur_inst & BITMASK(12);
2505: cur_inst_len = 0;
1.1.1.6 root 2506: dsp_core.pc = newpc;
1.1.1.4 root 2507:
1.1.1.6 root 2508: dsp_core.instr_cycle += 2;
1.1 root 2509: }
2510:
1.1.1.4 root 2511: static void dsp_jscc_ea(void)
1.1 root 2512: {
1.1.1.2 root 2513: Uint32 newpc, cc_code;
1.1 root 2514:
1.1.1.4 root 2515: dsp_calc_ea((cur_inst >>8) & BITMASK(6), &newpc);
2516: cc_code=cur_inst & BITMASK(4);
2517:
2518: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2519: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2520: dsp_core.pc = newpc;
1.1.1.4 root 2521: cur_inst_len = 0;
2522: }
2523:
1.1.1.6 root 2524: dsp_core.instr_cycle += 2;
1.1.1.4 root 2525: }
1.1 root 2526:
1.1.1.4 root 2527: static void dsp_jscc_imm(void)
2528: {
2529: Uint32 cc_code, newpc;
2530:
2531: newpc = cur_inst & BITMASK(12);
2532: cc_code=(cur_inst>>12) & BITMASK(4);
1.1 root 2533: if (dsp_calc_cc(cc_code)) {
1.1.1.6 root 2534: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
2535: dsp_core.pc = newpc;
1.1.1.4 root 2536: cur_inst_len = 0;
2537: }
2538:
1.1.1.6 root 2539: dsp_core.instr_cycle += 2;
1.1.1.4 root 2540: }
1.1 root 2541:
1.1.1.4 root 2542: static void dsp_jsclr_aa(void)
2543: {
2544: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2545:
2546: memspace = (cur_inst>>6) & 1;
2547: addr = (cur_inst>>8) & BITMASK(6);
2548: numbit = cur_inst & BITMASK(5);
2549: value = read_memory(memspace, addr);
1.1.1.6 root 2550: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2551:
1.1.1.6 root 2552: dsp_core.instr_cycle += 4;
1.1.1.4 root 2553:
2554: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2555: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2556: newpc = newaddr;
1.1.1.6 root 2557: dsp_core.pc = newpc;
1.1 root 2558: cur_inst_len = 0;
1.1.1.4 root 2559: return;
1.1 root 2560: }
1.1.1.4 root 2561: ++cur_inst_len;
1.1 root 2562: }
2563:
1.1.1.4 root 2564: static void dsp_jsclr_ea(void)
1.1 root 2565: {
1.1.1.4 root 2566: Uint32 memspace, addr, value, newpc, numbit, newaddr;
1.1 root 2567:
2568: memspace = (cur_inst>>6) & 1;
2569: value = (cur_inst>>8) & BITMASK(6);
2570: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2571: dsp_calc_ea(value, &addr);
2572: value = read_memory(memspace, addr);
1.1.1.6 root 2573: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2574:
1.1.1.6 root 2575: dsp_core.instr_cycle += 4;
1.1.1.4 root 2576:
2577: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2578: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2579: newpc = newaddr;
1.1.1.6 root 2580: dsp_core.pc = newpc;
1.1.1.4 root 2581: cur_inst_len = 0;
2582: return;
2583: }
1.1.1.2 root 2584: ++cur_inst_len;
1.1.1.4 root 2585: }
2586:
2587: static void dsp_jsclr_pp(void)
2588: {
2589: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2590:
2591: memspace = (cur_inst>>6) & 1;
2592: value = (cur_inst>>8) & BITMASK(6);
2593: numbit = cur_inst & BITMASK(5);
2594: addr = 0xffc0 + value;
2595: value = read_memory(memspace, addr);
1.1.1.6 root 2596: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2597:
1.1.1.6 root 2598: dsp_core.instr_cycle += 4;
1.1.1.4 root 2599:
1.1 root 2600: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2601: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2602: newpc = newaddr;
1.1.1.6 root 2603: dsp_core.pc = newpc;
1.1.1.4 root 2604: cur_inst_len = 0;
2605: return;
2606: }
2607: ++cur_inst_len;
2608: }
2609:
2610: static void dsp_jsclr_reg(void)
2611: {
2612: Uint32 value, numreg, newpc, numbit, newaddr;
2613:
2614: numreg = (cur_inst>>8) & BITMASK(6);
2615: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2616: newaddr = read_memory_p(dsp_core.pc+1);
1.1 root 2617:
1.1.1.4 root 2618: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2619: dsp_pm_read_accu24(numreg, &value);
2620: } else {
1.1.1.6 root 2621: value = dsp_core.registers[numreg];
1.1.1.4 root 2622: }
2623:
1.1.1.6 root 2624: dsp_core.instr_cycle += 4;
1.1.1.4 root 2625:
2626: if ((value & (1<<numbit))==0) {
1.1.1.6 root 2627: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2628: newpc = newaddr;
1.1.1.6 root 2629: dsp_core.pc = newpc;
1.1 root 2630: cur_inst_len = 0;
1.1.1.4 root 2631: return;
1.1 root 2632: }
1.1.1.4 root 2633: ++cur_inst_len;
1.1 root 2634: }
2635:
1.1.1.4 root 2636: static void dsp_jset_aa(void)
1.1 root 2637: {
1.1.1.4 root 2638: Uint32 memspace, addr, value, numbit, newpc, newaddr;
2639:
2640: memspace = (cur_inst>>6) & 1;
2641: addr = (cur_inst>>8) & BITMASK(6);
2642: numbit = cur_inst & BITMASK(5);
2643: value = read_memory(memspace, addr);
1.1.1.6 root 2644: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2645:
1.1.1.6 root 2646: dsp_core.instr_cycle += 4;
1.1.1.4 root 2647:
2648: if (value & (1<<numbit)) {
2649: newpc = newaddr;
1.1.1.6 root 2650: dsp_core.pc = newpc;
1.1.1.4 root 2651: cur_inst_len=0;
2652: return;
2653: }
2654: ++cur_inst_len;
2655: }
2656:
2657: static void dsp_jset_ea(void)
2658: {
2659: Uint32 memspace, addr, value, numbit, newpc, newaddr;
1.1 root 2660:
2661: memspace = (cur_inst>>6) & 1;
2662: value = (cur_inst>>8) & BITMASK(6);
2663: numbit = cur_inst & BITMASK(5);
1.1.1.4 root 2664: dsp_calc_ea(value, &addr);
2665: value = read_memory(memspace, addr);
1.1.1.6 root 2666: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2667:
1.1.1.6 root 2668: dsp_core.instr_cycle += 4;
1.1.1.7 root 2669:
1.1.1.4 root 2670: if (value & (1<<numbit)) {
2671: newpc = newaddr;
1.1.1.6 root 2672: dsp_core.pc = newpc;
1.1.1.4 root 2673: cur_inst_len=0;
2674: return;
2675: }
2676: ++cur_inst_len;
2677: }
1.1 root 2678:
1.1.1.4 root 2679: static void dsp_jset_pp(void)
2680: {
2681: Uint32 memspace, addr, value, numbit, newpc, newaddr;
2682:
2683: memspace = (cur_inst>>6) & 1;
2684: value = (cur_inst>>8) & BITMASK(6);
2685: numbit = cur_inst & BITMASK(5);
2686: addr = 0xffc0 + value;
2687: value = read_memory(memspace, addr);
1.1.1.6 root 2688: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2689:
1.1.1.6 root 2690: dsp_core.instr_cycle += 4;
1.1.1.4 root 2691:
2692: if (value & (1<<numbit)) {
2693: newpc = newaddr;
1.1.1.6 root 2694: dsp_core.pc = newpc;
1.1.1.4 root 2695: cur_inst_len=0;
2696: return;
2697: }
2698: ++cur_inst_len;
2699: }
2700:
2701: static void dsp_jset_reg(void)
2702: {
2703: Uint32 value, numreg, numbit, newpc, newaddr;
2704:
2705: numreg = (cur_inst>>8) & BITMASK(6);
2706: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2707: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2708:
2709: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2710: dsp_pm_read_accu24(numreg, &value);
2711: } else {
1.1.1.6 root 2712: value = dsp_core.registers[numreg];
1.1.1.4 root 2713: }
2714:
1.1.1.6 root 2715: dsp_core.instr_cycle += 4;
1.1.1.4 root 2716:
2717: if (value & (1<<numbit)) {
2718: newpc = newaddr;
1.1.1.6 root 2719: dsp_core.pc = newpc;
1.1.1.4 root 2720: cur_inst_len=0;
2721: return;
2722: }
2723: ++cur_inst_len;
2724: }
2725:
2726: static void dsp_jsr_imm(void)
2727: {
2728: Uint32 newpc;
2729:
2730: newpc = cur_inst & BITMASK(12);
2731:
1.1.1.6 root 2732: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2733: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2734: }
2735: else {
1.1.1.6 root 2736: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1.1.1.4 root 2737: }
2738:
1.1.1.6 root 2739: dsp_core.pc = newpc;
1.1.1.4 root 2740: cur_inst_len = 0;
2741:
1.1.1.6 root 2742: dsp_core.instr_cycle += 2;
1.1.1.4 root 2743: }
2744:
2745: static void dsp_jsr_ea(void)
2746: {
2747: Uint32 newpc;
2748:
2749: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&newpc);
2750:
1.1.1.6 root 2751: if (dsp_core.interrupt_state != DSP_INTERRUPT_LONG){
2752: dsp_stack_push(dsp_core.pc+cur_inst_len, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2753: }
2754: else {
1.1.1.6 root 2755: dsp_core.interrupt_state = DSP_INTERRUPT_DISABLED;
1.1.1.4 root 2756: }
2757:
1.1.1.6 root 2758: dsp_core.pc = newpc;
1.1.1.4 root 2759: cur_inst_len = 0;
2760:
1.1.1.6 root 2761: dsp_core.instr_cycle += 2;
1.1.1.4 root 2762: }
2763:
2764: static void dsp_jsset_aa(void)
2765: {
2766: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2767:
2768: memspace = (cur_inst>>6) & 1;
2769: addr = (cur_inst>>8) & BITMASK(6);
2770: numbit = cur_inst & BITMASK(5);
2771: value = read_memory(memspace, addr);
1.1.1.6 root 2772: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2773:
1.1.1.6 root 2774: dsp_core.instr_cycle += 4;
1.1.1.4 root 2775:
2776: if (value & (1<<numbit)) {
1.1.1.6 root 2777: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2778: newpc = newaddr;
1.1.1.6 root 2779: dsp_core.pc = newpc;
1.1.1.4 root 2780: cur_inst_len = 0;
2781: return;
2782: }
2783: ++cur_inst_len;
2784: }
2785:
2786: static void dsp_jsset_ea(void)
2787: {
2788: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2789:
2790: memspace = (cur_inst>>6) & 1;
2791: value = (cur_inst>>8) & BITMASK(6);
2792: numbit = cur_inst & BITMASK(5);
2793: dsp_calc_ea(value, &addr);
2794: value = read_memory(memspace, addr);
1.1.1.6 root 2795: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2796:
1.1.1.6 root 2797: dsp_core.instr_cycle += 4;
1.1 root 2798:
2799: if (value & (1<<numbit)) {
1.1.1.6 root 2800: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2801: newpc = newaddr;
1.1.1.6 root 2802: dsp_core.pc = newpc;
1.1.1.4 root 2803: cur_inst_len = 0;
2804: return;
1.1 root 2805: }
1.1.1.4 root 2806: ++cur_inst_len;
1.1 root 2807: }
2808:
1.1.1.4 root 2809: static void dsp_jsset_pp(void)
1.1 root 2810: {
1.1.1.4 root 2811: Uint32 memspace, addr, value, newpc, numbit, newaddr;
2812:
2813: memspace = (cur_inst>>6) & 1;
2814: value = (cur_inst>>8) & BITMASK(6);
2815: numbit = cur_inst & BITMASK(5);
2816: addr = 0xffc0 + value;
2817: value = read_memory(memspace, addr);
1.1.1.6 root 2818: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2819:
1.1.1.6 root 2820: dsp_core.instr_cycle += 4;
1.1 root 2821:
1.1.1.4 root 2822: if (value & (1<<numbit)) {
1.1.1.6 root 2823: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2824: newpc = newaddr;
1.1.1.6 root 2825: dsp_core.pc = newpc;
1.1.1.4 root 2826: cur_inst_len = 0;
2827: return;
2828: }
2829: ++cur_inst_len;
1.1 root 2830: }
2831:
1.1.1.4 root 2832: static void dsp_jsset_reg(void)
1.1 root 2833: {
1.1.1.4 root 2834: Uint32 value, numreg, newpc, numbit, newaddr;
1.1 root 2835:
1.1.1.4 root 2836: numreg = (cur_inst>>8) & BITMASK(6);
1.1 root 2837: numbit = cur_inst & BITMASK(5);
1.1.1.6 root 2838: newaddr = read_memory_p(dsp_core.pc+1);
1.1.1.4 root 2839:
2840: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B)) {
2841: dsp_pm_read_accu24(numreg, &value);
2842: } else {
1.1.1.6 root 2843: value = dsp_core.registers[numreg];
1.1.1.4 root 2844: }
1.1 root 2845:
1.1.1.6 root 2846: dsp_core.instr_cycle += 4;
1.1 root 2847:
2848: if (value & (1<<numbit)) {
1.1.1.6 root 2849: dsp_stack_push(dsp_core.pc+2, dsp_core.registers[DSP_REG_SR], 0);
1.1.1.4 root 2850: newpc = newaddr;
1.1.1.6 root 2851: dsp_core.pc = newpc;
1.1 root 2852: cur_inst_len = 0;
1.1.1.4 root 2853: return;
1.1 root 2854: }
1.1.1.4 root 2855: ++cur_inst_len;
1.1 root 2856: }
2857:
2858: static void dsp_lua(void)
2859: {
1.1.1.2 root 2860: Uint32 value, srcreg, dstreg, srcsave, srcnew;
2861:
1.1 root 2862: srcreg = (cur_inst>>8) & BITMASK(3);
1.1.1.2 root 2863:
1.1.1.6 root 2864: srcsave = dsp_core.registers[DSP_REG_R0+srcreg];
1.1.1.2 root 2865: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &value);
1.1.1.6 root 2866: srcnew = dsp_core.registers[DSP_REG_R0+srcreg];
2867: dsp_core.registers[DSP_REG_R0+srcreg] = srcsave;
1.1.1.2 root 2868:
1.1 root 2869: dstreg = cur_inst & BITMASK(3);
2870:
2871: if (cur_inst & (1<<3)) {
1.1.1.6 root 2872: dsp_core.registers[DSP_REG_N0+dstreg] = srcnew;
1.1 root 2873: } else {
1.1.1.6 root 2874: dsp_core.registers[DSP_REG_R0+dstreg] = srcnew;
1.1 root 2875: }
2876:
1.1.1.6 root 2877: dsp_core.instr_cycle += 2;
1.1 root 2878: }
2879:
1.1.1.3 root 2880: static void dsp_movec_reg(void)
1.1 root 2881: {
1.1.1.4 root 2882: Uint32 numreg1, numreg2, value, dummy;
1.1 root 2883:
2884: /* S1,D2 */
2885: /* S2,D1 */
2886:
2887: numreg2 = (cur_inst>>8) & BITMASK(6);
1.1.1.4 root 2888: numreg1 = cur_inst & BITMASK(6);
1.1 root 2889:
2890: if (cur_inst & (1<<15)) {
2891: /* Write D1 */
2892:
2893: if ((numreg2 == DSP_REG_A) || (numreg2 == DSP_REG_B)) {
1.1.1.4 root 2894: dsp_pm_read_accu24(numreg2, &value);
1.1 root 2895: } else {
1.1.1.6 root 2896: value = dsp_core.registers[numreg2];
1.1 root 2897: }
1.1.1.4 root 2898: value &= BITMASK(registers_mask[numreg1]);
2899: dsp_write_reg(numreg1, value);
1.1 root 2900: } else {
2901: /* Read S1 */
1.1.1.4 root 2902: if (numreg1 == DSP_REG_SSH) {
2903: dsp_stack_pop(&value, &dummy);
2904: }
2905: else {
1.1.1.6 root 2906: value = dsp_core.registers[numreg1];
1.1.1.4 root 2907: }
1.1 root 2908:
1.1.1.7 root 2909: if (numreg2 == DSP_REG_A) {
2910: dsp_core.registers[DSP_REG_A0] = 0;
2911: dsp_core.registers[DSP_REG_A1] = value & BITMASK(24);
2912: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
2913: }
2914: else if (numreg2 == DSP_REG_B) {
2915: dsp_core.registers[DSP_REG_B0] = 0;
2916: dsp_core.registers[DSP_REG_B1] = value & BITMASK(24);
2917: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
2918: }
2919: else {
1.1.1.6 root 2920: dsp_core.registers[numreg2] = value & BITMASK(registers_mask[numreg2]);
1.1 root 2921: }
2922: }
2923: }
2924:
1.1.1.3 root 2925: static void dsp_movec_aa(void)
1.1 root 2926: {
1.1.1.4 root 2927: Uint32 numreg, addr, memspace, value, dummy;
1.1 root 2928:
2929: /* x:aa,D1 */
2930: /* S1,x:aa */
2931: /* y:aa,D1 */
2932: /* S1,y:aa */
2933:
1.1.1.4 root 2934: numreg = cur_inst & BITMASK(6);
1.1 root 2935: addr = (cur_inst>>8) & BITMASK(6);
2936: memspace = (cur_inst>>6) & 1;
2937:
2938: if (cur_inst & (1<<15)) {
2939: /* Write D1 */
1.1.1.4 root 2940: value = read_memory(memspace, addr);
2941: value &= BITMASK(registers_mask[numreg]);
2942: dsp_write_reg(numreg, value);
1.1 root 2943: } else {
2944: /* Read S1 */
1.1.1.4 root 2945: if (numreg == DSP_REG_SSH) {
2946: dsp_stack_pop(&value, &dummy);
2947: }
2948: else {
1.1.1.6 root 2949: value = dsp_core.registers[numreg];
1.1.1.4 root 2950: }
2951: write_memory(memspace, addr, value);
1.1 root 2952: }
2953: }
2954:
1.1.1.3 root 2955: static void dsp_movec_imm(void)
1.1 root 2956: {
1.1.1.4 root 2957: Uint32 numreg, value;
1.1 root 2958:
2959: /* #xx,D1 */
1.1.1.4 root 2960: numreg = cur_inst & BITMASK(6);
2961: value = (cur_inst>>8) & BITMASK(8);
2962: value &= BITMASK(registers_mask[numreg]);
2963: dsp_write_reg(numreg, value);
1.1 root 2964: }
2965:
1.1.1.3 root 2966: static void dsp_movec_ea(void)
1.1 root 2967: {
1.1.1.4 root 2968: Uint32 numreg, addr, memspace, ea_mode, value, dummy;
1.1 root 2969: int retour;
2970:
2971: /* x:ea,D1 */
2972: /* S1,x:ea */
2973: /* y:ea,D1 */
2974: /* S1,y:ea */
2975: /* #xxxx,D1 */
2976:
1.1.1.4 root 2977: numreg = cur_inst & BITMASK(6);
1.1 root 2978: ea_mode = (cur_inst>>8) & BITMASK(6);
2979: memspace = (cur_inst>>6) & 1;
2980:
2981: if (cur_inst & (1<<15)) {
2982: /* Write D1 */
2983: retour = dsp_calc_ea(ea_mode, &addr);
2984: if (retour) {
1.1.1.4 root 2985: value = addr;
1.1 root 2986: } else {
1.1.1.4 root 2987: value = read_memory(memspace, addr);
1.1 root 2988: }
1.1.1.4 root 2989: value &= BITMASK(registers_mask[numreg]);
2990: dsp_write_reg(numreg, value);
1.1 root 2991: } else {
2992: /* Read S1 */
1.1.1.4 root 2993: dsp_calc_ea(ea_mode, &addr);
2994: if (numreg == DSP_REG_SSH) {
2995: dsp_stack_pop(&value, &dummy);
2996: }
2997: else {
1.1.1.6 root 2998: value = dsp_core.registers[numreg];
1.1.1.4 root 2999: }
3000: write_memory(memspace, addr, value);
1.1 root 3001: }
3002: }
3003:
1.1.1.4 root 3004: static void dsp_movem_aa(void)
1.1 root 3005: {
1.1.1.4 root 3006: Uint32 numreg, addr, value, dummy;
1.1 root 3007:
3008: numreg = cur_inst & BITMASK(6);
1.1.1.4 root 3009: addr = (cur_inst>>8) & BITMASK(6);
1.1 root 3010:
1.1.1.4 root 3011: if (cur_inst & (1<<15)) {
3012: /* Write D */
3013: value = read_memory_p(addr);
3014: value &= BITMASK(registers_mask[numreg]);
3015: dsp_write_reg(numreg, value);
1.1 root 3016: } else {
1.1.1.4 root 3017: /* Read S */
3018: if (numreg == DSP_REG_SSH) {
3019: dsp_stack_pop(&value, &dummy);
3020: }
3021: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
3022: dsp_pm_read_accu24(numreg, &value);
3023: }
3024: else {
1.1.1.6 root 3025: value = dsp_core.registers[numreg];
1.1.1.4 root 3026: }
3027: write_memory(DSP_SPACE_P, addr, value);
3028: }
1.1 root 3029:
1.1.1.6 root 3030: dsp_core.instr_cycle += 4;
1.1.1.4 root 3031: }
3032:
3033: static void dsp_movem_ea(void)
3034: {
3035: Uint32 numreg, addr, ea_mode, value, dummy;
3036:
3037: numreg = cur_inst & BITMASK(6);
3038: ea_mode = (cur_inst>>8) & BITMASK(6);
3039: dsp_calc_ea(ea_mode, &addr);
1.1 root 3040:
3041: if (cur_inst & (1<<15)) {
3042: /* Write D */
1.1.1.4 root 3043: value = read_memory_p(addr);
3044: value &= BITMASK(registers_mask[numreg]);
3045: dsp_write_reg(numreg, value);
1.1 root 3046: } else {
3047: /* Read S */
1.1.1.4 root 3048: if (numreg == DSP_REG_SSH) {
3049: dsp_stack_pop(&value, &dummy);
3050: }
3051: else if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1 root 3052: dsp_pm_read_accu24(numreg, &value);
1.1.1.4 root 3053: }
3054: else {
1.1.1.6 root 3055: value = dsp_core.registers[numreg];
1.1 root 3056: }
3057: write_memory(DSP_SPACE_P, addr, value);
3058: }
3059:
1.1.1.6 root 3060: dsp_core.instr_cycle += 4;
1.1 root 3061: }
3062:
3063: static void dsp_movep_0(void)
3064: {
3065: /* S,x:pp */
3066: /* x:pp,D */
3067: /* S,y:pp */
3068: /* y:pp,D */
3069:
1.1.1.4 root 3070: Uint32 addr, memspace, numreg, value, dummy;
1.1 root 3071:
3072: addr = 0xffc0 + (cur_inst & BITMASK(6));
3073: memspace = (cur_inst>>16) & 1;
3074: numreg = (cur_inst>>8) & BITMASK(6);
3075:
3076: if (cur_inst & (1<<15)) {
3077: /* Write pp */
3078: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
3079: dsp_pm_read_accu24(numreg, &value);
1.1.1.4 root 3080: }
3081: else if (numreg == DSP_REG_SSH) {
3082: dsp_stack_pop(&value, &dummy);
3083: }
3084: else {
1.1.1.6 root 3085: value = dsp_core.registers[numreg];
1.1 root 3086: }
3087: write_memory(memspace, addr, value);
3088: } else {
3089: /* Read pp */
3090: value = read_memory(memspace, addr);
1.1.1.4 root 3091: value &= BITMASK(registers_mask[numreg]);
3092: dsp_write_reg(numreg, value);
1.1 root 3093: }
1.1.1.4 root 3094:
1.1.1.6 root 3095: dsp_core.instr_cycle += 2;
1.1 root 3096: }
3097:
3098: static void dsp_movep_1(void)
3099: {
3100: /* p:ea,x:pp */
3101: /* x:pp,p:ea */
3102: /* p:ea,y:pp */
3103: /* y:pp,p:ea */
3104:
1.1.1.2 root 3105: Uint32 xyaddr, memspace, paddr;
1.1 root 3106:
3107: xyaddr = 0xffc0 + (cur_inst & BITMASK(6));
3108: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &paddr);
3109: memspace = (cur_inst>>16) & 1;
3110:
3111: if (cur_inst & (1<<15)) {
3112: /* Write pp */
1.1.1.4 root 3113: write_memory(memspace, xyaddr, read_memory_p(paddr));
1.1 root 3114: } else {
3115: /* Read pp */
3116: write_memory(DSP_SPACE_P, paddr, read_memory(memspace, xyaddr));
3117: }
1.1.1.4 root 3118:
1.1.1.7 root 3119: /* Movep is 4 cycles, but according to the motorola doc, */
3120: /* movep from p memory to x or y peripheral memory takes */
3121: /* 2 more cycles, so +4 cycles at total */
3122: dsp_core.instr_cycle += 4;
1.1 root 3123: }
3124:
1.1.1.4 root 3125: static void dsp_movep_23(void)
1.1 root 3126: {
3127: /* x:ea,x:pp */
3128: /* y:ea,x:pp */
3129: /* #xxxxxx,x:pp */
3130: /* x:pp,x:ea */
3131: /* x:pp,y:pp */
3132: /* x:ea,y:pp */
3133: /* y:ea,y:pp */
3134: /* #xxxxxx,y:pp */
3135: /* y:pp,y:ea */
3136: /* y:pp,x:ea */
3137:
1.1.1.2 root 3138: Uint32 addr, peraddr, easpace, perspace, ea_mode;
1.1 root 3139: int retour;
3140:
3141: peraddr = 0xffc0 + (cur_inst & BITMASK(6));
3142: perspace = (cur_inst>>16) & 1;
3143:
3144: ea_mode = (cur_inst>>8) & BITMASK(6);
3145: easpace = (cur_inst>>6) & 1;
3146: retour = dsp_calc_ea(ea_mode, &addr);
3147:
3148: if (cur_inst & (1<<15)) {
3149: /* Write pp */
3150:
3151: if (retour) {
3152: write_memory(perspace, peraddr, addr);
3153: } else {
3154: write_memory(perspace, peraddr, read_memory(easpace, addr));
3155: }
3156: } else {
3157: /* Read pp */
3158: write_memory(easpace, addr, read_memory(perspace, peraddr));
3159: }
1.1.1.4 root 3160:
1.1.1.6 root 3161: dsp_core.instr_cycle += 2;
1.1 root 3162: }
3163:
3164: static void dsp_norm(void)
3165: {
1.1.1.2 root 3166: Uint32 cursr,cur_e, cur_euz, dest[3], numreg, rreg;
3167: Uint16 newsr;
1.1 root 3168:
1.1.1.6 root 3169: cursr = dsp_core.registers[DSP_REG_SR];
1.1 root 3170: cur_e = (cursr>>DSP_SR_E) & 1; /* E */
3171: cur_euz = ~cur_e; /* (not E) and U and (not Z) */
3172: cur_euz &= (cursr>>DSP_SR_U) & 1;
3173: cur_euz &= ~((cursr>>DSP_SR_Z) & 1);
3174: cur_euz &= 1;
3175:
3176: numreg = (cur_inst>>3) & 1;
1.1.1.6 root 3177: dest[0] = dsp_core.registers[DSP_REG_A2+numreg];
3178: dest[1] = dsp_core.registers[DSP_REG_A1+numreg];
3179: dest[2] = dsp_core.registers[DSP_REG_A0+numreg];
1.1 root 3180: rreg = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3181:
3182: if (cur_euz) {
3183: newsr = dsp_asl56(dest);
1.1.1.6 root 3184: --dsp_core.registers[rreg];
3185: dsp_core.registers[rreg] &= BITMASK(16);
1.1 root 3186: } else if (cur_e) {
3187: newsr = dsp_asr56(dest);
1.1.1.6 root 3188: ++dsp_core.registers[rreg];
3189: dsp_core.registers[rreg] &= BITMASK(16);
1.1 root 3190: } else {
3191: newsr = 0;
3192: }
3193:
1.1.1.6 root 3194: dsp_core.registers[DSP_REG_A2+numreg] = dest[0];
3195: dsp_core.registers[DSP_REG_A1+numreg] = dest[1];
3196: dsp_core.registers[DSP_REG_A0+numreg] = dest[2];
1.1.1.2 root 3197:
1.1.1.6 root 3198: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 3199:
1.1.1.6 root 3200: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
3201: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 3202: }
3203:
3204: static void dsp_ori(void)
3205: {
1.1.1.2 root 3206: Uint32 regnum, value;
1.1 root 3207:
3208: value = (cur_inst >> 8) & BITMASK(8);
3209: regnum = cur_inst & BITMASK(2);
3210: switch(regnum) {
3211: case 0:
3212: /* mr */
1.1.1.6 root 3213: dsp_core.registers[DSP_REG_SR] |= value<<8;
1.1 root 3214: break;
3215: case 1:
3216: /* ccr */
1.1.1.6 root 3217: dsp_core.registers[DSP_REG_SR] |= value;
1.1 root 3218: break;
3219: case 2:
3220: /* omr */
1.1.1.6 root 3221: dsp_core.registers[DSP_REG_OMR] |= value;
1.1 root 3222: break;
3223: }
3224: }
3225:
1.1.1.3 root 3226: /*
3227: REP instruction parameter encoding
3228:
3229: xxxxxxxx 00xxxxxx 0xxxxxxx aa
3230: xxxxxxxx 01xxxxxx 0xxxxxxx ea
3231: xxxxxxxx YYxxxxxx 1xxxxxxx imm
3232: xxxxxxxx 11xxxxxx 0xxxxxxx reg
3233: */
3234:
3235: static void dsp_rep_aa(void)
1.1 root 3236: {
3237: /* x:aa */
3238: /* y:aa */
1.1.1.6 root 3239: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3240: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3241: dsp_core.loop_rep = 1; /* We are now running rep */
1.1 root 3242:
1.1.1.6 root 3243: dsp_core.registers[DSP_REG_LC]=read_memory((cur_inst>>6) & 1,(cur_inst>>8) & BITMASK(6));
1.1.1.4 root 3244:
1.1.1.6 root 3245: dsp_core.instr_cycle += 2;
1.1 root 3246: }
3247:
1.1.1.3 root 3248: static void dsp_rep_imm(void)
1.1 root 3249: {
3250: /* #xxx */
3251:
1.1.1.6 root 3252: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3253: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3254: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3255:
1.1.1.6 root 3256: dsp_core.registers[DSP_REG_LC] = ((cur_inst>>8) & BITMASK(8))
1.1.1.3 root 3257: + ((cur_inst & BITMASK(4))<<8);
1.1.1.4 root 3258:
1.1.1.6 root 3259: dsp_core.instr_cycle += 2;
1.1 root 3260: }
3261:
1.1.1.3 root 3262: static void dsp_rep_ea(void)
1.1 root 3263: {
1.1.1.2 root 3264: Uint32 value;
1.1 root 3265:
3266: /* x:ea */
3267: /* y:ea */
3268:
1.1.1.6 root 3269: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3270: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3271: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3272:
1.1 root 3273: dsp_calc_ea((cur_inst>>8) & BITMASK(6),&value);
1.1.1.6 root 3274: dsp_core.registers[DSP_REG_LC]= read_memory((cur_inst>>6) & 1, value);
1.1.1.4 root 3275:
1.1.1.6 root 3276: dsp_core.instr_cycle += 2;
1.1 root 3277: }
3278:
1.1.1.3 root 3279: static void dsp_rep_reg(void)
1.1 root 3280: {
1.1.1.2 root 3281: Uint32 numreg;
1.1 root 3282:
3283: /* R */
3284:
1.1.1.6 root 3285: dsp_core.registers[DSP_REG_LCSAVE] = dsp_core.registers[DSP_REG_LC];
3286: dsp_core.pc_on_rep = 1; /* Not decrement LC at first time */
3287: dsp_core.loop_rep = 1; /* We are now running rep */
1.1.1.4 root 3288:
1.1 root 3289: numreg = (cur_inst>>8) & BITMASK(6);
3290: if ((numreg == DSP_REG_A) || (numreg == DSP_REG_B)) {
1.1.1.6 root 3291: dsp_pm_read_accu24(numreg, &dsp_core.registers[DSP_REG_LC]);
1.1 root 3292: } else {
1.1.1.6 root 3293: dsp_core.registers[DSP_REG_LC] = dsp_core.registers[numreg];
1.1 root 3294: }
1.1.1.6 root 3295: dsp_core.registers[DSP_REG_LC] &= BITMASK(16);
1.1.1.4 root 3296:
1.1.1.6 root 3297: dsp_core.instr_cycle += 2;
1.1 root 3298: }
3299:
3300: static void dsp_reset(void)
3301: {
3302: /* Reset external peripherals */
1.1.1.6 root 3303: dsp_core.instr_cycle += 2;
1.1 root 3304: }
3305:
3306: static void dsp_rti(void)
3307: {
1.1.1.2 root 3308: Uint32 newpc = 0, newsr = 0;
1.1 root 3309:
3310: dsp_stack_pop(&newpc, &newsr);
1.1.1.6 root 3311: dsp_core.pc = newpc;
3312: dsp_core.registers[DSP_REG_SR] = newsr;
1.1 root 3313: cur_inst_len = 0;
1.1.1.4 root 3314:
1.1.1.6 root 3315: dsp_core.instr_cycle += 2;
1.1 root 3316: }
3317:
3318: static void dsp_rts(void)
3319: {
1.1.1.2 root 3320: Uint32 newpc = 0, newsr;
1.1 root 3321:
3322: dsp_stack_pop(&newpc, &newsr);
1.1.1.6 root 3323: dsp_core.pc = newpc;
1.1 root 3324: cur_inst_len = 0;
1.1.1.4 root 3325:
1.1.1.6 root 3326: dsp_core.instr_cycle += 2;
1.1 root 3327: }
3328:
3329: static void dsp_stop(void)
3330: {
1.1.1.6 root 3331: LOG_TRACE(TRACE_DSP_STATE, "Dsp: STOP instruction\n");
1.1 root 3332: }
3333:
3334: static void dsp_swi(void)
3335: {
3336: /* Raise interrupt p:0x0006 */
1.1.1.6 root 3337: dsp_core.instr_cycle += 6;
1.1 root 3338: }
3339:
3340: static void dsp_tcc(void)
3341: {
1.1.1.6 root 3342: Uint32 cc_code, regsrc1, regdest1;
1.1.1.2 root 3343: Uint32 regsrc2, regdest2;
1.1.1.6 root 3344: Uint32 val0, val1, val2;
3345:
1.1 root 3346: cc_code = (cur_inst>>12) & BITMASK(4);
3347:
3348: if (dsp_calc_cc(cc_code)) {
3349: regsrc1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][0];
1.1.1.2 root 3350: regdest1 = registers_tcc[(cur_inst>>3) & BITMASK(4)][1];
1.1 root 3351:
3352: /* Read S1 */
1.1.1.7 root 3353: if (regsrc1 == DSP_REG_A) {
3354: val0 = dsp_core.registers[DSP_REG_A0];
3355: val1 = dsp_core.registers[DSP_REG_A1];
3356: val2 = dsp_core.registers[DSP_REG_A2];
3357: }
3358: else if (regsrc1 == DSP_REG_B) {
3359: val0 = dsp_core.registers[DSP_REG_B0];
3360: val1 = dsp_core.registers[DSP_REG_B1];
3361: val2 = dsp_core.registers[DSP_REG_B2];
3362: }
3363: else {
1.1.1.6 root 3364: val0 = 0;
3365: val1 = dsp_core.registers[regsrc1];
1.1.1.7 root 3366: val2 = val1 & (1<<23) ? 0xff : 0x0;
1.1 root 3367: }
3368:
3369: /* Write D1 */
1.1.1.7 root 3370: if (regdest1 == DSP_REG_A) {
3371: dsp_core.registers[DSP_REG_A2] = val2;
3372: dsp_core.registers[DSP_REG_A1] = val1;
3373: dsp_core.registers[DSP_REG_A0] = val0;
3374: }
3375: else {
3376: dsp_core.registers[DSP_REG_B2] = val2;
3377: dsp_core.registers[DSP_REG_B1] = val1;
3378: dsp_core.registers[DSP_REG_B0] = val0;
3379: }
1.1 root 3380:
3381: /* S2,D2 transfer */
3382: if (cur_inst & (1<<16)) {
1.1.1.2 root 3383: regsrc2 = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
3384: regdest2 = DSP_REG_R0+(cur_inst & BITMASK(3));
1.1 root 3385:
1.1.1.6 root 3386: dsp_core.registers[regdest2] = dsp_core.registers[regsrc2];
1.1 root 3387: }
3388: }
3389: }
3390:
3391: static void dsp_wait(void)
3392: {
1.1.1.6 root 3393: LOG_TRACE(TRACE_DSP_STATE, "Dsp: WAIT instruction\n");
1.1 root 3394: }
3395:
1.1.1.2 root 3396: static int dsp_pm_read_accu24(int numreg, Uint32 *dest)
1.1 root 3397: {
1.1.1.4 root 3398: Uint32 scaling, value, reg;
1.1.1.7 root 3399: int got_limited = 0;
1.1 root 3400:
3401: /* Read an accumulator, stores it limited */
3402:
1.1.1.6 root 3403: scaling = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_S0) & BITMASK(2);
1.1.1.4 root 3404: reg = numreg & 1;
1.1 root 3405:
1.1.1.6 root 3406: value = (dsp_core.registers[DSP_REG_A2+reg]) << 24;
3407: value += dsp_core.registers[DSP_REG_A1+reg];
1.1 root 3408:
3409: switch(scaling) {
3410: case 0:
1.1.1.4 root 3411: /* No scaling */
3412: break;
3413: case 1:
3414: /* scaling down */
3415: value >>= 1;
1.1 root 3416: break;
3417: case 2:
1.1.1.4 root 3418: /* scaling up */
3419: value <<= 1;
1.1.1.6 root 3420: value |= (dsp_core.registers[DSP_REG_A0+reg]>>23) & 1;
1.1 root 3421: break;
1.1.1.4 root 3422: /* indeterminate */
3423: case 3:
3424: break;
3425: }
3426:
3427: /* limiting ? */
3428: value &= BITMASK(24);
3429:
1.1.1.6 root 3430: if (dsp_core.registers[DSP_REG_A2+reg] == 0) {
1.1.1.4 root 3431: if (value <= 0x007fffff) {
3432: /* No limiting */
3433: *dest=value;
3434: return 0;
3435: }
3436: }
3437:
1.1.1.6 root 3438: if (dsp_core.registers[DSP_REG_A2+reg] == 0xff) {
1.1.1.4 root 3439: if (value >= 0x00800000) {
3440: /* No limiting */
3441: *dest=value;
3442: return 0;
3443: }
1.1 root 3444: }
3445:
1.1.1.6 root 3446: if (dsp_core.registers[DSP_REG_A2+reg] & (1<<7)) {
1.1 root 3447: /* Limited to maximum negative value */
3448: *dest=0x00800000;
1.1.1.6 root 3449: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
1.1.1.2 root 3450: got_limited=1;
1.1 root 3451: } else {
3452: /* Limited to maximal positive value */
3453: *dest=0x007fffff;
1.1.1.6 root 3454: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_L);
1.1.1.2 root 3455: got_limited=1;
1.1 root 3456: }
1.1.1.2 root 3457:
3458: return got_limited;
1.1 root 3459: }
3460:
3461: static void dsp_pm_0(void)
3462: {
1.1.1.6 root 3463: Uint32 memspace, numreg, addr, save_accu, save_xy0;
1.1 root 3464: /*
3465: 0000 100d 00mm mrrr S,x:ea x0,D
3466: 0000 100d 10mm mrrr S,y:ea y0,D
3467: */
3468: memspace = (cur_inst>>15) & 1;
3469: numreg = (cur_inst>>16) & 1;
1.1.1.6 root 3470: dsp_calc_ea((cur_inst>>8) & BITMASK(6), &addr);
3471:
3472: /* Save A or B */
3473: dsp_pm_read_accu24(numreg, &save_accu);
1.1 root 3474:
1.1.1.6 root 3475: /* Save X0 or Y0 */
3476: save_xy0 = dsp_core.registers[DSP_REG_X0+(memspace<<1)];
3477:
3478: /* Execute parallel instruction */
3479: opcodes_alu[cur_inst & BITMASK(8)]();
3480:
3481: /* Move [A|B] to [x|y]:ea */
3482: write_memory(memspace, addr, save_accu);
3483:
3484: /* Move [x|y]0 to [A|B] */
3485: dsp_core.registers[DSP_REG_A0+numreg] = 0;
3486: dsp_core.registers[DSP_REG_A1+numreg] = save_xy0;
1.1.1.7 root 3487: dsp_core.registers[DSP_REG_A2+numreg] = save_xy0 & (1<<23) ? 0xff : 0x0;
1.1 root 3488: }
3489:
3490: static void dsp_pm_1(void)
3491: {
1.1.1.6 root 3492: Uint32 memspace, numreg1, numreg2, value, xy_addr, retour, save_1, save_2;
1.1 root 3493: /*
3494: 0001 ffdf w0mm mrrr x:ea,D1 S2,D2
3495: S1,x:ea S2,D2
3496: #xxxxxx,D1 S2,D2
3497: 0001 deff w1mm mrrr S1,D1 y:ea,D2
3498: S1,D1 S2,y:ea
3499: S1,D1 #xxxxxx,D2
3500: */
3501: value = (cur_inst>>8) & BITMASK(6);
3502: retour = dsp_calc_ea(value, &xy_addr);
3503: memspace = (cur_inst>>14) & 1;
1.1.1.6 root 3504: numreg1 = numreg2 = DSP_REG_NULL;
1.1 root 3505:
3506: if (memspace) {
3507: /* Y: */
3508: switch((cur_inst>>16) & BITMASK(2)) {
1.1.1.6 root 3509: case 0: numreg1 = DSP_REG_Y0; break;
3510: case 1: numreg1 = DSP_REG_Y1; break;
3511: case 2: numreg1 = DSP_REG_A; break;
3512: case 3: numreg1 = DSP_REG_B; break;
1.1 root 3513: }
3514: } else {
3515: /* X: */
3516: switch((cur_inst>>18) & BITMASK(2)) {
1.1.1.6 root 3517: case 0: numreg1 = DSP_REG_X0; break;
3518: case 1: numreg1 = DSP_REG_X1; break;
3519: case 2: numreg1 = DSP_REG_A; break;
3520: case 3: numreg1 = DSP_REG_B; break;
1.1 root 3521: }
3522: }
3523:
3524: if (cur_inst & (1<<15)) {
3525: /* Write D1 */
1.1.1.6 root 3526: if (retour)
3527: save_1 = xy_addr;
3528: else
3529: save_1 = read_memory(memspace, xy_addr);
1.1 root 3530: } else {
3531: /* Read S1 */
1.1.1.6 root 3532: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
3533: dsp_pm_read_accu24(numreg1, &save_1);
3534: else
3535: save_1 = dsp_core.registers[numreg1];
1.1 root 3536: }
1.1.1.6 root 3537:
1.1 root 3538: /* S2 */
3539: if (memspace) {
3540: /* Y: */
1.1.1.6 root 3541: numreg2 = DSP_REG_A + ((cur_inst>>19) & 1);
1.1 root 3542: } else {
3543: /* X: */
1.1.1.6 root 3544: numreg2 = DSP_REG_A + ((cur_inst>>17) & 1);
1.1 root 3545: }
1.1.1.6 root 3546: dsp_pm_read_accu24(numreg2, &save_2);
1.1 root 3547:
1.1.1.6 root 3548:
3549: /* Execute parallel instruction */
3550: opcodes_alu[cur_inst & BITMASK(8)]();
3551:
3552:
3553: /* Write parallel move values */
3554: if (cur_inst & (1<<15)) {
3555: /* Write D1 */
3556: if (numreg1 == DSP_REG_A) {
3557: dsp_core.registers[DSP_REG_A0] = 0x0;
3558: dsp_core.registers[DSP_REG_A1] = save_1;
3559: dsp_core.registers[DSP_REG_A2] = save_1 & (1<<23) ? 0xff : 0x0;
3560: }
3561: else if (numreg1 == DSP_REG_B) {
3562: dsp_core.registers[DSP_REG_B0] = 0x0;
3563: dsp_core.registers[DSP_REG_B1] = save_1;
3564: dsp_core.registers[DSP_REG_B2] = save_1 & (1<<23) ? 0xff : 0x0;
3565: }
3566: else {
3567: } dsp_core.registers[numreg1] = save_1;
3568: } else {
3569: /* Read S1 */
3570: write_memory(memspace, xy_addr, save_1);
3571: }
3572:
3573: /* S2 -> D2 */
1.1 root 3574: if (memspace) {
3575: /* Y: */
1.1.1.6 root 3576: numreg2 = DSP_REG_X0 + ((cur_inst>>18) & 1);
1.1 root 3577: } else {
3578: /* X: */
1.1.1.6 root 3579: numreg2 = DSP_REG_Y0 + ((cur_inst>>16) & 1);
1.1 root 3580: }
1.1.1.6 root 3581: dsp_core.registers[numreg2] = save_2;
1.1 root 3582: }
3583:
3584: static void dsp_pm_2(void)
3585: {
1.1.1.2 root 3586: Uint32 dummy;
1.1 root 3587: /*
3588: 0010 0000 0000 0000 nop
3589: 0010 0000 010m mrrr R update
3590: 0010 00ee eeed dddd S,D
3591: 001d dddd iiii iiii #xx,D
3592: */
1.1.1.4 root 3593: if ((cur_inst & 0xffff00) == 0x200000) {
1.1.1.6 root 3594: /* Execute parallel instruction */
3595: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3596: return;
3597: }
3598:
1.1.1.4 root 3599: if ((cur_inst & 0xffe000) == 0x204000) {
1.1 root 3600: dsp_calc_ea((cur_inst>>8) & BITMASK(5), &dummy);
1.1.1.6 root 3601: /* Execute parallel instruction */
3602: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3603: return;
3604: }
3605:
1.1.1.4 root 3606: if ((cur_inst & 0xfc0000) == 0x200000) {
1.1 root 3607: dsp_pm_2_2();
3608: return;
3609: }
3610:
3611: dsp_pm_3();
3612: }
3613:
3614: static void dsp_pm_2_2(void)
3615: {
3616: /*
3617: 0010 00ee eeed dddd S,D
3618: */
1.1.1.6 root 3619: Uint32 srcreg, dstreg, save_reg;
1.1 root 3620:
3621: srcreg = (cur_inst >> 13) & BITMASK(5);
3622: dstreg = (cur_inst >> 8) & BITMASK(5);
3623:
1.1.1.6 root 3624: if ((srcreg == DSP_REG_A) || (srcreg == DSP_REG_B))
3625: /* Accu to register: limited 24 bits */
3626: dsp_pm_read_accu24(srcreg, &save_reg);
3627: else
3628: save_reg = dsp_core.registers[srcreg];
3629:
3630: /* Execute parallel instruction */
3631: opcodes_alu[cur_inst & BITMASK(8)]();
3632:
3633: /* Write reg */
3634: if (dstreg == DSP_REG_A) {
3635: dsp_core.registers[DSP_REG_A0] = 0x0;
3636: dsp_core.registers[DSP_REG_A1] = save_reg;
3637: dsp_core.registers[DSP_REG_A2] = save_reg & (1<<23) ? 0xff : 0x0;
3638: }
3639: else if (dstreg == DSP_REG_B) {
3640: dsp_core.registers[DSP_REG_B0] = 0x0;
3641: dsp_core.registers[DSP_REG_B1] = save_reg;
3642: dsp_core.registers[DSP_REG_B2] = save_reg & (1<<23) ? 0xff : 0x0;
3643: }
3644: else {
3645: dsp_core.registers[dstreg] = save_reg & BITMASK(registers_mask[dstreg]);
1.1 root 3646: }
3647: }
3648:
3649: static void dsp_pm_3(void)
3650: {
1.1.1.6 root 3651: Uint32 dstreg, srcvalue;
1.1 root 3652: /*
3653: 001d dddd iiii iiii #xx,R
3654: */
1.1.1.6 root 3655:
3656: /* Execute parallel instruction */
3657: opcodes_alu[cur_inst & BITMASK(8)]();
3658:
3659: /* Write reg */
3660: dstreg = (cur_inst >> 16) & BITMASK(5);
1.1 root 3661: srcvalue = (cur_inst >> 8) & BITMASK(8);
3662:
1.1.1.6 root 3663: switch(dstreg) {
1.1 root 3664: case DSP_REG_X0:
3665: case DSP_REG_X1:
3666: case DSP_REG_Y0:
3667: case DSP_REG_Y1:
3668: case DSP_REG_A:
3669: case DSP_REG_B:
3670: srcvalue <<= 16;
3671: break;
3672: }
3673:
1.1.1.6 root 3674: if (dstreg == DSP_REG_A) {
3675: dsp_core.registers[DSP_REG_A0] = 0x0;
3676: dsp_core.registers[DSP_REG_A1] = srcvalue;
3677: dsp_core.registers[DSP_REG_A2] = srcvalue & (1<<23) ? 0xff : 0x0;
3678: }
3679: else if (dstreg == DSP_REG_B) {
3680: dsp_core.registers[DSP_REG_B0] = 0x0;
3681: dsp_core.registers[DSP_REG_B1] = srcvalue;
3682: dsp_core.registers[DSP_REG_B2] = srcvalue & (1<<23) ? 0xff : 0x0;
3683: }
3684: else {
3685: dsp_core.registers[dstreg] = srcvalue & BITMASK(registers_mask[dstreg]);
1.1 root 3686: }
3687: }
3688:
3689: static void dsp_pm_4(void)
3690: {
3691: /*
1.1.1.4 root 3692: 0100 l0ll w0aa aaaa l:aa,D
1.1 root 3693: S,l:aa
1.1.1.4 root 3694: 0100 l0ll w1mm mrrr l:ea,D
1.1 root 3695: S,l:ea
1.1.1.4 root 3696: 01dd 0ddd w0aa aaaa x:aa,D
1.1 root 3697: S,x:aa
1.1.1.4 root 3698: 01dd 0ddd w1mm mrrr x:ea,D
1.1 root 3699: S,x:ea
3700: #xxxxxx,D
1.1.1.4 root 3701: 01dd 1ddd w0aa aaaa y:aa,D
1.1 root 3702: S,y:aa
1.1.1.4 root 3703: 01dd 1ddd w1mm mrrr y:ea,D
1.1 root 3704: S,y:ea
3705: #xxxxxx,D
3706: */
1.1.1.4 root 3707: if ((cur_inst & 0xf40000)==0x400000) {
3708: dsp_pm_4x();
1.1 root 3709: return;
3710: }
3711:
3712: dsp_pm_5();
3713: }
3714:
1.1.1.4 root 3715: static void dsp_pm_4x(void)
1.1 root 3716: {
1.1.1.6 root 3717: Uint32 value, numreg, l_addr, save_lx, save_ly;
1.1 root 3718: /*
1.1.1.4 root 3719: 0100 l0ll w0aa aaaa l:aa,D
3720: S,l:aa
3721: 0100 l0ll w1mm mrrr l:ea,D
3722: S,l:ea
1.1 root 3723: */
1.1.1.4 root 3724: value = (cur_inst>>8) & BITMASK(6);
3725: if (cur_inst & (1<<14)) {
3726: dsp_calc_ea(value, &l_addr);
3727: } else {
3728: l_addr = value;
3729: }
3730:
1.1 root 3731: numreg = (cur_inst>>16) & BITMASK(2);
3732: numreg |= (cur_inst>>17) & (1<<2);
3733:
3734: if (cur_inst & (1<<15)) {
3735: /* Write D */
1.1.1.6 root 3736: save_lx = read_memory(DSP_SPACE_X,l_addr);
3737: save_ly = read_memory(DSP_SPACE_Y,l_addr);
3738: }
3739: else {
3740: /* Read S */
1.1.1.4 root 3741: switch(numreg) {
3742: case 0:
3743: /* A10 */
1.1.1.6 root 3744: save_lx = dsp_core.registers[DSP_REG_A1];
3745: save_ly = dsp_core.registers[DSP_REG_A0];
1.1.1.4 root 3746: break;
3747: case 1:
3748: /* B10 */
1.1.1.6 root 3749: save_lx = dsp_core.registers[DSP_REG_B1];
3750: save_ly = dsp_core.registers[DSP_REG_B0];
1.1.1.4 root 3751: break;
3752: case 2:
3753: /* X */
1.1.1.6 root 3754: save_lx = dsp_core.registers[DSP_REG_X1];
3755: save_ly = dsp_core.registers[DSP_REG_X0];
1.1.1.4 root 3756: break;
3757: case 3:
3758: /* Y */
1.1.1.6 root 3759: save_lx = dsp_core.registers[DSP_REG_Y1];
3760: save_ly = dsp_core.registers[DSP_REG_Y0];
1.1.1.4 root 3761: break;
3762: case 4:
3763: /* A */
1.1.1.6 root 3764: if (dsp_pm_read_accu24(DSP_REG_A, &save_lx)) {
3765: /* Was limited, set lower part */
3766: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3767: } else {
3768: /* Not limited */
3769: save_ly = dsp_core.registers[DSP_REG_A0];
3770: }
1.1.1.4 root 3771: break;
3772: case 5:
3773: /* B */
1.1.1.6 root 3774: if (dsp_pm_read_accu24(DSP_REG_B, &save_lx)) {
3775: /* Was limited, set lower part */
3776: save_ly = (save_lx & (1<<23) ? 0 : 0xffffff);
3777: } else {
3778: /* Not limited */
3779: save_ly = dsp_core.registers[DSP_REG_B0];
3780: }
1.1.1.4 root 3781: break;
3782: case 6:
3783: /* AB */
1.1.1.6 root 3784: dsp_pm_read_accu24(DSP_REG_A, &save_lx);
3785: dsp_pm_read_accu24(DSP_REG_B, &save_ly);
1.1.1.4 root 3786: break;
3787: case 7:
3788: /* BA */
1.1.1.6 root 3789: dsp_pm_read_accu24(DSP_REG_B, &save_lx);
3790: dsp_pm_read_accu24(DSP_REG_A, &save_ly);
1.1.1.4 root 3791: break;
1.1 root 3792: }
1.1.1.6 root 3793: }
1.1 root 3794:
1.1.1.6 root 3795: /* Execute parallel instruction */
3796: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3797:
1.1.1.6 root 3798:
3799: if (cur_inst & (1<<15)) {
3800: /* Write D */
1.1.1.4 root 3801: switch(numreg) {
1.1.1.6 root 3802: case 0: /* A10 */
3803: dsp_core.registers[DSP_REG_A1] = save_lx;
3804: dsp_core.registers[DSP_REG_A0] = save_ly;
1.1.1.4 root 3805: break;
1.1.1.6 root 3806: case 1: /* B10 */
3807: dsp_core.registers[DSP_REG_B1] = save_lx;
3808: dsp_core.registers[DSP_REG_B0] = save_ly;
1.1.1.4 root 3809: break;
1.1.1.6 root 3810: case 2: /* X */
3811: dsp_core.registers[DSP_REG_X1] = save_lx;
3812: dsp_core.registers[DSP_REG_X0] = save_ly;
1.1.1.4 root 3813: break;
1.1.1.6 root 3814: case 3: /* Y */
3815: dsp_core.registers[DSP_REG_Y1] = save_lx;
3816: dsp_core.registers[DSP_REG_Y0] = save_ly;
1.1.1.4 root 3817: break;
1.1.1.6 root 3818: case 4: /* A */
3819: dsp_core.registers[DSP_REG_A0] = save_ly;
3820: dsp_core.registers[DSP_REG_A1] = save_lx;
3821: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
1.1.1.4 root 3822: break;
1.1.1.6 root 3823: case 5: /* B */
3824: dsp_core.registers[DSP_REG_B0] = save_ly;
3825: dsp_core.registers[DSP_REG_B1] = save_lx;
3826: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
1.1.1.4 root 3827: break;
1.1.1.6 root 3828: case 6: /* AB */
3829: dsp_core.registers[DSP_REG_A0] = 0;
3830: dsp_core.registers[DSP_REG_A1] = save_lx;
3831: dsp_core.registers[DSP_REG_A2] = save_lx & (1<<23) ? 0xff : 0;
3832: dsp_core.registers[DSP_REG_B0] = 0;
3833: dsp_core.registers[DSP_REG_B1] = save_ly;
3834: dsp_core.registers[DSP_REG_B2] = save_ly & (1<<23) ? 0xff : 0;
1.1.1.4 root 3835: break;
1.1.1.6 root 3836: case 7: /* BA */
3837: dsp_core.registers[DSP_REG_B0] = 0;
3838: dsp_core.registers[DSP_REG_B1] = save_lx;
3839: dsp_core.registers[DSP_REG_B2] = save_lx & (1<<23) ? 0xff : 0;
3840: dsp_core.registers[DSP_REG_A0] = 0;
3841: dsp_core.registers[DSP_REG_A1] = save_ly;
3842: dsp_core.registers[DSP_REG_A2] = save_ly & (1<<23) ? 0xff : 0;
1.1.1.4 root 3843: break;
1.1 root 3844: }
1.1.1.6 root 3845: }
3846: else {
3847: /* Read S */
3848: write_memory(DSP_SPACE_X, l_addr, save_lx);
3849: write_memory(DSP_SPACE_Y, l_addr, save_ly);
1.1 root 3850: }
3851: }
3852:
3853: static void dsp_pm_5(void)
3854: {
1.1.1.2 root 3855: Uint32 memspace, numreg, value, xy_addr, retour;
1.1 root 3856: /*
1.1.1.4 root 3857: 01dd 0ddd w0aa aaaa x:aa,D
1.1 root 3858: S,x:aa
1.1.1.4 root 3859: 01dd 0ddd w1mm mrrr x:ea,D
1.1 root 3860: S,x:ea
3861: #xxxxxx,D
1.1.1.4 root 3862: 01dd 1ddd w0aa aaaa y:aa,D
1.1 root 3863: S,y:aa
1.1.1.4 root 3864: 01dd 1ddd w1mm mrrr y:ea,D
1.1 root 3865: S,y:ea
3866: #xxxxxx,D
3867: */
3868:
3869: value = (cur_inst>>8) & BITMASK(6);
3870:
3871: if (cur_inst & (1<<14)) {
3872: retour = dsp_calc_ea(value, &xy_addr);
3873: } else {
3874: xy_addr = value;
3875: retour = 0;
3876: }
3877:
3878: memspace = (cur_inst>>19) & 1;
3879: numreg = (cur_inst>>16) & BITMASK(3);
3880: numreg |= (cur_inst>>17) & (BITMASK(2)<<3);
3881:
3882: if (cur_inst & (1<<15)) {
3883: /* Write D */
1.1.1.6 root 3884: if (retour)
1.1 root 3885: value = xy_addr;
1.1.1.6 root 3886: else
1.1 root 3887: value = read_memory(memspace, xy_addr);
1.1.1.6 root 3888: }
3889: else {
1.1 root 3890: /* Read S */
1.1.1.6 root 3891: if ((numreg==DSP_REG_A) || (numreg==DSP_REG_B))
3892: dsp_pm_read_accu24(numreg, &value);
3893: else
3894: value = dsp_core.registers[numreg];
3895: }
1.1 root 3896:
3897:
1.1.1.6 root 3898: /* Execute parallel instruction */
3899: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3900:
1.1.1.6 root 3901: if (cur_inst & (1<<15)) {
3902: /* Write D */
3903: if (numreg == DSP_REG_A) {
3904: dsp_core.registers[DSP_REG_A0] = 0x0;
3905: dsp_core.registers[DSP_REG_A1] = value;
3906: dsp_core.registers[DSP_REG_A2] = value & (1<<23) ? 0xff : 0x0;
3907: }
3908: else if (numreg == DSP_REG_B) {
3909: dsp_core.registers[DSP_REG_B0] = 0x0;
3910: dsp_core.registers[DSP_REG_B1] = value;
3911: dsp_core.registers[DSP_REG_B2] = value & (1<<23) ? 0xff : 0x0;
3912: }
3913: else {
3914: dsp_core.registers[numreg] = value & BITMASK(registers_mask[numreg]);
3915: }
3916: }
3917: else {
1.1.1.7 root 3918: /* Read S */
1.1.1.6 root 3919: write_memory(memspace, xy_addr, value);
1.1 root 3920: }
3921: }
3922:
3923: static void dsp_pm_8(void)
3924: {
1.1.1.2 root 3925: Uint32 ea1, ea2;
3926: Uint32 numreg1, numreg2;
1.1.1.6 root 3927: Uint32 save_reg1, save_reg2, x_addr, y_addr;
1.1 root 3928: /*
1.1.1.4 root 3929: 1wmm eeff WrrM MRRR x:ea,D1 y:ea,D2
1.1 root 3930: x:ea,D1 S2,y:ea
3931: S1,x:ea y:ea,D2
3932: S1,x:ea S2,y:ea
3933: */
3934: numreg1 = numreg2 = DSP_REG_NULL;
3935:
3936: ea1 = (cur_inst>>8) & BITMASK(5);
3937: if ((ea1>>3) == 0) {
3938: ea1 |= (1<<5);
3939: }
3940: ea2 = (cur_inst>>13) & BITMASK(2);
3941: ea2 |= (cur_inst>>17) & (BITMASK(2)<<3);
3942: if ((ea1 & (1<<2))==0) {
3943: ea2 |= 1<<2;
3944: }
3945: if ((ea2>>3) == 0) {
3946: ea2 |= (1<<5);
3947: }
3948:
1.1.1.4 root 3949: dsp_calc_ea(ea1, &x_addr);
3950: dsp_calc_ea(ea2, &y_addr);
3951:
1.1 root 3952: switch((cur_inst>>18) & BITMASK(2)) {
3953: case 0: numreg1=DSP_REG_X0; break;
3954: case 1: numreg1=DSP_REG_X1; break;
3955: case 2: numreg1=DSP_REG_A; break;
3956: case 3: numreg1=DSP_REG_B; break;
3957: }
3958: switch((cur_inst>>16) & BITMASK(2)) {
3959: case 0: numreg2=DSP_REG_Y0; break;
3960: case 1: numreg2=DSP_REG_Y1; break;
3961: case 2: numreg2=DSP_REG_A; break;
3962: case 3: numreg2=DSP_REG_B; break;
3963: }
3964:
3965: if (cur_inst & (1<<15)) {
3966: /* Write D1 */
1.1.1.6 root 3967: save_reg1 = read_memory(DSP_SPACE_X, x_addr);
1.1 root 3968: } else {
3969: /* Read S1 */
1.1.1.6 root 3970: if ((numreg1==DSP_REG_A) || (numreg1==DSP_REG_B))
3971: dsp_pm_read_accu24(numreg1, &save_reg1);
3972: else
3973: save_reg1 = dsp_core.registers[numreg1];
1.1 root 3974: }
3975:
3976: if (cur_inst & (1<<22)) {
3977: /* Write D2 */
1.1.1.6 root 3978: save_reg2 = read_memory(DSP_SPACE_Y, y_addr);
1.1 root 3979: } else {
3980: /* Read S2 */
1.1.1.6 root 3981: if ((numreg2==DSP_REG_A) || (numreg2==DSP_REG_B))
3982: dsp_pm_read_accu24(numreg2, &save_reg2);
3983: else
3984: save_reg2 = dsp_core.registers[numreg2];
1.1 root 3985: }
3986:
3987:
1.1.1.6 root 3988: /* Execute parallel instruction */
3989: opcodes_alu[cur_inst & BITMASK(8)]();
1.1 root 3990:
1.1.1.6 root 3991: /* Write first parallel move */
3992: if (cur_inst & (1<<15)) {
3993: /* Write D1 */
3994: if (numreg1 == DSP_REG_A) {
3995: dsp_core.registers[DSP_REG_A0] = 0x0;
3996: dsp_core.registers[DSP_REG_A1] = save_reg1;
3997: dsp_core.registers[DSP_REG_A2] = save_reg1 & (1<<23) ? 0xff : 0x0;
3998: }
3999: else if (numreg1 == DSP_REG_B) {
4000: dsp_core.registers[DSP_REG_B0] = 0x0;
4001: dsp_core.registers[DSP_REG_B1] = save_reg1;
4002: dsp_core.registers[DSP_REG_B2] = save_reg1 & (1<<23) ? 0xff : 0x0;
4003: }
4004: else {
4005: dsp_core.registers[numreg1] = save_reg1;
4006: }
4007: } else {
4008: /* Read S1 */
4009: write_memory(DSP_SPACE_X, x_addr, save_reg1);
4010: }
4011:
4012: /* Write second parallel move */
4013: if (cur_inst & (1<<22)) {
4014: /* Write D2 */
4015: if (numreg2 == DSP_REG_A) {
4016: dsp_core.registers[DSP_REG_A0] = 0x0;
4017: dsp_core.registers[DSP_REG_A1] = save_reg2;
4018: dsp_core.registers[DSP_REG_A2] = save_reg2 & (1<<23) ? 0xff : 0x0;
4019: }
4020: else if (numreg2 == DSP_REG_B) {
4021: dsp_core.registers[DSP_REG_B0] = 0x0;
4022: dsp_core.registers[DSP_REG_B1] = save_reg2;
4023: dsp_core.registers[DSP_REG_B2] = save_reg2 & (1<<23) ? 0xff : 0x0;
4024: }
4025: else {
4026: dsp_core.registers[numreg2] = save_reg2;
4027: }
4028: } else {
4029: /* Read S2 */
4030: write_memory(DSP_SPACE_Y, y_addr, save_reg2);
4031: }
4032: }
4033:
4034: /**********************************
4035: * 56bit arithmetic
4036: **********************************/
4037:
4038: /* source,dest[0] is 55:48 */
4039: /* source,dest[1] is 47:24 */
4040: /* source,dest[2] is 23:00 */
4041:
4042: static Uint16 dsp_abs56(Uint32 *dest)
1.1 root 4043: {
1.1.1.2 root 4044: Uint32 zerodest[3];
4045: Uint16 newsr;
1.1 root 4046:
4047: /* D=|D| */
4048:
4049: if (dest[0] & (1<<7)) {
4050: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4051:
4052: newsr = dsp_sub56(dest, zerodest);
4053:
4054: dest[0] = zerodest[0];
4055: dest[1] = zerodest[1];
4056: dest[2] = zerodest[2];
4057: } else {
4058: newsr = 0;
4059: }
4060:
4061: return newsr;
4062: }
4063:
1.1.1.2 root 4064: static Uint16 dsp_asl56(Uint32 *dest)
1.1 root 4065: {
1.1.1.2 root 4066: Uint16 overflow, carry;
1.1 root 4067:
4068: /* Shift left dest 1 bit: D<<=1 */
4069:
4070: carry = (dest[0]>>7) & 1;
4071:
4072: dest[0] <<= 1;
4073: dest[0] |= (dest[1]>>23) & 1;
4074: dest[0] &= BITMASK(8);
4075:
4076: dest[1] <<= 1;
4077: dest[1] |= (dest[2]>>23) & 1;
4078: dest[1] &= BITMASK(24);
4079:
4080: dest[2] <<= 1;
4081: dest[2] &= BITMASK(24);
4082:
4083: overflow = (carry != ((dest[0]>>7) & 1));
4084:
4085: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4086: }
4087:
1.1.1.2 root 4088: static Uint16 dsp_asr56(Uint32 *dest)
1.1 root 4089: {
1.1.1.2 root 4090: Uint16 carry;
1.1 root 4091:
4092: /* Shift right dest 1 bit: D>>=1 */
4093:
4094: carry = dest[2] & 1;
4095:
4096: dest[2] >>= 1;
4097: dest[2] |= (dest[1] & 1)<<23;
4098:
4099: dest[1] >>= 1;
4100: dest[1] |= (dest[0] & 1)<<23;
4101:
4102: dest[0] >>= 1;
4103: dest[0] |= (dest[0] & (1<<6))<<1;
4104:
4105: return (carry<<DSP_SR_C);
4106: }
4107:
1.1.1.2 root 4108: static Uint16 dsp_add56(Uint32 *source, Uint32 *dest)
1.1 root 4109: {
1.1.1.4 root 4110: Uint16 overflow, carry, flg_s, flg_d, flg_r;
4111:
4112: flg_s = (source[0]>>7) & 1;
4113: flg_d = (dest[0]>>7) & 1;
4114:
1.1 root 4115: /* Add source to dest: D = D+S */
1.1.1.2 root 4116: dest[2] += source[2];
4117: dest[1] += source[1]+((dest[2]>>24) & 1);
4118: dest[0] += source[0]+((dest[1]>>24) & 1);
1.1 root 4119:
1.1.1.5 root 4120: carry = (dest[0]>>8) & 1;
4121:
1.1 root 4122: dest[2] &= BITMASK(24);
4123: dest[1] &= BITMASK(24);
4124: dest[0] &= BITMASK(8);
4125:
1.1.1.4 root 4126: flg_r = (dest[0]>>7) & 1;
4127:
4128: /*set overflow*/
4129: overflow = (flg_s ^ flg_r) & (flg_d ^ flg_r);
4130:
1.1 root 4131: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4132: }
4133:
1.1.1.2 root 4134: static Uint16 dsp_sub56(Uint32 *source, Uint32 *dest)
1.1 root 4135: {
1.1.1.5 root 4136: Uint16 overflow, carry, flg_s, flg_d, flg_r, dest_save;
1.1.1.4 root 4137:
1.1.1.5 root 4138: dest_save = dest[0];
1.1 root 4139:
1.1.1.9 ! root 4140: /* Subtract source from dest: D = D-S */
1.1.1.2 root 4141: dest[2] -= source[2];
4142: dest[1] -= source[1]+((dest[2]>>24) & 1);
4143: dest[0] -= source[0]+((dest[1]>>24) & 1);
1.1 root 4144:
1.1.1.5 root 4145: carry = (dest[0]>>8) & 1;
4146:
1.1 root 4147: dest[2] &= BITMASK(24);
4148: dest[1] &= BITMASK(24);
4149: dest[0] &= BITMASK(8);
4150:
1.1.1.4 root 4151: flg_s = (source[0]>>7) & 1;
1.1.1.5 root 4152: flg_d = (dest_save>>7) & 1;
1.1.1.4 root 4153: flg_r = (dest[0]>>7) & 1;
4154:
4155: /* set overflow */
4156: overflow = (flg_s ^ flg_d) & (flg_r ^ flg_d);
4157:
1.1 root 4158: return (overflow<<DSP_SR_L)|(overflow<<DSP_SR_V)|(carry<<DSP_SR_C);
4159: }
4160:
1.1.1.5 root 4161: static void dsp_mul56(Uint32 source1, Uint32 source2, Uint32 *dest, Uint8 signe)
1.1 root 4162: {
1.1.1.2 root 4163: Uint32 part[4], zerodest[3], value;
1.1 root 4164:
4165: /* Multiply: D = S1*S2 */
4166: if (source1 & (1<<23)) {
1.1.1.5 root 4167: signe ^= 1;
1.1.1.6 root 4168: source1 = (1<<24) - source1;
1.1 root 4169: }
4170: if (source2 & (1<<23)) {
1.1.1.5 root 4171: signe ^= 1;
1.1.1.6 root 4172: source2 = (1<<24) - source2;
1.1 root 4173: }
4174:
4175: /* bits 0-11 * bits 0-11 */
4176: part[0]=(source1 & BITMASK(12))*(source2 & BITMASK(12));
4177: /* bits 12-23 * bits 0-11 */
4178: part[1]=((source1>>12) & BITMASK(12))*(source2 & BITMASK(12));
4179: /* bits 0-11 * bits 12-23 */
4180: part[2]=(source1 & BITMASK(12))*((source2>>12) & BITMASK(12));
4181: /* bits 12-23 * bits 12-23 */
4182: part[3]=((source1>>12) & BITMASK(12))*((source2>>12) & BITMASK(12));
4183:
4184: /* Calc dest 2 */
4185: dest[2] = part[0];
4186: dest[2] += (part[1] & BITMASK(12)) << 12;
4187: dest[2] += (part[2] & BITMASK(12)) << 12;
4188:
4189: /* Calc dest 1 */
4190: dest[1] = (part[1]>>12) & BITMASK(12);
4191: dest[1] += (part[2]>>12) & BITMASK(12);
4192: dest[1] += part[3];
4193:
4194: /* Calc dest 0 */
4195: dest[0] = 0;
4196:
4197: /* Add carries */
4198: value = (dest[2]>>24) & BITMASK(8);
4199: if (value) {
4200: dest[1] += value;
4201: dest[2] &= BITMASK(24);
4202: }
4203: value = (dest[1]>>24) & BITMASK(8);
4204: if (value) {
4205: dest[0] += value;
4206: dest[1] &= BITMASK(24);
4207: }
4208:
4209: /* Get rid of extra sign bit */
4210: dsp_asl56(dest);
4211:
1.1.1.5 root 4212: if (signe) {
1.1 root 4213: zerodest[0] = zerodest[1] = zerodest[2] = 0;
4214:
4215: dsp_sub56(dest, zerodest);
4216:
4217: dest[0] = zerodest[0];
4218: dest[1] = zerodest[1];
4219: dest[2] = zerodest[2];
4220: }
4221: }
4222:
1.1.1.2 root 4223: static void dsp_rnd56(Uint32 *dest)
1.1 root 4224: {
1.1.1.4 root 4225: Uint32 rnd_const[3];
1.1 root 4226:
1.1.1.4 root 4227: rnd_const[0] = 0;
1.1 root 4228:
1.1.1.4 root 4229: /* Scaling mode S0 */
1.1.1.6 root 4230: if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S0)) {
1.1.1.4 root 4231: rnd_const[1] = 1;
4232: rnd_const[2] = 0;
4233: dsp_add56(rnd_const, dest);
4234:
4235: if ((dest[2]==0) && ((dest[1] & 1) == 0)) {
4236: dest[1] &= (0xffffff - 0x3);
4237: }
4238: dest[1] &= 0xfffffe;
4239: dest[2]=0;
4240: }
4241: /* Scaling mode S1 */
1.1.1.6 root 4242: else if (dsp_core.registers[DSP_REG_SR] & (1<<DSP_SR_S1)) {
1.1.1.4 root 4243: rnd_const[1] = 0;
4244: rnd_const[2] = (1<<22);
4245: dsp_add56(rnd_const, dest);
4246:
4247: if ((dest[2] & 0x7fffff) == 0){
4248: dest[2] = 0;
4249: }
4250: dest[2] &= 0x800000;
4251: }
4252: /* No Scaling */
4253: else {
4254: rnd_const[1] = 0;
4255: rnd_const[2] = (1<<23);
4256: dsp_add56(rnd_const, dest);
4257:
4258: if (dest[2] == 0) {
4259: dest[1] &= 0xfffffe;
1.1 root 4260: }
1.1.1.4 root 4261: dest[2]=0;
1.1 root 4262: }
4263: }
4264:
4265: /**********************************
4266: * Parallel moves instructions
4267: **********************************/
4268:
1.1.1.6 root 4269: static void dsp_abs_a(void)
1.1 root 4270: {
1.1.1.6 root 4271: Uint32 dest[3], overflowed;
1.1 root 4272:
1.1.1.6 root 4273: dest[0] = dsp_core.registers[DSP_REG_A2];
4274: dest[1] = dsp_core.registers[DSP_REG_A1];
4275: dest[2] = dsp_core.registers[DSP_REG_A0];
4276:
4277: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4278:
4279: dsp_abs56(dest);
4280:
4281: dsp_core.registers[DSP_REG_A2] = dest[0];
4282: dsp_core.registers[DSP_REG_A1] = dest[1];
4283: dsp_core.registers[DSP_REG_A0] = dest[2];
4284:
4285: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4286: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
4287:
4288: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4289: }
4290:
4291: static void dsp_abs_b(void)
4292: {
4293: Uint32 dest[3], overflowed;
1.1 root 4294:
1.1.1.6 root 4295: dest[0] = dsp_core.registers[DSP_REG_B2];
4296: dest[1] = dsp_core.registers[DSP_REG_B1];
4297: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 4298:
4299: overflowed = ((dest[2]==0) && (dest[1]==0) && (dest[0]==0x80));
4300:
4301: dsp_abs56(dest);
4302:
1.1.1.6 root 4303: dsp_core.registers[DSP_REG_B2] = dest[0];
4304: dsp_core.registers[DSP_REG_B1] = dest[1];
4305: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4306:
1.1.1.6 root 4307: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
4308: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
1.1.1.2 root 4309:
1.1.1.6 root 4310: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4311: }
4312:
1.1.1.6 root 4313: static void dsp_adc_x_a(void)
1.1 root 4314: {
1.1.1.6 root 4315: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4316: Uint16 newsr;
1.1 root 4317:
1.1.1.6 root 4318: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4319:
1.1.1.6 root 4320: dest[0] = dsp_core.registers[DSP_REG_A2];
4321: dest[1] = dsp_core.registers[DSP_REG_A1];
4322: dest[2] = dsp_core.registers[DSP_REG_A0];
4323:
4324: source[2] = dsp_core.registers[DSP_REG_X0];
4325: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4326: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4327:
4328: newsr = dsp_add56(source, dest);
4329:
4330: if (curcarry) {
1.1.1.6 root 4331: source[0]=0; source[1]=0; source[2]=1;
1.1 root 4332: newsr |= dsp_add56(source, dest);
4333: }
4334:
1.1.1.6 root 4335: dsp_core.registers[DSP_REG_A2] = dest[0];
4336: dsp_core.registers[DSP_REG_A1] = dest[1];
4337: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4338:
1.1.1.6 root 4339: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4340:
1.1.1.6 root 4341: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4342: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4343: }
4344:
1.1.1.6 root 4345: static void dsp_adc_x_b(void)
1.1 root 4346: {
1.1.1.6 root 4347: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4348: Uint16 newsr;
1.1 root 4349:
1.1.1.6 root 4350: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
4351:
4352: dest[0] = dsp_core.registers[DSP_REG_B2];
4353: dest[1] = dsp_core.registers[DSP_REG_B1];
4354: dest[2] = dsp_core.registers[DSP_REG_B0];
4355:
4356: source[2] = dsp_core.registers[DSP_REG_X0];
4357: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4358: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4359:
4360: newsr = dsp_add56(source, dest);
1.1.1.6 root 4361:
4362: if (curcarry) {
4363: source[0]=0; source[1]=0; source[2]=1;
4364: newsr |= dsp_add56(source, dest);
4365: }
1.1 root 4366:
1.1.1.6 root 4367: dsp_core.registers[DSP_REG_B2] = dest[0];
4368: dsp_core.registers[DSP_REG_B1] = dest[1];
4369: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4370:
1.1.1.6 root 4371: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4372:
1.1.1.6 root 4373: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4374: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4375: }
4376:
1.1.1.6 root 4377: static void dsp_adc_y_a(void)
1.1 root 4378: {
1.1.1.6 root 4379: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4380: Uint16 newsr;
1.1 root 4381:
1.1.1.6 root 4382: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4383:
1.1.1.6 root 4384: dest[0] = dsp_core.registers[DSP_REG_A2];
4385: dest[1] = dsp_core.registers[DSP_REG_A1];
4386: dest[2] = dsp_core.registers[DSP_REG_A0];
4387:
4388: source[2] = dsp_core.registers[DSP_REG_Y0];
4389: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4390: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4391:
1.1.1.6 root 4392: newsr = dsp_add56(source, dest);
4393:
4394: if (curcarry) {
4395: source[0]=0; source[1]=0; source[2]=1;
4396: newsr |= dsp_add56(source, dest);
4397: }
1.1 root 4398:
1.1.1.6 root 4399: dsp_core.registers[DSP_REG_A2] = dest[0];
4400: dsp_core.registers[DSP_REG_A1] = dest[1];
4401: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4402:
1.1.1.6 root 4403: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4404:
1.1.1.6 root 4405: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4406: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4407: }
4408:
1.1.1.6 root 4409: static void dsp_adc_y_b(void)
1.1 root 4410: {
1.1.1.6 root 4411: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 4412: Uint16 newsr;
1.1 root 4413:
1.1.1.6 root 4414: curcarry = (dsp_core.registers[DSP_REG_SR]>>DSP_SR_C) & 1;
1.1 root 4415:
1.1.1.6 root 4416: dest[0] = dsp_core.registers[DSP_REG_B2];
4417: dest[1] = dsp_core.registers[DSP_REG_B1];
4418: dest[2] = dsp_core.registers[DSP_REG_B0];
4419:
4420: source[2] = dsp_core.registers[DSP_REG_Y0];
4421: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4422: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4423:
1.1.1.6 root 4424: newsr = dsp_add56(source, dest);
4425:
4426: if (curcarry) {
4427: source[0]=0; source[1]=0; source[2]=1;
4428: newsr |= dsp_add56(source, dest);
4429: }
1.1 root 4430:
1.1.1.6 root 4431: dsp_core.registers[DSP_REG_B2] = dest[0];
4432: dsp_core.registers[DSP_REG_B1] = dest[1];
4433: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4434:
1.1.1.6 root 4435: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4436:
1.1.1.6 root 4437: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4438: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4439: }
4440:
1.1.1.6 root 4441: static void dsp_add_b_a(void)
1.1 root 4442: {
1.1.1.6 root 4443: Uint32 source[3], dest[3];
4444: Uint16 newsr;
1.1 root 4445:
1.1.1.6 root 4446: dest[0] = dsp_core.registers[DSP_REG_A2];
4447: dest[1] = dsp_core.registers[DSP_REG_A1];
4448: dest[2] = dsp_core.registers[DSP_REG_A0];
4449:
4450: source[0] = dsp_core.registers[DSP_REG_B2];
4451: source[1] = dsp_core.registers[DSP_REG_B1];
4452: source[2] = dsp_core.registers[DSP_REG_B0];
4453:
4454: newsr = dsp_add56(source, dest);
4455:
4456: dsp_core.registers[DSP_REG_A2] = dest[0];
4457: dsp_core.registers[DSP_REG_A1] = dest[1];
4458: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4459:
1.1.1.6 root 4460: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4461:
1.1.1.6 root 4462: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4463: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4464: }
4465:
1.1.1.6 root 4466: static void dsp_add_a_b(void)
1.1 root 4467: {
1.1.1.6 root 4468: Uint32 source[3], dest[3];
1.1.1.2 root 4469: Uint16 newsr;
1.1 root 4470:
1.1.1.6 root 4471: dest[0] = dsp_core.registers[DSP_REG_B2];
4472: dest[1] = dsp_core.registers[DSP_REG_B1];
4473: dest[2] = dsp_core.registers[DSP_REG_B0];
4474:
4475: source[0] = dsp_core.registers[DSP_REG_A2];
4476: source[1] = dsp_core.registers[DSP_REG_A1];
4477: source[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 4478:
1.1.1.6 root 4479: newsr = dsp_add56(source, dest);
1.1 root 4480:
1.1.1.6 root 4481: dsp_core.registers[DSP_REG_B2] = dest[0];
4482: dsp_core.registers[DSP_REG_B1] = dest[1];
4483: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4484:
1.1.1.6 root 4485: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4486:
1.1.1.6 root 4487: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4488: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4489: }
4490:
1.1.1.6 root 4491: static void dsp_add_x_a(void)
1.1 root 4492: {
1.1.1.6 root 4493: Uint32 source[3], dest[3];
4494: Uint16 newsr;
1.1 root 4495:
1.1.1.6 root 4496: dest[0] = dsp_core.registers[DSP_REG_A2];
4497: dest[1] = dsp_core.registers[DSP_REG_A1];
4498: dest[2] = dsp_core.registers[DSP_REG_A0];
4499:
4500: source[1] = dsp_core.registers[DSP_REG_X1];
4501: source[2] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4502: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4503:
1.1.1.6 root 4504: newsr = dsp_add56(source, dest);
1.1 root 4505:
1.1.1.6 root 4506: dsp_core.registers[DSP_REG_A2] = dest[0];
4507: dsp_core.registers[DSP_REG_A1] = dest[1];
4508: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4509:
1.1.1.6 root 4510: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4511:
1.1.1.6 root 4512: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4513: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4514: }
4515:
1.1.1.6 root 4516: static void dsp_add_x_b(void)
1.1 root 4517: {
1.1.1.6 root 4518: Uint32 source[3], dest[3];
4519: Uint16 newsr;
1.1 root 4520:
1.1.1.6 root 4521: dest[0] = dsp_core.registers[DSP_REG_B2];
4522: dest[1] = dsp_core.registers[DSP_REG_B1];
4523: dest[2] = dsp_core.registers[DSP_REG_B0];
4524:
4525: source[1] = dsp_core.registers[DSP_REG_X1];
4526: source[2] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4527: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4528:
4529: newsr = dsp_add56(source, dest);
1.1 root 4530:
1.1.1.6 root 4531: dsp_core.registers[DSP_REG_B2] = dest[0];
4532: dsp_core.registers[DSP_REG_B1] = dest[1];
4533: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4534:
1.1.1.6 root 4535: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4536:
4537: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4538: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4539: }
4540:
1.1.1.6 root 4541: static void dsp_add_y_a(void)
1.1 root 4542: {
1.1.1.6 root 4543: Uint32 source[3], dest[3];
1.1.1.2 root 4544: Uint16 newsr;
1.1 root 4545:
1.1.1.6 root 4546: dest[0] = dsp_core.registers[DSP_REG_A2];
4547: dest[1] = dsp_core.registers[DSP_REG_A1];
4548: dest[2] = dsp_core.registers[DSP_REG_A0];
4549:
4550: source[1] = dsp_core.registers[DSP_REG_Y1];
4551: source[2] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4552: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4553:
1.1.1.6 root 4554: newsr = dsp_add56(source, dest);
1.1 root 4555:
1.1.1.6 root 4556: dsp_core.registers[DSP_REG_A2] = dest[0];
4557: dsp_core.registers[DSP_REG_A1] = dest[1];
4558: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4559:
1.1.1.6 root 4560: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4561:
4562: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4563: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4564: }
4565:
1.1.1.6 root 4566: static void dsp_add_y_b(void)
1.1 root 4567: {
1.1.1.6 root 4568: Uint32 source[3], dest[3];
1.1.1.2 root 4569: Uint16 newsr;
1.1 root 4570:
1.1.1.6 root 4571: dest[0] = dsp_core.registers[DSP_REG_B2];
4572: dest[1] = dsp_core.registers[DSP_REG_B1];
4573: dest[2] = dsp_core.registers[DSP_REG_B0];
4574:
4575: source[1] = dsp_core.registers[DSP_REG_Y1];
4576: source[2] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4577: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4578:
1.1.1.6 root 4579: newsr = dsp_add56(source, dest);
1.1 root 4580:
1.1.1.6 root 4581: dsp_core.registers[DSP_REG_B2] = dest[0];
4582: dsp_core.registers[DSP_REG_B1] = dest[1];
4583: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4584:
1.1.1.6 root 4585: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4586:
1.1.1.6 root 4587: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4588: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4589: }
4590:
1.1.1.6 root 4591: static void dsp_add_x0_a(void)
1.1 root 4592: {
1.1.1.6 root 4593: Uint32 source[3], dest[3];
4594: Uint16 newsr;
1.1 root 4595:
1.1.1.6 root 4596: dest[0] = dsp_core.registers[DSP_REG_A2];
4597: dest[1] = dsp_core.registers[DSP_REG_A1];
4598: dest[2] = dsp_core.registers[DSP_REG_A0];
4599:
4600: source[2] = 0;
4601: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4602: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4603:
4604: newsr = dsp_add56(source, dest);
4605:
4606: dsp_core.registers[DSP_REG_A2] = dest[0];
4607: dsp_core.registers[DSP_REG_A1] = dest[1];
4608: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4609:
1.1.1.6 root 4610: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4611:
1.1.1.6 root 4612: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4613: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4614: }
4615:
1.1.1.6 root 4616: static void dsp_add_x0_b(void)
1.1 root 4617: {
1.1.1.6 root 4618: Uint32 source[3], dest[3];
4619: Uint16 newsr;
4620:
4621: dest[0] = dsp_core.registers[DSP_REG_B2];
4622: dest[1] = dsp_core.registers[DSP_REG_B1];
4623: dest[2] = dsp_core.registers[DSP_REG_B0];
4624:
4625: source[2] = 0;
4626: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 4627: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4628:
1.1.1.6 root 4629: newsr = dsp_add56(source, dest);
1.1 root 4630:
1.1.1.6 root 4631: dsp_core.registers[DSP_REG_B2] = dest[0];
4632: dsp_core.registers[DSP_REG_B1] = dest[1];
4633: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4634:
1.1.1.6 root 4635: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4636:
1.1.1.6 root 4637: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4638: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4639: }
4640:
1.1.1.6 root 4641: static void dsp_add_y0_a(void)
1.1 root 4642: {
1.1.1.6 root 4643: Uint32 source[3], dest[3];
4644: Uint16 newsr;
1.1 root 4645:
1.1.1.6 root 4646: dest[0] = dsp_core.registers[DSP_REG_A2];
4647: dest[1] = dsp_core.registers[DSP_REG_A1];
4648: dest[2] = dsp_core.registers[DSP_REG_A0];
4649:
4650: source[2] = 0;
4651: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4652: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4653:
1.1.1.6 root 4654: newsr = dsp_add56(source, dest);
4655:
4656: dsp_core.registers[DSP_REG_A2] = dest[0];
4657: dsp_core.registers[DSP_REG_A1] = dest[1];
4658: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4659:
1.1.1.6 root 4660: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4661:
1.1.1.6 root 4662: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4663: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4664: }
4665:
1.1.1.6 root 4666: static void dsp_add_y0_b(void)
1.1 root 4667: {
1.1.1.6 root 4668: Uint32 source[3], dest[3];
1.1.1.2 root 4669: Uint16 newsr;
1.1 root 4670:
1.1.1.6 root 4671: dest[0] = dsp_core.registers[DSP_REG_B2];
4672: dest[1] = dsp_core.registers[DSP_REG_B1];
4673: dest[2] = dsp_core.registers[DSP_REG_B0];
4674:
4675: source[2] = 0;
4676: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 4677: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4678:
4679: newsr = dsp_add56(source, dest);
4680:
1.1.1.6 root 4681: dsp_core.registers[DSP_REG_B2] = dest[0];
4682: dsp_core.registers[DSP_REG_B1] = dest[1];
4683: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4684:
1.1.1.6 root 4685: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4686:
1.1.1.6 root 4687: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4688: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4689: }
4690:
1.1.1.6 root 4691: static void dsp_add_x1_a(void)
1.1 root 4692: {
1.1.1.6 root 4693: Uint32 source[3], dest[3];
1.1.1.2 root 4694: Uint16 newsr;
1.1 root 4695:
1.1.1.6 root 4696: dest[0] = dsp_core.registers[DSP_REG_A2];
4697: dest[1] = dsp_core.registers[DSP_REG_A1];
4698: dest[2] = dsp_core.registers[DSP_REG_A0];
4699:
4700: source[2] = 0;
4701: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4702: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4703:
4704: newsr = dsp_add56(source, dest);
4705:
1.1.1.6 root 4706: dsp_core.registers[DSP_REG_A2] = dest[0];
4707: dsp_core.registers[DSP_REG_A1] = dest[1];
4708: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 4709:
1.1.1.6 root 4710: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4711:
1.1.1.6 root 4712: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4713: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4714: }
4715:
1.1.1.6 root 4716: static void dsp_add_x1_b(void)
1.1 root 4717: {
1.1.1.6 root 4718: Uint32 source[3], dest[3];
4719: Uint16 newsr;
4720:
4721: dest[0] = dsp_core.registers[DSP_REG_B2];
4722: dest[1] = dsp_core.registers[DSP_REG_B1];
4723: dest[2] = dsp_core.registers[DSP_REG_B0];
4724:
4725: source[2] = 0;
4726: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 4727: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 4728:
4729: newsr = dsp_add56(source, dest);
4730:
4731: dsp_core.registers[DSP_REG_B2] = dest[0];
4732: dsp_core.registers[DSP_REG_B1] = dest[1];
4733: dsp_core.registers[DSP_REG_B0] = dest[2];
4734:
4735: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4736:
4737: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4738: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4739: }
4740:
1.1.1.6 root 4741: static void dsp_add_y1_a(void)
1.1 root 4742: {
1.1.1.6 root 4743: Uint32 source[3], dest[3];
4744: Uint16 newsr;
1.1 root 4745:
1.1.1.6 root 4746: dest[0] = dsp_core.registers[DSP_REG_A2];
4747: dest[1] = dsp_core.registers[DSP_REG_A1];
4748: dest[2] = dsp_core.registers[DSP_REG_A0];
4749:
4750: source[2] = 0;
4751: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4752: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4753:
1.1.1.6 root 4754: newsr = dsp_add56(source, dest);
1.1 root 4755:
1.1.1.6 root 4756: dsp_core.registers[DSP_REG_A2] = dest[0];
4757: dsp_core.registers[DSP_REG_A1] = dest[1];
4758: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4759:
1.1.1.6 root 4760: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4761:
1.1.1.6 root 4762: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4763: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4764: }
4765:
1.1.1.6 root 4766: static void dsp_add_y1_b(void)
1.1 root 4767: {
1.1.1.6 root 4768: Uint32 source[3], dest[3];
4769: Uint16 newsr;
1.1 root 4770:
1.1.1.6 root 4771: dest[0] = dsp_core.registers[DSP_REG_B2];
4772: dest[1] = dsp_core.registers[DSP_REG_B1];
4773: dest[2] = dsp_core.registers[DSP_REG_B0];
4774:
4775: source[2] = 0;
4776: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 4777: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1 root 4778:
1.1.1.6 root 4779: newsr = dsp_add56(source, dest);
1.1 root 4780:
1.1.1.6 root 4781: dsp_core.registers[DSP_REG_B2] = dest[0];
4782: dsp_core.registers[DSP_REG_B1] = dest[1];
4783: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4784:
1.1.1.6 root 4785: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4786:
1.1.1.6 root 4787: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4788: dsp_core.registers[DSP_REG_SR] |= newsr;
4789: }
1.1 root 4790:
1.1.1.6 root 4791: static void dsp_addl_b_a(void)
4792: {
4793: Uint32 source[3], dest[3];
4794: Uint16 newsr;
1.1.1.2 root 4795:
1.1.1.6 root 4796: dest[0] = dsp_core.registers[DSP_REG_A2];
4797: dest[1] = dsp_core.registers[DSP_REG_A1];
4798: dest[2] = dsp_core.registers[DSP_REG_A0];
4799: newsr = dsp_asl56(dest);
1.1 root 4800:
1.1.1.6 root 4801: source[0] = dsp_core.registers[DSP_REG_B2];
4802: source[1] = dsp_core.registers[DSP_REG_B1];
4803: source[2] = dsp_core.registers[DSP_REG_B0];
4804: newsr |= dsp_add56(source, dest);
1.1 root 4805:
1.1.1.6 root 4806: dsp_core.registers[DSP_REG_A2] = dest[0];
4807: dsp_core.registers[DSP_REG_A1] = dest[1];
4808: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4809:
1.1.1.6 root 4810: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4811:
1.1.1.6 root 4812: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4813: dsp_core.registers[DSP_REG_SR] |= newsr;
4814: }
1.1 root 4815:
1.1.1.6 root 4816: static void dsp_addl_a_b(void)
4817: {
4818: Uint32 source[3], dest[3];
4819: Uint16 newsr;
1.1 root 4820:
1.1.1.6 root 4821: dest[0] = dsp_core.registers[DSP_REG_B2];
4822: dest[1] = dsp_core.registers[DSP_REG_B1];
4823: dest[2] = dsp_core.registers[DSP_REG_B0];
4824: newsr = dsp_asl56(dest);
1.1 root 4825:
1.1.1.6 root 4826: source[0] = dsp_core.registers[DSP_REG_A2];
4827: source[1] = dsp_core.registers[DSP_REG_A1];
4828: source[2] = dsp_core.registers[DSP_REG_A0];
4829: newsr |= dsp_add56(source, dest);
4830:
4831: dsp_core.registers[DSP_REG_B2] = dest[0];
4832: dsp_core.registers[DSP_REG_B1] = dest[1];
4833: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4834:
1.1.1.6 root 4835: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1.1.2 root 4836:
1.1.1.6 root 4837: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4838: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4839: }
4840:
1.1.1.6 root 4841: static void dsp_addr_b_a(void)
1.1 root 4842: {
1.1.1.6 root 4843: Uint32 source[3], dest[3];
4844: Uint16 newsr;
4845:
4846: dest[0] = dsp_core.registers[DSP_REG_A2];
4847: dest[1] = dsp_core.registers[DSP_REG_A1];
4848: dest[2] = dsp_core.registers[DSP_REG_A0];
4849: newsr = dsp_asr56(dest);
4850:
4851: source[0] = dsp_core.registers[DSP_REG_B2];
4852: source[1] = dsp_core.registers[DSP_REG_B1];
4853: source[2] = dsp_core.registers[DSP_REG_B0];
4854: newsr |= dsp_add56(source, dest);
4855:
4856: dsp_core.registers[DSP_REG_A2] = dest[0];
4857: dsp_core.registers[DSP_REG_A1] = dest[1];
4858: dsp_core.registers[DSP_REG_A0] = dest[2];
4859:
4860: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
4861:
4862: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4863: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4864: }
4865:
1.1.1.6 root 4866: static void dsp_addr_a_b(void)
1.1 root 4867: {
1.1.1.6 root 4868: Uint32 source[3], dest[3];
4869: Uint16 newsr;
4870:
4871: dest[0] = dsp_core.registers[DSP_REG_B2];
4872: dest[1] = dsp_core.registers[DSP_REG_B1];
4873: dest[2] = dsp_core.registers[DSP_REG_B0];
4874: newsr = dsp_asr56(dest);
4875:
4876: source[0] = dsp_core.registers[DSP_REG_A2];
4877: source[1] = dsp_core.registers[DSP_REG_A1];
4878: source[2] = dsp_core.registers[DSP_REG_A0];
4879: newsr |= dsp_add56(source, dest);
1.1 root 4880:
1.1.1.6 root 4881: dsp_core.registers[DSP_REG_B2] = dest[0];
4882: dsp_core.registers[DSP_REG_B1] = dest[1];
4883: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1 root 4884:
1.1.1.6 root 4885: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4886:
1.1.1.6 root 4887: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
4888: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 4889: }
4890:
1.1.1.6 root 4891: static void dsp_and_x0_a(void)
1.1 root 4892: {
1.1.1.6 root 4893: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X0];
1.1 root 4894:
1.1.1.6 root 4895: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4896: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4897: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4898: }
1.1 root 4899:
1.1.1.6 root 4900: static void dsp_and_x0_b(void)
4901: {
4902: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X0];
1.1 root 4903:
1.1.1.6 root 4904: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4905: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4906: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
1.1 root 4907: }
4908:
1.1.1.6 root 4909: static void dsp_and_y0_a(void)
1.1 root 4910: {
1.1.1.6 root 4911: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y0];
1.1 root 4912:
1.1.1.6 root 4913: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4914: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4915: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4916: }
1.1 root 4917:
1.1.1.6 root 4918: static void dsp_and_y0_b(void)
4919: {
4920: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y0];
1.1 root 4921:
1.1.1.6 root 4922: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4923: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4924: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
4925: }
1.1 root 4926:
1.1.1.6 root 4927: static void dsp_and_x1_a(void)
4928: {
4929: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_X1];
1.1.1.2 root 4930:
1.1.1.6 root 4931: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4932: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4933: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
1.1 root 4934: }
4935:
1.1.1.6 root 4936: static void dsp_and_x1_b(void)
1.1 root 4937: {
1.1.1.6 root 4938: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_X1];
4939:
4940: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4941: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4942: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
4943: }
1.1 root 4944:
1.1.1.6 root 4945: static void dsp_and_y1_a(void)
4946: {
4947: dsp_core.registers[DSP_REG_A1] &= dsp_core.registers[DSP_REG_Y1];
1.1 root 4948:
1.1.1.6 root 4949: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4950: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
4951: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
4952: }
1.1 root 4953:
1.1.1.6 root 4954: static void dsp_and_y1_b(void)
4955: {
4956: dsp_core.registers[DSP_REG_B1] &= dsp_core.registers[DSP_REG_Y1];
1.1.1.2 root 4957:
1.1.1.6 root 4958: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
4959: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
4960: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
1.1 root 4961: }
4962:
1.1.1.7 root 4963: static void dsp_asl_a(void)
1.1 root 4964: {
1.1.1.6 root 4965: Uint32 dest[3];
4966: Uint16 newsr;
1.1 root 4967:
1.1.1.6 root 4968: dest[0] = dsp_core.registers[DSP_REG_A2];
4969: dest[1] = dsp_core.registers[DSP_REG_A1];
4970: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 4971:
1.1.1.6 root 4972: newsr = dsp_asl56(dest);
4973:
4974: dsp_core.registers[DSP_REG_A2] = dest[0];
4975: dsp_core.registers[DSP_REG_A1] = dest[1];
4976: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1 root 4977:
1.1.1.6 root 4978: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
4979: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1.1.2 root 4980:
1.1.1.6 root 4981: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 4982: }
4983:
1.1.1.7 root 4984: static void dsp_asl_b(void)
1.1 root 4985: {
1.1.1.6 root 4986: Uint32 dest[3];
1.1.1.2 root 4987: Uint16 newsr;
1.1 root 4988:
1.1.1.6 root 4989: dest[0] = dsp_core.registers[DSP_REG_B2];
4990: dest[1] = dsp_core.registers[DSP_REG_B1];
4991: dest[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 4992:
1.1.1.6 root 4993: newsr = dsp_asl56(dest);
1.1 root 4994:
1.1.1.6 root 4995: dsp_core.registers[DSP_REG_B2] = dest[0];
4996: dsp_core.registers[DSP_REG_B1] = dest[1];
4997: dsp_core.registers[DSP_REG_B0] = dest[2];
1.1.1.2 root 4998:
1.1.1.6 root 4999: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5000: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 5001:
1.1.1.6 root 5002: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 5003: }
5004:
1.1.1.7 root 5005: static void dsp_asr_a(void)
1.1 root 5006: {
1.1.1.6 root 5007: Uint32 dest[3];
5008: Uint16 newsr;
5009:
5010: dest[0] = dsp_core.registers[DSP_REG_A2];
5011: dest[1] = dsp_core.registers[DSP_REG_A1];
5012: dest[2] = dsp_core.registers[DSP_REG_A0];
5013:
5014: newsr = dsp_asr56(dest);
5015:
5016: dsp_core.registers[DSP_REG_A2] = dest[0];
5017: dsp_core.registers[DSP_REG_A1] = dest[1];
5018: dsp_core.registers[DSP_REG_A0] = dest[2];
5019:
5020: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5021: dsp_core.registers[DSP_REG_SR] |= newsr;
5022:
5023: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5024: }
5025:
1.1.1.7 root 5026: static void dsp_asr_b(void)
1.1.1.6 root 5027: {
5028: Uint32 dest[3];
5029: Uint16 newsr;
5030:
5031: dest[0] = dsp_core.registers[DSP_REG_B2];
5032: dest[1] = dsp_core.registers[DSP_REG_B1];
5033: dest[2] = dsp_core.registers[DSP_REG_B0];
5034:
5035: newsr = dsp_asr56(dest);
5036:
5037: dsp_core.registers[DSP_REG_B2] = dest[0];
5038: dsp_core.registers[DSP_REG_B1] = dest[1];
5039: dsp_core.registers[DSP_REG_B0] = dest[2];
5040:
5041: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_V));
5042: dsp_core.registers[DSP_REG_SR] |= newsr;
5043:
5044: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5045: }
5046:
5047: static void dsp_clr_a(void)
5048: {
1.1.1.7 root 5049: dsp_core.registers[DSP_REG_A2] = 0;
5050: dsp_core.registers[DSP_REG_A1] = 0;
5051: dsp_core.registers[DSP_REG_A0] = 0;
1.1.1.6 root 5052:
5053: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5054: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5055: }
5056:
5057: static void dsp_clr_b(void)
5058: {
1.1.1.7 root 5059: dsp_core.registers[DSP_REG_B2] = 0;
5060: dsp_core.registers[DSP_REG_B1] = 0;
5061: dsp_core.registers[DSP_REG_B0] = 0;
1.1.1.6 root 5062:
5063: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_E)|(1<<DSP_SR_N)|(1<<DSP_SR_V));
5064: dsp_core.registers[DSP_REG_SR] |= (1<<DSP_SR_U)|(1<<DSP_SR_Z);
5065: }
5066:
5067: static void dsp_cmp_b_a(void)
5068: {
5069: Uint32 source[3], dest[3];
5070: Uint16 newsr;
5071:
5072: dest[0] = dsp_core.registers[DSP_REG_A2];
5073: dest[1] = dsp_core.registers[DSP_REG_A1];
5074: dest[2] = dsp_core.registers[DSP_REG_A0];
5075:
5076: source[0] = dsp_core.registers[DSP_REG_B2];
5077: source[1] = dsp_core.registers[DSP_REG_B1];
5078: source[2] = dsp_core.registers[DSP_REG_B0];
5079:
5080: newsr = dsp_sub56(source, dest);
5081:
5082: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5083:
5084: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5085: dsp_core.registers[DSP_REG_SR] |= newsr;
5086: }
5087:
5088: static void dsp_cmp_a_b(void)
5089: {
5090: Uint32 source[3], dest[3];
5091: Uint16 newsr;
5092:
5093: dest[0] = dsp_core.registers[DSP_REG_B2];
5094: dest[1] = dsp_core.registers[DSP_REG_B1];
5095: dest[2] = dsp_core.registers[DSP_REG_B0];
5096:
5097: source[0] = dsp_core.registers[DSP_REG_A2];
5098: source[1] = dsp_core.registers[DSP_REG_A1];
5099: source[2] = dsp_core.registers[DSP_REG_A0];
5100:
5101: newsr = dsp_sub56(source, dest);
5102:
5103: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5104:
5105: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5106: dsp_core.registers[DSP_REG_SR] |= newsr;
5107: }
5108:
5109: static void dsp_cmp_x0_a(void)
5110: {
5111: Uint32 source[3], dest[3];
5112: Uint16 newsr;
5113:
5114: dest[2] = dsp_core.registers[DSP_REG_A0];
5115: dest[1] = dsp_core.registers[DSP_REG_A1];
5116: dest[0] = dsp_core.registers[DSP_REG_A2];
5117:
5118: source[2] = 0;
5119: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5120: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5121:
5122: newsr = dsp_sub56(source, dest);
5123:
5124: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5125:
5126: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5127: dsp_core.registers[DSP_REG_SR] |= newsr;
5128: }
5129:
5130: static void dsp_cmp_x0_b(void)
5131: {
5132: Uint32 source[3], dest[3];
5133: Uint16 newsr;
5134:
5135: dest[0] = dsp_core.registers[DSP_REG_B2];
5136: dest[1] = dsp_core.registers[DSP_REG_B1];
5137: dest[2] = dsp_core.registers[DSP_REG_B0];
5138:
5139: source[2] = 0;
5140: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5141: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5142:
5143: newsr = dsp_sub56(source, dest);
5144:
5145: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5146:
5147: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5148: dsp_core.registers[DSP_REG_SR] |= newsr;
5149: }
5150:
5151: static void dsp_cmp_y0_a(void)
5152: {
5153: Uint32 source[3], dest[3];
5154: Uint16 newsr;
5155:
5156: dest[2] = dsp_core.registers[DSP_REG_A0];
5157: dest[1] = dsp_core.registers[DSP_REG_A1];
5158: dest[0] = dsp_core.registers[DSP_REG_A2];
5159:
5160: source[2] = 0;
5161: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5162: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5163:
5164: newsr = dsp_sub56(source, dest);
5165:
5166: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5167:
5168: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5169: dsp_core.registers[DSP_REG_SR] |= newsr;
5170: }
5171:
5172: static void dsp_cmp_y0_b(void)
5173: {
5174: Uint32 source[3], dest[3];
5175: Uint16 newsr;
5176:
5177: dest[0] = dsp_core.registers[DSP_REG_B2];
5178: dest[1] = dsp_core.registers[DSP_REG_B1];
5179: dest[2] = dsp_core.registers[DSP_REG_B0];
5180:
5181: source[2] = 0;
5182: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5183: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5184:
5185: newsr = dsp_sub56(source, dest);
5186:
5187: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5188:
5189: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5190: dsp_core.registers[DSP_REG_SR] |= newsr;
5191: }
5192: static void dsp_cmp_x1_a(void)
5193: {
5194: Uint32 source[3], dest[3];
5195: Uint16 newsr;
5196:
5197: dest[2] = dsp_core.registers[DSP_REG_A0];
5198: dest[1] = dsp_core.registers[DSP_REG_A1];
5199: dest[0] = dsp_core.registers[DSP_REG_A2];
5200:
5201: source[2] = 0;
5202: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5203: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5204:
5205: newsr = dsp_sub56(source, dest);
5206:
5207: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5208:
5209: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5210: dsp_core.registers[DSP_REG_SR] |= newsr;
5211: }
5212:
5213: static void dsp_cmp_x1_b(void)
5214: {
5215: Uint32 source[3], dest[3];
5216: Uint16 newsr;
5217:
5218: dest[0] = dsp_core.registers[DSP_REG_B2];
5219: dest[1] = dsp_core.registers[DSP_REG_B1];
5220: dest[2] = dsp_core.registers[DSP_REG_B0];
5221:
5222: source[2] = 0;
5223: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5224: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5225:
5226: newsr = dsp_sub56(source, dest);
5227:
5228: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5229:
5230: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5231: dsp_core.registers[DSP_REG_SR] |= newsr;
5232: }
5233:
5234: static void dsp_cmp_y1_a(void)
5235: {
5236: Uint32 source[3], dest[3];
5237: Uint16 newsr;
5238:
5239: dest[2] = dsp_core.registers[DSP_REG_A0];
5240: dest[1] = dsp_core.registers[DSP_REG_A1];
5241: dest[0] = dsp_core.registers[DSP_REG_A2];
5242:
5243: source[2] = 0;
5244: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5245: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5246:
5247: newsr = dsp_sub56(source, dest);
5248:
5249: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5250:
5251: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5252: dsp_core.registers[DSP_REG_SR] |= newsr;
5253: }
5254:
5255: static void dsp_cmp_y1_b(void)
5256: {
5257: Uint32 source[3], dest[3];
5258: Uint16 newsr;
5259:
5260: dest[0] = dsp_core.registers[DSP_REG_B2];
5261: dest[1] = dsp_core.registers[DSP_REG_B1];
5262: dest[2] = dsp_core.registers[DSP_REG_B0];
5263:
5264: source[2] = 0;
5265: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5266: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5267:
5268: newsr = dsp_sub56(source, dest);
5269:
5270: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5271:
5272: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5273: dsp_core.registers[DSP_REG_SR] |= newsr;
5274: }
5275:
5276: static void dsp_cmpm_b_a(void)
5277: {
5278: Uint32 source[3], dest[3];
5279: Uint16 newsr;
5280:
5281: dest[0] = dsp_core.registers[DSP_REG_A2];
5282: dest[1] = dsp_core.registers[DSP_REG_A1];
5283: dest[2] = dsp_core.registers[DSP_REG_A0];
5284: dsp_abs56(dest);
5285:
5286: source[0] = dsp_core.registers[DSP_REG_B2];
5287: source[1] = dsp_core.registers[DSP_REG_B1];
5288: source[2] = dsp_core.registers[DSP_REG_B0];
5289: dsp_abs56(source);
5290:
5291: newsr = dsp_sub56(source, dest);
5292:
5293: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5294:
5295: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5296: dsp_core.registers[DSP_REG_SR] |= newsr;
5297: }
5298:
5299: static void dsp_cmpm_a_b(void)
5300: {
5301: Uint32 source[3], dest[3];
5302: Uint16 newsr;
5303:
5304: dest[0] = dsp_core.registers[DSP_REG_B2];
5305: dest[1] = dsp_core.registers[DSP_REG_B1];
5306: dest[2] = dsp_core.registers[DSP_REG_B0];
5307: dsp_abs56(dest);
5308:
5309: source[0] = dsp_core.registers[DSP_REG_A2];
5310: source[1] = dsp_core.registers[DSP_REG_A1];
5311: source[2] = dsp_core.registers[DSP_REG_A0];
5312: dsp_abs56(source);
5313:
5314: newsr = dsp_sub56(source, dest);
5315:
5316: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5317:
5318: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5319: dsp_core.registers[DSP_REG_SR] |= newsr;
5320: }
5321:
5322: static void dsp_cmpm_x0_a(void)
5323: {
5324: Uint32 source[3], dest[3];
5325: Uint16 newsr;
5326:
5327: dest[2] = dsp_core.registers[DSP_REG_A0];
5328: dest[1] = dsp_core.registers[DSP_REG_A1];
5329: dest[0] = dsp_core.registers[DSP_REG_A2];
5330: dsp_abs56(dest);
5331:
5332: source[2] = 0;
5333: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5334: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5335: dsp_abs56(source);
5336:
5337: newsr = dsp_sub56(source, dest);
5338:
5339: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5340:
5341: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5342: dsp_core.registers[DSP_REG_SR] |= newsr;
5343: }
5344:
5345: static void dsp_cmpm_x0_b(void)
5346: {
5347: Uint32 source[3], dest[3];
5348: Uint16 newsr;
5349:
5350: dest[0] = dsp_core.registers[DSP_REG_B2];
5351: dest[1] = dsp_core.registers[DSP_REG_B1];
5352: dest[2] = dsp_core.registers[DSP_REG_B0];
5353: dsp_abs56(dest);
5354:
5355: source[2] = 0;
5356: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 5357: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5358: dsp_abs56(source);
5359:
5360: newsr = dsp_sub56(source, dest);
5361:
5362: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5363:
5364: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5365: dsp_core.registers[DSP_REG_SR] |= newsr;
5366: }
5367:
5368: static void dsp_cmpm_y0_a(void)
5369: {
5370: Uint32 source[3], dest[3];
5371: Uint16 newsr;
5372:
5373: dest[2] = dsp_core.registers[DSP_REG_A0];
5374: dest[1] = dsp_core.registers[DSP_REG_A1];
5375: dest[0] = dsp_core.registers[DSP_REG_A2];
5376: dsp_abs56(dest);
5377:
5378: source[2] = 0;
5379: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5380: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5381: dsp_abs56(source);
5382:
5383: newsr = dsp_sub56(source, dest);
5384:
5385: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5386:
5387: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5388: dsp_core.registers[DSP_REG_SR] |= newsr;
5389: }
5390:
5391: static void dsp_cmpm_y0_b(void)
5392: {
5393: Uint32 source[3], dest[3];
5394: Uint16 newsr;
5395:
5396: dest[0] = dsp_core.registers[DSP_REG_B2];
5397: dest[1] = dsp_core.registers[DSP_REG_B1];
5398: dest[2] = dsp_core.registers[DSP_REG_B0];
5399: dsp_abs56(dest);
5400:
5401: source[2] = 0;
5402: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 5403: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5404: dsp_abs56(source);
5405:
5406: newsr = dsp_sub56(source, dest);
5407:
5408: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5409:
5410: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5411: dsp_core.registers[DSP_REG_SR] |= newsr;
5412: }
5413:
5414: static void dsp_cmpm_x1_a(void)
5415: {
5416: Uint32 source[3], dest[3];
5417: Uint16 newsr;
5418:
5419: dest[2] = dsp_core.registers[DSP_REG_A0];
5420: dest[1] = dsp_core.registers[DSP_REG_A1];
5421: dest[0] = dsp_core.registers[DSP_REG_A2];
5422: dsp_abs56(dest);
5423:
5424: source[2] = 0;
5425: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5426: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5427: dsp_abs56(source);
5428:
5429: newsr = dsp_sub56(source, dest);
5430:
5431: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5432:
5433: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5434: dsp_core.registers[DSP_REG_SR] |= newsr;
5435: }
5436:
5437: static void dsp_cmpm_x1_b(void)
5438: {
5439: Uint32 source[3], dest[3];
5440: Uint16 newsr;
5441:
5442: dest[0] = dsp_core.registers[DSP_REG_B2];
5443: dest[1] = dsp_core.registers[DSP_REG_B1];
5444: dest[2] = dsp_core.registers[DSP_REG_B0];
5445: dsp_abs56(dest);
5446:
5447: source[2] = 0;
5448: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 5449: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5450: dsp_abs56(source);
5451:
5452: newsr = dsp_sub56(source, dest);
5453:
5454: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5455:
5456: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5457: dsp_core.registers[DSP_REG_SR] |= newsr;
5458: }
5459:
5460: static void dsp_cmpm_y1_a(void)
5461: {
5462: Uint32 source[3], dest[3];
5463: Uint16 newsr;
5464:
5465: dest[2] = dsp_core.registers[DSP_REG_A0];
5466: dest[1] = dsp_core.registers[DSP_REG_A1];
5467: dest[0] = dsp_core.registers[DSP_REG_A2];
5468: dsp_abs56(dest);
5469:
5470: source[2] = 0;
5471: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5472: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5473: dsp_abs56(source);
5474:
5475: newsr = dsp_sub56(source, dest);
5476:
5477: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5478:
5479: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5480: dsp_core.registers[DSP_REG_SR] |= newsr;
5481: }
5482:
5483: static void dsp_cmpm_y1_b(void)
5484: {
5485: Uint32 source[3], dest[3];
5486: Uint16 newsr;
5487:
5488: dest[0] = dsp_core.registers[DSP_REG_B2];
5489: dest[1] = dsp_core.registers[DSP_REG_B1];
5490: dest[2] = dsp_core.registers[DSP_REG_B0];
5491: dsp_abs56(dest);
5492:
5493: source[2] = 0;
5494: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 5495: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 5496: dsp_abs56(source);
5497:
5498: newsr = dsp_sub56(source, dest);
5499:
5500: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5501:
5502: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
5503: dsp_core.registers[DSP_REG_SR] |= newsr;
5504: }
5505:
5506: static void dsp_eor_x0_a(void)
5507: {
5508: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X0];
5509: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5510:
5511: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5512: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5513: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5514: }
5515:
5516: static void dsp_eor_x0_b(void)
5517: {
5518: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X0];
5519: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5520:
5521: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5522: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5523: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5524: }
5525:
5526: static void dsp_eor_y0_a(void)
5527: {
5528: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y0];
5529: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5530:
5531: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5532: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5533: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5534: }
5535:
5536: static void dsp_eor_y0_b(void)
5537: {
5538: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y0];
5539: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5540:
5541: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5542: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5543: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5544: }
5545:
5546: static void dsp_eor_x1_a(void)
5547: {
5548: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_X1];
5549: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5550:
5551: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5552: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5553: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5554: }
5555:
5556: static void dsp_eor_x1_b(void)
5557: {
5558: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_X1];
5559: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5560:
5561: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5562: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5563: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5564: }
5565:
5566: static void dsp_eor_y1_a(void)
5567: {
5568: dsp_core.registers[DSP_REG_A1] ^= dsp_core.registers[DSP_REG_Y1];
5569: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
5570:
5571: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5572: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5573: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5574: }
5575:
5576: static void dsp_eor_y1_b(void)
5577: {
5578: dsp_core.registers[DSP_REG_B1] ^= dsp_core.registers[DSP_REG_Y1];
5579: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
5580:
5581: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5582: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5583: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5584: }
5585:
5586: static void dsp_lsl_a(void)
5587: {
5588: Uint32 newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
5589:
5590: dsp_core.registers[DSP_REG_A1] <<= 1;
5591: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
5592:
5593: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5594: dsp_core.registers[DSP_REG_SR] |= newcarry;
5595: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
5596: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5597: }
5598:
5599: static void dsp_lsl_b(void)
5600: {
5601: Uint32 newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
5602:
5603: dsp_core.registers[DSP_REG_B1] <<= 1;
5604: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
5605:
5606: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5607: dsp_core.registers[DSP_REG_SR] |= newcarry;
5608: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
5609: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5610: }
5611:
5612: static void dsp_lsr_a(void)
5613: {
5614: Uint32 newcarry = dsp_core.registers[DSP_REG_A1] & 1;
5615: dsp_core.registers[DSP_REG_A1] >>= 1;
5616:
5617: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5618: dsp_core.registers[DSP_REG_SR] |= newcarry;
5619: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
5620: }
5621:
5622: static void dsp_lsr_b(void)
5623: {
5624: Uint32 newcarry = dsp_core.registers[DSP_REG_B1] & 1;
5625: dsp_core.registers[DSP_REG_B1] >>= 1;
5626:
5627: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
5628: dsp_core.registers[DSP_REG_SR] |= newcarry;
5629: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
5630: }
5631:
5632: static void dsp_mac_p_x0_x0_a(void)
5633: {
5634: Uint32 source[3], dest[3];
5635: Uint16 newsr;
5636:
5637: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5638:
5639: dest[0] = dsp_core.registers[DSP_REG_A2];
5640: dest[1] = dsp_core.registers[DSP_REG_A1];
5641: dest[2] = dsp_core.registers[DSP_REG_A0];
5642: newsr = dsp_add56(source, dest);
5643:
5644: dsp_core.registers[DSP_REG_A2] = dest[0];
5645: dsp_core.registers[DSP_REG_A1] = dest[1];
5646: dsp_core.registers[DSP_REG_A0] = dest[2];
5647:
5648: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5649:
5650: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5651: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5652: }
5653:
5654: static void dsp_mac_m_x0_x0_a(void)
5655: {
5656: Uint32 source[3], dest[3];
5657: Uint16 newsr;
5658:
5659: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5660:
5661: dest[0] = dsp_core.registers[DSP_REG_A2];
5662: dest[1] = dsp_core.registers[DSP_REG_A1];
5663: dest[2] = dsp_core.registers[DSP_REG_A0];
5664: newsr = dsp_add56(source, dest);
5665:
5666: dsp_core.registers[DSP_REG_A2] = dest[0];
5667: dsp_core.registers[DSP_REG_A1] = dest[1];
5668: dsp_core.registers[DSP_REG_A0] = dest[2];
5669:
5670: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5671:
5672: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5673: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5674: }
5675: static void dsp_mac_p_x0_x0_b(void)
5676: {
5677: Uint32 source[3], dest[3];
5678: Uint16 newsr;
5679:
5680: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5681:
5682: dest[0] = dsp_core.registers[DSP_REG_B2];
5683: dest[1] = dsp_core.registers[DSP_REG_B1];
5684: dest[2] = dsp_core.registers[DSP_REG_B0];
5685: newsr = dsp_add56(source, dest);
5686:
5687: dsp_core.registers[DSP_REG_B2] = dest[0];
5688: dsp_core.registers[DSP_REG_B1] = dest[1];
5689: dsp_core.registers[DSP_REG_B0] = dest[2];
5690:
5691: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5692:
5693: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5694: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5695: }
5696:
5697: static void dsp_mac_m_x0_x0_b(void)
5698: {
5699: Uint32 source[3], dest[3];
5700: Uint16 newsr;
5701:
5702: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5703:
5704: dest[0] = dsp_core.registers[DSP_REG_B2];
5705: dest[1] = dsp_core.registers[DSP_REG_B1];
5706: dest[2] = dsp_core.registers[DSP_REG_B0];
5707: newsr = dsp_add56(source, dest);
5708:
5709: dsp_core.registers[DSP_REG_B2] = dest[0];
5710: dsp_core.registers[DSP_REG_B1] = dest[1];
5711: dsp_core.registers[DSP_REG_B0] = dest[2];
5712:
5713: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5714:
5715: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5716: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5717: }
5718:
5719: static void dsp_mac_p_y0_y0_a(void)
5720: {
5721: Uint32 source[3], dest[3];
5722: Uint16 newsr;
5723:
5724: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5725:
5726: dest[0] = dsp_core.registers[DSP_REG_A2];
5727: dest[1] = dsp_core.registers[DSP_REG_A1];
5728: dest[2] = dsp_core.registers[DSP_REG_A0];
5729: newsr = dsp_add56(source, dest);
5730:
5731: dsp_core.registers[DSP_REG_A2] = dest[0];
5732: dsp_core.registers[DSP_REG_A1] = dest[1];
5733: dsp_core.registers[DSP_REG_A0] = dest[2];
5734:
5735: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5736:
5737: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5738: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5739: }
5740:
5741: static void dsp_mac_m_y0_y0_a(void)
5742: {
5743: Uint32 source[3], dest[3];
5744: Uint16 newsr;
5745:
5746: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5747:
5748: dest[0] = dsp_core.registers[DSP_REG_A2];
5749: dest[1] = dsp_core.registers[DSP_REG_A1];
5750: dest[2] = dsp_core.registers[DSP_REG_A0];
5751: newsr = dsp_add56(source, dest);
5752:
5753: dsp_core.registers[DSP_REG_A2] = dest[0];
5754: dsp_core.registers[DSP_REG_A1] = dest[1];
5755: dsp_core.registers[DSP_REG_A0] = dest[2];
5756:
5757: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5758:
5759: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5760: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5761: }
5762: static void dsp_mac_p_y0_y0_b(void)
5763: {
5764: Uint32 source[3], dest[3];
5765: Uint16 newsr;
5766:
5767: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5768:
5769: dest[0] = dsp_core.registers[DSP_REG_B2];
5770: dest[1] = dsp_core.registers[DSP_REG_B1];
5771: dest[2] = dsp_core.registers[DSP_REG_B0];
5772: newsr = dsp_add56(source, dest);
5773:
5774: dsp_core.registers[DSP_REG_B2] = dest[0];
5775: dsp_core.registers[DSP_REG_B1] = dest[1];
5776: dsp_core.registers[DSP_REG_B0] = dest[2];
5777:
5778: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5779:
5780: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5781: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5782: }
5783:
5784: static void dsp_mac_m_y0_y0_b(void)
5785: {
5786: Uint32 source[3], dest[3];
5787: Uint16 newsr;
5788:
5789: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5790:
5791: dest[0] = dsp_core.registers[DSP_REG_B2];
5792: dest[1] = dsp_core.registers[DSP_REG_B1];
5793: dest[2] = dsp_core.registers[DSP_REG_B0];
5794: newsr = dsp_add56(source, dest);
5795:
5796: dsp_core.registers[DSP_REG_B2] = dest[0];
5797: dsp_core.registers[DSP_REG_B1] = dest[1];
5798: dsp_core.registers[DSP_REG_B0] = dest[2];
5799:
5800: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5801:
5802: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5803: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5804: }
5805:
5806: static void dsp_mac_p_x1_x0_a(void)
5807: {
5808: Uint32 source[3], dest[3];
5809: Uint16 newsr;
5810:
5811: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5812:
5813: dest[0] = dsp_core.registers[DSP_REG_A2];
5814: dest[1] = dsp_core.registers[DSP_REG_A1];
5815: dest[2] = dsp_core.registers[DSP_REG_A0];
5816: newsr = dsp_add56(source, dest);
5817:
5818: dsp_core.registers[DSP_REG_A2] = dest[0];
5819: dsp_core.registers[DSP_REG_A1] = dest[1];
5820: dsp_core.registers[DSP_REG_A0] = dest[2];
5821:
5822: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5823:
5824: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5825: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5826: }
5827:
5828: static void dsp_mac_m_x1_x0_a(void)
5829: {
5830: Uint32 source[3], dest[3];
5831: Uint16 newsr;
5832:
5833: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5834:
5835: dest[0] = dsp_core.registers[DSP_REG_A2];
5836: dest[1] = dsp_core.registers[DSP_REG_A1];
5837: dest[2] = dsp_core.registers[DSP_REG_A0];
5838: newsr = dsp_add56(source, dest);
5839:
5840: dsp_core.registers[DSP_REG_A2] = dest[0];
5841: dsp_core.registers[DSP_REG_A1] = dest[1];
5842: dsp_core.registers[DSP_REG_A0] = dest[2];
5843:
5844: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5845:
5846: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5847: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5848: }
5849:
5850: static void dsp_mac_p_x1_x0_b(void)
5851: {
5852: Uint32 source[3], dest[3];
5853: Uint16 newsr;
5854:
5855: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
5856:
5857: dest[0] = dsp_core.registers[DSP_REG_B2];
5858: dest[1] = dsp_core.registers[DSP_REG_B1];
5859: dest[2] = dsp_core.registers[DSP_REG_B0];
5860: newsr = dsp_add56(source, dest);
5861:
5862: dsp_core.registers[DSP_REG_B2] = dest[0];
5863: dsp_core.registers[DSP_REG_B1] = dest[1];
5864: dsp_core.registers[DSP_REG_B0] = dest[2];
5865:
5866: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5867:
5868: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5869: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5870: }
5871:
5872: static void dsp_mac_m_x1_x0_b(void)
5873: {
5874: Uint32 source[3], dest[3];
5875: Uint16 newsr;
5876:
5877: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
5878:
5879: dest[0] = dsp_core.registers[DSP_REG_B2];
5880: dest[1] = dsp_core.registers[DSP_REG_B1];
5881: dest[2] = dsp_core.registers[DSP_REG_B0];
5882: newsr = dsp_add56(source, dest);
5883:
5884: dsp_core.registers[DSP_REG_B2] = dest[0];
5885: dsp_core.registers[DSP_REG_B1] = dest[1];
5886: dsp_core.registers[DSP_REG_B0] = dest[2];
5887:
5888: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5889:
5890: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5891: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5892: }
5893:
5894: static void dsp_mac_p_y1_y0_a(void)
5895: {
5896: Uint32 source[3], dest[3];
5897: Uint16 newsr;
5898:
5899: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5900:
5901: dest[0] = dsp_core.registers[DSP_REG_A2];
5902: dest[1] = dsp_core.registers[DSP_REG_A1];
5903: dest[2] = dsp_core.registers[DSP_REG_A0];
5904: newsr = dsp_add56(source, dest);
5905:
5906: dsp_core.registers[DSP_REG_A2] = dest[0];
5907: dsp_core.registers[DSP_REG_A1] = dest[1];
5908: dsp_core.registers[DSP_REG_A0] = dest[2];
5909:
5910: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5911:
5912: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5913: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5914: }
5915:
5916: static void dsp_mac_m_y1_y0_a(void)
5917: {
5918: Uint32 source[3], dest[3];
5919: Uint16 newsr;
5920:
5921: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5922:
5923: dest[0] = dsp_core.registers[DSP_REG_A2];
5924: dest[1] = dsp_core.registers[DSP_REG_A1];
5925: dest[2] = dsp_core.registers[DSP_REG_A0];
5926: newsr = dsp_add56(source, dest);
5927:
5928: dsp_core.registers[DSP_REG_A2] = dest[0];
5929: dsp_core.registers[DSP_REG_A1] = dest[1];
5930: dsp_core.registers[DSP_REG_A0] = dest[2];
5931:
5932: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5933:
5934: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5935: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5936: }
5937:
5938: static void dsp_mac_p_y1_y0_b(void)
5939: {
5940: Uint32 source[3], dest[3];
5941: Uint16 newsr;
5942:
5943: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
5944:
5945: dest[0] = dsp_core.registers[DSP_REG_B2];
5946: dest[1] = dsp_core.registers[DSP_REG_B1];
5947: dest[2] = dsp_core.registers[DSP_REG_B0];
5948: newsr = dsp_add56(source, dest);
5949:
5950: dsp_core.registers[DSP_REG_B2] = dest[0];
5951: dsp_core.registers[DSP_REG_B1] = dest[1];
5952: dsp_core.registers[DSP_REG_B0] = dest[2];
5953:
5954: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5955:
5956: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5957: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5958: }
5959:
5960: static void dsp_mac_m_y1_y0_b(void)
5961: {
5962: Uint32 source[3], dest[3];
5963: Uint16 newsr;
5964:
5965: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
5966:
5967: dest[0] = dsp_core.registers[DSP_REG_B2];
5968: dest[1] = dsp_core.registers[DSP_REG_B1];
5969: dest[2] = dsp_core.registers[DSP_REG_B0];
5970: newsr = dsp_add56(source, dest);
5971:
5972: dsp_core.registers[DSP_REG_B2] = dest[0];
5973: dsp_core.registers[DSP_REG_B1] = dest[1];
5974: dsp_core.registers[DSP_REG_B0] = dest[2];
5975:
5976: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5977:
5978: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
5979: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
5980: }
5981:
5982: static void dsp_mac_p_x0_y1_a(void)
5983: {
5984: Uint32 source[3], dest[3];
5985: Uint16 newsr;
5986:
5987: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
5988:
5989: dest[0] = dsp_core.registers[DSP_REG_A2];
5990: dest[1] = dsp_core.registers[DSP_REG_A1];
5991: dest[2] = dsp_core.registers[DSP_REG_A0];
5992: newsr = dsp_add56(source, dest);
5993:
5994: dsp_core.registers[DSP_REG_A2] = dest[0];
5995: dsp_core.registers[DSP_REG_A1] = dest[1];
5996: dsp_core.registers[DSP_REG_A0] = dest[2];
5997:
5998: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
5999:
6000: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6001: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6002: }
6003:
6004: static void dsp_mac_m_x0_y1_a(void)
6005: {
6006: Uint32 source[3], dest[3];
6007: Uint16 newsr;
6008:
6009: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6010:
6011: dest[0] = dsp_core.registers[DSP_REG_A2];
6012: dest[1] = dsp_core.registers[DSP_REG_A1];
6013: dest[2] = dsp_core.registers[DSP_REG_A0];
6014: newsr = dsp_add56(source, dest);
6015:
6016: dsp_core.registers[DSP_REG_A2] = dest[0];
6017: dsp_core.registers[DSP_REG_A1] = dest[1];
6018: dsp_core.registers[DSP_REG_A0] = dest[2];
6019:
6020: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6021:
6022: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6023: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6024: }
6025:
6026: static void dsp_mac_p_x0_y1_b(void)
6027: {
6028: Uint32 source[3], dest[3];
6029: Uint16 newsr;
6030:
6031: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6032:
6033: dest[0] = dsp_core.registers[DSP_REG_B2];
6034: dest[1] = dsp_core.registers[DSP_REG_B1];
6035: dest[2] = dsp_core.registers[DSP_REG_B0];
6036: newsr = dsp_add56(source, dest);
6037:
6038: dsp_core.registers[DSP_REG_B2] = dest[0];
6039: dsp_core.registers[DSP_REG_B1] = dest[1];
6040: dsp_core.registers[DSP_REG_B0] = dest[2];
6041:
6042: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6043:
6044: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6045: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6046: }
6047:
6048: static void dsp_mac_m_x0_y1_b(void)
6049: {
6050: Uint32 source[3], dest[3];
6051: Uint16 newsr;
6052:
6053: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6054:
6055: dest[0] = dsp_core.registers[DSP_REG_B2];
6056: dest[1] = dsp_core.registers[DSP_REG_B1];
6057: dest[2] = dsp_core.registers[DSP_REG_B0];
6058: newsr = dsp_add56(source, dest);
6059:
6060: dsp_core.registers[DSP_REG_B2] = dest[0];
6061: dsp_core.registers[DSP_REG_B1] = dest[1];
6062: dsp_core.registers[DSP_REG_B0] = dest[2];
6063:
6064: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6065:
6066: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6067: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6068: }
6069:
6070: static void dsp_mac_p_y0_x0_a(void)
6071: {
6072: Uint32 source[3], dest[3];
6073: Uint16 newsr;
6074:
6075: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6076:
6077: dest[0] = dsp_core.registers[DSP_REG_A2];
6078: dest[1] = dsp_core.registers[DSP_REG_A1];
6079: dest[2] = dsp_core.registers[DSP_REG_A0];
6080: newsr = dsp_add56(source, dest);
6081:
6082: dsp_core.registers[DSP_REG_A2] = dest[0];
6083: dsp_core.registers[DSP_REG_A1] = dest[1];
6084: dsp_core.registers[DSP_REG_A0] = dest[2];
6085:
6086: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6087:
6088: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6089: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6090: }
6091:
6092: static void dsp_mac_m_y0_x0_a(void)
6093: {
6094: Uint32 source[3], dest[3];
6095: Uint16 newsr;
6096:
6097: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6098:
6099: dest[0] = dsp_core.registers[DSP_REG_A2];
6100: dest[1] = dsp_core.registers[DSP_REG_A1];
6101: dest[2] = dsp_core.registers[DSP_REG_A0];
6102: newsr = dsp_add56(source, dest);
6103:
6104: dsp_core.registers[DSP_REG_A2] = dest[0];
6105: dsp_core.registers[DSP_REG_A1] = dest[1];
6106: dsp_core.registers[DSP_REG_A0] = dest[2];
6107:
6108: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6109:
6110: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6111: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6112: }
6113:
6114: static void dsp_mac_p_y0_x0_b(void)
6115: {
6116: Uint32 source[3], dest[3];
6117: Uint16 newsr;
6118:
6119: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6120:
6121: dest[0] = dsp_core.registers[DSP_REG_B2];
6122: dest[1] = dsp_core.registers[DSP_REG_B1];
6123: dest[2] = dsp_core.registers[DSP_REG_B0];
6124: newsr = dsp_add56(source, dest);
6125:
6126: dsp_core.registers[DSP_REG_B2] = dest[0];
6127: dsp_core.registers[DSP_REG_B1] = dest[1];
6128: dsp_core.registers[DSP_REG_B0] = dest[2];
6129:
6130: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6131:
6132: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6133: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6134: }
6135:
6136: static void dsp_mac_m_y0_x0_b(void)
6137: {
6138: Uint32 source[3], dest[3];
6139: Uint16 newsr;
6140:
6141: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6142:
6143: dest[0] = dsp_core.registers[DSP_REG_B2];
6144: dest[1] = dsp_core.registers[DSP_REG_B1];
6145: dest[2] = dsp_core.registers[DSP_REG_B0];
6146: newsr = dsp_add56(source, dest);
6147:
6148: dsp_core.registers[DSP_REG_B2] = dest[0];
6149: dsp_core.registers[DSP_REG_B1] = dest[1];
6150: dsp_core.registers[DSP_REG_B0] = dest[2];
6151:
6152: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6153:
6154: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6155: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6156: }
6157:
6158: static void dsp_mac_p_x1_y0_a(void)
6159: {
6160: Uint32 source[3], dest[3];
6161: Uint16 newsr;
6162:
6163: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6164:
6165: dest[0] = dsp_core.registers[DSP_REG_A2];
6166: dest[1] = dsp_core.registers[DSP_REG_A1];
6167: dest[2] = dsp_core.registers[DSP_REG_A0];
6168: newsr = dsp_add56(source, dest);
6169:
6170: dsp_core.registers[DSP_REG_A2] = dest[0];
6171: dsp_core.registers[DSP_REG_A1] = dest[1];
6172: dsp_core.registers[DSP_REG_A0] = dest[2];
6173:
6174: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6175:
6176: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6177: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6178: }
6179:
6180: static void dsp_mac_m_x1_y0_a(void)
6181: {
6182: Uint32 source[3], dest[3];
6183: Uint16 newsr;
6184:
6185: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6186:
6187: dest[0] = dsp_core.registers[DSP_REG_A2];
6188: dest[1] = dsp_core.registers[DSP_REG_A1];
6189: dest[2] = dsp_core.registers[DSP_REG_A0];
6190: newsr = dsp_add56(source, dest);
6191:
6192: dsp_core.registers[DSP_REG_A2] = dest[0];
6193: dsp_core.registers[DSP_REG_A1] = dest[1];
6194: dsp_core.registers[DSP_REG_A0] = dest[2];
6195:
6196: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6197:
6198: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6199: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6200: }
6201:
6202: static void dsp_mac_p_x1_y0_b(void)
6203: {
6204: Uint32 source[3], dest[3];
6205: Uint16 newsr;
6206:
6207: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6208:
6209: dest[0] = dsp_core.registers[DSP_REG_B2];
6210: dest[1] = dsp_core.registers[DSP_REG_B1];
6211: dest[2] = dsp_core.registers[DSP_REG_B0];
6212: newsr = dsp_add56(source, dest);
6213:
6214: dsp_core.registers[DSP_REG_B2] = dest[0];
6215: dsp_core.registers[DSP_REG_B1] = dest[1];
6216: dsp_core.registers[DSP_REG_B0] = dest[2];
6217:
6218: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6219:
6220: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6221: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6222: }
6223:
6224: static void dsp_mac_m_x1_y0_b(void)
6225: {
6226: Uint32 source[3], dest[3];
6227: Uint16 newsr;
6228:
6229: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6230:
6231: dest[0] = dsp_core.registers[DSP_REG_B2];
6232: dest[1] = dsp_core.registers[DSP_REG_B1];
6233: dest[2] = dsp_core.registers[DSP_REG_B0];
6234: newsr = dsp_add56(source, dest);
6235:
6236: dsp_core.registers[DSP_REG_B2] = dest[0];
6237: dsp_core.registers[DSP_REG_B1] = dest[1];
6238: dsp_core.registers[DSP_REG_B0] = dest[2];
6239:
6240: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6241:
6242: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6243: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6244: }
6245:
6246: static void dsp_mac_p_y1_x1_a(void)
6247: {
6248: Uint32 source[3], dest[3];
6249: Uint16 newsr;
6250:
6251: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6252:
6253: dest[0] = dsp_core.registers[DSP_REG_A2];
6254: dest[1] = dsp_core.registers[DSP_REG_A1];
6255: dest[2] = dsp_core.registers[DSP_REG_A0];
6256: newsr = dsp_add56(source, dest);
6257:
6258: dsp_core.registers[DSP_REG_A2] = dest[0];
6259: dsp_core.registers[DSP_REG_A1] = dest[1];
6260: dsp_core.registers[DSP_REG_A0] = dest[2];
6261:
6262: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6263:
6264: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6265: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6266: }
6267:
6268: static void dsp_mac_m_y1_x1_a(void)
6269: {
6270: Uint32 source[3], dest[3];
6271: Uint16 newsr;
6272:
6273: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6274:
6275: dest[0] = dsp_core.registers[DSP_REG_A2];
6276: dest[1] = dsp_core.registers[DSP_REG_A1];
6277: dest[2] = dsp_core.registers[DSP_REG_A0];
6278: newsr = dsp_add56(source, dest);
6279:
6280: dsp_core.registers[DSP_REG_A2] = dest[0];
6281: dsp_core.registers[DSP_REG_A1] = dest[1];
6282: dsp_core.registers[DSP_REG_A0] = dest[2];
6283:
6284: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6285:
6286: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6287: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6288: }
6289:
6290: static void dsp_mac_p_y1_x1_b(void)
6291: {
6292: Uint32 source[3], dest[3];
6293: Uint16 newsr;
6294:
6295: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
6296:
6297: dest[0] = dsp_core.registers[DSP_REG_B2];
6298: dest[1] = dsp_core.registers[DSP_REG_B1];
6299: dest[2] = dsp_core.registers[DSP_REG_B0];
6300: newsr = dsp_add56(source, dest);
6301:
6302: dsp_core.registers[DSP_REG_B2] = dest[0];
6303: dsp_core.registers[DSP_REG_B1] = dest[1];
6304: dsp_core.registers[DSP_REG_B0] = dest[2];
6305:
6306: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6307:
6308: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6309: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6310: }
6311:
6312: static void dsp_mac_m_y1_x1_b(void)
6313: {
6314: Uint32 source[3], dest[3];
6315: Uint16 newsr;
6316:
6317: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
6318:
6319: dest[0] = dsp_core.registers[DSP_REG_B2];
6320: dest[1] = dsp_core.registers[DSP_REG_B1];
6321: dest[2] = dsp_core.registers[DSP_REG_B0];
6322: newsr = dsp_add56(source, dest);
6323:
6324: dsp_core.registers[DSP_REG_B2] = dest[0];
6325: dsp_core.registers[DSP_REG_B1] = dest[1];
6326: dsp_core.registers[DSP_REG_B0] = dest[2];
6327:
6328: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6329:
6330: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6331: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6332: }
6333:
6334: static void dsp_macr_p_x0_x0_a(void)
6335: {
6336: Uint32 source[3], dest[3];
6337: Uint16 newsr;
6338:
6339: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6340:
6341: dest[0] = dsp_core.registers[DSP_REG_A2];
6342: dest[1] = dsp_core.registers[DSP_REG_A1];
6343: dest[2] = dsp_core.registers[DSP_REG_A0];
6344: newsr = dsp_add56(source, dest);
6345:
6346: dsp_rnd56(dest);
6347:
6348: dsp_core.registers[DSP_REG_A2] = dest[0];
6349: dsp_core.registers[DSP_REG_A1] = dest[1];
6350: dsp_core.registers[DSP_REG_A0] = dest[2];
6351:
6352: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6353:
6354: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6355: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6356: }
6357:
6358: static void dsp_macr_m_x0_x0_a(void)
6359: {
6360: Uint32 source[3], dest[3];
6361: Uint16 newsr;
6362:
6363: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6364:
6365: dest[0] = dsp_core.registers[DSP_REG_A2];
6366: dest[1] = dsp_core.registers[DSP_REG_A1];
6367: dest[2] = dsp_core.registers[DSP_REG_A0];
6368: newsr = dsp_add56(source, dest);
6369:
6370: dsp_rnd56(dest);
6371:
6372: dsp_core.registers[DSP_REG_A2] = dest[0];
6373: dsp_core.registers[DSP_REG_A1] = dest[1];
6374: dsp_core.registers[DSP_REG_A0] = dest[2];
6375:
6376: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6377:
6378: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6379: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6380: }
6381: static void dsp_macr_p_x0_x0_b(void)
6382: {
6383: Uint32 source[3], dest[3];
6384: Uint16 newsr;
6385:
6386: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6387:
6388: dest[0] = dsp_core.registers[DSP_REG_B2];
6389: dest[1] = dsp_core.registers[DSP_REG_B1];
6390: dest[2] = dsp_core.registers[DSP_REG_B0];
6391: newsr = dsp_add56(source, dest);
6392:
6393: dsp_rnd56(dest);
6394:
6395: dsp_core.registers[DSP_REG_B2] = dest[0];
6396: dsp_core.registers[DSP_REG_B1] = dest[1];
6397: dsp_core.registers[DSP_REG_B0] = dest[2];
6398:
6399: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6400:
6401: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6402: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6403: }
6404:
6405: static void dsp_macr_m_x0_x0_b(void)
6406: {
6407: Uint32 source[3], dest[3];
6408: Uint16 newsr;
6409:
6410: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6411:
6412: dest[0] = dsp_core.registers[DSP_REG_B2];
6413: dest[1] = dsp_core.registers[DSP_REG_B1];
6414: dest[2] = dsp_core.registers[DSP_REG_B0];
6415: newsr = dsp_add56(source, dest);
6416:
6417: dsp_rnd56(dest);
6418:
6419: dsp_core.registers[DSP_REG_B2] = dest[0];
6420: dsp_core.registers[DSP_REG_B1] = dest[1];
6421: dsp_core.registers[DSP_REG_B0] = dest[2];
6422:
6423: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6424:
6425: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6426: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6427: }
6428:
6429: static void dsp_macr_p_y0_y0_a(void)
6430: {
6431: Uint32 source[3], dest[3];
6432: Uint16 newsr;
6433:
6434: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6435:
6436: dest[0] = dsp_core.registers[DSP_REG_A2];
6437: dest[1] = dsp_core.registers[DSP_REG_A1];
6438: dest[2] = dsp_core.registers[DSP_REG_A0];
6439: newsr = dsp_add56(source, dest);
6440:
6441: dsp_rnd56(dest);
6442:
6443: dsp_core.registers[DSP_REG_A2] = dest[0];
6444: dsp_core.registers[DSP_REG_A1] = dest[1];
6445: dsp_core.registers[DSP_REG_A0] = dest[2];
6446:
6447: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6448:
6449: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6450: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6451: }
6452:
6453: static void dsp_macr_m_y0_y0_a(void)
6454: {
6455: Uint32 source[3], dest[3];
6456: Uint16 newsr;
6457:
6458: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6459:
6460: dest[0] = dsp_core.registers[DSP_REG_A2];
6461: dest[1] = dsp_core.registers[DSP_REG_A1];
6462: dest[2] = dsp_core.registers[DSP_REG_A0];
6463: newsr = dsp_add56(source, dest);
6464:
6465: dsp_rnd56(dest);
6466:
6467: dsp_core.registers[DSP_REG_A2] = dest[0];
6468: dsp_core.registers[DSP_REG_A1] = dest[1];
6469: dsp_core.registers[DSP_REG_A0] = dest[2];
6470:
6471: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6472:
6473: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6474: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6475: }
6476: static void dsp_macr_p_y0_y0_b(void)
6477: {
6478: Uint32 source[3], dest[3];
6479: Uint16 newsr;
6480:
6481: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6482:
6483: dest[0] = dsp_core.registers[DSP_REG_B2];
6484: dest[1] = dsp_core.registers[DSP_REG_B1];
6485: dest[2] = dsp_core.registers[DSP_REG_B0];
6486: newsr = dsp_add56(source, dest);
6487:
6488: dsp_rnd56(dest);
6489:
6490: dsp_core.registers[DSP_REG_B2] = dest[0];
6491: dsp_core.registers[DSP_REG_B1] = dest[1];
6492: dsp_core.registers[DSP_REG_B0] = dest[2];
6493:
6494: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6495:
6496: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6497: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6498: }
6499:
6500: static void dsp_macr_m_y0_y0_b(void)
6501: {
6502: Uint32 source[3], dest[3];
6503: Uint16 newsr;
6504:
6505: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6506:
6507: dest[0] = dsp_core.registers[DSP_REG_B2];
6508: dest[1] = dsp_core.registers[DSP_REG_B1];
6509: dest[2] = dsp_core.registers[DSP_REG_B0];
6510: newsr = dsp_add56(source, dest);
6511:
6512: dsp_rnd56(dest);
6513:
6514: dsp_core.registers[DSP_REG_B2] = dest[0];
6515: dsp_core.registers[DSP_REG_B1] = dest[1];
6516: dsp_core.registers[DSP_REG_B0] = dest[2];
6517:
6518: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6519:
6520: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6521: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6522: }
6523:
6524: static void dsp_macr_p_x1_x0_a(void)
6525: {
6526: Uint32 source[3], dest[3];
6527: Uint16 newsr;
6528:
6529: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6530:
6531: dest[0] = dsp_core.registers[DSP_REG_A2];
6532: dest[1] = dsp_core.registers[DSP_REG_A1];
6533: dest[2] = dsp_core.registers[DSP_REG_A0];
6534: newsr = dsp_add56(source, dest);
6535:
6536: dsp_rnd56(dest);
6537:
6538: dsp_core.registers[DSP_REG_A2] = dest[0];
6539: dsp_core.registers[DSP_REG_A1] = dest[1];
6540: dsp_core.registers[DSP_REG_A0] = dest[2];
6541:
6542: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6543:
6544: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6545: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6546: }
6547:
6548: static void dsp_macr_m_x1_x0_a(void)
6549: {
6550: Uint32 source[3], dest[3];
6551: Uint16 newsr;
6552:
6553: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6554:
6555: dest[0] = dsp_core.registers[DSP_REG_A2];
6556: dest[1] = dsp_core.registers[DSP_REG_A1];
6557: dest[2] = dsp_core.registers[DSP_REG_A0];
6558: newsr = dsp_add56(source, dest);
6559:
6560: dsp_rnd56(dest);
6561:
6562: dsp_core.registers[DSP_REG_A2] = dest[0];
6563: dsp_core.registers[DSP_REG_A1] = dest[1];
6564: dsp_core.registers[DSP_REG_A0] = dest[2];
6565:
6566: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6567:
6568: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6569: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6570: }
6571:
6572: static void dsp_macr_p_x1_x0_b(void)
6573: {
6574: Uint32 source[3], dest[3];
6575: Uint16 newsr;
6576:
6577: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6578:
6579: dest[0] = dsp_core.registers[DSP_REG_B2];
6580: dest[1] = dsp_core.registers[DSP_REG_B1];
6581: dest[2] = dsp_core.registers[DSP_REG_B0];
6582: newsr = dsp_add56(source, dest);
6583:
6584: dsp_rnd56(dest);
6585:
6586: dsp_core.registers[DSP_REG_B2] = dest[0];
6587: dsp_core.registers[DSP_REG_B1] = dest[1];
6588: dsp_core.registers[DSP_REG_B0] = dest[2];
6589:
6590: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6591:
6592: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6593: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6594: }
6595:
6596: static void dsp_macr_m_x1_x0_b(void)
6597: {
6598: Uint32 source[3], dest[3];
6599: Uint16 newsr;
6600:
6601: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6602:
6603: dest[0] = dsp_core.registers[DSP_REG_B2];
6604: dest[1] = dsp_core.registers[DSP_REG_B1];
6605: dest[2] = dsp_core.registers[DSP_REG_B0];
6606: newsr = dsp_add56(source, dest);
6607:
6608: dsp_rnd56(dest);
6609:
6610: dsp_core.registers[DSP_REG_B2] = dest[0];
6611: dsp_core.registers[DSP_REG_B1] = dest[1];
6612: dsp_core.registers[DSP_REG_B0] = dest[2];
6613:
6614: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6615:
6616: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6617: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6618: }
6619:
6620: static void dsp_macr_p_y1_y0_a(void)
6621: {
6622: Uint32 source[3], dest[3];
6623: Uint16 newsr;
6624:
6625: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6626:
6627: dest[0] = dsp_core.registers[DSP_REG_A2];
6628: dest[1] = dsp_core.registers[DSP_REG_A1];
6629: dest[2] = dsp_core.registers[DSP_REG_A0];
6630: newsr = dsp_add56(source, dest);
6631:
6632: dsp_rnd56(dest);
6633:
6634: dsp_core.registers[DSP_REG_A2] = dest[0];
6635: dsp_core.registers[DSP_REG_A1] = dest[1];
6636: dsp_core.registers[DSP_REG_A0] = dest[2];
6637:
6638: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6639:
6640: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6641: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6642: }
6643:
6644: static void dsp_macr_m_y1_y0_a(void)
6645: {
6646: Uint32 source[3], dest[3];
6647: Uint16 newsr;
6648:
6649: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6650:
6651: dest[0] = dsp_core.registers[DSP_REG_A2];
6652: dest[1] = dsp_core.registers[DSP_REG_A1];
6653: dest[2] = dsp_core.registers[DSP_REG_A0];
6654: newsr = dsp_add56(source, dest);
6655:
6656: dsp_rnd56(dest);
6657:
6658: dsp_core.registers[DSP_REG_A2] = dest[0];
6659: dsp_core.registers[DSP_REG_A1] = dest[1];
6660: dsp_core.registers[DSP_REG_A0] = dest[2];
6661:
6662: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6663:
6664: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6665: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6666: }
6667:
6668: static void dsp_macr_p_y1_y0_b(void)
6669: {
6670: Uint32 source[3], dest[3];
6671: Uint16 newsr;
6672:
6673: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6674:
6675: dest[0] = dsp_core.registers[DSP_REG_B2];
6676: dest[1] = dsp_core.registers[DSP_REG_B1];
6677: dest[2] = dsp_core.registers[DSP_REG_B0];
6678: newsr = dsp_add56(source, dest);
6679:
6680: dsp_rnd56(dest);
6681:
6682: dsp_core.registers[DSP_REG_B2] = dest[0];
6683: dsp_core.registers[DSP_REG_B1] = dest[1];
6684: dsp_core.registers[DSP_REG_B0] = dest[2];
6685:
6686: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6687:
6688: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6689: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6690: }
6691:
6692: static void dsp_macr_m_y1_y0_b(void)
6693: {
6694: Uint32 source[3], dest[3];
6695: Uint16 newsr;
6696:
6697: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6698:
6699: dest[0] = dsp_core.registers[DSP_REG_B2];
6700: dest[1] = dsp_core.registers[DSP_REG_B1];
6701: dest[2] = dsp_core.registers[DSP_REG_B0];
6702: newsr = dsp_add56(source, dest);
6703:
6704: dsp_rnd56(dest);
6705:
6706: dsp_core.registers[DSP_REG_B2] = dest[0];
6707: dsp_core.registers[DSP_REG_B1] = dest[1];
6708: dsp_core.registers[DSP_REG_B0] = dest[2];
6709:
6710: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6711:
6712: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6713: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6714: }
6715:
6716: static void dsp_macr_p_x0_y1_a(void)
6717: {
6718: Uint32 source[3], dest[3];
6719: Uint16 newsr;
6720:
6721: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6722:
6723: dest[0] = dsp_core.registers[DSP_REG_A2];
6724: dest[1] = dsp_core.registers[DSP_REG_A1];
6725: dest[2] = dsp_core.registers[DSP_REG_A0];
6726: newsr = dsp_add56(source, dest);
6727:
6728: dsp_rnd56(dest);
6729:
6730: dsp_core.registers[DSP_REG_A2] = dest[0];
6731: dsp_core.registers[DSP_REG_A1] = dest[1];
6732: dsp_core.registers[DSP_REG_A0] = dest[2];
6733:
6734: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6735:
6736: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6737: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6738: }
6739:
6740: static void dsp_macr_m_x0_y1_a(void)
6741: {
6742: Uint32 source[3], dest[3];
6743: Uint16 newsr;
6744:
6745: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6746:
6747: dest[0] = dsp_core.registers[DSP_REG_A2];
6748: dest[1] = dsp_core.registers[DSP_REG_A1];
6749: dest[2] = dsp_core.registers[DSP_REG_A0];
6750: newsr = dsp_add56(source, dest);
6751:
6752: dsp_rnd56(dest);
6753:
6754: dsp_core.registers[DSP_REG_A2] = dest[0];
6755: dsp_core.registers[DSP_REG_A1] = dest[1];
6756: dsp_core.registers[DSP_REG_A0] = dest[2];
6757:
6758: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6759:
6760: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6761: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6762: }
6763:
6764: static void dsp_macr_p_x0_y1_b(void)
6765: {
6766: Uint32 source[3], dest[3];
6767: Uint16 newsr;
6768:
6769: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
6770:
6771: dest[0] = dsp_core.registers[DSP_REG_B2];
6772: dest[1] = dsp_core.registers[DSP_REG_B1];
6773: dest[2] = dsp_core.registers[DSP_REG_B0];
6774: newsr = dsp_add56(source, dest);
6775:
6776: dsp_rnd56(dest);
6777:
6778: dsp_core.registers[DSP_REG_B2] = dest[0];
6779: dsp_core.registers[DSP_REG_B1] = dest[1];
6780: dsp_core.registers[DSP_REG_B0] = dest[2];
6781:
6782: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6783:
6784: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6785: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6786: }
6787:
6788: static void dsp_macr_m_x0_y1_b(void)
6789: {
6790: Uint32 source[3], dest[3];
6791: Uint16 newsr;
6792:
6793: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
6794:
6795: dest[0] = dsp_core.registers[DSP_REG_B2];
6796: dest[1] = dsp_core.registers[DSP_REG_B1];
6797: dest[2] = dsp_core.registers[DSP_REG_B0];
6798: newsr = dsp_add56(source, dest);
6799:
6800: dsp_rnd56(dest);
6801:
6802: dsp_core.registers[DSP_REG_B2] = dest[0];
6803: dsp_core.registers[DSP_REG_B1] = dest[1];
6804: dsp_core.registers[DSP_REG_B0] = dest[2];
6805:
6806: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6807:
6808: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6809: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6810: }
6811:
6812: static void dsp_macr_p_y0_x0_a(void)
6813: {
6814: Uint32 source[3], dest[3];
6815: Uint16 newsr;
6816:
6817: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6818:
6819: dest[0] = dsp_core.registers[DSP_REG_A2];
6820: dest[1] = dsp_core.registers[DSP_REG_A1];
6821: dest[2] = dsp_core.registers[DSP_REG_A0];
6822: newsr = dsp_add56(source, dest);
6823:
6824: dsp_rnd56(dest);
6825:
6826: dsp_core.registers[DSP_REG_A2] = dest[0];
6827: dsp_core.registers[DSP_REG_A1] = dest[1];
6828: dsp_core.registers[DSP_REG_A0] = dest[2];
6829:
6830: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6831:
6832: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6833: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6834: }
6835:
6836: static void dsp_macr_m_y0_x0_a(void)
6837: {
6838: Uint32 source[3], dest[3];
6839: Uint16 newsr;
6840:
6841: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6842:
6843: dest[0] = dsp_core.registers[DSP_REG_A2];
6844: dest[1] = dsp_core.registers[DSP_REG_A1];
6845: dest[2] = dsp_core.registers[DSP_REG_A0];
6846: newsr = dsp_add56(source, dest);
6847:
6848: dsp_rnd56(dest);
6849:
6850: dsp_core.registers[DSP_REG_A2] = dest[0];
6851: dsp_core.registers[DSP_REG_A1] = dest[1];
6852: dsp_core.registers[DSP_REG_A0] = dest[2];
6853:
6854: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6855:
6856: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6857: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6858: }
6859:
6860: static void dsp_macr_p_y0_x0_b(void)
6861: {
6862: Uint32 source[3], dest[3];
6863: Uint16 newsr;
6864:
6865: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
6866:
6867: dest[0] = dsp_core.registers[DSP_REG_B2];
6868: dest[1] = dsp_core.registers[DSP_REG_B1];
6869: dest[2] = dsp_core.registers[DSP_REG_B0];
6870: newsr = dsp_add56(source, dest);
6871:
6872: dsp_rnd56(dest);
6873:
6874: dsp_core.registers[DSP_REG_B2] = dest[0];
6875: dsp_core.registers[DSP_REG_B1] = dest[1];
6876: dsp_core.registers[DSP_REG_B0] = dest[2];
6877:
6878: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6879:
6880: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6881: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6882: }
6883:
6884: static void dsp_macr_m_y0_x0_b(void)
6885: {
6886: Uint32 source[3], dest[3];
6887: Uint16 newsr;
6888:
6889: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
6890:
6891: dest[0] = dsp_core.registers[DSP_REG_B2];
6892: dest[1] = dsp_core.registers[DSP_REG_B1];
6893: dest[2] = dsp_core.registers[DSP_REG_B0];
6894: newsr = dsp_add56(source, dest);
6895:
6896: dsp_rnd56(dest);
6897:
6898: dsp_core.registers[DSP_REG_B2] = dest[0];
6899: dsp_core.registers[DSP_REG_B1] = dest[1];
6900: dsp_core.registers[DSP_REG_B0] = dest[2];
6901:
6902: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6903:
6904: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6905: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6906: }
6907:
6908: static void dsp_macr_p_x1_y0_a(void)
6909: {
6910: Uint32 source[3], dest[3];
6911: Uint16 newsr;
6912:
6913: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6914:
6915: dest[0] = dsp_core.registers[DSP_REG_A2];
6916: dest[1] = dsp_core.registers[DSP_REG_A1];
6917: dest[2] = dsp_core.registers[DSP_REG_A0];
6918: newsr = dsp_add56(source, dest);
6919:
6920: dsp_rnd56(dest);
6921:
6922: dsp_core.registers[DSP_REG_A2] = dest[0];
6923: dsp_core.registers[DSP_REG_A1] = dest[1];
6924: dsp_core.registers[DSP_REG_A0] = dest[2];
6925:
6926: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6927:
6928: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6929: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6930: }
6931:
6932: static void dsp_macr_m_x1_y0_a(void)
6933: {
6934: Uint32 source[3], dest[3];
6935: Uint16 newsr;
6936:
6937: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6938:
6939: dest[0] = dsp_core.registers[DSP_REG_A2];
6940: dest[1] = dsp_core.registers[DSP_REG_A1];
6941: dest[2] = dsp_core.registers[DSP_REG_A0];
6942: newsr = dsp_add56(source, dest);
6943:
6944: dsp_rnd56(dest);
6945:
6946: dsp_core.registers[DSP_REG_A2] = dest[0];
6947: dsp_core.registers[DSP_REG_A1] = dest[1];
6948: dsp_core.registers[DSP_REG_A0] = dest[2];
6949:
6950: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6951:
6952: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6953: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6954: }
6955:
6956: static void dsp_macr_p_x1_y0_b(void)
6957: {
6958: Uint32 source[3], dest[3];
6959: Uint16 newsr;
6960:
6961: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
6962:
6963: dsp_rnd56(dest);
6964:
6965: dest[0] = dsp_core.registers[DSP_REG_B2];
6966: dest[1] = dsp_core.registers[DSP_REG_B1];
6967: dest[2] = dsp_core.registers[DSP_REG_B0];
6968: newsr = dsp_add56(source, dest);
6969:
6970: dsp_core.registers[DSP_REG_B2] = dest[0];
6971: dsp_core.registers[DSP_REG_B1] = dest[1];
6972: dsp_core.registers[DSP_REG_B0] = dest[2];
6973:
6974: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6975:
6976: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
6977: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
6978: }
6979:
6980: static void dsp_macr_m_x1_y0_b(void)
6981: {
6982: Uint32 source[3], dest[3];
6983: Uint16 newsr;
6984:
6985: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
6986:
6987: dest[0] = dsp_core.registers[DSP_REG_B2];
6988: dest[1] = dsp_core.registers[DSP_REG_B1];
6989: dest[2] = dsp_core.registers[DSP_REG_B0];
6990: newsr = dsp_add56(source, dest);
6991:
6992: dsp_rnd56(dest);
6993:
6994: dsp_core.registers[DSP_REG_B2] = dest[0];
6995: dsp_core.registers[DSP_REG_B1] = dest[1];
6996: dsp_core.registers[DSP_REG_B0] = dest[2];
6997:
6998: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
6999:
7000: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7001: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7002: }
7003:
7004: static void dsp_macr_p_y1_x1_a(void)
7005: {
7006: Uint32 source[3], dest[3];
7007: Uint16 newsr;
7008:
7009: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7010:
7011: dest[0] = dsp_core.registers[DSP_REG_A2];
7012: dest[1] = dsp_core.registers[DSP_REG_A1];
7013: dest[2] = dsp_core.registers[DSP_REG_A0];
7014: newsr = dsp_add56(source, dest);
7015:
7016: dsp_rnd56(dest);
7017:
7018: dsp_core.registers[DSP_REG_A2] = dest[0];
7019: dsp_core.registers[DSP_REG_A1] = dest[1];
7020: dsp_core.registers[DSP_REG_A0] = dest[2];
7021:
7022: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7023:
7024: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7025: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7026: }
7027:
7028: static void dsp_macr_m_y1_x1_a(void)
7029: {
7030: Uint32 source[3], dest[3];
7031: Uint16 newsr;
7032:
7033: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7034:
7035: dest[0] = dsp_core.registers[DSP_REG_A2];
7036: dest[1] = dsp_core.registers[DSP_REG_A1];
7037: dest[2] = dsp_core.registers[DSP_REG_A0];
7038: newsr = dsp_add56(source, dest);
7039:
7040: dsp_rnd56(dest);
7041:
7042: dsp_core.registers[DSP_REG_A2] = dest[0];
7043: dsp_core.registers[DSP_REG_A1] = dest[1];
7044: dsp_core.registers[DSP_REG_A0] = dest[2];
7045:
7046: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7047:
7048: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7049: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7050: }
7051:
7052: static void dsp_macr_p_y1_x1_b(void)
7053: {
7054: Uint32 source[3], dest[3];
7055: Uint16 newsr;
7056:
7057: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7058:
7059: dest[0] = dsp_core.registers[DSP_REG_B2];
7060: dest[1] = dsp_core.registers[DSP_REG_B1];
7061: dest[2] = dsp_core.registers[DSP_REG_B0];
7062: newsr = dsp_add56(source, dest);
7063:
7064: dsp_rnd56(dest);
7065:
7066: dsp_core.registers[DSP_REG_B2] = dest[0];
7067: dsp_core.registers[DSP_REG_B1] = dest[1];
7068: dsp_core.registers[DSP_REG_B0] = dest[2];
7069:
7070: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7071:
7072: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7073: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7074: }
7075:
7076: static void dsp_macr_m_y1_x1_b(void)
7077: {
7078: Uint32 source[3], dest[3];
7079: Uint16 newsr;
7080:
7081: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7082:
7083: dest[0] = dsp_core.registers[DSP_REG_B2];
7084: dest[1] = dsp_core.registers[DSP_REG_B1];
7085: dest[2] = dsp_core.registers[DSP_REG_B0];
7086: newsr = dsp_add56(source, dest);
7087:
7088: dsp_rnd56(dest);
7089:
7090: dsp_core.registers[DSP_REG_B2] = dest[0];
7091: dsp_core.registers[DSP_REG_B1] = dest[1];
7092: dsp_core.registers[DSP_REG_B0] = dest[2];
7093:
7094: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
7095:
7096: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7097: dsp_core.registers[DSP_REG_SR] |= newsr & 0xfe;
7098: }
7099:
7100:
7101: static void dsp_move(void)
7102: {
7103: /* move instruction inside alu opcodes
7104: taken care of by parallel move dispatcher */
7105: }
7106:
7107: static void dsp_mpy_p_x0_x0_a(void)
7108: {
7109: Uint32 source[3];
7110:
7111: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7112:
7113: dsp_core.registers[DSP_REG_A2] = source[0];
7114: dsp_core.registers[DSP_REG_A1] = source[1];
7115: dsp_core.registers[DSP_REG_A0] = source[2];
7116:
7117: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7118: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7119: }
7120:
7121: static void dsp_mpy_m_x0_x0_a(void)
7122: {
7123: Uint32 source[3];
7124:
7125: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7126:
7127: dsp_core.registers[DSP_REG_A2] = source[0];
7128: dsp_core.registers[DSP_REG_A1] = source[1];
7129: dsp_core.registers[DSP_REG_A0] = source[2];
7130:
7131: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7132: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7133: }
7134:
7135: static void dsp_mpy_p_x0_x0_b(void)
7136: {
7137: Uint32 source[3];
7138:
7139: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7140:
7141: dsp_core.registers[DSP_REG_B2] = source[0];
7142: dsp_core.registers[DSP_REG_B1] = source[1];
7143: dsp_core.registers[DSP_REG_B0] = source[2];
7144:
7145: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7146: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7147: }
7148:
7149: static void dsp_mpy_m_x0_x0_b(void)
7150: {
7151: Uint32 source[3];
7152:
7153:
7154: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7155:
7156: dsp_core.registers[DSP_REG_B2] = source[0];
7157: dsp_core.registers[DSP_REG_B1] = source[1];
7158: dsp_core.registers[DSP_REG_B0] = source[2];
7159:
7160: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7161: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7162: }
7163:
7164: static void dsp_mpy_p_y0_y0_a(void)
7165: {
7166: Uint32 source[3];
7167:
7168: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7169:
7170: dsp_core.registers[DSP_REG_A2] = source[0];
7171: dsp_core.registers[DSP_REG_A1] = source[1];
7172: dsp_core.registers[DSP_REG_A0] = source[2];
7173:
7174: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7175: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7176: }
7177:
7178: static void dsp_mpy_m_y0_y0_a(void)
7179: {
7180: Uint32 source[3];
7181:
7182: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7183:
7184: dsp_core.registers[DSP_REG_A2] = source[0];
7185: dsp_core.registers[DSP_REG_A1] = source[1];
7186: dsp_core.registers[DSP_REG_A0] = source[2];
7187:
7188: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7189: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7190: }
7191:
7192: static void dsp_mpy_p_y0_y0_b(void)
7193: {
7194: Uint32 source[3];
7195:
7196: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7197:
7198: dsp_core.registers[DSP_REG_B2] = source[0];
7199: dsp_core.registers[DSP_REG_B1] = source[1];
7200: dsp_core.registers[DSP_REG_B0] = source[2];
7201:
7202: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7203: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7204: }
7205:
7206: static void dsp_mpy_m_y0_y0_b(void)
7207: {
7208: Uint32 source[3];
7209:
7210: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7211:
7212: dsp_core.registers[DSP_REG_B2] = source[0];
7213: dsp_core.registers[DSP_REG_B1] = source[1];
7214: dsp_core.registers[DSP_REG_B0] = source[2];
7215:
7216: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7217: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7218: }
7219:
7220: static void dsp_mpy_p_x1_x0_a(void)
7221: {
7222: Uint32 source[3];
7223:
7224: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7225:
7226: dsp_core.registers[DSP_REG_A2] = source[0];
7227: dsp_core.registers[DSP_REG_A1] = source[1];
7228: dsp_core.registers[DSP_REG_A0] = source[2];
7229:
7230: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7231: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7232: }
7233:
7234: static void dsp_mpy_m_x1_x0_a(void)
7235: {
7236: Uint32 source[3];
7237:
7238: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7239:
7240: dsp_core.registers[DSP_REG_A2] = source[0];
7241: dsp_core.registers[DSP_REG_A1] = source[1];
7242: dsp_core.registers[DSP_REG_A0] = source[2];
7243:
7244: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7245: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7246: }
7247:
7248: static void dsp_mpy_p_x1_x0_b(void)
7249: {
7250: Uint32 source[3];
7251:
7252: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7253:
7254: dsp_core.registers[DSP_REG_B2] = source[0];
7255: dsp_core.registers[DSP_REG_B1] = source[1];
7256: dsp_core.registers[DSP_REG_B0] = source[2];
7257:
7258: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7259: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7260: }
7261:
7262: static void dsp_mpy_m_x1_x0_b(void)
7263: {
7264: Uint32 source[3];
7265:
7266: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7267:
7268: dsp_core.registers[DSP_REG_B2] = source[0];
7269: dsp_core.registers[DSP_REG_B1] = source[1];
7270: dsp_core.registers[DSP_REG_B0] = source[2];
7271:
7272: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7273: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7274: }
7275:
7276: static void dsp_mpy_p_y1_y0_a(void)
7277: {
7278: Uint32 source[3];
7279:
7280: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7281:
7282: dsp_core.registers[DSP_REG_A2] = source[0];
7283: dsp_core.registers[DSP_REG_A1] = source[1];
7284: dsp_core.registers[DSP_REG_A0] = source[2];
7285:
7286: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7287: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7288: }
7289:
7290: static void dsp_mpy_m_y1_y0_a(void)
7291: {
7292: Uint32 source[3];
7293:
7294: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7295:
7296: dsp_core.registers[DSP_REG_A2] = source[0];
7297: dsp_core.registers[DSP_REG_A1] = source[1];
7298: dsp_core.registers[DSP_REG_A0] = source[2];
7299:
7300: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7301: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7302: }
7303:
7304: static void dsp_mpy_p_y1_y0_b(void)
7305: {
7306: Uint32 source[3];
7307:
7308: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7309:
7310: dsp_core.registers[DSP_REG_B2] = source[0];
7311: dsp_core.registers[DSP_REG_B1] = source[1];
7312: dsp_core.registers[DSP_REG_B0] = source[2];
7313:
7314: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7315: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7316: }
7317:
7318: static void dsp_mpy_m_y1_y0_b(void)
7319: {
7320: Uint32 source[3];
7321:
7322: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7323:
7324: dsp_core.registers[DSP_REG_B2] = source[0];
7325: dsp_core.registers[DSP_REG_B1] = source[1];
7326: dsp_core.registers[DSP_REG_B0] = source[2];
7327:
7328: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7329: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7330: }
7331:
7332: static void dsp_mpy_p_x0_y1_a(void)
7333: {
7334: Uint32 source[3];
7335:
7336: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7337:
7338: dsp_core.registers[DSP_REG_A2] = source[0];
7339: dsp_core.registers[DSP_REG_A1] = source[1];
7340: dsp_core.registers[DSP_REG_A0] = source[2];
7341:
7342: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7343: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7344: }
7345:
7346: static void dsp_mpy_m_x0_y1_a(void)
7347: {
7348: Uint32 source[3];
7349:
7350: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7351:
7352: dsp_core.registers[DSP_REG_A2] = source[0];
7353: dsp_core.registers[DSP_REG_A1] = source[1];
7354: dsp_core.registers[DSP_REG_A0] = source[2];
7355:
7356: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7357: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7358: }
7359:
7360: static void dsp_mpy_p_x0_y1_b(void)
7361: {
7362: Uint32 source[3];
7363:
7364: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7365:
7366: dsp_core.registers[DSP_REG_B2] = source[0];
7367: dsp_core.registers[DSP_REG_B1] = source[1];
7368: dsp_core.registers[DSP_REG_B0] = source[2];
7369:
7370: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7371: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7372: }
7373:
7374: static void dsp_mpy_m_x0_y1_b(void)
7375: {
7376: Uint32 source[3];
7377:
7378: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7379:
7380: dsp_core.registers[DSP_REG_B2] = source[0];
7381: dsp_core.registers[DSP_REG_B1] = source[1];
7382: dsp_core.registers[DSP_REG_B0] = source[2];
7383:
7384: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7385: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7386: }
7387:
7388: static void dsp_mpy_p_y0_x0_a(void)
7389: {
7390: Uint32 source[3];
7391:
7392: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7393:
7394: dsp_core.registers[DSP_REG_A2] = source[0];
7395: dsp_core.registers[DSP_REG_A1] = source[1];
7396: dsp_core.registers[DSP_REG_A0] = source[2];
7397:
7398: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7399: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7400: }
7401:
7402: static void dsp_mpy_m_y0_x0_a(void)
7403: {
7404: Uint32 source[3];
7405:
7406: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7407:
7408: dsp_core.registers[DSP_REG_A2] = source[0];
7409: dsp_core.registers[DSP_REG_A1] = source[1];
7410: dsp_core.registers[DSP_REG_A0] = source[2];
7411:
7412: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7413: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7414: }
7415:
7416: static void dsp_mpy_p_y0_x0_b(void)
7417: {
7418: Uint32 source[3];
7419:
7420: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7421:
7422: dsp_core.registers[DSP_REG_B2] = source[0];
7423: dsp_core.registers[DSP_REG_B1] = source[1];
7424: dsp_core.registers[DSP_REG_B0] = source[2];
7425:
7426: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7427: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7428: }
7429:
7430: static void dsp_mpy_m_y0_x0_b(void)
7431: {
7432: Uint32 source[3];
7433:
7434: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7435:
7436: dsp_core.registers[DSP_REG_B2] = source[0];
7437: dsp_core.registers[DSP_REG_B1] = source[1];
7438: dsp_core.registers[DSP_REG_B0] = source[2];
7439:
7440: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7441: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7442: }
7443:
7444: static void dsp_mpy_p_x1_y0_a(void)
7445: {
7446: Uint32 source[3];
7447:
7448: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7449:
7450: dsp_core.registers[DSP_REG_A2] = source[0];
7451: dsp_core.registers[DSP_REG_A1] = source[1];
7452: dsp_core.registers[DSP_REG_A0] = source[2];
7453:
7454: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7455: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7456: }
7457:
7458: static void dsp_mpy_m_x1_y0_a(void)
7459: {
7460: Uint32 source[3];
7461:
7462: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7463:
7464: dsp_core.registers[DSP_REG_A2] = source[0];
7465: dsp_core.registers[DSP_REG_A1] = source[1];
7466: dsp_core.registers[DSP_REG_A0] = source[2];
7467:
7468: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7469: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7470: }
7471:
7472: static void dsp_mpy_p_x1_y0_b(void)
7473: {
7474: Uint32 source[3];
7475:
7476: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7477:
7478: dsp_core.registers[DSP_REG_B2] = source[0];
7479: dsp_core.registers[DSP_REG_B1] = source[1];
7480: dsp_core.registers[DSP_REG_B0] = source[2];
7481:
7482: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7483: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7484: }
7485:
7486: static void dsp_mpy_m_x1_y0_b(void)
7487: {
7488: Uint32 source[3];
7489:
7490: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7491:
7492: dsp_core.registers[DSP_REG_B2] = source[0];
7493: dsp_core.registers[DSP_REG_B1] = source[1];
7494: dsp_core.registers[DSP_REG_B0] = source[2];
7495:
7496: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7497: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7498: }
7499:
7500: static void dsp_mpy_p_y1_x1_a(void)
7501: {
7502: Uint32 source[3];
7503:
7504: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7505:
7506: dsp_core.registers[DSP_REG_A2] = source[0];
7507: dsp_core.registers[DSP_REG_A1] = source[1];
7508: dsp_core.registers[DSP_REG_A0] = source[2];
7509:
7510: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7511: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7512: }
7513:
7514: static void dsp_mpy_m_y1_x1_a(void)
7515: {
7516: Uint32 source[3];
7517:
7518: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7519:
7520: dsp_core.registers[DSP_REG_A2] = source[0];
7521: dsp_core.registers[DSP_REG_A1] = source[1];
7522: dsp_core.registers[DSP_REG_A0] = source[2];
7523:
7524: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7525: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7526: }
7527:
7528: static void dsp_mpy_p_y1_x1_b(void)
7529: {
7530: Uint32 source[3];
7531:
7532: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7533:
7534: dsp_core.registers[DSP_REG_B2] = source[0];
7535: dsp_core.registers[DSP_REG_B1] = source[1];
7536: dsp_core.registers[DSP_REG_B0] = source[2];
7537:
7538: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7539: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7540: }
7541:
7542: static void dsp_mpy_m_y1_x1_b(void)
7543: {
7544: Uint32 source[3];
7545:
7546: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7547:
7548: dsp_core.registers[DSP_REG_B2] = source[0];
7549: dsp_core.registers[DSP_REG_B1] = source[1];
7550: dsp_core.registers[DSP_REG_B0] = source[2];
7551:
7552: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7553: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7554: }
7555:
7556: static void dsp_mpyr_p_x0_x0_a(void)
7557: {
7558: Uint32 source[3];
7559:
7560: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7561: dsp_rnd56(source);
7562:
7563: dsp_core.registers[DSP_REG_A2] = source[0];
7564: dsp_core.registers[DSP_REG_A1] = source[1];
7565: dsp_core.registers[DSP_REG_A0] = source[2];
7566:
7567: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7568: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7569: }
7570:
7571: static void dsp_mpyr_m_x0_x0_a(void)
7572: {
7573: Uint32 source[3];
7574:
7575: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7576: dsp_rnd56(source);
7577:
7578: dsp_core.registers[DSP_REG_A2] = source[0];
7579: dsp_core.registers[DSP_REG_A1] = source[1];
7580: dsp_core.registers[DSP_REG_A0] = source[2];
7581:
7582: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7583: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7584: }
7585:
7586: static void dsp_mpyr_p_x0_x0_b(void)
7587: {
7588: Uint32 source[3];
7589:
7590: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7591: dsp_rnd56(source);
7592:
7593: dsp_core.registers[DSP_REG_B2] = source[0];
7594: dsp_core.registers[DSP_REG_B1] = source[1];
7595: dsp_core.registers[DSP_REG_B0] = source[2];
7596:
7597: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7598: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7599: }
7600:
7601: static void dsp_mpyr_m_x0_x0_b(void)
7602: {
7603: Uint32 source[3];
7604:
7605:
7606: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7607: dsp_rnd56(source);
7608:
7609: dsp_core.registers[DSP_REG_B2] = source[0];
7610: dsp_core.registers[DSP_REG_B1] = source[1];
7611: dsp_core.registers[DSP_REG_B0] = source[2];
7612:
7613: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7614: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7615: }
7616:
7617: static void dsp_mpyr_p_y0_y0_a(void)
7618: {
7619: Uint32 source[3];
7620:
7621: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7622: dsp_rnd56(source);
7623:
7624: dsp_core.registers[DSP_REG_A2] = source[0];
7625: dsp_core.registers[DSP_REG_A1] = source[1];
7626: dsp_core.registers[DSP_REG_A0] = source[2];
7627:
7628: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7629: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7630: }
7631:
7632: static void dsp_mpyr_m_y0_y0_a(void)
7633: {
7634: Uint32 source[3];
7635:
7636: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7637: dsp_rnd56(source);
7638:
7639: dsp_core.registers[DSP_REG_A2] = source[0];
7640: dsp_core.registers[DSP_REG_A1] = source[1];
7641: dsp_core.registers[DSP_REG_A0] = source[2];
7642:
7643: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7644: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7645: }
7646:
7647: static void dsp_mpyr_p_y0_y0_b(void)
7648: {
7649: Uint32 source[3];
7650:
7651: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7652: dsp_rnd56(source);
7653:
7654: dsp_core.registers[DSP_REG_B2] = source[0];
7655: dsp_core.registers[DSP_REG_B1] = source[1];
7656: dsp_core.registers[DSP_REG_B0] = source[2];
7657:
7658: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7659: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7660: }
7661:
7662: static void dsp_mpyr_m_y0_y0_b(void)
7663: {
7664: Uint32 source[3];
7665:
7666: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7667: dsp_rnd56(source);
7668:
7669: dsp_core.registers[DSP_REG_B2] = source[0];
7670: dsp_core.registers[DSP_REG_B1] = source[1];
7671: dsp_core.registers[DSP_REG_B0] = source[2];
7672:
7673: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7674: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7675: }
7676:
7677: static void dsp_mpyr_p_x1_x0_a(void)
7678: {
7679: Uint32 source[3];
7680:
7681: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7682: dsp_rnd56(source);
7683:
7684: dsp_core.registers[DSP_REG_A2] = source[0];
7685: dsp_core.registers[DSP_REG_A1] = source[1];
7686: dsp_core.registers[DSP_REG_A0] = source[2];
7687:
7688: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7689: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7690: }
7691:
7692: static void dsp_mpyr_m_x1_x0_a(void)
7693: {
7694: Uint32 source[3];
7695:
7696: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7697: dsp_rnd56(source);
7698:
7699: dsp_core.registers[DSP_REG_A2] = source[0];
7700: dsp_core.registers[DSP_REG_A1] = source[1];
7701: dsp_core.registers[DSP_REG_A0] = source[2];
7702:
7703: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7704: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7705: }
7706:
7707: static void dsp_mpyr_p_x1_x0_b(void)
7708: {
7709: Uint32 source[3];
7710:
7711: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7712: dsp_rnd56(source);
7713:
7714: dsp_core.registers[DSP_REG_B2] = source[0];
7715: dsp_core.registers[DSP_REG_B1] = source[1];
7716: dsp_core.registers[DSP_REG_B0] = source[2];
7717:
7718: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7719: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7720: }
7721:
7722: static void dsp_mpyr_m_x1_x0_b(void)
7723: {
7724: Uint32 source[3];
7725:
7726: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7727: dsp_rnd56(source);
7728:
7729: dsp_core.registers[DSP_REG_B2] = source[0];
7730: dsp_core.registers[DSP_REG_B1] = source[1];
7731: dsp_core.registers[DSP_REG_B0] = source[2];
7732:
7733: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7734: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7735: }
7736:
7737: static void dsp_mpyr_p_y1_y0_a(void)
7738: {
7739: Uint32 source[3];
7740:
7741: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7742: dsp_rnd56(source);
7743:
7744: dsp_core.registers[DSP_REG_A2] = source[0];
7745: dsp_core.registers[DSP_REG_A1] = source[1];
7746: dsp_core.registers[DSP_REG_A0] = source[2];
7747:
7748: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7749: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7750: }
7751:
7752: static void dsp_mpyr_m_y1_y0_a(void)
7753: {
7754: Uint32 source[3];
7755:
7756: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7757: dsp_rnd56(source);
7758:
7759: dsp_core.registers[DSP_REG_A2] = source[0];
7760: dsp_core.registers[DSP_REG_A1] = source[1];
7761: dsp_core.registers[DSP_REG_A0] = source[2];
7762:
7763: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7764: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7765: }
7766:
7767: static void dsp_mpyr_p_y1_y0_b(void)
7768: {
7769: Uint32 source[3];
7770:
7771: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7772: dsp_rnd56(source);
7773:
7774: dsp_core.registers[DSP_REG_B2] = source[0];
7775: dsp_core.registers[DSP_REG_B1] = source[1];
7776: dsp_core.registers[DSP_REG_B0] = source[2];
7777:
7778: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7779: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7780: }
7781:
7782: static void dsp_mpyr_m_y1_y0_b(void)
7783: {
7784: Uint32 source[3];
7785:
7786: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7787: dsp_rnd56(source);
7788:
7789: dsp_core.registers[DSP_REG_B2] = source[0];
7790: dsp_core.registers[DSP_REG_B1] = source[1];
7791: dsp_core.registers[DSP_REG_B0] = source[2];
7792:
7793: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7794: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7795: }
7796:
7797: static void dsp_mpyr_p_x0_y1_a(void)
7798: {
7799: Uint32 source[3];
7800:
7801: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7802: dsp_rnd56(source);
7803:
7804: dsp_core.registers[DSP_REG_A2] = source[0];
7805: dsp_core.registers[DSP_REG_A1] = source[1];
7806: dsp_core.registers[DSP_REG_A0] = source[2];
7807:
7808: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7809: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7810: }
7811:
7812: static void dsp_mpyr_m_x0_y1_a(void)
7813: {
7814: Uint32 source[3];
7815:
7816: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7817: dsp_rnd56(source);
7818:
7819: dsp_core.registers[DSP_REG_A2] = source[0];
7820: dsp_core.registers[DSP_REG_A1] = source[1];
7821: dsp_core.registers[DSP_REG_A0] = source[2];
7822:
7823: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7824: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7825: }
7826:
7827: static void dsp_mpyr_p_x0_y1_b(void)
7828: {
7829: Uint32 source[3];
7830:
7831: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_PLUS);
7832: dsp_rnd56(source);
7833:
7834: dsp_core.registers[DSP_REG_B2] = source[0];
7835: dsp_core.registers[DSP_REG_B1] = source[1];
7836: dsp_core.registers[DSP_REG_B0] = source[2];
7837:
7838: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7839: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7840: }
7841:
7842: static void dsp_mpyr_m_x0_y1_b(void)
7843: {
7844: Uint32 source[3];
7845:
7846: dsp_mul56(dsp_core.registers[DSP_REG_X0], dsp_core.registers[DSP_REG_Y1], source, SIGN_MINUS);
7847: dsp_rnd56(source);
7848:
7849: dsp_core.registers[DSP_REG_B2] = source[0];
7850: dsp_core.registers[DSP_REG_B1] = source[1];
7851: dsp_core.registers[DSP_REG_B0] = source[2];
7852:
7853: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7854: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7855: }
7856:
7857: static void dsp_mpyr_p_y0_x0_a(void)
7858: {
7859: Uint32 source[3];
7860:
7861: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7862: dsp_rnd56(source);
7863:
7864: dsp_core.registers[DSP_REG_A2] = source[0];
7865: dsp_core.registers[DSP_REG_A1] = source[1];
7866: dsp_core.registers[DSP_REG_A0] = source[2];
7867:
7868: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7869: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7870: }
7871:
7872: static void dsp_mpyr_m_y0_x0_a(void)
7873: {
7874: Uint32 source[3];
7875:
7876: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7877: dsp_rnd56(source);
7878:
7879: dsp_core.registers[DSP_REG_A2] = source[0];
7880: dsp_core.registers[DSP_REG_A1] = source[1];
7881: dsp_core.registers[DSP_REG_A0] = source[2];
7882:
7883: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7884: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7885: }
7886:
7887: static void dsp_mpyr_p_y0_x0_b(void)
7888: {
7889: Uint32 source[3];
7890:
7891: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_PLUS);
7892: dsp_rnd56(source);
7893:
7894: dsp_core.registers[DSP_REG_B2] = source[0];
7895: dsp_core.registers[DSP_REG_B1] = source[1];
7896: dsp_core.registers[DSP_REG_B0] = source[2];
7897:
7898: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7899: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7900: }
7901:
7902: static void dsp_mpyr_m_y0_x0_b(void)
7903: {
7904: Uint32 source[3];
7905:
7906: dsp_mul56(dsp_core.registers[DSP_REG_Y0], dsp_core.registers[DSP_REG_X0], source, SIGN_MINUS);
7907: dsp_rnd56(source);
7908:
7909: dsp_core.registers[DSP_REG_B2] = source[0];
7910: dsp_core.registers[DSP_REG_B1] = source[1];
7911: dsp_core.registers[DSP_REG_B0] = source[2];
7912:
7913: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7914: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7915: }
7916:
7917: static void dsp_mpyr_p_x1_y0_a(void)
7918: {
7919: Uint32 source[3];
7920:
7921: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7922: dsp_rnd56(source);
7923:
7924: dsp_core.registers[DSP_REG_A2] = source[0];
7925: dsp_core.registers[DSP_REG_A1] = source[1];
7926: dsp_core.registers[DSP_REG_A0] = source[2];
7927:
7928: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7929: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7930: }
7931:
7932: static void dsp_mpyr_m_x1_y0_a(void)
7933: {
7934: Uint32 source[3];
7935:
7936: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7937: dsp_rnd56(source);
7938:
7939: dsp_core.registers[DSP_REG_A2] = source[0];
7940: dsp_core.registers[DSP_REG_A1] = source[1];
7941: dsp_core.registers[DSP_REG_A0] = source[2];
7942:
7943: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7944: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7945: }
7946:
7947: static void dsp_mpyr_p_x1_y0_b(void)
7948: {
7949: Uint32 source[3];
7950:
7951: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_PLUS);
7952: dsp_rnd56(source);
7953:
7954: dsp_core.registers[DSP_REG_B2] = source[0];
7955: dsp_core.registers[DSP_REG_B1] = source[1];
7956: dsp_core.registers[DSP_REG_B0] = source[2];
7957:
7958: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7959: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7960: }
7961:
7962: static void dsp_mpyr_m_x1_y0_b(void)
7963: {
7964: Uint32 source[3];
7965:
7966: dsp_mul56(dsp_core.registers[DSP_REG_X1], dsp_core.registers[DSP_REG_Y0], source, SIGN_MINUS);
7967: dsp_rnd56(source);
7968:
7969: dsp_core.registers[DSP_REG_B2] = source[0];
7970: dsp_core.registers[DSP_REG_B1] = source[1];
7971: dsp_core.registers[DSP_REG_B0] = source[2];
7972:
7973: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7974: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7975: }
7976:
7977: static void dsp_mpyr_p_y1_x1_a(void)
7978: {
7979: Uint32 source[3];
7980:
7981: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
7982: dsp_rnd56(source);
7983:
7984: dsp_core.registers[DSP_REG_A2] = source[0];
7985: dsp_core.registers[DSP_REG_A1] = source[1];
7986: dsp_core.registers[DSP_REG_A0] = source[2];
7987:
7988: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
7989: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
7990: }
7991:
7992: static void dsp_mpyr_m_y1_x1_a(void)
7993: {
7994: Uint32 source[3];
7995:
7996: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
7997: dsp_rnd56(source);
7998:
7999: dsp_core.registers[DSP_REG_A2] = source[0];
8000: dsp_core.registers[DSP_REG_A1] = source[1];
8001: dsp_core.registers[DSP_REG_A0] = source[2];
8002:
8003: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8004: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8005: }
8006:
8007: static void dsp_mpyr_p_y1_x1_b(void)
8008: {
8009: Uint32 source[3];
8010:
8011: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_PLUS);
8012: dsp_rnd56(source);
8013:
8014: dsp_core.registers[DSP_REG_B2] = source[0];
8015: dsp_core.registers[DSP_REG_B1] = source[1];
8016: dsp_core.registers[DSP_REG_B0] = source[2];
8017:
8018: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8019: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8020: }
8021:
8022: static void dsp_mpyr_m_y1_x1_b(void)
8023: {
8024: Uint32 source[3];
8025:
8026: dsp_mul56(dsp_core.registers[DSP_REG_Y1], dsp_core.registers[DSP_REG_X1], source, SIGN_MINUS);
8027: dsp_rnd56(source);
8028:
8029: dsp_core.registers[DSP_REG_B2] = source[0];
8030: dsp_core.registers[DSP_REG_B1] = source[1];
8031: dsp_core.registers[DSP_REG_B0] = source[2];
8032:
8033: dsp_ccr_update_e_u_n_z(source[0], source[1], source[2]);
8034: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8035: }
8036:
8037: static void dsp_neg_a(void)
8038: {
8039: Uint32 source[3], dest[3], overflowed;
8040:
8041: source[0] = dsp_core.registers[DSP_REG_A2];
8042: source[1] = dsp_core.registers[DSP_REG_A1];
8043: source[2] = dsp_core.registers[DSP_REG_A0];
8044:
8045: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8046:
8047: dest[0] = dest[1] = dest[2] = 0;
8048:
8049: dsp_sub56(source, dest);
8050:
8051: dsp_core.registers[DSP_REG_A2] = dest[0];
8052: dsp_core.registers[DSP_REG_A1] = dest[1];
8053: dsp_core.registers[DSP_REG_A0] = dest[2];
8054:
8055: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8056: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8057:
8058: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8059: }
8060:
8061: static void dsp_neg_b(void)
8062: {
8063: Uint32 source[3], dest[3], overflowed;
8064:
8065: source[0] = dsp_core.registers[DSP_REG_B2];
8066: source[1] = dsp_core.registers[DSP_REG_B1];
8067: source[2] = dsp_core.registers[DSP_REG_B0];
8068:
8069: overflowed = ((source[2]==0) && (source[1]==0) && (source[0]==0x80));
8070:
8071: dest[0] = dest[1] = dest[2] = 0;
8072:
8073: dsp_sub56(source, dest);
8074:
8075: dsp_core.registers[DSP_REG_B2] = dest[0];
8076: dsp_core.registers[DSP_REG_B1] = dest[1];
8077: dsp_core.registers[DSP_REG_B0] = dest[2];
8078:
8079: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8080: dsp_core.registers[DSP_REG_SR] |= (overflowed<<DSP_SR_L)|(overflowed<<DSP_SR_V);
8081:
8082: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8083: }
8084:
8085: static void dsp_nop(void)
8086: {
8087: }
8088:
8089: static void dsp_not_a(void)
8090: {
8091: dsp_core.registers[DSP_REG_A1] = ~dsp_core.registers[DSP_REG_A1];
8092: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8093:
8094: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8095: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8096: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8097: }
8098:
8099: static void dsp_not_b(void)
8100: {
8101: dsp_core.registers[DSP_REG_B1] = ~dsp_core.registers[DSP_REG_B1];
8102: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8103:
8104: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8105: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8106: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8107: }
8108:
8109: static void dsp_or_x0_a(void)
8110: {
8111: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X0];
8112: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8113:
8114: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8115: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8116: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8117: }
8118:
8119: static void dsp_or_x0_b(void)
8120: {
8121: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X0];
8122: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8123:
8124: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8125: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8126: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8127: }
8128:
8129: static void dsp_or_y0_a(void)
8130: {
8131: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y0];
8132: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8133:
8134: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8135: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8136: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8137: }
8138:
8139: static void dsp_or_y0_b(void)
8140: {
8141: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y0];
8142: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8143:
8144: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8145: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8146: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8147: }
8148:
8149: static void dsp_or_x1_a(void)
8150: {
8151: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_X1];
8152: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8153:
8154: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8155: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8156: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8157: }
8158:
8159: static void dsp_or_x1_b(void)
8160: {
8161: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_X1];
8162: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8163:
8164: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8165: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8166: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8167: }
8168:
8169: static void dsp_or_y1_a(void)
8170: {
8171: dsp_core.registers[DSP_REG_A1] |= dsp_core.registers[DSP_REG_Y1];
8172: dsp_core.registers[DSP_REG_A1] &= BITMASK(24); /* FIXME: useless ? */
8173:
8174: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8175: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8176: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8177: }
8178:
8179: static void dsp_or_y1_b(void)
8180: {
8181: dsp_core.registers[DSP_REG_B1] |= dsp_core.registers[DSP_REG_Y1];
8182: dsp_core.registers[DSP_REG_B1] &= BITMASK(24); /* FIXME: useless ? */
8183:
8184: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8185: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8186: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8187: }
8188:
8189: static void dsp_rnd_a(void)
8190: {
8191: Uint32 dest[3];
8192:
8193: dest[0] = dsp_core.registers[DSP_REG_A2];
8194: dest[1] = dsp_core.registers[DSP_REG_A1];
8195: dest[2] = dsp_core.registers[DSP_REG_A0];
8196:
8197: dsp_rnd56(dest);
8198:
8199: dsp_core.registers[DSP_REG_A2] = dest[0];
8200: dsp_core.registers[DSP_REG_A1] = dest[1];
8201: dsp_core.registers[DSP_REG_A0] = dest[2];
8202:
8203: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8204: }
8205:
8206: static void dsp_rnd_b(void)
8207: {
8208: Uint32 dest[3];
8209:
8210: dest[0] = dsp_core.registers[DSP_REG_B2];
8211: dest[1] = dsp_core.registers[DSP_REG_B1];
8212: dest[2] = dsp_core.registers[DSP_REG_B0];
8213:
8214: dsp_rnd56(dest);
8215:
8216: dsp_core.registers[DSP_REG_B2] = dest[0];
8217: dsp_core.registers[DSP_REG_B1] = dest[1];
8218: dsp_core.registers[DSP_REG_B0] = dest[2];
8219:
8220: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8221: }
8222:
8223: static void dsp_rol_a(void)
8224: {
8225: Uint32 newcarry;
8226:
8227: newcarry = (dsp_core.registers[DSP_REG_A1]>>23) & 1;
8228:
8229: dsp_core.registers[DSP_REG_A1] <<= 1;
8230: dsp_core.registers[DSP_REG_A1] |= newcarry;
8231: dsp_core.registers[DSP_REG_A1] &= BITMASK(24);
8232:
8233: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8234: dsp_core.registers[DSP_REG_SR] |= newcarry;
8235: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_A1]>>23) & 1)<<DSP_SR_N;
8236: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8237: }
8238:
8239: static void dsp_rol_b(void)
8240: {
8241: Uint32 newcarry;
8242:
8243: newcarry = (dsp_core.registers[DSP_REG_B1]>>23) & 1;
8244:
8245: dsp_core.registers[DSP_REG_B1] <<= 1;
8246: dsp_core.registers[DSP_REG_B1] |= newcarry;
8247: dsp_core.registers[DSP_REG_B1] &= BITMASK(24);
8248:
8249: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8250: dsp_core.registers[DSP_REG_SR] |= newcarry;
8251: dsp_core.registers[DSP_REG_SR] |= ((dsp_core.registers[DSP_REG_B1]>>23) & 1)<<DSP_SR_N;
8252: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8253: }
8254:
8255: static void dsp_ror_a(void)
8256: {
8257: Uint32 newcarry;
8258:
8259: newcarry = dsp_core.registers[DSP_REG_A1] & 1;
8260:
8261: dsp_core.registers[DSP_REG_A1] >>= 1;
8262: dsp_core.registers[DSP_REG_A1] |= newcarry<<23;
8263:
8264: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8265: dsp_core.registers[DSP_REG_SR] |= newcarry;
8266: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8267: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_A1]==0)<<DSP_SR_Z;
8268: }
8269:
8270: static void dsp_ror_b(void)
8271: {
8272: Uint32 newcarry;
8273:
8274: newcarry = dsp_core.registers[DSP_REG_B1] & 1;
8275:
8276: dsp_core.registers[DSP_REG_B1] >>= 1;
8277: dsp_core.registers[DSP_REG_B1] |= newcarry<<23;
8278:
8279: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_C)|(1<<DSP_SR_N)|(1<<DSP_SR_Z)|(1<<DSP_SR_V));
8280: dsp_core.registers[DSP_REG_SR] |= newcarry;
8281: dsp_core.registers[DSP_REG_SR] |= newcarry<<DSP_SR_N;
8282: dsp_core.registers[DSP_REG_SR] |= (dsp_core.registers[DSP_REG_B1]==0)<<DSP_SR_Z;
8283: }
8284:
8285: static void dsp_sbc_x_a(void)
8286: {
8287: Uint32 source[3], dest[3], curcarry;
8288: Uint16 newsr;
8289:
8290: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8291:
8292: dest[2] = dsp_core.registers[DSP_REG_A0];
8293: dest[1] = dsp_core.registers[DSP_REG_A1];
8294: dest[0] = dsp_core.registers[DSP_REG_A2];
8295:
8296: source[2] = dsp_core.registers[DSP_REG_X0];
8297: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8298: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8299:
8300: newsr = dsp_sub56(source, dest);
8301:
8302: if (curcarry) {
8303: source[0]=0; source[1]=0; source[2]=1;
8304: newsr |= dsp_sub56(source, dest);
8305: }
8306:
8307: dsp_core.registers[DSP_REG_A2] = dest[0];
8308: dsp_core.registers[DSP_REG_A1] = dest[1];
8309: dsp_core.registers[DSP_REG_A0] = dest[2];
8310:
8311: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8312:
8313: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8314: dsp_core.registers[DSP_REG_SR] |= newsr;
8315: }
8316:
8317: static void dsp_sbc_x_b(void)
8318: {
8319: Uint32 source[3], dest[3], curcarry;
8320: Uint16 newsr;
8321:
8322: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8323:
8324: dest[2] = dsp_core.registers[DSP_REG_B0];
8325: dest[1] = dsp_core.registers[DSP_REG_B1];
8326: dest[0] = dsp_core.registers[DSP_REG_B2];
8327:
8328: source[2] = dsp_core.registers[DSP_REG_X0];
8329: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8330: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8331:
8332: newsr = dsp_sub56(source, dest);
8333:
8334: if (curcarry) {
8335: source[0]=0; source[1]=0; source[2]=1;
8336: newsr |= dsp_sub56(source, dest);
8337: }
8338:
8339: dsp_core.registers[DSP_REG_B2] = dest[0];
8340: dsp_core.registers[DSP_REG_B1] = dest[1];
8341: dsp_core.registers[DSP_REG_B0] = dest[2];
8342:
8343: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8344:
8345: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8346: dsp_core.registers[DSP_REG_SR] |= newsr;
8347: }
8348:
8349: static void dsp_sbc_y_a(void)
8350: {
8351: Uint32 source[3], dest[3], curcarry;
1.1.1.2 root 8352: Uint16 newsr;
1.1 root 8353:
1.1.1.6 root 8354: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8355:
8356: dest[2] = dsp_core.registers[DSP_REG_A0];
8357: dest[1] = dsp_core.registers[DSP_REG_A1];
8358: dest[0] = dsp_core.registers[DSP_REG_A2];
8359:
8360: source[2] = dsp_core.registers[DSP_REG_Y0];
8361: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8362: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8363:
8364: newsr = dsp_sub56(source, dest);
8365:
8366: if (curcarry) {
8367: source[0]=0; source[1]=0; source[2]=1;
8368: newsr |= dsp_sub56(source, dest);
8369: }
8370:
8371: dsp_core.registers[DSP_REG_A2] = dest[0];
8372: dsp_core.registers[DSP_REG_A1] = dest[1];
8373: dsp_core.registers[DSP_REG_A0] = dest[2];
8374:
8375: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8376:
8377: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8378: dsp_core.registers[DSP_REG_SR] |= newsr;
8379: }
8380:
8381: static void dsp_sbc_y_b(void)
8382: {
8383: Uint32 source[3], dest[3], curcarry;
8384: Uint16 newsr;
8385:
8386: curcarry = (dsp_core.registers[DSP_REG_SR]>>(DSP_SR_C)) & 1;
8387:
8388: dest[2] = dsp_core.registers[DSP_REG_B0];
8389: dest[1] = dsp_core.registers[DSP_REG_B1];
8390: dest[0] = dsp_core.registers[DSP_REG_B2];
8391:
8392: source[2] = dsp_core.registers[DSP_REG_Y0];
8393: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8394: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8395:
8396: newsr = dsp_sub56(source, dest);
8397:
8398: if (curcarry) {
8399: source[0]=0; source[1]=0; source[2]=1;
8400: newsr |= dsp_sub56(source, dest);
1.1 root 8401: }
8402:
1.1.1.6 root 8403: dsp_core.registers[DSP_REG_B2] = dest[0];
8404: dsp_core.registers[DSP_REG_B1] = dest[1];
8405: dsp_core.registers[DSP_REG_B0] = dest[2];
8406:
8407: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8408:
8409: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8410: dsp_core.registers[DSP_REG_SR] |= newsr;
8411: }
8412:
8413: static void dsp_sub_b_a(void)
8414: {
8415: Uint32 source[3], dest[3];
8416: Uint16 newsr;
8417:
8418: dest[2] = dsp_core.registers[DSP_REG_A0];
8419: dest[1] = dsp_core.registers[DSP_REG_A1];
8420: dest[0] = dsp_core.registers[DSP_REG_A2];
8421:
8422: source[2] = dsp_core.registers[DSP_REG_B0];
8423: source[1] = dsp_core.registers[DSP_REG_B1];
8424: source[0] = dsp_core.registers[DSP_REG_B2];
8425:
1.1 root 8426: newsr = dsp_sub56(source, dest);
8427:
1.1.1.6 root 8428: dsp_core.registers[DSP_REG_A2] = dest[0];
8429: dsp_core.registers[DSP_REG_A1] = dest[1];
8430: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8431:
1.1.1.6 root 8432: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8433:
1.1.1.6 root 8434: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8435: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8436: }
8437:
1.1.1.6 root 8438: static void dsp_sub_a_b(void)
1.1 root 8439: {
1.1.1.6 root 8440: Uint32 source[3], dest[3];
1.1.1.2 root 8441: Uint16 newsr;
1.1 root 8442:
1.1.1.6 root 8443: dest[2] = dsp_core.registers[DSP_REG_B0];
8444: dest[1] = dsp_core.registers[DSP_REG_B1];
8445: dest[0] = dsp_core.registers[DSP_REG_B2];
8446:
8447: source[2] = dsp_core.registers[DSP_REG_A0];
8448: source[1] = dsp_core.registers[DSP_REG_A1];
8449: source[0] = dsp_core.registers[DSP_REG_A2];
8450:
8451: newsr = dsp_sub56(source, dest);
8452:
8453: dsp_core.registers[DSP_REG_B2] = dest[0];
8454: dsp_core.registers[DSP_REG_B1] = dest[1];
8455: dsp_core.registers[DSP_REG_B0] = dest[2];
8456:
8457: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8458:
8459: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8460: dsp_core.registers[DSP_REG_SR] |= newsr;
8461: }
8462:
8463: static void dsp_sub_x_a(void)
8464: {
8465: Uint32 source[3], dest[3];
8466: Uint16 newsr;
8467:
8468: dest[2] = dsp_core.registers[DSP_REG_A0];
8469: dest[1] = dsp_core.registers[DSP_REG_A1];
8470: dest[0] = dsp_core.registers[DSP_REG_A2];
8471:
8472: source[2] = dsp_core.registers[DSP_REG_X0];
8473: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8474: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8475:
8476: newsr = dsp_sub56(source, dest);
8477:
8478: dsp_core.registers[DSP_REG_A2] = dest[0];
8479: dsp_core.registers[DSP_REG_A1] = dest[1];
8480: dsp_core.registers[DSP_REG_A0] = dest[2];
8481:
8482: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8483:
8484: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8485: dsp_core.registers[DSP_REG_SR] |= newsr;
8486: }
8487:
8488: static void dsp_sub_x_b(void)
8489: {
8490: Uint32 source[3], dest[3];
8491: Uint16 newsr;
8492:
8493: dest[2] = dsp_core.registers[DSP_REG_B0];
8494: dest[1] = dsp_core.registers[DSP_REG_B1];
8495: dest[0] = dsp_core.registers[DSP_REG_B2];
8496:
8497: source[2] = dsp_core.registers[DSP_REG_X0];
8498: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8499: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8500:
8501: newsr = dsp_sub56(source, dest);
8502:
8503: dsp_core.registers[DSP_REG_B2] = dest[0];
8504: dsp_core.registers[DSP_REG_B1] = dest[1];
8505: dsp_core.registers[DSP_REG_B0] = dest[2];
8506:
8507: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8508:
8509: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8510: dsp_core.registers[DSP_REG_SR] |= newsr;
8511: }
8512:
8513: static void dsp_sub_y_a(void)
8514: {
8515: Uint32 source[3], dest[3];
8516: Uint16 newsr;
8517:
8518: dest[2] = dsp_core.registers[DSP_REG_A0];
8519: dest[1] = dsp_core.registers[DSP_REG_A1];
8520: dest[0] = dsp_core.registers[DSP_REG_A2];
8521:
8522: source[2] = dsp_core.registers[DSP_REG_Y0];
8523: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8524: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8525:
8526: newsr = dsp_sub56(source, dest);
8527:
8528: dsp_core.registers[DSP_REG_A2] = dest[0];
8529: dsp_core.registers[DSP_REG_A1] = dest[1];
8530: dsp_core.registers[DSP_REG_A0] = dest[2];
8531:
8532: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8533:
8534: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8535: dsp_core.registers[DSP_REG_SR] |= newsr;
8536: }
8537:
8538: static void dsp_sub_y_b(void)
8539: {
8540: Uint32 source[3], dest[3];
8541: Uint16 newsr;
8542:
8543: dest[2] = dsp_core.registers[DSP_REG_B0];
8544: dest[1] = dsp_core.registers[DSP_REG_B1];
8545: dest[0] = dsp_core.registers[DSP_REG_B2];
8546:
8547: source[2] = dsp_core.registers[DSP_REG_Y0];
8548: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8549: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8550:
8551: newsr = dsp_sub56(source, dest);
8552:
8553: dsp_core.registers[DSP_REG_B2] = dest[0];
8554: dsp_core.registers[DSP_REG_B1] = dest[1];
8555: dsp_core.registers[DSP_REG_B0] = dest[2];
8556:
8557: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8558:
8559: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8560: dsp_core.registers[DSP_REG_SR] |= newsr;
8561: }
8562:
8563: static void dsp_sub_x0_a(void)
8564: {
8565: Uint32 source[3], dest[3];
8566: Uint16 newsr;
8567:
8568: dest[2] = dsp_core.registers[DSP_REG_A0];
8569: dest[1] = dsp_core.registers[DSP_REG_A1];
8570: dest[0] = dsp_core.registers[DSP_REG_A2];
8571:
8572: source[2] = 0;
8573: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 8574: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8575:
8576: newsr = dsp_sub56(source, dest);
8577:
8578: dsp_core.registers[DSP_REG_A2] = dest[0];
8579: dsp_core.registers[DSP_REG_A1] = dest[1];
8580: dsp_core.registers[DSP_REG_A0] = dest[2];
8581:
8582: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8583:
8584: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8585: dsp_core.registers[DSP_REG_SR] |= newsr;
8586: }
8587:
8588: static void dsp_sub_x0_b(void)
8589: {
8590: Uint32 source[3], dest[3];
8591: Uint16 newsr;
8592:
8593: dest[2] = dsp_core.registers[DSP_REG_B0];
8594: dest[1] = dsp_core.registers[DSP_REG_B1];
8595: dest[0] = dsp_core.registers[DSP_REG_B2];
8596:
8597: source[2] = 0;
8598: source[1] = dsp_core.registers[DSP_REG_X0];
1.1.1.7 root 8599: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8600:
8601: newsr = dsp_sub56(source, dest);
8602:
8603: dsp_core.registers[DSP_REG_B2] = dest[0];
8604: dsp_core.registers[DSP_REG_B1] = dest[1];
8605: dsp_core.registers[DSP_REG_B0] = dest[2];
8606:
8607: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8608:
8609: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8610: dsp_core.registers[DSP_REG_SR] |= newsr;
8611: }
8612:
8613: static void dsp_sub_y0_a(void)
8614: {
8615: Uint32 source[3], dest[3];
8616: Uint16 newsr;
8617:
8618: dest[2] = dsp_core.registers[DSP_REG_A0];
8619: dest[1] = dsp_core.registers[DSP_REG_A1];
8620: dest[0] = dsp_core.registers[DSP_REG_A2];
8621:
8622: source[2] = 0;
8623: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 8624: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8625:
8626: newsr = dsp_sub56(source, dest);
1.1 root 8627:
1.1.1.6 root 8628: dsp_core.registers[DSP_REG_A2] = dest[0];
8629: dsp_core.registers[DSP_REG_A1] = dest[1];
8630: dsp_core.registers[DSP_REG_A0] = dest[2];
8631:
8632: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8633:
8634: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8635: dsp_core.registers[DSP_REG_SR] |= newsr;
8636: }
8637:
8638: static void dsp_sub_y0_b(void)
8639: {
8640: Uint32 source[3], dest[3];
8641: Uint16 newsr;
8642:
8643: dest[2] = dsp_core.registers[DSP_REG_B0];
8644: dest[1] = dsp_core.registers[DSP_REG_B1];
8645: dest[0] = dsp_core.registers[DSP_REG_B2];
8646:
8647: source[2] = 0;
8648: source[1] = dsp_core.registers[DSP_REG_Y0];
1.1.1.7 root 8649: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8650:
8651: newsr = dsp_sub56(source, dest);
8652:
8653: dsp_core.registers[DSP_REG_B2] = dest[0];
8654: dsp_core.registers[DSP_REG_B1] = dest[1];
8655: dsp_core.registers[DSP_REG_B0] = dest[2];
8656:
8657: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8658:
8659: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8660: dsp_core.registers[DSP_REG_SR] |= newsr;
8661: }
8662:
8663: static void dsp_sub_x1_a(void)
8664: {
8665: Uint32 source[3], dest[3];
8666: Uint16 newsr;
8667:
8668: dest[2] = dsp_core.registers[DSP_REG_A0];
8669: dest[1] = dsp_core.registers[DSP_REG_A1];
8670: dest[0] = dsp_core.registers[DSP_REG_A2];
8671:
8672: source[2] = 0;
8673: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8674: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8675:
8676: newsr = dsp_sub56(source, dest);
8677:
8678: dsp_core.registers[DSP_REG_A2] = dest[0];
8679: dsp_core.registers[DSP_REG_A1] = dest[1];
8680: dsp_core.registers[DSP_REG_A0] = dest[2];
8681:
8682: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8683:
8684: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8685: dsp_core.registers[DSP_REG_SR] |= newsr;
8686: }
8687:
8688: static void dsp_sub_x1_b(void)
8689: {
8690: Uint32 source[3], dest[3];
8691: Uint16 newsr;
8692:
8693: dest[2] = dsp_core.registers[DSP_REG_B0];
8694: dest[1] = dsp_core.registers[DSP_REG_B1];
8695: dest[0] = dsp_core.registers[DSP_REG_B2];
8696:
8697: source[2] = 0;
8698: source[1] = dsp_core.registers[DSP_REG_X1];
1.1.1.7 root 8699: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8700:
8701: newsr = dsp_sub56(source, dest);
8702:
8703: dsp_core.registers[DSP_REG_B2] = dest[0];
8704: dsp_core.registers[DSP_REG_B1] = dest[1];
8705: dsp_core.registers[DSP_REG_B0] = dest[2];
8706:
8707: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8708:
8709: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8710: dsp_core.registers[DSP_REG_SR] |= newsr;
8711: }
8712:
8713: static void dsp_sub_y1_a(void)
8714: {
8715: Uint32 source[3], dest[3];
8716: Uint16 newsr;
8717:
8718: dest[2] = dsp_core.registers[DSP_REG_A0];
8719: dest[1] = dsp_core.registers[DSP_REG_A1];
8720: dest[0] = dsp_core.registers[DSP_REG_A2];
8721:
8722: source[2] = 0;
8723: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8724: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8725:
8726: newsr = dsp_sub56(source, dest);
8727:
8728: dsp_core.registers[DSP_REG_A2] = dest[0];
8729: dsp_core.registers[DSP_REG_A1] = dest[1];
8730: dsp_core.registers[DSP_REG_A0] = dest[2];
8731:
8732: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8733:
8734: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8735: dsp_core.registers[DSP_REG_SR] |= newsr;
8736: }
8737:
8738: static void dsp_sub_y1_b(void)
8739: {
8740: Uint32 source[3], dest[3];
8741: Uint16 newsr;
8742:
8743: dest[2] = dsp_core.registers[DSP_REG_B0];
8744: dest[1] = dsp_core.registers[DSP_REG_B1];
8745: dest[0] = dsp_core.registers[DSP_REG_B2];
8746:
8747: source[2] = 0;
8748: source[1] = dsp_core.registers[DSP_REG_Y1];
1.1.1.7 root 8749: source[0] = source[1] & (1<<23) ? 0xff : 0x0;
1.1.1.6 root 8750:
8751: newsr = dsp_sub56(source, dest);
8752:
8753: dsp_core.registers[DSP_REG_B2] = dest[0];
8754: dsp_core.registers[DSP_REG_B1] = dest[1];
8755: dsp_core.registers[DSP_REG_B0] = dest[2];
8756:
8757: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8758:
8759: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8760: dsp_core.registers[DSP_REG_SR] |= newsr;
8761: }
8762:
8763: static void dsp_subl_a(void)
8764: {
8765: Uint32 source[3], dest[3];
8766: Uint16 newsr;
8767:
8768: dest[0] = dsp_core.registers[DSP_REG_A2];
8769: dest[1] = dsp_core.registers[DSP_REG_A1];
8770: dest[2] = dsp_core.registers[DSP_REG_A0];
1.1 root 8771: newsr = dsp_asl56(dest);
8772:
1.1.1.6 root 8773: source[0] = dsp_core.registers[DSP_REG_B2];
8774: source[1] = dsp_core.registers[DSP_REG_B1];
8775: source[2] = dsp_core.registers[DSP_REG_B0];
1.1 root 8776: newsr |= dsp_sub56(source, dest);
8777:
1.1.1.6 root 8778: dsp_core.registers[DSP_REG_A2] = dest[0];
8779: dsp_core.registers[DSP_REG_A1] = dest[1];
8780: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8781:
1.1.1.6 root 8782: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8783:
1.1.1.6 root 8784: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8785: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8786: }
8787:
1.1.1.6 root 8788: static void dsp_subl_b(void)
1.1 root 8789: {
1.1.1.6 root 8790: Uint32 source[3], dest[3];
1.1.1.2 root 8791: Uint16 newsr;
1.1 root 8792:
1.1.1.6 root 8793: dest[0] = dsp_core.registers[DSP_REG_B2];
8794: dest[1] = dsp_core.registers[DSP_REG_B1];
8795: dest[2] = dsp_core.registers[DSP_REG_B0];
8796: newsr = dsp_asl56(dest);
1.1 root 8797:
1.1.1.6 root 8798: source[0] = dsp_core.registers[DSP_REG_A2];
8799: source[1] = dsp_core.registers[DSP_REG_A1];
8800: source[2] = dsp_core.registers[DSP_REG_A0];
8801: newsr |= dsp_sub56(source, dest);
8802:
8803: dsp_core.registers[DSP_REG_B2] = dest[0];
8804: dsp_core.registers[DSP_REG_B1] = dest[1];
8805: dsp_core.registers[DSP_REG_B0] = dest[2];
8806:
8807: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8808:
8809: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8810: dsp_core.registers[DSP_REG_SR] |= newsr;
8811: }
8812:
8813: static void dsp_subr_a(void)
8814: {
8815: Uint32 source[3], dest[3];
8816: Uint16 newsr;
8817:
8818: dest[0] = dsp_core.registers[DSP_REG_A2];
8819: dest[1] = dsp_core.registers[DSP_REG_A1];
8820: dest[2] = dsp_core.registers[DSP_REG_A0];
8821:
1.1 root 8822: newsr = dsp_asr56(dest);
8823:
1.1.1.6 root 8824: source[0] = dsp_core.registers[DSP_REG_B2];
8825: source[1] = dsp_core.registers[DSP_REG_B1];
8826: source[2] = dsp_core.registers[DSP_REG_B0];
8827:
1.1 root 8828: newsr |= dsp_sub56(source, dest);
8829:
1.1.1.6 root 8830: dsp_core.registers[DSP_REG_A2] = dest[0];
8831: dsp_core.registers[DSP_REG_A1] = dest[1];
8832: dsp_core.registers[DSP_REG_A0] = dest[2];
1.1.1.2 root 8833:
1.1.1.6 root 8834: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
1.1 root 8835:
1.1.1.6 root 8836: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8837: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8838: }
8839:
1.1.1.6 root 8840: static void dsp_subr_b(void)
1.1 root 8841: {
1.1.1.6 root 8842: Uint32 source[3], dest[3];
8843: Uint16 newsr;
1.1 root 8844:
1.1.1.6 root 8845: dest[0] = dsp_core.registers[DSP_REG_B2];
8846: dest[1] = dsp_core.registers[DSP_REG_B1];
8847: dest[2] = dsp_core.registers[DSP_REG_B0];
8848:
8849: newsr = dsp_asr56(dest);
1.1 root 8850:
1.1.1.6 root 8851: source[0] = dsp_core.registers[DSP_REG_A2];
8852: source[1] = dsp_core.registers[DSP_REG_A1];
8853: source[2] = dsp_core.registers[DSP_REG_A0];
8854:
8855: newsr |= dsp_sub56(source, dest);
1.1 root 8856:
1.1.1.6 root 8857: dsp_core.registers[DSP_REG_B2] = dest[0];
8858: dsp_core.registers[DSP_REG_B1] = dest[1];
8859: dsp_core.registers[DSP_REG_B0] = dest[2];
8860:
8861: dsp_ccr_update_e_u_n_z(dest[0], dest[1], dest[2]);
8862:
8863: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-((1<<DSP_SR_V)|(1<<DSP_SR_C));
8864: dsp_core.registers[DSP_REG_SR] |= newsr;
1.1 root 8865: }
8866:
1.1.1.6 root 8867: static void dsp_tfr_b_a(void)
1.1 root 8868: {
1.1.1.6 root 8869: dsp_core.registers[DSP_REG_A0] = dsp_core.registers[DSP_REG_B0];
8870: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_B1];
8871: dsp_core.registers[DSP_REG_A2] = dsp_core.registers[DSP_REG_B2];
8872: }
1.1 root 8873:
1.1.1.6 root 8874: static void dsp_tfr_a_b(void)
8875: {
8876: dsp_core.registers[DSP_REG_B0] = dsp_core.registers[DSP_REG_A0];
8877: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_A1];
8878: dsp_core.registers[DSP_REG_B2] = dsp_core.registers[DSP_REG_A2];
8879: }
8880:
8881: static void dsp_tfr_x0_a(void)
8882: {
8883: dsp_core.registers[DSP_REG_A0] = 0;
8884: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_X0];
8885: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
8886: dsp_core.registers[DSP_REG_A2] = 0xff;
8887: else
8888: dsp_core.registers[DSP_REG_A2] = 0x0;
8889: }
8890:
8891: static void dsp_tfr_x0_b(void)
8892: {
8893: dsp_core.registers[DSP_REG_B0] = 0;
8894: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_X0];
8895: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
8896: dsp_core.registers[DSP_REG_B2] = 0xff;
8897: else
8898: dsp_core.registers[DSP_REG_B2] = 0x0;
8899: }
8900:
8901: static void dsp_tfr_y0_a(void)
8902: {
8903: dsp_core.registers[DSP_REG_A0] = 0;
8904: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_Y0];
8905: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
8906: dsp_core.registers[DSP_REG_A2] = 0xff;
8907: else
8908: dsp_core.registers[DSP_REG_A2] = 0x0;
8909: }
8910:
8911: static void dsp_tfr_y0_b(void)
8912: {
8913: dsp_core.registers[DSP_REG_B0] = 0;
8914: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_Y0];
8915: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
8916: dsp_core.registers[DSP_REG_B2] = 0xff;
8917: else
8918: dsp_core.registers[DSP_REG_B2] = 0x0;
8919: }
8920:
8921: static void dsp_tfr_x1_a(void)
8922: {
8923: dsp_core.registers[DSP_REG_A0] = 0;
8924: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_X1];
8925: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
8926: dsp_core.registers[DSP_REG_A2] = 0xff;
8927: else
8928: dsp_core.registers[DSP_REG_A2] = 0x0;
8929: }
8930:
8931: static void dsp_tfr_x1_b(void)
8932: {
8933: dsp_core.registers[DSP_REG_B0] = 0;
8934: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_X1];
8935: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
8936: dsp_core.registers[DSP_REG_B2] = 0xff;
8937: else
8938: dsp_core.registers[DSP_REG_B2] = 0x0;
8939: }
8940:
8941: static void dsp_tfr_y1_a(void)
8942: {
8943: dsp_core.registers[DSP_REG_A0] = 0;
8944: dsp_core.registers[DSP_REG_A1] = dsp_core.registers[DSP_REG_Y1];
8945: if (dsp_core.registers[DSP_REG_A1] & (1<<23))
8946: dsp_core.registers[DSP_REG_A2] = 0xff;
8947: else
8948: dsp_core.registers[DSP_REG_A2] = 0x0;
8949: }
8950:
8951: static void dsp_tfr_y1_b(void)
8952: {
8953: dsp_core.registers[DSP_REG_B0] = 0;
8954: dsp_core.registers[DSP_REG_B1] = dsp_core.registers[DSP_REG_Y1];
8955: if (dsp_core.registers[DSP_REG_B1] & (1<<23))
8956: dsp_core.registers[DSP_REG_B2] = 0xff;
8957: else
8958: dsp_core.registers[DSP_REG_B2] = 0x0;
8959: }
8960:
8961: static void dsp_tst_a(void)
8962: {
8963: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_A2],
1.1.1.7 root 8964: dsp_core.registers[DSP_REG_A1],
8965: dsp_core.registers[DSP_REG_A0]);
1.1.1.6 root 8966:
8967: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
8968: }
8969:
8970: static void dsp_tst_b(void)
8971: {
8972: dsp_ccr_update_e_u_n_z( dsp_core.registers[DSP_REG_B2],
1.1.1.7 root 8973: dsp_core.registers[DSP_REG_B1],
8974: dsp_core.registers[DSP_REG_B0]);
1.1 root 8975:
1.1.1.6 root 8976: dsp_core.registers[DSP_REG_SR] &= BITMASK(16)-(1<<DSP_SR_V);
1.1 root 8977: }
8978:
1.1.1.2 root 8979: /*
8980: vim:ts=4:sw=4:
8981: */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.