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1.1 root 1: /*
2: Hatari - ioMemTabFalcon.c
3:
1.1.1.9 root 4: This file is distributed under the GNU General Public License, version 2
5: or at your option any later version. Read the file gpl.txt for details.
1.1 root 6:
7: Table with hardware IO handlers for the Falcon.
8: */
1.1.1.3 root 9: const char IoMemTabFalc_fileid[] = "Hatari ioMemTabFalcon.c : " __DATE__ " " __TIME__;
1.1 root 10:
11: #include "main.h"
12: #include "fdc.h"
1.1.1.9 root 13: #include "acia.h"
1.1 root 14: #include "ioMem.h"
15: #include "ioMemTables.h"
1.1.1.6 root 16: #include "m68000.h"
1.1 root 17: #include "joy.h"
18: #include "mfp.h"
19: #include "midi.h"
20: #include "nvram.h"
21: #include "psg.h"
22: #include "rs232.h"
23: #include "rtc.h"
1.1.1.6 root 24: #include "screen.h"
1.1 root 25: #include "blitter.h"
1.1.1.5 root 26: #include "crossbar.h"
1.1 root 27: #include "falcon/videl.h"
1.1.1.10 root 28: #include "configuration.h"
29: #include "statusbar.h"
1.1.1.13! root 30: #include "stMemory.h"
1.1 root 31: #if ENABLE_DSP_EMU
32: #include "falcon/dsp.h"
33: #endif
34:
35: /**
36: * no DSP
37: */
38: void IoMemTabFalcon_DSPnone(void (**readtab)(void), void (**writetab)(void))
39: {
40: int i, offset;
1.1.1.12 root 41:
1.1 root 42: offset = 0xffa200 - 0xff8000;
1.1.1.12 root 43: for (i = 0; i < 8; i++)
44: {
1.1 root 45: readtab[offset+i] = IoMem_ReadWithoutInterception;
46: }
47: readtab[offset+2] = IoMem_VoidRead; /* TODO: why this is needed */
1.1.1.12 root 48: for (i = 0; i < 8; i++)
49: {
1.1 root 50: writetab[offset+i] = IoMem_WriteWithoutInterception;
51: }
52: }
53:
54: /**
55: * Just a temporary hack - some programs are polling on this register and
56: * are expecting the handshake bit (#7) to change after a while...
57: */
58: static void DSP_DummyHostCommand_ReadByte(void)
59: {
60: IoMem[0xffa201] ^= 0x80;
61: }
62:
63: /**
64: * Just a temporary hack - some programs are polling on this register and
65: * are expecting some bits to change after a while...
66: */
67: static void DSP_DummyInterruptStatus_ReadByte(void)
68: {
69: IoMem[0xffa202] ^= 0xff;
70: }
71:
72: /**
73: * dummy IO when DSP emulation is not enabled
74: */
75: void IoMemTabFalcon_DSPdummy(void (**readtab)(void), void (**writetab)(void))
76: {
77: int i, offset;
1.1.1.12 root 78:
1.1 root 79: offset = 0xffa200 - 0xff8000;
80: readtab[offset+0] = IoMem_ReadWithoutInterception;
81: readtab[offset+1] = DSP_DummyHostCommand_ReadByte;
82: readtab[offset+2] = DSP_DummyInterruptStatus_ReadByte;
1.1.1.12 root 83: for (i = 3; i < 8; i++)
84: {
1.1 root 85: readtab[offset+i] = IoMem_ReadWithoutInterception;
86: }
1.1.1.12 root 87: for (i = 0; i < 8; i++)
88: {
1.1 root 89: writetab[offset+i] = IoMem_WriteWithoutInterception;
90: }
91: }
92:
93: #if ENABLE_DSP_EMU
94: /**
95: * enable DSP emulation
96: */
97: void IoMemTabFalcon_DSPemulation(void (**readtab)(void), void (**writetab)(void))
98: {
99: int i, offset;
1.1.1.12 root 100:
1.1 root 101: offset = 0xffa200 - 0xff8000;
1.1.1.12 root 102: for (i = 0; i < 8; i++)
103: {
1.1 root 104: readtab[offset+i] = DSP_HandleReadAccess;
105: writetab[offset+i] = DSP_HandleWriteAccess;
106: }
107: }
108: #endif
109:
110:
1.1.1.6 root 111: /**
112: * Take into account the Falcon Bus Control register $ff8007.b
113: $FFFF8007 Falcon Bus Control
1.1.1.13! root 114: BIT 6 : F30 Start (0=Cold, 1=Warm)
1.1.1.6 root 115: BIT 5 : STe Bus Emulation (0=on)
116: BIT 3 : Blitter Flag (0=on, 1=off)
117: BIT 2 : Blitter (0=8mhz, 1=16mhz)
118: BIT 0 : 68030 (0=8mhz, 1=16mhz)
119: */
120: static void IoMemTabFalcon_BusCtrl_WriteByte(void)
121: {
122: Uint8 busCtrl = IoMem_ReadByte(0xff8007);
1.1.1.12 root 123:
1.1.1.6 root 124: /* Set Falcon bus or STE compatible bus emulation */
125: if ((busCtrl & 0x20) == 0)
126: IoMem_Init_FalconInSTeBuscompatibilityMode(0);
127: else
128: IoMem_Init_FalconInSTeBuscompatibilityMode(1);
129:
1.1.1.13! root 130: /* 68030 Frequency changed ? We change freq only in 68030 mode
! 131: * for a normal Falcon, not if CPU is 68040 or 68060 is used,
! 132: * or if the user requested a faster frequency manually */
! 133: if (ConfigureParams.System.nCpuLevel == 3 && ConfigureParams.System.nCpuFreq <= 16)
1.1.1.11 root 134: {
135: if ((busCtrl & 0x1) == 1) {
136: /* 16 Mhz bus for 68030 */
1.1.1.13! root 137: Configuration_ChangeCpuFreq ( 16 );
1.1.1.11 root 138: }
139: else {
140: /* 8 Mhz bus for 68030 */
1.1.1.13! root 141: Configuration_ChangeCpuFreq ( 8 );
1.1.1.11 root 142: }
1.1.1.6 root 143: }
1.1.1.12 root 144: Statusbar_UpdateInfo(); /* Update clock speed in the status bar */
1.1.1.6 root 145: }
146:
147:
1.1.1.12 root 148: /**
149: * This register represents the configuration switches ("half moon" soldering
150: * points) on the Falcon's motherboard at location U46 and U47. The meaning
151: * of the switches is the following:
152: *
153: * 1-5 Not used
154: * 6 Connected = Quad Density Floppy; not connected = Don't care
155: * 7 Connected = AJAX FDC (1.44MB); not connected = 1772 FDC (720K)
156: * 8 Connected = No DMA sound; not connected = DMA Sound available
157: *
158: * Logic is inverted, i.e. connected means the corresponding bit is 0.
159: * Switch 8 is represented by the highest bit in the register.
160: */
161: static void IoMemTabFalc_Switches_ReadByte(void)
162: {
163: IoMem_WriteByte(0xff9200, 0xbf);
164: }
165:
166:
167: /**
168: * Some IO memory ranges do not result in a bus error when accessed
169: * in STE-compatible bus mode and with single byte access.
170: */
171: static void IoMemTabFalc_Compatible_ReadByte(void)
172: {
173: if (nIoMemAccessSize != SIZE_BYTE || (IoMem_ReadByte(0xff8007) & 0x20) != 0)
174: {
1.1.1.13! root 175: M68000_BusError(IoAccessFullAddress, BUS_ERROR_READ,
1.1.1.12 root 176: nIoMemAccessSize, BUS_ERROR_ACCESS_DATA);
177: }
178: }
179:
180: static void IoMemTabFalc_Compatible_WriteByte(void)
181: {
182: if (nIoMemAccessSize != SIZE_BYTE || (IoMem_ReadByte(0xff8007) & 0x20) != 0)
183: {
1.1.1.13! root 184: M68000_BusError(IoAccessFullAddress, BUS_ERROR_WRITE,
1.1.1.12 root 185: nIoMemAccessSize, BUS_ERROR_ACCESS_DATA);
186: }
187: }
188:
189: /**
190: * Some IO memory ranges do not result in a bus error when
191: * accessed in STE-compatible bus mode and with word access.
192: */
193: static void IoMemTabFalc_Compatible_ReadWord(void)
194: {
195: if (nIoMemAccessSize == SIZE_BYTE || (IoMem_ReadByte(0xff8007) & 0x20) != 0)
196: {
1.1.1.13! root 197: M68000_BusError(IoAccessFullAddress, BUS_ERROR_READ,
1.1.1.12 root 198: nIoMemAccessSize, BUS_ERROR_ACCESS_DATA);
199: }
200: }
201:
202: static void IoMemTabFalc_Compatible_WriteWord(void)
203: {
204: if (nIoMemAccessSize == SIZE_BYTE || (IoMem_ReadByte(0xff8007) & 0x20) != 0)
205: {
1.1.1.13! root 206: M68000_BusError(IoAccessFullAddress, BUS_ERROR_WRITE,
1.1.1.12 root 207: nIoMemAccessSize, BUS_ERROR_ACCESS_DATA);
208: }
209: }
210:
1.1 root 211: /*-----------------------------------------------------------------------*/
212: /*
213: List of functions to handle read/write hardware interceptions for a Falcon.
214: */
215: const INTERCEPT_ACCESS_FUNC IoMemTable_Falcon[] =
216: {
217: { 0xff8000, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.13! root 218: { 0xff8001, SIZE_BYTE, STMemory_MMU_Config_ReadByte, STMemory_MMU_Config_WriteByte }, /* Memory configuration */
1.1.1.6 root 219: { 0xff8006, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_Monitor_WriteByte }, /* Falcon monitor and memory configuration */
220: { 0xff8007, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMemTabFalcon_BusCtrl_WriteByte }, /* Falcon bus configuration */
1.1 root 221: { 0xff800C, SIZE_WORD, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
222: { 0xff8060, SIZE_LONG, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
223:
224: { 0xff8200, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.6 root 225: { 0xff8201, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_ScreenBase_WriteByte }, /* Video base high byte */
1.1 root 226: { 0xff8202, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.6 root 227: { 0xff8203, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_ScreenBase_WriteByte }, /* Video base med byte */
1.1 root 228: { 0xff8204, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.8 root 229: { 0xff8205, SIZE_BYTE, VIDEL_ScreenCounter_ReadByte, VIDEL_ScreenCounter_WriteByte },
1.1 root 230: { 0xff8206, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.8 root 231: { 0xff8207, SIZE_BYTE, VIDEL_ScreenCounter_ReadByte, VIDEL_ScreenCounter_WriteByte },
1.1 root 232: { 0xff8208, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.8 root 233: { 0xff8209, SIZE_BYTE, VIDEL_ScreenCounter_ReadByte, VIDEL_ScreenCounter_WriteByte },
234: { 0xff820a, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_SyncMode_WriteByte }, /* VIDEL Synch mode */
1.1.1.6 root 235: { 0xff820b, SIZE_BYTE, IoMem_VoidRead_00, IoMem_VoidWrite }, /* No bus error here : return 0 not ff */
236: { 0xff820c, SIZE_BYTE, IoMem_VoidRead_00, IoMem_VoidWrite }, /* No bus error here : return 0 not ff */
1.1.1.8 root 237: { 0xff820d, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_ScreenBase_WriteByte }, /* Video base low byte */
1.1.1.13! root 238: { 0xff820e, SIZE_WORD, VIDEL_LineOffset_ReadWord, VIDEL_LineOffset_WriteWord }, /* Falcon line offset */
1.1.1.8 root 239: { 0xff8210, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_Line_Width_WriteWord }, /* Falcon line width */
240: { 0xff8212, 46 , IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.10 root 241:
242: { 0xff8240, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color0_WriteWord }, /* ST COLOR 0 */
243: { 0xff8242, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color1_WriteWord }, /* ST COLOR 1 */
244: { 0xff8244, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color2_WriteWord }, /* ST COLOR 2 */
245: { 0xff8246, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color3_WriteWord }, /* ST COLOR 3 */
246: { 0xff8248, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color4_WriteWord }, /* ST COLOR 4 */
247: { 0xff824a, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color5_WriteWord }, /* ST COLOR 5 */
248: { 0xff824c, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color6_WriteWord }, /* ST COLOR 6 */
249: { 0xff824e, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color7_WriteWord }, /* ST COLOR 7 */
250: { 0xff8250, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color8_WriteWord }, /* ST COLOR 8 */
251: { 0xff8252, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color9_WriteWord }, /* ST COLOR 9 */
252: { 0xff8254, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color10_WriteWord }, /* ST COLOR 10 */
253: { 0xff8256, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color11_WriteWord }, /* ST COLOR 11 */
254: { 0xff8258, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color12_WriteWord }, /* ST COLOR 12 */
255: { 0xff825a, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color13_WriteWord }, /* ST COLOR 13 */
256: { 0xff825c, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color14_WriteWord }, /* ST COLOR 14 */
257: { 0xff825e, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color15_WriteWord }, /* ST COLOR 15 */
258:
1.1.1.8 root 259: { 0xff8260, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_ST_ShiftModeWriteByte },
260: { 0xff8261, 3 , IoMem_VoidRead_00, IoMem_VoidWrite }, /* No bus errors here : return 0 not ff */
261: { 0xff8264, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_HorScroll64_WriteByte }, /* Falcon horizontal fine scrolling high ? */
262: { 0xff8265, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_HorScroll65_WriteByte }, /* horizontal fine scrolling */
263: { 0xff8266, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_Falcon_ShiftMode_WriteWord }, /* Falcon shift mode */
264: { 0xff8268, 24 , IoMem_VoidRead_00, IoMem_VoidWrite }, /* No bus errors here : return 0 not ff */
1.1 root 265:
1.1.1.6 root 266: { 0xff8280, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HHC_WriteWord }, /* HHC : Horizontal Hold Counter */
267: { 0xff8282, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HHT_WriteWord }, /* HHT : Horizontal Hold Timer */
268: { 0xff8284, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HBB_WriteWord }, /* HBB : Horizontal Border Begin */
269: { 0xff8286, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HBE_WriteWord }, /* HBE : Horizontal Border End */
270: { 0xff8288, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HDB_WriteWord }, /* HDB : Horizontal Display Begin */
271: { 0xff828a, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HDE_WriteWord }, /* HDE : Horizontal Display End */
272: { 0xff828c, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HSS_WriteWord }, /* HSS : Horizontal SS */
273: { 0xff828e, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HFS_WriteWord }, /* HFS : Horizontal FS */
274: { 0xff8290, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HEE_WriteWord }, /* HEE : Horizontal EE */
275: { 0xff8292, 14, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus errors here */
276: { 0xff82a0, SIZE_WORD, VIDEL_VFC_ReadWord, IoMem_VoidWrite }, /* VFC - Vertical Frequency Counter */
277: { 0xff82a2, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VFT_WriteWord }, /* VFT - Vertical Frequency Timer */
278: { 0xff82a4, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VBB_WriteWord }, /* VBB - Vertical Border Begin */
279: { 0xff82a6, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VBE_WriteWord }, /* VBE - Vertical Border End */
280: { 0xff82a8, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VDB_WriteWord }, /* VDB - Vertical Display Begin */
281: { 0xff82aa, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VDE_WriteWord }, /* VDE - Vertical Display End */
282: { 0xff82ac, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VSS_WriteWord }, /* VSS - Vertical SS */
283: { 0xff82ae, 18, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus errors here */
284: { 0xff82c0, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VCO_WriteWord }, /* VCO - Video control */
285: { 0xff82c2, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VMD_WriteWord }, /* VMD - Video mode */
1.1 root 286:
1.1.1.12 root 287: { 0xff8560, SIZE_BYTE, IoMemTabFalc_Compatible_ReadByte, IoMemTabFalc_Compatible_WriteByte },
288: { 0xff8564, SIZE_BYTE, IoMemTabFalc_Compatible_ReadByte, IoMemTabFalc_Compatible_WriteByte },
289:
1.1 root 290: { 0xff8604, SIZE_WORD, FDC_DiskControllerStatus_ReadWord, FDC_DiskController_WriteWord },
291: { 0xff8606, SIZE_WORD, FDC_DmaStatus_ReadWord, FDC_DmaModeControl_WriteWord },
292: { 0xff8608, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.7 root 293: { 0xff8609, SIZE_BYTE, FDC_DmaAddress_ReadByte, FDC_DmaAddress_WriteByte }, /* DMA base and counter high byte */
1.1 root 294: { 0xff860a, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.7 root 295: { 0xff860b, SIZE_BYTE, FDC_DmaAddress_ReadByte, FDC_DmaAddress_WriteByte }, /* DMA base and counter med byte */
1.1 root 296: { 0xff860c, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.7 root 297: { 0xff860d, SIZE_BYTE, FDC_DmaAddress_ReadByte, FDC_DmaAddress_WriteByte }, /* DMA base and counter low byte */
1.1 root 298: { 0xff860e, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
299: { 0xff860f, SIZE_BYTE, FDC_FloppyMode_ReadByte, FDC_FloppyMode_WriteByte }, /* Floppy mode (?) register */
300:
1.1.1.4 root 301: { 0xff8800, SIZE_BYTE, PSG_ff8800_ReadByte, PSG_ff8800_WriteByte },
302: { 0xff8801, SIZE_BYTE, PSG_ff880x_ReadByte, PSG_ff8801_WriteByte },
303: { 0xff8802, SIZE_BYTE, PSG_ff880x_ReadByte, PSG_ff8802_WriteByte },
304: { 0xff8803, SIZE_BYTE, PSG_ff880x_ReadByte, PSG_ff8803_WriteByte },
1.1 root 305:
1.1.1.5 root 306: { 0xff8900, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_BufferInter_WriteByte }, /* Crossbar Buffer interrupts */
307: { 0xff8901, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_DmaCtrlReg_WriteByte }, /* Crossbar control register */
308: { 0xff8902, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
309: { 0xff8903, SIZE_BYTE, Crossbar_FrameStartHigh_ReadByte, Crossbar_FrameStartHigh_WriteByte }, /* DMA sound frame start high */
310: { 0xff8904, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
311: { 0xff8905, SIZE_BYTE, Crossbar_FrameStartMed_ReadByte, Crossbar_FrameStartMed_WriteByte }, /* DMA sound frame start med */
312: { 0xff8906, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
313: { 0xff8907, SIZE_BYTE, Crossbar_FrameStartLow_ReadByte, Crossbar_FrameStartLow_WriteByte }, /* DMA sound frame start low */
314: { 0xff8908, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
315: { 0xff8909, SIZE_BYTE, Crossbar_FrameCountHigh_ReadByte, Crossbar_FrameCountHigh_WriteByte }, /* DMA sound frame count high */
316: { 0xff890a, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
317: { 0xff890b, SIZE_BYTE, Crossbar_FrameCountMed_ReadByte, Crossbar_FrameCountMed_WriteByte }, /* DMA sound frame count med */
318: { 0xff890c, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
319: { 0xff890d, SIZE_BYTE, Crossbar_FrameCountLow_ReadByte, Crossbar_FrameCountLow_WriteByte }, /* DMA sound frame count low */
320: { 0xff890e, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
321: { 0xff890f, SIZE_BYTE, Crossbar_FrameEndHigh_ReadByte, Crossbar_FrameEndHigh_WriteByte }, /* DMA sound frame end high */
322: { 0xff8910, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
323: { 0xff8911, SIZE_BYTE, Crossbar_FrameEndMed_ReadByte, Crossbar_FrameEndMed_WriteByte }, /* DMA sound frame end med */
324: { 0xff8912, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
325: { 0xff8913, SIZE_BYTE, Crossbar_FrameEndLow_ReadByte, Crossbar_FrameEndLow_WriteByte }, /* DMA sound frame end low */
326: { 0xff8920, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_DmaTrckCtrl_WriteByte }, /* Crossbar track control */
327: { 0xff8921, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_SoundModeCtrl_WriteByte }, /* DMA sound mode control */
1.1.1.8 root 328: { 0xff8922, SIZE_WORD, IoMem_VoidRead_00, IoMem_VoidWrite }, /* Microwire data - n/a on Falcon, alwayes read 0 */
329: { 0xff8924, SIZE_WORD, IoMem_ReadWithoutInterception, Crossbar_Microwire_WriteWord }, /* Microwire mask - n/a on Falcon, see crossbar.c */
1.1.1.5 root 330:
1.1.1.9 root 331: { 0xff8930, SIZE_WORD, IoMem_ReadWithoutInterception, Crossbar_SrcControler_WriteWord }, /* Crossbar source controller */
332: { 0xff8932, SIZE_WORD, IoMem_ReadWithoutInterception, Crossbar_DstControler_WriteWord }, /* Crossbar destination controller */
1.1.1.5 root 333: { 0xff8934, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_FreqDivExt_WriteByte }, /* External clock divider */
334: { 0xff8935, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_FreqDivInt_WriteByte }, /* Internal clock divider */
335: { 0xff8936, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_TrackRecSelect_WriteByte }, /* Track record select */
336: { 0xff8937, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_CodecInput_WriteByte }, /* CODEC input source from 16 bits adder */
337: { 0xff8938, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_AdcInput_WriteByte }, /* ADC converter input for L+R channel */
338: { 0xff8939, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_InputAmp_WriteByte }, /* Input amplifier (+1.5 dB step) */
1.1.1.9 root 339: { 0xff893a, SIZE_WORD, IoMem_ReadWithoutInterception, Crossbar_OutputReduct_WriteWord }, /* Output reduction (-1.5 dB step) */
1.1.1.5 root 340: { 0xff893c, SIZE_WORD, IoMem_ReadWithoutInterception, Crossbar_CodecStatus_WriteWord }, /* CODEC status */
341: { 0xff893e, SIZE_WORD, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception }, /* No bus error here */
342: { 0xff8940, SIZE_WORD, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception }, /* GPx direction */
343: { 0xff8942, SIZE_WORD, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception }, /* GPx port */
1.1 root 344:
345: { 0xff8960, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
346: { 0xff8961, SIZE_BYTE, NvRam_Select_ReadByte, NvRam_Select_WriteByte }, /* NVRAM/RTC chip */
347: { 0xff8962, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
348: { 0xff8963, SIZE_BYTE, NvRam_Data_ReadByte, NvRam_Data_WriteByte }, /* NVRAM/RTC chip */
349:
1.1.1.3 root 350: { 0xff8a00, SIZE_WORD, Blitter_Halftone00_ReadWord, Blitter_Halftone00_WriteWord }, /* Blitter halftone RAM 0 */
351: { 0xff8a02, SIZE_WORD, Blitter_Halftone01_ReadWord, Blitter_Halftone01_WriteWord }, /* Blitter halftone RAM 1 */
352: { 0xff8a04, SIZE_WORD, Blitter_Halftone02_ReadWord, Blitter_Halftone02_WriteWord }, /* Blitter halftone RAM 2 */
353: { 0xff8a06, SIZE_WORD, Blitter_Halftone03_ReadWord, Blitter_Halftone03_WriteWord }, /* Blitter halftone RAM 3 */
354: { 0xff8a08, SIZE_WORD, Blitter_Halftone04_ReadWord, Blitter_Halftone04_WriteWord }, /* Blitter halftone RAM 4 */
355: { 0xff8a0a, SIZE_WORD, Blitter_Halftone05_ReadWord, Blitter_Halftone05_WriteWord }, /* Blitter halftone RAM 5 */
356: { 0xff8a0c, SIZE_WORD, Blitter_Halftone06_ReadWord, Blitter_Halftone06_WriteWord }, /* Blitter halftone RAM 6 */
357: { 0xff8a0e, SIZE_WORD, Blitter_Halftone07_ReadWord, Blitter_Halftone07_WriteWord }, /* Blitter halftone RAM 7 */
358: { 0xff8a10, SIZE_WORD, Blitter_Halftone08_ReadWord, Blitter_Halftone08_WriteWord }, /* Blitter halftone RAM 8 */
359: { 0xff8a12, SIZE_WORD, Blitter_Halftone09_ReadWord, Blitter_Halftone09_WriteWord }, /* Blitter halftone RAM 9 */
360: { 0xff8a14, SIZE_WORD, Blitter_Halftone10_ReadWord, Blitter_Halftone10_WriteWord }, /* Blitter halftone RAM 10 */
361: { 0xff8a16, SIZE_WORD, Blitter_Halftone11_ReadWord, Blitter_Halftone11_WriteWord }, /* Blitter halftone RAM 11 */
362: { 0xff8a18, SIZE_WORD, Blitter_Halftone12_ReadWord, Blitter_Halftone12_WriteWord }, /* Blitter halftone RAM 12 */
363: { 0xff8a1a, SIZE_WORD, Blitter_Halftone13_ReadWord, Blitter_Halftone13_WriteWord }, /* Blitter halftone RAM 13 */
364: { 0xff8a1c, SIZE_WORD, Blitter_Halftone14_ReadWord, Blitter_Halftone14_WriteWord }, /* Blitter halftone RAM 14 */
365: { 0xff8a1e, SIZE_WORD, Blitter_Halftone15_ReadWord, Blitter_Halftone15_WriteWord }, /* Blitter halftone RAM 15 */
366: { 0xff8a20, SIZE_WORD, Blitter_SourceXInc_ReadWord, Blitter_SourceXInc_WriteWord }, /* Blitter source x increment */
367: { 0xff8a22, SIZE_WORD, Blitter_SourceYInc_ReadWord, Blitter_SourceYInc_WriteWord }, /* Blitter source y increment */
1.1.1.2 root 368: { 0xff8a24, SIZE_LONG, Blitter_SourceAddr_ReadLong, Blitter_SourceAddr_WriteLong }, /* Blitter source address */
1.1 root 369: { 0xff8a28, SIZE_WORD, Blitter_Endmask1_ReadWord, Blitter_Endmask1_WriteWord },
370: { 0xff8a2a, SIZE_WORD, Blitter_Endmask2_ReadWord, Blitter_Endmask2_WriteWord },
371: { 0xff8a2c, SIZE_WORD, Blitter_Endmask3_ReadWord, Blitter_Endmask3_WriteWord },
1.1.1.3 root 372: { 0xff8a2e, SIZE_WORD, Blitter_DestXInc_ReadWord, Blitter_DestXInc_WriteWord }, /* Blitter dest. x increment */
373: { 0xff8a30, SIZE_WORD, Blitter_DestYInc_ReadWord, Blitter_DestYInc_WriteWord }, /* Blitter dest. y increment */
1.1 root 374: { 0xff8a32, SIZE_LONG, Blitter_DestAddr_ReadLong, Blitter_DestAddr_WriteLong },
375: { 0xff8a36, SIZE_WORD, Blitter_WordsPerLine_ReadWord, Blitter_WordsPerLine_WriteWord },
376: { 0xff8a38, SIZE_WORD, Blitter_LinesPerBitblock_ReadWord, Blitter_LinesPerBitblock_WriteWord },
377: { 0xff8a3a, SIZE_BYTE, Blitter_HalftoneOp_ReadByte, Blitter_HalftoneOp_WriteByte },
378: { 0xff8a3b, SIZE_BYTE, Blitter_LogOp_ReadByte, Blitter_LogOp_WriteByte },
379: { 0xff8a3c, SIZE_BYTE, Blitter_Control_ReadByte, Blitter_Control_WriteByte },
380: { 0xff8a3d, SIZE_BYTE, Blitter_Skew_ReadByte, Blitter_Skew_WriteByte },
381: { 0xff8a3e, SIZE_WORD, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
382:
383: { 0xff8c80, 8, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* TODO: SCC */
384:
1.1.1.12 root 385: { 0xff9200, SIZE_BYTE, IoMemTabFalc_Switches_ReadByte, IoMem_WriteWithoutInterception }, /* Falcon switches */
386: { 0xff9201, SIZE_BYTE, Joy_StePadButtons_ReadByte, IoMem_WriteWithoutInterception }, /* Joypad fire buttons */
1.1 root 387: { 0xff9202, SIZE_WORD, Joy_StePadMulti_ReadWord, Joy_StePadMulti_WriteWord }, /* Joypad directions/buttons/selection */
1.1.1.5 root 388: { 0xff9210, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1 root 389: { 0xff9211, SIZE_BYTE, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Joypad 0 X position (?) */
1.1.1.5 root 390: { 0xff9212, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1 root 391: { 0xff9213, SIZE_BYTE, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Joypad 0 Y position (?) */
1.1.1.5 root 392: { 0xff9214, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1 root 393: { 0xff9215, SIZE_BYTE, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Joypad 1 X position (?) */
1.1.1.5 root 394: { 0xff9216, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1 root 395: { 0xff9217, SIZE_BYTE, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Joypad 1 Y position (?) */
1.1.1.5 root 396: { 0xff9220, SIZE_WORD, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Lightpen X position */
397: { 0xff9222, SIZE_WORD, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Lightpen Y position */
1.1 root 398:
1.1.1.10 root 399: { 0xff9800, 0x400, IoMem_ReadWithoutInterception, VIDEL_FalconColorRegsWrite }, /* Falcon Videl palette */
1.1 root 400:
1.1.1.12 root 401: { 0xffc020, SIZE_BYTE, IoMemTabFalc_Compatible_ReadByte, IoMemTabFalc_Compatible_WriteByte },
402: { 0xffc021, SIZE_BYTE, IoMemTabFalc_Compatible_ReadByte, IoMemTabFalc_Compatible_WriteByte },
403: { 0xffd020, SIZE_BYTE, IoMemTabFalc_Compatible_ReadByte, IoMemTabFalc_Compatible_WriteByte },
404: { 0xffd074, SIZE_WORD, IoMemTabFalc_Compatible_ReadWord, IoMemTabFalc_Compatible_WriteWord },
405: { 0xffd420, SIZE_BYTE, IoMemTabFalc_Compatible_ReadByte, IoMemTabFalc_Compatible_WriteByte },
406: { 0xffd425, SIZE_BYTE, IoMemTabFalc_Compatible_ReadByte, IoMemTabFalc_Compatible_WriteByte },
407: { 0xffd520, SIZE_WORD, IoMemTabFalc_Compatible_ReadWord, IoMemTabFalc_Compatible_WriteWord },
408: { 0xffd530, SIZE_WORD, IoMemTabFalc_Compatible_ReadWord, IoMemTabFalc_Compatible_WriteWord },
409:
1.1 root 410: { 0xfffa00, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
411: { 0xfffa01, SIZE_BYTE, MFP_GPIP_ReadByte, MFP_GPIP_WriteByte },
412: { 0xfffa02, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
413: { 0xfffa03, SIZE_BYTE, MFP_ActiveEdge_ReadByte, MFP_ActiveEdge_WriteByte },
414: { 0xfffa04, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
415: { 0xfffa05, SIZE_BYTE, MFP_DataDirection_ReadByte, MFP_DataDirection_WriteByte },
416: { 0xfffa06, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
417: { 0xfffa07, SIZE_BYTE, MFP_EnableA_ReadByte, MFP_EnableA_WriteByte },
418: { 0xfffa08, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
419: { 0xfffa09, SIZE_BYTE, MFP_EnableB_ReadByte, MFP_EnableB_WriteByte },
420: { 0xfffa0a, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
421: { 0xfffa0b, SIZE_BYTE, MFP_PendingA_ReadByte, MFP_PendingA_WriteByte },
422: { 0xfffa0c, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
423: { 0xfffa0d, SIZE_BYTE, MFP_PendingB_ReadByte, MFP_PendingB_WriteByte },
424: { 0xfffa0e, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
425: { 0xfffa0f, SIZE_BYTE, MFP_InServiceA_ReadByte, MFP_InServiceA_WriteByte },
426: { 0xfffa10, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
427: { 0xfffa11, SIZE_BYTE, MFP_InServiceB_ReadByte, MFP_InServiceB_WriteByte },
428: { 0xfffa12, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
429: { 0xfffa13, SIZE_BYTE, MFP_MaskA_ReadByte, MFP_MaskA_WriteByte },
430: { 0xfffa14, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
431: { 0xfffa15, SIZE_BYTE, MFP_MaskB_ReadByte, MFP_MaskB_WriteByte },
432: { 0xfffa16, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
433: { 0xfffa17, SIZE_BYTE, MFP_VectorReg_ReadByte, MFP_VectorReg_WriteByte },
434: { 0xfffa18, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
435: { 0xfffa19, SIZE_BYTE, MFP_TimerACtrl_ReadByte, MFP_TimerACtrl_WriteByte },
436: { 0xfffa1a, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
437: { 0xfffa1b, SIZE_BYTE, MFP_TimerBCtrl_ReadByte, MFP_TimerBCtrl_WriteByte },
438: { 0xfffa1c, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
439: { 0xfffa1d, SIZE_BYTE, MFP_TimerCDCtrl_ReadByte, MFP_TimerCDCtrl_WriteByte },
440: { 0xfffa1e, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
441: { 0xfffa1f, SIZE_BYTE, MFP_TimerAData_ReadByte, MFP_TimerAData_WriteByte },
442: { 0xfffa20, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
443: { 0xfffa21, SIZE_BYTE, MFP_TimerBData_ReadByte, MFP_TimerBData_WriteByte },
444: { 0xfffa22, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
445: { 0xfffa23, SIZE_BYTE, MFP_TimerCData_ReadByte, MFP_TimerCData_WriteByte },
446: { 0xfffa24, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
447: { 0xfffa25, SIZE_BYTE, MFP_TimerDData_ReadByte, MFP_TimerDData_WriteByte },
448:
449: { 0xfffa26, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
450: { 0xfffa27, SIZE_BYTE, RS232_SCR_ReadByte, RS232_SCR_WriteByte }, /* Sync character register */
451: { 0xfffa28, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
452: { 0xfffa29, SIZE_BYTE, RS232_UCR_ReadByte, RS232_UCR_WriteByte }, /* USART control register */
453: { 0xfffa2a, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
454: { 0xfffa2b, SIZE_BYTE, RS232_RSR_ReadByte, RS232_RSR_WriteByte }, /* Receiver status register */
455: { 0xfffa2c, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
456: { 0xfffa2d, SIZE_BYTE, RS232_TSR_ReadByte, RS232_TSR_WriteByte }, /* Transmitter status register */
457: { 0xfffa2e, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
458: { 0xfffa2f, SIZE_BYTE, RS232_UDR_ReadByte, RS232_UDR_WriteByte }, /* USART data register */
459:
1.1.1.9 root 460: { 0xfffc00, SIZE_BYTE, ACIA_IKBD_Read_SR, ACIA_IKBD_Write_CR },
1.1 root 461: { 0xfffc01, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.9 root 462: { 0xfffc02, SIZE_BYTE, ACIA_IKBD_Read_RDR, ACIA_IKBD_Write_TDR },
1.1 root 463: { 0xfffc03, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
464: { 0xfffc04, SIZE_BYTE, Midi_Control_ReadByte, Midi_Control_WriteByte },
465: { 0xfffc05, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
466: { 0xfffc06, SIZE_BYTE, Midi_Data_ReadByte, Midi_Data_WriteByte },
467: { 0xfffc07, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus errors here */
468:
469: { 0xffff82, SIZE_WORD, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus errors here */
470:
471: { 0, 0, NULL, NULL }
472: };
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