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1.1 root 1: /*
2: Hatari - ioMemTabFalcon.c
3:
1.1.1.9 root 4: This file is distributed under the GNU General Public License, version 2
5: or at your option any later version. Read the file gpl.txt for details.
1.1 root 6:
7: Table with hardware IO handlers for the Falcon.
8: */
1.1.1.3 root 9: const char IoMemTabFalc_fileid[] = "Hatari ioMemTabFalcon.c : " __DATE__ " " __TIME__;
1.1 root 10:
11: #include "main.h"
1.1.1.14! root 12: #include "configuration.h"
1.1 root 13: #include "fdc.h"
1.1.1.9 root 14: #include "acia.h"
1.1 root 15: #include "ioMem.h"
16: #include "ioMemTables.h"
1.1.1.6 root 17: #include "m68000.h"
1.1 root 18: #include "joy.h"
19: #include "mfp.h"
20: #include "midi.h"
21: #include "nvram.h"
22: #include "psg.h"
23: #include "rs232.h"
24: #include "rtc.h"
1.1.1.14! root 25: #include "scc.h"
1.1.1.6 root 26: #include "screen.h"
1.1 root 27: #include "blitter.h"
1.1.1.5 root 28: #include "crossbar.h"
1.1 root 29: #include "falcon/videl.h"
1.1.1.10 root 30: #include "configuration.h"
31: #include "statusbar.h"
1.1.1.13 root 32: #include "stMemory.h"
1.1 root 33: #if ENABLE_DSP_EMU
34: #include "falcon/dsp.h"
35: #endif
36:
37: /**
38: * no DSP
39: */
40: void IoMemTabFalcon_DSPnone(void (**readtab)(void), void (**writetab)(void))
41: {
42: int i, offset;
1.1.1.12 root 43:
1.1 root 44: offset = 0xffa200 - 0xff8000;
1.1.1.12 root 45: for (i = 0; i < 8; i++)
46: {
1.1 root 47: readtab[offset+i] = IoMem_ReadWithoutInterception;
48: }
49: readtab[offset+2] = IoMem_VoidRead; /* TODO: why this is needed */
1.1.1.12 root 50: for (i = 0; i < 8; i++)
51: {
1.1 root 52: writetab[offset+i] = IoMem_WriteWithoutInterception;
53: }
54: }
55:
56: /**
57: * Just a temporary hack - some programs are polling on this register and
58: * are expecting the handshake bit (#7) to change after a while...
59: */
60: static void DSP_DummyHostCommand_ReadByte(void)
61: {
62: IoMem[0xffa201] ^= 0x80;
63: }
64:
65: /**
66: * Just a temporary hack - some programs are polling on this register and
67: * are expecting some bits to change after a while...
68: */
69: static void DSP_DummyInterruptStatus_ReadByte(void)
70: {
71: IoMem[0xffa202] ^= 0xff;
72: }
73:
74: /**
75: * dummy IO when DSP emulation is not enabled
76: */
77: void IoMemTabFalcon_DSPdummy(void (**readtab)(void), void (**writetab)(void))
78: {
79: int i, offset;
1.1.1.12 root 80:
1.1 root 81: offset = 0xffa200 - 0xff8000;
82: readtab[offset+0] = IoMem_ReadWithoutInterception;
83: readtab[offset+1] = DSP_DummyHostCommand_ReadByte;
84: readtab[offset+2] = DSP_DummyInterruptStatus_ReadByte;
1.1.1.12 root 85: for (i = 3; i < 8; i++)
86: {
1.1 root 87: readtab[offset+i] = IoMem_ReadWithoutInterception;
88: }
1.1.1.12 root 89: for (i = 0; i < 8; i++)
90: {
1.1 root 91: writetab[offset+i] = IoMem_WriteWithoutInterception;
92: }
93: }
94:
95: #if ENABLE_DSP_EMU
96: /**
97: * enable DSP emulation
98: */
99: void IoMemTabFalcon_DSPemulation(void (**readtab)(void), void (**writetab)(void))
100: {
101: int i, offset;
1.1.1.12 root 102:
1.1 root 103: offset = 0xffa200 - 0xff8000;
1.1.1.12 root 104: for (i = 0; i < 8; i++)
105: {
1.1 root 106: readtab[offset+i] = DSP_HandleReadAccess;
107: writetab[offset+i] = DSP_HandleWriteAccess;
108: }
109: }
110: #endif
111:
112:
1.1.1.6 root 113: /**
114: * Take into account the Falcon Bus Control register $ff8007.b
115: $FFFF8007 Falcon Bus Control
1.1.1.13 root 116: BIT 6 : F30 Start (0=Cold, 1=Warm)
1.1.1.6 root 117: BIT 5 : STe Bus Emulation (0=on)
118: BIT 3 : Blitter Flag (0=on, 1=off)
119: BIT 2 : Blitter (0=8mhz, 1=16mhz)
120: BIT 0 : 68030 (0=8mhz, 1=16mhz)
121: */
122: static void IoMemTabFalcon_BusCtrl_WriteByte(void)
123: {
124: Uint8 busCtrl = IoMem_ReadByte(0xff8007);
1.1.1.12 root 125:
1.1.1.6 root 126: /* Set Falcon bus or STE compatible bus emulation */
127: if ((busCtrl & 0x20) == 0)
1.1.1.14! root 128: IoMem_SetFalconBusMode(STE_BUS_COMPATIBLE);
1.1.1.6 root 129: else
1.1.1.14! root 130: IoMem_SetFalconBusMode(FALCON_ONLY_BUS);
1.1.1.6 root 131:
1.1.1.13 root 132: /* 68030 Frequency changed ? We change freq only in 68030 mode
133: * for a normal Falcon, not if CPU is 68040 or 68060 is used,
134: * or if the user requested a faster frequency manually */
135: if (ConfigureParams.System.nCpuLevel == 3 && ConfigureParams.System.nCpuFreq <= 16)
1.1.1.11 root 136: {
137: if ((busCtrl & 0x1) == 1) {
138: /* 16 Mhz bus for 68030 */
1.1.1.13 root 139: Configuration_ChangeCpuFreq ( 16 );
1.1.1.11 root 140: }
141: else {
142: /* 8 Mhz bus for 68030 */
1.1.1.13 root 143: Configuration_ChangeCpuFreq ( 8 );
1.1.1.11 root 144: }
1.1.1.6 root 145: }
1.1.1.12 root 146: Statusbar_UpdateInfo(); /* Update clock speed in the status bar */
1.1.1.6 root 147: }
148:
1.1.1.14! root 149: static void IoMemTabFalcon_BusCtrl_ReadByte(void)
! 150: {
! 151: Uint8 nBusCtrl = IoMem_ReadByte(0xff8007);
! 152:
! 153: /* Set the bit manually to get it right after cold boot */
! 154: if (IoMem_IsFalconBusMode())
! 155: nBusCtrl |= 0x20;
! 156: else
! 157: nBusCtrl &= ~0x20;
! 158:
! 159: if (ConfigureParams.System.nCpuFreq == 8)
! 160: nBusCtrl &= ~1;
! 161: else
! 162: nBusCtrl |= 1;
! 163:
! 164: IoMem_WriteByte(0xff8007, nBusCtrl);
! 165: }
! 166:
1.1.1.6 root 167:
1.1.1.12 root 168: /**
169: * This register represents the configuration switches ("half moon" soldering
170: * points) on the Falcon's motherboard at location U46 and U47. The meaning
171: * of the switches is the following:
172: *
173: * 1-5 Not used
174: * 6 Connected = Quad Density Floppy; not connected = Don't care
175: * 7 Connected = AJAX FDC (1.44MB); not connected = 1772 FDC (720K)
176: * 8 Connected = No DMA sound; not connected = DMA Sound available
177: *
178: * Logic is inverted, i.e. connected means the corresponding bit is 0.
179: * Switch 8 is represented by the highest bit in the register.
180: */
181: static void IoMemTabFalc_Switches_ReadByte(void)
182: {
183: IoMem_WriteByte(0xff9200, 0xbf);
184: }
185:
186:
187: /**
188: * Some IO memory ranges do not result in a bus error when accessed
189: * in STE-compatible bus mode and with single byte access.
190: */
191: static void IoMemTabFalc_Compatible_ReadByte(void)
192: {
1.1.1.14! root 193: if (nIoMemAccessSize != SIZE_BYTE || IoMem_IsFalconBusMode())
1.1.1.12 root 194: {
1.1.1.13 root 195: M68000_BusError(IoAccessFullAddress, BUS_ERROR_READ,
1.1.1.12 root 196: nIoMemAccessSize, BUS_ERROR_ACCESS_DATA);
197: }
198: }
199:
200: static void IoMemTabFalc_Compatible_WriteByte(void)
201: {
1.1.1.14! root 202: if (nIoMemAccessSize != SIZE_BYTE || IoMem_IsFalconBusMode())
1.1.1.12 root 203: {
1.1.1.13 root 204: M68000_BusError(IoAccessFullAddress, BUS_ERROR_WRITE,
1.1.1.12 root 205: nIoMemAccessSize, BUS_ERROR_ACCESS_DATA);
206: }
207: }
208:
209: /**
210: * Some IO memory ranges do not result in a bus error when
211: * accessed in STE-compatible bus mode and with word access.
212: */
213: static void IoMemTabFalc_Compatible_ReadWord(void)
214: {
1.1.1.14! root 215: if (nIoMemAccessSize == SIZE_BYTE || IoMem_IsFalconBusMode())
1.1.1.12 root 216: {
1.1.1.13 root 217: M68000_BusError(IoAccessFullAddress, BUS_ERROR_READ,
1.1.1.12 root 218: nIoMemAccessSize, BUS_ERROR_ACCESS_DATA);
219: }
220: }
221:
222: static void IoMemTabFalc_Compatible_WriteWord(void)
223: {
1.1.1.14! root 224: if (nIoMemAccessSize == SIZE_BYTE || IoMem_IsFalconBusMode())
1.1.1.12 root 225: {
1.1.1.13 root 226: M68000_BusError(IoAccessFullAddress, BUS_ERROR_WRITE,
1.1.1.12 root 227: nIoMemAccessSize, BUS_ERROR_ACCESS_DATA);
228: }
229: }
230:
1.1 root 231: /*-----------------------------------------------------------------------*/
232: /*
233: List of functions to handle read/write hardware interceptions for a Falcon.
234: */
235: const INTERCEPT_ACCESS_FUNC IoMemTable_Falcon[] =
236: {
237: { 0xff8000, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.13 root 238: { 0xff8001, SIZE_BYTE, STMemory_MMU_Config_ReadByte, STMemory_MMU_Config_WriteByte }, /* Memory configuration */
1.1.1.6 root 239: { 0xff8006, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_Monitor_WriteByte }, /* Falcon monitor and memory configuration */
1.1.1.14! root 240: { 0xff8007, SIZE_BYTE, IoMemTabFalcon_BusCtrl_ReadByte, IoMemTabFalcon_BusCtrl_WriteByte }, /* Falcon bus configuration */
1.1 root 241: { 0xff800C, SIZE_WORD, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
242: { 0xff8060, SIZE_LONG, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
243:
244: { 0xff8200, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.6 root 245: { 0xff8201, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_ScreenBase_WriteByte }, /* Video base high byte */
1.1 root 246: { 0xff8202, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.6 root 247: { 0xff8203, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_ScreenBase_WriteByte }, /* Video base med byte */
1.1 root 248: { 0xff8204, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.8 root 249: { 0xff8205, SIZE_BYTE, VIDEL_ScreenCounter_ReadByte, VIDEL_ScreenCounter_WriteByte },
1.1 root 250: { 0xff8206, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.8 root 251: { 0xff8207, SIZE_BYTE, VIDEL_ScreenCounter_ReadByte, VIDEL_ScreenCounter_WriteByte },
1.1 root 252: { 0xff8208, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.8 root 253: { 0xff8209, SIZE_BYTE, VIDEL_ScreenCounter_ReadByte, VIDEL_ScreenCounter_WriteByte },
254: { 0xff820a, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_SyncMode_WriteByte }, /* VIDEL Synch mode */
1.1.1.6 root 255: { 0xff820b, SIZE_BYTE, IoMem_VoidRead_00, IoMem_VoidWrite }, /* No bus error here : return 0 not ff */
256: { 0xff820c, SIZE_BYTE, IoMem_VoidRead_00, IoMem_VoidWrite }, /* No bus error here : return 0 not ff */
1.1.1.8 root 257: { 0xff820d, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_ScreenBase_WriteByte }, /* Video base low byte */
1.1.1.13 root 258: { 0xff820e, SIZE_WORD, VIDEL_LineOffset_ReadWord, VIDEL_LineOffset_WriteWord }, /* Falcon line offset */
1.1.1.8 root 259: { 0xff8210, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_Line_Width_WriteWord }, /* Falcon line width */
260: { 0xff8212, 46 , IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.10 root 261:
262: { 0xff8240, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color0_WriteWord }, /* ST COLOR 0 */
263: { 0xff8242, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color1_WriteWord }, /* ST COLOR 1 */
264: { 0xff8244, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color2_WriteWord }, /* ST COLOR 2 */
265: { 0xff8246, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color3_WriteWord }, /* ST COLOR 3 */
266: { 0xff8248, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color4_WriteWord }, /* ST COLOR 4 */
267: { 0xff824a, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color5_WriteWord }, /* ST COLOR 5 */
268: { 0xff824c, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color6_WriteWord }, /* ST COLOR 6 */
269: { 0xff824e, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color7_WriteWord }, /* ST COLOR 7 */
270: { 0xff8250, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color8_WriteWord }, /* ST COLOR 8 */
271: { 0xff8252, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color9_WriteWord }, /* ST COLOR 9 */
272: { 0xff8254, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color10_WriteWord }, /* ST COLOR 10 */
273: { 0xff8256, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color11_WriteWord }, /* ST COLOR 11 */
274: { 0xff8258, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color12_WriteWord }, /* ST COLOR 12 */
275: { 0xff825a, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color13_WriteWord }, /* ST COLOR 13 */
276: { 0xff825c, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color14_WriteWord }, /* ST COLOR 14 */
277: { 0xff825e, SIZE_WORD, IoMem_ReadWithoutInterception, Videl_Color15_WriteWord }, /* ST COLOR 15 */
278:
1.1.1.8 root 279: { 0xff8260, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_ST_ShiftModeWriteByte },
280: { 0xff8261, 3 , IoMem_VoidRead_00, IoMem_VoidWrite }, /* No bus errors here : return 0 not ff */
281: { 0xff8264, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_HorScroll64_WriteByte }, /* Falcon horizontal fine scrolling high ? */
282: { 0xff8265, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_HorScroll65_WriteByte }, /* horizontal fine scrolling */
283: { 0xff8266, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_Falcon_ShiftMode_WriteWord }, /* Falcon shift mode */
284: { 0xff8268, 24 , IoMem_VoidRead_00, IoMem_VoidWrite }, /* No bus errors here : return 0 not ff */
1.1 root 285:
1.1.1.6 root 286: { 0xff8280, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HHC_WriteWord }, /* HHC : Horizontal Hold Counter */
287: { 0xff8282, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HHT_WriteWord }, /* HHT : Horizontal Hold Timer */
288: { 0xff8284, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HBB_WriteWord }, /* HBB : Horizontal Border Begin */
289: { 0xff8286, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HBE_WriteWord }, /* HBE : Horizontal Border End */
290: { 0xff8288, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HDB_WriteWord }, /* HDB : Horizontal Display Begin */
291: { 0xff828a, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HDE_WriteWord }, /* HDE : Horizontal Display End */
292: { 0xff828c, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HSS_WriteWord }, /* HSS : Horizontal SS */
293: { 0xff828e, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HFS_WriteWord }, /* HFS : Horizontal FS */
294: { 0xff8290, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HEE_WriteWord }, /* HEE : Horizontal EE */
295: { 0xff8292, 14, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus errors here */
296: { 0xff82a0, SIZE_WORD, VIDEL_VFC_ReadWord, IoMem_VoidWrite }, /* VFC - Vertical Frequency Counter */
297: { 0xff82a2, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VFT_WriteWord }, /* VFT - Vertical Frequency Timer */
298: { 0xff82a4, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VBB_WriteWord }, /* VBB - Vertical Border Begin */
299: { 0xff82a6, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VBE_WriteWord }, /* VBE - Vertical Border End */
300: { 0xff82a8, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VDB_WriteWord }, /* VDB - Vertical Display Begin */
301: { 0xff82aa, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VDE_WriteWord }, /* VDE - Vertical Display End */
302: { 0xff82ac, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VSS_WriteWord }, /* VSS - Vertical SS */
303: { 0xff82ae, 18, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus errors here */
304: { 0xff82c0, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VCO_WriteWord }, /* VCO - Video control */
305: { 0xff82c2, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VMD_WriteWord }, /* VMD - Video mode */
1.1 root 306:
1.1.1.12 root 307: { 0xff8560, SIZE_BYTE, IoMemTabFalc_Compatible_ReadByte, IoMemTabFalc_Compatible_WriteByte },
308: { 0xff8564, SIZE_BYTE, IoMemTabFalc_Compatible_ReadByte, IoMemTabFalc_Compatible_WriteByte },
309:
1.1 root 310: { 0xff8604, SIZE_WORD, FDC_DiskControllerStatus_ReadWord, FDC_DiskController_WriteWord },
311: { 0xff8606, SIZE_WORD, FDC_DmaStatus_ReadWord, FDC_DmaModeControl_WriteWord },
312: { 0xff8608, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.7 root 313: { 0xff8609, SIZE_BYTE, FDC_DmaAddress_ReadByte, FDC_DmaAddress_WriteByte }, /* DMA base and counter high byte */
1.1 root 314: { 0xff860a, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.7 root 315: { 0xff860b, SIZE_BYTE, FDC_DmaAddress_ReadByte, FDC_DmaAddress_WriteByte }, /* DMA base and counter med byte */
1.1 root 316: { 0xff860c, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.7 root 317: { 0xff860d, SIZE_BYTE, FDC_DmaAddress_ReadByte, FDC_DmaAddress_WriteByte }, /* DMA base and counter low byte */
1.1 root 318: { 0xff860e, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
319: { 0xff860f, SIZE_BYTE, FDC_FloppyMode_ReadByte, FDC_FloppyMode_WriteByte }, /* Floppy mode (?) register */
320:
1.1.1.4 root 321: { 0xff8800, SIZE_BYTE, PSG_ff8800_ReadByte, PSG_ff8800_WriteByte },
322: { 0xff8801, SIZE_BYTE, PSG_ff880x_ReadByte, PSG_ff8801_WriteByte },
323: { 0xff8802, SIZE_BYTE, PSG_ff880x_ReadByte, PSG_ff8802_WriteByte },
324: { 0xff8803, SIZE_BYTE, PSG_ff880x_ReadByte, PSG_ff8803_WriteByte },
1.1 root 325:
1.1.1.5 root 326: { 0xff8900, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_BufferInter_WriteByte }, /* Crossbar Buffer interrupts */
327: { 0xff8901, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_DmaCtrlReg_WriteByte }, /* Crossbar control register */
328: { 0xff8902, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
329: { 0xff8903, SIZE_BYTE, Crossbar_FrameStartHigh_ReadByte, Crossbar_FrameStartHigh_WriteByte }, /* DMA sound frame start high */
330: { 0xff8904, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
331: { 0xff8905, SIZE_BYTE, Crossbar_FrameStartMed_ReadByte, Crossbar_FrameStartMed_WriteByte }, /* DMA sound frame start med */
332: { 0xff8906, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
333: { 0xff8907, SIZE_BYTE, Crossbar_FrameStartLow_ReadByte, Crossbar_FrameStartLow_WriteByte }, /* DMA sound frame start low */
334: { 0xff8908, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
335: { 0xff8909, SIZE_BYTE, Crossbar_FrameCountHigh_ReadByte, Crossbar_FrameCountHigh_WriteByte }, /* DMA sound frame count high */
336: { 0xff890a, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
337: { 0xff890b, SIZE_BYTE, Crossbar_FrameCountMed_ReadByte, Crossbar_FrameCountMed_WriteByte }, /* DMA sound frame count med */
338: { 0xff890c, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
339: { 0xff890d, SIZE_BYTE, Crossbar_FrameCountLow_ReadByte, Crossbar_FrameCountLow_WriteByte }, /* DMA sound frame count low */
340: { 0xff890e, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
341: { 0xff890f, SIZE_BYTE, Crossbar_FrameEndHigh_ReadByte, Crossbar_FrameEndHigh_WriteByte }, /* DMA sound frame end high */
342: { 0xff8910, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
343: { 0xff8911, SIZE_BYTE, Crossbar_FrameEndMed_ReadByte, Crossbar_FrameEndMed_WriteByte }, /* DMA sound frame end med */
344: { 0xff8912, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
345: { 0xff8913, SIZE_BYTE, Crossbar_FrameEndLow_ReadByte, Crossbar_FrameEndLow_WriteByte }, /* DMA sound frame end low */
346: { 0xff8920, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_DmaTrckCtrl_WriteByte }, /* Crossbar track control */
347: { 0xff8921, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_SoundModeCtrl_WriteByte }, /* DMA sound mode control */
1.1.1.8 root 348: { 0xff8922, SIZE_WORD, IoMem_VoidRead_00, IoMem_VoidWrite }, /* Microwire data - n/a on Falcon, alwayes read 0 */
349: { 0xff8924, SIZE_WORD, IoMem_ReadWithoutInterception, Crossbar_Microwire_WriteWord }, /* Microwire mask - n/a on Falcon, see crossbar.c */
1.1.1.5 root 350:
1.1.1.9 root 351: { 0xff8930, SIZE_WORD, IoMem_ReadWithoutInterception, Crossbar_SrcControler_WriteWord }, /* Crossbar source controller */
352: { 0xff8932, SIZE_WORD, IoMem_ReadWithoutInterception, Crossbar_DstControler_WriteWord }, /* Crossbar destination controller */
1.1.1.5 root 353: { 0xff8934, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_FreqDivExt_WriteByte }, /* External clock divider */
354: { 0xff8935, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_FreqDivInt_WriteByte }, /* Internal clock divider */
355: { 0xff8936, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_TrackRecSelect_WriteByte }, /* Track record select */
356: { 0xff8937, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_CodecInput_WriteByte }, /* CODEC input source from 16 bits adder */
357: { 0xff8938, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_AdcInput_WriteByte }, /* ADC converter input for L+R channel */
358: { 0xff8939, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_InputAmp_WriteByte }, /* Input amplifier (+1.5 dB step) */
1.1.1.9 root 359: { 0xff893a, SIZE_WORD, IoMem_ReadWithoutInterception, Crossbar_OutputReduct_WriteWord }, /* Output reduction (-1.5 dB step) */
1.1.1.5 root 360: { 0xff893c, SIZE_WORD, IoMem_ReadWithoutInterception, Crossbar_CodecStatus_WriteWord }, /* CODEC status */
361: { 0xff893e, SIZE_WORD, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception }, /* No bus error here */
362: { 0xff8940, SIZE_WORD, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception }, /* GPx direction */
363: { 0xff8942, SIZE_WORD, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception }, /* GPx port */
1.1 root 364:
365: { 0xff8960, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
366: { 0xff8961, SIZE_BYTE, NvRam_Select_ReadByte, NvRam_Select_WriteByte }, /* NVRAM/RTC chip */
367: { 0xff8962, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
368: { 0xff8963, SIZE_BYTE, NvRam_Data_ReadByte, NvRam_Data_WriteByte }, /* NVRAM/RTC chip */
369:
1.1.1.3 root 370: { 0xff8a00, SIZE_WORD, Blitter_Halftone00_ReadWord, Blitter_Halftone00_WriteWord }, /* Blitter halftone RAM 0 */
371: { 0xff8a02, SIZE_WORD, Blitter_Halftone01_ReadWord, Blitter_Halftone01_WriteWord }, /* Blitter halftone RAM 1 */
372: { 0xff8a04, SIZE_WORD, Blitter_Halftone02_ReadWord, Blitter_Halftone02_WriteWord }, /* Blitter halftone RAM 2 */
373: { 0xff8a06, SIZE_WORD, Blitter_Halftone03_ReadWord, Blitter_Halftone03_WriteWord }, /* Blitter halftone RAM 3 */
374: { 0xff8a08, SIZE_WORD, Blitter_Halftone04_ReadWord, Blitter_Halftone04_WriteWord }, /* Blitter halftone RAM 4 */
375: { 0xff8a0a, SIZE_WORD, Blitter_Halftone05_ReadWord, Blitter_Halftone05_WriteWord }, /* Blitter halftone RAM 5 */
376: { 0xff8a0c, SIZE_WORD, Blitter_Halftone06_ReadWord, Blitter_Halftone06_WriteWord }, /* Blitter halftone RAM 6 */
377: { 0xff8a0e, SIZE_WORD, Blitter_Halftone07_ReadWord, Blitter_Halftone07_WriteWord }, /* Blitter halftone RAM 7 */
378: { 0xff8a10, SIZE_WORD, Blitter_Halftone08_ReadWord, Blitter_Halftone08_WriteWord }, /* Blitter halftone RAM 8 */
379: { 0xff8a12, SIZE_WORD, Blitter_Halftone09_ReadWord, Blitter_Halftone09_WriteWord }, /* Blitter halftone RAM 9 */
380: { 0xff8a14, SIZE_WORD, Blitter_Halftone10_ReadWord, Blitter_Halftone10_WriteWord }, /* Blitter halftone RAM 10 */
381: { 0xff8a16, SIZE_WORD, Blitter_Halftone11_ReadWord, Blitter_Halftone11_WriteWord }, /* Blitter halftone RAM 11 */
382: { 0xff8a18, SIZE_WORD, Blitter_Halftone12_ReadWord, Blitter_Halftone12_WriteWord }, /* Blitter halftone RAM 12 */
383: { 0xff8a1a, SIZE_WORD, Blitter_Halftone13_ReadWord, Blitter_Halftone13_WriteWord }, /* Blitter halftone RAM 13 */
384: { 0xff8a1c, SIZE_WORD, Blitter_Halftone14_ReadWord, Blitter_Halftone14_WriteWord }, /* Blitter halftone RAM 14 */
385: { 0xff8a1e, SIZE_WORD, Blitter_Halftone15_ReadWord, Blitter_Halftone15_WriteWord }, /* Blitter halftone RAM 15 */
386: { 0xff8a20, SIZE_WORD, Blitter_SourceXInc_ReadWord, Blitter_SourceXInc_WriteWord }, /* Blitter source x increment */
387: { 0xff8a22, SIZE_WORD, Blitter_SourceYInc_ReadWord, Blitter_SourceYInc_WriteWord }, /* Blitter source y increment */
1.1.1.2 root 388: { 0xff8a24, SIZE_LONG, Blitter_SourceAddr_ReadLong, Blitter_SourceAddr_WriteLong }, /* Blitter source address */
1.1 root 389: { 0xff8a28, SIZE_WORD, Blitter_Endmask1_ReadWord, Blitter_Endmask1_WriteWord },
390: { 0xff8a2a, SIZE_WORD, Blitter_Endmask2_ReadWord, Blitter_Endmask2_WriteWord },
391: { 0xff8a2c, SIZE_WORD, Blitter_Endmask3_ReadWord, Blitter_Endmask3_WriteWord },
1.1.1.3 root 392: { 0xff8a2e, SIZE_WORD, Blitter_DestXInc_ReadWord, Blitter_DestXInc_WriteWord }, /* Blitter dest. x increment */
393: { 0xff8a30, SIZE_WORD, Blitter_DestYInc_ReadWord, Blitter_DestYInc_WriteWord }, /* Blitter dest. y increment */
1.1 root 394: { 0xff8a32, SIZE_LONG, Blitter_DestAddr_ReadLong, Blitter_DestAddr_WriteLong },
395: { 0xff8a36, SIZE_WORD, Blitter_WordsPerLine_ReadWord, Blitter_WordsPerLine_WriteWord },
396: { 0xff8a38, SIZE_WORD, Blitter_LinesPerBitblock_ReadWord, Blitter_LinesPerBitblock_WriteWord },
397: { 0xff8a3a, SIZE_BYTE, Blitter_HalftoneOp_ReadByte, Blitter_HalftoneOp_WriteByte },
398: { 0xff8a3b, SIZE_BYTE, Blitter_LogOp_ReadByte, Blitter_LogOp_WriteByte },
399: { 0xff8a3c, SIZE_BYTE, Blitter_Control_ReadByte, Blitter_Control_WriteByte },
400: { 0xff8a3d, SIZE_BYTE, Blitter_Skew_ReadByte, Blitter_Skew_WriteByte },
1.1.1.14! root 401: { 0xff8a3e, SIZE_WORD, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1 root 402:
1.1.1.14! root 403: { 0xff8c80, 8, SCC_IoMem_ReadByte, SCC_IoMem_WriteByte }, /* SCC */
1.1 root 404:
1.1.1.12 root 405: { 0xff9200, SIZE_BYTE, IoMemTabFalc_Switches_ReadByte, IoMem_WriteWithoutInterception }, /* Falcon switches */
406: { 0xff9201, SIZE_BYTE, Joy_StePadButtons_ReadByte, IoMem_WriteWithoutInterception }, /* Joypad fire buttons */
1.1 root 407: { 0xff9202, SIZE_WORD, Joy_StePadMulti_ReadWord, Joy_StePadMulti_WriteWord }, /* Joypad directions/buttons/selection */
1.1.1.5 root 408: { 0xff9210, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1 root 409: { 0xff9211, SIZE_BYTE, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Joypad 0 X position (?) */
1.1.1.5 root 410: { 0xff9212, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1 root 411: { 0xff9213, SIZE_BYTE, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Joypad 0 Y position (?) */
1.1.1.5 root 412: { 0xff9214, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1 root 413: { 0xff9215, SIZE_BYTE, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Joypad 1 X position (?) */
1.1.1.5 root 414: { 0xff9216, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1 root 415: { 0xff9217, SIZE_BYTE, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Joypad 1 Y position (?) */
1.1.1.5 root 416: { 0xff9220, SIZE_WORD, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Lightpen X position */
417: { 0xff9222, SIZE_WORD, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Lightpen Y position */
1.1 root 418:
1.1.1.10 root 419: { 0xff9800, 0x400, IoMem_ReadWithoutInterception, VIDEL_FalconColorRegsWrite }, /* Falcon Videl palette */
1.1 root 420:
1.1.1.12 root 421: { 0xffc020, SIZE_BYTE, IoMemTabFalc_Compatible_ReadByte, IoMemTabFalc_Compatible_WriteByte },
422: { 0xffc021, SIZE_BYTE, IoMemTabFalc_Compatible_ReadByte, IoMemTabFalc_Compatible_WriteByte },
423: { 0xffd020, SIZE_BYTE, IoMemTabFalc_Compatible_ReadByte, IoMemTabFalc_Compatible_WriteByte },
424: { 0xffd074, SIZE_WORD, IoMemTabFalc_Compatible_ReadWord, IoMemTabFalc_Compatible_WriteWord },
425: { 0xffd420, SIZE_BYTE, IoMemTabFalc_Compatible_ReadByte, IoMemTabFalc_Compatible_WriteByte },
426: { 0xffd425, SIZE_BYTE, IoMemTabFalc_Compatible_ReadByte, IoMemTabFalc_Compatible_WriteByte },
427: { 0xffd520, SIZE_WORD, IoMemTabFalc_Compatible_ReadWord, IoMemTabFalc_Compatible_WriteWord },
428: { 0xffd530, SIZE_WORD, IoMemTabFalc_Compatible_ReadWord, IoMemTabFalc_Compatible_WriteWord },
429:
1.1 root 430: { 0xfffa00, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
431: { 0xfffa01, SIZE_BYTE, MFP_GPIP_ReadByte, MFP_GPIP_WriteByte },
432: { 0xfffa02, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
433: { 0xfffa03, SIZE_BYTE, MFP_ActiveEdge_ReadByte, MFP_ActiveEdge_WriteByte },
434: { 0xfffa04, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
435: { 0xfffa05, SIZE_BYTE, MFP_DataDirection_ReadByte, MFP_DataDirection_WriteByte },
436: { 0xfffa06, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
437: { 0xfffa07, SIZE_BYTE, MFP_EnableA_ReadByte, MFP_EnableA_WriteByte },
438: { 0xfffa08, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
439: { 0xfffa09, SIZE_BYTE, MFP_EnableB_ReadByte, MFP_EnableB_WriteByte },
440: { 0xfffa0a, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
441: { 0xfffa0b, SIZE_BYTE, MFP_PendingA_ReadByte, MFP_PendingA_WriteByte },
442: { 0xfffa0c, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
443: { 0xfffa0d, SIZE_BYTE, MFP_PendingB_ReadByte, MFP_PendingB_WriteByte },
444: { 0xfffa0e, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
445: { 0xfffa0f, SIZE_BYTE, MFP_InServiceA_ReadByte, MFP_InServiceA_WriteByte },
446: { 0xfffa10, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
447: { 0xfffa11, SIZE_BYTE, MFP_InServiceB_ReadByte, MFP_InServiceB_WriteByte },
448: { 0xfffa12, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
449: { 0xfffa13, SIZE_BYTE, MFP_MaskA_ReadByte, MFP_MaskA_WriteByte },
450: { 0xfffa14, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
451: { 0xfffa15, SIZE_BYTE, MFP_MaskB_ReadByte, MFP_MaskB_WriteByte },
452: { 0xfffa16, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
453: { 0xfffa17, SIZE_BYTE, MFP_VectorReg_ReadByte, MFP_VectorReg_WriteByte },
454: { 0xfffa18, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
455: { 0xfffa19, SIZE_BYTE, MFP_TimerACtrl_ReadByte, MFP_TimerACtrl_WriteByte },
456: { 0xfffa1a, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
457: { 0xfffa1b, SIZE_BYTE, MFP_TimerBCtrl_ReadByte, MFP_TimerBCtrl_WriteByte },
458: { 0xfffa1c, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
459: { 0xfffa1d, SIZE_BYTE, MFP_TimerCDCtrl_ReadByte, MFP_TimerCDCtrl_WriteByte },
460: { 0xfffa1e, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
461: { 0xfffa1f, SIZE_BYTE, MFP_TimerAData_ReadByte, MFP_TimerAData_WriteByte },
462: { 0xfffa20, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
463: { 0xfffa21, SIZE_BYTE, MFP_TimerBData_ReadByte, MFP_TimerBData_WriteByte },
464: { 0xfffa22, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
465: { 0xfffa23, SIZE_BYTE, MFP_TimerCData_ReadByte, MFP_TimerCData_WriteByte },
466: { 0xfffa24, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
467: { 0xfffa25, SIZE_BYTE, MFP_TimerDData_ReadByte, MFP_TimerDData_WriteByte },
468:
469: { 0xfffa26, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
470: { 0xfffa27, SIZE_BYTE, RS232_SCR_ReadByte, RS232_SCR_WriteByte }, /* Sync character register */
471: { 0xfffa28, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
472: { 0xfffa29, SIZE_BYTE, RS232_UCR_ReadByte, RS232_UCR_WriteByte }, /* USART control register */
473: { 0xfffa2a, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
474: { 0xfffa2b, SIZE_BYTE, RS232_RSR_ReadByte, RS232_RSR_WriteByte }, /* Receiver status register */
475: { 0xfffa2c, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
476: { 0xfffa2d, SIZE_BYTE, RS232_TSR_ReadByte, RS232_TSR_WriteByte }, /* Transmitter status register */
477: { 0xfffa2e, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
478: { 0xfffa2f, SIZE_BYTE, RS232_UDR_ReadByte, RS232_UDR_WriteByte }, /* USART data register */
479:
1.1.1.9 root 480: { 0xfffc00, SIZE_BYTE, ACIA_IKBD_Read_SR, ACIA_IKBD_Write_CR },
1.1 root 481: { 0xfffc01, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.9 root 482: { 0xfffc02, SIZE_BYTE, ACIA_IKBD_Read_RDR, ACIA_IKBD_Write_TDR },
1.1 root 483: { 0xfffc03, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
484: { 0xfffc04, SIZE_BYTE, Midi_Control_ReadByte, Midi_Control_WriteByte },
485: { 0xfffc05, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
486: { 0xfffc06, SIZE_BYTE, Midi_Data_ReadByte, Midi_Data_WriteByte },
487: { 0xfffc07, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus errors here */
488:
489: { 0xffff82, SIZE_WORD, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus errors here */
490:
491: { 0, 0, NULL, NULL }
492: };
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.