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1.1 root 1: /*
2: Hatari - ioMemTabFalcon.c
3:
1.1.1.9 ! root 4: This file is distributed under the GNU General Public License, version 2
! 5: or at your option any later version. Read the file gpl.txt for details.
1.1 root 6:
7: Table with hardware IO handlers for the Falcon.
8: */
1.1.1.3 root 9: const char IoMemTabFalc_fileid[] = "Hatari ioMemTabFalcon.c : " __DATE__ " " __TIME__;
1.1 root 10:
11: #include "main.h"
12: #include "fdc.h"
1.1.1.9 ! root 13: #include "acia.h"
1.1 root 14: #include "ioMem.h"
15: #include "ioMemTables.h"
1.1.1.6 root 16: #include "m68000.h"
1.1 root 17: #include "joy.h"
18: #include "mfp.h"
19: #include "midi.h"
20: #include "nvram.h"
21: #include "psg.h"
22: #include "rs232.h"
23: #include "rtc.h"
1.1.1.6 root 24: #include "screen.h"
1.1 root 25: #include "blitter.h"
1.1.1.5 root 26: #include "crossbar.h"
1.1 root 27: #include "falcon/videl.h"
28: #if ENABLE_DSP_EMU
29: #include "falcon/dsp.h"
30: #endif
31:
32: /**
33: * no DSP
34: */
35: void IoMemTabFalcon_DSPnone(void (**readtab)(void), void (**writetab)(void))
36: {
37: int i, offset;
38: offset = 0xffa200 - 0xff8000;
39: for (i = 0; i < 8; i++) {
40: readtab[offset+i] = IoMem_ReadWithoutInterception;
41: }
42: readtab[offset+2] = IoMem_VoidRead; /* TODO: why this is needed */
43: for (i = 0; i < 8; i++) {
44: writetab[offset+i] = IoMem_WriteWithoutInterception;
45: }
46: }
47:
48: /**
49: * Just a temporary hack - some programs are polling on this register and
50: * are expecting the handshake bit (#7) to change after a while...
51: */
52: static void DSP_DummyHostCommand_ReadByte(void)
53: {
54: IoMem[0xffa201] ^= 0x80;
55: }
56:
57: /**
58: * Just a temporary hack - some programs are polling on this register and
59: * are expecting some bits to change after a while...
60: */
61: static void DSP_DummyInterruptStatus_ReadByte(void)
62: {
63: IoMem[0xffa202] ^= 0xff;
64: }
65:
66: /**
67: * dummy IO when DSP emulation is not enabled
68: */
69: void IoMemTabFalcon_DSPdummy(void (**readtab)(void), void (**writetab)(void))
70: {
71: int i, offset;
72: offset = 0xffa200 - 0xff8000;
73: readtab[offset+0] = IoMem_ReadWithoutInterception;
74: readtab[offset+1] = DSP_DummyHostCommand_ReadByte;
75: readtab[offset+2] = DSP_DummyInterruptStatus_ReadByte;
76: for (i = 3; i < 8; i++) {
77: readtab[offset+i] = IoMem_ReadWithoutInterception;
78: }
79: for (i = 0; i < 8; i++) {
80: writetab[offset+i] = IoMem_WriteWithoutInterception;
81: }
82: }
83:
84: #if ENABLE_DSP_EMU
85: /**
86: * enable DSP emulation
87: */
88: void IoMemTabFalcon_DSPemulation(void (**readtab)(void), void (**writetab)(void))
89: {
90: int i, offset;
91: offset = 0xffa200 - 0xff8000;
92: for (i = 0; i < 8; i++) {
93: readtab[offset+i] = DSP_HandleReadAccess;
94: writetab[offset+i] = DSP_HandleWriteAccess;
95: }
96: }
97: #endif
98:
99:
1.1.1.6 root 100: /**
101: * Take into account the Falcon Bus Control register $ff8007.b
102: $FFFF8007 Falcon Bus Control
103: BIT 6 : F30 Start (0=Cold, 1=Warm)
104: BIT 5 : STe Bus Emulation (0=on)
105: BIT 3 : Blitter Flag (0=on, 1=off)
106: BIT 2 : Blitter (0=8mhz, 1=16mhz)
107: BIT 0 : 68030 (0=8mhz, 1=16mhz)
108: */
109: static void IoMemTabFalcon_BusCtrl_WriteByte(void)
110: {
111: Uint8 busCtrl = IoMem_ReadByte(0xff8007);
112:
113: /* Set Falcon bus or STE compatible bus emulation */
114: if ((busCtrl & 0x20) == 0)
115: IoMem_Init_FalconInSTeBuscompatibilityMode(0);
116: else
117: IoMem_Init_FalconInSTeBuscompatibilityMode(1);
118:
119: /* 68030 Frequency changed ? */
120: if ((busCtrl & 0x1) == 1) {
121: /* 16 Mhz bus for 68030 */
122: nCpuFreqShift = 1;
123: }
124: else {
125: /* 8 Mhz bus for 68030 */
126: nCpuFreqShift = 0;
127: }
128: }
129:
130:
1.1 root 131: /*-----------------------------------------------------------------------*/
132: /*
133: List of functions to handle read/write hardware interceptions for a Falcon.
134: */
135: const INTERCEPT_ACCESS_FUNC IoMemTable_Falcon[] =
136: {
137: { 0xff8000, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
138: { 0xff8001, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception }, /* Memory configuration */
1.1.1.6 root 139: { 0xff8006, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_Monitor_WriteByte }, /* Falcon monitor and memory configuration */
140: { 0xff8007, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMemTabFalcon_BusCtrl_WriteByte }, /* Falcon bus configuration */
1.1 root 141: { 0xff800C, SIZE_WORD, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
142: { 0xff8060, SIZE_LONG, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
143:
144: { 0xff8200, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.6 root 145: { 0xff8201, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_ScreenBase_WriteByte }, /* Video base high byte */
1.1 root 146: { 0xff8202, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.6 root 147: { 0xff8203, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_ScreenBase_WriteByte }, /* Video base med byte */
1.1 root 148: { 0xff8204, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.8 root 149: { 0xff8205, SIZE_BYTE, VIDEL_ScreenCounter_ReadByte, VIDEL_ScreenCounter_WriteByte },
1.1 root 150: { 0xff8206, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.8 root 151: { 0xff8207, SIZE_BYTE, VIDEL_ScreenCounter_ReadByte, VIDEL_ScreenCounter_WriteByte },
1.1 root 152: { 0xff8208, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.8 root 153: { 0xff8209, SIZE_BYTE, VIDEL_ScreenCounter_ReadByte, VIDEL_ScreenCounter_WriteByte },
154: { 0xff820a, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_SyncMode_WriteByte }, /* VIDEL Synch mode */
1.1.1.6 root 155: { 0xff820b, SIZE_BYTE, IoMem_VoidRead_00, IoMem_VoidWrite }, /* No bus error here : return 0 not ff */
156: { 0xff820c, SIZE_BYTE, IoMem_VoidRead_00, IoMem_VoidWrite }, /* No bus error here : return 0 not ff */
1.1.1.8 root 157: { 0xff820d, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_ScreenBase_WriteByte }, /* Video base low byte */
158: { 0xff820e, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_LineOffset_WriteWord }, /* Falcon line offset */
159: { 0xff8210, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_Line_Width_WriteWord }, /* Falcon line width */
160: { 0xff8212, 46 , IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
161: { 0xff8240, 32 , IoMem_ReadWithoutInterception, VIDEL_ColorRegsWrite }, /* ST color regs */
162: { 0xff8260, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_ST_ShiftModeWriteByte },
163: { 0xff8261, 3 , IoMem_VoidRead_00, IoMem_VoidWrite }, /* No bus errors here : return 0 not ff */
164: { 0xff8264, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_HorScroll64_WriteByte }, /* Falcon horizontal fine scrolling high ? */
165: { 0xff8265, SIZE_BYTE, IoMem_ReadWithoutInterception, VIDEL_HorScroll65_WriteByte }, /* horizontal fine scrolling */
166: { 0xff8266, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_Falcon_ShiftMode_WriteWord }, /* Falcon shift mode */
167: { 0xff8268, 24 , IoMem_VoidRead_00, IoMem_VoidWrite }, /* No bus errors here : return 0 not ff */
1.1 root 168:
1.1.1.6 root 169: { 0xff8280, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HHC_WriteWord }, /* HHC : Horizontal Hold Counter */
170: { 0xff8282, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HHT_WriteWord }, /* HHT : Horizontal Hold Timer */
171: { 0xff8284, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HBB_WriteWord }, /* HBB : Horizontal Border Begin */
172: { 0xff8286, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HBE_WriteWord }, /* HBE : Horizontal Border End */
173: { 0xff8288, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HDB_WriteWord }, /* HDB : Horizontal Display Begin */
174: { 0xff828a, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HDE_WriteWord }, /* HDE : Horizontal Display End */
175: { 0xff828c, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HSS_WriteWord }, /* HSS : Horizontal SS */
176: { 0xff828e, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HFS_WriteWord }, /* HFS : Horizontal FS */
177: { 0xff8290, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_HEE_WriteWord }, /* HEE : Horizontal EE */
178: { 0xff8292, 14, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus errors here */
179: { 0xff82a0, SIZE_WORD, VIDEL_VFC_ReadWord, IoMem_VoidWrite }, /* VFC - Vertical Frequency Counter */
180: { 0xff82a2, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VFT_WriteWord }, /* VFT - Vertical Frequency Timer */
181: { 0xff82a4, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VBB_WriteWord }, /* VBB - Vertical Border Begin */
182: { 0xff82a6, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VBE_WriteWord }, /* VBE - Vertical Border End */
183: { 0xff82a8, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VDB_WriteWord }, /* VDB - Vertical Display Begin */
184: { 0xff82aa, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VDE_WriteWord }, /* VDE - Vertical Display End */
185: { 0xff82ac, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VSS_WriteWord }, /* VSS - Vertical SS */
186: { 0xff82ae, 18, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus errors here */
187: { 0xff82c0, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VCO_WriteWord }, /* VCO - Video control */
188: { 0xff82c2, SIZE_WORD, IoMem_ReadWithoutInterception, VIDEL_VMD_WriteWord }, /* VMD - Video mode */
1.1 root 189:
190: { 0xff8604, SIZE_WORD, FDC_DiskControllerStatus_ReadWord, FDC_DiskController_WriteWord },
191: { 0xff8606, SIZE_WORD, FDC_DmaStatus_ReadWord, FDC_DmaModeControl_WriteWord },
192: { 0xff8608, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.7 root 193: { 0xff8609, SIZE_BYTE, FDC_DmaAddress_ReadByte, FDC_DmaAddress_WriteByte }, /* DMA base and counter high byte */
1.1 root 194: { 0xff860a, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.7 root 195: { 0xff860b, SIZE_BYTE, FDC_DmaAddress_ReadByte, FDC_DmaAddress_WriteByte }, /* DMA base and counter med byte */
1.1 root 196: { 0xff860c, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.7 root 197: { 0xff860d, SIZE_BYTE, FDC_DmaAddress_ReadByte, FDC_DmaAddress_WriteByte }, /* DMA base and counter low byte */
1.1 root 198: { 0xff860e, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
199: { 0xff860f, SIZE_BYTE, FDC_FloppyMode_ReadByte, FDC_FloppyMode_WriteByte }, /* Floppy mode (?) register */
200:
1.1.1.4 root 201: { 0xff8800, SIZE_BYTE, PSG_ff8800_ReadByte, PSG_ff8800_WriteByte },
202: { 0xff8801, SIZE_BYTE, PSG_ff880x_ReadByte, PSG_ff8801_WriteByte },
203: { 0xff8802, SIZE_BYTE, PSG_ff880x_ReadByte, PSG_ff8802_WriteByte },
204: { 0xff8803, SIZE_BYTE, PSG_ff880x_ReadByte, PSG_ff8803_WriteByte },
1.1 root 205:
1.1.1.5 root 206: { 0xff8900, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_BufferInter_WriteByte }, /* Crossbar Buffer interrupts */
207: { 0xff8901, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_DmaCtrlReg_WriteByte }, /* Crossbar control register */
208: { 0xff8902, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
209: { 0xff8903, SIZE_BYTE, Crossbar_FrameStartHigh_ReadByte, Crossbar_FrameStartHigh_WriteByte }, /* DMA sound frame start high */
210: { 0xff8904, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
211: { 0xff8905, SIZE_BYTE, Crossbar_FrameStartMed_ReadByte, Crossbar_FrameStartMed_WriteByte }, /* DMA sound frame start med */
212: { 0xff8906, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
213: { 0xff8907, SIZE_BYTE, Crossbar_FrameStartLow_ReadByte, Crossbar_FrameStartLow_WriteByte }, /* DMA sound frame start low */
214: { 0xff8908, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
215: { 0xff8909, SIZE_BYTE, Crossbar_FrameCountHigh_ReadByte, Crossbar_FrameCountHigh_WriteByte }, /* DMA sound frame count high */
216: { 0xff890a, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
217: { 0xff890b, SIZE_BYTE, Crossbar_FrameCountMed_ReadByte, Crossbar_FrameCountMed_WriteByte }, /* DMA sound frame count med */
218: { 0xff890c, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
219: { 0xff890d, SIZE_BYTE, Crossbar_FrameCountLow_ReadByte, Crossbar_FrameCountLow_WriteByte }, /* DMA sound frame count low */
220: { 0xff890e, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
221: { 0xff890f, SIZE_BYTE, Crossbar_FrameEndHigh_ReadByte, Crossbar_FrameEndHigh_WriteByte }, /* DMA sound frame end high */
222: { 0xff8910, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
223: { 0xff8911, SIZE_BYTE, Crossbar_FrameEndMed_ReadByte, Crossbar_FrameEndMed_WriteByte }, /* DMA sound frame end med */
224: { 0xff8912, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
225: { 0xff8913, SIZE_BYTE, Crossbar_FrameEndLow_ReadByte, Crossbar_FrameEndLow_WriteByte }, /* DMA sound frame end low */
226: { 0xff8920, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_DmaTrckCtrl_WriteByte }, /* Crossbar track control */
227: { 0xff8921, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_SoundModeCtrl_WriteByte }, /* DMA sound mode control */
1.1.1.8 root 228: { 0xff8922, SIZE_WORD, IoMem_VoidRead_00, IoMem_VoidWrite }, /* Microwire data - n/a on Falcon, alwayes read 0 */
229: { 0xff8924, SIZE_WORD, IoMem_ReadWithoutInterception, Crossbar_Microwire_WriteWord }, /* Microwire mask - n/a on Falcon, see crossbar.c */
1.1.1.5 root 230:
1.1.1.9 ! root 231: { 0xff8930, SIZE_WORD, IoMem_ReadWithoutInterception, Crossbar_SrcControler_WriteWord }, /* Crossbar source controller */
! 232: { 0xff8932, SIZE_WORD, IoMem_ReadWithoutInterception, Crossbar_DstControler_WriteWord }, /* Crossbar destination controller */
1.1.1.5 root 233: { 0xff8934, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_FreqDivExt_WriteByte }, /* External clock divider */
234: { 0xff8935, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_FreqDivInt_WriteByte }, /* Internal clock divider */
235: { 0xff8936, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_TrackRecSelect_WriteByte }, /* Track record select */
236: { 0xff8937, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_CodecInput_WriteByte }, /* CODEC input source from 16 bits adder */
237: { 0xff8938, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_AdcInput_WriteByte }, /* ADC converter input for L+R channel */
238: { 0xff8939, SIZE_BYTE, IoMem_ReadWithoutInterception, Crossbar_InputAmp_WriteByte }, /* Input amplifier (+1.5 dB step) */
1.1.1.9 ! root 239: { 0xff893a, SIZE_WORD, IoMem_ReadWithoutInterception, Crossbar_OutputReduct_WriteWord }, /* Output reduction (-1.5 dB step) */
1.1.1.5 root 240: { 0xff893c, SIZE_WORD, IoMem_ReadWithoutInterception, Crossbar_CodecStatus_WriteWord }, /* CODEC status */
241: { 0xff893e, SIZE_WORD, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception }, /* No bus error here */
242: { 0xff8940, SIZE_WORD, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception }, /* GPx direction */
243: { 0xff8942, SIZE_WORD, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception }, /* GPx port */
1.1 root 244:
245: { 0xff8960, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
246: { 0xff8961, SIZE_BYTE, NvRam_Select_ReadByte, NvRam_Select_WriteByte }, /* NVRAM/RTC chip */
247: { 0xff8962, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
248: { 0xff8963, SIZE_BYTE, NvRam_Data_ReadByte, NvRam_Data_WriteByte }, /* NVRAM/RTC chip */
249:
1.1.1.3 root 250: { 0xff8a00, SIZE_WORD, Blitter_Halftone00_ReadWord, Blitter_Halftone00_WriteWord }, /* Blitter halftone RAM 0 */
251: { 0xff8a02, SIZE_WORD, Blitter_Halftone01_ReadWord, Blitter_Halftone01_WriteWord }, /* Blitter halftone RAM 1 */
252: { 0xff8a04, SIZE_WORD, Blitter_Halftone02_ReadWord, Blitter_Halftone02_WriteWord }, /* Blitter halftone RAM 2 */
253: { 0xff8a06, SIZE_WORD, Blitter_Halftone03_ReadWord, Blitter_Halftone03_WriteWord }, /* Blitter halftone RAM 3 */
254: { 0xff8a08, SIZE_WORD, Blitter_Halftone04_ReadWord, Blitter_Halftone04_WriteWord }, /* Blitter halftone RAM 4 */
255: { 0xff8a0a, SIZE_WORD, Blitter_Halftone05_ReadWord, Blitter_Halftone05_WriteWord }, /* Blitter halftone RAM 5 */
256: { 0xff8a0c, SIZE_WORD, Blitter_Halftone06_ReadWord, Blitter_Halftone06_WriteWord }, /* Blitter halftone RAM 6 */
257: { 0xff8a0e, SIZE_WORD, Blitter_Halftone07_ReadWord, Blitter_Halftone07_WriteWord }, /* Blitter halftone RAM 7 */
258: { 0xff8a10, SIZE_WORD, Blitter_Halftone08_ReadWord, Blitter_Halftone08_WriteWord }, /* Blitter halftone RAM 8 */
259: { 0xff8a12, SIZE_WORD, Blitter_Halftone09_ReadWord, Blitter_Halftone09_WriteWord }, /* Blitter halftone RAM 9 */
260: { 0xff8a14, SIZE_WORD, Blitter_Halftone10_ReadWord, Blitter_Halftone10_WriteWord }, /* Blitter halftone RAM 10 */
261: { 0xff8a16, SIZE_WORD, Blitter_Halftone11_ReadWord, Blitter_Halftone11_WriteWord }, /* Blitter halftone RAM 11 */
262: { 0xff8a18, SIZE_WORD, Blitter_Halftone12_ReadWord, Blitter_Halftone12_WriteWord }, /* Blitter halftone RAM 12 */
263: { 0xff8a1a, SIZE_WORD, Blitter_Halftone13_ReadWord, Blitter_Halftone13_WriteWord }, /* Blitter halftone RAM 13 */
264: { 0xff8a1c, SIZE_WORD, Blitter_Halftone14_ReadWord, Blitter_Halftone14_WriteWord }, /* Blitter halftone RAM 14 */
265: { 0xff8a1e, SIZE_WORD, Blitter_Halftone15_ReadWord, Blitter_Halftone15_WriteWord }, /* Blitter halftone RAM 15 */
266: { 0xff8a20, SIZE_WORD, Blitter_SourceXInc_ReadWord, Blitter_SourceXInc_WriteWord }, /* Blitter source x increment */
267: { 0xff8a22, SIZE_WORD, Blitter_SourceYInc_ReadWord, Blitter_SourceYInc_WriteWord }, /* Blitter source y increment */
1.1.1.2 root 268: { 0xff8a24, SIZE_LONG, Blitter_SourceAddr_ReadLong, Blitter_SourceAddr_WriteLong }, /* Blitter source address */
1.1 root 269: { 0xff8a28, SIZE_WORD, Blitter_Endmask1_ReadWord, Blitter_Endmask1_WriteWord },
270: { 0xff8a2a, SIZE_WORD, Blitter_Endmask2_ReadWord, Blitter_Endmask2_WriteWord },
271: { 0xff8a2c, SIZE_WORD, Blitter_Endmask3_ReadWord, Blitter_Endmask3_WriteWord },
1.1.1.3 root 272: { 0xff8a2e, SIZE_WORD, Blitter_DestXInc_ReadWord, Blitter_DestXInc_WriteWord }, /* Blitter dest. x increment */
273: { 0xff8a30, SIZE_WORD, Blitter_DestYInc_ReadWord, Blitter_DestYInc_WriteWord }, /* Blitter dest. y increment */
1.1 root 274: { 0xff8a32, SIZE_LONG, Blitter_DestAddr_ReadLong, Blitter_DestAddr_WriteLong },
275: { 0xff8a36, SIZE_WORD, Blitter_WordsPerLine_ReadWord, Blitter_WordsPerLine_WriteWord },
276: { 0xff8a38, SIZE_WORD, Blitter_LinesPerBitblock_ReadWord, Blitter_LinesPerBitblock_WriteWord },
277: { 0xff8a3a, SIZE_BYTE, Blitter_HalftoneOp_ReadByte, Blitter_HalftoneOp_WriteByte },
278: { 0xff8a3b, SIZE_BYTE, Blitter_LogOp_ReadByte, Blitter_LogOp_WriteByte },
279: { 0xff8a3c, SIZE_BYTE, Blitter_Control_ReadByte, Blitter_Control_WriteByte },
280: { 0xff8a3d, SIZE_BYTE, Blitter_Skew_ReadByte, Blitter_Skew_WriteByte },
281: { 0xff8a3e, SIZE_WORD, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
282:
283: { 0xff8c80, 8, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* TODO: SCC */
284:
1.1.1.5 root 285: { 0xff9200, SIZE_WORD, Joy_StePadButtons_ReadWord, IoMem_WriteWithoutInterception }, /* Joypad fire buttons */
1.1 root 286: { 0xff9202, SIZE_WORD, Joy_StePadMulti_ReadWord, Joy_StePadMulti_WriteWord }, /* Joypad directions/buttons/selection */
1.1.1.5 root 287: { 0xff9206, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here ; fix Wotanoid game */
288: { 0xff9210, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1 root 289: { 0xff9211, SIZE_BYTE, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Joypad 0 X position (?) */
1.1.1.5 root 290: { 0xff9212, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1 root 291: { 0xff9213, SIZE_BYTE, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Joypad 0 Y position (?) */
1.1.1.5 root 292: { 0xff9214, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1 root 293: { 0xff9215, SIZE_BYTE, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Joypad 1 X position (?) */
1.1.1.5 root 294: { 0xff9216, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1 root 295: { 0xff9217, SIZE_BYTE, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Joypad 1 Y position (?) */
1.1.1.5 root 296: { 0xff9220, SIZE_WORD, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Lightpen X position */
297: { 0xff9222, SIZE_WORD, IoMem_VoidRead, IoMem_WriteWithoutInterception }, /* Lightpen Y position */
1.1 root 298:
299: { 0xff9800, 0x400, IoMem_ReadWithoutInterception, VIDEL_ColorRegsWrite }, /* Falcon Videl palette */
300:
301: { 0xfffa00, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
302: { 0xfffa01, SIZE_BYTE, MFP_GPIP_ReadByte, MFP_GPIP_WriteByte },
303: { 0xfffa02, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
304: { 0xfffa03, SIZE_BYTE, MFP_ActiveEdge_ReadByte, MFP_ActiveEdge_WriteByte },
305: { 0xfffa04, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
306: { 0xfffa05, SIZE_BYTE, MFP_DataDirection_ReadByte, MFP_DataDirection_WriteByte },
307: { 0xfffa06, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
308: { 0xfffa07, SIZE_BYTE, MFP_EnableA_ReadByte, MFP_EnableA_WriteByte },
309: { 0xfffa08, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
310: { 0xfffa09, SIZE_BYTE, MFP_EnableB_ReadByte, MFP_EnableB_WriteByte },
311: { 0xfffa0a, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
312: { 0xfffa0b, SIZE_BYTE, MFP_PendingA_ReadByte, MFP_PendingA_WriteByte },
313: { 0xfffa0c, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
314: { 0xfffa0d, SIZE_BYTE, MFP_PendingB_ReadByte, MFP_PendingB_WriteByte },
315: { 0xfffa0e, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
316: { 0xfffa0f, SIZE_BYTE, MFP_InServiceA_ReadByte, MFP_InServiceA_WriteByte },
317: { 0xfffa10, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
318: { 0xfffa11, SIZE_BYTE, MFP_InServiceB_ReadByte, MFP_InServiceB_WriteByte },
319: { 0xfffa12, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
320: { 0xfffa13, SIZE_BYTE, MFP_MaskA_ReadByte, MFP_MaskA_WriteByte },
321: { 0xfffa14, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
322: { 0xfffa15, SIZE_BYTE, MFP_MaskB_ReadByte, MFP_MaskB_WriteByte },
323: { 0xfffa16, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
324: { 0xfffa17, SIZE_BYTE, MFP_VectorReg_ReadByte, MFP_VectorReg_WriteByte },
325: { 0xfffa18, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
326: { 0xfffa19, SIZE_BYTE, MFP_TimerACtrl_ReadByte, MFP_TimerACtrl_WriteByte },
327: { 0xfffa1a, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
328: { 0xfffa1b, SIZE_BYTE, MFP_TimerBCtrl_ReadByte, MFP_TimerBCtrl_WriteByte },
329: { 0xfffa1c, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
330: { 0xfffa1d, SIZE_BYTE, MFP_TimerCDCtrl_ReadByte, MFP_TimerCDCtrl_WriteByte },
331: { 0xfffa1e, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
332: { 0xfffa1f, SIZE_BYTE, MFP_TimerAData_ReadByte, MFP_TimerAData_WriteByte },
333: { 0xfffa20, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
334: { 0xfffa21, SIZE_BYTE, MFP_TimerBData_ReadByte, MFP_TimerBData_WriteByte },
335: { 0xfffa22, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
336: { 0xfffa23, SIZE_BYTE, MFP_TimerCData_ReadByte, MFP_TimerCData_WriteByte },
337: { 0xfffa24, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
338: { 0xfffa25, SIZE_BYTE, MFP_TimerDData_ReadByte, MFP_TimerDData_WriteByte },
339:
340: { 0xfffa26, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
341: { 0xfffa27, SIZE_BYTE, RS232_SCR_ReadByte, RS232_SCR_WriteByte }, /* Sync character register */
342: { 0xfffa28, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
343: { 0xfffa29, SIZE_BYTE, RS232_UCR_ReadByte, RS232_UCR_WriteByte }, /* USART control register */
344: { 0xfffa2a, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
345: { 0xfffa2b, SIZE_BYTE, RS232_RSR_ReadByte, RS232_RSR_WriteByte }, /* Receiver status register */
346: { 0xfffa2c, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
347: { 0xfffa2d, SIZE_BYTE, RS232_TSR_ReadByte, RS232_TSR_WriteByte }, /* Transmitter status register */
348: { 0xfffa2e, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
349: { 0xfffa2f, SIZE_BYTE, RS232_UDR_ReadByte, RS232_UDR_WriteByte }, /* USART data register */
350:
1.1.1.9 ! root 351: { 0xfffc00, SIZE_BYTE, ACIA_IKBD_Read_SR, ACIA_IKBD_Write_CR },
1.1 root 352: { 0xfffc01, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.9 ! root 353: { 0xfffc02, SIZE_BYTE, ACIA_IKBD_Read_RDR, ACIA_IKBD_Write_TDR },
1.1 root 354: { 0xfffc03, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
355: { 0xfffc04, SIZE_BYTE, Midi_Control_ReadByte, Midi_Control_WriteByte },
356: { 0xfffc05, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
357: { 0xfffc06, SIZE_BYTE, Midi_Data_ReadByte, Midi_Data_WriteByte },
358: { 0xfffc07, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus errors here */
359:
360: { 0xffff82, SIZE_WORD, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus errors here */
361:
362: { 0, 0, NULL, NULL }
363: };
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