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1.1 root 1: /*
2: Hatari - ioMemTabST.c
3:
1.1.1.6 root 4: This file is distributed under the GNU General Public License, version 2
5: or at your option any later version. Read the file gpl.txt for details.
1.1 root 6:
7: Table with hardware IO handlers for the ST.
8: */
9:
10: /* 2007/04/29 [NP] Functions PSG_Void_WriteByte and PSG_Void_ReadByte to handle */
11: /* accesses to $ff8801/03. These adresses have no effect, but they */
12: /* give some wait states (e.g. move.l d0,ff8800). */
13: /* 2007/12/16 [NP] 0xff820d/0xff820f are only available on STE, not on ST. We call */
14: /* IoMem_VoidRead and IoMem_VoidWrite for these addresses. */
1.1.1.3 root 15: /* 2008/12/21 [NP] Change functions used to access 0xff88xx (see psg.c) */
1.1 root 16:
1.1.1.3 root 17:
18: const char IoMemTabST_fileid[] = "Hatari ioMemTabST.c : " __DATE__ " " __TIME__;
1.1 root 19:
20: #include "main.h"
1.1.1.8 ! root 21: #include "configuration.h"
1.1 root 22: #include "dmaSnd.h"
23: #include "fdc.h"
1.1.1.6 root 24: #include "acia.h"
1.1 root 25: #include "ioMem.h"
26: #include "ioMemTables.h"
27: #include "joy.h"
28: #include "mfp.h"
29: #include "midi.h"
30: #include "psg.h"
31: #include "rs232.h"
32: #include "rtc.h"
1.1.1.4 root 33: #include "screen.h"
1.1 root 34: #include "video.h"
35: #include "blitter.h"
36:
37:
38: /*-----------------------------------------------------------------------*/
39: /*
40: List of functions to handle read/write hardware interceptions for a plain ST.
41: */
42: const INTERCEPT_ACCESS_FUNC IoMemTable_ST[] =
43: {
44: { 0xff8001, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception }, /* Memory configuration */
45:
1.1.1.8 ! root 46: { 0xff8201, SIZE_BYTE, IoMem_ReadWithoutInterception, Video_ScreenBase_WriteByte }, /* Video base high byte */
! 47: { 0xff8203, SIZE_BYTE, IoMem_ReadWithoutInterception, Video_ScreenBase_WriteByte }, /* Video base med byte */
1.1 root 48: { 0xff8205, SIZE_BYTE, Video_ScreenCounter_ReadByte, IoMem_WriteWithoutInterception },
49: { 0xff8207, SIZE_BYTE, Video_ScreenCounter_ReadByte, IoMem_WriteWithoutInterception },
50: { 0xff8209, SIZE_BYTE, Video_ScreenCounter_ReadByte, IoMem_WriteWithoutInterception },
51: { 0xff820a, SIZE_BYTE, Video_Sync_ReadByte, Video_Sync_WriteByte },
52: { 0xff820b, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
53: { 0xff820d, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite },
1.1.1.7 root 54: { 0xff8240, SIZE_WORD, Video_Color0_ReadWord, Video_Color0_WriteWord }, /* COLOR 0 */
55: { 0xff8242, SIZE_WORD, Video_Color1_ReadWord, Video_Color1_WriteWord }, /* COLOR 1 */
56: { 0xff8244, SIZE_WORD, Video_Color2_ReadWord, Video_Color2_WriteWord }, /* COLOR 2 */
57: { 0xff8246, SIZE_WORD, Video_Color3_ReadWord, Video_Color3_WriteWord }, /* COLOR 3 */
58: { 0xff8248, SIZE_WORD, Video_Color4_ReadWord, Video_Color4_WriteWord }, /* COLOR 4 */
59: { 0xff824a, SIZE_WORD, Video_Color5_ReadWord, Video_Color5_WriteWord }, /* COLOR 5 */
60: { 0xff824c, SIZE_WORD, Video_Color6_ReadWord, Video_Color6_WriteWord }, /* COLOR 6 */
61: { 0xff824e, SIZE_WORD, Video_Color7_ReadWord, Video_Color7_WriteWord }, /* COLOR 7 */
62: { 0xff8250, SIZE_WORD, Video_Color8_ReadWord, Video_Color8_WriteWord }, /* COLOR 8 */
63: { 0xff8252, SIZE_WORD, Video_Color9_ReadWord, Video_Color9_WriteWord }, /* COLOR 9 */
64: { 0xff8254, SIZE_WORD, Video_Color10_ReadWord, Video_Color10_WriteWord }, /* COLOR 10 */
65: { 0xff8256, SIZE_WORD, Video_Color11_ReadWord, Video_Color11_WriteWord }, /* COLOR 11 */
66: { 0xff8258, SIZE_WORD, Video_Color12_ReadWord, Video_Color12_WriteWord }, /* COLOR 12 */
67: { 0xff825a, SIZE_WORD, Video_Color13_ReadWord, Video_Color13_WriteWord }, /* COLOR 13 */
68: { 0xff825c, SIZE_WORD, Video_Color14_ReadWord, Video_Color14_WriteWord }, /* COLOR 14 */
69: { 0xff825e, SIZE_WORD, Video_Color15_ReadWord, Video_Color15_WriteWord }, /* COLOR 15 */
1.1.1.8 ! root 70: { 0xff8260, SIZE_BYTE, Video_Res_ReadByte, Video_Res_WriteByte },
1.1 root 71: { 0xff8261, 31, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus errors here */
72:
73: { 0xff8604, SIZE_WORD, FDC_DiskControllerStatus_ReadWord, FDC_DiskController_WriteWord },
74: { 0xff8606, SIZE_WORD, FDC_DmaStatus_ReadWord, FDC_DmaModeControl_WriteWord },
1.1.1.5 root 75: { 0xff8609, SIZE_BYTE, FDC_DmaAddress_ReadByte, FDC_DmaAddress_WriteByte }, /* DMA base and counter high byte */
76: { 0xff860b, SIZE_BYTE, FDC_DmaAddress_ReadByte, FDC_DmaAddress_WriteByte }, /* DMA base and counter med byte */
77: { 0xff860d, SIZE_BYTE, FDC_DmaAddress_ReadByte, FDC_DmaAddress_WriteByte }, /* DMA base and counter low byte */
1.1 root 78:
1.1.1.3 root 79: { 0xff8800, SIZE_BYTE, PSG_ff8800_ReadByte, PSG_ff8800_WriteByte },
80: { 0xff8801, SIZE_BYTE, PSG_ff880x_ReadByte, PSG_ff8801_WriteByte },
81: { 0xff8802, SIZE_BYTE, PSG_ff880x_ReadByte, PSG_ff8802_WriteByte },
82: { 0xff8803, SIZE_BYTE, PSG_ff880x_ReadByte, PSG_ff8803_WriteByte },
83:
84: { 0xff8a00, SIZE_WORD, Blitter_Halftone00_ReadWord, Blitter_Halftone00_WriteWord }, /* Blitter halftone RAM 0 */
85: { 0xff8a02, SIZE_WORD, Blitter_Halftone01_ReadWord, Blitter_Halftone01_WriteWord }, /* Blitter halftone RAM 1 */
86: { 0xff8a04, SIZE_WORD, Blitter_Halftone02_ReadWord, Blitter_Halftone02_WriteWord }, /* Blitter halftone RAM 2 */
87: { 0xff8a06, SIZE_WORD, Blitter_Halftone03_ReadWord, Blitter_Halftone03_WriteWord }, /* Blitter halftone RAM 3 */
88: { 0xff8a08, SIZE_WORD, Blitter_Halftone04_ReadWord, Blitter_Halftone04_WriteWord }, /* Blitter halftone RAM 4 */
89: { 0xff8a0a, SIZE_WORD, Blitter_Halftone05_ReadWord, Blitter_Halftone05_WriteWord }, /* Blitter halftone RAM 5 */
90: { 0xff8a0c, SIZE_WORD, Blitter_Halftone06_ReadWord, Blitter_Halftone06_WriteWord }, /* Blitter halftone RAM 6 */
91: { 0xff8a0e, SIZE_WORD, Blitter_Halftone07_ReadWord, Blitter_Halftone07_WriteWord }, /* Blitter halftone RAM 7 */
92: { 0xff8a10, SIZE_WORD, Blitter_Halftone08_ReadWord, Blitter_Halftone08_WriteWord }, /* Blitter halftone RAM 8 */
93: { 0xff8a12, SIZE_WORD, Blitter_Halftone09_ReadWord, Blitter_Halftone09_WriteWord }, /* Blitter halftone RAM 9 */
94: { 0xff8a14, SIZE_WORD, Blitter_Halftone10_ReadWord, Blitter_Halftone10_WriteWord }, /* Blitter halftone RAM 10 */
95: { 0xff8a16, SIZE_WORD, Blitter_Halftone11_ReadWord, Blitter_Halftone11_WriteWord }, /* Blitter halftone RAM 11 */
96: { 0xff8a18, SIZE_WORD, Blitter_Halftone12_ReadWord, Blitter_Halftone12_WriteWord }, /* Blitter halftone RAM 12 */
97: { 0xff8a1a, SIZE_WORD, Blitter_Halftone13_ReadWord, Blitter_Halftone13_WriteWord }, /* Blitter halftone RAM 13 */
98: { 0xff8a1c, SIZE_WORD, Blitter_Halftone14_ReadWord, Blitter_Halftone14_WriteWord }, /* Blitter halftone RAM 14 */
99: { 0xff8a1e, SIZE_WORD, Blitter_Halftone15_ReadWord, Blitter_Halftone15_WriteWord }, /* Blitter halftone RAM 15 */
100: { 0xff8a20, SIZE_WORD, Blitter_SourceXInc_ReadWord, Blitter_SourceXInc_WriteWord }, /* Blitter source x increment */
101: { 0xff8a22, SIZE_WORD, Blitter_SourceYInc_ReadWord, Blitter_SourceYInc_WriteWord }, /* Blitter source y increment */
1.1.1.2 root 102: { 0xff8a24, SIZE_LONG, Blitter_SourceAddr_ReadLong, Blitter_SourceAddr_WriteLong }, /* Blitter source address */
1.1 root 103: { 0xff8a28, SIZE_WORD, Blitter_Endmask1_ReadWord, Blitter_Endmask1_WriteWord },
104: { 0xff8a2a, SIZE_WORD, Blitter_Endmask2_ReadWord, Blitter_Endmask2_WriteWord },
105: { 0xff8a2c, SIZE_WORD, Blitter_Endmask3_ReadWord, Blitter_Endmask3_WriteWord },
1.1.1.3 root 106: { 0xff8a2e, SIZE_WORD, Blitter_DestXInc_ReadWord, Blitter_DestXInc_WriteWord }, /* Blitter dest. x increment */
107: { 0xff8a30, SIZE_WORD, Blitter_DestYInc_ReadWord, Blitter_DestYInc_WriteWord }, /* Blitter dest. y increment */
1.1 root 108: { 0xff8a32, SIZE_LONG, Blitter_DestAddr_ReadLong, Blitter_DestAddr_WriteLong },
109: { 0xff8a36, SIZE_WORD, Blitter_WordsPerLine_ReadWord, Blitter_WordsPerLine_WriteWord },
110: { 0xff8a38, SIZE_WORD, Blitter_LinesPerBitblock_ReadWord, Blitter_LinesPerBitblock_WriteWord },
111: { 0xff8a3a, SIZE_BYTE, Blitter_HalftoneOp_ReadByte, Blitter_HalftoneOp_WriteByte },
112: { 0xff8a3b, SIZE_BYTE, Blitter_LogOp_ReadByte, Blitter_LogOp_WriteByte },
113: { 0xff8a3c, SIZE_BYTE, Blitter_Control_ReadByte, Blitter_Control_WriteByte },
114: { 0xff8a3d, SIZE_BYTE, Blitter_Skew_ReadByte, Blitter_Skew_WriteByte },
115:
116: { 0xfffa01, SIZE_BYTE, MFP_GPIP_ReadByte, MFP_GPIP_WriteByte },
117: { 0xfffa03, SIZE_BYTE, MFP_ActiveEdge_ReadByte, MFP_ActiveEdge_WriteByte },
118: { 0xfffa05, SIZE_BYTE, MFP_DataDirection_ReadByte, MFP_DataDirection_WriteByte },
119: { 0xfffa07, SIZE_BYTE, MFP_EnableA_ReadByte, MFP_EnableA_WriteByte },
120: { 0xfffa09, SIZE_BYTE, MFP_EnableB_ReadByte, MFP_EnableB_WriteByte },
121: { 0xfffa0b, SIZE_BYTE, MFP_PendingA_ReadByte, MFP_PendingA_WriteByte },
122: { 0xfffa0d, SIZE_BYTE, MFP_PendingB_ReadByte, MFP_PendingB_WriteByte },
123: { 0xfffa0f, SIZE_BYTE, MFP_InServiceA_ReadByte, MFP_InServiceA_WriteByte },
124: { 0xfffa11, SIZE_BYTE, MFP_InServiceB_ReadByte, MFP_InServiceB_WriteByte },
125: { 0xfffa13, SIZE_BYTE, MFP_MaskA_ReadByte, MFP_MaskA_WriteByte },
126: { 0xfffa15, SIZE_BYTE, MFP_MaskB_ReadByte, MFP_MaskB_WriteByte },
127: { 0xfffa17, SIZE_BYTE, MFP_VectorReg_ReadByte, MFP_VectorReg_WriteByte },
128: { 0xfffa19, SIZE_BYTE, MFP_TimerACtrl_ReadByte, MFP_TimerACtrl_WriteByte },
129: { 0xfffa1b, SIZE_BYTE, MFP_TimerBCtrl_ReadByte, MFP_TimerBCtrl_WriteByte },
130: { 0xfffa1d, SIZE_BYTE, MFP_TimerCDCtrl_ReadByte, MFP_TimerCDCtrl_WriteByte },
131: { 0xfffa1f, SIZE_BYTE, MFP_TimerAData_ReadByte, MFP_TimerAData_WriteByte },
132: { 0xfffa21, SIZE_BYTE, MFP_TimerBData_ReadByte, MFP_TimerBData_WriteByte },
133: { 0xfffa23, SIZE_BYTE, MFP_TimerCData_ReadByte, MFP_TimerCData_WriteByte },
134: { 0xfffa25, SIZE_BYTE, MFP_TimerDData_ReadByte, MFP_TimerDData_WriteByte },
135:
136: { 0xfffa27, SIZE_BYTE, RS232_SCR_ReadByte, RS232_SCR_WriteByte }, /* Sync character register */
137: { 0xfffa29, SIZE_BYTE, RS232_UCR_ReadByte, RS232_UCR_WriteByte }, /* USART control register */
138: { 0xfffa2b, SIZE_BYTE, RS232_RSR_ReadByte, RS232_RSR_WriteByte }, /* Receiver status register */
139: { 0xfffa2d, SIZE_BYTE, RS232_TSR_ReadByte, RS232_TSR_WriteByte }, /* Transmitter status register */
140: { 0xfffa2f, SIZE_BYTE, RS232_UDR_ReadByte, RS232_UDR_WriteByte }, /* USART data register */
141:
142: { 0xfffa31, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
143: { 0xfffa33, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
144: { 0xfffa35, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
145: { 0xfffa37, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
146: { 0xfffa39, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
147: { 0xfffa3b, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
148: { 0xfffa3d, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
149: { 0xfffa3f, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
150:
1.1.1.6 root 151: { 0xfffc00, SIZE_BYTE, ACIA_IKBD_Read_SR, ACIA_IKBD_Write_CR },
1.1 root 152: { 0xfffc01, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
1.1.1.6 root 153: { 0xfffc02, SIZE_BYTE, ACIA_IKBD_Read_RDR, ACIA_IKBD_Write_TDR },
1.1 root 154: { 0xfffc03, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
155: { 0xfffc04, SIZE_BYTE, Midi_Control_ReadByte, Midi_Control_WriteByte },
156: { 0xfffc05, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
157: { 0xfffc06, SIZE_BYTE, Midi_Data_ReadByte, Midi_Data_WriteByte },
158: { 0xfffc07, 26, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus errors here */
159:
160: { 0xfffc21, SIZE_BYTE, Rtc_SecondsUnits_ReadByte, IoMem_WriteWithoutInterception },
161: { 0xfffc22, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
162: { 0xfffc23, SIZE_BYTE, Rtc_SecondsTens_ReadByte, IoMem_WriteWithoutInterception },
163: { 0xfffc24, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
164: { 0xfffc25, SIZE_BYTE, Rtc_MinutesUnits_ReadByte, Rtc_MinutesUnits_WriteByte },
165: { 0xfffc26, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
166: { 0xfffc27, SIZE_BYTE, Rtc_MinutesTens_ReadByte, Rtc_MinutesTens_WriteByte },
167: { 0xfffc28, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
168: { 0xfffc29, SIZE_BYTE, Rtc_HoursUnits_ReadByte, IoMem_WriteWithoutInterception },
169: { 0xfffc2a, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
170: { 0xfffc2b, SIZE_BYTE, Rtc_HoursTens_ReadByte, IoMem_WriteWithoutInterception },
171: { 0xfffc2c, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
172: { 0xfffc2d, SIZE_BYTE, Rtc_Weekday_ReadByte, IoMem_WriteWithoutInterception },
173: { 0xfffc2e, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
174: { 0xfffc2f, SIZE_BYTE, Rtc_DayUnits_ReadByte, IoMem_WriteWithoutInterception },
175: { 0xfffc30, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
176: { 0xfffc31, SIZE_BYTE, Rtc_DayTens_ReadByte, IoMem_WriteWithoutInterception },
177: { 0xfffc32, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
178: { 0xfffc33, SIZE_BYTE, Rtc_MonthUnits_ReadByte, IoMem_WriteWithoutInterception },
179: { 0xfffc34, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
180: { 0xfffc35, SIZE_BYTE, Rtc_MonthTens_ReadByte, IoMem_WriteWithoutInterception },
181: { 0xfffc36, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
182: { 0xfffc37, SIZE_BYTE, Rtc_YearUnits_ReadByte, IoMem_WriteWithoutInterception },
183: { 0xfffc38, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
184: { 0xfffc39, SIZE_BYTE, Rtc_YearTens_ReadByte, IoMem_WriteWithoutInterception },
185: { 0xfffc3a, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
186: { 0xfffc3b, SIZE_BYTE, Rtc_ClockMod_ReadByte, Rtc_ClockMod_WriteByte },
187: { 0xfffc3c, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
188: { 0xfffc3d, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception }, /* Clock test */
189: { 0xfffc3e, SIZE_BYTE, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus error here */
190: { 0xfffc3f, SIZE_BYTE, IoMem_ReadWithoutInterception, IoMem_WriteWithoutInterception }, /* Clock reset */
191: { 0xfffc40, 448, IoMem_VoidRead, IoMem_VoidWrite }, /* No bus errors here */
192:
193: { 0, 0, NULL, NULL }
194: };
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