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1.1 root 1: /*
1.1.1.6 root 2: Hatari - m68000.c
1.1 root 3:
1.1.1.6 root 4: This file is distributed under the GNU Public License, version 2 or at
5: your option any later version. Read the file gpl.txt for details.
6:
7: These routines originally (in WinSTon) handled exceptions as well as some
1.1.1.5 root 8: few OpCode's such as Line-F and Line-A. In Hatari it has mainly become a
9: wrapper between the WinSTon sources and the UAE CPU code.
1.1 root 10: */
1.1.1.12 root 11:
12: /* 2007/03/xx [NP] Possibility to add several wait states for the same instruction in */
13: /* M68000_WaitState (e.g. clr.b $fa1b.w in Decade Demo Menu). */
14: /* 2007/04/14 [NP] Add support for instruction pairing in M68000_AddCycles, using OpcodeFamily and */
15: /* LastOpcodeFamily (No Cooper Loader, Oh Crickey ... Hidden Screen). */
16: /* 2007/04/24 [NP] Add pairing for BCLR/Bcc. */
17: /* 2007/09/29 [NP] Use the new int.c and INT_CONVERT_TO_INTERNAL. */
18: /* 2007/11/26 [NP] We set BusErrorPC in m68k_run_1 instead of M68000_BusError, else the BusErrorPC */
19: /* will not point to the opcode that generated the bus error. */
20: /* In M68000_BusError, if we have 'move.l $0,$24', we need to generate a bus error */
21: /* for the read, not for the write that should occur after (TransBeauce 2 Demo). */
22: /* 2008/01/07 [NP] Function 'M68000_InitPairing' and 'PairingArray' as a lookup table for fast */
23: /* determination of valid pairing combinations (replace lots of 'if' tests in */
24: /* m68000.h). */
25: /* 2008/01/25 [NP] Add pairing for LSR/MOVE (and all other bit shifting instr) (Anomaly Demo Intro)*/
26: /* 2008/02/02 [NP] Add pairing for CMP/Bcc (Level 16 Fullscreen (1988)). */
27: /* 2008/02/08 [NP] Add pairing for LSL/LEA (and all other bit shifting instr) (TVI 2 - The Year */
28: /* After Demo). */
29: /* 2008/02/11 [NP] Add pairing for MULS/MOVEA (Delirious Demo IV Loader). */
30: /* 2008/01/25 [NP] Add pairing for LSR/MOVEA (and all other bit shifting instr) (Decade Demo Reset)*/
1.1.1.13 root 31: /* 2008/02/16 [NP] Add pairing for MULS/DIVS (fixes e605 demo part 3). */
1.1.1.12 root 32: /* 2008/03/08 [NP] In M68000_Exception, we need to know if the exception was triggered by an MFP */
33: /* interrupt or by a video interrupt. In the case MFP vector base was changed in */
34: /* fffa17 to an other value than the default $40, testing exceptionNr is not enough*/
35: /* to correctly process the exception. For example, if vector base is set to $10 */
36: /* then MFP Timer A will call vector stored at address $74, which would be wrongly */
37: /* interpreted as a level 5 int (which doesn't exist on Atari and will cause an */
1.1.1.13 root 38: /* assert to fail in intlevel()). We use InterruptSource to correctly recognize the*/
1.1.1.12 root 39: /* MFP interrupts (fix 'Toki' end part fullscreen which sets vector base to $10). */
1.1.1.13 root 40: /* 2008/04/14 [NP] Add pairing for BTST/Bcc (eg btst #7,d0 + bne.s label (with branch taken)). */
41: /* 2008/04/15 [NP] As tested on a real STF : */
42: /* - MUL/DIV can pair (but DIV/MUL can't) */
43: /* (eg mulu d0,d0 + divs d1,d1 with d0=0 and d1=1) */
44: /* - MUL/MOVE can pair, but not DIV/MOVE */
45: /* - EXG/MOVE can pair (eg exg d3,d4 + move.l 0(a3,d1.w),a4) */
46: /* - MOVE/DBcc can't pair */
47: /* 2008/04/16 [NP] Functions 'M68000_InitPairing_BitShift' to ease code maintenance. */
48: /* Tested on STF : add pairing between bit shift instr and ADD/SUB/OR/AND/EOR/NOT */
49: /* CLR/NEG (certainly some more possible, haven't tested everything) */
50: /* (fixes lsr.w #4,d4 + add.b $f0(a4,d4),d7 used in Zoolook part of ULM New Year). */
51: /* 2008/07/08 [NP] Add pairing between bit shift instr and ADDX/SUBX/ABCD/SBCD (fixes lsl.l #1,d0 */
52: /* + abcd d1,d1 used in Dragonnels - Rainbow Wall). */
53: /* 2008/10/05 [NP] Pass the 'ExceptionSource' parameter to Exception() in uae-cpu/newcpu.c */
1.1.1.12 root 54:
55:
1.1.1.14 root 56: const char M68000_fileid[] = "Hatari m68000.c : " __DATE__ " " __TIME__;
1.1 root 57:
58: #include "main.h"
1.1.1.12 root 59: #include "configuration.h"
1.1 root 60: #include "gemdos.h"
1.1.1.6 root 61: #include "hatari-glue.h"
1.1 root 62: #include "int.h"
63: #include "m68000.h"
64: #include "memorySnapShot.h"
65: #include "mfp.h"
1.1.1.12 root 66: #include "options.h"
67: #include "savestate.h"
1.1 root 68: #include "stMemory.h"
69: #include "tos.h"
70:
71:
1.1.1.12 root 72: Uint32 BusErrorAddress; /* Stores the offending address for bus-/address errors */
73: Uint32 BusErrorPC; /* Value of the PC when bus error occurs */
1.1.1.13 root 74: bool bBusErrorReadWrite; /* 0 for write error, 1 for read error */
1.1.1.12 root 75: int nCpuFreqShift; /* Used to emulate higher CPU frequencies: 0=8MHz, 1=16MHz, 2=32Mhz */
76: int nWaitStateCycles; /* Used to emulate the wait state cycles of certain IO registers */
1.1.1.14 root 77: int BusMode = BUS_MODE_CPU; /* Used to tell which part is owning the bus (cpu, blitter, ...) */
1.1.1.12 root 78:
79: int LastOpcodeFamily = -1; /* see the enum in readcpu.h i_XXX */
80: int LastInstrCycles = -1; /* number of cycles for previous instr. (not rounded to 4) */
81: int Pairing = 0; /* set to 1 if the latest 2 intr paired */
82: char PairingArray[ MAX_OPCODE_FAMILY ][ MAX_OPCODE_FAMILY ];
83:
84:
85: /* to convert the enum from OpcodeFamily to a readable value for pairing's debug */
86: const char *OpcodeName[] = { "ILLG",
87: "OR","AND","EOR","ORSR","ANDSR","EORSR",
88: "SUB","SUBA","SUBX","SBCD",
89: "ADD","ADDA","ADDX","ABCD",
90: "NEG","NEGX","NBCD","CLR","NOT","TST",
91: "BTST","BCHG","BCLR","BSET",
92: "CMP","CMPM","CMPA",
93: "MVPRM","MVPMR","MOVE","MOVEA","MVSR2","MV2SR",
94: "SWAP","EXG","EXT","MVMEL","MVMLE",
95: "TRAP","MVR2USP","MVUSP2R","RESET","NOP","STOP","RTE","RTD",
96: "LINK","UNLK",
97: "RTS","TRAPV","RTR",
98: "JSR","JMP","BSR","Bcc",
99: "LEA","PEA","DBcc","Scc",
100: "DIVU","DIVS","MULU","MULS",
101: "ASR","ASL","LSR","LSL","ROL","ROR","ROXL","ROXR",
102: "ASRW","ASLW","LSRW","LSLW","ROLW","RORW","ROXLW","ROXRW",
103: "CHK","CHK2",
104: "MOVEC2","MOVE2C","CAS","CAS2","DIVL","MULL",
105: "BFTST","BFEXTU","BFCHG","BFEXTS","BFCLR","BFFFO","BFSET","BFINS",
106: "PACK","UNPK","TAS","BKPT","CALLM","RTM","TRAPcc","MOVES",
107: "FPP","FDBcc","FScc","FTRAPcc","FBcc","FSAVE","FRESTORE",
108: "CINVL","CINVP","CINVA","CPUSHL","CPUSHP","CPUSHA","MOVE16",
109: "MMUOP"
110: };
1.1.1.8 root 111:
1.1.1.12 root 112:
113: /*-----------------------------------------------------------------------*/
114: /**
1.1.1.13 root 115: * Add pairing between all the bit shifting instructions and a given Opcode
116: */
117:
118: static void M68000_InitPairing_BitShift ( int OpCode )
119: {
120: PairingArray[ i_ASR ][ OpCode ] = 1;
121: PairingArray[ i_ASL ][ OpCode ] = 1;
122: PairingArray[ i_LSR ][ OpCode ] = 1;
123: PairingArray[ i_LSL ][ OpCode ] = 1;
124: PairingArray[ i_ROL ][ OpCode ] = 1;
125: PairingArray[ i_ROR ][ OpCode ] = 1;
126: PairingArray[ i_ROXR ][ OpCode ] = 1;
127: PairingArray[ i_ROXL ][ OpCode ] = 1;
128: }
129:
130:
131: /*-----------------------------------------------------------------------*/
132: /**
1.1.1.12 root 133: * Init the pairing matrix
134: * Two instructions can pair if PairingArray[ LastOpcodeFamily ][ OpcodeFamily ] == 1
135: */
136: void M68000_InitPairing(void)
137: {
138: /* First, clear the matrix (pairing is false) */
139: memset(PairingArray , 0 , MAX_OPCODE_FAMILY * MAX_OPCODE_FAMILY);
140:
141: /* Set all valid pairing combinations to 1 */
142: PairingArray[ i_EXG ][ i_DBcc ] = 1;
1.1.1.13 root 143: PairingArray[ i_EXG ][ i_MOVE ] = 1;
144: PairingArray[ i_EXG ][ i_MOVEA] = 1;
145:
1.1.1.12 root 146: PairingArray[ i_CMPA ][ i_Bcc ] = 1;
147: PairingArray[ i_CMP ][ i_Bcc ] = 1;
1.1.1.13 root 148:
149: M68000_InitPairing_BitShift ( i_DBcc );
150: M68000_InitPairing_BitShift ( i_MOVE );
151: M68000_InitPairing_BitShift ( i_MOVEA );
152: M68000_InitPairing_BitShift ( i_LEA );
153:
1.1.1.12 root 154: PairingArray[ i_MULU ][ i_MOVEA] = 1;
155: PairingArray[ i_MULS ][ i_MOVEA] = 1;
156: PairingArray[ i_MULU ][ i_MOVE ] = 1;
157: PairingArray[ i_MULS ][ i_MOVE ] = 1;
1.1.1.13 root 158:
159: PairingArray[ i_MULU ][ i_DIVU ] = 1;
160: PairingArray[ i_MULU ][ i_DIVS ] = 1;
161: PairingArray[ i_MULS ][ i_DIVU ] = 1;
162: PairingArray[ i_MULS ][ i_DIVS ] = 1;
163:
164: PairingArray[ i_BTST ][ i_Bcc ] = 1;
165:
166: M68000_InitPairing_BitShift ( i_ADD );
167: M68000_InitPairing_BitShift ( i_SUB );
168: M68000_InitPairing_BitShift ( i_OR );
169: M68000_InitPairing_BitShift ( i_AND );
170: M68000_InitPairing_BitShift ( i_EOR );
171: M68000_InitPairing_BitShift ( i_NOT );
172: M68000_InitPairing_BitShift ( i_CLR );
173: M68000_InitPairing_BitShift ( i_NEG );
174: M68000_InitPairing_BitShift ( i_ADDX );
175: M68000_InitPairing_BitShift ( i_SUBX );
176: M68000_InitPairing_BitShift ( i_ABCD );
177: M68000_InitPairing_BitShift ( i_SBCD );
1.1.1.12 root 178: }
1.1 root 179:
180:
1.1.1.3 root 181: /*-----------------------------------------------------------------------*/
1.1.1.12 root 182: /**
183: * Reset CPU 68000 variables
184: */
1.1.1.13 root 185: void M68000_Reset(bool bCold)
1.1 root 186: {
1.1.1.12 root 187: int i;
188:
189: /* Clear registers */
190: if (bCold)
191: {
192: for (i=0; i<(16+1); i++)
193: Regs[i] = 0;
194: }
195:
196: /* Now directly reset the UAE CPU core: */
197: m68k_reset();
198:
199: /* Init the pairing matrix */
200: M68000_InitPairing();
1.1.1.14 root 201:
202: BusMode = BUS_MODE_CPU;
1.1.1.12 root 203: }
204:
205:
206: /*-----------------------------------------------------------------------*/
207: /**
208: * Reset and start 680x0 emulation
209: */
210: void M68000_Start(void)
211: {
212: m68k_reset();
1.1 root 213:
1.1.1.12 root 214: /* Load initial memory snapshot */
215: if (bLoadMemorySave)
216: {
1.1.1.15! root 217: MemorySnapShot_Restore(ConfigureParams.Memory.szMemoryCaptureFileName, false);
1.1.1.12 root 218: }
219: else if (bLoadAutoSave)
220: {
1.1.1.15! root 221: MemorySnapShot_Restore(ConfigureParams.Memory.szAutoSaveFileName, false);
1.1.1.12 root 222: }
1.1.1.7 root 223:
1.1.1.15! root 224: m68k_go(true);
1.1 root 225: }
226:
1.1.1.3 root 227:
228: /*-----------------------------------------------------------------------*/
1.1.1.12 root 229: /**
230: * Check wether the CPU mode has been changed.
231: */
232: void M68000_CheckCpuLevel(void)
233: {
234: changed_prefs.cpu_level = ConfigureParams.System.nCpuLevel;
235: changed_prefs.cpu_compatible = ConfigureParams.System.bCompatibleCpu;
236: #ifndef UAE_NEWCPU_H
237: changed_prefs.cpu_cycle_exact = 0; // TODO
238: #endif
239: if (table68k)
240: check_prefs_changed_cpu();
241: }
242:
243:
244: /*-----------------------------------------------------------------------*/
245: /**
246: * Save/Restore snapshot of CPU variables ('MemorySnapShot_Store' handles type)
247: */
1.1.1.13 root 248: void M68000_MemorySnapShot_Capture(bool bSave)
1.1 root 249: {
1.1.1.12 root 250: Uint32 savepc;
1.1 root 251:
1.1.1.12 root 252: /* Save/Restore details */
253: MemorySnapShot_Store(Regs,sizeof(Regs));
254: MemorySnapShot_Store(&STRamEnd,sizeof(STRamEnd));
255:
256: /* For the UAE CPU core: */
257: MemorySnapShot_Store(&currprefs.address_space_24,
258: sizeof(currprefs.address_space_24));
259: MemorySnapShot_Store(®s.regs[0], sizeof(regs.regs)); /* D0-D7 A0-A6 */
260:
261: if (bSave)
262: {
263: savepc = M68000_GetPC();
264: MemorySnapShot_Store(&savepc, sizeof(savepc)); /* PC */
265: }
266: else
267: {
268: MemorySnapShot_Store(&savepc, sizeof(savepc)); /* PC */
269: regs.pc = savepc;
270: #ifdef UAE_NEWCPU_H
271: regs.prefetch_pc = regs.pc + 128;
272: #endif
273: }
1.1.1.8 root 274:
1.1.1.12 root 275: #ifdef UAE_NEWCPU_H
276: MemorySnapShot_Store(®s.prefetch, sizeof(regs.prefetch)); /* prefetch */
277: #else
278: uae_u32 prefetch_dummy;
279: MemorySnapShot_Store(&prefetch_dummy, sizeof(prefetch_dummy));
280: #endif
281:
282: if (bSave)
283: {
284: #ifdef UAE_NEWCPU_H
285: MakeSR();
286: #else
287: MakeSR(®s);
288: #endif
289: if (regs.s)
290: {
291: MemorySnapShot_Store(®s.usp, sizeof(regs.usp)); /* USP */
292: MemorySnapShot_Store(®s.regs[15], sizeof(regs.regs[15])); /* ISP */
293: }
294: else
295: {
296: MemorySnapShot_Store(®s.regs[15], sizeof(regs.regs[15])); /* USP */
297: MemorySnapShot_Store(®s.isp, sizeof(regs.isp)); /* ISP */
298: }
299: MemorySnapShot_Store(®s.sr, sizeof(regs.sr)); /* SR/CCR */
300: }
301: else
302: {
303: MemorySnapShot_Store(®s.usp, sizeof(regs.usp));
304: MemorySnapShot_Store(®s.isp, sizeof(regs.isp));
305: MemorySnapShot_Store(®s.sr, sizeof(regs.sr));
306: }
307: MemorySnapShot_Store(®s.stopped, sizeof(regs.stopped));
308: MemorySnapShot_Store(®s.dfc, sizeof(regs.dfc)); /* DFC */
309: MemorySnapShot_Store(®s.sfc, sizeof(regs.sfc)); /* SFC */
310: MemorySnapShot_Store(®s.vbr, sizeof(regs.vbr)); /* VBR */
311: MemorySnapShot_Store(&caar, sizeof(caar)); /* CAAR */
312: MemorySnapShot_Store(&cacr, sizeof(cacr)); /* CACR */
313: MemorySnapShot_Store(®s.msp, sizeof(regs.msp)); /* MSP */
314:
315: if (!bSave)
316: {
317: M68000_SetPC(regs.pc);
318: /* MakeFromSR() must not swap stack pointer */
319: regs.s = (regs.sr >> 13) & 1;
320: #ifdef UAE_NEWCPU_H
321: MakeFromSR();
322: /* set stack pointer */
323: if (regs.s)
324: m68k_areg(regs, 7) = regs.isp;
325: else
326: m68k_areg(regs, 7) = regs.usp;
327: #else
328: MakeFromSR(®s);
329: /* set stack pointer */
330: if (regs.s)
331: m68k_areg(®s, 7) = regs.isp;
332: else
333: m68k_areg(®s, 7) = regs.usp;
334: #endif
335: }
336:
337: if (bSave)
338: save_fpu();
339: else
340: restore_fpu();
1.1 root 341: }
342:
343:
1.1.1.3 root 344: /*-----------------------------------------------------------------------*/
1.1.1.12 root 345: /**
346: * BUSERROR - Access outside valid memory range.
347: * Use bReadWrite = 0 for write errors and bReadWrite = 1 for read errors!
348: */
1.1.1.13 root 349: void M68000_BusError(Uint32 addr, bool bReadWrite)
1.1 root 350: {
1.1.1.12 root 351: /* FIXME: In prefetch mode, m68k_getpc() seems already to point to the next instruction */
352: // BusErrorPC = M68000_GetPC(); /* [NP] We set BusErrorPC in m68k_run_1 */
1.1.1.7 root 353:
1.1.1.15! root 354: /* Do not print message when TOS is testing for available HW or
! 355: * when a program just checks for the floating point co-processor. */
! 356: if ((BusErrorPC < TosAddress || BusErrorPC > TosAddress + TosSize)
! 357: && addr != 0xfffa42)
1.1.1.12 root 358: {
1.1.1.15! root 359: /* Print bus error message */
! 360: fprintf(stderr, "M68000 Bus Error at address $%x.\n", addr);
1.1.1.12 root 361: }
362:
363: if ((regs.spcflags & SPCFLAG_BUSERROR) == 0) /* [NP] Check that the opcode has not already generated a read bus error */
364: {
365: BusErrorAddress = addr; /* Store for exception frame */
366: bBusErrorReadWrite = bReadWrite;
367: M68000_SetSpecial(SPCFLAG_BUSERROR); /* The exception will be done in newcpu.c */
368: }
1.1 root 369: }
370:
1.1.1.3 root 371:
372: /*-----------------------------------------------------------------------*/
1.1.1.12 root 373: /**
374: * Exception handler
375: */
1.1.1.13 root 376: void M68000_Exception(Uint32 ExceptionVector , int ExceptionSource)
1.1.1.12 root 377: {
378: int exceptionNr = ExceptionVector/4;
379:
1.1.1.13 root 380: if ( ( ExceptionSource == M68000_EXCEPTION_SRC_INT_VIDEO )
1.1.1.12 root 381: && (exceptionNr>24 && exceptionNr<32) ) /* 68k autovector interrupt? */
382: {
383: /* Handle autovector interrupts the UAE's way
384: * (see intlev() and do_specialties() in UAE CPU core) */
385: /* In our case, this part is only called for HBL and VBL interrupts */
386: int intnr = exceptionNr - 24;
387: pendingInterrupts |= (1 << intnr);
388: M68000_SetSpecial(SPCFLAG_INT);
389: }
1.1.1.13 root 390:
391: else /* MFP or direct CPU exceptions */
1.1.1.12 root 392: {
393: Uint16 SR;
394:
395: /* Was the CPU stopped, i.e. by a STOP instruction? */
396: if (regs.spcflags & SPCFLAG_STOP)
397: {
398: regs.stopped = 0;
399: M68000_UnsetSpecial(SPCFLAG_STOP); /* All is go,go,go! */
400: }
401:
402: /* 68k exceptions are handled by Exception() of the UAE CPU core */
403: #ifdef UAE_NEWCPU_H
1.1.1.13 root 404: Exception(exceptionNr, m68k_getpc(), ExceptionSource);
1.1.1.12 root 405: #else
406: Exception(exceptionNr, ®s, m68k_getpc(®s));
407: #endif
408:
409: SR = M68000_GetSR();
410:
411: /* Set Status Register so interrupt can ONLY be stopped by another interrupt
412: * of higher priority! */
1.1.1.6 root 413: #if 0 /* VBL and HBL are handled in the UAE CPU core (see above). */
1.1.1.12 root 414: if (ExceptionVector == EXCEPTION_VBLANK)
415: SR = (SR&SR_CLEAR_IPL)|0x0400; /* VBL, level 4 */
416: else if (ExceptionVector == EXCEPTION_HBLANK)
417: SR = (SR&SR_CLEAR_IPL)|0x0200; /* HBL, level 2 */
418: else
419: #endif
420: {
421: Uint32 MFPBaseVector = (unsigned int)(MFP_VR&0xf0)<<2;
422: if ( (ExceptionVector>=MFPBaseVector) && (ExceptionVector<=(MFPBaseVector+0x3c)) )
423: SR = (SR&SR_CLEAR_IPL)|0x0600; /* MFP, level 6 */
424: }
425:
426: M68000_SetSR(SR);
427: }
1.1 root 428: }
429:
1.1.1.8 root 430:
431: /*-----------------------------------------------------------------------*/
1.1.1.12 root 432: /**
433: * There seem to be wait states when a program accesses certain hardware
434: * registers on the ST. Use this function to simulate these wait states.
435: * [NP] with some instructions like CLR, we have a read then a write at the
436: * same location, so we may have 2 wait states (read and write) to add
437: * (nWaitStateCycles should be reset to 0 after the cycles were added).
438: */
1.1.1.11 root 439: void M68000_WaitState(int nCycles)
1.1.1.8 root 440: {
1.1.1.12 root 441: M68000_SetSpecial(SPCFLAG_EXTRA_CYCLES);
1.1.1.11 root 442:
1.1.1.12 root 443: nWaitStateCycles += nCycles; /* add all the wait states for this instruction */
1.1.1.8 root 444: }
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