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1.1 root 1: /*
1.1.1.6 root 2: Hatari - m68000.c
1.1 root 3:
1.1.1.6 root 4: This file is distributed under the GNU Public License, version 2 or at
5: your option any later version. Read the file gpl.txt for details.
6:
7: These routines originally (in WinSTon) handled exceptions as well as some
1.1.1.5 root 8: few OpCode's such as Line-F and Line-A. In Hatari it has mainly become a
9: wrapper between the WinSTon sources and the UAE CPU code.
1.1 root 10: */
1.1.1.12 root 11:
12: /* 2007/03/xx [NP] Possibility to add several wait states for the same instruction in */
13: /* M68000_WaitState (e.g. clr.b $fa1b.w in Decade Demo Menu). */
14: /* 2007/04/14 [NP] Add support for instruction pairing in M68000_AddCycles, using OpcodeFamily and */
15: /* LastOpcodeFamily (No Cooper Loader, Oh Crickey ... Hidden Screen). */
16: /* 2007/04/24 [NP] Add pairing for BCLR/Bcc. */
17: /* 2007/09/29 [NP] Use the new int.c and INT_CONVERT_TO_INTERNAL. */
18: /* 2007/11/26 [NP] We set BusErrorPC in m68k_run_1 instead of M68000_BusError, else the BusErrorPC */
19: /* will not point to the opcode that generated the bus error. */
20: /* In M68000_BusError, if we have 'move.l $0,$24', we need to generate a bus error */
21: /* for the read, not for the write that should occur after (TransBeauce 2 Demo). */
22: /* 2008/01/07 [NP] Function 'M68000_InitPairing' and 'PairingArray' as a lookup table for fast */
23: /* determination of valid pairing combinations (replace lots of 'if' tests in */
24: /* m68000.h). */
25: /* 2008/01/25 [NP] Add pairing for LSR/MOVE (and all other bit shifting instr) (Anomaly Demo Intro)*/
26: /* 2008/02/02 [NP] Add pairing for CMP/Bcc (Level 16 Fullscreen (1988)). */
27: /* 2008/02/08 [NP] Add pairing for LSL/LEA (and all other bit shifting instr) (TVI 2 - The Year */
28: /* After Demo). */
29: /* 2008/02/11 [NP] Add pairing for MULS/MOVEA (Delirious Demo IV Loader). */
30: /* 2008/01/25 [NP] Add pairing for LSR/MOVEA (and all other bit shifting instr) (Decade Demo Reset)*/
1.1.1.13 root 31: /* 2008/02/16 [NP] Add pairing for MULS/DIVS (fixes e605 demo part 3). */
1.1.1.12 root 32: /* 2008/03/08 [NP] In M68000_Exception, we need to know if the exception was triggered by an MFP */
33: /* interrupt or by a video interrupt. In the case MFP vector base was changed in */
34: /* fffa17 to an other value than the default $40, testing exceptionNr is not enough*/
35: /* to correctly process the exception. For example, if vector base is set to $10 */
36: /* then MFP Timer A will call vector stored at address $74, which would be wrongly */
37: /* interpreted as a level 5 int (which doesn't exist on Atari and will cause an */
1.1.1.13 root 38: /* assert to fail in intlevel()). We use InterruptSource to correctly recognize the*/
1.1.1.12 root 39: /* MFP interrupts (fix 'Toki' end part fullscreen which sets vector base to $10). */
1.1.1.13 root 40: /* 2008/04/14 [NP] Add pairing for BTST/Bcc (eg btst #7,d0 + bne.s label (with branch taken)). */
41: /* 2008/04/15 [NP] As tested on a real STF : */
42: /* - MUL/DIV can pair (but DIV/MUL can't) */
43: /* (eg mulu d0,d0 + divs d1,d1 with d0=0 and d1=1) */
44: /* - MUL/MOVE can pair, but not DIV/MOVE */
45: /* - EXG/MOVE can pair (eg exg d3,d4 + move.l 0(a3,d1.w),a4) */
46: /* - MOVE/DBcc can't pair */
47: /* 2008/04/16 [NP] Functions 'M68000_InitPairing_BitShift' to ease code maintenance. */
48: /* Tested on STF : add pairing between bit shift instr and ADD/SUB/OR/AND/EOR/NOT */
49: /* CLR/NEG (certainly some more possible, haven't tested everything) */
50: /* (fixes lsr.w #4,d4 + add.b $f0(a4,d4),d7 used in Zoolook part of ULM New Year). */
51: /* 2008/07/08 [NP] Add pairing between bit shift instr and ADDX/SUBX/ABCD/SBCD (fixes lsl.l #1,d0 */
52: /* + abcd d1,d1 used in Dragonnels - Rainbow Wall). */
53: /* 2008/10/05 [NP] Pass the 'ExceptionSource' parameter to Exception() in uae-cpu/newcpu.c */
1.1.1.16! root 54: /* 2010/05/07 [NP] Add pairing for ADD/MOVE ; such pairing should only be possible when combined */
! 55: /* with d8(an,ix) address mode (eg: add.l (a5,d1.w),d0 + move.b 7(a5,d1.w),d5) */
! 56: /* (fixes Sommarhack 2010 Invitation by DHS). */
1.1.1.12 root 57:
58:
1.1.1.14 root 59: const char M68000_fileid[] = "Hatari m68000.c : " __DATE__ " " __TIME__;
1.1 root 60:
61: #include "main.h"
1.1.1.12 root 62: #include "configuration.h"
1.1 root 63: #include "gemdos.h"
1.1.1.6 root 64: #include "hatari-glue.h"
1.1.1.16! root 65: #include "cycInt.h"
1.1 root 66: #include "m68000.h"
67: #include "memorySnapShot.h"
68: #include "mfp.h"
1.1.1.12 root 69: #include "options.h"
70: #include "savestate.h"
1.1 root 71: #include "stMemory.h"
72: #include "tos.h"
73:
74:
1.1.1.12 root 75: Uint32 BusErrorAddress; /* Stores the offending address for bus-/address errors */
76: Uint32 BusErrorPC; /* Value of the PC when bus error occurs */
1.1.1.13 root 77: bool bBusErrorReadWrite; /* 0 for write error, 1 for read error */
1.1.1.12 root 78: int nCpuFreqShift; /* Used to emulate higher CPU frequencies: 0=8MHz, 1=16MHz, 2=32Mhz */
79: int nWaitStateCycles; /* Used to emulate the wait state cycles of certain IO registers */
1.1.1.14 root 80: int BusMode = BUS_MODE_CPU; /* Used to tell which part is owning the bus (cpu, blitter, ...) */
1.1.1.12 root 81:
1.1.1.16! root 82: int LastOpcodeFamily = i_NOP; /* see the enum in readcpu.h i_XXX */
! 83: int LastInstrCycles = 0; /* number of cycles for previous instr. (not rounded to 4) */
! 84: int Pairing = 0; /* set to 1 if the latest 2 intr paired */
1.1.1.12 root 85: char PairingArray[ MAX_OPCODE_FAMILY ][ MAX_OPCODE_FAMILY ];
86:
87:
88: /* to convert the enum from OpcodeFamily to a readable value for pairing's debug */
89: const char *OpcodeName[] = { "ILLG",
90: "OR","AND","EOR","ORSR","ANDSR","EORSR",
91: "SUB","SUBA","SUBX","SBCD",
92: "ADD","ADDA","ADDX","ABCD",
93: "NEG","NEGX","NBCD","CLR","NOT","TST",
94: "BTST","BCHG","BCLR","BSET",
95: "CMP","CMPM","CMPA",
96: "MVPRM","MVPMR","MOVE","MOVEA","MVSR2","MV2SR",
97: "SWAP","EXG","EXT","MVMEL","MVMLE",
98: "TRAP","MVR2USP","MVUSP2R","RESET","NOP","STOP","RTE","RTD",
99: "LINK","UNLK",
100: "RTS","TRAPV","RTR",
101: "JSR","JMP","BSR","Bcc",
102: "LEA","PEA","DBcc","Scc",
103: "DIVU","DIVS","MULU","MULS",
104: "ASR","ASL","LSR","LSL","ROL","ROR","ROXL","ROXR",
105: "ASRW","ASLW","LSRW","LSLW","ROLW","RORW","ROXLW","ROXRW",
106: "CHK","CHK2",
107: "MOVEC2","MOVE2C","CAS","CAS2","DIVL","MULL",
108: "BFTST","BFEXTU","BFCHG","BFEXTS","BFCLR","BFFFO","BFSET","BFINS",
109: "PACK","UNPK","TAS","BKPT","CALLM","RTM","TRAPcc","MOVES",
110: "FPP","FDBcc","FScc","FTRAPcc","FBcc","FSAVE","FRESTORE",
111: "CINVL","CINVP","CINVA","CPUSHL","CPUSHP","CPUSHA","MOVE16",
112: "MMUOP"
113: };
1.1.1.8 root 114:
1.1.1.12 root 115:
116: /*-----------------------------------------------------------------------*/
117: /**
1.1.1.13 root 118: * Add pairing between all the bit shifting instructions and a given Opcode
119: */
120:
121: static void M68000_InitPairing_BitShift ( int OpCode )
122: {
123: PairingArray[ i_ASR ][ OpCode ] = 1;
124: PairingArray[ i_ASL ][ OpCode ] = 1;
125: PairingArray[ i_LSR ][ OpCode ] = 1;
126: PairingArray[ i_LSL ][ OpCode ] = 1;
127: PairingArray[ i_ROL ][ OpCode ] = 1;
128: PairingArray[ i_ROR ][ OpCode ] = 1;
129: PairingArray[ i_ROXR ][ OpCode ] = 1;
130: PairingArray[ i_ROXL ][ OpCode ] = 1;
131: }
132:
133:
134: /**
1.1.1.12 root 135: * Init the pairing matrix
136: * Two instructions can pair if PairingArray[ LastOpcodeFamily ][ OpcodeFamily ] == 1
137: */
1.1.1.16! root 138: static void M68000_InitPairing(void)
1.1.1.12 root 139: {
140: /* First, clear the matrix (pairing is false) */
141: memset(PairingArray , 0 , MAX_OPCODE_FAMILY * MAX_OPCODE_FAMILY);
142:
143: /* Set all valid pairing combinations to 1 */
144: PairingArray[ i_EXG ][ i_DBcc ] = 1;
1.1.1.13 root 145: PairingArray[ i_EXG ][ i_MOVE ] = 1;
146: PairingArray[ i_EXG ][ i_MOVEA] = 1;
147:
1.1.1.12 root 148: PairingArray[ i_CMPA ][ i_Bcc ] = 1;
149: PairingArray[ i_CMP ][ i_Bcc ] = 1;
1.1.1.13 root 150:
151: M68000_InitPairing_BitShift ( i_DBcc );
152: M68000_InitPairing_BitShift ( i_MOVE );
153: M68000_InitPairing_BitShift ( i_MOVEA );
154: M68000_InitPairing_BitShift ( i_LEA );
155:
1.1.1.12 root 156: PairingArray[ i_MULU ][ i_MOVEA] = 1;
157: PairingArray[ i_MULS ][ i_MOVEA] = 1;
158: PairingArray[ i_MULU ][ i_MOVE ] = 1;
159: PairingArray[ i_MULS ][ i_MOVE ] = 1;
1.1.1.13 root 160:
161: PairingArray[ i_MULU ][ i_DIVU ] = 1;
162: PairingArray[ i_MULU ][ i_DIVS ] = 1;
163: PairingArray[ i_MULS ][ i_DIVU ] = 1;
164: PairingArray[ i_MULS ][ i_DIVS ] = 1;
165:
166: PairingArray[ i_BTST ][ i_Bcc ] = 1;
167:
168: M68000_InitPairing_BitShift ( i_ADD );
169: M68000_InitPairing_BitShift ( i_SUB );
170: M68000_InitPairing_BitShift ( i_OR );
171: M68000_InitPairing_BitShift ( i_AND );
172: M68000_InitPairing_BitShift ( i_EOR );
173: M68000_InitPairing_BitShift ( i_NOT );
174: M68000_InitPairing_BitShift ( i_CLR );
175: M68000_InitPairing_BitShift ( i_NEG );
176: M68000_InitPairing_BitShift ( i_ADDX );
177: M68000_InitPairing_BitShift ( i_SUBX );
178: M68000_InitPairing_BitShift ( i_ABCD );
179: M68000_InitPairing_BitShift ( i_SBCD );
1.1.1.16! root 180:
! 181: PairingArray[ i_ADD ][ i_MOVE ] = 1; /* when using xx(an,dn) addr mode */
! 182: PairingArray[ i_SUB ][ i_MOVE ] = 1;
! 183: }
! 184:
! 185:
! 186: /**
! 187: * One-time CPU initialization.
! 188: */
! 189: void M68000_Init(void)
! 190: {
! 191: /* Init UAE CPU core */
! 192: Init680x0();
! 193:
! 194: /* Init the pairing matrix */
! 195: M68000_InitPairing();
1.1.1.12 root 196: }
1.1 root 197:
198:
1.1.1.3 root 199: /*-----------------------------------------------------------------------*/
1.1.1.12 root 200: /**
201: * Reset CPU 68000 variables
202: */
1.1.1.13 root 203: void M68000_Reset(bool bCold)
1.1 root 204: {
1.1.1.12 root 205: /* Clear registers */
206: if (bCold)
207: {
1.1.1.16! root 208: memset(®s, 0, sizeof(regs));
1.1.1.12 root 209: }
210:
211: /* Now directly reset the UAE CPU core: */
212: m68k_reset();
213:
1.1.1.14 root 214: BusMode = BUS_MODE_CPU;
1.1.1.12 root 215: }
216:
217:
218: /*-----------------------------------------------------------------------*/
219: /**
1.1.1.16! root 220: * Start 680x0 emulation
1.1.1.12 root 221: */
222: void M68000_Start(void)
223: {
224: /* Load initial memory snapshot */
225: if (bLoadMemorySave)
226: {
1.1.1.15 root 227: MemorySnapShot_Restore(ConfigureParams.Memory.szMemoryCaptureFileName, false);
1.1.1.12 root 228: }
229: else if (bLoadAutoSave)
230: {
1.1.1.15 root 231: MemorySnapShot_Restore(ConfigureParams.Memory.szAutoSaveFileName, false);
1.1.1.12 root 232: }
1.1.1.7 root 233:
1.1.1.15 root 234: m68k_go(true);
1.1 root 235: }
236:
1.1.1.3 root 237:
238: /*-----------------------------------------------------------------------*/
1.1.1.12 root 239: /**
240: * Check wether the CPU mode has been changed.
241: */
242: void M68000_CheckCpuLevel(void)
243: {
244: changed_prefs.cpu_level = ConfigureParams.System.nCpuLevel;
245: changed_prefs.cpu_compatible = ConfigureParams.System.bCompatibleCpu;
246: #ifndef UAE_NEWCPU_H
247: changed_prefs.cpu_cycle_exact = 0; // TODO
248: #endif
249: if (table68k)
250: check_prefs_changed_cpu();
251: }
252:
253:
254: /*-----------------------------------------------------------------------*/
255: /**
256: * Save/Restore snapshot of CPU variables ('MemorySnapShot_Store' handles type)
257: */
1.1.1.13 root 258: void M68000_MemorySnapShot_Capture(bool bSave)
1.1 root 259: {
1.1.1.12 root 260: Uint32 savepc;
1.1 root 261:
1.1.1.12 root 262: /* For the UAE CPU core: */
263: MemorySnapShot_Store(&currprefs.address_space_24,
264: sizeof(currprefs.address_space_24));
265: MemorySnapShot_Store(®s.regs[0], sizeof(regs.regs)); /* D0-D7 A0-A6 */
266:
267: if (bSave)
268: {
269: savepc = M68000_GetPC();
270: MemorySnapShot_Store(&savepc, sizeof(savepc)); /* PC */
271: }
272: else
273: {
274: MemorySnapShot_Store(&savepc, sizeof(savepc)); /* PC */
275: regs.pc = savepc;
276: #ifdef UAE_NEWCPU_H
277: regs.prefetch_pc = regs.pc + 128;
278: #endif
279: }
1.1.1.8 root 280:
1.1.1.12 root 281: #ifdef UAE_NEWCPU_H
282: MemorySnapShot_Store(®s.prefetch, sizeof(regs.prefetch)); /* prefetch */
283: #else
284: uae_u32 prefetch_dummy;
285: MemorySnapShot_Store(&prefetch_dummy, sizeof(prefetch_dummy));
286: #endif
287:
288: if (bSave)
289: {
290: #ifdef UAE_NEWCPU_H
291: MakeSR();
292: #else
293: MakeSR(®s);
294: #endif
295: if (regs.s)
296: {
297: MemorySnapShot_Store(®s.usp, sizeof(regs.usp)); /* USP */
298: MemorySnapShot_Store(®s.regs[15], sizeof(regs.regs[15])); /* ISP */
299: }
300: else
301: {
302: MemorySnapShot_Store(®s.regs[15], sizeof(regs.regs[15])); /* USP */
303: MemorySnapShot_Store(®s.isp, sizeof(regs.isp)); /* ISP */
304: }
305: MemorySnapShot_Store(®s.sr, sizeof(regs.sr)); /* SR/CCR */
306: }
307: else
308: {
309: MemorySnapShot_Store(®s.usp, sizeof(regs.usp));
310: MemorySnapShot_Store(®s.isp, sizeof(regs.isp));
311: MemorySnapShot_Store(®s.sr, sizeof(regs.sr));
312: }
313: MemorySnapShot_Store(®s.stopped, sizeof(regs.stopped));
314: MemorySnapShot_Store(®s.dfc, sizeof(regs.dfc)); /* DFC */
315: MemorySnapShot_Store(®s.sfc, sizeof(regs.sfc)); /* SFC */
316: MemorySnapShot_Store(®s.vbr, sizeof(regs.vbr)); /* VBR */
317: MemorySnapShot_Store(&caar, sizeof(caar)); /* CAAR */
318: MemorySnapShot_Store(&cacr, sizeof(cacr)); /* CACR */
319: MemorySnapShot_Store(®s.msp, sizeof(regs.msp)); /* MSP */
320:
321: if (!bSave)
322: {
323: M68000_SetPC(regs.pc);
324: /* MakeFromSR() must not swap stack pointer */
325: regs.s = (regs.sr >> 13) & 1;
326: #ifdef UAE_NEWCPU_H
327: MakeFromSR();
328: /* set stack pointer */
329: if (regs.s)
330: m68k_areg(regs, 7) = regs.isp;
331: else
332: m68k_areg(regs, 7) = regs.usp;
333: #else
334: MakeFromSR(®s);
335: /* set stack pointer */
336: if (regs.s)
337: m68k_areg(®s, 7) = regs.isp;
338: else
339: m68k_areg(®s, 7) = regs.usp;
340: #endif
341: }
342:
343: if (bSave)
344: save_fpu();
345: else
346: restore_fpu();
1.1 root 347: }
348:
349:
1.1.1.3 root 350: /*-----------------------------------------------------------------------*/
1.1.1.12 root 351: /**
352: * BUSERROR - Access outside valid memory range.
353: * Use bReadWrite = 0 for write errors and bReadWrite = 1 for read errors!
354: */
1.1.1.13 root 355: void M68000_BusError(Uint32 addr, bool bReadWrite)
1.1 root 356: {
1.1.1.12 root 357: /* FIXME: In prefetch mode, m68k_getpc() seems already to point to the next instruction */
358: // BusErrorPC = M68000_GetPC(); /* [NP] We set BusErrorPC in m68k_run_1 */
1.1.1.7 root 359:
1.1.1.15 root 360: /* Do not print message when TOS is testing for available HW or
361: * when a program just checks for the floating point co-processor. */
362: if ((BusErrorPC < TosAddress || BusErrorPC > TosAddress + TosSize)
363: && addr != 0xfffa42)
1.1.1.12 root 364: {
1.1.1.15 root 365: /* Print bus error message */
366: fprintf(stderr, "M68000 Bus Error at address $%x.\n", addr);
1.1.1.12 root 367: }
368:
369: if ((regs.spcflags & SPCFLAG_BUSERROR) == 0) /* [NP] Check that the opcode has not already generated a read bus error */
370: {
371: BusErrorAddress = addr; /* Store for exception frame */
372: bBusErrorReadWrite = bReadWrite;
373: M68000_SetSpecial(SPCFLAG_BUSERROR); /* The exception will be done in newcpu.c */
374: }
1.1 root 375: }
376:
1.1.1.3 root 377:
378: /*-----------------------------------------------------------------------*/
1.1.1.12 root 379: /**
380: * Exception handler
381: */
1.1.1.13 root 382: void M68000_Exception(Uint32 ExceptionVector , int ExceptionSource)
1.1.1.12 root 383: {
384: int exceptionNr = ExceptionVector/4;
385:
1.1.1.16! root 386: if ((ExceptionSource == M68000_EXC_SRC_AUTOVEC)
! 387: && (exceptionNr>24 && exceptionNr<32)) /* 68k autovector interrupt? */
1.1.1.12 root 388: {
389: /* Handle autovector interrupts the UAE's way
390: * (see intlev() and do_specialties() in UAE CPU core) */
391: /* In our case, this part is only called for HBL and VBL interrupts */
392: int intnr = exceptionNr - 24;
393: pendingInterrupts |= (1 << intnr);
394: M68000_SetSpecial(SPCFLAG_INT);
395: }
1.1.1.13 root 396:
397: else /* MFP or direct CPU exceptions */
1.1.1.12 root 398: {
399: Uint16 SR;
400:
401: /* Was the CPU stopped, i.e. by a STOP instruction? */
402: if (regs.spcflags & SPCFLAG_STOP)
403: {
404: regs.stopped = 0;
405: M68000_UnsetSpecial(SPCFLAG_STOP); /* All is go,go,go! */
406: }
407:
408: /* 68k exceptions are handled by Exception() of the UAE CPU core */
409: #ifdef UAE_NEWCPU_H
1.1.1.13 root 410: Exception(exceptionNr, m68k_getpc(), ExceptionSource);
1.1.1.12 root 411: #else
412: Exception(exceptionNr, ®s, m68k_getpc(®s));
413: #endif
414:
415: SR = M68000_GetSR();
416:
417: /* Set Status Register so interrupt can ONLY be stopped by another interrupt
418: * of higher priority! */
1.1.1.16! root 419: if (ExceptionSource == M68000_EXC_SRC_INT_MFP)
1.1.1.12 root 420: {
421: Uint32 MFPBaseVector = (unsigned int)(MFP_VR&0xf0)<<2;
422: if ( (ExceptionVector>=MFPBaseVector) && (ExceptionVector<=(MFPBaseVector+0x3c)) )
423: SR = (SR&SR_CLEAR_IPL)|0x0600; /* MFP, level 6 */
424: }
1.1.1.16! root 425: else if (ExceptionSource == M68000_EXC_SRC_INT_DSP)
! 426: {
! 427: SR = (SR&SR_CLEAR_IPL)|0x0600; /* DSP, level 6 */
! 428: }
1.1.1.12 root 429:
430: M68000_SetSR(SR);
431: }
1.1 root 432: }
433:
1.1.1.8 root 434:
435: /*-----------------------------------------------------------------------*/
1.1.1.12 root 436: /**
437: * There seem to be wait states when a program accesses certain hardware
438: * registers on the ST. Use this function to simulate these wait states.
439: * [NP] with some instructions like CLR, we have a read then a write at the
440: * same location, so we may have 2 wait states (read and write) to add
441: * (nWaitStateCycles should be reset to 0 after the cycles were added).
442: */
1.1.1.11 root 443: void M68000_WaitState(int nCycles)
1.1.1.8 root 444: {
1.1.1.12 root 445: M68000_SetSpecial(SPCFLAG_EXTRA_CYCLES);
1.1.1.11 root 446:
1.1.1.12 root 447: nWaitStateCycles += nCycles; /* add all the wait states for this instruction */
1.1.1.8 root 448: }
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