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1.1 root 1: /*
1.1.1.6 root 2: Hatari - m68000.c
1.1 root 3:
1.1.1.6 root 4: This file is distributed under the GNU Public License, version 2 or at
5: your option any later version. Read the file gpl.txt for details.
6:
7: These routines originally (in WinSTon) handled exceptions as well as some
1.1.1.5 root 8: few OpCode's such as Line-F and Line-A. In Hatari it has mainly become a
9: wrapper between the WinSTon sources and the UAE CPU code.
1.1 root 10: */
1.1.1.12 root 11:
12: /* 2007/03/xx [NP] Possibility to add several wait states for the same instruction in */
13: /* M68000_WaitState (e.g. clr.b $fa1b.w in Decade Demo Menu). */
14: /* 2007/04/14 [NP] Add support for instruction pairing in M68000_AddCycles, using OpcodeFamily and */
15: /* LastOpcodeFamily (No Cooper Loader, Oh Crickey ... Hidden Screen). */
16: /* 2007/04/24 [NP] Add pairing for BCLR/Bcc. */
17: /* 2007/09/29 [NP] Use the new int.c and INT_CONVERT_TO_INTERNAL. */
18: /* 2007/11/26 [NP] We set BusErrorPC in m68k_run_1 instead of M68000_BusError, else the BusErrorPC */
19: /* will not point to the opcode that generated the bus error. */
20: /* In M68000_BusError, if we have 'move.l $0,$24', we need to generate a bus error */
21: /* for the read, not for the write that should occur after (TransBeauce 2 Demo). */
22: /* 2008/01/07 [NP] Function 'M68000_InitPairing' and 'PairingArray' as a lookup table for fast */
23: /* determination of valid pairing combinations (replace lots of 'if' tests in */
24: /* m68000.h). */
25: /* 2008/01/25 [NP] Add pairing for LSR/MOVE (and all other bit shifting instr) (Anomaly Demo Intro)*/
26: /* 2008/02/02 [NP] Add pairing for CMP/Bcc (Level 16 Fullscreen (1988)). */
27: /* 2008/02/08 [NP] Add pairing for LSL/LEA (and all other bit shifting instr) (TVI 2 - The Year */
28: /* After Demo). */
29: /* 2008/02/11 [NP] Add pairing for MULS/MOVEA (Delirious Demo IV Loader). */
30: /* 2008/01/25 [NP] Add pairing for LSR/MOVEA (and all other bit shifting instr) (Decade Demo Reset)*/
1.1.1.13 root 31: /* 2008/02/16 [NP] Add pairing for MULS/DIVS (fixes e605 demo part 3). */
1.1.1.12 root 32: /* 2008/03/08 [NP] In M68000_Exception, we need to know if the exception was triggered by an MFP */
33: /* interrupt or by a video interrupt. In the case MFP vector base was changed in */
34: /* fffa17 to an other value than the default $40, testing exceptionNr is not enough*/
35: /* to correctly process the exception. For example, if vector base is set to $10 */
36: /* then MFP Timer A will call vector stored at address $74, which would be wrongly */
37: /* interpreted as a level 5 int (which doesn't exist on Atari and will cause an */
1.1.1.13 root 38: /* assert to fail in intlevel()). We use InterruptSource to correctly recognize the*/
1.1.1.12 root 39: /* MFP interrupts (fix 'Toki' end part fullscreen which sets vector base to $10). */
1.1.1.13 root 40: /* 2008/04/14 [NP] Add pairing for BTST/Bcc (eg btst #7,d0 + bne.s label (with branch taken)). */
41: /* 2008/04/15 [NP] As tested on a real STF : */
42: /* - MUL/DIV can pair (but DIV/MUL can't) */
43: /* (eg mulu d0,d0 + divs d1,d1 with d0=0 and d1=1) */
44: /* - MUL/MOVE can pair, but not DIV/MOVE */
45: /* - EXG/MOVE can pair (eg exg d3,d4 + move.l 0(a3,d1.w),a4) */
46: /* - MOVE/DBcc can't pair */
47: /* 2008/04/16 [NP] Functions 'M68000_InitPairing_BitShift' to ease code maintenance. */
48: /* Tested on STF : add pairing between bit shift instr and ADD/SUB/OR/AND/EOR/NOT */
49: /* CLR/NEG (certainly some more possible, haven't tested everything) */
50: /* (fixes lsr.w #4,d4 + add.b $f0(a4,d4),d7 used in Zoolook part of ULM New Year). */
51: /* 2008/07/08 [NP] Add pairing between bit shift instr and ADDX/SUBX/ABCD/SBCD (fixes lsl.l #1,d0 */
52: /* + abcd d1,d1 used in Dragonnels - Rainbow Wall). */
53: /* 2008/10/05 [NP] Pass the 'ExceptionSource' parameter to Exception() in uae-cpu/newcpu.c */
1.1.1.16 root 54: /* 2010/05/07 [NP] Add pairing for ADD/MOVE ; such pairing should only be possible when combined */
55: /* with d8(an,ix) address mode (eg: add.l (a5,d1.w),d0 + move.b 7(a5,d1.w),d5) */
56: /* (fixes Sommarhack 2010 Invitation by DHS). */
1.1.1.17 root 57: /* 2010/11/07 [NP] Add pairing between bit shift instr and JMP (fixes lsl.w #2,d0 + jmp 2(pc,d0) */
58: /* used in Fullparts by Hemoroids). */
1.1.1.18 root 59: /* 2011/12/11 [NP] Add pairing between MUL and JSR (fixes muls #52,d2 + jsr 0(a1,d2.w) used in */
60: /* Lemmings Compilation 40's Intro). */
1.1.1.12 root 61:
62:
1.1.1.14 root 63: const char M68000_fileid[] = "Hatari m68000.c : " __DATE__ " " __TIME__;
1.1 root 64:
65: #include "main.h"
1.1.1.12 root 66: #include "configuration.h"
1.1 root 67: #include "gemdos.h"
1.1.1.6 root 68: #include "hatari-glue.h"
1.1.1.16 root 69: #include "cycInt.h"
1.1 root 70: #include "m68000.h"
71: #include "memorySnapShot.h"
72: #include "mfp.h"
1.1.1.12 root 73: #include "options.h"
74: #include "savestate.h"
1.1 root 75: #include "stMemory.h"
76: #include "tos.h"
77:
78:
1.1.1.12 root 79: Uint32 BusErrorAddress; /* Stores the offending address for bus-/address errors */
80: Uint32 BusErrorPC; /* Value of the PC when bus error occurs */
1.1.1.13 root 81: bool bBusErrorReadWrite; /* 0 for write error, 1 for read error */
1.1.1.12 root 82: int nCpuFreqShift; /* Used to emulate higher CPU frequencies: 0=8MHz, 1=16MHz, 2=32Mhz */
83: int nWaitStateCycles; /* Used to emulate the wait state cycles of certain IO registers */
1.1.1.14 root 84: int BusMode = BUS_MODE_CPU; /* Used to tell which part is owning the bus (cpu, blitter, ...) */
1.1.1.12 root 85:
1.1.1.16 root 86: int LastOpcodeFamily = i_NOP; /* see the enum in readcpu.h i_XXX */
87: int LastInstrCycles = 0; /* number of cycles for previous instr. (not rounded to 4) */
88: int Pairing = 0; /* set to 1 if the latest 2 intr paired */
1.1.1.12 root 89: char PairingArray[ MAX_OPCODE_FAMILY ][ MAX_OPCODE_FAMILY ];
90:
91:
92: /* to convert the enum from OpcodeFamily to a readable value for pairing's debug */
93: const char *OpcodeName[] = { "ILLG",
94: "OR","AND","EOR","ORSR","ANDSR","EORSR",
95: "SUB","SUBA","SUBX","SBCD",
96: "ADD","ADDA","ADDX","ABCD",
97: "NEG","NEGX","NBCD","CLR","NOT","TST",
98: "BTST","BCHG","BCLR","BSET",
99: "CMP","CMPM","CMPA",
100: "MVPRM","MVPMR","MOVE","MOVEA","MVSR2","MV2SR",
101: "SWAP","EXG","EXT","MVMEL","MVMLE",
102: "TRAP","MVR2USP","MVUSP2R","RESET","NOP","STOP","RTE","RTD",
103: "LINK","UNLK",
104: "RTS","TRAPV","RTR",
105: "JSR","JMP","BSR","Bcc",
106: "LEA","PEA","DBcc","Scc",
107: "DIVU","DIVS","MULU","MULS",
108: "ASR","ASL","LSR","LSL","ROL","ROR","ROXL","ROXR",
109: "ASRW","ASLW","LSRW","LSLW","ROLW","RORW","ROXLW","ROXRW",
110: "CHK","CHK2",
111: "MOVEC2","MOVE2C","CAS","CAS2","DIVL","MULL",
112: "BFTST","BFEXTU","BFCHG","BFEXTS","BFCLR","BFFFO","BFSET","BFINS",
113: "PACK","UNPK","TAS","BKPT","CALLM","RTM","TRAPcc","MOVES",
114: "FPP","FDBcc","FScc","FTRAPcc","FBcc","FSAVE","FRESTORE",
115: "CINVL","CINVP","CINVA","CPUSHL","CPUSHP","CPUSHA","MOVE16",
116: "MMUOP"
117: };
1.1.1.8 root 118:
1.1.1.12 root 119:
120: /*-----------------------------------------------------------------------*/
121: /**
1.1.1.13 root 122: * Add pairing between all the bit shifting instructions and a given Opcode
123: */
124:
125: static void M68000_InitPairing_BitShift ( int OpCode )
126: {
127: PairingArray[ i_ASR ][ OpCode ] = 1;
128: PairingArray[ i_ASL ][ OpCode ] = 1;
129: PairingArray[ i_LSR ][ OpCode ] = 1;
130: PairingArray[ i_LSL ][ OpCode ] = 1;
131: PairingArray[ i_ROL ][ OpCode ] = 1;
132: PairingArray[ i_ROR ][ OpCode ] = 1;
133: PairingArray[ i_ROXR ][ OpCode ] = 1;
134: PairingArray[ i_ROXL ][ OpCode ] = 1;
135: }
136:
137:
138: /**
1.1.1.12 root 139: * Init the pairing matrix
140: * Two instructions can pair if PairingArray[ LastOpcodeFamily ][ OpcodeFamily ] == 1
141: */
1.1.1.16 root 142: static void M68000_InitPairing(void)
1.1.1.12 root 143: {
144: /* First, clear the matrix (pairing is false) */
145: memset(PairingArray , 0 , MAX_OPCODE_FAMILY * MAX_OPCODE_FAMILY);
146:
147: /* Set all valid pairing combinations to 1 */
148: PairingArray[ i_EXG ][ i_DBcc ] = 1;
1.1.1.13 root 149: PairingArray[ i_EXG ][ i_MOVE ] = 1;
150: PairingArray[ i_EXG ][ i_MOVEA] = 1;
151:
1.1.1.12 root 152: PairingArray[ i_CMPA ][ i_Bcc ] = 1;
153: PairingArray[ i_CMP ][ i_Bcc ] = 1;
1.1.1.13 root 154:
155: M68000_InitPairing_BitShift ( i_DBcc );
156: M68000_InitPairing_BitShift ( i_MOVE );
157: M68000_InitPairing_BitShift ( i_MOVEA );
158: M68000_InitPairing_BitShift ( i_LEA );
1.1.1.17 root 159: M68000_InitPairing_BitShift ( i_JMP );
1.1.1.13 root 160:
1.1.1.12 root 161: PairingArray[ i_MULU ][ i_MOVEA] = 1;
162: PairingArray[ i_MULS ][ i_MOVEA] = 1;
163: PairingArray[ i_MULU ][ i_MOVE ] = 1;
164: PairingArray[ i_MULS ][ i_MOVE ] = 1;
1.1.1.13 root 165:
166: PairingArray[ i_MULU ][ i_DIVU ] = 1;
167: PairingArray[ i_MULU ][ i_DIVS ] = 1;
168: PairingArray[ i_MULS ][ i_DIVU ] = 1;
169: PairingArray[ i_MULS ][ i_DIVS ] = 1;
170:
1.1.1.18 root 171: PairingArray[ i_MULU ][ i_JSR ] = 1;
172: PairingArray[ i_MULS ][ i_JSR ] = 1;
173:
1.1.1.13 root 174: PairingArray[ i_BTST ][ i_Bcc ] = 1;
175:
176: M68000_InitPairing_BitShift ( i_ADD );
177: M68000_InitPairing_BitShift ( i_SUB );
178: M68000_InitPairing_BitShift ( i_OR );
179: M68000_InitPairing_BitShift ( i_AND );
180: M68000_InitPairing_BitShift ( i_EOR );
181: M68000_InitPairing_BitShift ( i_NOT );
182: M68000_InitPairing_BitShift ( i_CLR );
183: M68000_InitPairing_BitShift ( i_NEG );
184: M68000_InitPairing_BitShift ( i_ADDX );
185: M68000_InitPairing_BitShift ( i_SUBX );
186: M68000_InitPairing_BitShift ( i_ABCD );
187: M68000_InitPairing_BitShift ( i_SBCD );
1.1.1.16 root 188:
189: PairingArray[ i_ADD ][ i_MOVE ] = 1; /* when using xx(an,dn) addr mode */
190: PairingArray[ i_SUB ][ i_MOVE ] = 1;
191: }
192:
193:
194: /**
195: * One-time CPU initialization.
196: */
197: void M68000_Init(void)
198: {
199: /* Init UAE CPU core */
200: Init680x0();
201:
202: /* Init the pairing matrix */
203: M68000_InitPairing();
1.1.1.12 root 204: }
1.1 root 205:
206:
1.1.1.3 root 207: /*-----------------------------------------------------------------------*/
1.1.1.12 root 208: /**
209: * Reset CPU 68000 variables
210: */
1.1.1.13 root 211: void M68000_Reset(bool bCold)
1.1 root 212: {
1.1.1.19! root 213: #if ENABLE_WINUAE_CPU
1.1.1.12 root 214: if (bCold)
215: {
1.1.1.19! root 216: /* Clear registers, but we need to keep SPCFLAG_MODE_CHANGE and SPCFLAG_BRK unchanged */
! 217: int spcFlags = regs.spcflags & (SPCFLAG_MODE_CHANGE | SPCFLAG_BRK);
1.1.1.16 root 218: memset(®s, 0, sizeof(regs));
1.1.1.19! root 219: regs.spcflags = spcFlags;
1.1.1.12 root 220: }
1.1.1.19! root 221: /* Now reset the WINUAE CPU core */
! 222: /* Laurent : for now, using parameter 0 (Hard reset), but some other parameters can be used here (see newcpu.c) */
1.1.1.17 root 223: m68k_reset(0);
1.1.1.19! root 224: #else /* UAE CPU core */
! 225: if (bCold)
! 226: {
! 227: /* Clear registers */
! 228: memset(®s, 0, sizeof(regs));
! 229: }
! 230: /* Now reset the UAE CPU core */
1.1.1.12 root 231: m68k_reset();
1.1.1.17 root 232: #endif
1.1.1.14 root 233: BusMode = BUS_MODE_CPU;
1.1.1.12 root 234: }
235:
236:
237: /*-----------------------------------------------------------------------*/
238: /**
1.1.1.16 root 239: * Start 680x0 emulation
1.1.1.12 root 240: */
241: void M68000_Start(void)
242: {
243: /* Load initial memory snapshot */
244: if (bLoadMemorySave)
245: {
1.1.1.15 root 246: MemorySnapShot_Restore(ConfigureParams.Memory.szMemoryCaptureFileName, false);
1.1.1.12 root 247: }
248: else if (bLoadAutoSave)
249: {
1.1.1.15 root 250: MemorySnapShot_Restore(ConfigureParams.Memory.szAutoSaveFileName, false);
1.1.1.12 root 251: }
1.1.1.7 root 252:
1.1.1.15 root 253: m68k_go(true);
1.1 root 254: }
255:
1.1.1.3 root 256:
257: /*-----------------------------------------------------------------------*/
1.1.1.12 root 258: /**
1.1.1.17 root 259: * Check whether CPU settings have been changed.
1.1.1.12 root 260: */
1.1.1.17 root 261: void M68000_CheckCpuSettings(void)
1.1.1.12 root 262: {
1.1.1.17 root 263: if (ConfigureParams.System.nCpuFreq < 12)
264: {
265: ConfigureParams.System.nCpuFreq = 8;
266: nCpuFreqShift = 0;
267: }
268: else if (ConfigureParams.System.nCpuFreq > 26)
269: {
270: ConfigureParams.System.nCpuFreq = 32;
271: nCpuFreqShift = 2;
272: }
273: else
274: {
275: ConfigureParams.System.nCpuFreq = 16;
276: nCpuFreqShift = 1;
277: }
1.1.1.12 root 278: changed_prefs.cpu_level = ConfigureParams.System.nCpuLevel;
279: changed_prefs.cpu_compatible = ConfigureParams.System.bCompatibleCpu;
1.1.1.17 root 280:
281: #if ENABLE_WINUAE_CPU
1.1.1.19! root 282: /* WinUAE core uses cpu_model instead of cpu_level, so we've got to
! 283: * convert these values here: */
1.1.1.17 root 284: switch (changed_prefs.cpu_level) {
285: case 0 : changed_prefs.cpu_model = 68000; break;
286: case 1 : changed_prefs.cpu_model = 68010; break;
287: case 2 : changed_prefs.cpu_model = 68020; break;
288: case 3 : changed_prefs.cpu_model = 68030; break;
289: case 4 : changed_prefs.cpu_model = 68040; break;
290: case 5 : changed_prefs.cpu_model = 68060; break;
291: default: fprintf (stderr, "Init680x0() : Error, cpu_level unknown\n");
292: }
1.1.1.19! root 293: currprefs.cpu_level = changed_prefs.cpu_level;
1.1.1.17 root 294:
295: changed_prefs.address_space_24 = ConfigureParams.System.bAddressSpace24;
296: changed_prefs.cpu_cycle_exact = ConfigureParams.System.bCycleExactCpu;
297: changed_prefs.fpu_model = ConfigureParams.System.n_FPUType;
298: changed_prefs.fpu_strict = ConfigureParams.System.bCompatibleFPU;
299: changed_prefs.mmu_model = ConfigureParams.System.bMMU;
1.1.1.12 root 300: #endif
301: if (table68k)
302: check_prefs_changed_cpu();
303: }
304:
305:
306: /*-----------------------------------------------------------------------*/
307: /**
308: * Save/Restore snapshot of CPU variables ('MemorySnapShot_Store' handles type)
309: */
1.1.1.13 root 310: void M68000_MemorySnapShot_Capture(bool bSave)
1.1 root 311: {
1.1.1.12 root 312: Uint32 savepc;
1.1.1.17 root 313: #if ENABLE_WINUAE_CPU
314: int len;
315: uae_u8 *chunk = 0;
316: #endif
1.1 root 317:
1.1.1.12 root 318: /* For the UAE CPU core: */
319: MemorySnapShot_Store(&currprefs.address_space_24,
320: sizeof(currprefs.address_space_24));
321: MemorySnapShot_Store(®s.regs[0], sizeof(regs.regs)); /* D0-D7 A0-A6 */
322:
323: if (bSave)
324: {
325: savepc = M68000_GetPC();
326: MemorySnapShot_Store(&savepc, sizeof(savepc)); /* PC */
327: }
328: else
329: {
330: MemorySnapShot_Store(&savepc, sizeof(savepc)); /* PC */
331: regs.pc = savepc;
332: #ifdef UAE_NEWCPU_H
333: regs.prefetch_pc = regs.pc + 128;
334: #endif
335: }
1.1.1.8 root 336:
1.1.1.12 root 337: #ifdef UAE_NEWCPU_H
338: MemorySnapShot_Store(®s.prefetch, sizeof(regs.prefetch)); /* prefetch */
339: #else
340: uae_u32 prefetch_dummy;
341: MemorySnapShot_Store(&prefetch_dummy, sizeof(prefetch_dummy));
342: #endif
343:
344: if (bSave)
345: {
346: MakeSR();
347: if (regs.s)
348: {
349: MemorySnapShot_Store(®s.usp, sizeof(regs.usp)); /* USP */
350: MemorySnapShot_Store(®s.regs[15], sizeof(regs.regs[15])); /* ISP */
351: }
352: else
353: {
354: MemorySnapShot_Store(®s.regs[15], sizeof(regs.regs[15])); /* USP */
355: MemorySnapShot_Store(®s.isp, sizeof(regs.isp)); /* ISP */
356: }
357: MemorySnapShot_Store(®s.sr, sizeof(regs.sr)); /* SR/CCR */
358: }
359: else
360: {
361: MemorySnapShot_Store(®s.usp, sizeof(regs.usp));
362: MemorySnapShot_Store(®s.isp, sizeof(regs.isp));
363: MemorySnapShot_Store(®s.sr, sizeof(regs.sr));
364: }
365: MemorySnapShot_Store(®s.stopped, sizeof(regs.stopped));
366: MemorySnapShot_Store(®s.dfc, sizeof(regs.dfc)); /* DFC */
367: MemorySnapShot_Store(®s.sfc, sizeof(regs.sfc)); /* SFC */
368: MemorySnapShot_Store(®s.vbr, sizeof(regs.vbr)); /* VBR */
1.1.1.17 root 369: #if ENABLE_WINUAE_CPU
370: MemorySnapShot_Store(®s.caar, sizeof(regs.caar)); /* CAAR */
371: MemorySnapShot_Store(®s.cacr, sizeof(regs.cacr)); /* CACR */
372: #else
1.1.1.12 root 373: MemorySnapShot_Store(&caar, sizeof(caar)); /* CAAR */
374: MemorySnapShot_Store(&cacr, sizeof(cacr)); /* CACR */
1.1.1.17 root 375: #endif
1.1.1.12 root 376: MemorySnapShot_Store(®s.msp, sizeof(regs.msp)); /* MSP */
377:
378: if (!bSave)
379: {
380: M68000_SetPC(regs.pc);
381: /* MakeFromSR() must not swap stack pointer */
382: regs.s = (regs.sr >> 13) & 1;
383: MakeFromSR();
384: /* set stack pointer */
385: if (regs.s)
386: m68k_areg(regs, 7) = regs.isp;
387: else
388: m68k_areg(regs, 7) = regs.usp;
389: }
390:
1.1.1.17 root 391: #if ENABLE_WINUAE_CPU
392: if (bSave)
393: save_fpu(&len,0);
394: else
395: restore_fpu(chunk);
396: #else
1.1.1.12 root 397: if (bSave)
398: save_fpu();
399: else
400: restore_fpu();
1.1.1.17 root 401: #endif
1.1 root 402: }
403:
404:
1.1.1.3 root 405: /*-----------------------------------------------------------------------*/
1.1.1.12 root 406: /**
407: * BUSERROR - Access outside valid memory range.
1.1.1.17 root 408: * Use bRead = 0 for write errors and bRead = 1 for read errors!
1.1.1.12 root 409: */
1.1.1.17 root 410: void M68000_BusError(Uint32 addr, bool bRead)
1.1 root 411: {
1.1.1.12 root 412: /* FIXME: In prefetch mode, m68k_getpc() seems already to point to the next instruction */
413: // BusErrorPC = M68000_GetPC(); /* [NP] We set BusErrorPC in m68k_run_1 */
1.1.1.7 root 414:
1.1.1.15 root 415: /* Do not print message when TOS is testing for available HW or
416: * when a program just checks for the floating point co-processor. */
417: if ((BusErrorPC < TosAddress || BusErrorPC > TosAddress + TosSize)
418: && addr != 0xfffa42)
1.1.1.12 root 419: {
1.1.1.15 root 420: /* Print bus error message */
1.1.1.17 root 421: fprintf(stderr, "M68000 Bus Error %s at address $%x.\n",
422: bRead ? "reading" : "writing", addr);
1.1.1.12 root 423: }
424:
425: if ((regs.spcflags & SPCFLAG_BUSERROR) == 0) /* [NP] Check that the opcode has not already generated a read bus error */
426: {
427: BusErrorAddress = addr; /* Store for exception frame */
1.1.1.17 root 428: bBusErrorReadWrite = bRead;
1.1.1.12 root 429: M68000_SetSpecial(SPCFLAG_BUSERROR); /* The exception will be done in newcpu.c */
430: }
1.1 root 431: }
432:
1.1.1.3 root 433:
434: /*-----------------------------------------------------------------------*/
1.1.1.12 root 435: /**
436: * Exception handler
437: */
1.1.1.13 root 438: void M68000_Exception(Uint32 ExceptionVector , int ExceptionSource)
1.1.1.12 root 439: {
440: int exceptionNr = ExceptionVector/4;
441:
1.1.1.16 root 442: if ((ExceptionSource == M68000_EXC_SRC_AUTOVEC)
443: && (exceptionNr>24 && exceptionNr<32)) /* 68k autovector interrupt? */
1.1.1.12 root 444: {
445: /* Handle autovector interrupts the UAE's way
446: * (see intlev() and do_specialties() in UAE CPU core) */
447: /* In our case, this part is only called for HBL and VBL interrupts */
448: int intnr = exceptionNr - 24;
449: pendingInterrupts |= (1 << intnr);
450: M68000_SetSpecial(SPCFLAG_INT);
451: }
1.1.1.13 root 452:
453: else /* MFP or direct CPU exceptions */
1.1.1.12 root 454: {
455: Uint16 SR;
456:
457: /* Was the CPU stopped, i.e. by a STOP instruction? */
458: if (regs.spcflags & SPCFLAG_STOP)
459: {
460: regs.stopped = 0;
461: M68000_UnsetSpecial(SPCFLAG_STOP); /* All is go,go,go! */
462: }
463:
464: /* 68k exceptions are handled by Exception() of the UAE CPU core */
1.1.1.17 root 465: #if ENABLE_WINUAE_CPU
466: Exception(exceptionNr, m68k_getpc(), ExceptionSource);
467: #else
1.1.1.12 root 468: #ifdef UAE_NEWCPU_H
1.1.1.13 root 469: Exception(exceptionNr, m68k_getpc(), ExceptionSource);
1.1.1.12 root 470: #else
471: Exception(exceptionNr, ®s, m68k_getpc(®s));
472: #endif
1.1.1.17 root 473: #endif
1.1.1.12 root 474: SR = M68000_GetSR();
475:
476: /* Set Status Register so interrupt can ONLY be stopped by another interrupt
477: * of higher priority! */
1.1.1.16 root 478: if (ExceptionSource == M68000_EXC_SRC_INT_MFP)
1.1.1.12 root 479: {
480: Uint32 MFPBaseVector = (unsigned int)(MFP_VR&0xf0)<<2;
481: if ( (ExceptionVector>=MFPBaseVector) && (ExceptionVector<=(MFPBaseVector+0x3c)) )
482: SR = (SR&SR_CLEAR_IPL)|0x0600; /* MFP, level 6 */
483: }
1.1.1.16 root 484: else if (ExceptionSource == M68000_EXC_SRC_INT_DSP)
485: {
486: SR = (SR&SR_CLEAR_IPL)|0x0600; /* DSP, level 6 */
487: }
1.1.1.12 root 488:
489: M68000_SetSR(SR);
490: }
1.1 root 491: }
492:
1.1.1.8 root 493:
494: /*-----------------------------------------------------------------------*/
1.1.1.12 root 495: /**
496: * There seem to be wait states when a program accesses certain hardware
497: * registers on the ST. Use this function to simulate these wait states.
498: * [NP] with some instructions like CLR, we have a read then a write at the
499: * same location, so we may have 2 wait states (read and write) to add
500: * (nWaitStateCycles should be reset to 0 after the cycles were added).
501: */
1.1.1.11 root 502: void M68000_WaitState(int nCycles)
1.1.1.8 root 503: {
1.1.1.12 root 504: M68000_SetSpecial(SPCFLAG_EXTRA_CYCLES);
1.1.1.11 root 505:
1.1.1.12 root 506: nWaitStateCycles += nCycles; /* add all the wait states for this instruction */
1.1.1.8 root 507: }
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