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1.1 root 1: /*
1.1.1.4 root 2: Hatari - psg.c
1.1 root 3:
1.1.1.4 root 4: This file is distributed under the GNU Public License, version 2 or at
5: your option any later version. Read the file gpl.txt for details.
1.1.1.3 root 6:
1.1.1.4 root 7: Programmable Sound Generator (YM-2149) - PSG
1.1.1.3 root 8:
1.1.1.4 root 9: Also used for the printer (centronics) port emulation (PSG Port B, Register 15)
1.1 root 10: */
1.1.1.7 root 11:
12:
13: /* 2007/04/14 [NP] First approximation to get cycle accurate accesses to ff8800/02 */
14: /* by cumulating wait state of 1 cycle and rounding the final */
15: /* result to 4. */
16: /* 2007/04/29 [NP] Functions PSG_Void_WriteByte and PSG_Void_ReadByte to handle */
17: /* accesses to $ff8801/03. These adresses have no effect, but they */
18: /* must give a 1 cycle wait state (e.g. move.l d0,ff8800). */
19: /* 2007/09/29 [NP] Replace printf by calls to HATARI_TRACE. */
20: /* 2007/10/23 [NP] In PSG_Void_WriteByte, add a wait state only if no wait state */
21: /* were added so far (hack, but gives good result). */
22: /* 2007/11/18 [NP] In PSG_DataRegister_WriteByte, set unused bit to 0, in case */
23: /* the data reg is read later (fix Mindbomb Demo / BBC). */
1.1.1.9 root 24: /* 2008/04/20 [NP] In PSG_DataRegister_WriteByte, set unused bit to 0 for register */
25: /* 6 too (noise period). */
26: /* 2008/07/27 [NP] Better separation between accesses to the YM hardware registers */
27: /* and the sound rendering routines. Use Sound_WriteReg() to pass */
28: /* all writes to the sound rendering functions. This allows to */
29: /* have sound.c independant of psg.c (to ease replacement of */
30: /* sound.c by another rendering method). */
31: /* 2008/08/11 [NP] Set drive leds. */
32: /* 2008/10/16 [NP] When writing to $ff8800, register select should not be masked */
33: /* with 0xf, it's a real 8 bits register where all bits are */
34: /* significant. This means only value <16 should be considered as */
35: /* valid register selection. When reg select is >= 16, all writes */
36: /* and reads in $ff8802 should be ignored. */
37: /* (fix European Demo Intro, which sets addr reg to 0x10 when */
38: /* sample playback is disabled). */
1.1.1.10 root 39: /* 2008/12/21 [NP] After testing different cases on a real STF, rewrite registers */
40: /* handling. As only pins BC1 and BDIR are used in an Atari to */
41: /* address the YM2149, this means only 1 bit is necessary to access*/
42: /* select/data registers. Other variations of the $ff88xx addresses*/
43: /* will point to either $ff8800 or $ff8802. Only bit 1 of $ff88xx */
44: /* is useful to know which register is accessed in the YM2149. */
45: /* So, it's possible to access the YM2149 with $ff8801 and $ff8803 */
46: /* but under conditions : the write to a shadow address (bit 0=1) */
47: /* can't be made by an instruction that writes to the same address */
48: /* with bit 0=0 at the same time (.W or .L access). */
49: /* In that case, only the address with bit 0=0 is taken into */
50: /* account. This means a write to $ff8801/03 will succeed only if */
51: /* the access size is .B (byte) or the opcode is a movep (because */
52: /* in that case we won't access the same register with 2 different */
53: /* addresses) (fix the game X-Out, which uses movep.w to write to */
54: /* $ff8801/03). */
55: /* Refactorize some code for cleaner handling of these accesses. */
56: /* Only reads to $ff8800 will return a data, reads to $ff8801/02/03*/
57: /* always return 0xff (tested on STF). */
58: /* When PSGRegisterSelect > 15, reads to $ff8800 also return 0xff. */
59: /* 2009/01/24 [NP] Remove redundant test, as movep implies SIZE_BYTE access. */
1.1.1.7 root 60:
61:
62: /* Emulating wait states when accessing $ff8800/01/02/03 with different 'move' variants */
63: /* is a complex task. So far, adding 1 cycle wait state to each access and rounding the */
64: /* final number to 4 gives some good results, but this is certainly not the way it's */
65: /* working for real in the ST. */
66: /* The following examples show some verified wait states for different accesses : */
67: /* lea $ffff8800,a1 */
68: /* lea $ffff8802,a2 */
69: /* lea $ffff8801,a3 */
70: /* */
71: /* movep.w d1,(a1) ; 20 16+4 (ventura loader) */
72: /* movep.l d1,(a1) ; 28 24+4 (ventura loader, ulm loader) */
73: /* */
74: /* movep.l d6,0(a5) ; 28 24+4 (SNY I, TCB) */
75: /* movep.w d5,0(a5) ; 20 16+4 (SNY I, TCB) */
76: /* */
77: /* move.b d1,(a1) ; 12 8+4 */
78: /* move.b d1,(a2) ; 12 8+4 */
79: /* move.b d1,(a3) ; 12 8+4 (crickey ulm hidden) */
80: /* */
81: /* move.w d1,(a1) ; 12 8+4 */
82: /* move.w d1,(a2) ; 12 8+4 */
83: /* move.l d1,(a1) ; 16 12+4 (ulm loader) */
84: /* */
85: /* movem.l d1,(a1) ; 20 16+4 */
86: /* movem.l d1-d2,(a1) ; 28 24+4 */
87: /* movem.l d1-d3,(a1) ; 40 32+4+4 */
88: /* movem.l d1-d4,(a1) ; 48 40+4+4 */
89: /* movem.l d1-d5,(a1) ; 60 48+4+4+4 */
90: /* movem.l d1-d6,(a1) ; 68 56+4+4+4 */
91: /* movem.l d1-d7,(a1) ; 80 64+4+4+4+4 */
92: /* movem.l d0-d7,(a1) ; 88 72+4+4+4+4 */
93: /* */
1.1.1.10 root 94: /* movep.w d0,(a3) (X-Out) */
95: /* */
1.1.1.7 root 96: /* This gives the following "model" : */
97: /* - each access to $ff8800 or $ff8802 add 1 cycle wait state */
1.1.1.10 root 98: /* - accesses to $ff8801 or $ff8803 are considered "valid" only if we don't access */
99: /* the corresponding "non shadow" addresses $ff8800/02 at the same time. */
100: /* This means only .B size (move.b for example) or movep opcode will work. */
101: /* If the access is valid, add 1 cycle wait state, else ignore the write and */
102: /* don't add any cycle. */
1.1.1.7 root 103:
104:
105:
1.1.1.11 root 106: const char PSG_fileid[] = "Hatari psg.c : " __DATE__ " " __TIME__;
1.1 root 107:
108: #include "main.h"
1.1.1.3 root 109: #include "configuration.h"
1.1.1.4 root 110: #include "ioMem.h"
1.1.1.5 root 111: #include "joy.h"
1.1.1.7 root 112: #include "log.h"
1.1.1.4 root 113: #include "m68000.h"
1.1 root 114: #include "memorySnapShot.h"
115: #include "sound.h"
1.1.1.4 root 116: #include "printer.h" /* because Printer I/O goes through PSG Register 15 */
1.1.1.3 root 117: #include "psg.h"
1.1.1.7 root 118: #if ENABLE_DSP_EMU
119: #include "falcon/dsp.h"
120: #endif
1.1.1.12! root 121: #include "screen.h"
1.1.1.7 root 122: #include "video.h"
1.1.1.9 root 123: #include "statusbar.h"
124: #include "mfp.h"
125:
1.1 root 126:
1.1.1.4 root 127: Uint8 PSGRegisterSelect; /* 0xff8800 (read/write) */
128: Uint8 PSGRegisters[16]; /* Register in PSG, see PSG_REG_xxxx */
129:
1.1.1.9 root 130: static unsigned int LastStrobe=0; /* Falling edge of Strobe used for printer */
1.1 root 131:
132:
133: /*-----------------------------------------------------------------------*/
1.1.1.7 root 134: /**
135: * Reset variables used in PSG
136: */
1.1 root 137: void PSG_Reset(void)
138: {
1.1.1.4 root 139: PSGRegisterSelect = 0;
140: memset(PSGRegisters, 0, sizeof(PSGRegisters));
1.1.1.9 root 141: LastStrobe=0;
1.1 root 142: }
143:
1.1.1.2 root 144:
145: /*-----------------------------------------------------------------------*/
1.1.1.7 root 146: /**
147: * Save/Restore snapshot of local variables ('MemorySnapShot_Store' handles type)
148: */
1.1.1.9 root 149: void PSG_MemorySnapShot_Capture(bool bSave)
1.1 root 150: {
1.1.1.4 root 151: /* Save/Restore details */
152: MemorySnapShot_Store(&PSGRegisterSelect, sizeof(PSGRegisterSelect));
153: MemorySnapShot_Store(PSGRegisters, sizeof(PSGRegisters));
1.1.1.9 root 154: MemorySnapShot_Store(&LastStrobe, sizeof(LastStrobe));
1.1 root 155: }
156:
1.1.1.2 root 157:
158: /*-----------------------------------------------------------------------*/
1.1.1.7 root 159: /**
1.1.1.10 root 160: * Write byte to the YM address register (usually 0xff8800). This is used
161: * as a selector for when we read/write the YM data register (0xff8802).
1.1.1.7 root 162: */
1.1.1.10 root 163: void PSG_Set_SelectRegister(Uint8 val)
1.1 root 164: {
1.1.1.9 root 165: /* Store register used to read/write in $ff8802. This register */
166: /* is 8 bits on the YM2149, this means it should not be masked */
167: /* with 0xf. Instead, we keep the 8 bits, but we must ignore */
168: /* read/write to ff8802 when PSGRegisterSelect >= 16 */
1.1.1.10 root 169: PSGRegisterSelect = val;
1.1.1.7 root 170:
1.1.1.11 root 171: if (LOG_TRACE_LEVEL(TRACE_PSG_WRITE))
172: {
173: int FrameCycles, HblCounterVideo, LineCycles;
174: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
175: LOG_TRACE_PRINT("ym write reg=0x%x video_cyc=%d %d@%d pc=%x instr_cycle %d\n",
176: PSGRegisterSelect, FrameCycles, LineCycles, HblCounterVideo,
177: M68000_GetPC(), CurrentInstrCycles);
178: }
1.1 root 179: }
180:
1.1.1.2 root 181:
182: /*-----------------------------------------------------------------------*/
1.1.1.7 root 183: /**
1.1.1.10 root 184: * Read byte from 0xff8800, return PSG data
1.1.1.7 root 185: */
1.1.1.10 root 186: Uint8 PSG_Get_DataRegister(void)
1.1 root 187: {
1.1.1.9 root 188: /* Is a valid PSG register currently selected ? */
189: if ( PSGRegisterSelect >= 16 )
1.1.1.10 root 190: return 0xff; /* not valid, return 0xff */
1.1.1.9 root 191:
1.1.1.5 root 192: if (PSGRegisterSelect == 14)
193: {
194: /* Second parallel port joystick uses centronics strobe bit as fire button: */
195: if (ConfigureParams.Joysticks.Joy[JOYID_PARPORT2].nJoystickMode != JOYSTICK_DISABLED)
196: {
197: if (Joy_GetStickData(JOYID_PARPORT2) & 0x80)
198: PSGRegisters[14] &= ~32;
199: else
200: PSGRegisters[14] |= 32;
201: }
202: }
203: else if (PSGRegisterSelect == 15)
204: {
205: /* PSG register 15 is parallel port data register - used by parallel port joysticks: */
206: if (ConfigureParams.Joysticks.Joy[JOYID_PARPORT1].nJoystickMode != JOYSTICK_DISABLED)
207: {
208: PSGRegisters[15] &= 0x0f;
209: PSGRegisters[15] |= ~Joy_GetStickData(JOYID_PARPORT1) << 4;
210: }
211: if (ConfigureParams.Joysticks.Joy[JOYID_PARPORT2].nJoystickMode != JOYSTICK_DISABLED)
212: {
213: PSGRegisters[15] &= 0xf0;
214: PSGRegisters[15] |= ~Joy_GetStickData(JOYID_PARPORT2) & 0x0f;
215: }
216: }
217:
1.1.1.4 root 218: /* Read data last selected by register */
1.1.1.10 root 219: return PSGRegisters[PSGRegisterSelect];
1.1 root 220: }
221:
1.1.1.2 root 222:
223: /*-----------------------------------------------------------------------*/
1.1.1.7 root 224: /**
1.1.1.10 root 225: * Write byte to YM's register (0xff8802), store according to PSG select register (0xff8800)
1.1.1.7 root 226: */
1.1.1.10 root 227: void PSG_Set_DataRegister(Uint8 val)
1.1.1.4 root 228: {
1.1.1.11 root 229: if (LOG_TRACE_LEVEL(TRACE_PSG_WRITE))
230: {
231: int FrameCycles, HblCounterVideo, LineCycles;
232: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
233: LOG_TRACE_PRINT("ym write data reg=0x%x val=0x%x video_cyc=%d %d@%d pc=%x instr_cycle %d\n",
234: PSGRegisterSelect, val, FrameCycles, LineCycles,
235: HblCounterVideo, M68000_GetPC(), CurrentInstrCycles);
236: }
1.1.1.9 root 237:
238: /* Is a valid PSG register currently selected ? */
239: if ( PSGRegisterSelect >= 16 )
240: return; /* not valid, ignore write and do nothing */
241:
1.1.1.8 root 242: /* Create samples up until this point with current values */
1.1.1.12! root 243: Sound_Update(false);
1.1.1.8 root 244:
1.1.1.10 root 245: /* Copy value to PSGRegisters[] */
246: PSGRegisters[PSGRegisterSelect] = val;
1.1.1.4 root 247:
1.1.1.9 root 248: /* Clear unused bits for some regs */
1.1.1.7 root 249: if ( ( PSGRegisterSelect == PSG_REG_CHANNEL_A_COARSE ) || ( PSGRegisterSelect == PSG_REG_CHANNEL_B_COARSE )
250: || ( PSGRegisterSelect == PSG_REG_CHANNEL_C_COARSE ) || ( PSGRegisterSelect == PSG_REG_ENV_SHAPE ) )
251: PSGRegisters[PSGRegisterSelect] &= 0x0f; /* only keep bits 0 - 3 */
252:
253: else if ( ( PSGRegisterSelect == PSG_REG_CHANNEL_A_AMP ) || ( PSGRegisterSelect == PSG_REG_CHANNEL_B_AMP )
1.1.1.9 root 254: || ( PSGRegisterSelect == PSG_REG_CHANNEL_C_AMP ) || ( PSGRegisterSelect == PSG_REG_NOISE_GENERATOR ) )
1.1.1.7 root 255: PSGRegisters[PSGRegisterSelect] &= 0x1f; /* only keep bits 0 - 4 */
256:
257:
258:
1.1.1.9 root 259: if ( PSGRegisterSelect < NUM_PSG_SOUND_REGISTERS )
1.1.1.4 root 260: {
1.1.1.9 root 261: /* Copy sound related registers 0..13 to the sound module's internal buffer */
262: Sound_WriteReg ( PSGRegisterSelect , PSGRegisters[PSGRegisterSelect] );
263: }
1.1.1.4 root 264:
1.1.1.9 root 265: else if ( PSGRegisterSelect == PSG_REG_IO_PORTA )
266: {
267: /*
268: * FIXME: This is only a prelimary dirty hack!
269: * Port B (Printer port) - writing here needs to be dispatched to the printer
270: * STROBE (Port A bit5) does a short LOW and back to HIGH when the char is valid
271: * To print you need to write the character byte to IOB and you need to toggle STROBE
272: * (like EmuTOS does).
273: */
1.1.1.4 root 274: /* Printer dispatching only when printing is activated */
275: if (ConfigureParams.Printer.bEnablePrinting)
276: {
1.1.1.9 root 277: /* Bit 5 - Centronics strobe? If STROBE is low and the LastStrobe was high,
278: then print/transfer to the emulated Centronics port.
1.1.1.7 root 279: */
1.1.1.9 root 280: if (LastStrobe && ( (PSGRegisters[PSG_REG_IO_PORTA]&(1<<5)) == 0 ))
1.1.1.4 root 281: {
282: /* Seems like we want to print something... */
1.1.1.9 root 283: Printer_TransferByteTo(PSGRegisters[PSG_REG_IO_PORTB]);
284: /* Initiate a possible GPIP0 Printer BUSY interrupt */
285: MFP_InputOnChannel(MFP_GPIP_0_BIT,MFP_IERB,&MFP_IPRB);
286: /* Initiate a possible GPIP1 Falcon ACK interrupt */
287: if (ConfigureParams.System.nMachineType == MACHINE_FALCON)
288: MFP_InputOnChannel(MFP_GPIP_1_BIT,MFP_IERB,&MFP_IPRB);
1.1.1.4 root 289: }
290: }
1.1.1.9 root 291: LastStrobe = PSGRegisters[PSG_REG_IO_PORTA]&(1<<5);
292:
293: /* Bit 0-2 : side and drive select */
294: if ( (PSGRegisters[PSG_REG_IO_PORTA]&(1<<1)) == 0 )
295: {
296: /* floppy drive A is ON */
1.1.1.11 root 297: Statusbar_SetFloppyLed(DRIVE_LED_A, true);
1.1.1.9 root 298: }
299: else
300: {
1.1.1.11 root 301: Statusbar_SetFloppyLed(DRIVE_LED_A, false);
1.1.1.9 root 302: }
303: if ( (PSGRegisters[PSG_REG_IO_PORTA]&(1<<2)) == 0 )
304: {
305: /* floppy drive B is ON */
1.1.1.11 root 306: Statusbar_SetFloppyLed(DRIVE_LED_B, true);
1.1.1.9 root 307: }
308: else
309: {
1.1.1.11 root 310: Statusbar_SetFloppyLed(DRIVE_LED_B, false);
1.1.1.9 root 311: }
312:
1.1.1.7 root 313: /* Bit 3 - Centronics as input */
314: if(PSGRegisters[PSG_REG_IO_PORTA]&(1<<3))
315: {
316: /* FIXME: might be needed if we want to emulate sound sampling hardware */
317: }
318:
319: /* handle Falcon specific bits in PORTA of the PSG */
320: if (ConfigureParams.System.nMachineType == MACHINE_FALCON)
321: {
322: /* Bit 4 - DSP reset? */
323: if(PSGRegisters[PSG_REG_IO_PORTA]&(1<<4))
324: {
325: Log_Printf(LOG_DEBUG, "Calling DSP_Reset?\n");
326: #if ENABLE_DSP_EMU
327: if (ConfigureParams.System.nDSPType == DSP_TYPE_EMU) {
328: DSP_Reset();
329: }
330: #endif
331: }
332: /* Bit 6 - Internal Speaker control */
333: if(PSGRegisters[PSG_REG_IO_PORTA]&(1<<6))
334: {
335: /*Log_Printf(LOG_DEBUG, "Falcon: Internal Speaker state\n");*/
336: /* FIXME: add code to handle? (if we want to emulate the speaker at all? */
337: }
338: /* Bit 7 - Reset IDE? */
339: if(PSGRegisters[PSG_REG_IO_PORTA]&(1<<7))
340: {
341: Log_Printf(LOG_DEBUG, "Falcon: Reset IDE subsystem\n");
342: /* FIXME: add code to handle IDE reset */
343: }
344: }
1.1.1.9 root 345:
1.1.1.4 root 346: }
1.1 root 347: }
348:
1.1.1.2 root 349:
350: /*-----------------------------------------------------------------------*/
1.1.1.7 root 351: /**
1.1.1.10 root 352: * Read byte from 0xff8800. Return current content of data register
1.1.1.7 root 353: */
1.1.1.10 root 354: void PSG_ff8800_ReadByte(void)
1.1 root 355: {
1.1.1.10 root 356: M68000_WaitState(1); /* [NP] FIXME not 100% accurate, but gives good results */
357:
358: IoMem[IoAccessCurrentAddress] = PSG_Get_DataRegister();
359:
1.1.1.11 root 360: if (LOG_TRACE_LEVEL(TRACE_PSG_READ))
361: {
362: int FrameCycles, HblCounterVideo, LineCycles;
363: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
364: LOG_TRACE_PRINT("ym read data %x=0x%x video_cyc=%d %d@%d pc=%x instr_cycle %d\n",
365: IoAccessCurrentAddress, IoMem[IoAccessCurrentAddress],
366: FrameCycles, LineCycles, HblCounterVideo, M68000_GetPC(), CurrentInstrCycles);
367: }
1.1.1.10 root 368: }
369:
370:
371: /*-----------------------------------------------------------------------*/
372: /**
373: * Read byte from 0xff8801/02/03. Return 0xff.
374: */
375: void PSG_ff880x_ReadByte(void)
376: {
377: M68000_WaitState(1); /* [NP] FIXME not 100% accurate, but gives good results */
1.1.1.4 root 378:
1.1.1.8 root 379: IoMem[IoAccessCurrentAddress] = 0xff;
1.1.1.10 root 380:
1.1.1.11 root 381: if (LOG_TRACE_LEVEL(TRACE_PSG_READ))
382: {
383: int FrameCycles, HblCounterVideo, LineCycles;
384: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
385: LOG_TRACE_PRINT("ym read void %x=0x%x video_cyc=%d %d@%d pc=%x instr_cycle %d\n",
386: IoAccessCurrentAddress, IoMem[IoAccessCurrentAddress],
387: FrameCycles, LineCycles, HblCounterVideo, M68000_GetPC(), CurrentInstrCycles);
388: }
1.1 root 389: }
1.1.1.7 root 390:
391:
392:
393: /*-----------------------------------------------------------------------*/
394: /**
1.1.1.10 root 395: * Write byte to 0xff8800. Set content of YM's address register.
1.1.1.7 root 396: */
1.1.1.10 root 397: void PSG_ff8800_WriteByte(void)
1.1.1.7 root 398: {
1.1.1.10 root 399: // M68000_WaitState(4);
400: M68000_WaitState(1); /* [NP] FIXME not 100% accurate, but gives good results */
1.1.1.7 root 401:
1.1.1.11 root 402: if (LOG_TRACE_LEVEL(TRACE_PSG_WRITE))
403: {
404: int FrameCycles, HblCounterVideo, LineCycles;
405: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
406: LOG_TRACE_PRINT("ym write %x=0x%x video_cyc=%d %d@%d pc=%x instr_cycle %d\n",
407: IoAccessCurrentAddress, IoMem[IoAccessCurrentAddress],
408: FrameCycles, LineCycles, HblCounterVideo, M68000_GetPC(), CurrentInstrCycles);
409: }
1.1.1.10 root 410:
411: PSG_Set_SelectRegister ( IoMem[IoAccessCurrentAddress] );
412: }
413:
414:
415: /*-----------------------------------------------------------------------*/
416: /**
417: * Write byte to 0xff8801. Set content of YM's address register under conditions.
418: * Address 0xff8801 is a shadow version of 0xff8800, so both addresses can't be written
419: * at the same time by the same instruction. This means only a .B access or
420: * a movep will have a valid effect, other accesses are ignored.
421: */
422: void PSG_ff8801_WriteByte(void)
423: {
424: if ( nIoMemAccessSize == SIZE_BYTE ) /* byte access or movep */
425: {
426: M68000_WaitState(1); /* [NP] FIXME not 100% accurate, but gives good results */
427:
1.1.1.11 root 428: if (LOG_TRACE_LEVEL(TRACE_PSG_WRITE))
429: {
430: int FrameCycles, HblCounterVideo, LineCycles;
431: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
432: LOG_TRACE_PRINT("ym write %x=0x%x video_cyc=%d %d@%d pc=%x instr_cycle %d\n",
433: IoAccessCurrentAddress, IoMem[IoAccessCurrentAddress],
434: FrameCycles, LineCycles, HblCounterVideo, M68000_GetPC(), CurrentInstrCycles);
435: }
1.1.1.10 root 436:
437: PSG_Set_SelectRegister ( IoMem[IoAccessCurrentAddress] );
438: }
439:
440: else
441: { /* do nothing, just a trace if needed */
1.1.1.11 root 442: if (LOG_TRACE_LEVEL(TRACE_PSG_WRITE))
443: {
444: int FrameCycles, HblCounterVideo, LineCycles;
445: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
446: LOG_TRACE_PRINT("ym write ignored %x=0x%x video_cyc=%d %d@%d pc=%x instr_cycle %d\n",
447: IoAccessCurrentAddress, IoMem[IoAccessCurrentAddress],
448: FrameCycles, LineCycles, HblCounterVideo, M68000_GetPC(), CurrentInstrCycles);
449: }
1.1.1.10 root 450: }
1.1.1.7 root 451: }
452:
453:
1.1.1.10 root 454: /*-----------------------------------------------------------------------*/
455: /**
456: * Write byte to 0xff8802. Set content of YM's data register.
457: */
458: void PSG_ff8802_WriteByte(void)
459: {
460: // M68000_WaitState(4);
461: M68000_WaitState(1); /* [NP] FIXME not 100% accurate, but gives good results */
462:
1.1.1.11 root 463: if (LOG_TRACE_LEVEL(TRACE_PSG_WRITE))
464: {
465: int FrameCycles, HblCounterVideo, LineCycles;
466: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
467: LOG_TRACE_PRINT("ym write %x=0x%x video_cyc=%d %d@%d pc=%x instr_cycle %d\n",
468: IoAccessCurrentAddress, IoMem[IoAccessCurrentAddress],
469: FrameCycles, LineCycles, HblCounterVideo, M68000_GetPC(), CurrentInstrCycles);
470: }
1.1.1.10 root 471:
472: PSG_Set_DataRegister ( IoMem[IoAccessCurrentAddress] );
473: }
474:
1.1.1.7 root 475:
476: /*-----------------------------------------------------------------------*/
477: /**
1.1.1.10 root 478: * Write byte to 0xff8803. Set content of YM's data register under conditions.
479: * Address 0xff8803 is a shadow version of 0xff8802, so both addresses can't be written
480: * at the same time by the same instruction. This means only a .B access or
481: * a movep will have a valid effect, other accesses are ignored.
1.1.1.7 root 482: */
1.1.1.10 root 483: void PSG_ff8803_WriteByte(void)
1.1.1.7 root 484: {
1.1.1.10 root 485: if ( nIoMemAccessSize == SIZE_BYTE ) /* byte access or movep */
486: {
487: M68000_WaitState(1); /* [NP] FIXME not 100% accurate, but gives good results */
488:
1.1.1.11 root 489: if (LOG_TRACE_LEVEL(TRACE_PSG_WRITE))
490: {
491: int FrameCycles, HblCounterVideo, LineCycles;
492: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
493: LOG_TRACE_PRINT("ym write %x=0x%x video_cyc=%d %d@%d pc=%x instr_cycle %d\n",
494: IoAccessCurrentAddress, IoMem[IoAccessCurrentAddress],
495: FrameCycles, LineCycles, HblCounterVideo, M68000_GetPC(), CurrentInstrCycles);
496: }
1.1.1.10 root 497:
498: PSG_Set_DataRegister ( IoMem[IoAccessCurrentAddress] );
499: }
500:
501: else
502: { /* do nothing, just a trace if needed */
1.1.1.11 root 503: if (LOG_TRACE_LEVEL(TRACE_PSG_WRITE))
504: {
505: int FrameCycles, HblCounterVideo, LineCycles;
506: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
507: LOG_TRACE_PRINT("ym write ignored %x=0x%x video_cyc=%d %d@%d pc=%x instr_cycle %d\n",
508: IoAccessCurrentAddress, IoMem[IoAccessCurrentAddress],
509: FrameCycles, LineCycles, HblCounterVideo, M68000_GetPC(), CurrentInstrCycles);
510: }
1.1.1.10 root 511: }
1.1.1.7 root 512: }
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