--- hatari/src/uae-cpu/fpp.c	2019/04/01 07:09:16	1.1.1.1
+++ hatari/src/uae-cpu/fpp.c	2019/04/01 07:15:37	1.1.1.8
@@ -4,29 +4,104 @@
   * MC68881 emulation
   *
   * Copyright 1996 Herman ten Brugge
+  *
+  * Adaptation to Hatari by Thomas Huth
+  *
+  * This file is distributed under the GNU Public License, version 2 or at
+  * your option any later version. Read the file gpl.txt for details.
   */
+const char FPP_rcsid[] = "Hatari $Id: fpp.c,v 1.1.1.8 2019/04/01 07:15:37 root Exp $";
 
+
+#define __USE_ISOC9X  /* We might be able to pick up a NaN */
 #include <math.h>
 
 #include "sysdeps.h"
 #include "hatari-glue.h"
-#include "maccess.h"
 #include "memory.h"
 #include "newcpu.h"
-#include "fpp-unknown.h"
+#include "savestate.h"
+
+#if defined(powerpc) || defined(__mc68020__)
+# include "fpp-ieee-be.h"
+#else
+# include "fpp-unknown.h"
+#endif
 
-/*
-#include "sysconfig.h"
-#include "config.h"
-#include "options.h"
-#include "custom.h"
-*/
 
 #if 1
 
 #define	DEBUG_FPP	0
 
-#define MAKE_FPSR(fpsr,r) (fpsr) = ((fpsr) & 0x00FFFFFF) | ((r) == 0 ? 0x4000000 : 0) | ((r) < 0 ? 0x8000000 : 0)
+#define FFLAG_Z   0x4000
+#define FFLAG_N   0x0100
+#define FFLAG_NAN 0x0400 
+
+#define MAKE_FPSR(r)  regs.fp_result=(r)
+
+static __inline__ void native_set_fpucw (uae_u32 m68k_cw)
+{
+}
+
+#if defined(uae_s64) /* Close enough for government work? */
+static __inline__ uae_s64 toint(fptype src)
+#else
+static __inline__ uae_s32 toint(fptype src)
+#endif
+{
+    switch ((regs.fpcr >> 4) & 0x3) {
+    case 0:
+	return (int) (src + 0.5);
+    case 1:
+	return (int) src;
+    case 2:
+	return floor (src);
+    case 3:
+	return ceil (src);
+    }
+    return src; /* Should never be reached */
+}
+
+static uae_u32 get_fpsr (void) 
+{
+    uae_u32 answer = regs.fpsr & 0x00ffffff;
+#ifdef HAVE_ISNAN
+    if (isnan (regs.fp_result))
+	answer |= 0x01000000;
+    else
+#endif
+    {
+	if (regs.fp_result == 0)
+	    answer |= 0x04000000;
+	else if (regs.fp_result < 0)
+	    answer |= 0x08000000;
+#ifdef HAVE_ISINF
+	if (isinf (regs.fp_result))
+	    answer |= 0x02000000;
+#endif
+    }
+    return answer;
+}
+
+STATIC_INLINE void set_fpsr (uae_u32 x) 
+{
+    regs.fpsr = x;
+
+    if (x & 0x01000000) {
+#ifdef NAN
+	regs.fp_result = NAN;
+#else
+	regs.fp_result = pow (1e100, 10) - pow(1e100, 10);  /* Any better way? */
+#endif
+    }
+    else if (x & 0x04000000)
+	regs.fp_result = 0;
+    else if (x & 0x08000000)
+	regs.fp_result = -1;
+    else
+	regs.fp_result = 1;
+}
+
 
 /* single   : S  8*E 23*F */
 /* double   : S 11*E 52*F */
@@ -36,9 +111,9 @@
 /* E = MAX & F # 0 -> NotANumber */
 /* E = biased by 127 (single) ,1023 (double) ,16383 (extended) */
 
-STATIC_INLINE double to_pack (uae_u32 wrd1, uae_u32 wrd2, uae_u32 wrd3)
+STATIC_INLINE fptype to_pack (uae_u32 wrd1, uae_u32 wrd2, uae_u32 wrd3)
 {
-    double d;
+    fptype d;
     char *cp;
     char str[100];
 
@@ -74,7 +149,7 @@ STATIC_INLINE double to_pack (uae_u32 wr
     return d;
 }
 
-STATIC_INLINE void from_pack (double src, uae_u32 * wrd1, uae_u32 * wrd2, uae_u32 * wrd3)
+STATIC_INLINE void from_pack (fptype src, uae_u32 * wrd1, uae_u32 * wrd2, uae_u32 * wrd3)
 {
     int i;
     int t;
@@ -120,7 +195,7 @@ STATIC_INLINE void from_pack (double src
     }
 }
 
-STATIC_INLINE int get_fp_value (uae_u32 opcode, uae_u16 extra, double *src)
+STATIC_INLINE int get_fp_value (uae_u32 opcode, uae_u16 extra, fptype *src)
 {
     uaecptr tmppc;
     uae_u16 tmp;
@@ -128,8 +203,8 @@ STATIC_INLINE int get_fp_value (uae_u32
     int mode;
     int reg;
     uae_u32 ad = 0;
-    static int sz1[8] = { 4, 4, 12, 12, 2, 8, 1, 0 };
-    static int sz2[8] = { 4, 4, 12, 12, 2, 8, 2, 0 };
+    static const int sz1[8] = { 4, 4, 12, 12, 2, 8, 1, 0 };
+    static const int sz2[8] = { 4, 4, 12, 12, 2, 8, 2, 0 };
 
     if ((extra & 0x4000) == 0) {
 	*src = regs.fp[(extra >> 10) & 7];
@@ -142,13 +217,13 @@ STATIC_INLINE int get_fp_value (uae_u32
     case 0:
 	switch (size) {
 	case 6:
-	    *src = (double) (uae_s8) m68k_dreg (regs, reg);
+	    *src = (fptype) (uae_s8) m68k_dreg (regs, reg);
 	    break;
 	case 4:
-	    *src = (double) (uae_s16) m68k_dreg (regs, reg);
+	    *src = (fptype) (uae_s16) m68k_dreg (regs, reg);
 	    break;
 	case 0:
-	    *src = (double) (uae_s32) m68k_dreg (regs, reg);
+	    *src = (fptype) (uae_s32) m68k_dreg (regs, reg);
 	    break;
 	case 1:
 	    *src = to_single (m68k_dreg (regs, reg));
@@ -203,7 +278,7 @@ STATIC_INLINE int get_fp_value (uae_u32
     }
     switch (size) {
     case 0:
-	*src = (double) (uae_s32) get_long (ad);
+	*src = (fptype) (uae_s32) get_long (ad);
 	break;
     case 1:
 	*src = to_single (get_long (ad));
@@ -229,7 +304,7 @@ STATIC_INLINE int get_fp_value (uae_u32
 	}
 	break;
     case 4:
-	*src = (double) (uae_s16) get_word (ad);
+	*src = (fptype) (uae_s16) get_word (ad);
 	break;
     case 5:{
 	    uae_u32 wrd1, wrd2;
@@ -240,7 +315,7 @@ STATIC_INLINE int get_fp_value (uae_u32
 	}
 	break;
     case 6:
-	*src = (double) (uae_s8) get_byte (ad);
+	*src = (fptype) (uae_s8) get_byte (ad);
 	break;
     default:
 	return 0;
@@ -248,7 +323,7 @@ STATIC_INLINE int get_fp_value (uae_u32
     return 1;
 }
 
-STATIC_INLINE int put_fp_value (double value, uae_u32 opcode, uae_u16 extra)
+STATIC_INLINE int put_fp_value (fptype value, uae_u32 opcode, uae_u16 extra)
 {
     uae_u16 tmp;
     uaecptr tmppc;
@@ -256,8 +331,8 @@ STATIC_INLINE int put_fp_value (double v
     int mode;
     int reg;
     uae_u32 ad;
-    static int sz1[8] = { 4, 4, 12, 12, 2, 8, 1, 0 };
-    static int sz2[8] = { 4, 4, 12, 12, 2, 8, 2, 0 };
+    static const int sz1[8] = { 4, 4, 12, 12, 2, 8, 1, 0 };
+    static const int sz2[8] = { 4, 4, 12, 12, 2, 8, 2, 0 };
 
     if ((extra & 0x4000) == 0) {
 	regs.fp[(extra >> 10) & 7] = value;
@@ -267,19 +342,20 @@ STATIC_INLINE int put_fp_value (double v
     reg = opcode & 7;
     size = (extra >> 10) & 7;
     ad = -1;
+    
     switch (mode) {
     case 0:
 	switch (size) {
 	case 6:
-	    m68k_dreg (regs, reg) = (((int) value & 0xff)
+	    m68k_dreg (regs, reg) = ((toint(value) & 0xff)
 				     | (m68k_dreg (regs, reg) & ~0xff));
 	    break;
 	case 4:
-	    m68k_dreg (regs, reg) = (((int) value & 0xffff)
+	    m68k_dreg (regs, reg) = ((toint(value) & 0xffff)
 				     | (m68k_dreg (regs, reg) & ~0xffff));
 	    break;
 	case 0:
-	    m68k_dreg (regs, reg) = (int) value;
+	    m68k_dreg (regs, reg) = toint(value);
 	    break;
 	case 1:
 	    m68k_dreg (regs, reg) = from_single (value);
@@ -334,7 +410,7 @@ STATIC_INLINE int put_fp_value (double v
     }
     switch (size) {
     case 0:
-	put_long (ad, (uae_s32) value);
+	put_long (ad,toint(value));
 	break;
     case 1:
 	put_long (ad, from_single (value));
@@ -362,7 +438,7 @@ STATIC_INLINE int put_fp_value (double v
 	}
 	break;
     case 4:
-	put_word (ad, (uae_s16) value);
+	put_word (ad, (uae_s16) toint(value));
 	break;
     case 5:{
 	    uae_u32 wrd1, wrd2;
@@ -373,7 +449,7 @@ STATIC_INLINE int put_fp_value (double v
 	}
 	break;
     case 6:
-	put_byte (ad, (uae_s8) value);
+	put_byte (ad, (uae_s8)toint(value));
 	break;
     default:
 	return 0;
@@ -435,10 +511,17 @@ STATIC_INLINE int get_fp_ad (uae_u32 opc
 
 STATIC_INLINE int fpp_cond (uae_u32 opcode, int contition)
 {
-    int N = (regs.fpsr & 0x8000000) != 0;
-    int Z = (regs.fpsr & 0x4000000) != 0;
+    int N = (regs.fp_result<0);
+    int Z = (regs.fp_result==0);
     /* int I = (regs.fpsr & 0x2000000) != 0; */
-    int NotANumber = (regs.fpsr & 0x1000000) != 0;
+    int NotANumber = 0;
+
+#ifdef HAVE_ISNAN
+    NotANumber = isnan (regs.fp_result);
+#endif
+
+    if (NotANumber)
+	N=Z=0;
 
     switch (contition) {
     case 0x00:
@@ -498,7 +581,11 @@ STATIC_INLINE int fpp_cond (uae_u32 opco
     case 0x1b:
 	return NotANumber || Z || !N;
     case 0x1c:
-	return NotANumber || (Z && N);
+#if 0
+        return NotANumber || (Z && N); /* This is wrong, compare 0x0c */
+#else
+        return NotANumber || (N && !Z);  
+#endif
     case 0x1d:
 	return NotANumber || Z || N;
     case 0x1e:
@@ -535,7 +622,7 @@ void fdbcc_opp (uae_u32 opcode, uae_u16
 
 void fscc_opp (uae_u32 opcode, uae_u16 extra)
 {
-    uae_u32 ad;
+    uae_u32 ad = 0;
     int cc;
 
 #if DEBUG_FPP
@@ -571,7 +658,7 @@ void ftrapcc_opp (uae_u32 opcode, uaecpt
 	op_illg (opcode);
     }
     if (cc)
-	Exception (7, oldpc - 2);
+	Exception (7, oldpc - 2, M68000_EXCEPTION_SRC_CPU);
 }
 
 void fbcc_opp (uae_u32 opcode, uaecptr pc, uae_u32 extra)
@@ -595,7 +682,7 @@ void fbcc_opp (uae_u32 opcode, uaecptr p
 
 void fsave_opp (uae_u32 opcode)
 {
-    uae_u32 ad;
+    uae_u32 ad = 0;
     int incr = (opcode & 0x38) == 0x20 ? -1 : 1;
     int i;
 
@@ -609,7 +696,7 @@ void fsave_opp (uae_u32 opcode)
 	return;
     }
 
-    if (cpu_level == 4) {
+    if (currprefs.cpu_level == 4) {
 	/* 4 byte 68040 IDLE frame.  */
 	if (incr < 0) {
 	    ad -= 4;
@@ -647,7 +734,7 @@ void fsave_opp (uae_u32 opcode)
 
 void frestore_opp (uae_u32 opcode)
 {
-    uae_u32 ad;
+    uae_u32 ad = 0;
     uae_u32 d;
     int incr = (opcode & 0x38) == 0x20 ? -1 : 1;
 
@@ -660,7 +747,7 @@ void frestore_opp (uae_u32 opcode)
 	op_illg (opcode);
 	return;
     }
-    if (cpu_level == 4) {
+    if (currprefs.cpu_level == 4) {
 	/* 68040 */
 	if (incr < 0) {
 	    /* @@@ This may be wrong.  */
@@ -720,7 +807,7 @@ void frestore_opp (uae_u32 opcode)
 void fpp_opp (uae_u32 opcode, uae_u16 extra)
 {
     int reg;
-    double src;
+    fptype src;
 
 #if DEBUG_FPP
     printf ("FPP %04lx %04x at %08lx\n", opcode & 0xffff, extra & 0xffff, m68k_getpc () - 4);
@@ -740,45 +827,51 @@ void fpp_opp (uae_u32 opcode, uae_u16 ex
 		if (extra & 0x1000)
 		    m68k_dreg (regs, opcode & 7) = regs.fpcr;
 		if (extra & 0x0800)
-		    m68k_dreg (regs, opcode & 7) = regs.fpsr;
+		    m68k_dreg (regs, opcode & 7) = get_fpsr ();
 		if (extra & 0x0400)
 		    m68k_dreg (regs, opcode & 7) = regs.fpiar;
 	    } else {
-		if (extra & 0x1000)
+		if (extra & 0x1000) {
 		    regs.fpcr = m68k_dreg (regs, opcode & 7);
+		    native_set_fpucw (regs.fpcr);
+		}
 		if (extra & 0x0800)
-		    regs.fpsr = m68k_dreg (regs, opcode & 7);
+		    set_fpsr (m68k_dreg (regs, opcode & 7));
 		if (extra & 0x0400)
 		    regs.fpiar = m68k_dreg (regs, opcode & 7);
 	    }
-	} else if ((opcode & 0x38) == 1) {
+	} else if ((opcode & 0x38) == 0x08) {
 	    if (extra & 0x2000) {
 		if (extra & 0x1000)
 		    m68k_areg (regs, opcode & 7) = regs.fpcr;
 		if (extra & 0x0800)
-		    m68k_areg (regs, opcode & 7) = regs.fpsr;
+		    m68k_areg (regs, opcode & 7) = get_fpsr ();
 		if (extra & 0x0400)
 		    m68k_areg (regs, opcode & 7) = regs.fpiar;
 	    } else {
-		if (extra & 0x1000)
+		if (extra & 0x1000) {
 		    regs.fpcr = m68k_areg (regs, opcode & 7);
+		    native_set_fpucw (regs.fpcr);
+		}
 		if (extra & 0x0800)
-		    regs.fpsr = m68k_areg (regs, opcode & 7);
+		    set_fpsr (m68k_areg (regs, opcode & 7));
 		if (extra & 0x0400)
 		    regs.fpiar = m68k_areg (regs, opcode & 7);
 	    }
 	} else if ((opcode & 0x3f) == 0x3c) {
 	    if ((extra & 0x2000) == 0) {
-		if (extra & 0x1000)
+		if (extra & 0x1000) {
 		    regs.fpcr = next_ilong ();
+		    native_set_fpucw (regs.fpcr);
+		}
 		if (extra & 0x0800)
-		    regs.fpsr = next_ilong ();
+		    set_fpsr (next_ilong ());
 		if (extra & 0x0400)
 		    regs.fpiar = next_ilong ();
 	    }
 	} else if (extra & 0x2000) {
 	    /* FMOVEM FPP->memory */
-	    uae_u32 ad;
+	    uae_u32 ad = 0;
 	    int incr = 0;
 
 	    if (get_fp_ad (opcode, &ad) == 0) {
@@ -800,7 +893,7 @@ void fpp_opp (uae_u32 opcode, uae_u16 ex
 		ad += 4;
 	    }
 	    if (extra & 0x0800) {
-		put_long (ad, regs.fpsr);
+		put_long (ad, get_fpsr());
 		ad += 4;
 	    }
 	    if (extra & 0x0400) {
@@ -814,7 +907,7 @@ void fpp_opp (uae_u32 opcode, uae_u16 ex
 		m68k_areg (regs, opcode & 7) = ad;
 	} else {
 	    /* FMOVEM memory->FPP */
-	    uae_u32 ad;
+	    uae_u32 ad = 0;
 
 	    if (get_fp_ad (opcode, &ad) == 0) {
 		m68k_setpc (m68k_getpc () - 4);
@@ -824,10 +917,11 @@ void fpp_opp (uae_u32 opcode, uae_u16 ex
 	    ad = (opcode & 0x38) == 0x20 ? ad - 12 : ad;
 	    if (extra & 0x1000) {
 		regs.fpcr = get_long (ad);
+		native_set_fpucw(regs.fpcr);
 		ad += 4;
 	    }
 	    if (extra & 0x0800) {
-		regs.fpsr = get_long (ad);
+		set_fpsr(get_long (ad));
 		ad += 4;
 	    }
 	    if (extra & 0x0400) {
@@ -842,114 +936,115 @@ void fpp_opp (uae_u32 opcode, uae_u16 ex
 	return;
     case 6:
     case 7:
-	{
-	    uae_u32 ad, list = 0;
-	    int incr = 0;
-	    if (extra & 0x2000) {
-		/* FMOVEM FPP->memory */
-		if (get_fp_ad (opcode, &ad) == 0) {
-		    m68k_setpc (m68k_getpc () - 4);
-		    op_illg (opcode);
-		    return;
-		}
-		switch ((extra >> 11) & 3) {
-		case 0:	/* static pred */
-		    list = extra & 0xff;
-		    incr = -1;
-		    break;
-		case 1:	/* dynamic pred */
-		    list = m68k_dreg (regs, (extra >> 4) & 3) & 0xff;
-		    incr = -1;
-		    break;
-		case 2:	/* static postinc */
-		    list = extra & 0xff;
-		    incr = 1;
-		    break;
-		case 3:	/* dynamic postinc */
-		    list = m68k_dreg (regs, (extra >> 4) & 3) & 0xff;
-		    incr = 1;
-		    break;
-		}
-		while (list) {
-		    uae_u32 wrd1, wrd2, wrd3;
-		    if (incr < 0) {
-			from_exten (regs.fp[fpp_movem_index2[list]], &wrd1, &wrd2, &wrd3);
-			ad -= 4;
-			put_long (ad, wrd3);
-			ad -= 4;
-			put_long (ad, wrd2);
-			ad -= 4;
-			put_long (ad, wrd1);
-		    } else {
-			from_exten (regs.fp[fpp_movem_index1[list]], &wrd1, &wrd2, &wrd3);
-			put_long (ad, wrd1);
-			ad += 4;
-			put_long (ad, wrd2);
-			ad += 4;
-			put_long (ad, wrd3);
-			ad += 4;
-		    }
-		    list = fpp_movem_next[list];
-		}
-		if ((opcode & 0x38) == 0x18)
-		    m68k_areg (regs, opcode & 7) = ad;
-		if ((opcode & 0x38) == 0x20)
-		    m68k_areg (regs, opcode & 7) = ad;
-	    } else {
-		/* FMOVEM memory->FPP */
-		if (get_fp_ad (opcode, &ad) == 0) {
-		    m68k_setpc (m68k_getpc () - 4);
-		    op_illg (opcode);
-		    return;
-		}
-		switch ((extra >> 11) & 3) {
-		case 0:	/* static pred */
-		    list = extra & 0xff;
-		    incr = -1;
-		    break;
-		case 1:	/* dynamic pred */
-		    list = m68k_dreg (regs, (extra >> 4) & 3) & 0xff;
-		    incr = -1;
-		    break;
-		case 2:	/* static postinc */
-		    list = extra & 0xff;
-		    incr = 1;
-		    break;
-		case 3:	/* dynamic postinc */
-		    list = m68k_dreg (regs, (extra >> 4) & 3) & 0xff;
-		    incr = 1;
-		    break;
+    {
+	uae_u32 ad = 0;
+	uae_u32 list = 0;
+	int incr = 0;
+	if (extra & 0x2000) {
+	    /* FMOVEM FPP->memory */
+	    if (get_fp_ad (opcode, &ad) == 0) {
+		m68k_setpc (m68k_getpc () - 4);
+		op_illg (opcode);
+		return;
+	    }
+	    switch ((extra >> 11) & 3) {
+	    case 0:	/* static pred */
+		list = extra & 0xff;
+		incr = -1;
+		break;
+	    case 1:	/* dynamic pred */
+		list = m68k_dreg (regs, (extra >> 4) & 3) & 0xff;
+		incr = -1;
+		break;
+	    case 2:	/* static postinc */
+		list = extra & 0xff;
+		incr = 1;
+		break;
+	    case 3:	/* dynamic postinc */
+		list = m68k_dreg (regs, (extra >> 4) & 3) & 0xff;
+		incr = 1;
+		break;
+	    }
+	    while (list) {
+		uae_u32 wrd1, wrd2, wrd3;
+		if (incr < 0) {
+		    from_exten (regs.fp[fpp_movem_index2[list]], &wrd1, &wrd2, &wrd3);
+		    ad -= 4;
+		    put_long (ad, wrd3);
+		    ad -= 4;
+		    put_long (ad, wrd2);
+		    ad -= 4;
+		    put_long (ad, wrd1);
+		} else {
+		    from_exten (regs.fp[fpp_movem_index1[list]], &wrd1, &wrd2, &wrd3);
+		    put_long (ad, wrd1);
+		    ad += 4;
+		    put_long (ad, wrd2);
+		    ad += 4;
+		    put_long (ad, wrd3);
+		    ad += 4;
 		}
-		while (list) {
-		    uae_u32 wrd1, wrd2, wrd3;
-		    if (incr < 0) {
-			ad -= 4;
-			wrd3 = get_long (ad);
-			ad -= 4;
-			wrd2 = get_long (ad);
-			ad -= 4;
-			wrd1 = get_long (ad);
-			regs.fp[fpp_movem_index2[list]] = to_exten (wrd1, wrd2, wrd3);
-		    } else {
-			wrd1 = get_long (ad);
-			ad += 4;
-			wrd2 = get_long (ad);
-			ad += 4;
-			wrd3 = get_long (ad);
-			ad += 4;
-			regs.fp[fpp_movem_index1[list]] = to_exten (wrd1, wrd2, wrd3);
-		    }
-		    list = fpp_movem_next[list];
+		list = fpp_movem_next[list];
+	    }
+	    if ((opcode & 0x38) == 0x18)
+		m68k_areg (regs, opcode & 7) = ad;
+	    if ((opcode & 0x38) == 0x20)
+		m68k_areg (regs, opcode & 7) = ad;
+	} else {
+	    /* FMOVEM memory->FPP */
+	    if (get_fp_ad (opcode, &ad) == 0) {
+		m68k_setpc (m68k_getpc () - 4);
+		op_illg (opcode);
+		return;
+	    }
+	    switch ((extra >> 11) & 3) {
+	    case 0:	/* static pred */
+		list = extra & 0xff;
+		incr = -1;
+		break;
+	    case 1:	/* dynamic pred */
+		list = m68k_dreg (regs, (extra >> 4) & 3) & 0xff;
+		incr = -1;
+		break;
+	    case 2:	/* static postinc */
+		list = extra & 0xff;
+		incr = 1;
+		break;
+	    case 3:	/* dynamic postinc */
+		list = m68k_dreg (regs, (extra >> 4) & 3) & 0xff;
+		incr = 1;
+		break;
+	    }
+	    while (list) {
+		uae_u32 wrd1, wrd2, wrd3;
+		if (incr < 0) {
+		    ad -= 4;
+		    wrd3 = get_long (ad);
+		    ad -= 4;
+		    wrd2 = get_long (ad);
+		    ad -= 4;
+		    wrd1 = get_long (ad);
+		    regs.fp[fpp_movem_index2[list]] = to_exten (wrd1, wrd2, wrd3);
+		} else {
+		    wrd1 = get_long (ad);
+		    ad += 4;
+		    wrd2 = get_long (ad);
+		    ad += 4;
+		    wrd3 = get_long (ad);
+		    ad += 4;
+		    regs.fp[fpp_movem_index1[list]] = to_exten (wrd1, wrd2, wrd3);
 		}
-		if ((opcode & 0x38) == 0x18)
-		    m68k_areg (regs, opcode & 7) = ad;
-		if ((opcode & 0x38) == 0x20)
-		    m68k_areg (regs, opcode & 7) = ad;
+		list = fpp_movem_next[list];
 	    }
+	    if ((opcode & 0x38) == 0x18)
+		m68k_areg (regs, opcode & 7) = ad;
+	    if ((opcode & 0x38) == 0x20)
+		m68k_areg (regs, opcode & 7) = ad;
 	}
-	return;
+    }
+    return;
     case 0:
-    case 2:
+    case 2: /* Extremely common */
 	reg = (extra >> 7) & 7;
 	if ((extra & 0xfc00) == 0x5c00) {
 	    switch (extra & 0x7f) {
@@ -1035,60 +1130,56 @@ void fpp_opp (uae_u32 opcode, uae_u16 ex
 	}
 	switch (extra & 0x7f) {
 	case 0x00:		/* FMOVE */
+	case 0x40:  /* Explicit rounding. This is just a quick fix. Same
+		     * for all other cases that have three choices */
+	case 0x44:   
 	    regs.fp[reg] = src;
 	    /* Brian King was here.  <ea> to register needs FPSR updated.
 	     * See page 3-73 in Motorola 68K programmers reference manual.
 	     * %%%FPU */
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    if ((extra & 0x44) == 0x40)
+		regs.fp[reg] = (float)regs.fp[reg];
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x01:		/* FINT */
 	    /* need to take the current rounding mode into account */
-	    switch ((regs.fpcr >> 4) & 0x3) {
-	    case 0:
-		regs.fp[reg] = (int) (src + 0.5);
-		break;
-	    case 1:
-		regs.fp[reg] = (int) src;
-		break;
-	    case 2:
-		regs.fp[reg] = floor (src);
-		break;
-	    case 3:
-		regs.fp[reg] = ceil (src);
-		break;
-	    }
+ 	    regs.fp[reg] = toint(src);
 	    break;
 	case 0x02:		/* FSINH */
 	    regs.fp[reg] = sinh (src);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x03:		/* FINTRZ */
 	    regs.fp[reg] = (int) src;
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x04:		/* FSQRT */
+	case 0x41:
+	case 0x45:
 	    regs.fp[reg] = sqrt (src);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    if ((extra & 0x44) == 0x40)
+		regs.fp[reg] = (float)regs.fp[reg];
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x06:		/* FLOGNP1 */
 	    regs.fp[reg] = log (src + 1.0);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x08:		/* FETOXM1 */
 	    regs.fp[reg] = exp (src) - 1.0;
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x09:		/* FTANH */
 	    regs.fp[reg] = tanh (src);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x0a:		/* FATAN */
 	    regs.fp[reg] = atan (src);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x0c:		/* FASIN */
 	    regs.fp[reg] = asin (src);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x0d:		/* FATANH */
 #if 1				/* The BeBox doesn't have atanh, and it isn't in the HPUX libm either */
@@ -1096,110 +1187,134 @@ void fpp_opp (uae_u32 opcode, uae_u16 ex
 #else
 	    regs.fp[reg] = atanh (src);
 #endif
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x0e:		/* FSIN */
 	    regs.fp[reg] = sin (src);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x0f:		/* FTAN */
 	    regs.fp[reg] = tan (src);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x10:		/* FETOX */
 	    regs.fp[reg] = exp (src);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x11:		/* FTWOTOX */
 	    regs.fp[reg] = pow (2.0, src);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x12:		/* FTENTOX */
 	    regs.fp[reg] = pow (10.0, src);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x14:		/* FLOGN */
 	    regs.fp[reg] = log (src);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x15:		/* FLOG10 */
 	    regs.fp[reg] = log10 (src);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x16:		/* FLOG2 */
 	    regs.fp[reg] = log (src) / log (2.0);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x18:		/* FABS */
+	case 0x58:
+	case 0x5c:
 	    regs.fp[reg] = src < 0 ? -src : src;
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    if ((extra & 0x44) == 0x40)
+		regs.fp[reg] = (float)regs.fp[reg];
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x19:		/* FCOSH */
 	    regs.fp[reg] = cosh (src);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x1a:		/* FNEG */
+	case 0x5a:
+	case 0x5e:
 	    regs.fp[reg] = -src;
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    if ((extra & 0x44) == 0x40)
+		regs.fp[reg] = (float)regs.fp[reg];
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x1c:		/* FACOS */
 	    regs.fp[reg] = acos (src);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x1d:		/* FCOS */
 	    regs.fp[reg] = cos (src);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x1e:		/* FGETEXP */
-	    {
-		int expon;
-		frexp (src, &expon);
-		regs.fp[reg] = (double) (expon - 1);
-		MAKE_FPSR (regs.fpsr, regs.fp[reg]);
-	    }
-	    break;
+	{
+	    int expon;
+	    frexp (src, &expon);
+	    regs.fp[reg] = (double) (expon - 1);
+	    MAKE_FPSR (regs.fp[reg]);
+	}
+	break;
 	case 0x1f:		/* FGETMAN */
-	    {
-		int expon;
-		regs.fp[reg] = frexp (src, &expon) * 2.0;
-		MAKE_FPSR (regs.fpsr, regs.fp[reg]);
-	    }
-	    break;
+	{
+	    int expon;
+	    regs.fp[reg] = frexp (src, &expon) * 2.0;
+	    MAKE_FPSR (regs.fp[reg]);
+	}
+	break;
 	case 0x20:		/* FDIV */
+	case 0x60:
+	case 0x64:
 	    regs.fp[reg] /= src;
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    if ((extra & 0x44) == 0x40)
+		regs.fp[reg] = (float)regs.fp[reg];
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x21:		/* FMOD */
 	    regs.fp[reg] = regs.fp[reg] - (double) ((int) (regs.fp[reg] / src)) * src;
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x22:		/* FADD */
+	case 0x62:
+	case 0x66:
 	    regs.fp[reg] += src;
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    if ((extra & 0x44) == 0x40)
+		regs.fp[reg] = (float)regs.fp[reg];
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x23:		/* FMUL */
+	case 0x63:
+	case 0x67:
 	    regs.fp[reg] *= src;
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    if ((extra & 0x44) == 0x40)
+		regs.fp[reg] = (float)regs.fp[reg];
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x24:		/* FSGLDIV */
 	    regs.fp[reg] /= src;
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x25:		/* FREM */
 	    regs.fp[reg] = regs.fp[reg] - (double) ((int) (regs.fp[reg] / src + 0.5)) * src;
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x26:		/* FSCALE */
 	    regs.fp[reg] *= exp (log (2.0) * src);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x27:		/* FSGLMUL */
 	    regs.fp[reg] *= src;
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x28:		/* FSUB */
+	case 0x68:
+	case 0x6c:
 	    regs.fp[reg] -= src;
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    if ((extra & 0x44) == 0x40)
+		regs.fp[reg] = (float)regs.fp[reg];
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x30:		/* FSINCOS */
 	case 0x31:
@@ -1211,16 +1326,18 @@ void fpp_opp (uae_u32 opcode, uae_u16 ex
 	case 0x37:
 	    regs.fp[reg] = sin (src);
 	    regs.fp[extra & 7] = cos (src);
-	    MAKE_FPSR (regs.fpsr, regs.fp[reg]);
+	    MAKE_FPSR (regs.fp[reg]);
 	    break;
 	case 0x38:		/* FCMP */
-	    {
-		double tmp = regs.fp[reg] - src;
-		regs.fpsr = (tmp == 0 ? 0x4000000 : 0) | (tmp < 0 ? 0x8000000 : 0);
-	    }
-	    break;
+	{
+	    fptype tmp = regs.fp[reg] - src;
+	    regs.fpsr = 0;
+	    MAKE_FPSR (tmp);
+	}
+	break;
 	case 0x3a:		/* FTST */
-	    regs.fpsr = (src == 0 ? 0x4000000 : 0) | (src < 0 ? 0x8000000 : 0);
+	    regs.fpsr = 0;
+	    MAKE_FPSR (src);
 	    break;
 	default:
 	    m68k_setpc (m68k_getpc () - 4);
@@ -1234,3 +1351,56 @@ void fpp_opp (uae_u32 opcode, uae_u16 ex
 }
 
 #endif
+
+
+void restore_fpu (void)
+{
+    int model, i;
+
+    model = restore_u32();
+
+    for (i = 0; i < 8; i++) {
+	uae_u32 w1 = restore_u32 ();
+	uae_u32 w2 = restore_u32 ();
+	uae_u32 w3 = restore_u16 ();
+	regs.fp[i] = to_exten (w1, w2, w3);
+    }
+
+    regs.fpcr = restore_u32 ();
+    regs.fpsr = restore_u32 ();
+    regs.fpiar = restore_u32 ();
+}
+
+
+void save_fpu (void)
+{
+    int model,i;
+
+    switch (currprefs.cpu_level) {
+     case 3:
+	model = 68881;
+	break;
+     case 4:
+	model = 68040;
+	break;
+     case 6:
+	model = 68060;
+	break;
+     default:
+	model = 0;
+    }
+
+    save_u32 (model);
+
+    for (i = 0; i < 8; i++) {
+	uae_u32 w1, w2, w3;
+	from_exten (regs.fp[i], &w1, &w2, &w3);
+	save_u32 (w1);
+	save_u32 (w2);
+	save_u16 (w3);
+    }
+
+    save_u32 (regs.fpcr);
+    save_u32 (regs.fpsr);
+    save_u32 (regs.fpiar);
+}