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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation generator
5: *
6: * This is a fairly stupid program that generates a lot of case labels that
7: * can be #included in a switch statement.
8: * As an alternative, it can generate functions that handle specific
9: * MC68000 instructions, plus a prototype header file and a function pointer
10: * array to look up the function for an opcode.
11: * Error checking is bad, an illegal table68k file will cause the program to
12: * call abort().
13: * The generated code is sometimes sub-optimal, an optimizing compiler should
14: * take care of this.
15: *
16: * The source for the insn timings is Markt & Technik's Amiga Magazin 8/1992.
17: *
18: * Copyright 1995, 1996, 1997, 1998, 1999, 2000 Bernd Schmidt
1.1.1.2 root 19: *
20: * Adaptation to Hatari and better cpu timings by Thomas Huth
21: *
1.1.1.4 root 22: * This file is distributed under the GNU Public License, version 2 or at
23: * your option any later version. Read the file gpl.txt for details.
1.1 root 24: */
1.1.1.8 root 25:
26:
27: /* 2007/03/xx [NP] Use add_cycles.pl to set 'CurrentInstrCycles' in each opcode. */
28: /* 2007/04/09 [NP] Correct CLR : on 68000, CLR reads the memory before clearing it (but we should */
29: /* not add cycles for reading). This means CLR can give 2 wait states (one for */
30: /* read and one for right) (clr.b $fa1b.w in Decade's Demo Main Menu). */
31: /* 2007/04/14 [NP] - Although dest -(an) normally takes 2 cycles, this is not the case for move : */
32: /* move dest (an), (an)+ and -(an) all take the same time (curi->dmode == Apdi) */
33: /* (Syntax Terror Demo Reset). */
34: /* - Scc takes 6 cycles instead of 4 if the result is true (Ventura Demo Loader). */
35: /* - Store the family of the current opcode into OpcodeFamily : used to check */
36: /* instruction pairing on ST into m68000.c */
37: /* 2007/04/17 [NP] Add support for cycle accurate MULU (No Cooper Greeting Screen). */
38: /* 2007/04/24 [NP] BCLR #n,Dx takes 12 cycles instead of 14 if n<16 (ULM Demo Menu). */
39: /* 2007/04/25 [NP] On ST, d8(An,Xn) and d8(PC,Xn) take 2 cycles more than the official 68000's */
40: /* table (ULM Demo Menu). */
41: /* 2007/11/12 [NP] Add refill_prefetch for i_ADD to fix Transbeauce 2 demo self modified code. */
42: /* Ugly hack, we need better prefetch emulation (switch to winuae gencpu.c) */
43: /* 2007/11/25 [NP] In i_DBcc, in case of address error, last_addr_for_exception_3 should be */
44: /* pc+4, not pc+2 (Transbeauce 2 demo) (e.g. 'dbf d0,#$fff5'). */
45: /* This means the value pushed on the frame stack should be the address of the */
46: /* instruction following the one generating the address error. */
47: /* FIXME : this should be the case for i_BSR and i_BCC too (need to check on */
48: /* a real 68000). */
49: /* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */
50: /* Cwik, [email protected]). */
51: /* 2007/12/08 [NP] In case of CHK/CHK2 exception, PC stored on the stack wasn't pointing to the */
52: /* next instruction but to the current CHK/CHK2 instruction (Transbeauce 2 demo). */
53: /* We need to call 'sync_m68k_pc' before calling 'Exception'. */
54: /* 2007/12/09 [NP] CHK.L (e.g. $4700) doesn't exist on 68000 and should be considered as an illegal*/
55: /* instruction (Transbeauce 2 demo) -> change in table68k. */
56: /* 2008/01/24 [NP] BCLR Dy,Dx takes 8 cycles instead of 10 if Dy<16 (Fullshade in Anomaly Demos). */
57: /* 2008/01/26 [NP] On ST, d8(An,Xn) takes 2 cycles more when used with ADDA/SUBA (ULM Demo Menu) */
58: /* but not when used with MOVE (e.g. 'move.l 0(a5,d1),(a4)' takes 26 cycles and so */
59: /* can pair with a lsr) (Anomaly Demo Intro). */
1.1.1.9 root 60: /* 2008/04/26 [NP] Handle sz_byte for Areg in genamode, as 'move.b a1,(a0)' ($1089) is possible */
61: /* on ST (fix Blood Money on Superior 65) */
1.1.1.8 root 62:
63:
64:
1.1.1.10! root 65: const char GenCpu_rcsid[] = "Hatari $Id: gencpu.c,v 1.17 2008-10-05 17:55:31 npomarede Exp $";
1.1 root 66:
67: #include <ctype.h>
1.1.1.3 root 68: #include <string.h>
1.1 root 69:
70: #include "sysdeps.h"
71: #include "readcpu.h"
72:
73: #define BOOL_TYPE "int"
74:
75: static FILE *headerfile;
76: static FILE *stblfile;
77:
78: static int using_prefetch;
79: static int using_exception_3;
80: static int cpu_level;
81:
1.1.1.2 root 82: char exactCpuCycles[256]; /* Space to store return string for exact cpu cycles */
83:
1.1.1.8 root 84: long nCurInstrCycPos; /* Stores where we have to patch in the current cycles value */
1.1.1.2 root 85:
1.1 root 86: /* For the current opcode, the next lower level that will have different code.
87: * Initialized to -1 for each opcode. If it remains unchanged, indicates we
88: * are done with that opcode. */
89: static int next_cpu_level;
90: static int *opcode_map;
91: static int *opcode_next_clev;
92: static int *opcode_last_postfix;
93: static unsigned long *counts;
94:
1.1.1.6 root 95:
1.1 root 96: static void read_counts (void)
97: {
98: FILE *file;
99: unsigned long opcode, count, total;
100: char name[20];
101: int nr = 0;
102: memset (counts, 0, 65536 * sizeof *counts);
103:
104: file = fopen ("frequent.68k", "r");
105: if (file) {
106: fscanf (file, "Total: %lu\n", &total);
107: while (fscanf (file, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
108: opcode_next_clev[nr] = 4;
109: opcode_last_postfix[nr] = -1;
110: opcode_map[nr++] = opcode;
111: counts[opcode] = count;
112: }
113: fclose (file);
114: }
115: if (nr == nr_cpuop_funcs)
116: return;
117: for (opcode = 0; opcode < 0x10000; opcode++) {
118: if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
119: && counts[opcode] == 0)
120: {
121: opcode_next_clev[nr] = 4;
122: opcode_last_postfix[nr] = -1;
123: opcode_map[nr++] = opcode;
124: counts[opcode] = count;
125: }
126: }
127: if (nr != nr_cpuop_funcs)
128: abort ();
129: }
130:
131: static char endlabelstr[80];
132: static int endlabelno = 0;
133: static int need_endlabel;
134:
135: static int n_braces = 0;
136: static int m68k_pc_offset = 0;
137: static int insn_n_cycles;
138:
139: static void start_brace (void)
140: {
141: n_braces++;
142: printf ("{");
143: }
144:
145: static void close_brace (void)
146: {
147: assert (n_braces > 0);
148: n_braces--;
149: printf ("}");
150: }
151:
152: static void finish_braces (void)
153: {
154: while (n_braces > 0)
155: close_brace ();
156: }
157:
158: static void pop_braces (int to)
159: {
160: while (n_braces > to)
161: close_brace ();
162: }
163:
164: static int bit_size (int size)
165: {
166: switch (size) {
167: case sz_byte: return 8;
168: case sz_word: return 16;
169: case sz_long: return 32;
170: default: abort ();
171: }
172: return 0;
173: }
174:
175: static const char *bit_mask (int size)
176: {
177: switch (size) {
178: case sz_byte: return "0xff";
179: case sz_word: return "0xffff";
180: case sz_long: return "0xffffffff";
181: default: abort ();
182: }
183: return 0;
184: }
185:
186: static const char *gen_nextilong (void)
187: {
188: static char buffer[80];
189: int r = m68k_pc_offset;
190: m68k_pc_offset += 4;
191:
192: insn_n_cycles += 8;
193:
194: if (using_prefetch)
195: sprintf (buffer, "get_ilong_prefetch(%d)", r);
196: else
197: sprintf (buffer, "get_ilong(%d)", r);
198: return buffer;
199: }
200:
201: static const char *gen_nextiword (void)
202: {
203: static char buffer[80];
204: int r = m68k_pc_offset;
205: m68k_pc_offset += 2;
206:
207: insn_n_cycles += 4;
208:
209: if (using_prefetch)
210: sprintf (buffer, "get_iword_prefetch(%d)", r);
211: else
212: sprintf (buffer, "get_iword(%d)", r);
213: return buffer;
214: }
215:
216: static const char *gen_nextibyte (void)
217: {
218: static char buffer[80];
219: int r = m68k_pc_offset;
220: m68k_pc_offset += 2;
221:
222: insn_n_cycles += 4;
223:
224: if (using_prefetch)
225: sprintf (buffer, "get_ibyte_prefetch(%d)", r);
226: else
227: sprintf (buffer, "get_ibyte(%d)", r);
228: return buffer;
229: }
230:
231: static void fill_prefetch_0 (void)
232: {
233: if (using_prefetch)
234: printf ("fill_prefetch_0 ();\n");
235: }
236:
237: static void fill_prefetch_2 (void)
238: {
239: if (using_prefetch)
240: printf ("fill_prefetch_2 ();\n");
241: }
242:
243: static void sync_m68k_pc (void)
244: {
245: if (m68k_pc_offset == 0)
246: return;
247: printf ("m68k_incpc(%d);\n", m68k_pc_offset);
248: switch (m68k_pc_offset) {
249: case 0:
250: /*fprintf (stderr, "refilling prefetch at 0\n"); */
251: break;
252: case 2:
253: fill_prefetch_2 ();
254: break;
255: default:
256: fill_prefetch_0 ();
257: break;
258: }
259: m68k_pc_offset = 0;
260: }
261:
262: /* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
1.1.1.4 root 263: * the calling routine handles Apdi and Aipi modes.
264: * gb-- movem == 2 means the same thing but for a MOVE16 instruction */
1.1 root 265: static void genamode (amodes mode, char *reg, wordsizes size, char *name, int getv, int movem)
266: {
267: start_brace ();
268: switch (mode) {
269: case Dreg:
270: if (movem)
271: abort ();
272: if (getv == 1)
273: switch (size) {
274: case sz_byte:
275: printf ("\tuae_s8 %s = m68k_dreg(regs, %s);\n", name, reg);
276: break;
277: case sz_word:
278: printf ("\tuae_s16 %s = m68k_dreg(regs, %s);\n", name, reg);
279: break;
280: case sz_long:
281: printf ("\tuae_s32 %s = m68k_dreg(regs, %s);\n", name, reg);
282: break;
283: default:
284: abort ();
285: }
286: return;
287: case Areg:
288: if (movem)
289: abort ();
290: if (getv == 1)
291: switch (size) {
1.1.1.9 root 292: case sz_byte: // [NP] Areg with .b is possible in MOVE source */
293: printf ("\tuae_s8 %s = m68k_areg(regs, %s);\n", name, reg);
294: break;
1.1 root 295: case sz_word:
296: printf ("\tuae_s16 %s = m68k_areg(regs, %s);\n", name, reg);
297: break;
298: case sz_long:
299: printf ("\tuae_s32 %s = m68k_areg(regs, %s);\n", name, reg);
300: break;
301: default:
302: abort ();
303: }
304: return;
305: case Aind:
306: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
307: break;
308: case Aipi:
309: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
310: break;
311: case Apdi:
312: insn_n_cycles += 2;
313: switch (size) {
314: case sz_byte:
315: if (movem)
316: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
317: else
318: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - areg_byteinc[%s];\n", name, reg, reg);
319: break;
320: case sz_word:
321: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 2);
322: break;
323: case sz_long:
324: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 4);
325: break;
326: default:
327: abort ();
328: }
329: break;
330: case Ad16:
331: printf ("\tuaecptr %sa = m68k_areg(regs, %s) + (uae_s32)(uae_s16)%s;\n", name, reg, gen_nextiword ());
332: break;
333: case Ad8r:
334: insn_n_cycles += 2;
335: if (cpu_level > 1) {
336: if (next_cpu_level < 1)
337: next_cpu_level = 1;
338: sync_m68k_pc ();
339: start_brace ();
340: /* This would ordinarily be done in gen_nextiword, which we bypass. */
341: insn_n_cycles += 4;
342: printf ("\tuaecptr %sa = get_disp_ea_020(m68k_areg(regs, %s), next_iword());\n", name, reg);
1.1.1.8 root 343: } else {
1.1 root 344: printf ("\tuaecptr %sa = get_disp_ea_000(m68k_areg(regs, %s), %s);\n", name, reg, gen_nextiword ());
1.1.1.8 root 345: }
1.1 root 346:
347: break;
348: case PC16:
349: printf ("\tuaecptr %sa = m68k_getpc () + %d;\n", name, m68k_pc_offset);
350: printf ("\t%sa += (uae_s32)(uae_s16)%s;\n", name, gen_nextiword ());
351: break;
352: case PC8r:
353: insn_n_cycles += 2;
354: if (cpu_level > 1) {
355: if (next_cpu_level < 1)
356: next_cpu_level = 1;
357: sync_m68k_pc ();
358: start_brace ();
359: /* This would ordinarily be done in gen_nextiword, which we bypass. */
360: insn_n_cycles += 4;
361: printf ("\tuaecptr tmppc = m68k_getpc();\n");
362: printf ("\tuaecptr %sa = get_disp_ea_020(tmppc, next_iword());\n", name);
363: } else {
364: printf ("\tuaecptr tmppc = m68k_getpc() + %d;\n", m68k_pc_offset);
365: printf ("\tuaecptr %sa = get_disp_ea_000(tmppc, %s);\n", name, gen_nextiword ());
366: }
367:
368: break;
369: case absw:
370: printf ("\tuaecptr %sa = (uae_s32)(uae_s16)%s;\n", name, gen_nextiword ());
371: break;
372: case absl:
373: printf ("\tuaecptr %sa = %s;\n", name, gen_nextilong ());
374: break;
375: case imm:
376: if (getv != 1)
377: abort ();
378: switch (size) {
379: case sz_byte:
380: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte ());
381: break;
382: case sz_word:
383: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword ());
384: break;
385: case sz_long:
386: printf ("\tuae_s32 %s = %s;\n", name, gen_nextilong ());
387: break;
388: default:
389: abort ();
390: }
391: return;
392: case imm0:
393: if (getv != 1)
394: abort ();
395: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte ());
396: return;
397: case imm1:
398: if (getv != 1)
399: abort ();
400: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword ());
401: return;
402: case imm2:
403: if (getv != 1)
404: abort ();
405: printf ("\tuae_s32 %s = %s;\n", name, gen_nextilong ());
406: return;
407: case immi:
408: if (getv != 1)
409: abort ();
410: printf ("\tuae_u32 %s = %s;\n", name, reg);
411: return;
412: default:
413: abort ();
414: }
415:
416: /* We get here for all non-reg non-immediate addressing modes to
417: * actually fetch the value. */
418:
419: if (using_exception_3 && getv != 0 && size != sz_byte) {
420: printf ("\tif ((%sa & 1) != 0) {\n", name);
421: printf ("\t\tlast_fault_for_exception_3 = %sa;\n", name);
422: printf ("\t\tlast_op_for_exception_3 = opcode;\n");
423: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + %d;\n", m68k_pc_offset);
1.1.1.9 root 424: printf ("\t\tException(3, 0, M68000_EXCEPTION_SRC_CPU);\n");
1.1 root 425: printf ("\t\tgoto %s;\n", endlabelstr);
426: printf ("\t}\n");
427: need_endlabel = 1;
428: start_brace ();
429: }
430:
431: if (getv == 1) {
432: switch (size) {
433: case sz_byte: insn_n_cycles += 4; break;
434: case sz_word: insn_n_cycles += 4; break;
435: case sz_long: insn_n_cycles += 8; break;
436: default: abort ();
437: }
438: start_brace ();
439: switch (size) {
440: case sz_byte: printf ("\tuae_s8 %s = get_byte(%sa);\n", name, name); break;
441: case sz_word: printf ("\tuae_s16 %s = get_word(%sa);\n", name, name); break;
442: case sz_long: printf ("\tuae_s32 %s = get_long(%sa);\n", name, name); break;
443: default: abort ();
444: }
445: }
446:
447: /* We now might have to fix up the register for pre-dec or post-inc
448: * addressing modes. */
449: if (!movem)
450: switch (mode) {
451: case Aipi:
452: switch (size) {
453: case sz_byte:
454: printf ("\tm68k_areg(regs, %s) += areg_byteinc[%s];\n", reg, reg);
455: break;
456: case sz_word:
457: printf ("\tm68k_areg(regs, %s) += 2;\n", reg);
458: break;
459: case sz_long:
460: printf ("\tm68k_areg(regs, %s) += 4;\n", reg);
461: break;
462: default:
463: abort ();
464: }
465: break;
466: case Apdi:
467: printf ("\tm68k_areg (regs, %s) = %sa;\n", reg, name);
468: break;
469: default:
470: break;
471: }
472: }
473:
474: static void genastore (char *from, amodes mode, char *reg, wordsizes size, char *to)
475: {
476: switch (mode) {
477: case Dreg:
478: switch (size) {
479: case sz_byte:
480: printf ("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from);
481: break;
482: case sz_word:
483: printf ("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from);
484: break;
485: case sz_long:
486: printf ("\tm68k_dreg(regs, %s) = (%s);\n", reg, from);
487: break;
488: default:
489: abort ();
490: }
491: break;
492: case Areg:
493: switch (size) {
494: case sz_word:
495: fprintf (stderr, "Foo\n");
496: printf ("\tm68k_areg(regs, %s) = (uae_s32)(uae_s16)(%s);\n", reg, from);
497: break;
498: case sz_long:
499: printf ("\tm68k_areg(regs, %s) = (%s);\n", reg, from);
500: break;
501: default:
502: abort ();
503: }
504: break;
505: case Aind:
506: case Aipi:
507: case Apdi:
508: case Ad16:
509: case Ad8r:
510: case absw:
511: case absl:
512: case PC16:
513: case PC8r:
514: if (using_prefetch)
515: sync_m68k_pc ();
516: switch (size) {
517: case sz_byte:
518: insn_n_cycles += 4;
519: printf ("\tput_byte(%sa,%s);\n", to, from);
520: break;
521: case sz_word:
522: insn_n_cycles += 4;
523: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
524: abort ();
525: printf ("\tput_word(%sa,%s);\n", to, from);
526: break;
527: case sz_long:
528: insn_n_cycles += 8;
529: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
530: abort ();
531: printf ("\tput_long(%sa,%s);\n", to, from);
532: break;
533: default:
534: abort ();
535: }
536: break;
537: case imm:
538: case imm0:
539: case imm1:
540: case imm2:
541: case immi:
542: abort ();
543: break;
544: default:
545: abort ();
546: }
547: }
548:
1.1.1.2 root 549:
1.1 root 550: static void genmovemel (uae_u16 opcode)
551: {
552: char getcode[100];
1.1.1.3 root 553: int bMovemLong = (table68k[opcode].size == sz_long);
554: int size = bMovemLong ? 4 : 2;
1.1 root 555:
1.1.1.3 root 556: if (bMovemLong) {
1.1 root 557: strcpy (getcode, "get_long(srca)");
558: } else {
559: strcpy (getcode, "(uae_s32)(uae_s16)get_word(srca)");
560: }
561:
562: printf ("\tuae_u16 mask = %s;\n", gen_nextiword ());
563: printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1.1.1.2 root 564: printf ("\tretcycles = 0;\n");
1.1.1.3 root 565: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1);
1.1 root 566: start_brace ();
1.1.1.2 root 567: printf ("\twhile (dmask) { m68k_dreg(regs, movem_index1[dmask]) = %s;"
1.1.1.3 root 568: " srca += %d; dmask = movem_next[dmask]; retcycles+=%d; }\n",
569: getcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 570: printf ("\twhile (amask) { m68k_areg(regs, movem_index1[amask]) = %s;"
1.1.1.3 root 571: " srca += %d; amask = movem_next[amask]; retcycles+=%d; }\n",
572: getcode, size, (bMovemLong ? 8 : 4));
1.1 root 573:
574: if (table68k[opcode].dmode == Aipi)
575: printf ("\tm68k_areg(regs, dstreg) = srca;\n");
1.1.1.2 root 576:
577: /* Better cycles - experimental! (Thothy) */
578: switch(table68k[opcode].dmode)
1.1.1.3 root 579: {
1.1.1.2 root 580: case Aind: insn_n_cycles=12; break;
581: case Aipi: insn_n_cycles=12; break;
582: case Ad16: insn_n_cycles=16; break;
583: case Ad8r: insn_n_cycles=18; break;
584: case absw: insn_n_cycles=16; break;
585: case absl: insn_n_cycles=20; break;
586: case PC16: insn_n_cycles=16; break;
587: case PC8r: insn_n_cycles=18; break;
1.1.1.3 root 588: }
589: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 590: }
591:
592: static void genmovemle (uae_u16 opcode)
593: {
594: char putcode[100];
1.1.1.3 root 595: int bMovemLong = (table68k[opcode].size == sz_long);
596: int size = bMovemLong ? 4 : 2;
597:
598: if (bMovemLong) {
1.1 root 599: strcpy (putcode, "put_long(srca,");
600: } else {
601: strcpy (putcode, "put_word(srca,");
602: }
603:
604: printf ("\tuae_u16 mask = %s;\n", gen_nextiword ());
1.1.1.3 root 605: printf ("\tretcycles = 0;\n");
1.1 root 606: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1);
607: if (using_prefetch)
608: sync_m68k_pc ();
609:
610: start_brace ();
611: if (table68k[opcode].dmode == Apdi) {
1.1.1.2 root 612: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
613: printf ("\twhile (amask) { srca -= %d; %s m68k_areg(regs, movem_index2[amask]));"
1.1.1.3 root 614: " amask = movem_next[amask]; retcycles+=%d; }\n",
615: size, putcode, (bMovemLong ? 8 : 4));
1.1.1.2 root 616: printf ("\twhile (dmask) { srca -= %d; %s m68k_dreg(regs, movem_index2[dmask]));"
1.1.1.3 root 617: " dmask = movem_next[dmask]; retcycles+=%d; }\n",
618: size, putcode, (bMovemLong ? 8 : 4));
1.1.1.2 root 619: printf ("\tm68k_areg(regs, dstreg) = srca;\n");
1.1 root 620: } else {
1.1.1.2 root 621: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
622: printf ("\twhile (dmask) { %s m68k_dreg(regs, movem_index1[dmask])); srca += %d;"
1.1.1.3 root 623: " dmask = movem_next[dmask]; retcycles+=%d; }\n",
624: putcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 625: printf ("\twhile (amask) { %s m68k_areg(regs, movem_index1[amask])); srca += %d;"
1.1.1.3 root 626: " amask = movem_next[amask]; retcycles+=%d; }\n",
627: putcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 628: }
629:
630: /* Better cycles - experimental! (Thothy) */
631: switch(table68k[opcode].dmode)
1.1.1.3 root 632: {
1.1.1.2 root 633: case Aind: insn_n_cycles=8; break;
634: case Apdi: insn_n_cycles=8; break;
635: case Ad16: insn_n_cycles=12; break;
636: case Ad8r: insn_n_cycles=14; break;
637: case absw: insn_n_cycles=12; break;
638: case absl: insn_n_cycles=16; break;
1.1.1.3 root 639: }
640: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 641: }
642:
1.1.1.2 root 643:
1.1 root 644: static void duplicate_carry (void)
645: {
646: printf ("\tCOPY_CARRY;\n");
647: }
648:
649: typedef enum
650: {
651: flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_zn,
652: flag_av, flag_sv
653: }
654: flagtypes;
655:
656: static void genflags_normal (flagtypes type, wordsizes size, char *value, char *src, char *dst)
657: {
658: char vstr[100], sstr[100], dstr[100];
659: char usstr[100], udstr[100];
660: char unsstr[100], undstr[100];
661:
662: switch (size) {
663: case sz_byte:
664: strcpy (vstr, "((uae_s8)(");
665: strcpy (usstr, "((uae_u8)(");
666: break;
667: case sz_word:
668: strcpy (vstr, "((uae_s16)(");
669: strcpy (usstr, "((uae_u16)(");
670: break;
671: case sz_long:
672: strcpy (vstr, "((uae_s32)(");
673: strcpy (usstr, "((uae_u32)(");
674: break;
675: default:
676: abort ();
677: }
678: strcpy (unsstr, usstr);
679:
680: strcpy (sstr, vstr);
681: strcpy (dstr, vstr);
682: strcat (vstr, value);
683: strcat (vstr, "))");
684: strcat (dstr, dst);
685: strcat (dstr, "))");
686: strcat (sstr, src);
687: strcat (sstr, "))");
688:
689: strcpy (udstr, usstr);
690: strcat (udstr, dst);
691: strcat (udstr, "))");
692: strcat (usstr, src);
693: strcat (usstr, "))");
694:
695: strcpy (undstr, unsstr);
696: strcat (unsstr, "-");
697: strcat (undstr, "~");
698: strcat (undstr, dst);
699: strcat (undstr, "))");
700: strcat (unsstr, src);
701: strcat (unsstr, "))");
702:
703: switch (type) {
704: case flag_logical_noclobber:
705: case flag_logical:
706: case flag_zn:
707: case flag_av:
708: case flag_sv:
709: case flag_addx:
710: case flag_subx:
711: break;
712:
713: case flag_add:
714: start_brace ();
715: printf ("uae_u32 %s = %s + %s;\n", value, dstr, sstr);
716: break;
717: case flag_sub:
718: case flag_cmp:
719: start_brace ();
720: printf ("uae_u32 %s = %s - %s;\n", value, dstr, sstr);
721: break;
722: }
723:
724: switch (type) {
725: case flag_logical_noclobber:
726: case flag_logical:
727: case flag_zn:
728: break;
729:
730: case flag_add:
731: case flag_sub:
732: case flag_addx:
733: case flag_subx:
734: case flag_cmp:
735: case flag_av:
736: case flag_sv:
737: start_brace ();
738: printf ("\t" BOOL_TYPE " flgs = %s < 0;\n", sstr);
739: printf ("\t" BOOL_TYPE " flgo = %s < 0;\n", dstr);
740: printf ("\t" BOOL_TYPE " flgn = %s < 0;\n", vstr);
741: break;
742: }
743:
744: switch (type) {
745: case flag_logical:
746: printf ("\tCLEAR_CZNV;\n");
747: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
748: printf ("\tSET_NFLG (%s < 0);\n", vstr);
749: break;
750: case flag_logical_noclobber:
751: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
752: printf ("\tSET_NFLG (%s < 0);\n", vstr);
753: break;
754: case flag_av:
755: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
756: break;
757: case flag_sv:
758: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
759: break;
760: case flag_zn:
761: printf ("\tSET_ZFLG (GET_ZFLG & (%s == 0));\n", vstr);
762: printf ("\tSET_NFLG (%s < 0);\n", vstr);
763: break;
764: case flag_add:
765: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
766: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
767: printf ("\tSET_CFLG (%s < %s);\n", undstr, usstr);
768: duplicate_carry ();
769: printf ("\tSET_NFLG (flgn != 0);\n");
770: break;
771: case flag_sub:
772: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
773: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
774: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
775: duplicate_carry ();
776: printf ("\tSET_NFLG (flgn != 0);\n");
777: break;
778: case flag_addx:
779: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n"); /* minterm SON: 0x42 */
780: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));\n"); /* minterm SON: 0xD4 */
781: duplicate_carry ();
782: break;
783: case flag_subx:
784: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));\n"); /* minterm SON: 0x24 */
785: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));\n"); /* minterm SON: 0xB2 */
786: duplicate_carry ();
787: break;
788: case flag_cmp:
789: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
790: printf ("\tSET_VFLG ((flgs != flgo) && (flgn != flgo));\n");
791: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
792: printf ("\tSET_NFLG (flgn != 0);\n");
793: break;
794: }
795: }
796:
797: static void genflags (flagtypes type, wordsizes size, char *value, char *src, char *dst)
798: {
799: /* Temporarily deleted 68k/ARM flag optimizations. I'd prefer to have
800: them in the appropriate m68k.h files and use just one copy of this
801: code here. The API can be changed if necessary. */
802: #ifdef OPTIMIZED_FLAGS
803: switch (type) {
804: case flag_add:
805: case flag_sub:
806: start_brace ();
807: printf ("\tuae_u32 %s;\n", value);
808: break;
809:
810: default:
811: break;
812: }
813:
814: /* At least some of those casts are fairly important! */
815: switch (type) {
816: case flag_logical_noclobber:
817: printf ("\t{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
818: if (strcmp (value, "0") == 0) {
819: printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n");
820: } else {
821: switch (size) {
822: case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
823: case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
824: case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
825: }
826: printf ("\tIOR_CZNV (oldcznv);\n");
827: }
828: printf ("\t}\n");
829: return;
830: case flag_logical:
831: if (strcmp (value, "0") == 0) {
832: printf ("\tSET_CZNV (FLAGVAL_Z);\n");
833: } else {
834: switch (size) {
835: case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
836: case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
837: case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
838: }
839: }
840: return;
841:
842: case flag_add:
843: switch (size) {
844: case sz_byte: printf ("\toptflag_addb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
845: case sz_word: printf ("\toptflag_addw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
846: case sz_long: printf ("\toptflag_addl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
847: }
848: return;
849:
850: case flag_sub:
851: switch (size) {
852: case sz_byte: printf ("\toptflag_subb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
853: case sz_word: printf ("\toptflag_subw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
854: case sz_long: printf ("\toptflag_subl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
855: }
856: return;
857:
858: case flag_cmp:
859: switch (size) {
860: case sz_byte: printf ("\toptflag_cmpb ((uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
861: case sz_word: printf ("\toptflag_cmpw ((uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
862: case sz_long: printf ("\toptflag_cmpl ((uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
863: }
864: return;
865:
866: default:
867: break;
868: }
869: #endif
870:
871: genflags_normal (type, size, value, src, dst);
872: }
873:
874: static void force_range_for_rox (const char *var, wordsizes size)
875: {
876: /* Could do a modulo operation here... which one is faster? */
877: switch (size) {
878: case sz_long:
879: printf ("\tif (%s >= 33) %s -= 33;\n", var, var);
880: break;
881: case sz_word:
882: printf ("\tif (%s >= 34) %s -= 34;\n", var, var);
883: printf ("\tif (%s >= 17) %s -= 17;\n", var, var);
884: break;
885: case sz_byte:
886: printf ("\tif (%s >= 36) %s -= 36;\n", var, var);
887: printf ("\tif (%s >= 18) %s -= 18;\n", var, var);
888: printf ("\tif (%s >= 9) %s -= 9;\n", var, var);
889: break;
890: }
891: }
892:
893: static const char *cmask (wordsizes size)
894: {
895: switch (size) {
896: case sz_byte: return "0x80";
897: case sz_word: return "0x8000";
898: case sz_long: return "0x80000000";
899: default: abort ();
900: }
901: }
902:
903: static int source_is_imm1_8 (struct instr *i)
904: {
905: return i->stype == 3;
906: }
907:
1.1.1.2 root 908:
909:
1.1 root 910: static void gen_opcode (unsigned long int opcode)
911: {
1.1.1.2 root 912: #if 0
913: char *amodenames[] = { "Dreg", "Areg", "Aind", "Aipi", "Apdi", "Ad16", "Ad8r",
914: "absw", "absl", "PC16", "PC8r", "imm", "imm0", "imm1", "imm2", "immi", "am_unknown", "am_illg"};
915: #endif
916:
1.1 root 917: struct instr *curi = table68k + opcode;
918: insn_n_cycles = 4;
919:
1.1.1.8 root 920: /* Store the family of the instruction (used to check for pairing on ST)
921: * and leave some space for patching in the current cycles later */
922: printf ("\tOpcodeFamily = %d; CurrentInstrCycles = \n", curi->mnemo);
923: nCurInstrCycPos = ftell(stdout) - 5;
924:
1.1 root 925: start_brace ();
926: m68k_pc_offset = 2;
1.1.1.2 root 927:
1.1 root 928: switch (curi->plev) {
929: case 0: /* not privileged */
930: break;
931: case 1: /* unprivileged only on 68000 */
932: if (cpu_level == 0)
933: break;
934: if (next_cpu_level < 0)
935: next_cpu_level = 0;
936:
937: /* fall through */
938: case 2: /* priviledged */
1.1.1.9 root 939: printf ("if (!regs.s) { Exception(8,0,M68000_EXCEPTION_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 940: need_endlabel = 1;
941: start_brace ();
942: break;
943: case 3: /* privileged if size == word */
944: if (curi->size == sz_byte)
945: break;
1.1.1.9 root 946: printf ("if (!regs.s) { Exception(8,0,M68000_EXCEPTION_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 947: need_endlabel = 1;
948: start_brace ();
949: break;
950: }
1.1.1.2 root 951:
952: /* Build the opcodes: */
1.1 root 953: switch (curi->mnemo) {
954: case i_OR:
955: case i_AND:
956: case i_EOR:
1.1.1.2 root 957: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
958: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
959: printf ("\tsrc %c= dst;\n", curi->mnemo == i_OR ? '|' : curi->mnemo == i_AND ? '&' : '^');
960: genflags (flag_logical, curi->size, "src", "", "");
961: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
962: if(curi->size==sz_long && curi->dmode==Dreg)
963: {
964: insn_n_cycles += 2;
965: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
966: insn_n_cycles += 2;
967: }
968: #if 0
969: /* Output the CPU cycles: */
970: fprintf(stderr,"MOVE, size %i: ",curi->size);
971: fprintf(stderr," %s ->",amodenames[curi->smode]);
972: fprintf(stderr," %s ",amodenames[curi->dmode]);
973: fprintf(stderr," Cycles: %i\n",insn_n_cycles);
974: #endif
975: break;
1.1 root 976: case i_ORSR:
977: case i_EORSR:
1.1.1.2 root 978: printf ("\tMakeSR();\n");
979: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
980: if (curi->size == sz_byte) {
981: printf ("\tsrc &= 0xFF;\n");
982: }
983: printf ("\tregs.sr %c= src;\n", curi->mnemo == i_EORSR ? '^' : '|');
984: printf ("\tMakeFromSR();\n");
985: insn_n_cycles = 20;
986: break;
1.1 root 987: case i_ANDSR:
1.1.1.2 root 988: printf ("\tMakeSR();\n");
989: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
990: if (curi->size == sz_byte) {
991: printf ("\tsrc |= 0xFF00;\n");
992: }
993: printf ("\tregs.sr &= src;\n");
994: printf ("\tMakeFromSR();\n");
995: insn_n_cycles = 20;
996: break;
1.1 root 997: case i_SUB:
998: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
999: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1000: start_brace ();
1001: genflags (flag_sub, curi->size, "newv", "src", "dst");
1002: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1003: if(curi->size==sz_long && curi->dmode==Dreg)
1004: {
1005: insn_n_cycles += 2;
1006: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
1007: insn_n_cycles += 2;
1008: }
1.1 root 1009: break;
1010: case i_SUBA:
1011: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1012: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1013: start_brace ();
1014: printf ("\tuae_u32 newv = dst - src;\n");
1015: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.2 root 1016: if(curi->size==sz_long && curi->smode!=Dreg && curi->smode!=Areg && !(curi->smode>=imm && curi->smode<=immi))
1017: insn_n_cycles += 2;
1018: else
1019: insn_n_cycles += 4;
1.1.1.8 root 1020: if( (curi->smode==Ad8r) || (curi->smode==PC8r) ) /* [NP] on 68000 ST, d8(An,Xn) takes 2 cycles more */
1021: insn_n_cycles += 2;
1.1 root 1022: break;
1023: case i_SUBX:
1024: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1025: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1026: start_brace ();
1027: printf ("\tuae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);\n");
1028: genflags (flag_subx, curi->size, "newv", "src", "dst");
1029: genflags (flag_zn, curi->size, "newv", "", "");
1030: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1031: if(curi->smode==Dreg && curi->size==sz_long)
1032: insn_n_cycles=8;
1033: if(curi->smode==Apdi)
1034: {
1035: if(curi->size==sz_long)
1036: insn_n_cycles=30;
1037: else
1038: insn_n_cycles=18;
1039: }
1.1 root 1040: break;
1041: case i_SBCD:
1042: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1043: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1044: start_brace ();
1045: printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
1046: printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
1.1.1.4 root 1047: printf ("\tuae_u16 newv, tmp_newv;\n");
1048: printf ("\tint bcd = 0;\n");
1049: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
1050: printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
1051: printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
1052: printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);\n");
1.1 root 1053: duplicate_carry ();
1054: genflags (flag_zn, curi->size, "newv", "", "");
1.1.1.4 root 1055: printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
1.1 root 1056: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.4 root 1057: if(curi->smode==Dreg) insn_n_cycles=6;
1058: if(curi->smode==Apdi) insn_n_cycles=18;
1.1 root 1059: break;
1060: case i_ADD:
1061: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1062: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1063: start_brace ();
1.1.1.8 root 1064: printf("\trefill_prefetch (m68k_getpc(), 2);\n"); // FIXME [NP] For Transbeauce 2 demo, need better prefetch emulation
1.1 root 1065: genflags (flag_add, curi->size, "newv", "src", "dst");
1066: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1067: if(curi->size==sz_long && curi->dmode==Dreg)
1068: {
1069: insn_n_cycles += 2;
1070: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
1071: insn_n_cycles += 2;
1072: }
1.1 root 1073: break;
1074: case i_ADDA:
1075: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1076: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1077: start_brace ();
1078: printf ("\tuae_u32 newv = dst + src;\n");
1079: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.2 root 1080: if(curi->size==sz_long && curi->smode!=Dreg && curi->smode!=Areg && !(curi->smode>=imm && curi->smode<=immi))
1081: insn_n_cycles += 2;
1082: else
1083: insn_n_cycles += 4;
1.1.1.8 root 1084: if( (curi->smode==Ad8r) || (curi->smode==PC8r) ) /* [NP] on 68000 ST, d8(An,Xn) takes 2 cycles more */
1085: insn_n_cycles += 2;
1.1 root 1086: break;
1087: case i_ADDX:
1088: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1089: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1090: start_brace ();
1091: printf ("\tuae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);\n");
1092: genflags (flag_addx, curi->size, "newv", "src", "dst");
1093: genflags (flag_zn, curi->size, "newv", "", "");
1094: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1095: if(curi->smode==Dreg && curi->size==sz_long)
1096: insn_n_cycles=8;
1097: if(curi->smode==Apdi)
1098: {
1099: if(curi->size==sz_long)
1100: insn_n_cycles=30;
1101: else
1102: insn_n_cycles=18;
1103: }
1.1 root 1104: break;
1105: case i_ABCD:
1106: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1107: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1108: start_brace ();
1109: printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);\n");
1110: printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
1.1.1.4 root 1111: printf ("\tuae_u16 newv, tmp_newv;\n");
1.1 root 1112: printf ("\tint cflg;\n");
1.1.1.4 root 1113: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;");
1114: printf ("\tif (newv_lo > 9) { newv += 6; }\n");
1115: printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
1116: printf ("\tif (cflg) newv += 0x60;\n");
1.1 root 1117: printf ("\tSET_CFLG (cflg);\n");
1118: duplicate_carry ();
1119: genflags (flag_zn, curi->size, "newv", "", "");
1.1.1.4 root 1120: printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
1.1 root 1121: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.4 root 1122: if(curi->smode==Dreg) insn_n_cycles=6;
1123: if(curi->smode==Apdi) insn_n_cycles=18;
1.1 root 1124: break;
1125: case i_NEG:
1126: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1127: start_brace ();
1128: genflags (flag_sub, curi->size, "dst", "src", "0");
1129: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1130: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1131: break;
1132: case i_NEGX:
1133: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1134: start_brace ();
1135: printf ("\tuae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);\n");
1136: genflags (flag_subx, curi->size, "newv", "src", "0");
1137: genflags (flag_zn, curi->size, "newv", "", "");
1138: genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1139: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1140: break;
1141: case i_NBCD:
1142: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1143: start_brace ();
1144: printf ("\tuae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
1145: printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
1146: printf ("\tuae_u16 newv;\n");
1147: printf ("\tint cflg;\n");
1.1.1.4 root 1148: printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
1149: printf ("\tnewv = newv_hi + newv_lo;");
1150: printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
1151: printf ("\tif (cflg) newv -= 0x60;\n");
1.1 root 1152: printf ("\tSET_CFLG (cflg);\n");
1153: duplicate_carry();
1154: genflags (flag_zn, curi->size, "newv", "", "");
1155: genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1.1.1.4 root 1156: if(curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1157: break;
1158: case i_CLR:
1159: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1.1.1.8 root 1160:
1161: /* [NP] CLR does a read before the write only on 68000 */
1162: /* but there's no cycle penalty for doing the read */
1163: if ( curi->smode != Dreg ) // only if destination is memory
1164: {
1165: if (curi->size==sz_byte)
1166: printf ("\tuae_s8 src = get_byte(srca);\n");
1167: else if (curi->size==sz_word)
1168: printf ("\tuae_s16 src = get_word(srca);\n");
1169: else if (curi->size==sz_long)
1170: printf ("\tuae_s32 src = get_long(srca);\n");
1171: }
1172:
1.1 root 1173: genflags (flag_logical, curi->size, "0", "", "");
1174: genastore ("0", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1175: if(curi->size==sz_long)
1.1.1.3 root 1176: {
1.1.1.2 root 1177: if(curi->smode==Dreg)
1178: insn_n_cycles += 2;
1179: else
1180: insn_n_cycles += 4;
1.1.1.3 root 1181: }
1.1.1.2 root 1182: if(curi->smode!=Dreg)
1183: insn_n_cycles += 4;
1.1 root 1184: break;
1185: case i_NOT:
1186: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1187: start_brace ();
1188: printf ("\tuae_u32 dst = ~src;\n");
1189: genflags (flag_logical, curi->size, "dst", "", "");
1190: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1191: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1192: break;
1193: case i_TST:
1194: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1195: genflags (flag_logical, curi->size, "src", "", "");
1196: break;
1197: case i_BTST:
1198: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1199: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1200: if (curi->size == sz_byte)
1201: printf ("\tsrc &= 7;\n");
1202: else
1203: printf ("\tsrc &= 31;\n");
1204: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1.1.1.2 root 1205: if(curi->dmode==Dreg) insn_n_cycles += 2;
1.1 root 1206: break;
1207: case i_BCHG:
1208: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1209: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1210: if (curi->size == sz_byte)
1211: printf ("\tsrc &= 7;\n");
1212: else
1213: printf ("\tsrc &= 31;\n");
1214: printf ("\tdst ^= (1 << src);\n");
1215: printf ("\tSET_ZFLG (((uae_u32)dst & (1 << src)) >> src);\n");
1216: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1217: if(curi->dmode==Dreg) insn_n_cycles += 4;
1.1 root 1218: break;
1219: case i_BCLR:
1220: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1221: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1222: if (curi->size == sz_byte)
1223: printf ("\tsrc &= 7;\n");
1224: else
1225: printf ("\tsrc &= 31;\n");
1226: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1227: printf ("\tdst &= ~(1 << src);\n");
1228: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1229: if(curi->dmode==Dreg) insn_n_cycles += 6;
1.1.1.8 root 1230: /* [NP] BCLR #n,Dx takes 12 cycles instead of 14 if n<16 */
1231: if((curi->smode==imm1) && (curi->dmode==Dreg))
1232: printf ("\tif ( src < 16 ) { m68k_incpc(4); return 12; }\n");
1233: /* [NP] BCLR Dy,Dx takes 8 cycles instead of 10 if Dy<16 */
1234: if((curi->smode==Dreg) && (curi->dmode==Dreg))
1235: printf ("\tif ( src < 16 ) { m68k_incpc(2); return 8; }\n");
1.1 root 1236: break;
1237: case i_BSET:
1238: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1239: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1240: if (curi->size == sz_byte)
1241: printf ("\tsrc &= 7;\n");
1242: else
1243: printf ("\tsrc &= 31;\n");
1244: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1245: printf ("\tdst |= (1 << src);\n");
1246: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1247: if(curi->dmode==Dreg) insn_n_cycles += 4;
1.1 root 1248: break;
1249: case i_CMPM:
1250: case i_CMP:
1251: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1252: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1253: start_brace ();
1254: genflags (flag_cmp, curi->size, "newv", "src", "dst");
1.1.1.2 root 1255: if(curi->size==sz_long && curi->dmode==Dreg)
1256: insn_n_cycles += 2;
1.1 root 1257: break;
1258: case i_CMPA:
1259: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1260: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1261: start_brace ();
1262: genflags (flag_cmp, sz_long, "newv", "src", "dst");
1.1.1.2 root 1263: insn_n_cycles += 2;
1.1 root 1264: break;
1265: /* The next two are coded a little unconventional, but they are doing
1266: * weird things... */
1267: case i_MVPRM:
1268: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1269:
1270: printf ("\tuaecptr memp = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword ());
1271: if (curi->size == sz_word) {
1272: printf ("\tput_byte(memp, src >> 8); put_byte(memp + 2, src);\n");
1273: } else {
1274: printf ("\tput_byte(memp, src >> 24); put_byte(memp + 2, src >> 16);\n");
1275: printf ("\tput_byte(memp + 4, src >> 8); put_byte(memp + 6, src);\n");
1276: }
1.1.1.2 root 1277: if(curi->size==sz_long) insn_n_cycles=24; else insn_n_cycles=16;
1.1 root 1278: break;
1279: case i_MVPMR:
1280: printf ("\tuaecptr memp = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword ());
1281: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1282: if (curi->size == sz_word) {
1283: printf ("\tuae_u16 val = (get_byte(memp) << 8) + get_byte(memp + 2);\n");
1284: } else {
1285: printf ("\tuae_u32 val = (get_byte(memp) << 24) + (get_byte(memp + 2) << 16)\n");
1286: printf (" + (get_byte(memp + 4) << 8) + get_byte(memp + 6);\n");
1287: }
1288: genastore ("val", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1289: if(curi->size==sz_long) insn_n_cycles=24; else insn_n_cycles=16;
1.1 root 1290: break;
1291: case i_MOVE:
1292: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1293: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1.1.1.8 root 1294:
1295: /* [NP] genamode counts 2 cycles if dest is -(An), this is wrong. */
1296: /* For move dest (An), (An)+ and -(An) take the same time */
1297: /* (for other instr, dest -(An) really takes 2 cycles more) */
1298: if ( curi->dmode == Apdi )
1299: insn_n_cycles -= 2; /* correct the wrong cycle count for -(An) */
1300:
1.1 root 1301: genflags (flag_logical, curi->size, "src", "", "");
1302: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
1303: break;
1304: case i_MOVEA:
1305: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1306: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1307: if (curi->size == sz_word) {
1308: printf ("\tuae_u32 val = (uae_s32)(uae_s16)src;\n");
1309: } else {
1310: printf ("\tuae_u32 val = src;\n");
1311: }
1312: genastore ("val", curi->dmode, "dstreg", sz_long, "dst");
1313: break;
1.1.1.2 root 1314: case i_MVSR2: /* Move from SR */
1.1 root 1315: genamode (curi->smode, "srcreg", sz_word, "src", 2, 0);
1316: printf ("\tMakeSR();\n");
1317: if (curi->size == sz_byte)
1318: genastore ("regs.sr & 0xff", curi->smode, "srcreg", sz_word, "src");
1319: else
1320: genastore ("regs.sr", curi->smode, "srcreg", sz_word, "src");
1.1.1.2 root 1321: if (curi->smode==Dreg) insn_n_cycles += 2; else insn_n_cycles += 4;
1.1 root 1322: break;
1.1.1.2 root 1323: case i_MV2SR: /* Move to SR */
1.1 root 1324: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1325: if (curi->size == sz_byte)
1326: printf ("\tMakeSR();\n\tregs.sr &= 0xFF00;\n\tregs.sr |= src & 0xFF;\n");
1327: else {
1328: printf ("\tregs.sr = src;\n");
1329: }
1330: printf ("\tMakeFromSR();\n");
1.1.1.2 root 1331: insn_n_cycles += 8;
1.1 root 1332: break;
1333: case i_SWAP:
1334: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1335: start_brace ();
1336: printf ("\tuae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);\n");
1337: genflags (flag_logical, sz_long, "dst", "", "");
1338: genastore ("dst", curi->smode, "srcreg", sz_long, "src");
1339: break;
1340: case i_EXG:
1341: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1342: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1343: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1344: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1345: insn_n_cycles = 6;
1.1 root 1346: break;
1347: case i_EXT:
1348: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1349: start_brace ();
1350: switch (curi->size) {
1351: case sz_byte: printf ("\tuae_u32 dst = (uae_s32)(uae_s8)src;\n"); break;
1352: case sz_word: printf ("\tuae_u16 dst = (uae_s16)(uae_s8)src;\n"); break;
1353: case sz_long: printf ("\tuae_u32 dst = (uae_s32)(uae_s16)src;\n"); break;
1354: default: abort ();
1355: }
1356: genflags (flag_logical,
1357: curi->size == sz_word ? sz_word : sz_long, "dst", "", "");
1358: genastore ("dst", curi->smode, "srcreg",
1359: curi->size == sz_word ? sz_word : sz_long, "src");
1360: break;
1361: case i_MVMEL:
1362: genmovemel (opcode);
1363: break;
1364: case i_MVMLE:
1365: genmovemle (opcode);
1366: break;
1367: case i_TRAP:
1368: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1369: sync_m68k_pc ();
1.1.1.9 root 1370: printf ("\tException(src+32,0,M68000_EXCEPTION_SRC_CPU);\n");
1.1 root 1371: m68k_pc_offset = 0;
1372: break;
1373: case i_MVR2USP:
1374: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1375: printf ("\tregs.usp = src;\n");
1376: break;
1377: case i_MVUSP2R:
1378: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1379: genastore ("regs.usp", curi->smode, "srcreg", curi->size, "src");
1380: break;
1381: case i_RESET:
1382: printf ("\tcustomreset();\n");
1.1.1.2 root 1383: insn_n_cycles = 132; /* I am not so sure about this!? - Thothy */
1.1 root 1384: break;
1385: case i_NOP:
1386: break;
1387: case i_STOP:
1388: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1389: printf ("\tregs.sr = src;\n");
1390: printf ("\tMakeFromSR();\n");
1391: printf ("\tm68k_setstopped(1);\n");
1.1.1.2 root 1392: insn_n_cycles = 4;
1.1 root 1393: break;
1394: case i_RTE:
1395: if (cpu_level == 0) {
1396: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1397: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1398: printf ("\tregs.sr = sr; m68k_setpc_rte(pc);\n");
1399: fill_prefetch_0 ();
1400: printf ("\tMakeFromSR();\n");
1401: } else {
1402: int old_brace_level = n_braces;
1403: if (next_cpu_level < 0)
1404: next_cpu_level = 0;
1405: printf ("\tuae_u16 newsr; uae_u32 newpc; for (;;) {\n");
1406: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1407: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1408: genamode (Aipi, "7", sz_word, "format", 1, 0);
1409: printf ("\tnewsr = sr; newpc = pc;\n");
1410: printf ("\tif ((format & 0xF000) == 0x0000) { break; }\n");
1411: printf ("\telse if ((format & 0xF000) == 0x1000) { ; }\n");
1412: printf ("\telse if ((format & 0xF000) == 0x2000) { m68k_areg(regs, 7) += 4; break; }\n");
1413: printf ("\telse if ((format & 0xF000) == 0x8000) { m68k_areg(regs, 7) += 50; break; }\n");
1414: printf ("\telse if ((format & 0xF000) == 0x9000) { m68k_areg(regs, 7) += 12; break; }\n");
1415: printf ("\telse if ((format & 0xF000) == 0xa000) { m68k_areg(regs, 7) += 24; break; }\n");
1416: printf ("\telse if ((format & 0xF000) == 0xb000) { m68k_areg(regs, 7) += 84; break; }\n");
1.1.1.9 root 1417: printf ("\telse { Exception(14,0,M68000_EXCEPTION_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 1418: printf ("\tregs.sr = newsr; MakeFromSR();\n}\n");
1419: pop_braces (old_brace_level);
1420: printf ("\tregs.sr = newsr; MakeFromSR();\n");
1421: printf ("\tm68k_setpc_rte(newpc);\n");
1422: fill_prefetch_0 ();
1423: need_endlabel = 1;
1424: }
1425: /* PC is set and prefetch filled. */
1426: m68k_pc_offset = 0;
1.1.1.2 root 1427: insn_n_cycles = 20;
1.1 root 1428: break;
1429: case i_RTD:
1430: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1431: genamode (curi->smode, "srcreg", curi->size, "offs", 1, 0);
1432: printf ("\tm68k_areg(regs, 7) += offs;\n");
1433: printf ("\tm68k_setpc_rte(pc);\n");
1434: fill_prefetch_0 ();
1435: /* PC is set and prefetch filled. */
1436: m68k_pc_offset = 0;
1437: break;
1438: case i_LINK:
1439: genamode (Apdi, "7", sz_long, "old", 2, 0);
1440: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1441: genastore ("src", Apdi, "7", sz_long, "old");
1442: genastore ("m68k_areg(regs, 7)", curi->smode, "srcreg", sz_long, "src");
1443: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0);
1444: printf ("\tm68k_areg(regs, 7) += offs;\n");
1445: break;
1446: case i_UNLK:
1447: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1448: printf ("\tm68k_areg(regs, 7) = src;\n");
1449: genamode (Aipi, "7", sz_long, "old", 1, 0);
1450: genastore ("old", curi->smode, "srcreg", curi->size, "src");
1451: break;
1452: case i_RTS:
1453: printf ("\tm68k_do_rts();\n");
1454: fill_prefetch_0 ();
1455: m68k_pc_offset = 0;
1.1.1.2 root 1456: insn_n_cycles = 16;
1.1 root 1457: break;
1458: case i_TRAPV:
1459: sync_m68k_pc ();
1.1.1.9 root 1460: printf ("\tif (GET_VFLG) { Exception(7,m68k_getpc(),M68000_EXCEPTION_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 1461: need_endlabel = 1;
1462: break;
1463: case i_RTR:
1464: printf ("\tMakeSR();\n");
1465: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1466: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1467: printf ("\tregs.sr &= 0xFF00; sr &= 0xFF;\n");
1468: printf ("\tregs.sr |= sr; m68k_setpc(pc);\n");
1469: fill_prefetch_0 ();
1470: printf ("\tMakeFromSR();\n");
1471: m68k_pc_offset = 0;
1.1.1.2 root 1472: insn_n_cycles = 20;
1.1 root 1473: break;
1474: case i_JSR:
1475: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1476: printf ("\tm68k_do_jsr(m68k_getpc() + %d, srca);\n", m68k_pc_offset);
1477: fill_prefetch_0 ();
1478: m68k_pc_offset = 0;
1.1.1.2 root 1479: switch(curi->smode)
1480: {
1481: case Aind: insn_n_cycles=16; break;
1482: case Ad16: insn_n_cycles=18; break;
1483: case Ad8r: insn_n_cycles=22; break;
1484: case absw: insn_n_cycles=18; break;
1485: case absl: insn_n_cycles=20; break;
1486: case PC16: insn_n_cycles=18; break;
1487: case PC8r: insn_n_cycles=22; break;
1488: }
1.1 root 1489: break;
1490: case i_JMP:
1491: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1492: printf ("\tm68k_setpc(srca);\n");
1493: fill_prefetch_0 ();
1494: m68k_pc_offset = 0;
1.1.1.2 root 1495: switch(curi->smode)
1496: {
1497: case Aind: insn_n_cycles=8; break;
1498: case Ad16: insn_n_cycles=10; break;
1499: case Ad8r: insn_n_cycles=14; break;
1500: case absw: insn_n_cycles=10; break;
1501: case absl: insn_n_cycles=12; break;
1502: case PC16: insn_n_cycles=10; break;
1503: case PC8r: insn_n_cycles=14; break;
1504: }
1.1 root 1505: break;
1506: case i_BSR:
1507: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1508: printf ("\tuae_s32 s = (uae_s32)src + 2;\n");
1509: if (using_exception_3) {
1510: printf ("\tif (src & 1) {\n");
1.1.1.8 root 1511: printf ("\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n"); // [NP] FIXME should be +4, not +2 (same as DBcc) ?
1.1 root 1512: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + s;\n");
1.1.1.9 root 1513: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXCEPTION_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1514: printf ("\t}\n");
1515: need_endlabel = 1;
1516: }
1517: printf ("\tm68k_do_bsr(m68k_getpc() + %d, s);\n", m68k_pc_offset);
1518: fill_prefetch_0 ();
1519: m68k_pc_offset = 0;
1.1.1.2 root 1520: insn_n_cycles = 18;
1.1 root 1521: break;
1522: case i_Bcc:
1523: if (curi->size == sz_long) {
1524: if (cpu_level < 2) {
1525: printf ("\tm68k_incpc(2);\n");
1526: printf ("\tif (!cctrue(%d)) goto %s;\n", curi->cc, endlabelstr);
1527: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n");
1528: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + 1;\n");
1.1.1.9 root 1529: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXCEPTION_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1530: need_endlabel = 1;
1531: } else {
1532: if (next_cpu_level < 1)
1533: next_cpu_level = 1;
1534: }
1535: }
1536: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1537: printf ("\tif (!cctrue(%d)) goto didnt_jump;\n", curi->cc);
1538: if (using_exception_3) {
1539: printf ("\tif (src & 1) {\n");
1.1.1.8 root 1540: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n"); // [NP] FIXME should be +4, not +2 (same as DBcc) ?
1.1 root 1541: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;\n");
1.1.1.9 root 1542: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXCEPTION_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1543: printf ("\t}\n");
1544: need_endlabel = 1;
1545: }
1546: printf ("\tm68k_incpc ((uae_s32)src + 2);\n");
1547: fill_prefetch_0 ();
1.1.1.2 root 1548: printf ("\treturn 10;\n");
1.1 root 1549: printf ("didnt_jump:;\n");
1550: need_endlabel = 1;
1.1.1.2 root 1551: insn_n_cycles = (curi->size == sz_byte) ? 8 : 12;
1.1 root 1552: break;
1553: case i_LEA:
1554: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1555: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1556: genastore ("srca", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.7 root 1557: /* Set correct cycles: According to the M68K User Manual, LEA takes 12
1558: * cycles in Ad8r and PC8r mode, but it takes 14 (or 16) cycles on a real ST: */
1559: if (curi->smode == Ad8r || curi->smode == PC8r)
1560: insn_n_cycles = 14;
1.1 root 1561: break;
1562: case i_PEA:
1563: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1564: genamode (Apdi, "7", sz_long, "dst", 2, 0);
1565: genastore ("srca", Apdi, "7", sz_long, "dst");
1.1.1.7 root 1566: /* Set correct cycles: */
1.1.1.2 root 1567: switch(curi->smode)
1568: {
1569: case Aind: insn_n_cycles=12; break;
1570: case Ad16: insn_n_cycles=16; break;
1.1.1.7 root 1571: /* Note: according to the M68K User Manual, PEA takes 20 cycles for
1572: * the Ad8r mode, but on a real ST, it takes 22 (or 24) cycles! */
1573: case Ad8r: insn_n_cycles=22; break;
1.1.1.2 root 1574: case absw: insn_n_cycles=16; break;
1575: case absl: insn_n_cycles=20; break;
1576: case PC16: insn_n_cycles=16; break;
1.1.1.7 root 1577: /* Note: PEA with PC8r takes 20 cycles according to the User Manual,
1578: * but it takes 22 (or 24) cycles on a real ST: */
1579: case PC8r: insn_n_cycles=22; break;
1.1.1.2 root 1580: }
1.1 root 1581: break;
1582: case i_DBcc:
1583: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1584: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0);
1585:
1.1.1.2 root 1586: printf ("\tif (!cctrue(%d)) {\n\t", curi->cc);
1.1 root 1587: genastore ("(src-1)", curi->smode, "srcreg", curi->size, "src");
1588:
1589: printf ("\t\tif (src) {\n");
1590: if (using_exception_3) {
1591: printf ("\t\t\tif (offs & 1) {\n");
1.1.1.8 root 1592: printf ("\t\t\tlast_addr_for_exception_3 = m68k_getpc() + 2 + 2;\n"); // [NP] last_addr is pc+4, not pc+2
1.1 root 1593: printf ("\t\t\tlast_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;\n");
1.1.1.9 root 1594: printf ("\t\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXCEPTION_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1595: printf ("\t\t}\n");
1596: need_endlabel = 1;
1597: }
1598: printf ("\t\t\tm68k_incpc((uae_s32)offs + 2);\n");
1599: fill_prefetch_0 ();
1.1.1.2 root 1600: printf ("\t\t\treturn 10;\n");
1601: printf ("\t\t} else {\n\t\t\t");
1602: {
1603: int tmp_offset = m68k_pc_offset;
1604: sync_m68k_pc(); /* not so nice to call it here... */
1605: m68k_pc_offset = tmp_offset;
1606: }
1607: printf ("\t\t\treturn 14;\n");
1608: printf ("\t\t}\n");
1.1 root 1609: printf ("\t}\n");
1610: insn_n_cycles = 12;
1611: need_endlabel = 1;
1612: break;
1613: case i_Scc:
1614: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1615: start_brace ();
1616: printf ("\tint val = cctrue(%d) ? 0xff : 0;\n", curi->cc);
1617: genastore ("val", curi->smode, "srcreg", curi->size, "src");
1.1.1.8 root 1618: if (curi->smode!=Dreg) insn_n_cycles += 4;
1619: else
1620: { /* [NP] if result is TRUE, we return 6 instead of 4 */
1621: printf ("\tif (val) { m68k_incpc(2) ; return 4+2; }\n");
1622: }
1.1 root 1623: break;
1624: case i_DIVU:
1625: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1626: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1627: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1628: sync_m68k_pc ();
1629: /* Clear V flag when dividing by zero - Alcatraz Odyssey demo depends
1630: * on this (actually, it's doing a DIVS). */
1.1.1.9 root 1631: printf ("\tif (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXCEPTION_SRC_CPU); goto %s; } else {\n", endlabelstr);
1.1 root 1632: printf ("\tuae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
1633: printf ("\tuae_u32 rem = (uae_u32)dst %% (uae_u32)(uae_u16)src;\n");
1634: /* The N flag appears to be set each time there is an overflow.
1635: * Weird. */
1636: printf ("\tif (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
1637: genflags (flag_logical, sz_word, "newv", "", "");
1638: printf ("\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
1639: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1640: printf ("\t}\n");
1641: printf ("\t}\n");
1.1.1.8 root 1642: // insn_n_cycles += 136;
1643: printf ("\tretcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);\n");
1644: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 1645: need_endlabel = 1;
1646: break;
1647: case i_DIVS:
1648: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1649: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1650: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1651: sync_m68k_pc ();
1.1.1.9 root 1652: printf ("\tif (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXCEPTION_SRC_CPU); goto %s; } else {\n", endlabelstr);
1.1 root 1653: printf ("\tuae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
1654: printf ("\tuae_u16 rem = (uae_s32)dst %% (uae_s32)(uae_s16)src;\n");
1655: printf ("\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
1656: printf ("\tif (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;\n");
1657: genflags (flag_logical, sz_word, "newv", "", "");
1658: printf ("\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
1659: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1660: printf ("\t}\n");
1661: printf ("\t}\n");
1.1.1.8 root 1662: // insn_n_cycles += 154;
1663: printf ("\tretcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);\n");
1664: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 1665: need_endlabel = 1;
1666: break;
1667: case i_MULU:
1668: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1669: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0);
1670: start_brace ();
1671: printf ("\tuae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;\n");
1672: genflags (flag_logical, sz_long, "newv", "", "");
1673: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.8 root 1674: /* [NP] number of cycles is 38 + 2n + ea time ; n is the number of 1 bits in src */
1675: insn_n_cycles += 38-4; /* insn_n_cycles is already initialized to 4 instead of 0 */
1676: printf ("\twhile (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }\n");
1677: sprintf(exactCpuCycles," return (%i+retcycles*2);", insn_n_cycles);
1.1 root 1678: break;
1679: case i_MULS:
1680: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1681: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0);
1682: start_brace ();
1683: printf ("\tuae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;\n");
1.1.1.8 root 1684: printf ("\tuae_u32 src2;\n");
1.1 root 1685: genflags (flag_logical, sz_long, "newv", "", "");
1686: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.8 root 1687: /* [NP] number of cycles is 38 + 2n + ea time ; n is the number of 01 or 10 patterns in src expanded to 17 bits */
1688: insn_n_cycles += 38-4; /* insn_n_cycles is already initialized to 4 instead of 0 */
1689: printf ("\tsrc2 = ((uae_u32)src) << 1;\n");
1690: printf ("\twhile (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }\n");
1691: sprintf(exactCpuCycles," return (%i+retcycles*2);", insn_n_cycles);
1.1 root 1692: break;
1693: case i_CHK:
1694: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1695: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1696: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1.1.1.8 root 1697: sync_m68k_pc ();
1.1.1.9 root 1698: printf ("\tif ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXCEPTION_SRC_CPU); goto %s; }\n", endlabelstr);
1699: printf ("\telse if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXCEPTION_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 1700: need_endlabel = 1;
1.1.1.2 root 1701: insn_n_cycles += 6;
1.1 root 1702: break;
1703:
1704: case i_CHK2:
1705: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1706: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
1707: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1708: printf ("\t{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];\n");
1709: switch (curi->size) {
1710: case sz_byte:
1711: printf ("\tlower=(uae_s32)(uae_s8)get_byte(dsta); upper = (uae_s32)(uae_s8)get_byte(dsta+1);\n");
1712: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;\n");
1713: break;
1714: case sz_word:
1715: printf ("\tlower=(uae_s32)(uae_s16)get_word(dsta); upper = (uae_s32)(uae_s16)get_word(dsta+2);\n");
1716: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;\n");
1717: break;
1718: case sz_long:
1719: printf ("\tlower=get_long(dsta); upper = get_long(dsta+4);\n");
1720: break;
1721: default:
1722: abort ();
1723: }
1724: printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
1725: printf ("\tSET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
1.1.1.8 root 1726: sync_m68k_pc ();
1.1.1.9 root 1727: printf ("\tif ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXCEPTION_SRC_CPU); goto %s; }\n}\n", endlabelstr);
1.1 root 1728: need_endlabel = 1;
1729: break;
1730:
1731: case i_ASR:
1732: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1733: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1734: start_brace ();
1735: switch (curi->size) {
1736: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1737: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1738: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1739: default: abort ();
1740: }
1741: printf ("\tuae_u32 sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1);
1742: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1743: printf ("\tretcycles = cnt;\n");
1.1 root 1744: printf ("\tCLEAR_CZNV;\n");
1745: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1746: printf ("\t\tval = %s & (uae_u32)-sign;\n", bit_mask (curi->size));
1747: printf ("\t\tSET_CFLG (sign);\n");
1748: duplicate_carry ();
1749: if (source_is_imm1_8 (curi))
1750: printf ("\t} else {\n");
1751: else
1752: printf ("\t} else if (cnt > 0) {\n");
1753: printf ("\t\tval >>= cnt - 1;\n");
1754: printf ("\t\tSET_CFLG (val & 1);\n");
1755: duplicate_carry ();
1756: printf ("\t\tval >>= 1;\n");
1757: printf ("\t\tval |= (%s << (%d - cnt)) & (uae_u32)-sign;\n",
1758: bit_mask (curi->size),
1759: bit_size (curi->size));
1760: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
1761: printf ("\t}\n");
1762: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1763: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1764: if(curi->size==sz_long)
1765: strcpy(exactCpuCycles," return (8+retcycles*2);");
1766: else
1767: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1768: break;
1769: case i_ASL:
1770: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1771: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1772: start_brace ();
1773: switch (curi->size) {
1774: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1775: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1776: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1777: default: abort ();
1778: }
1779: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1780: printf ("\tretcycles = cnt;\n");
1.1 root 1781: printf ("\tCLEAR_CZNV;\n");
1782: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1783: printf ("\t\tSET_VFLG (val != 0);\n");
1784: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
1785: bit_size (curi->size));
1786: duplicate_carry ();
1787: printf ("\t\tval = 0;\n");
1788: if (source_is_imm1_8 (curi))
1789: printf ("\t} else {\n");
1790: else
1791: printf ("\t} else if (cnt > 0) {\n");
1792: printf ("\t\tuae_u32 mask = (%s << (%d - cnt)) & %s;\n",
1793: bit_mask (curi->size),
1794: bit_size (curi->size) - 1,
1795: bit_mask (curi->size));
1796: printf ("\t\tSET_VFLG ((val & mask) != mask && (val & mask) != 0);\n");
1797: printf ("\t\tval <<= cnt - 1;\n");
1798: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
1799: duplicate_carry ();
1800: printf ("\t\tval <<= 1;\n");
1801: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
1802: printf ("\t}\n");
1803: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1804: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1805: if(curi->size==sz_long)
1806: strcpy(exactCpuCycles," return (8+retcycles*2);");
1807: else
1808: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1809: break;
1810: case i_LSR:
1811: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1812: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1813: start_brace ();
1814: switch (curi->size) {
1815: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1816: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1817: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1818: default: abort ();
1819: }
1820: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1821: printf ("\tretcycles = cnt;\n");
1.1 root 1822: printf ("\tCLEAR_CZNV;\n");
1823: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1824: printf ("\t\tSET_CFLG ((cnt == %d) & (val >> %d));\n",
1825: bit_size (curi->size), bit_size (curi->size) - 1);
1826: duplicate_carry ();
1827: printf ("\t\tval = 0;\n");
1828: if (source_is_imm1_8 (curi))
1829: printf ("\t} else {\n");
1830: else
1831: printf ("\t} else if (cnt > 0) {\n");
1832: printf ("\t\tval >>= cnt - 1;\n");
1833: printf ("\t\tSET_CFLG (val & 1);\n");
1834: duplicate_carry ();
1835: printf ("\t\tval >>= 1;\n");
1836: printf ("\t}\n");
1837: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1838: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1839: if(curi->size==sz_long)
1840: strcpy(exactCpuCycles," return (8+retcycles*2);");
1841: else
1842: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1843: break;
1844: case i_LSL:
1845: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1846: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1847: start_brace ();
1848: switch (curi->size) {
1849: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1850: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1851: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1852: default: abort ();
1853: }
1854: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1855: printf ("\tretcycles = cnt;\n");
1.1 root 1856: printf ("\tCLEAR_CZNV;\n");
1857: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1858: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
1859: bit_size (curi->size));
1860: duplicate_carry ();
1861: printf ("\t\tval = 0;\n");
1862: if (source_is_imm1_8 (curi))
1863: printf ("\t} else {\n");
1864: else
1865: printf ("\t} else if (cnt > 0) {\n");
1866: printf ("\t\tval <<= (cnt - 1);\n");
1867: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
1868: duplicate_carry ();
1869: printf ("\t\tval <<= 1;\n");
1870: printf ("\tval &= %s;\n", bit_mask (curi->size));
1871: printf ("\t}\n");
1872: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1873: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1874: if(curi->size==sz_long)
1875: strcpy(exactCpuCycles," return (8+retcycles*2);");
1876: else
1877: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1878: break;
1879: case i_ROL:
1880: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1881: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1882: start_brace ();
1883: switch (curi->size) {
1884: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1885: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1886: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1887: default: abort ();
1888: }
1889: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1890: printf ("\tretcycles = cnt;\n");
1.1 root 1891: printf ("\tCLEAR_CZNV;\n");
1892: if (source_is_imm1_8 (curi))
1893: printf ("{");
1894: else
1895: printf ("\tif (cnt > 0) {\n");
1896: printf ("\tuae_u32 loval;\n");
1897: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
1898: printf ("\tloval = val >> (%d - cnt);\n", bit_size (curi->size));
1899: printf ("\tval <<= cnt;\n");
1900: printf ("\tval |= loval;\n");
1901: printf ("\tval &= %s;\n", bit_mask (curi->size));
1902: printf ("\tSET_CFLG (val & 1);\n");
1903: printf ("}\n");
1904: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1905: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1906: if(curi->size==sz_long)
1907: strcpy(exactCpuCycles," return (8+retcycles*2);");
1908: else
1909: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1910: break;
1911: case i_ROR:
1912: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1913: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1914: start_brace ();
1915: switch (curi->size) {
1916: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1917: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1918: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1919: default: abort ();
1920: }
1921: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1922: printf ("\tretcycles = cnt;\n");
1.1 root 1923: printf ("\tCLEAR_CZNV;\n");
1924: if (source_is_imm1_8 (curi))
1925: printf ("{");
1926: else
1927: printf ("\tif (cnt > 0) {");
1928: printf ("\tuae_u32 hival;\n");
1929: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
1930: printf ("\thival = val << (%d - cnt);\n", bit_size (curi->size));
1931: printf ("\tval >>= cnt;\n");
1932: printf ("\tval |= hival;\n");
1933: printf ("\tval &= %s;\n", bit_mask (curi->size));
1934: printf ("\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
1935: printf ("\t}\n");
1936: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1937: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1938: if(curi->size==sz_long)
1939: strcpy(exactCpuCycles," return (8+retcycles*2);");
1940: else
1941: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1942: break;
1943: case i_ROXL:
1944: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1945: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1946: start_brace ();
1947: switch (curi->size) {
1948: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1949: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1950: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1951: default: abort ();
1952: }
1953: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1954: printf ("\tretcycles = cnt;\n");
1.1 root 1955: printf ("\tCLEAR_CZNV;\n");
1956: if (source_is_imm1_8 (curi))
1957: printf ("{");
1958: else {
1959: force_range_for_rox ("cnt", curi->size);
1960: printf ("\tif (cnt > 0) {\n");
1961: }
1962: printf ("\tcnt--;\n");
1963: printf ("\t{\n\tuae_u32 carry;\n");
1964: printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
1965: printf ("\tcarry = loval & 1;\n");
1966: printf ("\tval = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);\n");
1967: printf ("\tSET_XFLG (carry);\n");
1968: printf ("\tval &= %s;\n", bit_mask (curi->size));
1969: printf ("\t} }\n");
1970: printf ("\tSET_CFLG (GET_XFLG);\n");
1971: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1972: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1973: if(curi->size==sz_long)
1974: strcpy(exactCpuCycles," return (8+retcycles*2);");
1975: else
1976: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1977: break;
1978: case i_ROXR:
1979: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1980: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1981: start_brace ();
1982: switch (curi->size) {
1983: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1984: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1985: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1986: default: abort ();
1987: }
1988: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1989: printf ("\tretcycles = cnt;\n");
1.1 root 1990: printf ("\tCLEAR_CZNV;\n");
1991: if (source_is_imm1_8 (curi))
1992: printf ("{");
1993: else {
1994: force_range_for_rox ("cnt", curi->size);
1995: printf ("\tif (cnt > 0) {\n");
1996: }
1997: printf ("\tcnt--;\n");
1998: printf ("\t{\n\tuae_u32 carry;\n");
1999: printf ("\tuae_u32 hival = (val << 1) | GET_XFLG;\n");
2000: printf ("\thival <<= (%d - cnt);\n", bit_size (curi->size) - 1);
2001: printf ("\tval >>= cnt;\n");
2002: printf ("\tcarry = val & 1;\n");
2003: printf ("\tval >>= 1;\n");
2004: printf ("\tval |= hival;\n");
2005: printf ("\tSET_XFLG (carry);\n");
2006: printf ("\tval &= %s;\n", bit_mask (curi->size));
2007: printf ("\t} }\n");
2008: printf ("\tSET_CFLG (GET_XFLG);\n");
2009: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2010: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 2011: if(curi->size==sz_long)
2012: strcpy(exactCpuCycles," return (8+retcycles*2);");
2013: else
2014: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 2015: break;
2016: case i_ASRW:
2017: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2018: start_brace ();
2019: switch (curi->size) {
2020: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2021: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2022: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2023: default: abort ();
2024: }
2025: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
2026: printf ("\tuae_u32 cflg = val & 1;\n");
2027: printf ("\tval = (val >> 1) | sign;\n");
2028: genflags (flag_logical, curi->size, "val", "", "");
2029: printf ("\tSET_CFLG (cflg);\n");
2030: duplicate_carry ();
2031: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2032: break;
2033: case i_ASLW:
2034: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2035: start_brace ();
2036: switch (curi->size) {
2037: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2038: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2039: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2040: default: abort ();
2041: }
2042: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
2043: printf ("\tuae_u32 sign2;\n");
2044: printf ("\tval <<= 1;\n");
2045: genflags (flag_logical, curi->size, "val", "", "");
2046: printf ("\tsign2 = %s & val;\n", cmask (curi->size));
2047: printf ("\tSET_CFLG (sign != 0);\n");
2048: duplicate_carry ();
2049:
2050: printf ("\tSET_VFLG (GET_VFLG | (sign2 != sign));\n");
2051: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2052: break;
2053: case i_LSRW:
2054: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2055: start_brace ();
2056: switch (curi->size) {
2057: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2058: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2059: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2060: default: abort ();
2061: }
2062: printf ("\tuae_u32 carry = val & 1;\n");
2063: printf ("\tval >>= 1;\n");
2064: genflags (flag_logical, curi->size, "val", "", "");
2065: printf ("SET_CFLG (carry);\n");
2066: duplicate_carry ();
2067: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2068: break;
2069: case i_LSLW:
2070: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2071: start_brace ();
2072: switch (curi->size) {
2073: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2074: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2075: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2076: default: abort ();
2077: }
2078: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2079: printf ("\tval <<= 1;\n");
2080: genflags (flag_logical, curi->size, "val", "", "");
2081: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2082: duplicate_carry ();
2083: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2084: break;
2085: case i_ROLW:
2086: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2087: start_brace ();
2088: switch (curi->size) {
2089: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2090: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2091: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2092: default: abort ();
2093: }
2094: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2095: printf ("\tval <<= 1;\n");
2096: printf ("\tif (carry) val |= 1;\n");
2097: genflags (flag_logical, curi->size, "val", "", "");
2098: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2099: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2100: break;
2101: case i_RORW:
2102: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2103: start_brace ();
2104: switch (curi->size) {
2105: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2106: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2107: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2108: default: abort ();
2109: }
2110: printf ("\tuae_u32 carry = val & 1;\n");
2111: printf ("\tval >>= 1;\n");
2112: printf ("\tif (carry) val |= %s;\n", cmask (curi->size));
2113: genflags (flag_logical, curi->size, "val", "", "");
2114: printf ("SET_CFLG (carry);\n");
2115: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2116: break;
2117: case i_ROXLW:
2118: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2119: start_brace ();
2120: switch (curi->size) {
2121: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2122: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2123: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2124: default: abort ();
2125: }
2126: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2127: printf ("\tval <<= 1;\n");
2128: printf ("\tif (GET_XFLG) val |= 1;\n");
2129: genflags (flag_logical, curi->size, "val", "", "");
2130: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2131: duplicate_carry ();
2132: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2133: break;
2134: case i_ROXRW:
2135: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2136: start_brace ();
2137: switch (curi->size) {
2138: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2139: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2140: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2141: default: abort ();
2142: }
2143: printf ("\tuae_u32 carry = val & 1;\n");
2144: printf ("\tval >>= 1;\n");
2145: printf ("\tif (GET_XFLG) val |= %s;\n", cmask (curi->size));
2146: genflags (flag_logical, curi->size, "val", "", "");
2147: printf ("SET_CFLG (carry);\n");
2148: duplicate_carry ();
2149: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2150: break;
2151: case i_MOVEC2:
2152: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2153: start_brace ();
2154: printf ("\tint regno = (src >> 12) & 15;\n");
2155: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
2156: printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
2157: break;
2158: case i_MOVE2C:
2159: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2160: start_brace ();
2161: printf ("\tint regno = (src >> 12) & 15;\n");
2162: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
2163: printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
2164: break;
2165: case i_CAS:
2166: {
2167: int old_brace_level;
2168: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2169: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2170: start_brace ();
2171: printf ("\tint ru = (src >> 6) & 7;\n");
2172: printf ("\tint rc = src & 7;\n");
2173: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, rc)", "dst");
2174: printf ("\tif (GET_ZFLG)");
2175: old_brace_level = n_braces;
2176: start_brace ();
2177: genastore ("(m68k_dreg(regs, ru))", curi->dmode, "dstreg", curi->size, "dst");
2178: pop_braces (old_brace_level);
2179: printf ("else");
2180: start_brace ();
2181: printf ("m68k_dreg(regs, rc) = dst;\n");
2182: pop_braces (old_brace_level);
2183: }
2184: break;
2185: case i_CAS2:
2186: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2187: printf ("\tuae_u32 rn1 = regs.regs[(extra >> 28) & 15];\n");
2188: printf ("\tuae_u32 rn2 = regs.regs[(extra >> 12) & 15];\n");
2189: if (curi->size == sz_word) {
2190: int old_brace_level = n_braces;
2191: printf ("\tuae_u16 dst1 = get_word(rn1), dst2 = get_word(rn2);\n");
2192: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
2193: printf ("\tif (GET_ZFLG) {\n");
2194: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
2195: printf ("\tif (GET_ZFLG) {\n");
2196: printf ("\tput_word(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n");
2197: printf ("\tput_word(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n");
2198: printf ("\t}}\n");
2199: pop_braces (old_brace_level);
2200: printf ("\tif (! GET_ZFLG) {\n");
2201: printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = (m68k_dreg(regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
2202: printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = (m68k_dreg(regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
2203: printf ("\t}\n");
2204: } else {
2205: int old_brace_level = n_braces;
2206: printf ("\tuae_u32 dst1 = get_long(rn1), dst2 = get_long(rn2);\n");
2207: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
2208: printf ("\tif (GET_ZFLG) {\n");
2209: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
2210: printf ("\tif (GET_ZFLG) {\n");
2211: printf ("\tput_long(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n");
2212: printf ("\tput_long(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n");
2213: printf ("\t}}\n");
2214: pop_braces (old_brace_level);
2215: printf ("\tif (! GET_ZFLG) {\n");
2216: printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = dst1;\n");
2217: printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = dst2;\n");
2218: printf ("\t}\n");
2219: }
2220: break;
2221: case i_MOVES: /* ignore DFC and SFC because we have no MMU */
2222: {
2223: int old_brace_level;
2224: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2225: printf ("\tif (extra & 0x800)\n");
2226: old_brace_level = n_braces;
2227: start_brace ();
2228: printf ("\tuae_u32 src = regs.regs[(extra >> 12) & 15];\n");
2229: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
2230: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
2231: pop_braces (old_brace_level);
2232: printf ("else");
2233: start_brace ();
2234: genamode (curi->dmode, "dstreg", curi->size, "src", 1, 0);
2235: printf ("\tif (extra & 0x8000) {\n");
2236: switch (curi->size) {
2237: case sz_byte: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;\n"); break;
2238: case sz_word: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;\n"); break;
2239: case sz_long: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = src;\n"); break;
2240: default: abort ();
2241: }
2242: printf ("\t} else {\n");
2243: genastore ("src", Dreg, "(extra >> 12) & 7", curi->size, "");
2244: printf ("\t}\n");
2245: pop_braces (old_brace_level);
2246: }
2247: break;
2248: case i_BKPT: /* only needed for hardware emulators */
2249: sync_m68k_pc ();
2250: printf ("\top_illg(opcode);\n");
2251: break;
2252: case i_CALLM: /* not present in 68030 */
2253: sync_m68k_pc ();
2254: printf ("\top_illg(opcode);\n");
2255: break;
2256: case i_RTM: /* not present in 68030 */
2257: sync_m68k_pc ();
2258: printf ("\top_illg(opcode);\n");
2259: break;
2260: case i_TRAPcc:
2261: if (curi->smode != am_unknown && curi->smode != am_illg)
2262: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
1.1.1.9 root 2263: printf ("\tif (cctrue(%d)) { Exception(7,m68k_getpc(),M68000_EXCEPTION_SRC_CPU); goto %s; }\n", curi->cc, endlabelstr);
1.1 root 2264: need_endlabel = 1;
2265: break;
2266: case i_DIVL:
2267: sync_m68k_pc ();
2268: start_brace ();
2269: printf ("\tuaecptr oldpc = m68k_getpc();\n");
2270: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2271: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2272: sync_m68k_pc ();
2273: printf ("\tm68k_divl(opcode, dst, extra, oldpc);\n");
2274: break;
2275: case i_MULL:
2276: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2277: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2278: sync_m68k_pc ();
2279: printf ("\tm68k_mull(opcode, dst, extra);\n");
2280: break;
2281: case i_BFTST:
2282: case i_BFEXTU:
2283: case i_BFCHG:
2284: case i_BFEXTS:
2285: case i_BFCLR:
2286: case i_BFFFO:
2287: case i_BFSET:
2288: case i_BFINS:
2289: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2290: genamode (curi->dmode, "dstreg", sz_long, "dst", 2, 0);
2291: start_brace ();
2292: printf ("\tuae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;\n");
2293: printf ("\tint width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;\n");
2294: if (curi->dmode == Dreg) {
2295: printf ("\tuae_u32 tmp = m68k_dreg(regs, dstreg) << (offset & 0x1f);\n");
2296: } else {
2297: printf ("\tuae_u32 tmp,bf0,bf1;\n");
2298: printf ("\tdsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);\n");
2299: printf ("\tbf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;\n");
2300: printf ("\ttmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));\n");
2301: }
2302: printf ("\ttmp >>= (32 - width);\n");
2303: printf ("\tSET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);\n");
2304: printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
2305: switch (curi->mnemo) {
2306: case i_BFTST:
2307: break;
2308: case i_BFEXTU:
2309: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n");
2310: break;
2311: case i_BFCHG:
2312: printf ("\ttmp = ~tmp;\n");
2313: break;
2314: case i_BFEXTS:
2315: printf ("\tif (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);\n");
2316: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n");
2317: break;
2318: case i_BFCLR:
2319: printf ("\ttmp = 0;\n");
2320: break;
2321: case i_BFFFO:
2322: printf ("\t{ uae_u32 mask = 1 << (width-1);\n");
2323: printf ("\twhile (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}\n");
2324: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = offset;\n");
2325: break;
2326: case i_BFSET:
2327: printf ("\ttmp = 0xffffffff;\n");
2328: break;
2329: case i_BFINS:
2330: printf ("\ttmp = m68k_dreg(regs, (extra >> 12) & 7);\n");
1.1.1.4 root 2331: printf ("\tSET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);\n");
2332: printf ("\tSET_ZFLG (tmp == 0);\n");
1.1 root 2333: break;
2334: default:
2335: break;
2336: }
2337: if (curi->mnemo == i_BFCHG
2338: || curi->mnemo == i_BFCLR
2339: || curi->mnemo == i_BFSET
2340: || curi->mnemo == i_BFINS)
2341: {
2342: printf ("\ttmp <<= (32 - width);\n");
2343: if (curi->dmode == Dreg) {
2344: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ((offset & 0x1f) == 0 ? 0 :\n");
2345: printf ("\t\t(0xffffffff << (32 - (offset & 0x1f))))) |\n");
2346: printf ("\t\t(tmp >> (offset & 0x1f)) |\n");
2347: printf ("\t\t(((offset & 0x1f) + width) >= 32 ? 0 :\n");
2348: printf (" (m68k_dreg(regs, dstreg) & ((uae_u32)0xffffffff >> ((offset & 0x1f) + width))));\n");
2349: } else {
2350: printf ("\tbf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |\n");
2351: printf ("\t\t(tmp >> (offset & 7)) |\n");
2352: printf ("\t\t(((offset & 7) + width) >= 32 ? 0 :\n");
2353: printf ("\t\t (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));\n");
2354: printf ("\tput_long(dsta,bf0 );\n");
2355: printf ("\tif (((offset & 7) + width) > 32) {\n");
2356: printf ("\t\tbf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |\n");
2357: printf ("\t\t\t(tmp << (8 - (offset & 7)));\n");
2358: printf ("\t\tput_byte(dsta+4,bf1);\n");
2359: printf ("\t}\n");
2360: }
2361: }
2362: break;
2363: case i_PACK:
2364: if (curi->smode == Dreg) {
2365: printf ("\tuae_u16 val = m68k_dreg(regs, srcreg) + %s;\n", gen_nextiword ());
2366: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);\n");
2367: } else {
2368: printf ("\tuae_u16 val;\n");
2369: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2370: printf ("\tval = (uae_u16)get_byte(m68k_areg(regs, srcreg));\n");
2371: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2372: printf ("\tval = (val | ((uae_u16)get_byte(m68k_areg(regs, srcreg)) << 8)) + %s;\n", gen_nextiword ());
2373: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2374: printf ("\tput_byte(m68k_areg(regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));\n");
2375: }
2376: break;
2377: case i_UNPK:
2378: if (curi->smode == Dreg) {
2379: printf ("\tuae_u16 val = m68k_dreg(regs, srcreg);\n");
2380: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword ());
2381: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffff0000) | (val & 0xffff);\n");
2382: } else {
2383: printf ("\tuae_u16 val;\n");
2384: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2385: printf ("\tval = (uae_u16)get_byte(m68k_areg(regs, srcreg));\n");
2386: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword ());
2387: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2388: printf ("\tput_byte(m68k_areg(regs, dstreg),val);\n");
2389: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2390: printf ("\tput_byte(m68k_areg(regs, dstreg),val >> 8);\n");
2391: }
2392: break;
2393: case i_TAS:
2394: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2395: genflags (flag_logical, curi->size, "src", "", "");
2396: printf ("\tsrc |= 0x80;\n");
2397: genastore ("src", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 2398: if( curi->smode!=Dreg ) insn_n_cycles += 2;
1.1 root 2399: break;
2400: case i_FPP:
2401: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2402: sync_m68k_pc ();
2403: printf ("\tfpp_opp(opcode,extra);\n");
2404: break;
2405: case i_FDBcc:
2406: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2407: sync_m68k_pc ();
2408: printf ("\tfdbcc_opp(opcode,extra);\n");
2409: break;
2410: case i_FScc:
2411: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2412: sync_m68k_pc ();
2413: printf ("\tfscc_opp(opcode,extra);\n");
2414: break;
2415: case i_FTRAPcc:
2416: sync_m68k_pc ();
2417: start_brace ();
2418: printf ("\tuaecptr oldpc = m68k_getpc();\n");
2419: if (curi->smode != am_unknown && curi->smode != am_illg)
2420: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
2421: sync_m68k_pc ();
2422: printf ("\tftrapcc_opp(opcode,oldpc);\n");
2423: break;
2424: case i_FBcc:
2425: sync_m68k_pc ();
2426: start_brace ();
2427: printf ("\tuaecptr pc = m68k_getpc();\n");
2428: genamode (curi->dmode, "srcreg", curi->size, "extra", 1, 0);
2429: sync_m68k_pc ();
2430: printf ("\tfbcc_opp(opcode,pc,extra);\n");
2431: break;
2432: case i_FSAVE:
2433: sync_m68k_pc ();
2434: printf ("\tfsave_opp(opcode);\n");
2435: break;
2436: case i_FRESTORE:
2437: sync_m68k_pc ();
2438: printf ("\tfrestore_opp(opcode);\n");
2439: break;
2440:
2441: case i_CINVL:
2442: case i_CINVP:
2443: case i_CINVA:
2444: case i_CPUSHL:
2445: case i_CPUSHP:
2446: case i_CPUSHA:
2447: break;
2448: case i_MOVE16:
1.1.1.4 root 2449: if ((opcode & 0xfff8) == 0xf620) {
2450: /* MOVE16 (Ax)+,(Ay)+ */
2451: printf ("\tuaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
2452: printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword());
2453: printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n");
2454: printf ("\tput_long(memd, get_long(mems));\n");
2455: printf ("\tput_long(memd+4, get_long(mems+4));\n");
2456: printf ("\tput_long(memd+8, get_long(mems+8));\n");
2457: printf ("\tput_long(memd+12, get_long(mems+12));\n");
2458: printf ("\tif (srcreg != dstreg)\n");
2459: printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2460: printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2461: } else {
2462: /* Other variants */
2463: genamode (curi->smode, "srcreg", curi->size, "mems", 0, 2);
2464: genamode (curi->dmode, "dstreg", curi->size, "memd", 0, 2);
2465: printf ("\tmemsa &= ~15;\n");
2466: printf ("\tmemda &= ~15;\n");
2467: printf ("\tput_long(memda, get_long(memsa));\n");
2468: printf ("\tput_long(memda+4, get_long(memsa+4));\n");
2469: printf ("\tput_long(memda+8, get_long(memsa+8));\n");
2470: printf ("\tput_long(memda+12, get_long(memsa+12));\n");
2471: if ((opcode & 0xfff8) == 0xf600)
2472: printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2473: else if ((opcode & 0xfff8) == 0xf608)
2474: printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2475: }
1.1 root 2476: break;
2477:
2478: case i_MMUOP:
2479: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2480: sync_m68k_pc ();
2481: printf ("\tmmu_op(opcode,extra);\n");
2482: break;
2483: default:
2484: abort ();
2485: break;
2486: }
2487: finish_braces ();
2488: sync_m68k_pc ();
2489: }
2490:
2491: static void generate_includes (FILE * f)
2492: {
2493: fprintf (f, "#include \"sysdeps.h\"\n");
2494: fprintf (f, "#include \"hatari-glue.h\"\n");
2495: fprintf (f, "#include \"maccess.h\"\n");
2496: fprintf (f, "#include \"memory.h\"\n");
2497: fprintf (f, "#include \"newcpu.h\"\n");
2498: fprintf (f, "#include \"cputbl.h\"\n");
2499: fprintf (f, "#define CPUFUNC(x) x##_ff\n"
2500: "#ifdef NOFLAGS\n"
2501: "#include \"noflags.h\"\n"
2502: "#endif\n");
2503: }
2504:
2505: static int postfix;
2506:
2507: static void generate_one_opcode (int rp)
2508: {
2509: int i;
2510: uae_u16 smsk, dmsk;
2511: long int opcode = opcode_map[rp];
2512:
1.1.1.2 root 2513: exactCpuCycles[0] = 0; /* Default: not used */
2514:
1.1 root 2515: if (table68k[opcode].mnemo == i_ILLG
2516: || table68k[opcode].clev > cpu_level)
2517: return;
2518:
2519: for (i = 0; lookuptab[i].name[0]; i++) {
2520: if (table68k[opcode].mnemo == lookuptab[i].mnemo)
2521: break;
2522: }
2523:
2524: if (table68k[opcode].handler != -1)
2525: return;
2526:
2527: if (opcode_next_clev[rp] != cpu_level) {
2528: fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp],
2529: opcode, lookuptab[i].name);
2530: return;
2531: }
2532: fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, postfix, opcode, lookuptab[i].name);
2533: fprintf (headerfile, "extern cpuop_func op_%lx_%d_nf;\n", opcode, postfix);
2534: fprintf (headerfile, "extern cpuop_func op_%lx_%d_ff;\n", opcode, postfix);
2535: printf ("unsigned long REGPARAM2 CPUFUNC(op_%lx_%d)(uae_u32 opcode) /* %s */\n{\n", opcode, postfix, lookuptab[i].name);
2536:
2537: switch (table68k[opcode].stype) {
2538: case 0: smsk = 7; break;
2539: case 1: smsk = 255; break;
2540: case 2: smsk = 15; break;
2541: case 3: smsk = 7; break;
2542: case 4: smsk = 7; break;
2543: case 5: smsk = 63; break;
1.1.1.4 root 2544: case 7: smsk = 3; break;
1.1 root 2545: default: abort ();
2546: }
2547: dmsk = 7;
2548:
2549: next_cpu_level = -1;
2550: if (table68k[opcode].suse
2551: && table68k[opcode].smode != imm && table68k[opcode].smode != imm0
2552: && table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
2553: && table68k[opcode].smode != absw && table68k[opcode].smode != absl
2554: && table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
2555: {
2556: if (table68k[opcode].spos == -1) {
2557: if (((int) table68k[opcode].sreg) >= 128)
2558: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].sreg);
2559: else
2560: printf ("\tuae_u32 srcreg = %d;\n", (int) table68k[opcode].sreg);
2561: } else {
2562: char source[100];
2563: int pos = table68k[opcode].spos;
2564:
2565: if (pos)
2566: sprintf (source, "((opcode >> %d) & %d)", pos, smsk);
2567: else
2568: sprintf (source, "(opcode & %d)", smsk);
2569:
2570: if (table68k[opcode].stype == 3)
2571: printf ("\tuae_u32 srcreg = imm8_table[%s];\n", source);
2572: else if (table68k[opcode].stype == 1)
2573: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%s;\n", source);
2574: else
2575: printf ("\tuae_u32 srcreg = %s;\n", source);
2576: }
2577: }
2578: if (table68k[opcode].duse
2579: /* Yes, the dmode can be imm, in case of LINK or DBcc */
2580: && table68k[opcode].dmode != imm && table68k[opcode].dmode != imm0
2581: && table68k[opcode].dmode != imm1 && table68k[opcode].dmode != imm2
2582: && table68k[opcode].dmode != absw && table68k[opcode].dmode != absl)
2583: {
2584: if (table68k[opcode].dpos == -1) {
2585: if (((int) table68k[opcode].dreg) >= 128)
2586: printf ("\tuae_u32 dstreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].dreg);
2587: else
2588: printf ("\tuae_u32 dstreg = %d;\n", (int) table68k[opcode].dreg);
2589: } else {
2590: int pos = table68k[opcode].dpos;
2591: #if 0
2592: /* Check that we can do the little endian optimization safely. */
2593: if (pos < 8 && (dmsk >> (8 - pos)) != 0)
2594: abort ();
2595: #endif
2596: if (pos)
2597: printf ("\tuae_u32 dstreg = (opcode >> %d) & %d;\n",
2598: pos, dmsk);
2599: else
2600: printf ("\tuae_u32 dstreg = opcode & %d;\n", dmsk);
2601: }
2602: }
2603: need_endlabel = 0;
2604: endlabelno++;
2605: sprintf (endlabelstr, "endlabel%d", endlabelno);
1.1.1.2 root 2606: if(table68k[opcode].mnemo==i_ASR || table68k[opcode].mnemo==i_ASL || table68k[opcode].mnemo==i_LSR || table68k[opcode].mnemo==i_LSL
2607: || table68k[opcode].mnemo==i_ROL || table68k[opcode].mnemo==i_ROR || table68k[opcode].mnemo==i_ROXL || table68k[opcode].mnemo==i_ROXR
1.1.1.8 root 2608: || table68k[opcode].mnemo==i_MVMEL || table68k[opcode].mnemo==i_MVMLE
2609: || table68k[opcode].mnemo==i_MULU || table68k[opcode].mnemo==i_MULS
2610: || table68k[opcode].mnemo==i_DIVU || table68k[opcode].mnemo==i_DIVS )
2611: printf("\tunsigned int retcycles = 0;\n");
1.1 root 2612: gen_opcode (opcode);
2613: if (need_endlabel)
2614: printf ("%s: ;\n", endlabelstr);
1.1.1.8 root 2615:
2616: if (strlen(exactCpuCycles) > 0)
2617: printf("%s\n",exactCpuCycles);
2618: else
2619: printf ("return %d;\n", insn_n_cycles);
2620: /* Now patch in the instruction cycles at the beginning of the function: */
2621: fseek(stdout, nCurInstrCycPos, SEEK_SET);
2622: printf("%d;", insn_n_cycles);
2623: fseek(stdout, 0, SEEK_END);
2624:
1.1 root 2625: printf ("}\n");
2626: opcode_next_clev[rp] = next_cpu_level;
2627: opcode_last_postfix[rp] = postfix;
2628: }
2629:
2630: static void generate_func (void)
2631: {
2632: int i, j, rp;
2633:
2634: using_prefetch = 0;
2635: using_exception_3 = 0;
2636: for (i = 0; i < 6; i++) {
2637: cpu_level = 4 - i;
2638: if (i == 5) {
2639: cpu_level = 0;
2640: using_prefetch = 1;
2641: using_exception_3 = 1;
2642: for (rp = 0; rp < nr_cpuop_funcs; rp++)
2643: opcode_next_clev[rp] = 0;
2644: }
2645:
2646: postfix = i;
1.1.1.7 root 2647: fprintf (stblfile, "const struct cputbl CPUFUNC(op_smalltbl_%d)[] = {\n", postfix);
1.1 root 2648:
2649: /* sam: this is for people with low memory (eg. me :)) */
2650: printf ("\n"
2651: "#if !defined(PART_1) && !defined(PART_2) && "
2652: "!defined(PART_3) && !defined(PART_4) && "
2653: "!defined(PART_5) && !defined(PART_6) && "
2654: "!defined(PART_7) && !defined(PART_8)"
2655: "\n"
2656: "#define PART_1 1\n"
2657: "#define PART_2 1\n"
2658: "#define PART_3 1\n"
2659: "#define PART_4 1\n"
2660: "#define PART_5 1\n"
2661: "#define PART_6 1\n"
2662: "#define PART_7 1\n"
2663: "#define PART_8 1\n"
2664: "#endif\n\n");
2665:
2666: rp = 0;
2667: for(j=1;j<=8;++j) {
2668: int k = (j*nr_cpuop_funcs)/8;
2669: printf ("#ifdef PART_%d\n",j);
2670: for (; rp < k; rp++)
2671: generate_one_opcode (rp);
2672: printf ("#endif\n\n");
2673: }
2674:
2675: fprintf (stblfile, "{ 0, 0, 0 }};\n");
2676: }
2677:
2678: }
2679:
2680: int main (int argc, char **argv)
2681: {
2682: read_table68k ();
2683: do_merges ();
2684:
2685: opcode_map = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2686: opcode_last_postfix = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2687: opcode_next_clev = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2688: counts = (unsigned long *) malloc (65536 * sizeof (unsigned long));
2689: read_counts ();
2690:
2691: /* It would be a lot nicer to put all in one file (we'd also get rid of
2692: * cputbl.h that way), but cpuopti can't cope. That could be fixed, but
2693: * I don't dare to touch the 68k version. */
2694:
2695: headerfile = fopen ("cputbl.h", "wb");
2696: stblfile = fopen ("cpustbl.c", "wb");
2697: freopen ("cpuemu.c", "wb", stdout);
2698:
2699: generate_includes (stdout);
2700: generate_includes (stblfile);
2701:
2702: generate_func ();
2703:
2704: free (table68k);
2705: return 0;
2706: }
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