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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation generator
5: *
6: * This is a fairly stupid program that generates a lot of case labels that
7: * can be #included in a switch statement.
8: * As an alternative, it can generate functions that handle specific
9: * MC68000 instructions, plus a prototype header file and a function pointer
10: * array to look up the function for an opcode.
11: * Error checking is bad, an illegal table68k file will cause the program to
12: * call abort().
13: * The generated code is sometimes sub-optimal, an optimizing compiler should
14: * take care of this.
15: *
16: * The source for the insn timings is Markt & Technik's Amiga Magazin 8/1992.
17: *
18: * Copyright 1995, 1996, 1997, 1998, 1999, 2000 Bernd Schmidt
1.1.1.2 root 19: *
20: * Adaptation to Hatari and better cpu timings by Thomas Huth
21: *
1.1.1.4 root 22: * This file is distributed under the GNU Public License, version 2 or at
23: * your option any later version. Read the file gpl.txt for details.
1.1 root 24: */
1.1.1.8 root 25:
26:
27: /* 2007/03/xx [NP] Use add_cycles.pl to set 'CurrentInstrCycles' in each opcode. */
28: /* 2007/04/09 [NP] Correct CLR : on 68000, CLR reads the memory before clearing it (but we should */
29: /* not add cycles for reading). This means CLR can give 2 wait states (one for */
30: /* read and one for right) (clr.b $fa1b.w in Decade's Demo Main Menu). */
31: /* 2007/04/14 [NP] - Although dest -(an) normally takes 2 cycles, this is not the case for move : */
32: /* move dest (an), (an)+ and -(an) all take the same time (curi->dmode == Apdi) */
33: /* (Syntax Terror Demo Reset). */
34: /* - Scc takes 6 cycles instead of 4 if the result is true (Ventura Demo Loader). */
35: /* - Store the family of the current opcode into OpcodeFamily : used to check */
36: /* instruction pairing on ST into m68000.c */
37: /* 2007/04/17 [NP] Add support for cycle accurate MULU (No Cooper Greeting Screen). */
38: /* 2007/04/24 [NP] BCLR #n,Dx takes 12 cycles instead of 14 if n<16 (ULM Demo Menu). */
39: /* 2007/04/25 [NP] On ST, d8(An,Xn) and d8(PC,Xn) take 2 cycles more than the official 68000's */
40: /* table (ULM Demo Menu). */
41: /* 2007/11/12 [NP] Add refill_prefetch for i_ADD to fix Transbeauce 2 demo self modified code. */
42: /* Ugly hack, we need better prefetch emulation (switch to winuae gencpu.c) */
43: /* 2007/11/25 [NP] In i_DBcc, in case of address error, last_addr_for_exception_3 should be */
44: /* pc+4, not pc+2 (Transbeauce 2 demo) (e.g. 'dbf d0,#$fff5'). */
45: /* This means the value pushed on the frame stack should be the address of the */
46: /* instruction following the one generating the address error. */
47: /* FIXME : this should be the case for i_BSR and i_BCC too (need to check on */
48: /* a real 68000). */
49: /* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */
50: /* Cwik, [email protected]). */
51: /* 2007/12/08 [NP] In case of CHK/CHK2 exception, PC stored on the stack wasn't pointing to the */
52: /* next instruction but to the current CHK/CHK2 instruction (Transbeauce 2 demo). */
53: /* We need to call 'sync_m68k_pc' before calling 'Exception'. */
54: /* 2007/12/09 [NP] CHK.L (e.g. $4700) doesn't exist on 68000 and should be considered as an illegal*/
55: /* instruction (Transbeauce 2 demo) -> change in table68k. */
56: /* 2008/01/24 [NP] BCLR Dy,Dx takes 8 cycles instead of 10 if Dy<16 (Fullshade in Anomaly Demos). */
57: /* 2008/01/26 [NP] On ST, d8(An,Xn) takes 2 cycles more when used with ADDA/SUBA (ULM Demo Menu) */
58: /* but not when used with MOVE (e.g. 'move.l 0(a5,d1),(a4)' takes 26 cycles and so */
59: /* can pair with a lsr) (Anomaly Demo Intro). */
1.1.1.9 root 60: /* 2008/04/26 [NP] Handle sz_byte for Areg in genamode, as 'move.b a1,(a0)' ($1089) is possible */
61: /* on ST (fix Blood Money on Superior 65) */
1.1.1.8 root 62:
63:
1.1.1.11! root 64: const char GenCpu_fileid[] = "Hatari gencpu.c : " __DATE__ " " __TIME__;
1.1 root 65:
66: #include <ctype.h>
1.1.1.3 root 67: #include <string.h>
1.1 root 68:
69: #include "sysdeps.h"
70: #include "readcpu.h"
71:
72: #define BOOL_TYPE "int"
73:
74: static FILE *headerfile;
75: static FILE *stblfile;
76:
77: static int using_prefetch;
78: static int using_exception_3;
79: static int cpu_level;
80:
1.1.1.2 root 81: char exactCpuCycles[256]; /* Space to store return string for exact cpu cycles */
82:
1.1.1.8 root 83: long nCurInstrCycPos; /* Stores where we have to patch in the current cycles value */
1.1.1.2 root 84:
1.1 root 85: /* For the current opcode, the next lower level that will have different code.
86: * Initialized to -1 for each opcode. If it remains unchanged, indicates we
87: * are done with that opcode. */
88: static int next_cpu_level;
89: static int *opcode_map;
90: static int *opcode_next_clev;
91: static int *opcode_last_postfix;
92: static unsigned long *counts;
93:
1.1.1.6 root 94:
1.1 root 95: static void read_counts (void)
96: {
97: FILE *file;
98: unsigned long opcode, count, total;
99: char name[20];
100: int nr = 0;
101: memset (counts, 0, 65536 * sizeof *counts);
102:
103: file = fopen ("frequent.68k", "r");
104: if (file) {
1.1.1.11! root 105: if (fscanf (file, "Total: %lu\n", &total) == EOF) {
! 106: perror("read_counts");
! 107: }
1.1 root 108: while (fscanf (file, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
109: opcode_next_clev[nr] = 4;
110: opcode_last_postfix[nr] = -1;
111: opcode_map[nr++] = opcode;
112: counts[opcode] = count;
113: }
114: fclose (file);
115: }
116: if (nr == nr_cpuop_funcs)
117: return;
118: for (opcode = 0; opcode < 0x10000; opcode++) {
119: if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
120: && counts[opcode] == 0)
121: {
122: opcode_next_clev[nr] = 4;
123: opcode_last_postfix[nr] = -1;
124: opcode_map[nr++] = opcode;
125: counts[opcode] = count;
126: }
127: }
128: if (nr != nr_cpuop_funcs)
129: abort ();
130: }
131:
132: static char endlabelstr[80];
133: static int endlabelno = 0;
134: static int need_endlabel;
135:
136: static int n_braces = 0;
137: static int m68k_pc_offset = 0;
138: static int insn_n_cycles;
139:
140: static void start_brace (void)
141: {
142: n_braces++;
143: printf ("{");
144: }
145:
146: static void close_brace (void)
147: {
148: assert (n_braces > 0);
149: n_braces--;
150: printf ("}");
151: }
152:
153: static void finish_braces (void)
154: {
155: while (n_braces > 0)
156: close_brace ();
157: }
158:
159: static void pop_braces (int to)
160: {
161: while (n_braces > to)
162: close_brace ();
163: }
164:
165: static int bit_size (int size)
166: {
167: switch (size) {
168: case sz_byte: return 8;
169: case sz_word: return 16;
170: case sz_long: return 32;
171: default: abort ();
172: }
173: return 0;
174: }
175:
176: static const char *bit_mask (int size)
177: {
178: switch (size) {
179: case sz_byte: return "0xff";
180: case sz_word: return "0xffff";
181: case sz_long: return "0xffffffff";
182: default: abort ();
183: }
184: return 0;
185: }
186:
187: static const char *gen_nextilong (void)
188: {
189: static char buffer[80];
190: int r = m68k_pc_offset;
191: m68k_pc_offset += 4;
192:
193: insn_n_cycles += 8;
194:
195: if (using_prefetch)
196: sprintf (buffer, "get_ilong_prefetch(%d)", r);
197: else
198: sprintf (buffer, "get_ilong(%d)", r);
199: return buffer;
200: }
201:
202: static const char *gen_nextiword (void)
203: {
204: static char buffer[80];
205: int r = m68k_pc_offset;
206: m68k_pc_offset += 2;
207:
208: insn_n_cycles += 4;
209:
210: if (using_prefetch)
211: sprintf (buffer, "get_iword_prefetch(%d)", r);
212: else
213: sprintf (buffer, "get_iword(%d)", r);
214: return buffer;
215: }
216:
217: static const char *gen_nextibyte (void)
218: {
219: static char buffer[80];
220: int r = m68k_pc_offset;
221: m68k_pc_offset += 2;
222:
223: insn_n_cycles += 4;
224:
225: if (using_prefetch)
226: sprintf (buffer, "get_ibyte_prefetch(%d)", r);
227: else
228: sprintf (buffer, "get_ibyte(%d)", r);
229: return buffer;
230: }
231:
232: static void fill_prefetch_0 (void)
233: {
234: if (using_prefetch)
235: printf ("fill_prefetch_0 ();\n");
236: }
237:
238: static void fill_prefetch_2 (void)
239: {
240: if (using_prefetch)
241: printf ("fill_prefetch_2 ();\n");
242: }
243:
244: static void sync_m68k_pc (void)
245: {
246: if (m68k_pc_offset == 0)
247: return;
248: printf ("m68k_incpc(%d);\n", m68k_pc_offset);
249: switch (m68k_pc_offset) {
250: case 0:
251: /*fprintf (stderr, "refilling prefetch at 0\n"); */
252: break;
253: case 2:
254: fill_prefetch_2 ();
255: break;
256: default:
257: fill_prefetch_0 ();
258: break;
259: }
260: m68k_pc_offset = 0;
261: }
262:
263: /* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
1.1.1.4 root 264: * the calling routine handles Apdi and Aipi modes.
265: * gb-- movem == 2 means the same thing but for a MOVE16 instruction */
1.1 root 266: static void genamode (amodes mode, char *reg, wordsizes size, char *name, int getv, int movem)
267: {
268: start_brace ();
269: switch (mode) {
270: case Dreg:
271: if (movem)
272: abort ();
273: if (getv == 1)
274: switch (size) {
275: case sz_byte:
276: printf ("\tuae_s8 %s = m68k_dreg(regs, %s);\n", name, reg);
277: break;
278: case sz_word:
279: printf ("\tuae_s16 %s = m68k_dreg(regs, %s);\n", name, reg);
280: break;
281: case sz_long:
282: printf ("\tuae_s32 %s = m68k_dreg(regs, %s);\n", name, reg);
283: break;
284: default:
285: abort ();
286: }
287: return;
288: case Areg:
289: if (movem)
290: abort ();
291: if (getv == 1)
292: switch (size) {
1.1.1.9 root 293: case sz_byte: // [NP] Areg with .b is possible in MOVE source */
294: printf ("\tuae_s8 %s = m68k_areg(regs, %s);\n", name, reg);
295: break;
1.1 root 296: case sz_word:
297: printf ("\tuae_s16 %s = m68k_areg(regs, %s);\n", name, reg);
298: break;
299: case sz_long:
300: printf ("\tuae_s32 %s = m68k_areg(regs, %s);\n", name, reg);
301: break;
302: default:
303: abort ();
304: }
305: return;
306: case Aind:
307: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
308: break;
309: case Aipi:
310: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
311: break;
312: case Apdi:
313: insn_n_cycles += 2;
314: switch (size) {
315: case sz_byte:
316: if (movem)
317: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
318: else
319: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - areg_byteinc[%s];\n", name, reg, reg);
320: break;
321: case sz_word:
322: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 2);
323: break;
324: case sz_long:
325: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 4);
326: break;
327: default:
328: abort ();
329: }
330: break;
331: case Ad16:
332: printf ("\tuaecptr %sa = m68k_areg(regs, %s) + (uae_s32)(uae_s16)%s;\n", name, reg, gen_nextiword ());
333: break;
334: case Ad8r:
335: insn_n_cycles += 2;
336: if (cpu_level > 1) {
337: if (next_cpu_level < 1)
338: next_cpu_level = 1;
339: sync_m68k_pc ();
340: start_brace ();
341: /* This would ordinarily be done in gen_nextiword, which we bypass. */
342: insn_n_cycles += 4;
343: printf ("\tuaecptr %sa = get_disp_ea_020(m68k_areg(regs, %s), next_iword());\n", name, reg);
1.1.1.8 root 344: } else {
1.1 root 345: printf ("\tuaecptr %sa = get_disp_ea_000(m68k_areg(regs, %s), %s);\n", name, reg, gen_nextiword ());
1.1.1.8 root 346: }
1.1 root 347:
348: break;
349: case PC16:
350: printf ("\tuaecptr %sa = m68k_getpc () + %d;\n", name, m68k_pc_offset);
351: printf ("\t%sa += (uae_s32)(uae_s16)%s;\n", name, gen_nextiword ());
352: break;
353: case PC8r:
354: insn_n_cycles += 2;
355: if (cpu_level > 1) {
356: if (next_cpu_level < 1)
357: next_cpu_level = 1;
358: sync_m68k_pc ();
359: start_brace ();
360: /* This would ordinarily be done in gen_nextiword, which we bypass. */
361: insn_n_cycles += 4;
362: printf ("\tuaecptr tmppc = m68k_getpc();\n");
363: printf ("\tuaecptr %sa = get_disp_ea_020(tmppc, next_iword());\n", name);
364: } else {
365: printf ("\tuaecptr tmppc = m68k_getpc() + %d;\n", m68k_pc_offset);
366: printf ("\tuaecptr %sa = get_disp_ea_000(tmppc, %s);\n", name, gen_nextiword ());
367: }
368:
369: break;
370: case absw:
371: printf ("\tuaecptr %sa = (uae_s32)(uae_s16)%s;\n", name, gen_nextiword ());
372: break;
373: case absl:
374: printf ("\tuaecptr %sa = %s;\n", name, gen_nextilong ());
375: break;
376: case imm:
377: if (getv != 1)
378: abort ();
379: switch (size) {
380: case sz_byte:
381: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte ());
382: break;
383: case sz_word:
384: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword ());
385: break;
386: case sz_long:
387: printf ("\tuae_s32 %s = %s;\n", name, gen_nextilong ());
388: break;
389: default:
390: abort ();
391: }
392: return;
393: case imm0:
394: if (getv != 1)
395: abort ();
396: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte ());
397: return;
398: case imm1:
399: if (getv != 1)
400: abort ();
401: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword ());
402: return;
403: case imm2:
404: if (getv != 1)
405: abort ();
406: printf ("\tuae_s32 %s = %s;\n", name, gen_nextilong ());
407: return;
408: case immi:
409: if (getv != 1)
410: abort ();
411: printf ("\tuae_u32 %s = %s;\n", name, reg);
412: return;
413: default:
414: abort ();
415: }
416:
417: /* We get here for all non-reg non-immediate addressing modes to
418: * actually fetch the value. */
419:
420: if (using_exception_3 && getv != 0 && size != sz_byte) {
421: printf ("\tif ((%sa & 1) != 0) {\n", name);
422: printf ("\t\tlast_fault_for_exception_3 = %sa;\n", name);
423: printf ("\t\tlast_op_for_exception_3 = opcode;\n");
424: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + %d;\n", m68k_pc_offset);
1.1.1.9 root 425: printf ("\t\tException(3, 0, M68000_EXCEPTION_SRC_CPU);\n");
1.1 root 426: printf ("\t\tgoto %s;\n", endlabelstr);
427: printf ("\t}\n");
428: need_endlabel = 1;
429: start_brace ();
430: }
431:
432: if (getv == 1) {
433: switch (size) {
434: case sz_byte: insn_n_cycles += 4; break;
435: case sz_word: insn_n_cycles += 4; break;
436: case sz_long: insn_n_cycles += 8; break;
437: default: abort ();
438: }
439: start_brace ();
440: switch (size) {
441: case sz_byte: printf ("\tuae_s8 %s = get_byte(%sa);\n", name, name); break;
442: case sz_word: printf ("\tuae_s16 %s = get_word(%sa);\n", name, name); break;
443: case sz_long: printf ("\tuae_s32 %s = get_long(%sa);\n", name, name); break;
444: default: abort ();
445: }
446: }
447:
448: /* We now might have to fix up the register for pre-dec or post-inc
449: * addressing modes. */
450: if (!movem)
451: switch (mode) {
452: case Aipi:
453: switch (size) {
454: case sz_byte:
455: printf ("\tm68k_areg(regs, %s) += areg_byteinc[%s];\n", reg, reg);
456: break;
457: case sz_word:
458: printf ("\tm68k_areg(regs, %s) += 2;\n", reg);
459: break;
460: case sz_long:
461: printf ("\tm68k_areg(regs, %s) += 4;\n", reg);
462: break;
463: default:
464: abort ();
465: }
466: break;
467: case Apdi:
468: printf ("\tm68k_areg (regs, %s) = %sa;\n", reg, name);
469: break;
470: default:
471: break;
472: }
473: }
474:
475: static void genastore (char *from, amodes mode, char *reg, wordsizes size, char *to)
476: {
477: switch (mode) {
478: case Dreg:
479: switch (size) {
480: case sz_byte:
481: printf ("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from);
482: break;
483: case sz_word:
484: printf ("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from);
485: break;
486: case sz_long:
487: printf ("\tm68k_dreg(regs, %s) = (%s);\n", reg, from);
488: break;
489: default:
490: abort ();
491: }
492: break;
493: case Areg:
494: switch (size) {
495: case sz_word:
496: fprintf (stderr, "Foo\n");
497: printf ("\tm68k_areg(regs, %s) = (uae_s32)(uae_s16)(%s);\n", reg, from);
498: break;
499: case sz_long:
500: printf ("\tm68k_areg(regs, %s) = (%s);\n", reg, from);
501: break;
502: default:
503: abort ();
504: }
505: break;
506: case Aind:
507: case Aipi:
508: case Apdi:
509: case Ad16:
510: case Ad8r:
511: case absw:
512: case absl:
513: case PC16:
514: case PC8r:
515: if (using_prefetch)
516: sync_m68k_pc ();
517: switch (size) {
518: case sz_byte:
519: insn_n_cycles += 4;
520: printf ("\tput_byte(%sa,%s);\n", to, from);
521: break;
522: case sz_word:
523: insn_n_cycles += 4;
524: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
525: abort ();
526: printf ("\tput_word(%sa,%s);\n", to, from);
527: break;
528: case sz_long:
529: insn_n_cycles += 8;
530: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
531: abort ();
532: printf ("\tput_long(%sa,%s);\n", to, from);
533: break;
534: default:
535: abort ();
536: }
537: break;
538: case imm:
539: case imm0:
540: case imm1:
541: case imm2:
542: case immi:
543: abort ();
544: break;
545: default:
546: abort ();
547: }
548: }
549:
1.1.1.2 root 550:
1.1 root 551: static void genmovemel (uae_u16 opcode)
552: {
553: char getcode[100];
1.1.1.3 root 554: int bMovemLong = (table68k[opcode].size == sz_long);
555: int size = bMovemLong ? 4 : 2;
1.1 root 556:
1.1.1.3 root 557: if (bMovemLong) {
1.1 root 558: strcpy (getcode, "get_long(srca)");
559: } else {
560: strcpy (getcode, "(uae_s32)(uae_s16)get_word(srca)");
561: }
562:
563: printf ("\tuae_u16 mask = %s;\n", gen_nextiword ());
564: printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1.1.1.2 root 565: printf ("\tretcycles = 0;\n");
1.1.1.3 root 566: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1);
1.1 root 567: start_brace ();
1.1.1.2 root 568: printf ("\twhile (dmask) { m68k_dreg(regs, movem_index1[dmask]) = %s;"
1.1.1.3 root 569: " srca += %d; dmask = movem_next[dmask]; retcycles+=%d; }\n",
570: getcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 571: printf ("\twhile (amask) { m68k_areg(regs, movem_index1[amask]) = %s;"
1.1.1.3 root 572: " srca += %d; amask = movem_next[amask]; retcycles+=%d; }\n",
573: getcode, size, (bMovemLong ? 8 : 4));
1.1 root 574:
575: if (table68k[opcode].dmode == Aipi)
576: printf ("\tm68k_areg(regs, dstreg) = srca;\n");
1.1.1.2 root 577:
578: /* Better cycles - experimental! (Thothy) */
579: switch(table68k[opcode].dmode)
1.1.1.3 root 580: {
1.1.1.2 root 581: case Aind: insn_n_cycles=12; break;
582: case Aipi: insn_n_cycles=12; break;
583: case Ad16: insn_n_cycles=16; break;
584: case Ad8r: insn_n_cycles=18; break;
585: case absw: insn_n_cycles=16; break;
586: case absl: insn_n_cycles=20; break;
587: case PC16: insn_n_cycles=16; break;
588: case PC8r: insn_n_cycles=18; break;
1.1.1.3 root 589: }
590: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 591: }
592:
593: static void genmovemle (uae_u16 opcode)
594: {
595: char putcode[100];
1.1.1.3 root 596: int bMovemLong = (table68k[opcode].size == sz_long);
597: int size = bMovemLong ? 4 : 2;
598:
599: if (bMovemLong) {
1.1 root 600: strcpy (putcode, "put_long(srca,");
601: } else {
602: strcpy (putcode, "put_word(srca,");
603: }
604:
605: printf ("\tuae_u16 mask = %s;\n", gen_nextiword ());
1.1.1.3 root 606: printf ("\tretcycles = 0;\n");
1.1 root 607: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1);
608: if (using_prefetch)
609: sync_m68k_pc ();
610:
611: start_brace ();
612: if (table68k[opcode].dmode == Apdi) {
1.1.1.2 root 613: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
614: printf ("\twhile (amask) { srca -= %d; %s m68k_areg(regs, movem_index2[amask]));"
1.1.1.3 root 615: " amask = movem_next[amask]; retcycles+=%d; }\n",
616: size, putcode, (bMovemLong ? 8 : 4));
1.1.1.2 root 617: printf ("\twhile (dmask) { srca -= %d; %s m68k_dreg(regs, movem_index2[dmask]));"
1.1.1.3 root 618: " dmask = movem_next[dmask]; retcycles+=%d; }\n",
619: size, putcode, (bMovemLong ? 8 : 4));
1.1.1.2 root 620: printf ("\tm68k_areg(regs, dstreg) = srca;\n");
1.1 root 621: } else {
1.1.1.2 root 622: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
623: printf ("\twhile (dmask) { %s m68k_dreg(regs, movem_index1[dmask])); srca += %d;"
1.1.1.3 root 624: " dmask = movem_next[dmask]; retcycles+=%d; }\n",
625: putcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 626: printf ("\twhile (amask) { %s m68k_areg(regs, movem_index1[amask])); srca += %d;"
1.1.1.3 root 627: " amask = movem_next[amask]; retcycles+=%d; }\n",
628: putcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 629: }
630:
631: /* Better cycles - experimental! (Thothy) */
632: switch(table68k[opcode].dmode)
1.1.1.3 root 633: {
1.1.1.2 root 634: case Aind: insn_n_cycles=8; break;
635: case Apdi: insn_n_cycles=8; break;
636: case Ad16: insn_n_cycles=12; break;
637: case Ad8r: insn_n_cycles=14; break;
638: case absw: insn_n_cycles=12; break;
639: case absl: insn_n_cycles=16; break;
1.1.1.3 root 640: }
641: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 642: }
643:
1.1.1.2 root 644:
1.1 root 645: static void duplicate_carry (void)
646: {
647: printf ("\tCOPY_CARRY;\n");
648: }
649:
650: typedef enum
651: {
652: flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_zn,
653: flag_av, flag_sv
654: }
655: flagtypes;
656:
657: static void genflags_normal (flagtypes type, wordsizes size, char *value, char *src, char *dst)
658: {
659: char vstr[100], sstr[100], dstr[100];
660: char usstr[100], udstr[100];
661: char unsstr[100], undstr[100];
662:
663: switch (size) {
664: case sz_byte:
665: strcpy (vstr, "((uae_s8)(");
666: strcpy (usstr, "((uae_u8)(");
667: break;
668: case sz_word:
669: strcpy (vstr, "((uae_s16)(");
670: strcpy (usstr, "((uae_u16)(");
671: break;
672: case sz_long:
673: strcpy (vstr, "((uae_s32)(");
674: strcpy (usstr, "((uae_u32)(");
675: break;
676: default:
677: abort ();
678: }
679: strcpy (unsstr, usstr);
680:
681: strcpy (sstr, vstr);
682: strcpy (dstr, vstr);
683: strcat (vstr, value);
684: strcat (vstr, "))");
685: strcat (dstr, dst);
686: strcat (dstr, "))");
687: strcat (sstr, src);
688: strcat (sstr, "))");
689:
690: strcpy (udstr, usstr);
691: strcat (udstr, dst);
692: strcat (udstr, "))");
693: strcat (usstr, src);
694: strcat (usstr, "))");
695:
696: strcpy (undstr, unsstr);
697: strcat (unsstr, "-");
698: strcat (undstr, "~");
699: strcat (undstr, dst);
700: strcat (undstr, "))");
701: strcat (unsstr, src);
702: strcat (unsstr, "))");
703:
704: switch (type) {
705: case flag_logical_noclobber:
706: case flag_logical:
707: case flag_zn:
708: case flag_av:
709: case flag_sv:
710: case flag_addx:
711: case flag_subx:
712: break;
713:
714: case flag_add:
715: start_brace ();
716: printf ("uae_u32 %s = %s + %s;\n", value, dstr, sstr);
717: break;
718: case flag_sub:
719: case flag_cmp:
720: start_brace ();
721: printf ("uae_u32 %s = %s - %s;\n", value, dstr, sstr);
722: break;
723: }
724:
725: switch (type) {
726: case flag_logical_noclobber:
727: case flag_logical:
728: case flag_zn:
729: break;
730:
731: case flag_add:
732: case flag_sub:
733: case flag_addx:
734: case flag_subx:
735: case flag_cmp:
736: case flag_av:
737: case flag_sv:
738: start_brace ();
739: printf ("\t" BOOL_TYPE " flgs = %s < 0;\n", sstr);
740: printf ("\t" BOOL_TYPE " flgo = %s < 0;\n", dstr);
741: printf ("\t" BOOL_TYPE " flgn = %s < 0;\n", vstr);
742: break;
743: }
744:
745: switch (type) {
746: case flag_logical:
747: printf ("\tCLEAR_CZNV;\n");
748: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
749: printf ("\tSET_NFLG (%s < 0);\n", vstr);
750: break;
751: case flag_logical_noclobber:
752: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
753: printf ("\tSET_NFLG (%s < 0);\n", vstr);
754: break;
755: case flag_av:
756: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
757: break;
758: case flag_sv:
759: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
760: break;
761: case flag_zn:
762: printf ("\tSET_ZFLG (GET_ZFLG & (%s == 0));\n", vstr);
763: printf ("\tSET_NFLG (%s < 0);\n", vstr);
764: break;
765: case flag_add:
766: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
767: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
768: printf ("\tSET_CFLG (%s < %s);\n", undstr, usstr);
769: duplicate_carry ();
770: printf ("\tSET_NFLG (flgn != 0);\n");
771: break;
772: case flag_sub:
773: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
774: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
775: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
776: duplicate_carry ();
777: printf ("\tSET_NFLG (flgn != 0);\n");
778: break;
779: case flag_addx:
780: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n"); /* minterm SON: 0x42 */
781: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));\n"); /* minterm SON: 0xD4 */
782: duplicate_carry ();
783: break;
784: case flag_subx:
785: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));\n"); /* minterm SON: 0x24 */
786: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));\n"); /* minterm SON: 0xB2 */
787: duplicate_carry ();
788: break;
789: case flag_cmp:
790: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
791: printf ("\tSET_VFLG ((flgs != flgo) && (flgn != flgo));\n");
792: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
793: printf ("\tSET_NFLG (flgn != 0);\n");
794: break;
795: }
796: }
797:
798: static void genflags (flagtypes type, wordsizes size, char *value, char *src, char *dst)
799: {
800: /* Temporarily deleted 68k/ARM flag optimizations. I'd prefer to have
801: them in the appropriate m68k.h files and use just one copy of this
802: code here. The API can be changed if necessary. */
803: #ifdef OPTIMIZED_FLAGS
804: switch (type) {
805: case flag_add:
806: case flag_sub:
807: start_brace ();
808: printf ("\tuae_u32 %s;\n", value);
809: break;
810:
811: default:
812: break;
813: }
814:
815: /* At least some of those casts are fairly important! */
816: switch (type) {
817: case flag_logical_noclobber:
818: printf ("\t{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
819: if (strcmp (value, "0") == 0) {
820: printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n");
821: } else {
822: switch (size) {
823: case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
824: case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
825: case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
826: }
827: printf ("\tIOR_CZNV (oldcznv);\n");
828: }
829: printf ("\t}\n");
830: return;
831: case flag_logical:
832: if (strcmp (value, "0") == 0) {
833: printf ("\tSET_CZNV (FLAGVAL_Z);\n");
834: } else {
835: switch (size) {
836: case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
837: case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
838: case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
839: }
840: }
841: return;
842:
843: case flag_add:
844: switch (size) {
845: case sz_byte: printf ("\toptflag_addb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
846: case sz_word: printf ("\toptflag_addw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
847: case sz_long: printf ("\toptflag_addl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
848: }
849: return;
850:
851: case flag_sub:
852: switch (size) {
853: case sz_byte: printf ("\toptflag_subb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
854: case sz_word: printf ("\toptflag_subw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
855: case sz_long: printf ("\toptflag_subl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
856: }
857: return;
858:
859: case flag_cmp:
860: switch (size) {
861: case sz_byte: printf ("\toptflag_cmpb ((uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
862: case sz_word: printf ("\toptflag_cmpw ((uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
863: case sz_long: printf ("\toptflag_cmpl ((uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
864: }
865: return;
866:
867: default:
868: break;
869: }
870: #endif
871:
872: genflags_normal (type, size, value, src, dst);
873: }
874:
875: static void force_range_for_rox (const char *var, wordsizes size)
876: {
877: /* Could do a modulo operation here... which one is faster? */
878: switch (size) {
879: case sz_long:
880: printf ("\tif (%s >= 33) %s -= 33;\n", var, var);
881: break;
882: case sz_word:
883: printf ("\tif (%s >= 34) %s -= 34;\n", var, var);
884: printf ("\tif (%s >= 17) %s -= 17;\n", var, var);
885: break;
886: case sz_byte:
887: printf ("\tif (%s >= 36) %s -= 36;\n", var, var);
888: printf ("\tif (%s >= 18) %s -= 18;\n", var, var);
889: printf ("\tif (%s >= 9) %s -= 9;\n", var, var);
890: break;
891: }
892: }
893:
894: static const char *cmask (wordsizes size)
895: {
896: switch (size) {
897: case sz_byte: return "0x80";
898: case sz_word: return "0x8000";
899: case sz_long: return "0x80000000";
900: default: abort ();
901: }
902: }
903:
904: static int source_is_imm1_8 (struct instr *i)
905: {
906: return i->stype == 3;
907: }
908:
1.1.1.2 root 909:
910:
1.1 root 911: static void gen_opcode (unsigned long int opcode)
912: {
1.1.1.2 root 913: #if 0
914: char *amodenames[] = { "Dreg", "Areg", "Aind", "Aipi", "Apdi", "Ad16", "Ad8r",
915: "absw", "absl", "PC16", "PC8r", "imm", "imm0", "imm1", "imm2", "immi", "am_unknown", "am_illg"};
916: #endif
917:
1.1 root 918: struct instr *curi = table68k + opcode;
919: insn_n_cycles = 4;
920:
1.1.1.8 root 921: /* Store the family of the instruction (used to check for pairing on ST)
922: * and leave some space for patching in the current cycles later */
923: printf ("\tOpcodeFamily = %d; CurrentInstrCycles = \n", curi->mnemo);
924: nCurInstrCycPos = ftell(stdout) - 5;
925:
1.1 root 926: start_brace ();
927: m68k_pc_offset = 2;
1.1.1.2 root 928:
1.1 root 929: switch (curi->plev) {
930: case 0: /* not privileged */
931: break;
932: case 1: /* unprivileged only on 68000 */
933: if (cpu_level == 0)
934: break;
935: if (next_cpu_level < 0)
936: next_cpu_level = 0;
937:
938: /* fall through */
939: case 2: /* priviledged */
1.1.1.9 root 940: printf ("if (!regs.s) { Exception(8,0,M68000_EXCEPTION_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 941: need_endlabel = 1;
942: start_brace ();
943: break;
944: case 3: /* privileged if size == word */
945: if (curi->size == sz_byte)
946: break;
1.1.1.9 root 947: printf ("if (!regs.s) { Exception(8,0,M68000_EXCEPTION_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 948: need_endlabel = 1;
949: start_brace ();
950: break;
951: }
1.1.1.2 root 952:
953: /* Build the opcodes: */
1.1 root 954: switch (curi->mnemo) {
955: case i_OR:
956: case i_AND:
957: case i_EOR:
1.1.1.2 root 958: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
959: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
960: printf ("\tsrc %c= dst;\n", curi->mnemo == i_OR ? '|' : curi->mnemo == i_AND ? '&' : '^');
961: genflags (flag_logical, curi->size, "src", "", "");
962: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
963: if(curi->size==sz_long && curi->dmode==Dreg)
964: {
965: insn_n_cycles += 2;
966: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
967: insn_n_cycles += 2;
968: }
969: #if 0
970: /* Output the CPU cycles: */
971: fprintf(stderr,"MOVE, size %i: ",curi->size);
972: fprintf(stderr," %s ->",amodenames[curi->smode]);
973: fprintf(stderr," %s ",amodenames[curi->dmode]);
974: fprintf(stderr," Cycles: %i\n",insn_n_cycles);
975: #endif
976: break;
1.1 root 977: case i_ORSR:
978: case i_EORSR:
1.1.1.2 root 979: printf ("\tMakeSR();\n");
980: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
981: if (curi->size == sz_byte) {
982: printf ("\tsrc &= 0xFF;\n");
983: }
984: printf ("\tregs.sr %c= src;\n", curi->mnemo == i_EORSR ? '^' : '|');
985: printf ("\tMakeFromSR();\n");
986: insn_n_cycles = 20;
987: break;
1.1 root 988: case i_ANDSR:
1.1.1.2 root 989: printf ("\tMakeSR();\n");
990: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
991: if (curi->size == sz_byte) {
992: printf ("\tsrc |= 0xFF00;\n");
993: }
994: printf ("\tregs.sr &= src;\n");
995: printf ("\tMakeFromSR();\n");
996: insn_n_cycles = 20;
997: break;
1.1 root 998: case i_SUB:
999: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1000: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1001: start_brace ();
1002: genflags (flag_sub, curi->size, "newv", "src", "dst");
1003: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1004: if(curi->size==sz_long && curi->dmode==Dreg)
1005: {
1006: insn_n_cycles += 2;
1007: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
1008: insn_n_cycles += 2;
1009: }
1.1 root 1010: break;
1011: case i_SUBA:
1012: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1013: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1014: start_brace ();
1015: printf ("\tuae_u32 newv = dst - src;\n");
1016: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.2 root 1017: if(curi->size==sz_long && curi->smode!=Dreg && curi->smode!=Areg && !(curi->smode>=imm && curi->smode<=immi))
1018: insn_n_cycles += 2;
1019: else
1020: insn_n_cycles += 4;
1.1.1.8 root 1021: if( (curi->smode==Ad8r) || (curi->smode==PC8r) ) /* [NP] on 68000 ST, d8(An,Xn) takes 2 cycles more */
1022: insn_n_cycles += 2;
1.1 root 1023: break;
1024: case i_SUBX:
1025: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1026: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1027: start_brace ();
1028: printf ("\tuae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);\n");
1029: genflags (flag_subx, curi->size, "newv", "src", "dst");
1030: genflags (flag_zn, curi->size, "newv", "", "");
1031: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1032: if(curi->smode==Dreg && curi->size==sz_long)
1033: insn_n_cycles=8;
1034: if(curi->smode==Apdi)
1035: {
1036: if(curi->size==sz_long)
1037: insn_n_cycles=30;
1038: else
1039: insn_n_cycles=18;
1040: }
1.1 root 1041: break;
1042: case i_SBCD:
1043: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1044: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1045: start_brace ();
1046: printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
1047: printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
1.1.1.4 root 1048: printf ("\tuae_u16 newv, tmp_newv;\n");
1049: printf ("\tint bcd = 0;\n");
1050: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
1051: printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
1052: printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
1053: printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);\n");
1.1 root 1054: duplicate_carry ();
1055: genflags (flag_zn, curi->size, "newv", "", "");
1.1.1.4 root 1056: printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
1.1 root 1057: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.4 root 1058: if(curi->smode==Dreg) insn_n_cycles=6;
1059: if(curi->smode==Apdi) insn_n_cycles=18;
1.1 root 1060: break;
1061: case i_ADD:
1062: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1063: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1064: start_brace ();
1.1.1.8 root 1065: printf("\trefill_prefetch (m68k_getpc(), 2);\n"); // FIXME [NP] For Transbeauce 2 demo, need better prefetch emulation
1.1 root 1066: genflags (flag_add, curi->size, "newv", "src", "dst");
1067: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1068: if(curi->size==sz_long && curi->dmode==Dreg)
1069: {
1070: insn_n_cycles += 2;
1071: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
1072: insn_n_cycles += 2;
1073: }
1.1 root 1074: break;
1075: case i_ADDA:
1076: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1077: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1078: start_brace ();
1079: printf ("\tuae_u32 newv = dst + src;\n");
1080: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.2 root 1081: if(curi->size==sz_long && curi->smode!=Dreg && curi->smode!=Areg && !(curi->smode>=imm && curi->smode<=immi))
1082: insn_n_cycles += 2;
1083: else
1084: insn_n_cycles += 4;
1.1.1.8 root 1085: if( (curi->smode==Ad8r) || (curi->smode==PC8r) ) /* [NP] on 68000 ST, d8(An,Xn) takes 2 cycles more */
1086: insn_n_cycles += 2;
1.1 root 1087: break;
1088: case i_ADDX:
1089: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1090: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1091: start_brace ();
1092: printf ("\tuae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);\n");
1093: genflags (flag_addx, curi->size, "newv", "src", "dst");
1094: genflags (flag_zn, curi->size, "newv", "", "");
1095: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1096: if(curi->smode==Dreg && curi->size==sz_long)
1097: insn_n_cycles=8;
1098: if(curi->smode==Apdi)
1099: {
1100: if(curi->size==sz_long)
1101: insn_n_cycles=30;
1102: else
1103: insn_n_cycles=18;
1104: }
1.1 root 1105: break;
1106: case i_ABCD:
1107: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1108: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1109: start_brace ();
1110: printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);\n");
1111: printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
1.1.1.4 root 1112: printf ("\tuae_u16 newv, tmp_newv;\n");
1.1 root 1113: printf ("\tint cflg;\n");
1.1.1.4 root 1114: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;");
1115: printf ("\tif (newv_lo > 9) { newv += 6; }\n");
1116: printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
1117: printf ("\tif (cflg) newv += 0x60;\n");
1.1 root 1118: printf ("\tSET_CFLG (cflg);\n");
1119: duplicate_carry ();
1120: genflags (flag_zn, curi->size, "newv", "", "");
1.1.1.4 root 1121: printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
1.1 root 1122: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.4 root 1123: if(curi->smode==Dreg) insn_n_cycles=6;
1124: if(curi->smode==Apdi) insn_n_cycles=18;
1.1 root 1125: break;
1126: case i_NEG:
1127: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1128: start_brace ();
1129: genflags (flag_sub, curi->size, "dst", "src", "0");
1130: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1131: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1132: break;
1133: case i_NEGX:
1134: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1135: start_brace ();
1136: printf ("\tuae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);\n");
1137: genflags (flag_subx, curi->size, "newv", "src", "0");
1138: genflags (flag_zn, curi->size, "newv", "", "");
1139: genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1140: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1141: break;
1142: case i_NBCD:
1143: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1144: start_brace ();
1145: printf ("\tuae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
1146: printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
1147: printf ("\tuae_u16 newv;\n");
1148: printf ("\tint cflg;\n");
1.1.1.4 root 1149: printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
1150: printf ("\tnewv = newv_hi + newv_lo;");
1151: printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
1152: printf ("\tif (cflg) newv -= 0x60;\n");
1.1 root 1153: printf ("\tSET_CFLG (cflg);\n");
1154: duplicate_carry();
1155: genflags (flag_zn, curi->size, "newv", "", "");
1156: genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1.1.1.4 root 1157: if(curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1158: break;
1159: case i_CLR:
1160: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1.1.1.8 root 1161:
1162: /* [NP] CLR does a read before the write only on 68000 */
1163: /* but there's no cycle penalty for doing the read */
1164: if ( curi->smode != Dreg ) // only if destination is memory
1165: {
1166: if (curi->size==sz_byte)
1167: printf ("\tuae_s8 src = get_byte(srca);\n");
1168: else if (curi->size==sz_word)
1169: printf ("\tuae_s16 src = get_word(srca);\n");
1170: else if (curi->size==sz_long)
1171: printf ("\tuae_s32 src = get_long(srca);\n");
1172: }
1173:
1.1 root 1174: genflags (flag_logical, curi->size, "0", "", "");
1175: genastore ("0", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1176: if(curi->size==sz_long)
1.1.1.3 root 1177: {
1.1.1.2 root 1178: if(curi->smode==Dreg)
1179: insn_n_cycles += 2;
1180: else
1181: insn_n_cycles += 4;
1.1.1.3 root 1182: }
1.1.1.2 root 1183: if(curi->smode!=Dreg)
1184: insn_n_cycles += 4;
1.1 root 1185: break;
1186: case i_NOT:
1187: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1188: start_brace ();
1189: printf ("\tuae_u32 dst = ~src;\n");
1190: genflags (flag_logical, curi->size, "dst", "", "");
1191: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1192: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1193: break;
1194: case i_TST:
1195: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1196: genflags (flag_logical, curi->size, "src", "", "");
1197: break;
1198: case i_BTST:
1199: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1200: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1201: if (curi->size == sz_byte)
1202: printf ("\tsrc &= 7;\n");
1203: else
1204: printf ("\tsrc &= 31;\n");
1205: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1.1.1.2 root 1206: if(curi->dmode==Dreg) insn_n_cycles += 2;
1.1 root 1207: break;
1208: case i_BCHG:
1209: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1210: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1211: if (curi->size == sz_byte)
1212: printf ("\tsrc &= 7;\n");
1213: else
1214: printf ("\tsrc &= 31;\n");
1215: printf ("\tdst ^= (1 << src);\n");
1216: printf ("\tSET_ZFLG (((uae_u32)dst & (1 << src)) >> src);\n");
1217: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1218: if(curi->dmode==Dreg) insn_n_cycles += 4;
1.1 root 1219: break;
1220: case i_BCLR:
1221: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1222: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1223: if (curi->size == sz_byte)
1224: printf ("\tsrc &= 7;\n");
1225: else
1226: printf ("\tsrc &= 31;\n");
1227: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1228: printf ("\tdst &= ~(1 << src);\n");
1229: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1230: if(curi->dmode==Dreg) insn_n_cycles += 6;
1.1.1.8 root 1231: /* [NP] BCLR #n,Dx takes 12 cycles instead of 14 if n<16 */
1232: if((curi->smode==imm1) && (curi->dmode==Dreg))
1233: printf ("\tif ( src < 16 ) { m68k_incpc(4); return 12; }\n");
1234: /* [NP] BCLR Dy,Dx takes 8 cycles instead of 10 if Dy<16 */
1235: if((curi->smode==Dreg) && (curi->dmode==Dreg))
1236: printf ("\tif ( src < 16 ) { m68k_incpc(2); return 8; }\n");
1.1 root 1237: break;
1238: case i_BSET:
1239: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1240: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1241: if (curi->size == sz_byte)
1242: printf ("\tsrc &= 7;\n");
1243: else
1244: printf ("\tsrc &= 31;\n");
1245: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1246: printf ("\tdst |= (1 << src);\n");
1247: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1248: if(curi->dmode==Dreg) insn_n_cycles += 4;
1.1 root 1249: break;
1250: case i_CMPM:
1251: case i_CMP:
1252: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1253: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1254: start_brace ();
1255: genflags (flag_cmp, curi->size, "newv", "src", "dst");
1.1.1.2 root 1256: if(curi->size==sz_long && curi->dmode==Dreg)
1257: insn_n_cycles += 2;
1.1 root 1258: break;
1259: case i_CMPA:
1260: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1261: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1262: start_brace ();
1263: genflags (flag_cmp, sz_long, "newv", "src", "dst");
1.1.1.2 root 1264: insn_n_cycles += 2;
1.1 root 1265: break;
1266: /* The next two are coded a little unconventional, but they are doing
1267: * weird things... */
1268: case i_MVPRM:
1269: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1270:
1271: printf ("\tuaecptr memp = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword ());
1272: if (curi->size == sz_word) {
1273: printf ("\tput_byte(memp, src >> 8); put_byte(memp + 2, src);\n");
1274: } else {
1275: printf ("\tput_byte(memp, src >> 24); put_byte(memp + 2, src >> 16);\n");
1276: printf ("\tput_byte(memp + 4, src >> 8); put_byte(memp + 6, src);\n");
1277: }
1.1.1.2 root 1278: if(curi->size==sz_long) insn_n_cycles=24; else insn_n_cycles=16;
1.1 root 1279: break;
1280: case i_MVPMR:
1281: printf ("\tuaecptr memp = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword ());
1282: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1283: if (curi->size == sz_word) {
1284: printf ("\tuae_u16 val = (get_byte(memp) << 8) + get_byte(memp + 2);\n");
1285: } else {
1286: printf ("\tuae_u32 val = (get_byte(memp) << 24) + (get_byte(memp + 2) << 16)\n");
1287: printf (" + (get_byte(memp + 4) << 8) + get_byte(memp + 6);\n");
1288: }
1289: genastore ("val", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1290: if(curi->size==sz_long) insn_n_cycles=24; else insn_n_cycles=16;
1.1 root 1291: break;
1292: case i_MOVE:
1293: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1294: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1.1.1.8 root 1295:
1296: /* [NP] genamode counts 2 cycles if dest is -(An), this is wrong. */
1297: /* For move dest (An), (An)+ and -(An) take the same time */
1298: /* (for other instr, dest -(An) really takes 2 cycles more) */
1299: if ( curi->dmode == Apdi )
1300: insn_n_cycles -= 2; /* correct the wrong cycle count for -(An) */
1301:
1.1 root 1302: genflags (flag_logical, curi->size, "src", "", "");
1303: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
1304: break;
1305: case i_MOVEA:
1306: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1307: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1308: if (curi->size == sz_word) {
1309: printf ("\tuae_u32 val = (uae_s32)(uae_s16)src;\n");
1310: } else {
1311: printf ("\tuae_u32 val = src;\n");
1312: }
1313: genastore ("val", curi->dmode, "dstreg", sz_long, "dst");
1314: break;
1.1.1.2 root 1315: case i_MVSR2: /* Move from SR */
1.1 root 1316: genamode (curi->smode, "srcreg", sz_word, "src", 2, 0);
1317: printf ("\tMakeSR();\n");
1318: if (curi->size == sz_byte)
1319: genastore ("regs.sr & 0xff", curi->smode, "srcreg", sz_word, "src");
1320: else
1321: genastore ("regs.sr", curi->smode, "srcreg", sz_word, "src");
1.1.1.2 root 1322: if (curi->smode==Dreg) insn_n_cycles += 2; else insn_n_cycles += 4;
1.1 root 1323: break;
1.1.1.2 root 1324: case i_MV2SR: /* Move to SR */
1.1 root 1325: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1326: if (curi->size == sz_byte)
1327: printf ("\tMakeSR();\n\tregs.sr &= 0xFF00;\n\tregs.sr |= src & 0xFF;\n");
1328: else {
1329: printf ("\tregs.sr = src;\n");
1330: }
1331: printf ("\tMakeFromSR();\n");
1.1.1.2 root 1332: insn_n_cycles += 8;
1.1 root 1333: break;
1334: case i_SWAP:
1335: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1336: start_brace ();
1337: printf ("\tuae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);\n");
1338: genflags (flag_logical, sz_long, "dst", "", "");
1339: genastore ("dst", curi->smode, "srcreg", sz_long, "src");
1340: break;
1341: case i_EXG:
1342: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1343: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1344: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1345: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1346: insn_n_cycles = 6;
1.1 root 1347: break;
1348: case i_EXT:
1349: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1350: start_brace ();
1351: switch (curi->size) {
1352: case sz_byte: printf ("\tuae_u32 dst = (uae_s32)(uae_s8)src;\n"); break;
1353: case sz_word: printf ("\tuae_u16 dst = (uae_s16)(uae_s8)src;\n"); break;
1354: case sz_long: printf ("\tuae_u32 dst = (uae_s32)(uae_s16)src;\n"); break;
1355: default: abort ();
1356: }
1357: genflags (flag_logical,
1358: curi->size == sz_word ? sz_word : sz_long, "dst", "", "");
1359: genastore ("dst", curi->smode, "srcreg",
1360: curi->size == sz_word ? sz_word : sz_long, "src");
1361: break;
1362: case i_MVMEL:
1363: genmovemel (opcode);
1364: break;
1365: case i_MVMLE:
1366: genmovemle (opcode);
1367: break;
1368: case i_TRAP:
1369: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1370: sync_m68k_pc ();
1.1.1.9 root 1371: printf ("\tException(src+32,0,M68000_EXCEPTION_SRC_CPU);\n");
1.1 root 1372: m68k_pc_offset = 0;
1373: break;
1374: case i_MVR2USP:
1375: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1376: printf ("\tregs.usp = src;\n");
1377: break;
1378: case i_MVUSP2R:
1379: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1380: genastore ("regs.usp", curi->smode, "srcreg", curi->size, "src");
1381: break;
1382: case i_RESET:
1383: printf ("\tcustomreset();\n");
1.1.1.2 root 1384: insn_n_cycles = 132; /* I am not so sure about this!? - Thothy */
1.1 root 1385: break;
1386: case i_NOP:
1387: break;
1388: case i_STOP:
1389: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1390: printf ("\tregs.sr = src;\n");
1391: printf ("\tMakeFromSR();\n");
1392: printf ("\tm68k_setstopped(1);\n");
1.1.1.2 root 1393: insn_n_cycles = 4;
1.1 root 1394: break;
1395: case i_RTE:
1396: if (cpu_level == 0) {
1397: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1398: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1399: printf ("\tregs.sr = sr; m68k_setpc_rte(pc);\n");
1400: fill_prefetch_0 ();
1401: printf ("\tMakeFromSR();\n");
1402: } else {
1403: int old_brace_level = n_braces;
1404: if (next_cpu_level < 0)
1405: next_cpu_level = 0;
1406: printf ("\tuae_u16 newsr; uae_u32 newpc; for (;;) {\n");
1407: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1408: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1409: genamode (Aipi, "7", sz_word, "format", 1, 0);
1410: printf ("\tnewsr = sr; newpc = pc;\n");
1411: printf ("\tif ((format & 0xF000) == 0x0000) { break; }\n");
1412: printf ("\telse if ((format & 0xF000) == 0x1000) { ; }\n");
1413: printf ("\telse if ((format & 0xF000) == 0x2000) { m68k_areg(regs, 7) += 4; break; }\n");
1414: printf ("\telse if ((format & 0xF000) == 0x8000) { m68k_areg(regs, 7) += 50; break; }\n");
1415: printf ("\telse if ((format & 0xF000) == 0x9000) { m68k_areg(regs, 7) += 12; break; }\n");
1416: printf ("\telse if ((format & 0xF000) == 0xa000) { m68k_areg(regs, 7) += 24; break; }\n");
1417: printf ("\telse if ((format & 0xF000) == 0xb000) { m68k_areg(regs, 7) += 84; break; }\n");
1.1.1.9 root 1418: printf ("\telse { Exception(14,0,M68000_EXCEPTION_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 1419: printf ("\tregs.sr = newsr; MakeFromSR();\n}\n");
1420: pop_braces (old_brace_level);
1421: printf ("\tregs.sr = newsr; MakeFromSR();\n");
1422: printf ("\tm68k_setpc_rte(newpc);\n");
1423: fill_prefetch_0 ();
1424: need_endlabel = 1;
1425: }
1426: /* PC is set and prefetch filled. */
1427: m68k_pc_offset = 0;
1.1.1.2 root 1428: insn_n_cycles = 20;
1.1 root 1429: break;
1430: case i_RTD:
1431: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1432: genamode (curi->smode, "srcreg", curi->size, "offs", 1, 0);
1433: printf ("\tm68k_areg(regs, 7) += offs;\n");
1434: printf ("\tm68k_setpc_rte(pc);\n");
1435: fill_prefetch_0 ();
1436: /* PC is set and prefetch filled. */
1437: m68k_pc_offset = 0;
1438: break;
1439: case i_LINK:
1440: genamode (Apdi, "7", sz_long, "old", 2, 0);
1441: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1442: genastore ("src", Apdi, "7", sz_long, "old");
1443: genastore ("m68k_areg(regs, 7)", curi->smode, "srcreg", sz_long, "src");
1444: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0);
1445: printf ("\tm68k_areg(regs, 7) += offs;\n");
1446: break;
1447: case i_UNLK:
1448: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1449: printf ("\tm68k_areg(regs, 7) = src;\n");
1450: genamode (Aipi, "7", sz_long, "old", 1, 0);
1451: genastore ("old", curi->smode, "srcreg", curi->size, "src");
1452: break;
1453: case i_RTS:
1454: printf ("\tm68k_do_rts();\n");
1455: fill_prefetch_0 ();
1456: m68k_pc_offset = 0;
1.1.1.2 root 1457: insn_n_cycles = 16;
1.1 root 1458: break;
1459: case i_TRAPV:
1460: sync_m68k_pc ();
1.1.1.9 root 1461: printf ("\tif (GET_VFLG) { Exception(7,m68k_getpc(),M68000_EXCEPTION_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 1462: need_endlabel = 1;
1463: break;
1464: case i_RTR:
1465: printf ("\tMakeSR();\n");
1466: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1467: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1468: printf ("\tregs.sr &= 0xFF00; sr &= 0xFF;\n");
1469: printf ("\tregs.sr |= sr; m68k_setpc(pc);\n");
1470: fill_prefetch_0 ();
1471: printf ("\tMakeFromSR();\n");
1472: m68k_pc_offset = 0;
1.1.1.2 root 1473: insn_n_cycles = 20;
1.1 root 1474: break;
1475: case i_JSR:
1476: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1477: printf ("\tm68k_do_jsr(m68k_getpc() + %d, srca);\n", m68k_pc_offset);
1478: fill_prefetch_0 ();
1479: m68k_pc_offset = 0;
1.1.1.2 root 1480: switch(curi->smode)
1481: {
1482: case Aind: insn_n_cycles=16; break;
1483: case Ad16: insn_n_cycles=18; break;
1484: case Ad8r: insn_n_cycles=22; break;
1485: case absw: insn_n_cycles=18; break;
1486: case absl: insn_n_cycles=20; break;
1487: case PC16: insn_n_cycles=18; break;
1488: case PC8r: insn_n_cycles=22; break;
1489: }
1.1 root 1490: break;
1491: case i_JMP:
1492: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1493: printf ("\tm68k_setpc(srca);\n");
1494: fill_prefetch_0 ();
1495: m68k_pc_offset = 0;
1.1.1.2 root 1496: switch(curi->smode)
1497: {
1498: case Aind: insn_n_cycles=8; break;
1499: case Ad16: insn_n_cycles=10; break;
1500: case Ad8r: insn_n_cycles=14; break;
1501: case absw: insn_n_cycles=10; break;
1502: case absl: insn_n_cycles=12; break;
1503: case PC16: insn_n_cycles=10; break;
1504: case PC8r: insn_n_cycles=14; break;
1505: }
1.1 root 1506: break;
1507: case i_BSR:
1508: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1509: printf ("\tuae_s32 s = (uae_s32)src + 2;\n");
1510: if (using_exception_3) {
1511: printf ("\tif (src & 1) {\n");
1.1.1.8 root 1512: printf ("\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n"); // [NP] FIXME should be +4, not +2 (same as DBcc) ?
1.1 root 1513: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + s;\n");
1.1.1.9 root 1514: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXCEPTION_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1515: printf ("\t}\n");
1516: need_endlabel = 1;
1517: }
1518: printf ("\tm68k_do_bsr(m68k_getpc() + %d, s);\n", m68k_pc_offset);
1519: fill_prefetch_0 ();
1520: m68k_pc_offset = 0;
1.1.1.2 root 1521: insn_n_cycles = 18;
1.1 root 1522: break;
1523: case i_Bcc:
1524: if (curi->size == sz_long) {
1525: if (cpu_level < 2) {
1526: printf ("\tm68k_incpc(2);\n");
1527: printf ("\tif (!cctrue(%d)) goto %s;\n", curi->cc, endlabelstr);
1528: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n");
1529: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + 1;\n");
1.1.1.9 root 1530: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXCEPTION_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1531: need_endlabel = 1;
1532: } else {
1533: if (next_cpu_level < 1)
1534: next_cpu_level = 1;
1535: }
1536: }
1537: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1538: printf ("\tif (!cctrue(%d)) goto didnt_jump;\n", curi->cc);
1539: if (using_exception_3) {
1540: printf ("\tif (src & 1) {\n");
1.1.1.8 root 1541: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n"); // [NP] FIXME should be +4, not +2 (same as DBcc) ?
1.1 root 1542: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;\n");
1.1.1.9 root 1543: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXCEPTION_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1544: printf ("\t}\n");
1545: need_endlabel = 1;
1546: }
1547: printf ("\tm68k_incpc ((uae_s32)src + 2);\n");
1548: fill_prefetch_0 ();
1.1.1.2 root 1549: printf ("\treturn 10;\n");
1.1 root 1550: printf ("didnt_jump:;\n");
1551: need_endlabel = 1;
1.1.1.2 root 1552: insn_n_cycles = (curi->size == sz_byte) ? 8 : 12;
1.1 root 1553: break;
1554: case i_LEA:
1555: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1556: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1557: genastore ("srca", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.7 root 1558: /* Set correct cycles: According to the M68K User Manual, LEA takes 12
1559: * cycles in Ad8r and PC8r mode, but it takes 14 (or 16) cycles on a real ST: */
1560: if (curi->smode == Ad8r || curi->smode == PC8r)
1561: insn_n_cycles = 14;
1.1 root 1562: break;
1563: case i_PEA:
1564: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1565: genamode (Apdi, "7", sz_long, "dst", 2, 0);
1566: genastore ("srca", Apdi, "7", sz_long, "dst");
1.1.1.7 root 1567: /* Set correct cycles: */
1.1.1.2 root 1568: switch(curi->smode)
1569: {
1570: case Aind: insn_n_cycles=12; break;
1571: case Ad16: insn_n_cycles=16; break;
1.1.1.7 root 1572: /* Note: according to the M68K User Manual, PEA takes 20 cycles for
1573: * the Ad8r mode, but on a real ST, it takes 22 (or 24) cycles! */
1574: case Ad8r: insn_n_cycles=22; break;
1.1.1.2 root 1575: case absw: insn_n_cycles=16; break;
1576: case absl: insn_n_cycles=20; break;
1577: case PC16: insn_n_cycles=16; break;
1.1.1.7 root 1578: /* Note: PEA with PC8r takes 20 cycles according to the User Manual,
1579: * but it takes 22 (or 24) cycles on a real ST: */
1580: case PC8r: insn_n_cycles=22; break;
1.1.1.2 root 1581: }
1.1 root 1582: break;
1583: case i_DBcc:
1584: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1585: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0);
1586:
1.1.1.2 root 1587: printf ("\tif (!cctrue(%d)) {\n\t", curi->cc);
1.1 root 1588: genastore ("(src-1)", curi->smode, "srcreg", curi->size, "src");
1589:
1590: printf ("\t\tif (src) {\n");
1591: if (using_exception_3) {
1592: printf ("\t\t\tif (offs & 1) {\n");
1.1.1.8 root 1593: printf ("\t\t\tlast_addr_for_exception_3 = m68k_getpc() + 2 + 2;\n"); // [NP] last_addr is pc+4, not pc+2
1.1 root 1594: printf ("\t\t\tlast_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;\n");
1.1.1.9 root 1595: printf ("\t\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXCEPTION_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1596: printf ("\t\t}\n");
1597: need_endlabel = 1;
1598: }
1599: printf ("\t\t\tm68k_incpc((uae_s32)offs + 2);\n");
1600: fill_prefetch_0 ();
1.1.1.2 root 1601: printf ("\t\t\treturn 10;\n");
1602: printf ("\t\t} else {\n\t\t\t");
1603: {
1604: int tmp_offset = m68k_pc_offset;
1605: sync_m68k_pc(); /* not so nice to call it here... */
1606: m68k_pc_offset = tmp_offset;
1607: }
1608: printf ("\t\t\treturn 14;\n");
1609: printf ("\t\t}\n");
1.1 root 1610: printf ("\t}\n");
1611: insn_n_cycles = 12;
1612: need_endlabel = 1;
1613: break;
1614: case i_Scc:
1615: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1616: start_brace ();
1617: printf ("\tint val = cctrue(%d) ? 0xff : 0;\n", curi->cc);
1618: genastore ("val", curi->smode, "srcreg", curi->size, "src");
1.1.1.8 root 1619: if (curi->smode!=Dreg) insn_n_cycles += 4;
1620: else
1621: { /* [NP] if result is TRUE, we return 6 instead of 4 */
1622: printf ("\tif (val) { m68k_incpc(2) ; return 4+2; }\n");
1623: }
1.1 root 1624: break;
1625: case i_DIVU:
1626: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1627: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1628: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1629: sync_m68k_pc ();
1630: /* Clear V flag when dividing by zero - Alcatraz Odyssey demo depends
1631: * on this (actually, it's doing a DIVS). */
1.1.1.9 root 1632: printf ("\tif (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXCEPTION_SRC_CPU); goto %s; } else {\n", endlabelstr);
1.1 root 1633: printf ("\tuae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
1634: printf ("\tuae_u32 rem = (uae_u32)dst %% (uae_u32)(uae_u16)src;\n");
1635: /* The N flag appears to be set each time there is an overflow.
1636: * Weird. */
1637: printf ("\tif (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
1638: genflags (flag_logical, sz_word, "newv", "", "");
1639: printf ("\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
1640: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1641: printf ("\t}\n");
1642: printf ("\t}\n");
1.1.1.8 root 1643: // insn_n_cycles += 136;
1644: printf ("\tretcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);\n");
1645: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 1646: need_endlabel = 1;
1647: break;
1648: case i_DIVS:
1649: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1650: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1651: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1652: sync_m68k_pc ();
1.1.1.9 root 1653: printf ("\tif (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXCEPTION_SRC_CPU); goto %s; } else {\n", endlabelstr);
1.1 root 1654: printf ("\tuae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
1655: printf ("\tuae_u16 rem = (uae_s32)dst %% (uae_s32)(uae_s16)src;\n");
1656: printf ("\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
1657: printf ("\tif (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;\n");
1658: genflags (flag_logical, sz_word, "newv", "", "");
1659: printf ("\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
1660: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1661: printf ("\t}\n");
1662: printf ("\t}\n");
1.1.1.8 root 1663: // insn_n_cycles += 154;
1664: printf ("\tretcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);\n");
1665: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 1666: need_endlabel = 1;
1667: break;
1668: case i_MULU:
1669: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1670: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0);
1671: start_brace ();
1672: printf ("\tuae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;\n");
1673: genflags (flag_logical, sz_long, "newv", "", "");
1674: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.8 root 1675: /* [NP] number of cycles is 38 + 2n + ea time ; n is the number of 1 bits in src */
1676: insn_n_cycles += 38-4; /* insn_n_cycles is already initialized to 4 instead of 0 */
1677: printf ("\twhile (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }\n");
1678: sprintf(exactCpuCycles," return (%i+retcycles*2);", insn_n_cycles);
1.1 root 1679: break;
1680: case i_MULS:
1681: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1682: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0);
1683: start_brace ();
1684: printf ("\tuae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;\n");
1.1.1.8 root 1685: printf ("\tuae_u32 src2;\n");
1.1 root 1686: genflags (flag_logical, sz_long, "newv", "", "");
1687: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.8 root 1688: /* [NP] number of cycles is 38 + 2n + ea time ; n is the number of 01 or 10 patterns in src expanded to 17 bits */
1689: insn_n_cycles += 38-4; /* insn_n_cycles is already initialized to 4 instead of 0 */
1690: printf ("\tsrc2 = ((uae_u32)src) << 1;\n");
1691: printf ("\twhile (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }\n");
1692: sprintf(exactCpuCycles," return (%i+retcycles*2);", insn_n_cycles);
1.1 root 1693: break;
1694: case i_CHK:
1695: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1696: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1697: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1.1.1.8 root 1698: sync_m68k_pc ();
1.1.1.9 root 1699: printf ("\tif ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXCEPTION_SRC_CPU); goto %s; }\n", endlabelstr);
1700: printf ("\telse if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXCEPTION_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 1701: need_endlabel = 1;
1.1.1.2 root 1702: insn_n_cycles += 6;
1.1 root 1703: break;
1704:
1705: case i_CHK2:
1706: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1707: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
1708: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1709: printf ("\t{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];\n");
1710: switch (curi->size) {
1711: case sz_byte:
1712: printf ("\tlower=(uae_s32)(uae_s8)get_byte(dsta); upper = (uae_s32)(uae_s8)get_byte(dsta+1);\n");
1713: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;\n");
1714: break;
1715: case sz_word:
1716: printf ("\tlower=(uae_s32)(uae_s16)get_word(dsta); upper = (uae_s32)(uae_s16)get_word(dsta+2);\n");
1717: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;\n");
1718: break;
1719: case sz_long:
1720: printf ("\tlower=get_long(dsta); upper = get_long(dsta+4);\n");
1721: break;
1722: default:
1723: abort ();
1724: }
1725: printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
1726: printf ("\tSET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
1.1.1.8 root 1727: sync_m68k_pc ();
1.1.1.9 root 1728: printf ("\tif ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXCEPTION_SRC_CPU); goto %s; }\n}\n", endlabelstr);
1.1 root 1729: need_endlabel = 1;
1730: break;
1731:
1732: case i_ASR:
1733: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1734: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1735: start_brace ();
1736: switch (curi->size) {
1737: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1738: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1739: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1740: default: abort ();
1741: }
1742: printf ("\tuae_u32 sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1);
1743: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1744: printf ("\tretcycles = cnt;\n");
1.1 root 1745: printf ("\tCLEAR_CZNV;\n");
1746: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1747: printf ("\t\tval = %s & (uae_u32)-sign;\n", bit_mask (curi->size));
1748: printf ("\t\tSET_CFLG (sign);\n");
1749: duplicate_carry ();
1750: if (source_is_imm1_8 (curi))
1751: printf ("\t} else {\n");
1752: else
1753: printf ("\t} else if (cnt > 0) {\n");
1754: printf ("\t\tval >>= cnt - 1;\n");
1755: printf ("\t\tSET_CFLG (val & 1);\n");
1756: duplicate_carry ();
1757: printf ("\t\tval >>= 1;\n");
1758: printf ("\t\tval |= (%s << (%d - cnt)) & (uae_u32)-sign;\n",
1759: bit_mask (curi->size),
1760: bit_size (curi->size));
1761: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
1762: printf ("\t}\n");
1763: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1764: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1765: if(curi->size==sz_long)
1766: strcpy(exactCpuCycles," return (8+retcycles*2);");
1767: else
1768: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1769: break;
1770: case i_ASL:
1771: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1772: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1773: start_brace ();
1774: switch (curi->size) {
1775: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1776: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1777: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1778: default: abort ();
1779: }
1780: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1781: printf ("\tretcycles = cnt;\n");
1.1 root 1782: printf ("\tCLEAR_CZNV;\n");
1783: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1784: printf ("\t\tSET_VFLG (val != 0);\n");
1785: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
1786: bit_size (curi->size));
1787: duplicate_carry ();
1788: printf ("\t\tval = 0;\n");
1789: if (source_is_imm1_8 (curi))
1790: printf ("\t} else {\n");
1791: else
1792: printf ("\t} else if (cnt > 0) {\n");
1793: printf ("\t\tuae_u32 mask = (%s << (%d - cnt)) & %s;\n",
1794: bit_mask (curi->size),
1795: bit_size (curi->size) - 1,
1796: bit_mask (curi->size));
1797: printf ("\t\tSET_VFLG ((val & mask) != mask && (val & mask) != 0);\n");
1798: printf ("\t\tval <<= cnt - 1;\n");
1799: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
1800: duplicate_carry ();
1801: printf ("\t\tval <<= 1;\n");
1802: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
1803: printf ("\t}\n");
1804: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1805: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1806: if(curi->size==sz_long)
1807: strcpy(exactCpuCycles," return (8+retcycles*2);");
1808: else
1809: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1810: break;
1811: case i_LSR:
1812: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1813: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1814: start_brace ();
1815: switch (curi->size) {
1816: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1817: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1818: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1819: default: abort ();
1820: }
1821: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1822: printf ("\tretcycles = cnt;\n");
1.1 root 1823: printf ("\tCLEAR_CZNV;\n");
1824: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1825: printf ("\t\tSET_CFLG ((cnt == %d) & (val >> %d));\n",
1826: bit_size (curi->size), bit_size (curi->size) - 1);
1827: duplicate_carry ();
1828: printf ("\t\tval = 0;\n");
1829: if (source_is_imm1_8 (curi))
1830: printf ("\t} else {\n");
1831: else
1832: printf ("\t} else if (cnt > 0) {\n");
1833: printf ("\t\tval >>= cnt - 1;\n");
1834: printf ("\t\tSET_CFLG (val & 1);\n");
1835: duplicate_carry ();
1836: printf ("\t\tval >>= 1;\n");
1837: printf ("\t}\n");
1838: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1839: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1840: if(curi->size==sz_long)
1841: strcpy(exactCpuCycles," return (8+retcycles*2);");
1842: else
1843: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1844: break;
1845: case i_LSL:
1846: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1847: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1848: start_brace ();
1849: switch (curi->size) {
1850: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1851: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1852: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1853: default: abort ();
1854: }
1855: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1856: printf ("\tretcycles = cnt;\n");
1.1 root 1857: printf ("\tCLEAR_CZNV;\n");
1858: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1859: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
1860: bit_size (curi->size));
1861: duplicate_carry ();
1862: printf ("\t\tval = 0;\n");
1863: if (source_is_imm1_8 (curi))
1864: printf ("\t} else {\n");
1865: else
1866: printf ("\t} else if (cnt > 0) {\n");
1867: printf ("\t\tval <<= (cnt - 1);\n");
1868: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
1869: duplicate_carry ();
1870: printf ("\t\tval <<= 1;\n");
1871: printf ("\tval &= %s;\n", bit_mask (curi->size));
1872: printf ("\t}\n");
1873: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1874: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1875: if(curi->size==sz_long)
1876: strcpy(exactCpuCycles," return (8+retcycles*2);");
1877: else
1878: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1879: break;
1880: case i_ROL:
1881: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1882: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1883: start_brace ();
1884: switch (curi->size) {
1885: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1886: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1887: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1888: default: abort ();
1889: }
1890: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1891: printf ("\tretcycles = cnt;\n");
1.1 root 1892: printf ("\tCLEAR_CZNV;\n");
1893: if (source_is_imm1_8 (curi))
1894: printf ("{");
1895: else
1896: printf ("\tif (cnt > 0) {\n");
1897: printf ("\tuae_u32 loval;\n");
1898: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
1899: printf ("\tloval = val >> (%d - cnt);\n", bit_size (curi->size));
1900: printf ("\tval <<= cnt;\n");
1901: printf ("\tval |= loval;\n");
1902: printf ("\tval &= %s;\n", bit_mask (curi->size));
1903: printf ("\tSET_CFLG (val & 1);\n");
1904: printf ("}\n");
1905: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1906: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1907: if(curi->size==sz_long)
1908: strcpy(exactCpuCycles," return (8+retcycles*2);");
1909: else
1910: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1911: break;
1912: case i_ROR:
1913: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1914: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1915: start_brace ();
1916: switch (curi->size) {
1917: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1918: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1919: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1920: default: abort ();
1921: }
1922: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1923: printf ("\tretcycles = cnt;\n");
1.1 root 1924: printf ("\tCLEAR_CZNV;\n");
1925: if (source_is_imm1_8 (curi))
1926: printf ("{");
1927: else
1928: printf ("\tif (cnt > 0) {");
1929: printf ("\tuae_u32 hival;\n");
1930: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
1931: printf ("\thival = val << (%d - cnt);\n", bit_size (curi->size));
1932: printf ("\tval >>= cnt;\n");
1933: printf ("\tval |= hival;\n");
1934: printf ("\tval &= %s;\n", bit_mask (curi->size));
1935: printf ("\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
1936: printf ("\t}\n");
1937: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1938: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1939: if(curi->size==sz_long)
1940: strcpy(exactCpuCycles," return (8+retcycles*2);");
1941: else
1942: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1943: break;
1944: case i_ROXL:
1945: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1946: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1947: start_brace ();
1948: switch (curi->size) {
1949: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1950: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1951: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1952: default: abort ();
1953: }
1954: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1955: printf ("\tretcycles = cnt;\n");
1.1 root 1956: printf ("\tCLEAR_CZNV;\n");
1957: if (source_is_imm1_8 (curi))
1958: printf ("{");
1959: else {
1960: force_range_for_rox ("cnt", curi->size);
1961: printf ("\tif (cnt > 0) {\n");
1962: }
1963: printf ("\tcnt--;\n");
1964: printf ("\t{\n\tuae_u32 carry;\n");
1965: printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
1966: printf ("\tcarry = loval & 1;\n");
1967: printf ("\tval = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);\n");
1968: printf ("\tSET_XFLG (carry);\n");
1969: printf ("\tval &= %s;\n", bit_mask (curi->size));
1970: printf ("\t} }\n");
1971: printf ("\tSET_CFLG (GET_XFLG);\n");
1972: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1973: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1974: if(curi->size==sz_long)
1975: strcpy(exactCpuCycles," return (8+retcycles*2);");
1976: else
1977: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1978: break;
1979: case i_ROXR:
1980: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1981: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1982: start_brace ();
1983: switch (curi->size) {
1984: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1985: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1986: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1987: default: abort ();
1988: }
1989: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1990: printf ("\tretcycles = cnt;\n");
1.1 root 1991: printf ("\tCLEAR_CZNV;\n");
1992: if (source_is_imm1_8 (curi))
1993: printf ("{");
1994: else {
1995: force_range_for_rox ("cnt", curi->size);
1996: printf ("\tif (cnt > 0) {\n");
1997: }
1998: printf ("\tcnt--;\n");
1999: printf ("\t{\n\tuae_u32 carry;\n");
2000: printf ("\tuae_u32 hival = (val << 1) | GET_XFLG;\n");
2001: printf ("\thival <<= (%d - cnt);\n", bit_size (curi->size) - 1);
2002: printf ("\tval >>= cnt;\n");
2003: printf ("\tcarry = val & 1;\n");
2004: printf ("\tval >>= 1;\n");
2005: printf ("\tval |= hival;\n");
2006: printf ("\tSET_XFLG (carry);\n");
2007: printf ("\tval &= %s;\n", bit_mask (curi->size));
2008: printf ("\t} }\n");
2009: printf ("\tSET_CFLG (GET_XFLG);\n");
2010: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2011: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 2012: if(curi->size==sz_long)
2013: strcpy(exactCpuCycles," return (8+retcycles*2);");
2014: else
2015: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 2016: break;
2017: case i_ASRW:
2018: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2019: start_brace ();
2020: switch (curi->size) {
2021: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2022: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2023: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2024: default: abort ();
2025: }
2026: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
2027: printf ("\tuae_u32 cflg = val & 1;\n");
2028: printf ("\tval = (val >> 1) | sign;\n");
2029: genflags (flag_logical, curi->size, "val", "", "");
2030: printf ("\tSET_CFLG (cflg);\n");
2031: duplicate_carry ();
2032: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2033: break;
2034: case i_ASLW:
2035: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2036: start_brace ();
2037: switch (curi->size) {
2038: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2039: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2040: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2041: default: abort ();
2042: }
2043: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
2044: printf ("\tuae_u32 sign2;\n");
2045: printf ("\tval <<= 1;\n");
2046: genflags (flag_logical, curi->size, "val", "", "");
2047: printf ("\tsign2 = %s & val;\n", cmask (curi->size));
2048: printf ("\tSET_CFLG (sign != 0);\n");
2049: duplicate_carry ();
2050:
2051: printf ("\tSET_VFLG (GET_VFLG | (sign2 != sign));\n");
2052: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2053: break;
2054: case i_LSRW:
2055: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2056: start_brace ();
2057: switch (curi->size) {
2058: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2059: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2060: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2061: default: abort ();
2062: }
2063: printf ("\tuae_u32 carry = val & 1;\n");
2064: printf ("\tval >>= 1;\n");
2065: genflags (flag_logical, curi->size, "val", "", "");
2066: printf ("SET_CFLG (carry);\n");
2067: duplicate_carry ();
2068: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2069: break;
2070: case i_LSLW:
2071: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2072: start_brace ();
2073: switch (curi->size) {
2074: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2075: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2076: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2077: default: abort ();
2078: }
2079: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2080: printf ("\tval <<= 1;\n");
2081: genflags (flag_logical, curi->size, "val", "", "");
2082: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2083: duplicate_carry ();
2084: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2085: break;
2086: case i_ROLW:
2087: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2088: start_brace ();
2089: switch (curi->size) {
2090: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2091: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2092: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2093: default: abort ();
2094: }
2095: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2096: printf ("\tval <<= 1;\n");
2097: printf ("\tif (carry) val |= 1;\n");
2098: genflags (flag_logical, curi->size, "val", "", "");
2099: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2100: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2101: break;
2102: case i_RORW:
2103: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2104: start_brace ();
2105: switch (curi->size) {
2106: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2107: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2108: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2109: default: abort ();
2110: }
2111: printf ("\tuae_u32 carry = val & 1;\n");
2112: printf ("\tval >>= 1;\n");
2113: printf ("\tif (carry) val |= %s;\n", cmask (curi->size));
2114: genflags (flag_logical, curi->size, "val", "", "");
2115: printf ("SET_CFLG (carry);\n");
2116: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2117: break;
2118: case i_ROXLW:
2119: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2120: start_brace ();
2121: switch (curi->size) {
2122: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2123: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2124: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2125: default: abort ();
2126: }
2127: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2128: printf ("\tval <<= 1;\n");
2129: printf ("\tif (GET_XFLG) val |= 1;\n");
2130: genflags (flag_logical, curi->size, "val", "", "");
2131: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2132: duplicate_carry ();
2133: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2134: break;
2135: case i_ROXRW:
2136: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2137: start_brace ();
2138: switch (curi->size) {
2139: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2140: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2141: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2142: default: abort ();
2143: }
2144: printf ("\tuae_u32 carry = val & 1;\n");
2145: printf ("\tval >>= 1;\n");
2146: printf ("\tif (GET_XFLG) val |= %s;\n", cmask (curi->size));
2147: genflags (flag_logical, curi->size, "val", "", "");
2148: printf ("SET_CFLG (carry);\n");
2149: duplicate_carry ();
2150: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2151: break;
2152: case i_MOVEC2:
2153: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2154: start_brace ();
2155: printf ("\tint regno = (src >> 12) & 15;\n");
2156: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
2157: printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
2158: break;
2159: case i_MOVE2C:
2160: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2161: start_brace ();
2162: printf ("\tint regno = (src >> 12) & 15;\n");
2163: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
2164: printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
2165: break;
2166: case i_CAS:
2167: {
2168: int old_brace_level;
2169: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2170: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2171: start_brace ();
2172: printf ("\tint ru = (src >> 6) & 7;\n");
2173: printf ("\tint rc = src & 7;\n");
2174: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, rc)", "dst");
2175: printf ("\tif (GET_ZFLG)");
2176: old_brace_level = n_braces;
2177: start_brace ();
2178: genastore ("(m68k_dreg(regs, ru))", curi->dmode, "dstreg", curi->size, "dst");
2179: pop_braces (old_brace_level);
2180: printf ("else");
2181: start_brace ();
2182: printf ("m68k_dreg(regs, rc) = dst;\n");
2183: pop_braces (old_brace_level);
2184: }
2185: break;
2186: case i_CAS2:
2187: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2188: printf ("\tuae_u32 rn1 = regs.regs[(extra >> 28) & 15];\n");
2189: printf ("\tuae_u32 rn2 = regs.regs[(extra >> 12) & 15];\n");
2190: if (curi->size == sz_word) {
2191: int old_brace_level = n_braces;
2192: printf ("\tuae_u16 dst1 = get_word(rn1), dst2 = get_word(rn2);\n");
2193: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
2194: printf ("\tif (GET_ZFLG) {\n");
2195: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
2196: printf ("\tif (GET_ZFLG) {\n");
2197: printf ("\tput_word(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n");
2198: printf ("\tput_word(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n");
2199: printf ("\t}}\n");
2200: pop_braces (old_brace_level);
2201: printf ("\tif (! GET_ZFLG) {\n");
2202: printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = (m68k_dreg(regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
2203: printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = (m68k_dreg(regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
2204: printf ("\t}\n");
2205: } else {
2206: int old_brace_level = n_braces;
2207: printf ("\tuae_u32 dst1 = get_long(rn1), dst2 = get_long(rn2);\n");
2208: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
2209: printf ("\tif (GET_ZFLG) {\n");
2210: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
2211: printf ("\tif (GET_ZFLG) {\n");
2212: printf ("\tput_long(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n");
2213: printf ("\tput_long(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n");
2214: printf ("\t}}\n");
2215: pop_braces (old_brace_level);
2216: printf ("\tif (! GET_ZFLG) {\n");
2217: printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = dst1;\n");
2218: printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = dst2;\n");
2219: printf ("\t}\n");
2220: }
2221: break;
2222: case i_MOVES: /* ignore DFC and SFC because we have no MMU */
2223: {
2224: int old_brace_level;
2225: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2226: printf ("\tif (extra & 0x800)\n");
2227: old_brace_level = n_braces;
2228: start_brace ();
2229: printf ("\tuae_u32 src = regs.regs[(extra >> 12) & 15];\n");
2230: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
2231: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
2232: pop_braces (old_brace_level);
2233: printf ("else");
2234: start_brace ();
2235: genamode (curi->dmode, "dstreg", curi->size, "src", 1, 0);
2236: printf ("\tif (extra & 0x8000) {\n");
2237: switch (curi->size) {
2238: case sz_byte: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;\n"); break;
2239: case sz_word: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;\n"); break;
2240: case sz_long: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = src;\n"); break;
2241: default: abort ();
2242: }
2243: printf ("\t} else {\n");
2244: genastore ("src", Dreg, "(extra >> 12) & 7", curi->size, "");
2245: printf ("\t}\n");
2246: pop_braces (old_brace_level);
2247: }
2248: break;
2249: case i_BKPT: /* only needed for hardware emulators */
2250: sync_m68k_pc ();
2251: printf ("\top_illg(opcode);\n");
2252: break;
2253: case i_CALLM: /* not present in 68030 */
2254: sync_m68k_pc ();
2255: printf ("\top_illg(opcode);\n");
2256: break;
2257: case i_RTM: /* not present in 68030 */
2258: sync_m68k_pc ();
2259: printf ("\top_illg(opcode);\n");
2260: break;
2261: case i_TRAPcc:
2262: if (curi->smode != am_unknown && curi->smode != am_illg)
2263: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
1.1.1.9 root 2264: printf ("\tif (cctrue(%d)) { Exception(7,m68k_getpc(),M68000_EXCEPTION_SRC_CPU); goto %s; }\n", curi->cc, endlabelstr);
1.1 root 2265: need_endlabel = 1;
2266: break;
2267: case i_DIVL:
2268: sync_m68k_pc ();
2269: start_brace ();
2270: printf ("\tuaecptr oldpc = m68k_getpc();\n");
2271: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2272: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2273: sync_m68k_pc ();
2274: printf ("\tm68k_divl(opcode, dst, extra, oldpc);\n");
2275: break;
2276: case i_MULL:
2277: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2278: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2279: sync_m68k_pc ();
2280: printf ("\tm68k_mull(opcode, dst, extra);\n");
2281: break;
2282: case i_BFTST:
2283: case i_BFEXTU:
2284: case i_BFCHG:
2285: case i_BFEXTS:
2286: case i_BFCLR:
2287: case i_BFFFO:
2288: case i_BFSET:
2289: case i_BFINS:
2290: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2291: genamode (curi->dmode, "dstreg", sz_long, "dst", 2, 0);
2292: start_brace ();
2293: printf ("\tuae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;\n");
2294: printf ("\tint width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;\n");
2295: if (curi->dmode == Dreg) {
2296: printf ("\tuae_u32 tmp = m68k_dreg(regs, dstreg) << (offset & 0x1f);\n");
2297: } else {
2298: printf ("\tuae_u32 tmp,bf0,bf1;\n");
2299: printf ("\tdsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);\n");
2300: printf ("\tbf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;\n");
2301: printf ("\ttmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));\n");
2302: }
2303: printf ("\ttmp >>= (32 - width);\n");
2304: printf ("\tSET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);\n");
2305: printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
2306: switch (curi->mnemo) {
2307: case i_BFTST:
2308: break;
2309: case i_BFEXTU:
2310: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n");
2311: break;
2312: case i_BFCHG:
2313: printf ("\ttmp = ~tmp;\n");
2314: break;
2315: case i_BFEXTS:
2316: printf ("\tif (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);\n");
2317: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n");
2318: break;
2319: case i_BFCLR:
2320: printf ("\ttmp = 0;\n");
2321: break;
2322: case i_BFFFO:
2323: printf ("\t{ uae_u32 mask = 1 << (width-1);\n");
2324: printf ("\twhile (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}\n");
2325: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = offset;\n");
2326: break;
2327: case i_BFSET:
2328: printf ("\ttmp = 0xffffffff;\n");
2329: break;
2330: case i_BFINS:
2331: printf ("\ttmp = m68k_dreg(regs, (extra >> 12) & 7);\n");
1.1.1.4 root 2332: printf ("\tSET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);\n");
2333: printf ("\tSET_ZFLG (tmp == 0);\n");
1.1 root 2334: break;
2335: default:
2336: break;
2337: }
2338: if (curi->mnemo == i_BFCHG
2339: || curi->mnemo == i_BFCLR
2340: || curi->mnemo == i_BFSET
2341: || curi->mnemo == i_BFINS)
2342: {
2343: printf ("\ttmp <<= (32 - width);\n");
2344: if (curi->dmode == Dreg) {
2345: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ((offset & 0x1f) == 0 ? 0 :\n");
2346: printf ("\t\t(0xffffffff << (32 - (offset & 0x1f))))) |\n");
2347: printf ("\t\t(tmp >> (offset & 0x1f)) |\n");
2348: printf ("\t\t(((offset & 0x1f) + width) >= 32 ? 0 :\n");
2349: printf (" (m68k_dreg(regs, dstreg) & ((uae_u32)0xffffffff >> ((offset & 0x1f) + width))));\n");
2350: } else {
2351: printf ("\tbf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |\n");
2352: printf ("\t\t(tmp >> (offset & 7)) |\n");
2353: printf ("\t\t(((offset & 7) + width) >= 32 ? 0 :\n");
2354: printf ("\t\t (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));\n");
2355: printf ("\tput_long(dsta,bf0 );\n");
2356: printf ("\tif (((offset & 7) + width) > 32) {\n");
2357: printf ("\t\tbf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |\n");
2358: printf ("\t\t\t(tmp << (8 - (offset & 7)));\n");
2359: printf ("\t\tput_byte(dsta+4,bf1);\n");
2360: printf ("\t}\n");
2361: }
2362: }
2363: break;
2364: case i_PACK:
2365: if (curi->smode == Dreg) {
2366: printf ("\tuae_u16 val = m68k_dreg(regs, srcreg) + %s;\n", gen_nextiword ());
2367: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);\n");
2368: } else {
2369: printf ("\tuae_u16 val;\n");
2370: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2371: printf ("\tval = (uae_u16)get_byte(m68k_areg(regs, srcreg));\n");
2372: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2373: printf ("\tval = (val | ((uae_u16)get_byte(m68k_areg(regs, srcreg)) << 8)) + %s;\n", gen_nextiword ());
2374: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2375: printf ("\tput_byte(m68k_areg(regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));\n");
2376: }
2377: break;
2378: case i_UNPK:
2379: if (curi->smode == Dreg) {
2380: printf ("\tuae_u16 val = m68k_dreg(regs, srcreg);\n");
2381: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword ());
2382: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffff0000) | (val & 0xffff);\n");
2383: } else {
2384: printf ("\tuae_u16 val;\n");
2385: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2386: printf ("\tval = (uae_u16)get_byte(m68k_areg(regs, srcreg));\n");
2387: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword ());
2388: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2389: printf ("\tput_byte(m68k_areg(regs, dstreg),val);\n");
2390: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2391: printf ("\tput_byte(m68k_areg(regs, dstreg),val >> 8);\n");
2392: }
2393: break;
2394: case i_TAS:
2395: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2396: genflags (flag_logical, curi->size, "src", "", "");
2397: printf ("\tsrc |= 0x80;\n");
2398: genastore ("src", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 2399: if( curi->smode!=Dreg ) insn_n_cycles += 2;
1.1 root 2400: break;
2401: case i_FPP:
2402: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2403: sync_m68k_pc ();
2404: printf ("\tfpp_opp(opcode,extra);\n");
2405: break;
2406: case i_FDBcc:
2407: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2408: sync_m68k_pc ();
2409: printf ("\tfdbcc_opp(opcode,extra);\n");
2410: break;
2411: case i_FScc:
2412: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2413: sync_m68k_pc ();
2414: printf ("\tfscc_opp(opcode,extra);\n");
2415: break;
2416: case i_FTRAPcc:
2417: sync_m68k_pc ();
2418: start_brace ();
2419: printf ("\tuaecptr oldpc = m68k_getpc();\n");
2420: if (curi->smode != am_unknown && curi->smode != am_illg)
2421: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
2422: sync_m68k_pc ();
2423: printf ("\tftrapcc_opp(opcode,oldpc);\n");
2424: break;
2425: case i_FBcc:
2426: sync_m68k_pc ();
2427: start_brace ();
2428: printf ("\tuaecptr pc = m68k_getpc();\n");
2429: genamode (curi->dmode, "srcreg", curi->size, "extra", 1, 0);
2430: sync_m68k_pc ();
2431: printf ("\tfbcc_opp(opcode,pc,extra);\n");
2432: break;
2433: case i_FSAVE:
2434: sync_m68k_pc ();
2435: printf ("\tfsave_opp(opcode);\n");
2436: break;
2437: case i_FRESTORE:
2438: sync_m68k_pc ();
2439: printf ("\tfrestore_opp(opcode);\n");
2440: break;
2441:
2442: case i_CINVL:
2443: case i_CINVP:
2444: case i_CINVA:
2445: case i_CPUSHL:
2446: case i_CPUSHP:
2447: case i_CPUSHA:
2448: break;
2449: case i_MOVE16:
1.1.1.4 root 2450: if ((opcode & 0xfff8) == 0xf620) {
2451: /* MOVE16 (Ax)+,(Ay)+ */
2452: printf ("\tuaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
2453: printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword());
2454: printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n");
2455: printf ("\tput_long(memd, get_long(mems));\n");
2456: printf ("\tput_long(memd+4, get_long(mems+4));\n");
2457: printf ("\tput_long(memd+8, get_long(mems+8));\n");
2458: printf ("\tput_long(memd+12, get_long(mems+12));\n");
2459: printf ("\tif (srcreg != dstreg)\n");
2460: printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2461: printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2462: } else {
2463: /* Other variants */
2464: genamode (curi->smode, "srcreg", curi->size, "mems", 0, 2);
2465: genamode (curi->dmode, "dstreg", curi->size, "memd", 0, 2);
2466: printf ("\tmemsa &= ~15;\n");
2467: printf ("\tmemda &= ~15;\n");
2468: printf ("\tput_long(memda, get_long(memsa));\n");
2469: printf ("\tput_long(memda+4, get_long(memsa+4));\n");
2470: printf ("\tput_long(memda+8, get_long(memsa+8));\n");
2471: printf ("\tput_long(memda+12, get_long(memsa+12));\n");
2472: if ((opcode & 0xfff8) == 0xf600)
2473: printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2474: else if ((opcode & 0xfff8) == 0xf608)
2475: printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2476: }
1.1 root 2477: break;
2478:
2479: case i_MMUOP:
2480: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2481: sync_m68k_pc ();
2482: printf ("\tmmu_op(opcode,extra);\n");
2483: break;
2484: default:
2485: abort ();
2486: break;
2487: }
2488: finish_braces ();
2489: sync_m68k_pc ();
2490: }
2491:
2492: static void generate_includes (FILE * f)
2493: {
2494: fprintf (f, "#include \"sysdeps.h\"\n");
2495: fprintf (f, "#include \"hatari-glue.h\"\n");
2496: fprintf (f, "#include \"maccess.h\"\n");
2497: fprintf (f, "#include \"memory.h\"\n");
2498: fprintf (f, "#include \"newcpu.h\"\n");
2499: fprintf (f, "#include \"cputbl.h\"\n");
2500: fprintf (f, "#define CPUFUNC(x) x##_ff\n"
2501: "#ifdef NOFLAGS\n"
2502: "#include \"noflags.h\"\n"
2503: "#endif\n");
2504: }
2505:
2506: static int postfix;
2507:
2508: static void generate_one_opcode (int rp)
2509: {
2510: int i;
2511: uae_u16 smsk, dmsk;
2512: long int opcode = opcode_map[rp];
2513:
1.1.1.2 root 2514: exactCpuCycles[0] = 0; /* Default: not used */
2515:
1.1 root 2516: if (table68k[opcode].mnemo == i_ILLG
2517: || table68k[opcode].clev > cpu_level)
2518: return;
2519:
2520: for (i = 0; lookuptab[i].name[0]; i++) {
2521: if (table68k[opcode].mnemo == lookuptab[i].mnemo)
2522: break;
2523: }
2524:
2525: if (table68k[opcode].handler != -1)
2526: return;
2527:
2528: if (opcode_next_clev[rp] != cpu_level) {
2529: fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp],
2530: opcode, lookuptab[i].name);
2531: return;
2532: }
2533: fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, postfix, opcode, lookuptab[i].name);
2534: fprintf (headerfile, "extern cpuop_func op_%lx_%d_nf;\n", opcode, postfix);
2535: fprintf (headerfile, "extern cpuop_func op_%lx_%d_ff;\n", opcode, postfix);
2536: printf ("unsigned long REGPARAM2 CPUFUNC(op_%lx_%d)(uae_u32 opcode) /* %s */\n{\n", opcode, postfix, lookuptab[i].name);
2537:
2538: switch (table68k[opcode].stype) {
2539: case 0: smsk = 7; break;
2540: case 1: smsk = 255; break;
2541: case 2: smsk = 15; break;
2542: case 3: smsk = 7; break;
2543: case 4: smsk = 7; break;
2544: case 5: smsk = 63; break;
1.1.1.4 root 2545: case 7: smsk = 3; break;
1.1 root 2546: default: abort ();
2547: }
2548: dmsk = 7;
2549:
2550: next_cpu_level = -1;
2551: if (table68k[opcode].suse
2552: && table68k[opcode].smode != imm && table68k[opcode].smode != imm0
2553: && table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
2554: && table68k[opcode].smode != absw && table68k[opcode].smode != absl
2555: && table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
2556: {
2557: if (table68k[opcode].spos == -1) {
2558: if (((int) table68k[opcode].sreg) >= 128)
2559: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].sreg);
2560: else
2561: printf ("\tuae_u32 srcreg = %d;\n", (int) table68k[opcode].sreg);
2562: } else {
2563: char source[100];
2564: int pos = table68k[opcode].spos;
2565:
2566: if (pos)
2567: sprintf (source, "((opcode >> %d) & %d)", pos, smsk);
2568: else
2569: sprintf (source, "(opcode & %d)", smsk);
2570:
2571: if (table68k[opcode].stype == 3)
2572: printf ("\tuae_u32 srcreg = imm8_table[%s];\n", source);
2573: else if (table68k[opcode].stype == 1)
2574: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%s;\n", source);
2575: else
2576: printf ("\tuae_u32 srcreg = %s;\n", source);
2577: }
2578: }
2579: if (table68k[opcode].duse
2580: /* Yes, the dmode can be imm, in case of LINK or DBcc */
2581: && table68k[opcode].dmode != imm && table68k[opcode].dmode != imm0
2582: && table68k[opcode].dmode != imm1 && table68k[opcode].dmode != imm2
2583: && table68k[opcode].dmode != absw && table68k[opcode].dmode != absl)
2584: {
2585: if (table68k[opcode].dpos == -1) {
2586: if (((int) table68k[opcode].dreg) >= 128)
2587: printf ("\tuae_u32 dstreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].dreg);
2588: else
2589: printf ("\tuae_u32 dstreg = %d;\n", (int) table68k[opcode].dreg);
2590: } else {
2591: int pos = table68k[opcode].dpos;
2592: #if 0
2593: /* Check that we can do the little endian optimization safely. */
2594: if (pos < 8 && (dmsk >> (8 - pos)) != 0)
2595: abort ();
2596: #endif
2597: if (pos)
2598: printf ("\tuae_u32 dstreg = (opcode >> %d) & %d;\n",
2599: pos, dmsk);
2600: else
2601: printf ("\tuae_u32 dstreg = opcode & %d;\n", dmsk);
2602: }
2603: }
2604: need_endlabel = 0;
2605: endlabelno++;
2606: sprintf (endlabelstr, "endlabel%d", endlabelno);
1.1.1.2 root 2607: if(table68k[opcode].mnemo==i_ASR || table68k[opcode].mnemo==i_ASL || table68k[opcode].mnemo==i_LSR || table68k[opcode].mnemo==i_LSL
2608: || table68k[opcode].mnemo==i_ROL || table68k[opcode].mnemo==i_ROR || table68k[opcode].mnemo==i_ROXL || table68k[opcode].mnemo==i_ROXR
1.1.1.8 root 2609: || table68k[opcode].mnemo==i_MVMEL || table68k[opcode].mnemo==i_MVMLE
2610: || table68k[opcode].mnemo==i_MULU || table68k[opcode].mnemo==i_MULS
2611: || table68k[opcode].mnemo==i_DIVU || table68k[opcode].mnemo==i_DIVS )
2612: printf("\tunsigned int retcycles = 0;\n");
1.1 root 2613: gen_opcode (opcode);
2614: if (need_endlabel)
2615: printf ("%s: ;\n", endlabelstr);
1.1.1.8 root 2616:
2617: if (strlen(exactCpuCycles) > 0)
2618: printf("%s\n",exactCpuCycles);
2619: else
2620: printf ("return %d;\n", insn_n_cycles);
2621: /* Now patch in the instruction cycles at the beginning of the function: */
2622: fseek(stdout, nCurInstrCycPos, SEEK_SET);
2623: printf("%d;", insn_n_cycles);
2624: fseek(stdout, 0, SEEK_END);
2625:
1.1 root 2626: printf ("}\n");
2627: opcode_next_clev[rp] = next_cpu_level;
2628: opcode_last_postfix[rp] = postfix;
2629: }
2630:
2631: static void generate_func (void)
2632: {
2633: int i, j, rp;
2634:
2635: using_prefetch = 0;
2636: using_exception_3 = 0;
2637: for (i = 0; i < 6; i++) {
2638: cpu_level = 4 - i;
2639: if (i == 5) {
2640: cpu_level = 0;
2641: using_prefetch = 1;
2642: using_exception_3 = 1;
2643: for (rp = 0; rp < nr_cpuop_funcs; rp++)
2644: opcode_next_clev[rp] = 0;
2645: }
2646:
2647: postfix = i;
1.1.1.7 root 2648: fprintf (stblfile, "const struct cputbl CPUFUNC(op_smalltbl_%d)[] = {\n", postfix);
1.1 root 2649:
2650: /* sam: this is for people with low memory (eg. me :)) */
2651: printf ("\n"
2652: "#if !defined(PART_1) && !defined(PART_2) && "
2653: "!defined(PART_3) && !defined(PART_4) && "
2654: "!defined(PART_5) && !defined(PART_6) && "
2655: "!defined(PART_7) && !defined(PART_8)"
2656: "\n"
2657: "#define PART_1 1\n"
2658: "#define PART_2 1\n"
2659: "#define PART_3 1\n"
2660: "#define PART_4 1\n"
2661: "#define PART_5 1\n"
2662: "#define PART_6 1\n"
2663: "#define PART_7 1\n"
2664: "#define PART_8 1\n"
2665: "#endif\n\n");
2666:
2667: rp = 0;
2668: for(j=1;j<=8;++j) {
2669: int k = (j*nr_cpuop_funcs)/8;
2670: printf ("#ifdef PART_%d\n",j);
2671: for (; rp < k; rp++)
2672: generate_one_opcode (rp);
2673: printf ("#endif\n\n");
2674: }
2675:
2676: fprintf (stblfile, "{ 0, 0, 0 }};\n");
2677: }
2678:
2679: }
2680:
2681: int main (int argc, char **argv)
2682: {
2683: read_table68k ();
2684: do_merges ();
2685:
2686: opcode_map = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2687: opcode_last_postfix = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2688: opcode_next_clev = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2689: counts = (unsigned long *) malloc (65536 * sizeof (unsigned long));
2690: read_counts ();
2691:
2692: /* It would be a lot nicer to put all in one file (we'd also get rid of
2693: * cputbl.h that way), but cpuopti can't cope. That could be fixed, but
2694: * I don't dare to touch the 68k version. */
2695:
2696: headerfile = fopen ("cputbl.h", "wb");
2697: stblfile = fopen ("cpustbl.c", "wb");
1.1.1.11! root 2698: if (freopen ("cpuemu.c", "wb", stdout) == NULL) {
! 2699: perror("cpuemu.c");
! 2700: return -1;
! 2701: }
1.1 root 2702:
2703: generate_includes (stdout);
2704: generate_includes (stblfile);
2705:
2706: generate_func ();
2707:
2708: free (table68k);
2709: return 0;
2710: }
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