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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation generator
5: *
6: * This is a fairly stupid program that generates a lot of case labels that
7: * can be #included in a switch statement.
8: * As an alternative, it can generate functions that handle specific
9: * MC68000 instructions, plus a prototype header file and a function pointer
10: * array to look up the function for an opcode.
11: * Error checking is bad, an illegal table68k file will cause the program to
12: * call abort().
13: * The generated code is sometimes sub-optimal, an optimizing compiler should
14: * take care of this.
15: *
16: * The source for the insn timings is Markt & Technik's Amiga Magazin 8/1992.
17: *
18: * Copyright 1995, 1996, 1997, 1998, 1999, 2000 Bernd Schmidt
1.1.1.2 root 19: *
20: * Adaptation to Hatari and better cpu timings by Thomas Huth
21: *
1.1.1.4 root 22: * This file is distributed under the GNU Public License, version 2 or at
23: * your option any later version. Read the file gpl.txt for details.
1.1 root 24: */
1.1.1.8 root 25:
26:
27: /* 2007/03/xx [NP] Use add_cycles.pl to set 'CurrentInstrCycles' in each opcode. */
28: /* 2007/04/09 [NP] Correct CLR : on 68000, CLR reads the memory before clearing it (but we should */
29: /* not add cycles for reading). This means CLR can give 2 wait states (one for */
30: /* read and one for right) (clr.b $fa1b.w in Decade's Demo Main Menu). */
31: /* 2007/04/14 [NP] - Although dest -(an) normally takes 2 cycles, this is not the case for move : */
32: /* move dest (an), (an)+ and -(an) all take the same time (curi->dmode == Apdi) */
33: /* (Syntax Terror Demo Reset). */
34: /* - Scc takes 6 cycles instead of 4 if the result is true (Ventura Demo Loader). */
35: /* - Store the family of the current opcode into OpcodeFamily : used to check */
36: /* instruction pairing on ST into m68000.c */
37: /* 2007/04/17 [NP] Add support for cycle accurate MULU (No Cooper Greeting Screen). */
38: /* 2007/04/24 [NP] BCLR #n,Dx takes 12 cycles instead of 14 if n<16 (ULM Demo Menu). */
39: /* 2007/04/25 [NP] On ST, d8(An,Xn) and d8(PC,Xn) take 2 cycles more than the official 68000's */
40: /* table (ULM Demo Menu). */
41: /* 2007/11/12 [NP] Add refill_prefetch for i_ADD to fix Transbeauce 2 demo self modified code. */
42: /* Ugly hack, we need better prefetch emulation (switch to winuae gencpu.c) */
43: /* 2007/11/25 [NP] In i_DBcc, in case of address error, last_addr_for_exception_3 should be */
44: /* pc+4, not pc+2 (Transbeauce 2 demo) (e.g. 'dbf d0,#$fff5'). */
45: /* This means the value pushed on the frame stack should be the address of the */
46: /* instruction following the one generating the address error. */
47: /* FIXME : this should be the case for i_BSR and i_BCC too (need to check on */
48: /* a real 68000). */
49: /* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */
50: /* Cwik, [email protected]). */
51: /* 2007/12/08 [NP] In case of CHK/CHK2 exception, PC stored on the stack wasn't pointing to the */
52: /* next instruction but to the current CHK/CHK2 instruction (Transbeauce 2 demo). */
53: /* We need to call 'sync_m68k_pc' before calling 'Exception'. */
54: /* 2007/12/09 [NP] CHK.L (e.g. $4700) doesn't exist on 68000 and should be considered as an illegal*/
55: /* instruction (Transbeauce 2 demo) -> change in table68k. */
56: /* 2008/01/24 [NP] BCLR Dy,Dx takes 8 cycles instead of 10 if Dy<16 (Fullshade in Anomaly Demos). */
57: /* 2008/01/26 [NP] On ST, d8(An,Xn) takes 2 cycles more when used with ADDA/SUBA (ULM Demo Menu) */
58: /* but not when used with MOVE (e.g. 'move.l 0(a5,d1),(a4)' takes 26 cycles and so */
59: /* can pair with a lsr) (Anomaly Demo Intro). */
1.1.1.9 root 60: /* 2008/04/26 [NP] Handle sz_byte for Areg in genamode, as 'move.b a1,(a0)' ($1089) is possible */
61: /* on ST (fix Blood Money on Superior 65) */
1.1.1.12 root 62: /* 2010/04/05 [NP] On ST, d8(An,Xn) takes 2 cycles more (which can generate pairing). */
63: /* Use BusCyclePenalty to properly handle the 2/4 cycles added in that case when */
64: /* addressing mode is Ad8r or PC8r (ULM Demo Menu, Anomaly Demo Intro, DHS */
65: /* Sommarhack 2010) (see m68000.h) */
1.1.1.8 root 66:
67:
1.1.1.11 root 68: const char GenCpu_fileid[] = "Hatari gencpu.c : " __DATE__ " " __TIME__;
1.1 root 69:
70: #include <ctype.h>
1.1.1.3 root 71: #include <string.h>
1.1 root 72:
73: #include "sysdeps.h"
74: #include "readcpu.h"
75:
76: #define BOOL_TYPE "int"
77:
78: static FILE *headerfile;
79: static FILE *stblfile;
80:
81: static int using_prefetch;
82: static int using_exception_3;
83: static int cpu_level;
84:
1.1.1.2 root 85: char exactCpuCycles[256]; /* Space to store return string for exact cpu cycles */
86:
1.1.1.8 root 87: long nCurInstrCycPos; /* Stores where we have to patch in the current cycles value */
1.1.1.2 root 88:
1.1 root 89: /* For the current opcode, the next lower level that will have different code.
90: * Initialized to -1 for each opcode. If it remains unchanged, indicates we
91: * are done with that opcode. */
92: static int next_cpu_level;
93: static int *opcode_map;
94: static int *opcode_next_clev;
95: static int *opcode_last_postfix;
96: static unsigned long *counts;
97:
1.1.1.6 root 98:
1.1 root 99: static void read_counts (void)
100: {
101: FILE *file;
102: unsigned long opcode, count, total;
103: char name[20];
104: int nr = 0;
105: memset (counts, 0, 65536 * sizeof *counts);
106:
107: file = fopen ("frequent.68k", "r");
108: if (file) {
1.1.1.11 root 109: if (fscanf (file, "Total: %lu\n", &total) == EOF) {
110: perror("read_counts");
111: }
1.1 root 112: while (fscanf (file, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
113: opcode_next_clev[nr] = 4;
114: opcode_last_postfix[nr] = -1;
115: opcode_map[nr++] = opcode;
116: counts[opcode] = count;
117: }
118: fclose (file);
119: }
120: if (nr == nr_cpuop_funcs)
121: return;
122: for (opcode = 0; opcode < 0x10000; opcode++) {
123: if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
124: && counts[opcode] == 0)
125: {
126: opcode_next_clev[nr] = 4;
127: opcode_last_postfix[nr] = -1;
128: opcode_map[nr++] = opcode;
129: counts[opcode] = count;
130: }
131: }
132: if (nr != nr_cpuop_funcs)
133: abort ();
134: }
135:
136: static char endlabelstr[80];
137: static int endlabelno = 0;
138: static int need_endlabel;
139:
140: static int n_braces = 0;
141: static int m68k_pc_offset = 0;
142: static int insn_n_cycles;
143:
144: static void start_brace (void)
145: {
146: n_braces++;
147: printf ("{");
148: }
149:
150: static void close_brace (void)
151: {
152: assert (n_braces > 0);
153: n_braces--;
154: printf ("}");
155: }
156:
157: static void finish_braces (void)
158: {
159: while (n_braces > 0)
160: close_brace ();
161: }
162:
163: static void pop_braces (int to)
164: {
165: while (n_braces > to)
166: close_brace ();
167: }
168:
169: static int bit_size (int size)
170: {
171: switch (size) {
172: case sz_byte: return 8;
173: case sz_word: return 16;
174: case sz_long: return 32;
175: default: abort ();
176: }
177: return 0;
178: }
179:
180: static const char *bit_mask (int size)
181: {
182: switch (size) {
183: case sz_byte: return "0xff";
184: case sz_word: return "0xffff";
185: case sz_long: return "0xffffffff";
186: default: abort ();
187: }
188: return 0;
189: }
190:
191: static const char *gen_nextilong (void)
192: {
193: static char buffer[80];
194: int r = m68k_pc_offset;
195: m68k_pc_offset += 4;
196:
197: insn_n_cycles += 8;
198:
199: if (using_prefetch)
200: sprintf (buffer, "get_ilong_prefetch(%d)", r);
201: else
202: sprintf (buffer, "get_ilong(%d)", r);
203: return buffer;
204: }
205:
206: static const char *gen_nextiword (void)
207: {
208: static char buffer[80];
209: int r = m68k_pc_offset;
210: m68k_pc_offset += 2;
211:
212: insn_n_cycles += 4;
213:
214: if (using_prefetch)
215: sprintf (buffer, "get_iword_prefetch(%d)", r);
216: else
217: sprintf (buffer, "get_iword(%d)", r);
218: return buffer;
219: }
220:
221: static const char *gen_nextibyte (void)
222: {
223: static char buffer[80];
224: int r = m68k_pc_offset;
225: m68k_pc_offset += 2;
226:
227: insn_n_cycles += 4;
228:
229: if (using_prefetch)
230: sprintf (buffer, "get_ibyte_prefetch(%d)", r);
231: else
232: sprintf (buffer, "get_ibyte(%d)", r);
233: return buffer;
234: }
235:
236: static void fill_prefetch_0 (void)
237: {
238: if (using_prefetch)
239: printf ("fill_prefetch_0 ();\n");
240: }
241:
242: static void fill_prefetch_2 (void)
243: {
244: if (using_prefetch)
245: printf ("fill_prefetch_2 ();\n");
246: }
247:
248: static void sync_m68k_pc (void)
249: {
250: if (m68k_pc_offset == 0)
251: return;
252: printf ("m68k_incpc(%d);\n", m68k_pc_offset);
253: switch (m68k_pc_offset) {
254: case 0:
255: /*fprintf (stderr, "refilling prefetch at 0\n"); */
256: break;
257: case 2:
258: fill_prefetch_2 ();
259: break;
260: default:
261: fill_prefetch_0 ();
262: break;
263: }
264: m68k_pc_offset = 0;
265: }
266:
267: /* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
1.1.1.4 root 268: * the calling routine handles Apdi and Aipi modes.
269: * gb-- movem == 2 means the same thing but for a MOVE16 instruction */
1.1.1.12 root 270: static void genamode (amodes mode, const char *reg, wordsizes size,
271: const char *name, int getv, int movem)
1.1 root 272: {
273: start_brace ();
274: switch (mode) {
275: case Dreg:
276: if (movem)
277: abort ();
278: if (getv == 1)
279: switch (size) {
280: case sz_byte:
281: printf ("\tuae_s8 %s = m68k_dreg(regs, %s);\n", name, reg);
282: break;
283: case sz_word:
284: printf ("\tuae_s16 %s = m68k_dreg(regs, %s);\n", name, reg);
285: break;
286: case sz_long:
287: printf ("\tuae_s32 %s = m68k_dreg(regs, %s);\n", name, reg);
288: break;
289: default:
290: abort ();
291: }
292: return;
293: case Areg:
294: if (movem)
295: abort ();
296: if (getv == 1)
297: switch (size) {
1.1.1.9 root 298: case sz_byte: // [NP] Areg with .b is possible in MOVE source */
299: printf ("\tuae_s8 %s = m68k_areg(regs, %s);\n", name, reg);
300: break;
1.1 root 301: case sz_word:
302: printf ("\tuae_s16 %s = m68k_areg(regs, %s);\n", name, reg);
303: break;
304: case sz_long:
305: printf ("\tuae_s32 %s = m68k_areg(regs, %s);\n", name, reg);
306: break;
307: default:
308: abort ();
309: }
310: return;
311: case Aind:
312: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
313: break;
314: case Aipi:
315: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
316: break;
317: case Apdi:
318: insn_n_cycles += 2;
319: switch (size) {
320: case sz_byte:
321: if (movem)
322: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
323: else
324: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - areg_byteinc[%s];\n", name, reg, reg);
325: break;
326: case sz_word:
327: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 2);
328: break;
329: case sz_long:
330: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 4);
331: break;
332: default:
333: abort ();
334: }
335: break;
336: case Ad16:
337: printf ("\tuaecptr %sa = m68k_areg(regs, %s) + (uae_s32)(uae_s16)%s;\n", name, reg, gen_nextiword ());
338: break;
339: case Ad8r:
340: insn_n_cycles += 2;
341: if (cpu_level > 1) {
342: if (next_cpu_level < 1)
343: next_cpu_level = 1;
344: sync_m68k_pc ();
345: start_brace ();
346: /* This would ordinarily be done in gen_nextiword, which we bypass. */
347: insn_n_cycles += 4;
348: printf ("\tuaecptr %sa = get_disp_ea_020(m68k_areg(regs, %s), next_iword());\n", name, reg);
1.1.1.8 root 349: } else {
1.1 root 350: printf ("\tuaecptr %sa = get_disp_ea_000(m68k_areg(regs, %s), %s);\n", name, reg, gen_nextiword ());
1.1.1.8 root 351: }
1.1.1.12 root 352: printf ("\tBusCyclePenalty += 2;\n");
1.1 root 353:
354: break;
355: case PC16:
356: printf ("\tuaecptr %sa = m68k_getpc () + %d;\n", name, m68k_pc_offset);
357: printf ("\t%sa += (uae_s32)(uae_s16)%s;\n", name, gen_nextiword ());
358: break;
359: case PC8r:
360: insn_n_cycles += 2;
361: if (cpu_level > 1) {
362: if (next_cpu_level < 1)
363: next_cpu_level = 1;
364: sync_m68k_pc ();
365: start_brace ();
366: /* This would ordinarily be done in gen_nextiword, which we bypass. */
367: insn_n_cycles += 4;
368: printf ("\tuaecptr tmppc = m68k_getpc();\n");
369: printf ("\tuaecptr %sa = get_disp_ea_020(tmppc, next_iword());\n", name);
370: } else {
371: printf ("\tuaecptr tmppc = m68k_getpc() + %d;\n", m68k_pc_offset);
372: printf ("\tuaecptr %sa = get_disp_ea_000(tmppc, %s);\n", name, gen_nextiword ());
373: }
1.1.1.12 root 374: printf ("\tBusCyclePenalty += 2;\n");
1.1 root 375:
376: break;
377: case absw:
378: printf ("\tuaecptr %sa = (uae_s32)(uae_s16)%s;\n", name, gen_nextiword ());
379: break;
380: case absl:
381: printf ("\tuaecptr %sa = %s;\n", name, gen_nextilong ());
382: break;
383: case imm:
384: if (getv != 1)
385: abort ();
386: switch (size) {
387: case sz_byte:
388: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte ());
389: break;
390: case sz_word:
391: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword ());
392: break;
393: case sz_long:
394: printf ("\tuae_s32 %s = %s;\n", name, gen_nextilong ());
395: break;
396: default:
397: abort ();
398: }
399: return;
400: case imm0:
401: if (getv != 1)
402: abort ();
403: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte ());
404: return;
405: case imm1:
406: if (getv != 1)
407: abort ();
408: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword ());
409: return;
410: case imm2:
411: if (getv != 1)
412: abort ();
413: printf ("\tuae_s32 %s = %s;\n", name, gen_nextilong ());
414: return;
415: case immi:
416: if (getv != 1)
417: abort ();
418: printf ("\tuae_u32 %s = %s;\n", name, reg);
419: return;
420: default:
421: abort ();
422: }
423:
424: /* We get here for all non-reg non-immediate addressing modes to
425: * actually fetch the value. */
426:
427: if (using_exception_3 && getv != 0 && size != sz_byte) {
428: printf ("\tif ((%sa & 1) != 0) {\n", name);
429: printf ("\t\tlast_fault_for_exception_3 = %sa;\n", name);
430: printf ("\t\tlast_op_for_exception_3 = opcode;\n");
431: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + %d;\n", m68k_pc_offset);
1.1.1.12 root 432: printf ("\t\tException(3, 0, M68000_EXC_SRC_CPU);\n");
1.1 root 433: printf ("\t\tgoto %s;\n", endlabelstr);
434: printf ("\t}\n");
435: need_endlabel = 1;
436: start_brace ();
437: }
438:
439: if (getv == 1) {
440: switch (size) {
441: case sz_byte: insn_n_cycles += 4; break;
442: case sz_word: insn_n_cycles += 4; break;
443: case sz_long: insn_n_cycles += 8; break;
444: default: abort ();
445: }
446: start_brace ();
447: switch (size) {
448: case sz_byte: printf ("\tuae_s8 %s = get_byte(%sa);\n", name, name); break;
449: case sz_word: printf ("\tuae_s16 %s = get_word(%sa);\n", name, name); break;
450: case sz_long: printf ("\tuae_s32 %s = get_long(%sa);\n", name, name); break;
451: default: abort ();
452: }
453: }
454:
455: /* We now might have to fix up the register for pre-dec or post-inc
456: * addressing modes. */
457: if (!movem)
458: switch (mode) {
459: case Aipi:
460: switch (size) {
461: case sz_byte:
462: printf ("\tm68k_areg(regs, %s) += areg_byteinc[%s];\n", reg, reg);
463: break;
464: case sz_word:
465: printf ("\tm68k_areg(regs, %s) += 2;\n", reg);
466: break;
467: case sz_long:
468: printf ("\tm68k_areg(regs, %s) += 4;\n", reg);
469: break;
470: default:
471: abort ();
472: }
473: break;
474: case Apdi:
475: printf ("\tm68k_areg (regs, %s) = %sa;\n", reg, name);
476: break;
477: default:
478: break;
479: }
480: }
481:
1.1.1.12 root 482: static void genastore (const char *from, amodes mode, const char *reg,
483: wordsizes size, const char *to)
1.1 root 484: {
485: switch (mode) {
486: case Dreg:
487: switch (size) {
488: case sz_byte:
489: printf ("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from);
490: break;
491: case sz_word:
492: printf ("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from);
493: break;
494: case sz_long:
495: printf ("\tm68k_dreg(regs, %s) = (%s);\n", reg, from);
496: break;
497: default:
498: abort ();
499: }
500: break;
501: case Areg:
502: switch (size) {
503: case sz_word:
504: fprintf (stderr, "Foo\n");
505: printf ("\tm68k_areg(regs, %s) = (uae_s32)(uae_s16)(%s);\n", reg, from);
506: break;
507: case sz_long:
508: printf ("\tm68k_areg(regs, %s) = (%s);\n", reg, from);
509: break;
510: default:
511: abort ();
512: }
513: break;
514: case Aind:
515: case Aipi:
516: case Apdi:
517: case Ad16:
518: case Ad8r:
519: case absw:
520: case absl:
521: case PC16:
522: case PC8r:
523: if (using_prefetch)
524: sync_m68k_pc ();
525: switch (size) {
526: case sz_byte:
527: insn_n_cycles += 4;
528: printf ("\tput_byte(%sa,%s);\n", to, from);
529: break;
530: case sz_word:
531: insn_n_cycles += 4;
532: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
533: abort ();
534: printf ("\tput_word(%sa,%s);\n", to, from);
535: break;
536: case sz_long:
537: insn_n_cycles += 8;
538: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
539: abort ();
540: printf ("\tput_long(%sa,%s);\n", to, from);
541: break;
542: default:
543: abort ();
544: }
545: break;
546: case imm:
547: case imm0:
548: case imm1:
549: case imm2:
550: case immi:
551: abort ();
552: break;
553: default:
554: abort ();
555: }
556: }
557:
1.1.1.2 root 558:
1.1 root 559: static void genmovemel (uae_u16 opcode)
560: {
561: char getcode[100];
1.1.1.3 root 562: int bMovemLong = (table68k[opcode].size == sz_long);
563: int size = bMovemLong ? 4 : 2;
1.1 root 564:
1.1.1.3 root 565: if (bMovemLong) {
1.1 root 566: strcpy (getcode, "get_long(srca)");
567: } else {
568: strcpy (getcode, "(uae_s32)(uae_s16)get_word(srca)");
569: }
570:
571: printf ("\tuae_u16 mask = %s;\n", gen_nextiword ());
572: printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1.1.1.2 root 573: printf ("\tretcycles = 0;\n");
1.1.1.3 root 574: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1);
1.1 root 575: start_brace ();
1.1.1.2 root 576: printf ("\twhile (dmask) { m68k_dreg(regs, movem_index1[dmask]) = %s;"
1.1.1.3 root 577: " srca += %d; dmask = movem_next[dmask]; retcycles+=%d; }\n",
578: getcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 579: printf ("\twhile (amask) { m68k_areg(regs, movem_index1[amask]) = %s;"
1.1.1.3 root 580: " srca += %d; amask = movem_next[amask]; retcycles+=%d; }\n",
581: getcode, size, (bMovemLong ? 8 : 4));
1.1 root 582:
583: if (table68k[opcode].dmode == Aipi)
584: printf ("\tm68k_areg(regs, dstreg) = srca;\n");
1.1.1.2 root 585:
586: /* Better cycles - experimental! (Thothy) */
587: switch(table68k[opcode].dmode)
1.1.1.3 root 588: {
1.1.1.2 root 589: case Aind: insn_n_cycles=12; break;
590: case Aipi: insn_n_cycles=12; break;
591: case Ad16: insn_n_cycles=16; break;
592: case Ad8r: insn_n_cycles=18; break;
593: case absw: insn_n_cycles=16; break;
594: case absl: insn_n_cycles=20; break;
595: case PC16: insn_n_cycles=16; break;
596: case PC8r: insn_n_cycles=18; break;
1.1.1.3 root 597: }
598: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 599: }
600:
601: static void genmovemle (uae_u16 opcode)
602: {
603: char putcode[100];
1.1.1.3 root 604: int bMovemLong = (table68k[opcode].size == sz_long);
605: int size = bMovemLong ? 4 : 2;
606:
607: if (bMovemLong) {
1.1 root 608: strcpy (putcode, "put_long(srca,");
609: } else {
610: strcpy (putcode, "put_word(srca,");
611: }
612:
613: printf ("\tuae_u16 mask = %s;\n", gen_nextiword ());
1.1.1.3 root 614: printf ("\tretcycles = 0;\n");
1.1 root 615: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1);
616: if (using_prefetch)
617: sync_m68k_pc ();
618:
619: start_brace ();
620: if (table68k[opcode].dmode == Apdi) {
1.1.1.2 root 621: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
622: printf ("\twhile (amask) { srca -= %d; %s m68k_areg(regs, movem_index2[amask]));"
1.1.1.3 root 623: " amask = movem_next[amask]; retcycles+=%d; }\n",
624: size, putcode, (bMovemLong ? 8 : 4));
1.1.1.2 root 625: printf ("\twhile (dmask) { srca -= %d; %s m68k_dreg(regs, movem_index2[dmask]));"
1.1.1.3 root 626: " dmask = movem_next[dmask]; retcycles+=%d; }\n",
627: size, putcode, (bMovemLong ? 8 : 4));
1.1.1.2 root 628: printf ("\tm68k_areg(regs, dstreg) = srca;\n");
1.1 root 629: } else {
1.1.1.2 root 630: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
631: printf ("\twhile (dmask) { %s m68k_dreg(regs, movem_index1[dmask])); srca += %d;"
1.1.1.3 root 632: " dmask = movem_next[dmask]; retcycles+=%d; }\n",
633: putcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 634: printf ("\twhile (amask) { %s m68k_areg(regs, movem_index1[amask])); srca += %d;"
1.1.1.3 root 635: " amask = movem_next[amask]; retcycles+=%d; }\n",
636: putcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 637: }
638:
639: /* Better cycles - experimental! (Thothy) */
640: switch(table68k[opcode].dmode)
1.1.1.3 root 641: {
1.1.1.2 root 642: case Aind: insn_n_cycles=8; break;
643: case Apdi: insn_n_cycles=8; break;
644: case Ad16: insn_n_cycles=12; break;
645: case Ad8r: insn_n_cycles=14; break;
646: case absw: insn_n_cycles=12; break;
647: case absl: insn_n_cycles=16; break;
1.1.1.3 root 648: }
649: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 650: }
651:
1.1.1.2 root 652:
1.1 root 653: static void duplicate_carry (void)
654: {
655: printf ("\tCOPY_CARRY;\n");
656: }
657:
658: typedef enum
659: {
660: flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_zn,
661: flag_av, flag_sv
662: }
663: flagtypes;
664:
1.1.1.12 root 665: static void genflags_normal (flagtypes type, wordsizes size, const char *value,
666: const char *src, const char *dst)
1.1 root 667: {
668: char vstr[100], sstr[100], dstr[100];
669: char usstr[100], udstr[100];
670: char unsstr[100], undstr[100];
671:
672: switch (size) {
673: case sz_byte:
674: strcpy (vstr, "((uae_s8)(");
675: strcpy (usstr, "((uae_u8)(");
676: break;
677: case sz_word:
678: strcpy (vstr, "((uae_s16)(");
679: strcpy (usstr, "((uae_u16)(");
680: break;
681: case sz_long:
682: strcpy (vstr, "((uae_s32)(");
683: strcpy (usstr, "((uae_u32)(");
684: break;
685: default:
686: abort ();
687: }
688: strcpy (unsstr, usstr);
689:
690: strcpy (sstr, vstr);
691: strcpy (dstr, vstr);
692: strcat (vstr, value);
693: strcat (vstr, "))");
694: strcat (dstr, dst);
695: strcat (dstr, "))");
696: strcat (sstr, src);
697: strcat (sstr, "))");
698:
699: strcpy (udstr, usstr);
700: strcat (udstr, dst);
701: strcat (udstr, "))");
702: strcat (usstr, src);
703: strcat (usstr, "))");
704:
705: strcpy (undstr, unsstr);
706: strcat (unsstr, "-");
707: strcat (undstr, "~");
708: strcat (undstr, dst);
709: strcat (undstr, "))");
710: strcat (unsstr, src);
711: strcat (unsstr, "))");
712:
713: switch (type) {
714: case flag_logical_noclobber:
715: case flag_logical:
716: case flag_zn:
717: case flag_av:
718: case flag_sv:
719: case flag_addx:
720: case flag_subx:
721: break;
722:
723: case flag_add:
724: start_brace ();
725: printf ("uae_u32 %s = %s + %s;\n", value, dstr, sstr);
726: break;
727: case flag_sub:
728: case flag_cmp:
729: start_brace ();
730: printf ("uae_u32 %s = %s - %s;\n", value, dstr, sstr);
731: break;
732: }
733:
734: switch (type) {
735: case flag_logical_noclobber:
736: case flag_logical:
737: case flag_zn:
738: break;
739:
740: case flag_add:
741: case flag_sub:
742: case flag_addx:
743: case flag_subx:
744: case flag_cmp:
745: case flag_av:
746: case flag_sv:
747: start_brace ();
748: printf ("\t" BOOL_TYPE " flgs = %s < 0;\n", sstr);
749: printf ("\t" BOOL_TYPE " flgo = %s < 0;\n", dstr);
750: printf ("\t" BOOL_TYPE " flgn = %s < 0;\n", vstr);
751: break;
752: }
753:
754: switch (type) {
755: case flag_logical:
756: printf ("\tCLEAR_CZNV;\n");
757: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
758: printf ("\tSET_NFLG (%s < 0);\n", vstr);
759: break;
760: case flag_logical_noclobber:
761: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
762: printf ("\tSET_NFLG (%s < 0);\n", vstr);
763: break;
764: case flag_av:
765: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
766: break;
767: case flag_sv:
768: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
769: break;
770: case flag_zn:
771: printf ("\tSET_ZFLG (GET_ZFLG & (%s == 0));\n", vstr);
772: printf ("\tSET_NFLG (%s < 0);\n", vstr);
773: break;
774: case flag_add:
775: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
776: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
777: printf ("\tSET_CFLG (%s < %s);\n", undstr, usstr);
778: duplicate_carry ();
779: printf ("\tSET_NFLG (flgn != 0);\n");
780: break;
781: case flag_sub:
782: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
783: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
784: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
785: duplicate_carry ();
786: printf ("\tSET_NFLG (flgn != 0);\n");
787: break;
788: case flag_addx:
789: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n"); /* minterm SON: 0x42 */
790: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));\n"); /* minterm SON: 0xD4 */
791: duplicate_carry ();
792: break;
793: case flag_subx:
794: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));\n"); /* minterm SON: 0x24 */
795: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));\n"); /* minterm SON: 0xB2 */
796: duplicate_carry ();
797: break;
798: case flag_cmp:
799: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
800: printf ("\tSET_VFLG ((flgs != flgo) && (flgn != flgo));\n");
801: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
802: printf ("\tSET_NFLG (flgn != 0);\n");
803: break;
804: }
805: }
806:
1.1.1.12 root 807: static void genflags (flagtypes type, wordsizes size, const char *value,
808: const char *src, const char *dst)
1.1 root 809: {
810: /* Temporarily deleted 68k/ARM flag optimizations. I'd prefer to have
811: them in the appropriate m68k.h files and use just one copy of this
812: code here. The API can be changed if necessary. */
813: #ifdef OPTIMIZED_FLAGS
814: switch (type) {
815: case flag_add:
816: case flag_sub:
817: start_brace ();
818: printf ("\tuae_u32 %s;\n", value);
819: break;
820:
821: default:
822: break;
823: }
824:
825: /* At least some of those casts are fairly important! */
826: switch (type) {
827: case flag_logical_noclobber:
828: printf ("\t{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
829: if (strcmp (value, "0") == 0) {
830: printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n");
831: } else {
832: switch (size) {
833: case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
834: case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
835: case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
836: }
837: printf ("\tIOR_CZNV (oldcznv);\n");
838: }
839: printf ("\t}\n");
840: return;
841: case flag_logical:
842: if (strcmp (value, "0") == 0) {
843: printf ("\tSET_CZNV (FLAGVAL_Z);\n");
844: } else {
845: switch (size) {
846: case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
847: case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
848: case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
849: }
850: }
851: return;
852:
853: case flag_add:
854: switch (size) {
855: case sz_byte: printf ("\toptflag_addb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
856: case sz_word: printf ("\toptflag_addw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
857: case sz_long: printf ("\toptflag_addl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
858: }
859: return;
860:
861: case flag_sub:
862: switch (size) {
863: case sz_byte: printf ("\toptflag_subb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
864: case sz_word: printf ("\toptflag_subw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
865: case sz_long: printf ("\toptflag_subl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
866: }
867: return;
868:
869: case flag_cmp:
870: switch (size) {
871: case sz_byte: printf ("\toptflag_cmpb ((uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
872: case sz_word: printf ("\toptflag_cmpw ((uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
873: case sz_long: printf ("\toptflag_cmpl ((uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
874: }
875: return;
876:
877: default:
878: break;
879: }
880: #endif
881:
882: genflags_normal (type, size, value, src, dst);
883: }
884:
885: static void force_range_for_rox (const char *var, wordsizes size)
886: {
887: /* Could do a modulo operation here... which one is faster? */
888: switch (size) {
889: case sz_long:
890: printf ("\tif (%s >= 33) %s -= 33;\n", var, var);
891: break;
892: case sz_word:
893: printf ("\tif (%s >= 34) %s -= 34;\n", var, var);
894: printf ("\tif (%s >= 17) %s -= 17;\n", var, var);
895: break;
896: case sz_byte:
897: printf ("\tif (%s >= 36) %s -= 36;\n", var, var);
898: printf ("\tif (%s >= 18) %s -= 18;\n", var, var);
899: printf ("\tif (%s >= 9) %s -= 9;\n", var, var);
900: break;
901: }
902: }
903:
904: static const char *cmask (wordsizes size)
905: {
906: switch (size) {
907: case sz_byte: return "0x80";
908: case sz_word: return "0x8000";
909: case sz_long: return "0x80000000";
910: default: abort ();
911: }
912: }
913:
914: static int source_is_imm1_8 (struct instr *i)
915: {
916: return i->stype == 3;
917: }
918:
1.1.1.2 root 919:
920:
1.1 root 921: static void gen_opcode (unsigned long int opcode)
922: {
1.1.1.2 root 923: #if 0
924: char *amodenames[] = { "Dreg", "Areg", "Aind", "Aipi", "Apdi", "Ad16", "Ad8r",
925: "absw", "absl", "PC16", "PC8r", "imm", "imm0", "imm1", "imm2", "immi", "am_unknown", "am_illg"};
926: #endif
927:
1.1 root 928: struct instr *curi = table68k + opcode;
929: insn_n_cycles = 4;
930:
1.1.1.8 root 931: /* Store the family of the instruction (used to check for pairing on ST)
932: * and leave some space for patching in the current cycles later */
933: printf ("\tOpcodeFamily = %d; CurrentInstrCycles = \n", curi->mnemo);
934: nCurInstrCycPos = ftell(stdout) - 5;
935:
1.1 root 936: start_brace ();
937: m68k_pc_offset = 2;
1.1.1.2 root 938:
1.1 root 939: switch (curi->plev) {
940: case 0: /* not privileged */
941: break;
942: case 1: /* unprivileged only on 68000 */
943: if (cpu_level == 0)
944: break;
945: if (next_cpu_level < 0)
946: next_cpu_level = 0;
947:
948: /* fall through */
949: case 2: /* priviledged */
1.1.1.12 root 950: printf ("if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 951: need_endlabel = 1;
952: start_brace ();
953: break;
954: case 3: /* privileged if size == word */
955: if (curi->size == sz_byte)
956: break;
1.1.1.12 root 957: printf ("if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 958: need_endlabel = 1;
959: start_brace ();
960: break;
961: }
1.1.1.2 root 962:
963: /* Build the opcodes: */
1.1 root 964: switch (curi->mnemo) {
965: case i_OR:
966: case i_AND:
967: case i_EOR:
1.1.1.2 root 968: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
969: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
970: printf ("\tsrc %c= dst;\n", curi->mnemo == i_OR ? '|' : curi->mnemo == i_AND ? '&' : '^');
971: genflags (flag_logical, curi->size, "src", "", "");
972: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
973: if(curi->size==sz_long && curi->dmode==Dreg)
974: {
975: insn_n_cycles += 2;
976: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
977: insn_n_cycles += 2;
978: }
979: #if 0
980: /* Output the CPU cycles: */
981: fprintf(stderr,"MOVE, size %i: ",curi->size);
982: fprintf(stderr," %s ->",amodenames[curi->smode]);
983: fprintf(stderr," %s ",amodenames[curi->dmode]);
984: fprintf(stderr," Cycles: %i\n",insn_n_cycles);
985: #endif
986: break;
1.1 root 987: case i_ORSR:
988: case i_EORSR:
1.1.1.2 root 989: printf ("\tMakeSR();\n");
990: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
991: if (curi->size == sz_byte) {
992: printf ("\tsrc &= 0xFF;\n");
993: }
994: printf ("\tregs.sr %c= src;\n", curi->mnemo == i_EORSR ? '^' : '|');
995: printf ("\tMakeFromSR();\n");
996: insn_n_cycles = 20;
997: break;
1.1 root 998: case i_ANDSR:
1.1.1.2 root 999: printf ("\tMakeSR();\n");
1000: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1001: if (curi->size == sz_byte) {
1002: printf ("\tsrc |= 0xFF00;\n");
1003: }
1004: printf ("\tregs.sr &= src;\n");
1005: printf ("\tMakeFromSR();\n");
1006: insn_n_cycles = 20;
1007: break;
1.1 root 1008: case i_SUB:
1009: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1010: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1011: start_brace ();
1012: genflags (flag_sub, curi->size, "newv", "src", "dst");
1013: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1014: if(curi->size==sz_long && curi->dmode==Dreg)
1015: {
1016: insn_n_cycles += 2;
1017: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
1018: insn_n_cycles += 2;
1019: }
1.1 root 1020: break;
1021: case i_SUBA:
1022: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1023: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1024: start_brace ();
1025: printf ("\tuae_u32 newv = dst - src;\n");
1026: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.2 root 1027: if(curi->size==sz_long && curi->smode!=Dreg && curi->smode!=Areg && !(curi->smode>=imm && curi->smode<=immi))
1028: insn_n_cycles += 2;
1029: else
1030: insn_n_cycles += 4;
1.1 root 1031: break;
1032: case i_SUBX:
1033: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1034: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1035: start_brace ();
1036: printf ("\tuae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);\n");
1037: genflags (flag_subx, curi->size, "newv", "src", "dst");
1038: genflags (flag_zn, curi->size, "newv", "", "");
1039: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1040: if(curi->smode==Dreg && curi->size==sz_long)
1041: insn_n_cycles=8;
1042: if(curi->smode==Apdi)
1043: {
1044: if(curi->size==sz_long)
1045: insn_n_cycles=30;
1046: else
1047: insn_n_cycles=18;
1048: }
1.1 root 1049: break;
1050: case i_SBCD:
1051: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1052: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1053: start_brace ();
1054: printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
1055: printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
1.1.1.4 root 1056: printf ("\tuae_u16 newv, tmp_newv;\n");
1057: printf ("\tint bcd = 0;\n");
1058: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
1059: printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
1060: printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
1061: printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);\n");
1.1 root 1062: duplicate_carry ();
1063: genflags (flag_zn, curi->size, "newv", "", "");
1.1.1.4 root 1064: printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
1.1 root 1065: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.4 root 1066: if(curi->smode==Dreg) insn_n_cycles=6;
1067: if(curi->smode==Apdi) insn_n_cycles=18;
1.1 root 1068: break;
1069: case i_ADD:
1070: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1071: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1072: start_brace ();
1.1.1.8 root 1073: printf("\trefill_prefetch (m68k_getpc(), 2);\n"); // FIXME [NP] For Transbeauce 2 demo, need better prefetch emulation
1.1 root 1074: genflags (flag_add, curi->size, "newv", "src", "dst");
1075: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1076: if(curi->size==sz_long && curi->dmode==Dreg)
1077: {
1078: insn_n_cycles += 2;
1079: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
1080: insn_n_cycles += 2;
1081: }
1.1 root 1082: break;
1083: case i_ADDA:
1084: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1085: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1086: start_brace ();
1087: printf ("\tuae_u32 newv = dst + src;\n");
1088: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.2 root 1089: if(curi->size==sz_long && curi->smode!=Dreg && curi->smode!=Areg && !(curi->smode>=imm && curi->smode<=immi))
1090: insn_n_cycles += 2;
1091: else
1092: insn_n_cycles += 4;
1.1 root 1093: break;
1094: case i_ADDX:
1095: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1096: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1097: start_brace ();
1098: printf ("\tuae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);\n");
1099: genflags (flag_addx, curi->size, "newv", "src", "dst");
1100: genflags (flag_zn, curi->size, "newv", "", "");
1101: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1102: if(curi->smode==Dreg && curi->size==sz_long)
1103: insn_n_cycles=8;
1104: if(curi->smode==Apdi)
1105: {
1106: if(curi->size==sz_long)
1107: insn_n_cycles=30;
1108: else
1109: insn_n_cycles=18;
1110: }
1.1 root 1111: break;
1112: case i_ABCD:
1113: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1114: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1115: start_brace ();
1116: printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);\n");
1117: printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
1.1.1.4 root 1118: printf ("\tuae_u16 newv, tmp_newv;\n");
1.1 root 1119: printf ("\tint cflg;\n");
1.1.1.4 root 1120: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;");
1121: printf ("\tif (newv_lo > 9) { newv += 6; }\n");
1122: printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
1123: printf ("\tif (cflg) newv += 0x60;\n");
1.1 root 1124: printf ("\tSET_CFLG (cflg);\n");
1125: duplicate_carry ();
1126: genflags (flag_zn, curi->size, "newv", "", "");
1.1.1.4 root 1127: printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
1.1 root 1128: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.4 root 1129: if(curi->smode==Dreg) insn_n_cycles=6;
1130: if(curi->smode==Apdi) insn_n_cycles=18;
1.1 root 1131: break;
1132: case i_NEG:
1133: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1134: start_brace ();
1135: genflags (flag_sub, curi->size, "dst", "src", "0");
1136: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1137: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1138: break;
1139: case i_NEGX:
1140: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1141: start_brace ();
1142: printf ("\tuae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);\n");
1143: genflags (flag_subx, curi->size, "newv", "src", "0");
1144: genflags (flag_zn, curi->size, "newv", "", "");
1145: genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1146: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1147: break;
1148: case i_NBCD:
1149: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1150: start_brace ();
1151: printf ("\tuae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
1152: printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
1153: printf ("\tuae_u16 newv;\n");
1154: printf ("\tint cflg;\n");
1.1.1.4 root 1155: printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
1156: printf ("\tnewv = newv_hi + newv_lo;");
1157: printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
1158: printf ("\tif (cflg) newv -= 0x60;\n");
1.1 root 1159: printf ("\tSET_CFLG (cflg);\n");
1160: duplicate_carry();
1161: genflags (flag_zn, curi->size, "newv", "", "");
1162: genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1.1.1.4 root 1163: if(curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1164: break;
1165: case i_CLR:
1166: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1.1.1.8 root 1167:
1168: /* [NP] CLR does a read before the write only on 68000 */
1169: /* but there's no cycle penalty for doing the read */
1170: if ( curi->smode != Dreg ) // only if destination is memory
1171: {
1172: if (curi->size==sz_byte)
1173: printf ("\tuae_s8 src = get_byte(srca);\n");
1174: else if (curi->size==sz_word)
1175: printf ("\tuae_s16 src = get_word(srca);\n");
1176: else if (curi->size==sz_long)
1177: printf ("\tuae_s32 src = get_long(srca);\n");
1178: }
1179:
1.1 root 1180: genflags (flag_logical, curi->size, "0", "", "");
1181: genastore ("0", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1182: if(curi->size==sz_long)
1.1.1.3 root 1183: {
1.1.1.2 root 1184: if(curi->smode==Dreg)
1185: insn_n_cycles += 2;
1186: else
1187: insn_n_cycles += 4;
1.1.1.3 root 1188: }
1.1.1.2 root 1189: if(curi->smode!=Dreg)
1190: insn_n_cycles += 4;
1.1 root 1191: break;
1192: case i_NOT:
1193: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1194: start_brace ();
1195: printf ("\tuae_u32 dst = ~src;\n");
1196: genflags (flag_logical, curi->size, "dst", "", "");
1197: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1198: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1199: break;
1200: case i_TST:
1201: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1202: genflags (flag_logical, curi->size, "src", "", "");
1203: break;
1204: case i_BTST:
1205: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1206: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1207: if (curi->size == sz_byte)
1208: printf ("\tsrc &= 7;\n");
1209: else
1210: printf ("\tsrc &= 31;\n");
1211: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1.1.1.2 root 1212: if(curi->dmode==Dreg) insn_n_cycles += 2;
1.1 root 1213: break;
1214: case i_BCHG:
1215: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1216: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1217: if (curi->size == sz_byte)
1218: printf ("\tsrc &= 7;\n");
1219: else
1220: printf ("\tsrc &= 31;\n");
1221: printf ("\tdst ^= (1 << src);\n");
1222: printf ("\tSET_ZFLG (((uae_u32)dst & (1 << src)) >> src);\n");
1223: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1224: if(curi->dmode==Dreg) insn_n_cycles += 4;
1.1 root 1225: break;
1226: case i_BCLR:
1227: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1228: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1229: if (curi->size == sz_byte)
1230: printf ("\tsrc &= 7;\n");
1231: else
1232: printf ("\tsrc &= 31;\n");
1233: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1234: printf ("\tdst &= ~(1 << src);\n");
1235: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1236: if(curi->dmode==Dreg) insn_n_cycles += 6;
1.1.1.8 root 1237: /* [NP] BCLR #n,Dx takes 12 cycles instead of 14 if n<16 */
1238: if((curi->smode==imm1) && (curi->dmode==Dreg))
1239: printf ("\tif ( src < 16 ) { m68k_incpc(4); return 12; }\n");
1240: /* [NP] BCLR Dy,Dx takes 8 cycles instead of 10 if Dy<16 */
1241: if((curi->smode==Dreg) && (curi->dmode==Dreg))
1242: printf ("\tif ( src < 16 ) { m68k_incpc(2); return 8; }\n");
1.1 root 1243: break;
1244: case i_BSET:
1245: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1246: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1247: if (curi->size == sz_byte)
1248: printf ("\tsrc &= 7;\n");
1249: else
1250: printf ("\tsrc &= 31;\n");
1251: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1252: printf ("\tdst |= (1 << src);\n");
1253: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1254: if(curi->dmode==Dreg) insn_n_cycles += 4;
1.1 root 1255: break;
1256: case i_CMPM:
1257: case i_CMP:
1258: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1259: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1260: start_brace ();
1261: genflags (flag_cmp, curi->size, "newv", "src", "dst");
1.1.1.2 root 1262: if(curi->size==sz_long && curi->dmode==Dreg)
1263: insn_n_cycles += 2;
1.1 root 1264: break;
1265: case i_CMPA:
1266: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1267: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1268: start_brace ();
1269: genflags (flag_cmp, sz_long, "newv", "src", "dst");
1.1.1.2 root 1270: insn_n_cycles += 2;
1.1 root 1271: break;
1272: /* The next two are coded a little unconventional, but they are doing
1273: * weird things... */
1274: case i_MVPRM:
1275: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1276:
1277: printf ("\tuaecptr memp = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword ());
1278: if (curi->size == sz_word) {
1279: printf ("\tput_byte(memp, src >> 8); put_byte(memp + 2, src);\n");
1280: } else {
1281: printf ("\tput_byte(memp, src >> 24); put_byte(memp + 2, src >> 16);\n");
1282: printf ("\tput_byte(memp + 4, src >> 8); put_byte(memp + 6, src);\n");
1283: }
1.1.1.2 root 1284: if(curi->size==sz_long) insn_n_cycles=24; else insn_n_cycles=16;
1.1 root 1285: break;
1286: case i_MVPMR:
1287: printf ("\tuaecptr memp = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword ());
1288: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1289: if (curi->size == sz_word) {
1290: printf ("\tuae_u16 val = (get_byte(memp) << 8) + get_byte(memp + 2);\n");
1291: } else {
1292: printf ("\tuae_u32 val = (get_byte(memp) << 24) + (get_byte(memp + 2) << 16)\n");
1293: printf (" + (get_byte(memp + 4) << 8) + get_byte(memp + 6);\n");
1294: }
1295: genastore ("val", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1296: if(curi->size==sz_long) insn_n_cycles=24; else insn_n_cycles=16;
1.1 root 1297: break;
1298: case i_MOVE:
1299: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1300: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1.1.1.8 root 1301:
1302: /* [NP] genamode counts 2 cycles if dest is -(An), this is wrong. */
1303: /* For move dest (An), (An)+ and -(An) take the same time */
1304: /* (for other instr, dest -(An) really takes 2 cycles more) */
1305: if ( curi->dmode == Apdi )
1306: insn_n_cycles -= 2; /* correct the wrong cycle count for -(An) */
1307:
1.1 root 1308: genflags (flag_logical, curi->size, "src", "", "");
1309: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
1310: break;
1311: case i_MOVEA:
1312: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1313: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1314: if (curi->size == sz_word) {
1315: printf ("\tuae_u32 val = (uae_s32)(uae_s16)src;\n");
1316: } else {
1317: printf ("\tuae_u32 val = src;\n");
1318: }
1319: genastore ("val", curi->dmode, "dstreg", sz_long, "dst");
1320: break;
1.1.1.2 root 1321: case i_MVSR2: /* Move from SR */
1.1 root 1322: genamode (curi->smode, "srcreg", sz_word, "src", 2, 0);
1323: printf ("\tMakeSR();\n");
1324: if (curi->size == sz_byte)
1325: genastore ("regs.sr & 0xff", curi->smode, "srcreg", sz_word, "src");
1326: else
1327: genastore ("regs.sr", curi->smode, "srcreg", sz_word, "src");
1.1.1.2 root 1328: if (curi->smode==Dreg) insn_n_cycles += 2; else insn_n_cycles += 4;
1.1 root 1329: break;
1.1.1.2 root 1330: case i_MV2SR: /* Move to SR */
1.1 root 1331: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1332: if (curi->size == sz_byte)
1333: printf ("\tMakeSR();\n\tregs.sr &= 0xFF00;\n\tregs.sr |= src & 0xFF;\n");
1334: else {
1335: printf ("\tregs.sr = src;\n");
1336: }
1337: printf ("\tMakeFromSR();\n");
1.1.1.2 root 1338: insn_n_cycles += 8;
1.1 root 1339: break;
1340: case i_SWAP:
1341: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1342: start_brace ();
1343: printf ("\tuae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);\n");
1344: genflags (flag_logical, sz_long, "dst", "", "");
1345: genastore ("dst", curi->smode, "srcreg", sz_long, "src");
1346: break;
1347: case i_EXG:
1348: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1349: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1350: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1351: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1352: insn_n_cycles = 6;
1.1 root 1353: break;
1354: case i_EXT:
1355: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1356: start_brace ();
1357: switch (curi->size) {
1358: case sz_byte: printf ("\tuae_u32 dst = (uae_s32)(uae_s8)src;\n"); break;
1359: case sz_word: printf ("\tuae_u16 dst = (uae_s16)(uae_s8)src;\n"); break;
1360: case sz_long: printf ("\tuae_u32 dst = (uae_s32)(uae_s16)src;\n"); break;
1361: default: abort ();
1362: }
1363: genflags (flag_logical,
1364: curi->size == sz_word ? sz_word : sz_long, "dst", "", "");
1365: genastore ("dst", curi->smode, "srcreg",
1366: curi->size == sz_word ? sz_word : sz_long, "src");
1367: break;
1368: case i_MVMEL:
1369: genmovemel (opcode);
1370: break;
1371: case i_MVMLE:
1372: genmovemle (opcode);
1373: break;
1374: case i_TRAP:
1375: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1376: sync_m68k_pc ();
1.1.1.12 root 1377: printf ("\tException(src+32,0,M68000_EXC_SRC_CPU);\n");
1.1 root 1378: m68k_pc_offset = 0;
1379: break;
1380: case i_MVR2USP:
1381: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1382: printf ("\tregs.usp = src;\n");
1383: break;
1384: case i_MVUSP2R:
1385: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1386: genastore ("regs.usp", curi->smode, "srcreg", curi->size, "src");
1387: break;
1388: case i_RESET:
1389: printf ("\tcustomreset();\n");
1.1.1.2 root 1390: insn_n_cycles = 132; /* I am not so sure about this!? - Thothy */
1.1 root 1391: break;
1392: case i_NOP:
1393: break;
1394: case i_STOP:
1395: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1396: printf ("\tregs.sr = src;\n");
1397: printf ("\tMakeFromSR();\n");
1398: printf ("\tm68k_setstopped(1);\n");
1.1.1.2 root 1399: insn_n_cycles = 4;
1.1 root 1400: break;
1401: case i_RTE:
1402: if (cpu_level == 0) {
1403: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1404: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1405: printf ("\tregs.sr = sr; m68k_setpc_rte(pc);\n");
1406: fill_prefetch_0 ();
1407: printf ("\tMakeFromSR();\n");
1408: } else {
1409: int old_brace_level = n_braces;
1410: if (next_cpu_level < 0)
1411: next_cpu_level = 0;
1412: printf ("\tuae_u16 newsr; uae_u32 newpc; for (;;) {\n");
1413: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1414: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1415: genamode (Aipi, "7", sz_word, "format", 1, 0);
1416: printf ("\tnewsr = sr; newpc = pc;\n");
1417: printf ("\tif ((format & 0xF000) == 0x0000) { break; }\n");
1418: printf ("\telse if ((format & 0xF000) == 0x1000) { ; }\n");
1419: printf ("\telse if ((format & 0xF000) == 0x2000) { m68k_areg(regs, 7) += 4; break; }\n");
1420: printf ("\telse if ((format & 0xF000) == 0x8000) { m68k_areg(regs, 7) += 50; break; }\n");
1421: printf ("\telse if ((format & 0xF000) == 0x9000) { m68k_areg(regs, 7) += 12; break; }\n");
1422: printf ("\telse if ((format & 0xF000) == 0xa000) { m68k_areg(regs, 7) += 24; break; }\n");
1423: printf ("\telse if ((format & 0xF000) == 0xb000) { m68k_areg(regs, 7) += 84; break; }\n");
1.1.1.12 root 1424: printf ("\telse { Exception(14,0,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 1425: printf ("\tregs.sr = newsr; MakeFromSR();\n}\n");
1426: pop_braces (old_brace_level);
1427: printf ("\tregs.sr = newsr; MakeFromSR();\n");
1428: printf ("\tm68k_setpc_rte(newpc);\n");
1429: fill_prefetch_0 ();
1430: need_endlabel = 1;
1431: }
1432: /* PC is set and prefetch filled. */
1433: m68k_pc_offset = 0;
1.1.1.2 root 1434: insn_n_cycles = 20;
1.1 root 1435: break;
1436: case i_RTD:
1437: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1438: genamode (curi->smode, "srcreg", curi->size, "offs", 1, 0);
1439: printf ("\tm68k_areg(regs, 7) += offs;\n");
1440: printf ("\tm68k_setpc_rte(pc);\n");
1441: fill_prefetch_0 ();
1442: /* PC is set and prefetch filled. */
1443: m68k_pc_offset = 0;
1444: break;
1445: case i_LINK:
1446: genamode (Apdi, "7", sz_long, "old", 2, 0);
1447: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1448: genastore ("src", Apdi, "7", sz_long, "old");
1449: genastore ("m68k_areg(regs, 7)", curi->smode, "srcreg", sz_long, "src");
1450: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0);
1451: printf ("\tm68k_areg(regs, 7) += offs;\n");
1452: break;
1453: case i_UNLK:
1454: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1455: printf ("\tm68k_areg(regs, 7) = src;\n");
1456: genamode (Aipi, "7", sz_long, "old", 1, 0);
1457: genastore ("old", curi->smode, "srcreg", curi->size, "src");
1458: break;
1459: case i_RTS:
1460: printf ("\tm68k_do_rts();\n");
1461: fill_prefetch_0 ();
1462: m68k_pc_offset = 0;
1.1.1.2 root 1463: insn_n_cycles = 16;
1.1 root 1464: break;
1465: case i_TRAPV:
1466: sync_m68k_pc ();
1.1.1.12 root 1467: printf ("\tif (GET_VFLG) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 1468: need_endlabel = 1;
1469: break;
1470: case i_RTR:
1471: printf ("\tMakeSR();\n");
1472: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1473: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1474: printf ("\tregs.sr &= 0xFF00; sr &= 0xFF;\n");
1475: printf ("\tregs.sr |= sr; m68k_setpc(pc);\n");
1476: fill_prefetch_0 ();
1477: printf ("\tMakeFromSR();\n");
1478: m68k_pc_offset = 0;
1.1.1.2 root 1479: insn_n_cycles = 20;
1.1 root 1480: break;
1481: case i_JSR:
1482: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1.1.1.13! root 1483: printf ("\tuaecptr oldpc = m68k_getpc () + %d;\n", m68k_pc_offset);
! 1484: if (using_exception_3) {
! 1485: printf ("\tif (srca & 1) {\n");
! 1486: printf ("\t\tlast_addr_for_exception_3 = oldpc;\n");
! 1487: printf ("\t\tlast_fault_for_exception_3 = srca;\n");
! 1488: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
! 1489: printf ("\t}\n");
! 1490: need_endlabel = 1;
! 1491: }
1.1 root 1492: printf ("\tm68k_do_jsr(m68k_getpc() + %d, srca);\n", m68k_pc_offset);
1493: fill_prefetch_0 ();
1494: m68k_pc_offset = 0;
1.1.1.2 root 1495: switch(curi->smode)
1496: {
1497: case Aind: insn_n_cycles=16; break;
1498: case Ad16: insn_n_cycles=18; break;
1499: case Ad8r: insn_n_cycles=22; break;
1500: case absw: insn_n_cycles=18; break;
1501: case absl: insn_n_cycles=20; break;
1502: case PC16: insn_n_cycles=18; break;
1503: case PC8r: insn_n_cycles=22; break;
1504: }
1.1 root 1505: break;
1506: case i_JMP:
1507: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1.1.1.13! root 1508: if (using_exception_3) {
! 1509: printf ("\tif (srca & 1) {\n");
! 1510: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 6;\n");
! 1511: printf ("\t\tlast_fault_for_exception_3 = srca;\n");
! 1512: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
! 1513: printf ("\t}\n");
! 1514: need_endlabel = 1;
! 1515: }
1.1 root 1516: printf ("\tm68k_setpc(srca);\n");
1517: fill_prefetch_0 ();
1518: m68k_pc_offset = 0;
1.1.1.2 root 1519: switch(curi->smode)
1520: {
1521: case Aind: insn_n_cycles=8; break;
1522: case Ad16: insn_n_cycles=10; break;
1523: case Ad8r: insn_n_cycles=14; break;
1524: case absw: insn_n_cycles=10; break;
1525: case absl: insn_n_cycles=12; break;
1526: case PC16: insn_n_cycles=10; break;
1527: case PC8r: insn_n_cycles=14; break;
1528: }
1.1 root 1529: break;
1530: case i_BSR:
1531: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1532: printf ("\tuae_s32 s = (uae_s32)src + 2;\n");
1533: if (using_exception_3) {
1534: printf ("\tif (src & 1) {\n");
1.1.1.13! root 1535: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n"); // [NP] FIXME should be +4, not +2 (same as DBcc) ?
1.1 root 1536: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + s;\n");
1.1.1.12 root 1537: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1538: printf ("\t}\n");
1539: need_endlabel = 1;
1540: }
1541: printf ("\tm68k_do_bsr(m68k_getpc() + %d, s);\n", m68k_pc_offset);
1542: fill_prefetch_0 ();
1543: m68k_pc_offset = 0;
1.1.1.2 root 1544: insn_n_cycles = 18;
1.1 root 1545: break;
1546: case i_Bcc:
1547: if (curi->size == sz_long) {
1548: if (cpu_level < 2) {
1549: printf ("\tm68k_incpc(2);\n");
1550: printf ("\tif (!cctrue(%d)) goto %s;\n", curi->cc, endlabelstr);
1551: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n");
1552: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + 1;\n");
1.1.1.12 root 1553: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1554: need_endlabel = 1;
1555: } else {
1556: if (next_cpu_level < 1)
1557: next_cpu_level = 1;
1558: }
1559: }
1560: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1561: printf ("\tif (!cctrue(%d)) goto didnt_jump;\n", curi->cc);
1562: if (using_exception_3) {
1563: printf ("\tif (src & 1) {\n");
1.1.1.8 root 1564: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n"); // [NP] FIXME should be +4, not +2 (same as DBcc) ?
1.1 root 1565: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;\n");
1.1.1.12 root 1566: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1567: printf ("\t}\n");
1568: need_endlabel = 1;
1569: }
1570: printf ("\tm68k_incpc ((uae_s32)src + 2);\n");
1571: fill_prefetch_0 ();
1.1.1.2 root 1572: printf ("\treturn 10;\n");
1.1 root 1573: printf ("didnt_jump:;\n");
1574: need_endlabel = 1;
1.1.1.2 root 1575: insn_n_cycles = (curi->size == sz_byte) ? 8 : 12;
1.1 root 1576: break;
1577: case i_LEA:
1578: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1579: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1580: genastore ("srca", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.7 root 1581: /* Set correct cycles: According to the M68K User Manual, LEA takes 12
1582: * cycles in Ad8r and PC8r mode, but it takes 14 (or 16) cycles on a real ST: */
1583: if (curi->smode == Ad8r || curi->smode == PC8r)
1584: insn_n_cycles = 14;
1.1 root 1585: break;
1586: case i_PEA:
1587: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1588: genamode (Apdi, "7", sz_long, "dst", 2, 0);
1589: genastore ("srca", Apdi, "7", sz_long, "dst");
1.1.1.7 root 1590: /* Set correct cycles: */
1.1.1.2 root 1591: switch(curi->smode)
1592: {
1593: case Aind: insn_n_cycles=12; break;
1594: case Ad16: insn_n_cycles=16; break;
1.1.1.7 root 1595: /* Note: according to the M68K User Manual, PEA takes 20 cycles for
1596: * the Ad8r mode, but on a real ST, it takes 22 (or 24) cycles! */
1597: case Ad8r: insn_n_cycles=22; break;
1.1.1.2 root 1598: case absw: insn_n_cycles=16; break;
1599: case absl: insn_n_cycles=20; break;
1600: case PC16: insn_n_cycles=16; break;
1.1.1.7 root 1601: /* Note: PEA with PC8r takes 20 cycles according to the User Manual,
1602: * but it takes 22 (or 24) cycles on a real ST: */
1603: case PC8r: insn_n_cycles=22; break;
1.1.1.2 root 1604: }
1.1 root 1605: break;
1606: case i_DBcc:
1607: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1608: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0);
1609:
1.1.1.2 root 1610: printf ("\tif (!cctrue(%d)) {\n\t", curi->cc);
1.1 root 1611: genastore ("(src-1)", curi->smode, "srcreg", curi->size, "src");
1612:
1613: printf ("\t\tif (src) {\n");
1614: if (using_exception_3) {
1615: printf ("\t\t\tif (offs & 1) {\n");
1.1.1.8 root 1616: printf ("\t\t\tlast_addr_for_exception_3 = m68k_getpc() + 2 + 2;\n"); // [NP] last_addr is pc+4, not pc+2
1.1 root 1617: printf ("\t\t\tlast_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;\n");
1.1.1.12 root 1618: printf ("\t\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1619: printf ("\t\t}\n");
1620: need_endlabel = 1;
1621: }
1622: printf ("\t\t\tm68k_incpc((uae_s32)offs + 2);\n");
1623: fill_prefetch_0 ();
1.1.1.2 root 1624: printf ("\t\t\treturn 10;\n");
1625: printf ("\t\t} else {\n\t\t\t");
1626: {
1627: int tmp_offset = m68k_pc_offset;
1628: sync_m68k_pc(); /* not so nice to call it here... */
1629: m68k_pc_offset = tmp_offset;
1630: }
1631: printf ("\t\t\treturn 14;\n");
1632: printf ("\t\t}\n");
1.1 root 1633: printf ("\t}\n");
1634: insn_n_cycles = 12;
1635: need_endlabel = 1;
1636: break;
1637: case i_Scc:
1638: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1639: start_brace ();
1640: printf ("\tint val = cctrue(%d) ? 0xff : 0;\n", curi->cc);
1641: genastore ("val", curi->smode, "srcreg", curi->size, "src");
1.1.1.8 root 1642: if (curi->smode!=Dreg) insn_n_cycles += 4;
1643: else
1644: { /* [NP] if result is TRUE, we return 6 instead of 4 */
1645: printf ("\tif (val) { m68k_incpc(2) ; return 4+2; }\n");
1646: }
1.1 root 1647: break;
1648: case i_DIVU:
1649: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1650: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1651: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1652: sync_m68k_pc ();
1653: /* Clear V flag when dividing by zero - Alcatraz Odyssey demo depends
1654: * on this (actually, it's doing a DIVS). */
1.1.1.12 root 1655: printf ("\tif (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto %s; } else {\n", endlabelstr);
1.1 root 1656: printf ("\tuae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
1657: printf ("\tuae_u32 rem = (uae_u32)dst %% (uae_u32)(uae_u16)src;\n");
1658: /* The N flag appears to be set each time there is an overflow.
1659: * Weird. */
1660: printf ("\tif (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
1661: genflags (flag_logical, sz_word, "newv", "", "");
1662: printf ("\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
1663: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1664: printf ("\t}\n");
1665: printf ("\t}\n");
1.1.1.8 root 1666: // insn_n_cycles += 136;
1667: printf ("\tretcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);\n");
1668: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 1669: need_endlabel = 1;
1670: break;
1671: case i_DIVS:
1672: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1673: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1674: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1675: sync_m68k_pc ();
1.1.1.12 root 1676: printf ("\tif (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto %s; } else {\n", endlabelstr);
1.1 root 1677: printf ("\tuae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
1678: printf ("\tuae_u16 rem = (uae_s32)dst %% (uae_s32)(uae_s16)src;\n");
1679: printf ("\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
1680: printf ("\tif (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;\n");
1681: genflags (flag_logical, sz_word, "newv", "", "");
1682: printf ("\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
1683: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1684: printf ("\t}\n");
1685: printf ("\t}\n");
1.1.1.8 root 1686: // insn_n_cycles += 154;
1687: printf ("\tretcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);\n");
1688: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 1689: need_endlabel = 1;
1690: break;
1691: case i_MULU:
1692: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1693: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0);
1694: start_brace ();
1695: printf ("\tuae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;\n");
1696: genflags (flag_logical, sz_long, "newv", "", "");
1697: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.8 root 1698: /* [NP] number of cycles is 38 + 2n + ea time ; n is the number of 1 bits in src */
1699: insn_n_cycles += 38-4; /* insn_n_cycles is already initialized to 4 instead of 0 */
1700: printf ("\twhile (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }\n");
1701: sprintf(exactCpuCycles," return (%i+retcycles*2);", insn_n_cycles);
1.1 root 1702: break;
1703: case i_MULS:
1704: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1705: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0);
1706: start_brace ();
1707: printf ("\tuae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;\n");
1.1.1.8 root 1708: printf ("\tuae_u32 src2;\n");
1.1 root 1709: genflags (flag_logical, sz_long, "newv", "", "");
1710: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.8 root 1711: /* [NP] number of cycles is 38 + 2n + ea time ; n is the number of 01 or 10 patterns in src expanded to 17 bits */
1712: insn_n_cycles += 38-4; /* insn_n_cycles is already initialized to 4 instead of 0 */
1713: printf ("\tsrc2 = ((uae_u32)src) << 1;\n");
1714: printf ("\twhile (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }\n");
1715: sprintf(exactCpuCycles," return (%i+retcycles*2);", insn_n_cycles);
1.1 root 1716: break;
1717: case i_CHK:
1718: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1719: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1720: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1.1.1.8 root 1721: sync_m68k_pc ();
1.1.1.12 root 1722: printf ("\tif ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1723: printf ("\telse if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 1724: need_endlabel = 1;
1.1.1.2 root 1725: insn_n_cycles += 6;
1.1 root 1726: break;
1727:
1728: case i_CHK2:
1729: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1730: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
1731: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1732: printf ("\t{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];\n");
1733: switch (curi->size) {
1734: case sz_byte:
1735: printf ("\tlower=(uae_s32)(uae_s8)get_byte(dsta); upper = (uae_s32)(uae_s8)get_byte(dsta+1);\n");
1736: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;\n");
1737: break;
1738: case sz_word:
1739: printf ("\tlower=(uae_s32)(uae_s16)get_word(dsta); upper = (uae_s32)(uae_s16)get_word(dsta+2);\n");
1740: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;\n");
1741: break;
1742: case sz_long:
1743: printf ("\tlower=get_long(dsta); upper = get_long(dsta+4);\n");
1744: break;
1745: default:
1746: abort ();
1747: }
1748: printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
1749: printf ("\tSET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
1.1.1.8 root 1750: sync_m68k_pc ();
1.1.1.12 root 1751: printf ("\tif ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto %s; }\n}\n", endlabelstr);
1.1 root 1752: need_endlabel = 1;
1753: break;
1754:
1755: case i_ASR:
1756: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1757: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1758: start_brace ();
1759: switch (curi->size) {
1760: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1761: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1762: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1763: default: abort ();
1764: }
1765: printf ("\tuae_u32 sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1);
1766: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1767: printf ("\tretcycles = cnt;\n");
1.1 root 1768: printf ("\tCLEAR_CZNV;\n");
1769: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1770: printf ("\t\tval = %s & (uae_u32)-sign;\n", bit_mask (curi->size));
1771: printf ("\t\tSET_CFLG (sign);\n");
1772: duplicate_carry ();
1773: if (source_is_imm1_8 (curi))
1774: printf ("\t} else {\n");
1775: else
1776: printf ("\t} else if (cnt > 0) {\n");
1777: printf ("\t\tval >>= cnt - 1;\n");
1778: printf ("\t\tSET_CFLG (val & 1);\n");
1779: duplicate_carry ();
1780: printf ("\t\tval >>= 1;\n");
1781: printf ("\t\tval |= (%s << (%d - cnt)) & (uae_u32)-sign;\n",
1782: bit_mask (curi->size),
1783: bit_size (curi->size));
1784: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
1785: printf ("\t}\n");
1786: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1787: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1788: if(curi->size==sz_long)
1789: strcpy(exactCpuCycles," return (8+retcycles*2);");
1790: else
1791: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1792: break;
1793: case i_ASL:
1794: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1795: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1796: start_brace ();
1797: switch (curi->size) {
1798: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1799: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1800: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1801: default: abort ();
1802: }
1803: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1804: printf ("\tretcycles = cnt;\n");
1.1 root 1805: printf ("\tCLEAR_CZNV;\n");
1806: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1807: printf ("\t\tSET_VFLG (val != 0);\n");
1808: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
1809: bit_size (curi->size));
1810: duplicate_carry ();
1811: printf ("\t\tval = 0;\n");
1812: if (source_is_imm1_8 (curi))
1813: printf ("\t} else {\n");
1814: else
1815: printf ("\t} else if (cnt > 0) {\n");
1816: printf ("\t\tuae_u32 mask = (%s << (%d - cnt)) & %s;\n",
1817: bit_mask (curi->size),
1818: bit_size (curi->size) - 1,
1819: bit_mask (curi->size));
1820: printf ("\t\tSET_VFLG ((val & mask) != mask && (val & mask) != 0);\n");
1821: printf ("\t\tval <<= cnt - 1;\n");
1822: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
1823: duplicate_carry ();
1824: printf ("\t\tval <<= 1;\n");
1825: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
1826: printf ("\t}\n");
1827: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1828: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1829: if(curi->size==sz_long)
1830: strcpy(exactCpuCycles," return (8+retcycles*2);");
1831: else
1832: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1833: break;
1834: case i_LSR:
1835: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1836: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1837: start_brace ();
1838: switch (curi->size) {
1839: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1840: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1841: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1842: default: abort ();
1843: }
1844: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1845: printf ("\tretcycles = cnt;\n");
1.1 root 1846: printf ("\tCLEAR_CZNV;\n");
1847: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1848: printf ("\t\tSET_CFLG ((cnt == %d) & (val >> %d));\n",
1849: bit_size (curi->size), bit_size (curi->size) - 1);
1850: duplicate_carry ();
1851: printf ("\t\tval = 0;\n");
1852: if (source_is_imm1_8 (curi))
1853: printf ("\t} else {\n");
1854: else
1855: printf ("\t} else if (cnt > 0) {\n");
1856: printf ("\t\tval >>= cnt - 1;\n");
1857: printf ("\t\tSET_CFLG (val & 1);\n");
1858: duplicate_carry ();
1859: printf ("\t\tval >>= 1;\n");
1860: printf ("\t}\n");
1861: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1862: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1863: if(curi->size==sz_long)
1864: strcpy(exactCpuCycles," return (8+retcycles*2);");
1865: else
1866: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1867: break;
1868: case i_LSL:
1869: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1870: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1871: start_brace ();
1872: switch (curi->size) {
1873: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1874: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1875: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1876: default: abort ();
1877: }
1878: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1879: printf ("\tretcycles = cnt;\n");
1.1 root 1880: printf ("\tCLEAR_CZNV;\n");
1881: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1882: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
1883: bit_size (curi->size));
1884: duplicate_carry ();
1885: printf ("\t\tval = 0;\n");
1886: if (source_is_imm1_8 (curi))
1887: printf ("\t} else {\n");
1888: else
1889: printf ("\t} else if (cnt > 0) {\n");
1890: printf ("\t\tval <<= (cnt - 1);\n");
1891: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
1892: duplicate_carry ();
1893: printf ("\t\tval <<= 1;\n");
1894: printf ("\tval &= %s;\n", bit_mask (curi->size));
1895: printf ("\t}\n");
1896: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1897: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1898: if(curi->size==sz_long)
1899: strcpy(exactCpuCycles," return (8+retcycles*2);");
1900: else
1901: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1902: break;
1903: case i_ROL:
1904: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1905: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1906: start_brace ();
1907: switch (curi->size) {
1908: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1909: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1910: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1911: default: abort ();
1912: }
1913: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1914: printf ("\tretcycles = cnt;\n");
1.1 root 1915: printf ("\tCLEAR_CZNV;\n");
1916: if (source_is_imm1_8 (curi))
1917: printf ("{");
1918: else
1919: printf ("\tif (cnt > 0) {\n");
1920: printf ("\tuae_u32 loval;\n");
1921: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
1922: printf ("\tloval = val >> (%d - cnt);\n", bit_size (curi->size));
1923: printf ("\tval <<= cnt;\n");
1924: printf ("\tval |= loval;\n");
1925: printf ("\tval &= %s;\n", bit_mask (curi->size));
1926: printf ("\tSET_CFLG (val & 1);\n");
1927: printf ("}\n");
1928: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1929: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1930: if(curi->size==sz_long)
1931: strcpy(exactCpuCycles," return (8+retcycles*2);");
1932: else
1933: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1934: break;
1935: case i_ROR:
1936: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1937: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1938: start_brace ();
1939: switch (curi->size) {
1940: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1941: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1942: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1943: default: abort ();
1944: }
1945: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1946: printf ("\tretcycles = cnt;\n");
1.1 root 1947: printf ("\tCLEAR_CZNV;\n");
1948: if (source_is_imm1_8 (curi))
1949: printf ("{");
1950: else
1951: printf ("\tif (cnt > 0) {");
1952: printf ("\tuae_u32 hival;\n");
1953: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
1954: printf ("\thival = val << (%d - cnt);\n", bit_size (curi->size));
1955: printf ("\tval >>= cnt;\n");
1956: printf ("\tval |= hival;\n");
1957: printf ("\tval &= %s;\n", bit_mask (curi->size));
1958: printf ("\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
1959: printf ("\t}\n");
1960: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1961: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1962: if(curi->size==sz_long)
1963: strcpy(exactCpuCycles," return (8+retcycles*2);");
1964: else
1965: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1966: break;
1967: case i_ROXL:
1968: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1969: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1970: start_brace ();
1971: switch (curi->size) {
1972: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1973: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1974: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1975: default: abort ();
1976: }
1977: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1978: printf ("\tretcycles = cnt;\n");
1.1 root 1979: printf ("\tCLEAR_CZNV;\n");
1980: if (source_is_imm1_8 (curi))
1981: printf ("{");
1982: else {
1983: force_range_for_rox ("cnt", curi->size);
1984: printf ("\tif (cnt > 0) {\n");
1985: }
1986: printf ("\tcnt--;\n");
1987: printf ("\t{\n\tuae_u32 carry;\n");
1988: printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
1989: printf ("\tcarry = loval & 1;\n");
1990: printf ("\tval = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);\n");
1991: printf ("\tSET_XFLG (carry);\n");
1992: printf ("\tval &= %s;\n", bit_mask (curi->size));
1993: printf ("\t} }\n");
1994: printf ("\tSET_CFLG (GET_XFLG);\n");
1995: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1996: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1997: if(curi->size==sz_long)
1998: strcpy(exactCpuCycles," return (8+retcycles*2);");
1999: else
2000: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 2001: break;
2002: case i_ROXR:
2003: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
2004: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
2005: start_brace ();
2006: switch (curi->size) {
2007: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2008: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2009: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2010: default: abort ();
2011: }
2012: printf ("\tcnt &= 63;\n");
1.1.1.2 root 2013: printf ("\tretcycles = cnt;\n");
1.1 root 2014: printf ("\tCLEAR_CZNV;\n");
2015: if (source_is_imm1_8 (curi))
2016: printf ("{");
2017: else {
2018: force_range_for_rox ("cnt", curi->size);
2019: printf ("\tif (cnt > 0) {\n");
2020: }
2021: printf ("\tcnt--;\n");
2022: printf ("\t{\n\tuae_u32 carry;\n");
2023: printf ("\tuae_u32 hival = (val << 1) | GET_XFLG;\n");
2024: printf ("\thival <<= (%d - cnt);\n", bit_size (curi->size) - 1);
2025: printf ("\tval >>= cnt;\n");
2026: printf ("\tcarry = val & 1;\n");
2027: printf ("\tval >>= 1;\n");
2028: printf ("\tval |= hival;\n");
2029: printf ("\tSET_XFLG (carry);\n");
2030: printf ("\tval &= %s;\n", bit_mask (curi->size));
2031: printf ("\t} }\n");
2032: printf ("\tSET_CFLG (GET_XFLG);\n");
2033: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2034: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 2035: if(curi->size==sz_long)
2036: strcpy(exactCpuCycles," return (8+retcycles*2);");
2037: else
2038: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 2039: break;
2040: case i_ASRW:
2041: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2042: start_brace ();
2043: switch (curi->size) {
2044: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2045: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2046: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2047: default: abort ();
2048: }
2049: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
2050: printf ("\tuae_u32 cflg = val & 1;\n");
2051: printf ("\tval = (val >> 1) | sign;\n");
2052: genflags (flag_logical, curi->size, "val", "", "");
2053: printf ("\tSET_CFLG (cflg);\n");
2054: duplicate_carry ();
2055: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2056: break;
2057: case i_ASLW:
2058: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2059: start_brace ();
2060: switch (curi->size) {
2061: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2062: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2063: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2064: default: abort ();
2065: }
2066: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
2067: printf ("\tuae_u32 sign2;\n");
2068: printf ("\tval <<= 1;\n");
2069: genflags (flag_logical, curi->size, "val", "", "");
2070: printf ("\tsign2 = %s & val;\n", cmask (curi->size));
2071: printf ("\tSET_CFLG (sign != 0);\n");
2072: duplicate_carry ();
2073:
2074: printf ("\tSET_VFLG (GET_VFLG | (sign2 != sign));\n");
2075: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2076: break;
2077: case i_LSRW:
2078: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2079: start_brace ();
2080: switch (curi->size) {
2081: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2082: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2083: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2084: default: abort ();
2085: }
2086: printf ("\tuae_u32 carry = val & 1;\n");
2087: printf ("\tval >>= 1;\n");
2088: genflags (flag_logical, curi->size, "val", "", "");
2089: printf ("SET_CFLG (carry);\n");
2090: duplicate_carry ();
2091: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2092: break;
2093: case i_LSLW:
2094: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2095: start_brace ();
2096: switch (curi->size) {
2097: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2098: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2099: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2100: default: abort ();
2101: }
2102: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2103: printf ("\tval <<= 1;\n");
2104: genflags (flag_logical, curi->size, "val", "", "");
2105: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2106: duplicate_carry ();
2107: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2108: break;
2109: case i_ROLW:
2110: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2111: start_brace ();
2112: switch (curi->size) {
2113: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2114: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2115: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2116: default: abort ();
2117: }
2118: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2119: printf ("\tval <<= 1;\n");
2120: printf ("\tif (carry) val |= 1;\n");
2121: genflags (flag_logical, curi->size, "val", "", "");
2122: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2123: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2124: break;
2125: case i_RORW:
2126: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2127: start_brace ();
2128: switch (curi->size) {
2129: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2130: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2131: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2132: default: abort ();
2133: }
2134: printf ("\tuae_u32 carry = val & 1;\n");
2135: printf ("\tval >>= 1;\n");
2136: printf ("\tif (carry) val |= %s;\n", cmask (curi->size));
2137: genflags (flag_logical, curi->size, "val", "", "");
2138: printf ("SET_CFLG (carry);\n");
2139: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2140: break;
2141: case i_ROXLW:
2142: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2143: start_brace ();
2144: switch (curi->size) {
2145: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2146: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2147: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2148: default: abort ();
2149: }
2150: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2151: printf ("\tval <<= 1;\n");
2152: printf ("\tif (GET_XFLG) val |= 1;\n");
2153: genflags (flag_logical, curi->size, "val", "", "");
2154: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2155: duplicate_carry ();
2156: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2157: break;
2158: case i_ROXRW:
2159: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2160: start_brace ();
2161: switch (curi->size) {
2162: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2163: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2164: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2165: default: abort ();
2166: }
2167: printf ("\tuae_u32 carry = val & 1;\n");
2168: printf ("\tval >>= 1;\n");
2169: printf ("\tif (GET_XFLG) val |= %s;\n", cmask (curi->size));
2170: genflags (flag_logical, curi->size, "val", "", "");
2171: printf ("SET_CFLG (carry);\n");
2172: duplicate_carry ();
2173: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2174: break;
2175: case i_MOVEC2:
2176: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2177: start_brace ();
2178: printf ("\tint regno = (src >> 12) & 15;\n");
2179: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
2180: printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
2181: break;
2182: case i_MOVE2C:
2183: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2184: start_brace ();
2185: printf ("\tint regno = (src >> 12) & 15;\n");
2186: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
2187: printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
2188: break;
2189: case i_CAS:
2190: {
2191: int old_brace_level;
2192: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2193: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2194: start_brace ();
2195: printf ("\tint ru = (src >> 6) & 7;\n");
2196: printf ("\tint rc = src & 7;\n");
2197: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, rc)", "dst");
2198: printf ("\tif (GET_ZFLG)");
2199: old_brace_level = n_braces;
2200: start_brace ();
2201: genastore ("(m68k_dreg(regs, ru))", curi->dmode, "dstreg", curi->size, "dst");
2202: pop_braces (old_brace_level);
2203: printf ("else");
2204: start_brace ();
2205: printf ("m68k_dreg(regs, rc) = dst;\n");
2206: pop_braces (old_brace_level);
2207: }
2208: break;
2209: case i_CAS2:
2210: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2211: printf ("\tuae_u32 rn1 = regs.regs[(extra >> 28) & 15];\n");
2212: printf ("\tuae_u32 rn2 = regs.regs[(extra >> 12) & 15];\n");
2213: if (curi->size == sz_word) {
2214: int old_brace_level = n_braces;
2215: printf ("\tuae_u16 dst1 = get_word(rn1), dst2 = get_word(rn2);\n");
2216: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
2217: printf ("\tif (GET_ZFLG) {\n");
2218: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
2219: printf ("\tif (GET_ZFLG) {\n");
2220: printf ("\tput_word(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n");
2221: printf ("\tput_word(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n");
2222: printf ("\t}}\n");
2223: pop_braces (old_brace_level);
2224: printf ("\tif (! GET_ZFLG) {\n");
2225: printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = (m68k_dreg(regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
2226: printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = (m68k_dreg(regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
2227: printf ("\t}\n");
2228: } else {
2229: int old_brace_level = n_braces;
2230: printf ("\tuae_u32 dst1 = get_long(rn1), dst2 = get_long(rn2);\n");
2231: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
2232: printf ("\tif (GET_ZFLG) {\n");
2233: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
2234: printf ("\tif (GET_ZFLG) {\n");
2235: printf ("\tput_long(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n");
2236: printf ("\tput_long(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n");
2237: printf ("\t}}\n");
2238: pop_braces (old_brace_level);
2239: printf ("\tif (! GET_ZFLG) {\n");
2240: printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = dst1;\n");
2241: printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = dst2;\n");
2242: printf ("\t}\n");
2243: }
2244: break;
2245: case i_MOVES: /* ignore DFC and SFC because we have no MMU */
2246: {
2247: int old_brace_level;
2248: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2249: printf ("\tif (extra & 0x800)\n");
2250: old_brace_level = n_braces;
2251: start_brace ();
2252: printf ("\tuae_u32 src = regs.regs[(extra >> 12) & 15];\n");
2253: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
2254: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
2255: pop_braces (old_brace_level);
2256: printf ("else");
2257: start_brace ();
2258: genamode (curi->dmode, "dstreg", curi->size, "src", 1, 0);
2259: printf ("\tif (extra & 0x8000) {\n");
2260: switch (curi->size) {
2261: case sz_byte: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;\n"); break;
2262: case sz_word: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;\n"); break;
2263: case sz_long: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = src;\n"); break;
2264: default: abort ();
2265: }
2266: printf ("\t} else {\n");
2267: genastore ("src", Dreg, "(extra >> 12) & 7", curi->size, "");
2268: printf ("\t}\n");
2269: pop_braces (old_brace_level);
2270: }
2271: break;
2272: case i_BKPT: /* only needed for hardware emulators */
2273: sync_m68k_pc ();
2274: printf ("\top_illg(opcode);\n");
2275: break;
2276: case i_CALLM: /* not present in 68030 */
2277: sync_m68k_pc ();
2278: printf ("\top_illg(opcode);\n");
2279: break;
2280: case i_RTM: /* not present in 68030 */
2281: sync_m68k_pc ();
2282: printf ("\top_illg(opcode);\n");
2283: break;
2284: case i_TRAPcc:
2285: if (curi->smode != am_unknown && curi->smode != am_illg)
2286: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
1.1.1.12 root 2287: printf ("\tif (cctrue(%d)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto %s; }\n", curi->cc, endlabelstr);
1.1 root 2288: need_endlabel = 1;
2289: break;
2290: case i_DIVL:
2291: sync_m68k_pc ();
2292: start_brace ();
2293: printf ("\tuaecptr oldpc = m68k_getpc();\n");
2294: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2295: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2296: sync_m68k_pc ();
2297: printf ("\tm68k_divl(opcode, dst, extra, oldpc);\n");
2298: break;
2299: case i_MULL:
2300: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2301: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2302: sync_m68k_pc ();
2303: printf ("\tm68k_mull(opcode, dst, extra);\n");
2304: break;
2305: case i_BFTST:
2306: case i_BFEXTU:
2307: case i_BFCHG:
2308: case i_BFEXTS:
2309: case i_BFCLR:
2310: case i_BFFFO:
2311: case i_BFSET:
2312: case i_BFINS:
2313: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2314: genamode (curi->dmode, "dstreg", sz_long, "dst", 2, 0);
2315: start_brace ();
2316: printf ("\tuae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;\n");
2317: printf ("\tint width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;\n");
2318: if (curi->dmode == Dreg) {
2319: printf ("\tuae_u32 tmp = m68k_dreg(regs, dstreg) << (offset & 0x1f);\n");
2320: } else {
2321: printf ("\tuae_u32 tmp,bf0,bf1;\n");
2322: printf ("\tdsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);\n");
2323: printf ("\tbf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;\n");
2324: printf ("\ttmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));\n");
2325: }
2326: printf ("\ttmp >>= (32 - width);\n");
2327: printf ("\tSET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);\n");
2328: printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
2329: switch (curi->mnemo) {
2330: case i_BFTST:
2331: break;
2332: case i_BFEXTU:
2333: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n");
2334: break;
2335: case i_BFCHG:
2336: printf ("\ttmp = ~tmp;\n");
2337: break;
2338: case i_BFEXTS:
2339: printf ("\tif (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);\n");
2340: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n");
2341: break;
2342: case i_BFCLR:
2343: printf ("\ttmp = 0;\n");
2344: break;
2345: case i_BFFFO:
2346: printf ("\t{ uae_u32 mask = 1 << (width-1);\n");
2347: printf ("\twhile (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}\n");
2348: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = offset;\n");
2349: break;
2350: case i_BFSET:
2351: printf ("\ttmp = 0xffffffff;\n");
2352: break;
2353: case i_BFINS:
2354: printf ("\ttmp = m68k_dreg(regs, (extra >> 12) & 7);\n");
1.1.1.4 root 2355: printf ("\tSET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);\n");
2356: printf ("\tSET_ZFLG (tmp == 0);\n");
1.1 root 2357: break;
2358: default:
2359: break;
2360: }
2361: if (curi->mnemo == i_BFCHG
2362: || curi->mnemo == i_BFCLR
2363: || curi->mnemo == i_BFSET
2364: || curi->mnemo == i_BFINS)
2365: {
2366: printf ("\ttmp <<= (32 - width);\n");
2367: if (curi->dmode == Dreg) {
2368: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ((offset & 0x1f) == 0 ? 0 :\n");
2369: printf ("\t\t(0xffffffff << (32 - (offset & 0x1f))))) |\n");
2370: printf ("\t\t(tmp >> (offset & 0x1f)) |\n");
2371: printf ("\t\t(((offset & 0x1f) + width) >= 32 ? 0 :\n");
2372: printf (" (m68k_dreg(regs, dstreg) & ((uae_u32)0xffffffff >> ((offset & 0x1f) + width))));\n");
2373: } else {
2374: printf ("\tbf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |\n");
2375: printf ("\t\t(tmp >> (offset & 7)) |\n");
2376: printf ("\t\t(((offset & 7) + width) >= 32 ? 0 :\n");
2377: printf ("\t\t (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));\n");
2378: printf ("\tput_long(dsta,bf0 );\n");
2379: printf ("\tif (((offset & 7) + width) > 32) {\n");
2380: printf ("\t\tbf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |\n");
2381: printf ("\t\t\t(tmp << (8 - (offset & 7)));\n");
2382: printf ("\t\tput_byte(dsta+4,bf1);\n");
2383: printf ("\t}\n");
2384: }
2385: }
2386: break;
2387: case i_PACK:
2388: if (curi->smode == Dreg) {
2389: printf ("\tuae_u16 val = m68k_dreg(regs, srcreg) + %s;\n", gen_nextiword ());
2390: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);\n");
2391: } else {
2392: printf ("\tuae_u16 val;\n");
2393: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2394: printf ("\tval = (uae_u16)get_byte(m68k_areg(regs, srcreg));\n");
2395: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2396: printf ("\tval = (val | ((uae_u16)get_byte(m68k_areg(regs, srcreg)) << 8)) + %s;\n", gen_nextiword ());
2397: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2398: printf ("\tput_byte(m68k_areg(regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));\n");
2399: }
2400: break;
2401: case i_UNPK:
2402: if (curi->smode == Dreg) {
2403: printf ("\tuae_u16 val = m68k_dreg(regs, srcreg);\n");
2404: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword ());
2405: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffff0000) | (val & 0xffff);\n");
2406: } else {
2407: printf ("\tuae_u16 val;\n");
2408: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2409: printf ("\tval = (uae_u16)get_byte(m68k_areg(regs, srcreg));\n");
2410: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword ());
2411: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2412: printf ("\tput_byte(m68k_areg(regs, dstreg),val);\n");
2413: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2414: printf ("\tput_byte(m68k_areg(regs, dstreg),val >> 8);\n");
2415: }
2416: break;
2417: case i_TAS:
2418: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2419: genflags (flag_logical, curi->size, "src", "", "");
2420: printf ("\tsrc |= 0x80;\n");
2421: genastore ("src", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 2422: if( curi->smode!=Dreg ) insn_n_cycles += 2;
1.1 root 2423: break;
2424: case i_FPP:
2425: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2426: sync_m68k_pc ();
2427: printf ("\tfpp_opp(opcode,extra);\n");
2428: break;
2429: case i_FDBcc:
2430: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2431: sync_m68k_pc ();
2432: printf ("\tfdbcc_opp(opcode,extra);\n");
2433: break;
2434: case i_FScc:
2435: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2436: sync_m68k_pc ();
2437: printf ("\tfscc_opp(opcode,extra);\n");
2438: break;
2439: case i_FTRAPcc:
2440: sync_m68k_pc ();
2441: start_brace ();
2442: printf ("\tuaecptr oldpc = m68k_getpc();\n");
2443: if (curi->smode != am_unknown && curi->smode != am_illg)
2444: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
2445: sync_m68k_pc ();
2446: printf ("\tftrapcc_opp(opcode,oldpc);\n");
2447: break;
2448: case i_FBcc:
2449: sync_m68k_pc ();
2450: start_brace ();
2451: printf ("\tuaecptr pc = m68k_getpc();\n");
2452: genamode (curi->dmode, "srcreg", curi->size, "extra", 1, 0);
2453: sync_m68k_pc ();
2454: printf ("\tfbcc_opp(opcode,pc,extra);\n");
2455: break;
2456: case i_FSAVE:
2457: sync_m68k_pc ();
2458: printf ("\tfsave_opp(opcode);\n");
2459: break;
2460: case i_FRESTORE:
2461: sync_m68k_pc ();
2462: printf ("\tfrestore_opp(opcode);\n");
2463: break;
2464:
2465: case i_CINVL:
2466: case i_CINVP:
2467: case i_CINVA:
2468: case i_CPUSHL:
2469: case i_CPUSHP:
2470: case i_CPUSHA:
2471: break;
2472: case i_MOVE16:
1.1.1.4 root 2473: if ((opcode & 0xfff8) == 0xf620) {
2474: /* MOVE16 (Ax)+,(Ay)+ */
2475: printf ("\tuaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
2476: printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword());
2477: printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n");
2478: printf ("\tput_long(memd, get_long(mems));\n");
2479: printf ("\tput_long(memd+4, get_long(mems+4));\n");
2480: printf ("\tput_long(memd+8, get_long(mems+8));\n");
2481: printf ("\tput_long(memd+12, get_long(mems+12));\n");
2482: printf ("\tif (srcreg != dstreg)\n");
2483: printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2484: printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2485: } else {
2486: /* Other variants */
2487: genamode (curi->smode, "srcreg", curi->size, "mems", 0, 2);
2488: genamode (curi->dmode, "dstreg", curi->size, "memd", 0, 2);
2489: printf ("\tmemsa &= ~15;\n");
2490: printf ("\tmemda &= ~15;\n");
2491: printf ("\tput_long(memda, get_long(memsa));\n");
2492: printf ("\tput_long(memda+4, get_long(memsa+4));\n");
2493: printf ("\tput_long(memda+8, get_long(memsa+8));\n");
2494: printf ("\tput_long(memda+12, get_long(memsa+12));\n");
2495: if ((opcode & 0xfff8) == 0xf600)
2496: printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2497: else if ((opcode & 0xfff8) == 0xf608)
2498: printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2499: }
1.1 root 2500: break;
2501:
2502: case i_MMUOP:
2503: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2504: sync_m68k_pc ();
2505: printf ("\tmmu_op(opcode,extra);\n");
2506: break;
2507: default:
2508: abort ();
2509: break;
2510: }
2511: finish_braces ();
2512: sync_m68k_pc ();
2513: }
2514:
2515: static void generate_includes (FILE * f)
2516: {
2517: fprintf (f, "#include \"sysdeps.h\"\n");
2518: fprintf (f, "#include \"hatari-glue.h\"\n");
2519: fprintf (f, "#include \"maccess.h\"\n");
2520: fprintf (f, "#include \"memory.h\"\n");
2521: fprintf (f, "#include \"newcpu.h\"\n");
2522: fprintf (f, "#include \"cputbl.h\"\n");
2523: fprintf (f, "#define CPUFUNC(x) x##_ff\n"
2524: "#ifdef NOFLAGS\n"
2525: "#include \"noflags.h\"\n"
2526: "#endif\n");
2527: }
2528:
2529: static int postfix;
2530:
2531: static void generate_one_opcode (int rp)
2532: {
2533: int i;
2534: uae_u16 smsk, dmsk;
2535: long int opcode = opcode_map[rp];
2536:
1.1.1.2 root 2537: exactCpuCycles[0] = 0; /* Default: not used */
2538:
1.1 root 2539: if (table68k[opcode].mnemo == i_ILLG
2540: || table68k[opcode].clev > cpu_level)
2541: return;
2542:
2543: for (i = 0; lookuptab[i].name[0]; i++) {
2544: if (table68k[opcode].mnemo == lookuptab[i].mnemo)
2545: break;
2546: }
2547:
2548: if (table68k[opcode].handler != -1)
2549: return;
2550:
2551: if (opcode_next_clev[rp] != cpu_level) {
2552: fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp],
2553: opcode, lookuptab[i].name);
2554: return;
2555: }
2556: fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, postfix, opcode, lookuptab[i].name);
2557: fprintf (headerfile, "extern cpuop_func op_%lx_%d_nf;\n", opcode, postfix);
2558: fprintf (headerfile, "extern cpuop_func op_%lx_%d_ff;\n", opcode, postfix);
2559: printf ("unsigned long REGPARAM2 CPUFUNC(op_%lx_%d)(uae_u32 opcode) /* %s */\n{\n", opcode, postfix, lookuptab[i].name);
2560:
2561: switch (table68k[opcode].stype) {
2562: case 0: smsk = 7; break;
2563: case 1: smsk = 255; break;
2564: case 2: smsk = 15; break;
2565: case 3: smsk = 7; break;
2566: case 4: smsk = 7; break;
2567: case 5: smsk = 63; break;
1.1.1.4 root 2568: case 7: smsk = 3; break;
1.1 root 2569: default: abort ();
2570: }
2571: dmsk = 7;
2572:
2573: next_cpu_level = -1;
2574: if (table68k[opcode].suse
2575: && table68k[opcode].smode != imm && table68k[opcode].smode != imm0
2576: && table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
2577: && table68k[opcode].smode != absw && table68k[opcode].smode != absl
2578: && table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
2579: {
2580: if (table68k[opcode].spos == -1) {
2581: if (((int) table68k[opcode].sreg) >= 128)
2582: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].sreg);
2583: else
2584: printf ("\tuae_u32 srcreg = %d;\n", (int) table68k[opcode].sreg);
2585: } else {
2586: char source[100];
2587: int pos = table68k[opcode].spos;
2588:
2589: if (pos)
2590: sprintf (source, "((opcode >> %d) & %d)", pos, smsk);
2591: else
2592: sprintf (source, "(opcode & %d)", smsk);
2593:
2594: if (table68k[opcode].stype == 3)
2595: printf ("\tuae_u32 srcreg = imm8_table[%s];\n", source);
2596: else if (table68k[opcode].stype == 1)
2597: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%s;\n", source);
2598: else
2599: printf ("\tuae_u32 srcreg = %s;\n", source);
2600: }
2601: }
2602: if (table68k[opcode].duse
2603: /* Yes, the dmode can be imm, in case of LINK or DBcc */
2604: && table68k[opcode].dmode != imm && table68k[opcode].dmode != imm0
2605: && table68k[opcode].dmode != imm1 && table68k[opcode].dmode != imm2
2606: && table68k[opcode].dmode != absw && table68k[opcode].dmode != absl)
2607: {
2608: if (table68k[opcode].dpos == -1) {
2609: if (((int) table68k[opcode].dreg) >= 128)
2610: printf ("\tuae_u32 dstreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].dreg);
2611: else
2612: printf ("\tuae_u32 dstreg = %d;\n", (int) table68k[opcode].dreg);
2613: } else {
2614: int pos = table68k[opcode].dpos;
2615: #if 0
2616: /* Check that we can do the little endian optimization safely. */
2617: if (pos < 8 && (dmsk >> (8 - pos)) != 0)
2618: abort ();
2619: #endif
2620: if (pos)
2621: printf ("\tuae_u32 dstreg = (opcode >> %d) & %d;\n",
2622: pos, dmsk);
2623: else
2624: printf ("\tuae_u32 dstreg = opcode & %d;\n", dmsk);
2625: }
2626: }
2627: need_endlabel = 0;
2628: endlabelno++;
2629: sprintf (endlabelstr, "endlabel%d", endlabelno);
1.1.1.2 root 2630: if(table68k[opcode].mnemo==i_ASR || table68k[opcode].mnemo==i_ASL || table68k[opcode].mnemo==i_LSR || table68k[opcode].mnemo==i_LSL
2631: || table68k[opcode].mnemo==i_ROL || table68k[opcode].mnemo==i_ROR || table68k[opcode].mnemo==i_ROXL || table68k[opcode].mnemo==i_ROXR
1.1.1.8 root 2632: || table68k[opcode].mnemo==i_MVMEL || table68k[opcode].mnemo==i_MVMLE
2633: || table68k[opcode].mnemo==i_MULU || table68k[opcode].mnemo==i_MULS
2634: || table68k[opcode].mnemo==i_DIVU || table68k[opcode].mnemo==i_DIVS )
2635: printf("\tunsigned int retcycles = 0;\n");
1.1 root 2636: gen_opcode (opcode);
2637: if (need_endlabel)
2638: printf ("%s: ;\n", endlabelstr);
1.1.1.8 root 2639:
2640: if (strlen(exactCpuCycles) > 0)
2641: printf("%s\n",exactCpuCycles);
2642: else
2643: printf ("return %d;\n", insn_n_cycles);
2644: /* Now patch in the instruction cycles at the beginning of the function: */
2645: fseek(stdout, nCurInstrCycPos, SEEK_SET);
2646: printf("%d;", insn_n_cycles);
2647: fseek(stdout, 0, SEEK_END);
2648:
1.1 root 2649: printf ("}\n");
2650: opcode_next_clev[rp] = next_cpu_level;
2651: opcode_last_postfix[rp] = postfix;
2652: }
2653:
2654: static void generate_func (void)
2655: {
2656: int i, j, rp;
2657:
2658: using_prefetch = 0;
2659: using_exception_3 = 0;
2660: for (i = 0; i < 6; i++) {
2661: cpu_level = 4 - i;
2662: if (i == 5) {
2663: cpu_level = 0;
2664: using_prefetch = 1;
2665: using_exception_3 = 1;
2666: for (rp = 0; rp < nr_cpuop_funcs; rp++)
2667: opcode_next_clev[rp] = 0;
2668: }
2669:
2670: postfix = i;
1.1.1.7 root 2671: fprintf (stblfile, "const struct cputbl CPUFUNC(op_smalltbl_%d)[] = {\n", postfix);
1.1 root 2672:
2673: /* sam: this is for people with low memory (eg. me :)) */
2674: printf ("\n"
2675: "#if !defined(PART_1) && !defined(PART_2) && "
2676: "!defined(PART_3) && !defined(PART_4) && "
2677: "!defined(PART_5) && !defined(PART_6) && "
2678: "!defined(PART_7) && !defined(PART_8)"
2679: "\n"
2680: "#define PART_1 1\n"
2681: "#define PART_2 1\n"
2682: "#define PART_3 1\n"
2683: "#define PART_4 1\n"
2684: "#define PART_5 1\n"
2685: "#define PART_6 1\n"
2686: "#define PART_7 1\n"
2687: "#define PART_8 1\n"
2688: "#endif\n\n");
2689:
2690: rp = 0;
2691: for(j=1;j<=8;++j) {
2692: int k = (j*nr_cpuop_funcs)/8;
2693: printf ("#ifdef PART_%d\n",j);
2694: for (; rp < k; rp++)
2695: generate_one_opcode (rp);
2696: printf ("#endif\n\n");
2697: }
2698:
2699: fprintf (stblfile, "{ 0, 0, 0 }};\n");
2700: }
2701:
2702: }
2703:
2704: int main (int argc, char **argv)
2705: {
2706: read_table68k ();
2707: do_merges ();
2708:
2709: opcode_map = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2710: opcode_last_postfix = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2711: opcode_next_clev = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2712: counts = (unsigned long *) malloc (65536 * sizeof (unsigned long));
2713: read_counts ();
2714:
2715: /* It would be a lot nicer to put all in one file (we'd also get rid of
2716: * cputbl.h that way), but cpuopti can't cope. That could be fixed, but
2717: * I don't dare to touch the 68k version. */
2718:
2719: headerfile = fopen ("cputbl.h", "wb");
2720: stblfile = fopen ("cpustbl.c", "wb");
1.1.1.11 root 2721: if (freopen ("cpuemu.c", "wb", stdout) == NULL) {
2722: perror("cpuemu.c");
2723: return -1;
2724: }
1.1 root 2725:
2726: generate_includes (stdout);
2727: generate_includes (stblfile);
2728:
2729: generate_func ();
2730:
2731: free (table68k);
2732: return 0;
2733: }
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