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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation generator
5: *
6: * This is a fairly stupid program that generates a lot of case labels that
7: * can be #included in a switch statement.
8: * As an alternative, it can generate functions that handle specific
9: * MC68000 instructions, plus a prototype header file and a function pointer
10: * array to look up the function for an opcode.
11: * Error checking is bad, an illegal table68k file will cause the program to
12: * call abort().
13: * The generated code is sometimes sub-optimal, an optimizing compiler should
14: * take care of this.
15: *
16: * The source for the insn timings is Markt & Technik's Amiga Magazin 8/1992.
17: *
18: * Copyright 1995, 1996, 1997, 1998, 1999, 2000 Bernd Schmidt
1.1.1.2 root 19: *
20: * Adaptation to Hatari and better cpu timings by Thomas Huth
21: *
1.1.1.16 root 22: * This file is distributed under the GNU General Public License, version 2
23: * or at your option any later version. Read the file gpl.txt for details.
1.1 root 24: */
1.1.1.8 root 25:
26:
27: /* 2007/03/xx [NP] Use add_cycles.pl to set 'CurrentInstrCycles' in each opcode. */
28: /* 2007/04/09 [NP] Correct CLR : on 68000, CLR reads the memory before clearing it (but we should */
29: /* not add cycles for reading). This means CLR can give 2 wait states (one for */
30: /* read and one for right) (clr.b $fa1b.w in Decade's Demo Main Menu). */
31: /* 2007/04/14 [NP] - Although dest -(an) normally takes 2 cycles, this is not the case for move : */
32: /* move dest (an), (an)+ and -(an) all take the same time (curi->dmode == Apdi) */
33: /* (Syntax Terror Demo Reset). */
34: /* - Scc takes 6 cycles instead of 4 if the result is true (Ventura Demo Loader). */
35: /* - Store the family of the current opcode into OpcodeFamily : used to check */
36: /* instruction pairing on ST into m68000.c */
37: /* 2007/04/17 [NP] Add support for cycle accurate MULU (No Cooper Greeting Screen). */
38: /* 2007/04/24 [NP] BCLR #n,Dx takes 12 cycles instead of 14 if n<16 (ULM Demo Menu). */
39: /* 2007/04/25 [NP] On ST, d8(An,Xn) and d8(PC,Xn) take 2 cycles more than the official 68000's */
40: /* table (ULM Demo Menu). */
41: /* 2007/11/12 [NP] Add refill_prefetch for i_ADD to fix Transbeauce 2 demo self modified code. */
42: /* Ugly hack, we need better prefetch emulation (switch to winuae gencpu.c) */
43: /* 2007/11/25 [NP] In i_DBcc, in case of address error, last_addr_for_exception_3 should be */
44: /* pc+4, not pc+2 (Transbeauce 2 demo) (e.g. 'dbf d0,#$fff5'). */
45: /* This means the value pushed on the frame stack should be the address of the */
46: /* instruction following the one generating the address error. */
47: /* FIXME : this should be the case for i_BSR and i_BCC too (need to check on */
48: /* a real 68000). */
49: /* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */
50: /* Cwik, [email protected]). */
51: /* 2007/12/08 [NP] In case of CHK/CHK2 exception, PC stored on the stack wasn't pointing to the */
52: /* next instruction but to the current CHK/CHK2 instruction (Transbeauce 2 demo). */
53: /* We need to call 'sync_m68k_pc' before calling 'Exception'. */
54: /* 2007/12/09 [NP] CHK.L (e.g. $4700) doesn't exist on 68000 and should be considered as an illegal*/
55: /* instruction (Transbeauce 2 demo) -> change in table68k. */
56: /* 2008/01/24 [NP] BCLR Dy,Dx takes 8 cycles instead of 10 if Dy<16 (Fullshade in Anomaly Demos). */
57: /* 2008/01/26 [NP] On ST, d8(An,Xn) takes 2 cycles more when used with ADDA/SUBA (ULM Demo Menu) */
58: /* but not when used with MOVE (e.g. 'move.l 0(a5,d1),(a4)' takes 26 cycles and so */
59: /* can pair with a lsr) (Anomaly Demo Intro). */
1.1.1.9 root 60: /* 2008/04/26 [NP] Handle sz_byte for Areg in genamode, as 'move.b a1,(a0)' ($1089) is possible */
61: /* on ST (fix Blood Money on Superior 65) */
1.1.1.12 root 62: /* 2010/04/05 [NP] On ST, d8(An,Xn) takes 2 cycles more (which can generate pairing). */
63: /* Use BusCyclePenalty to properly handle the 2/4 cycles added in that case when */
64: /* addressing mode is Ad8r or PC8r (ULM Demo Menu, Anomaly Demo Intro, DHS */
65: /* Sommarhack 2010) (see m68000.h) */
1.1.1.15 root 66: /* 2012/01/29 [NP] Add refill_prefetch for i_EOR to fix Operation Clean Streets self modified code.*/
67: /* Ugly hack, we need better prefetch emulation (switch to winuae gencpu.c) */
68: /* 2012/05/05 [NP] In i_JMP, in case of address error, last_addr_for_exception_3 should not always */
69: /* be pc+6, (Sherman Cracktro in No Extra V2 compilation) (e.g. 'jmp (a2)' : pc+2) */
1.1.1.17! root 70: /* 2013/03/17 [NP] Add refill_prefetch for i_SUB, i_NEG, i_NEGX, i_NOT (similar to i_ADD/i_EOR) */
! 71: /* 2014/03/07 [NP] Add refill_prefetch for i_Move Dn,xxxx.l (Union Demo, Darkman, Parasol Stars) */
! 72: /* Add refill_prefetch for i_Move #xxxx,(An) (Titan) */
! 73: /* 2014/04/09 [NP] Similar to CLR on 68000, Scc should do a read before doing the write and can */
! 74: /* give 2 wait states (sf $fffa07 in Chart Attack compilation by Gremlin) */
! 75: /* 2014/04/11 [NP] Add refill_prefetch for i_Move Dn,(An) (International 3D Tennis) */
1.1.1.8 root 76:
77:
1.1.1.11 root 78: const char GenCpu_fileid[] = "Hatari gencpu.c : " __DATE__ " " __TIME__;
1.1 root 79:
80: #include <ctype.h>
1.1.1.3 root 81: #include <string.h>
1.1 root 82:
83: #include "sysdeps.h"
84: #include "readcpu.h"
85:
86: #define BOOL_TYPE "int"
87:
88: static FILE *headerfile;
89: static FILE *stblfile;
90:
91: static int using_prefetch;
92: static int using_exception_3;
93: static int cpu_level;
94:
1.1.1.2 root 95: char exactCpuCycles[256]; /* Space to store return string for exact cpu cycles */
96:
1.1.1.8 root 97: long nCurInstrCycPos; /* Stores where we have to patch in the current cycles value */
1.1.1.2 root 98:
1.1 root 99: /* For the current opcode, the next lower level that will have different code.
100: * Initialized to -1 for each opcode. If it remains unchanged, indicates we
101: * are done with that opcode. */
102: static int next_cpu_level;
103: static int *opcode_map;
104: static int *opcode_next_clev;
105: static int *opcode_last_postfix;
106: static unsigned long *counts;
107:
1.1.1.6 root 108:
1.1 root 109: static void read_counts (void)
110: {
111: FILE *file;
112: unsigned long opcode, count, total;
113: char name[20];
114: int nr = 0;
115: memset (counts, 0, 65536 * sizeof *counts);
116:
117: file = fopen ("frequent.68k", "r");
118: if (file) {
1.1.1.11 root 119: if (fscanf (file, "Total: %lu\n", &total) == EOF) {
120: perror("read_counts");
121: }
1.1 root 122: while (fscanf (file, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
123: opcode_next_clev[nr] = 4;
124: opcode_last_postfix[nr] = -1;
125: opcode_map[nr++] = opcode;
126: counts[opcode] = count;
127: }
128: fclose (file);
129: }
130: if (nr == nr_cpuop_funcs)
131: return;
132: for (opcode = 0; opcode < 0x10000; opcode++) {
133: if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
134: && counts[opcode] == 0)
135: {
136: opcode_next_clev[nr] = 4;
137: opcode_last_postfix[nr] = -1;
138: opcode_map[nr++] = opcode;
139: counts[opcode] = count;
140: }
141: }
142: if (nr != nr_cpuop_funcs)
143: abort ();
144: }
145:
146: static char endlabelstr[80];
147: static int endlabelno = 0;
148: static int need_endlabel;
149:
150: static int n_braces = 0;
151: static int m68k_pc_offset = 0;
152: static int insn_n_cycles;
153:
154: static void start_brace (void)
155: {
156: n_braces++;
157: printf ("{");
158: }
159:
160: static void close_brace (void)
161: {
162: assert (n_braces > 0);
163: n_braces--;
164: printf ("}");
165: }
166:
167: static void finish_braces (void)
168: {
169: while (n_braces > 0)
170: close_brace ();
171: }
172:
173: static void pop_braces (int to)
174: {
175: while (n_braces > to)
176: close_brace ();
177: }
178:
179: static int bit_size (int size)
180: {
181: switch (size) {
182: case sz_byte: return 8;
183: case sz_word: return 16;
184: case sz_long: return 32;
185: default: abort ();
186: }
187: return 0;
188: }
189:
190: static const char *bit_mask (int size)
191: {
192: switch (size) {
193: case sz_byte: return "0xff";
194: case sz_word: return "0xffff";
195: case sz_long: return "0xffffffff";
196: default: abort ();
197: }
198: return 0;
199: }
200:
201: static const char *gen_nextilong (void)
202: {
203: static char buffer[80];
204: int r = m68k_pc_offset;
205: m68k_pc_offset += 4;
206:
207: insn_n_cycles += 8;
208:
209: if (using_prefetch)
210: sprintf (buffer, "get_ilong_prefetch(%d)", r);
211: else
212: sprintf (buffer, "get_ilong(%d)", r);
213: return buffer;
214: }
215:
216: static const char *gen_nextiword (void)
217: {
218: static char buffer[80];
219: int r = m68k_pc_offset;
220: m68k_pc_offset += 2;
221:
222: insn_n_cycles += 4;
223:
224: if (using_prefetch)
225: sprintf (buffer, "get_iword_prefetch(%d)", r);
226: else
227: sprintf (buffer, "get_iword(%d)", r);
228: return buffer;
229: }
230:
231: static const char *gen_nextibyte (void)
232: {
233: static char buffer[80];
234: int r = m68k_pc_offset;
235: m68k_pc_offset += 2;
236:
237: insn_n_cycles += 4;
238:
239: if (using_prefetch)
240: sprintf (buffer, "get_ibyte_prefetch(%d)", r);
241: else
242: sprintf (buffer, "get_ibyte(%d)", r);
243: return buffer;
244: }
245:
246: static void fill_prefetch_0 (void)
247: {
248: if (using_prefetch)
249: printf ("fill_prefetch_0 ();\n");
250: }
251:
252: static void fill_prefetch_2 (void)
253: {
254: if (using_prefetch)
255: printf ("fill_prefetch_2 ();\n");
256: }
257:
258: static void sync_m68k_pc (void)
259: {
260: if (m68k_pc_offset == 0)
261: return;
262: printf ("m68k_incpc(%d);\n", m68k_pc_offset);
263: switch (m68k_pc_offset) {
264: case 0:
265: /*fprintf (stderr, "refilling prefetch at 0\n"); */
266: break;
267: case 2:
268: fill_prefetch_2 ();
269: break;
270: default:
271: fill_prefetch_0 ();
272: break;
273: }
274: m68k_pc_offset = 0;
275: }
276:
277: /* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
1.1.1.4 root 278: * the calling routine handles Apdi and Aipi modes.
279: * gb-- movem == 2 means the same thing but for a MOVE16 instruction */
1.1.1.12 root 280: static void genamode (amodes mode, const char *reg, wordsizes size,
281: const char *name, int getv, int movem)
1.1 root 282: {
283: start_brace ();
284: switch (mode) {
285: case Dreg:
286: if (movem)
287: abort ();
288: if (getv == 1)
289: switch (size) {
290: case sz_byte:
291: printf ("\tuae_s8 %s = m68k_dreg(regs, %s);\n", name, reg);
292: break;
293: case sz_word:
294: printf ("\tuae_s16 %s = m68k_dreg(regs, %s);\n", name, reg);
295: break;
296: case sz_long:
297: printf ("\tuae_s32 %s = m68k_dreg(regs, %s);\n", name, reg);
298: break;
299: default:
300: abort ();
301: }
302: return;
303: case Areg:
304: if (movem)
305: abort ();
306: if (getv == 1)
307: switch (size) {
1.1.1.9 root 308: case sz_byte: // [NP] Areg with .b is possible in MOVE source */
309: printf ("\tuae_s8 %s = m68k_areg(regs, %s);\n", name, reg);
310: break;
1.1 root 311: case sz_word:
312: printf ("\tuae_s16 %s = m68k_areg(regs, %s);\n", name, reg);
313: break;
314: case sz_long:
315: printf ("\tuae_s32 %s = m68k_areg(regs, %s);\n", name, reg);
316: break;
317: default:
318: abort ();
319: }
320: return;
321: case Aind:
322: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
323: break;
324: case Aipi:
325: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
326: break;
327: case Apdi:
328: insn_n_cycles += 2;
329: switch (size) {
330: case sz_byte:
331: if (movem)
332: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
333: else
334: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - areg_byteinc[%s];\n", name, reg, reg);
335: break;
336: case sz_word:
337: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 2);
338: break;
339: case sz_long:
340: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 4);
341: break;
342: default:
343: abort ();
344: }
345: break;
346: case Ad16:
347: printf ("\tuaecptr %sa = m68k_areg(regs, %s) + (uae_s32)(uae_s16)%s;\n", name, reg, gen_nextiword ());
348: break;
349: case Ad8r:
350: insn_n_cycles += 2;
351: if (cpu_level > 1) {
352: if (next_cpu_level < 1)
353: next_cpu_level = 1;
354: sync_m68k_pc ();
355: start_brace ();
356: /* This would ordinarily be done in gen_nextiword, which we bypass. */
357: insn_n_cycles += 4;
358: printf ("\tuaecptr %sa = get_disp_ea_020(m68k_areg(regs, %s), next_iword());\n", name, reg);
1.1.1.8 root 359: } else {
1.1 root 360: printf ("\tuaecptr %sa = get_disp_ea_000(m68k_areg(regs, %s), %s);\n", name, reg, gen_nextiword ());
1.1.1.8 root 361: }
1.1.1.12 root 362: printf ("\tBusCyclePenalty += 2;\n");
1.1 root 363:
364: break;
365: case PC16:
366: printf ("\tuaecptr %sa = m68k_getpc () + %d;\n", name, m68k_pc_offset);
367: printf ("\t%sa += (uae_s32)(uae_s16)%s;\n", name, gen_nextiword ());
368: break;
369: case PC8r:
370: insn_n_cycles += 2;
371: if (cpu_level > 1) {
372: if (next_cpu_level < 1)
373: next_cpu_level = 1;
374: sync_m68k_pc ();
375: start_brace ();
376: /* This would ordinarily be done in gen_nextiword, which we bypass. */
377: insn_n_cycles += 4;
378: printf ("\tuaecptr tmppc = m68k_getpc();\n");
379: printf ("\tuaecptr %sa = get_disp_ea_020(tmppc, next_iword());\n", name);
380: } else {
381: printf ("\tuaecptr tmppc = m68k_getpc() + %d;\n", m68k_pc_offset);
382: printf ("\tuaecptr %sa = get_disp_ea_000(tmppc, %s);\n", name, gen_nextiword ());
383: }
1.1.1.12 root 384: printf ("\tBusCyclePenalty += 2;\n");
1.1 root 385:
386: break;
387: case absw:
388: printf ("\tuaecptr %sa = (uae_s32)(uae_s16)%s;\n", name, gen_nextiword ());
389: break;
390: case absl:
391: printf ("\tuaecptr %sa = %s;\n", name, gen_nextilong ());
392: break;
393: case imm:
394: if (getv != 1)
395: abort ();
396: switch (size) {
397: case sz_byte:
398: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte ());
399: break;
400: case sz_word:
401: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword ());
402: break;
403: case sz_long:
404: printf ("\tuae_s32 %s = %s;\n", name, gen_nextilong ());
405: break;
406: default:
407: abort ();
408: }
409: return;
410: case imm0:
411: if (getv != 1)
412: abort ();
413: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte ());
414: return;
415: case imm1:
416: if (getv != 1)
417: abort ();
418: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword ());
419: return;
420: case imm2:
421: if (getv != 1)
422: abort ();
423: printf ("\tuae_s32 %s = %s;\n", name, gen_nextilong ());
424: return;
425: case immi:
426: if (getv != 1)
427: abort ();
428: printf ("\tuae_u32 %s = %s;\n", name, reg);
429: return;
430: default:
431: abort ();
432: }
433:
434: /* We get here for all non-reg non-immediate addressing modes to
435: * actually fetch the value. */
436:
437: if (using_exception_3 && getv != 0 && size != sz_byte) {
438: printf ("\tif ((%sa & 1) != 0) {\n", name);
439: printf ("\t\tlast_fault_for_exception_3 = %sa;\n", name);
440: printf ("\t\tlast_op_for_exception_3 = opcode;\n");
441: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + %d;\n", m68k_pc_offset);
1.1.1.12 root 442: printf ("\t\tException(3, 0, M68000_EXC_SRC_CPU);\n");
1.1 root 443: printf ("\t\tgoto %s;\n", endlabelstr);
444: printf ("\t}\n");
445: need_endlabel = 1;
446: start_brace ();
447: }
448:
449: if (getv == 1) {
450: switch (size) {
451: case sz_byte: insn_n_cycles += 4; break;
452: case sz_word: insn_n_cycles += 4; break;
453: case sz_long: insn_n_cycles += 8; break;
454: default: abort ();
455: }
456: start_brace ();
457: switch (size) {
458: case sz_byte: printf ("\tuae_s8 %s = get_byte(%sa);\n", name, name); break;
459: case sz_word: printf ("\tuae_s16 %s = get_word(%sa);\n", name, name); break;
460: case sz_long: printf ("\tuae_s32 %s = get_long(%sa);\n", name, name); break;
461: default: abort ();
462: }
463: }
464:
465: /* We now might have to fix up the register for pre-dec or post-inc
466: * addressing modes. */
467: if (!movem)
468: switch (mode) {
469: case Aipi:
470: switch (size) {
471: case sz_byte:
472: printf ("\tm68k_areg(regs, %s) += areg_byteinc[%s];\n", reg, reg);
473: break;
474: case sz_word:
475: printf ("\tm68k_areg(regs, %s) += 2;\n", reg);
476: break;
477: case sz_long:
478: printf ("\tm68k_areg(regs, %s) += 4;\n", reg);
479: break;
480: default:
481: abort ();
482: }
483: break;
484: case Apdi:
485: printf ("\tm68k_areg (regs, %s) = %sa;\n", reg, name);
486: break;
487: default:
488: break;
489: }
490: }
491:
1.1.1.12 root 492: static void genastore (const char *from, amodes mode, const char *reg,
493: wordsizes size, const char *to)
1.1 root 494: {
495: switch (mode) {
496: case Dreg:
497: switch (size) {
498: case sz_byte:
499: printf ("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from);
500: break;
501: case sz_word:
502: printf ("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from);
503: break;
504: case sz_long:
505: printf ("\tm68k_dreg(regs, %s) = (%s);\n", reg, from);
506: break;
507: default:
508: abort ();
509: }
510: break;
511: case Areg:
512: switch (size) {
513: case sz_word:
514: fprintf (stderr, "Foo\n");
515: printf ("\tm68k_areg(regs, %s) = (uae_s32)(uae_s16)(%s);\n", reg, from);
516: break;
517: case sz_long:
518: printf ("\tm68k_areg(regs, %s) = (%s);\n", reg, from);
519: break;
520: default:
521: abort ();
522: }
523: break;
524: case Aind:
525: case Aipi:
526: case Apdi:
527: case Ad16:
528: case Ad8r:
529: case absw:
530: case absl:
531: case PC16:
532: case PC8r:
533: if (using_prefetch)
534: sync_m68k_pc ();
535: switch (size) {
536: case sz_byte:
537: insn_n_cycles += 4;
538: printf ("\tput_byte(%sa,%s);\n", to, from);
539: break;
540: case sz_word:
541: insn_n_cycles += 4;
542: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
543: abort ();
544: printf ("\tput_word(%sa,%s);\n", to, from);
545: break;
546: case sz_long:
547: insn_n_cycles += 8;
548: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
549: abort ();
550: printf ("\tput_long(%sa,%s);\n", to, from);
551: break;
552: default:
553: abort ();
554: }
555: break;
556: case imm:
557: case imm0:
558: case imm1:
559: case imm2:
560: case immi:
561: abort ();
562: break;
563: default:
564: abort ();
565: }
566: }
567:
1.1.1.2 root 568:
1.1 root 569: static void genmovemel (uae_u16 opcode)
570: {
571: char getcode[100];
1.1.1.3 root 572: int bMovemLong = (table68k[opcode].size == sz_long);
573: int size = bMovemLong ? 4 : 2;
1.1 root 574:
1.1.1.3 root 575: if (bMovemLong) {
1.1 root 576: strcpy (getcode, "get_long(srca)");
577: } else {
578: strcpy (getcode, "(uae_s32)(uae_s16)get_word(srca)");
579: }
580:
581: printf ("\tuae_u16 mask = %s;\n", gen_nextiword ());
582: printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1.1.1.2 root 583: printf ("\tretcycles = 0;\n");
1.1.1.3 root 584: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1);
1.1 root 585: start_brace ();
1.1.1.2 root 586: printf ("\twhile (dmask) { m68k_dreg(regs, movem_index1[dmask]) = %s;"
1.1.1.3 root 587: " srca += %d; dmask = movem_next[dmask]; retcycles+=%d; }\n",
588: getcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 589: printf ("\twhile (amask) { m68k_areg(regs, movem_index1[amask]) = %s;"
1.1.1.3 root 590: " srca += %d; amask = movem_next[amask]; retcycles+=%d; }\n",
591: getcode, size, (bMovemLong ? 8 : 4));
1.1 root 592:
593: if (table68k[opcode].dmode == Aipi)
594: printf ("\tm68k_areg(regs, dstreg) = srca;\n");
1.1.1.2 root 595:
596: /* Better cycles - experimental! (Thothy) */
597: switch(table68k[opcode].dmode)
1.1.1.3 root 598: {
1.1.1.2 root 599: case Aind: insn_n_cycles=12; break;
600: case Aipi: insn_n_cycles=12; break;
601: case Ad16: insn_n_cycles=16; break;
602: case Ad8r: insn_n_cycles=18; break;
603: case absw: insn_n_cycles=16; break;
604: case absl: insn_n_cycles=20; break;
605: case PC16: insn_n_cycles=16; break;
606: case PC8r: insn_n_cycles=18; break;
1.1.1.3 root 607: }
608: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 609: }
610:
611: static void genmovemle (uae_u16 opcode)
612: {
613: char putcode[100];
1.1.1.3 root 614: int bMovemLong = (table68k[opcode].size == sz_long);
615: int size = bMovemLong ? 4 : 2;
616:
617: if (bMovemLong) {
1.1 root 618: strcpy (putcode, "put_long(srca,");
619: } else {
620: strcpy (putcode, "put_word(srca,");
621: }
622:
623: printf ("\tuae_u16 mask = %s;\n", gen_nextiword ());
1.1.1.3 root 624: printf ("\tretcycles = 0;\n");
1.1 root 625: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1);
626: if (using_prefetch)
627: sync_m68k_pc ();
628:
629: start_brace ();
630: if (table68k[opcode].dmode == Apdi) {
1.1.1.2 root 631: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
632: printf ("\twhile (amask) { srca -= %d; %s m68k_areg(regs, movem_index2[amask]));"
1.1.1.3 root 633: " amask = movem_next[amask]; retcycles+=%d; }\n",
634: size, putcode, (bMovemLong ? 8 : 4));
1.1.1.2 root 635: printf ("\twhile (dmask) { srca -= %d; %s m68k_dreg(regs, movem_index2[dmask]));"
1.1.1.3 root 636: " dmask = movem_next[dmask]; retcycles+=%d; }\n",
637: size, putcode, (bMovemLong ? 8 : 4));
1.1.1.2 root 638: printf ("\tm68k_areg(regs, dstreg) = srca;\n");
1.1 root 639: } else {
1.1.1.2 root 640: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
641: printf ("\twhile (dmask) { %s m68k_dreg(regs, movem_index1[dmask])); srca += %d;"
1.1.1.3 root 642: " dmask = movem_next[dmask]; retcycles+=%d; }\n",
643: putcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 644: printf ("\twhile (amask) { %s m68k_areg(regs, movem_index1[amask])); srca += %d;"
1.1.1.3 root 645: " amask = movem_next[amask]; retcycles+=%d; }\n",
646: putcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 647: }
648:
649: /* Better cycles - experimental! (Thothy) */
650: switch(table68k[opcode].dmode)
1.1.1.3 root 651: {
1.1.1.2 root 652: case Aind: insn_n_cycles=8; break;
653: case Apdi: insn_n_cycles=8; break;
654: case Ad16: insn_n_cycles=12; break;
655: case Ad8r: insn_n_cycles=14; break;
656: case absw: insn_n_cycles=12; break;
657: case absl: insn_n_cycles=16; break;
1.1.1.3 root 658: }
659: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 660: }
661:
1.1.1.2 root 662:
1.1 root 663: static void duplicate_carry (void)
664: {
665: printf ("\tCOPY_CARRY;\n");
666: }
667:
668: typedef enum
669: {
670: flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_zn,
671: flag_av, flag_sv
672: }
673: flagtypes;
674:
1.1.1.12 root 675: static void genflags_normal (flagtypes type, wordsizes size, const char *value,
676: const char *src, const char *dst)
1.1 root 677: {
678: char vstr[100], sstr[100], dstr[100];
679: char usstr[100], udstr[100];
680: char unsstr[100], undstr[100];
681:
682: switch (size) {
683: case sz_byte:
684: strcpy (vstr, "((uae_s8)(");
685: strcpy (usstr, "((uae_u8)(");
686: break;
687: case sz_word:
688: strcpy (vstr, "((uae_s16)(");
689: strcpy (usstr, "((uae_u16)(");
690: break;
691: case sz_long:
692: strcpy (vstr, "((uae_s32)(");
693: strcpy (usstr, "((uae_u32)(");
694: break;
695: default:
696: abort ();
697: }
698: strcpy (unsstr, usstr);
699:
700: strcpy (sstr, vstr);
701: strcpy (dstr, vstr);
702: strcat (vstr, value);
703: strcat (vstr, "))");
704: strcat (dstr, dst);
705: strcat (dstr, "))");
706: strcat (sstr, src);
707: strcat (sstr, "))");
708:
709: strcpy (udstr, usstr);
710: strcat (udstr, dst);
711: strcat (udstr, "))");
712: strcat (usstr, src);
713: strcat (usstr, "))");
714:
715: strcpy (undstr, unsstr);
716: strcat (unsstr, "-");
717: strcat (undstr, "~");
718: strcat (undstr, dst);
719: strcat (undstr, "))");
720: strcat (unsstr, src);
721: strcat (unsstr, "))");
722:
723: switch (type) {
724: case flag_logical_noclobber:
725: case flag_logical:
726: case flag_zn:
727: case flag_av:
728: case flag_sv:
729: case flag_addx:
730: case flag_subx:
731: break;
732:
733: case flag_add:
734: start_brace ();
735: printf ("uae_u32 %s = %s + %s;\n", value, dstr, sstr);
736: break;
737: case flag_sub:
738: case flag_cmp:
739: start_brace ();
740: printf ("uae_u32 %s = %s - %s;\n", value, dstr, sstr);
741: break;
742: }
743:
744: switch (type) {
745: case flag_logical_noclobber:
746: case flag_logical:
747: case flag_zn:
748: break;
749:
750: case flag_add:
751: case flag_sub:
752: case flag_addx:
753: case flag_subx:
754: case flag_cmp:
755: case flag_av:
756: case flag_sv:
757: start_brace ();
758: printf ("\t" BOOL_TYPE " flgs = %s < 0;\n", sstr);
759: printf ("\t" BOOL_TYPE " flgo = %s < 0;\n", dstr);
760: printf ("\t" BOOL_TYPE " flgn = %s < 0;\n", vstr);
761: break;
762: }
763:
764: switch (type) {
765: case flag_logical:
766: printf ("\tCLEAR_CZNV;\n");
767: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
768: printf ("\tSET_NFLG (%s < 0);\n", vstr);
769: break;
770: case flag_logical_noclobber:
771: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
772: printf ("\tSET_NFLG (%s < 0);\n", vstr);
773: break;
774: case flag_av:
775: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
776: break;
777: case flag_sv:
778: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
779: break;
780: case flag_zn:
781: printf ("\tSET_ZFLG (GET_ZFLG & (%s == 0));\n", vstr);
782: printf ("\tSET_NFLG (%s < 0);\n", vstr);
783: break;
784: case flag_add:
785: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
786: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
787: printf ("\tSET_CFLG (%s < %s);\n", undstr, usstr);
788: duplicate_carry ();
789: printf ("\tSET_NFLG (flgn != 0);\n");
790: break;
791: case flag_sub:
792: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
793: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
794: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
795: duplicate_carry ();
796: printf ("\tSET_NFLG (flgn != 0);\n");
797: break;
798: case flag_addx:
799: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n"); /* minterm SON: 0x42 */
800: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));\n"); /* minterm SON: 0xD4 */
801: duplicate_carry ();
802: break;
803: case flag_subx:
804: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));\n"); /* minterm SON: 0x24 */
805: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));\n"); /* minterm SON: 0xB2 */
806: duplicate_carry ();
807: break;
808: case flag_cmp:
809: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
810: printf ("\tSET_VFLG ((flgs != flgo) && (flgn != flgo));\n");
811: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
812: printf ("\tSET_NFLG (flgn != 0);\n");
813: break;
814: }
815: }
816:
1.1.1.12 root 817: static void genflags (flagtypes type, wordsizes size, const char *value,
818: const char *src, const char *dst)
1.1 root 819: {
820: /* Temporarily deleted 68k/ARM flag optimizations. I'd prefer to have
821: them in the appropriate m68k.h files and use just one copy of this
822: code here. The API can be changed if necessary. */
823: #ifdef OPTIMIZED_FLAGS
824: switch (type) {
825: case flag_add:
826: case flag_sub:
827: start_brace ();
828: printf ("\tuae_u32 %s;\n", value);
829: break;
830:
831: default:
832: break;
833: }
834:
835: /* At least some of those casts are fairly important! */
836: switch (type) {
837: case flag_logical_noclobber:
838: printf ("\t{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
839: if (strcmp (value, "0") == 0) {
840: printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n");
841: } else {
842: switch (size) {
843: case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
844: case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
845: case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
846: }
847: printf ("\tIOR_CZNV (oldcznv);\n");
848: }
849: printf ("\t}\n");
850: return;
851: case flag_logical:
852: if (strcmp (value, "0") == 0) {
853: printf ("\tSET_CZNV (FLAGVAL_Z);\n");
854: } else {
855: switch (size) {
856: case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
857: case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
858: case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
859: }
860: }
861: return;
862:
863: case flag_add:
864: switch (size) {
865: case sz_byte: printf ("\toptflag_addb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
866: case sz_word: printf ("\toptflag_addw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
867: case sz_long: printf ("\toptflag_addl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
868: }
869: return;
870:
871: case flag_sub:
872: switch (size) {
873: case sz_byte: printf ("\toptflag_subb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
874: case sz_word: printf ("\toptflag_subw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
875: case sz_long: printf ("\toptflag_subl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
876: }
877: return;
878:
879: case flag_cmp:
880: switch (size) {
881: case sz_byte: printf ("\toptflag_cmpb ((uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
882: case sz_word: printf ("\toptflag_cmpw ((uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
883: case sz_long: printf ("\toptflag_cmpl ((uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
884: }
885: return;
886:
887: default:
888: break;
889: }
890: #endif
891:
892: genflags_normal (type, size, value, src, dst);
893: }
894:
895: static void force_range_for_rox (const char *var, wordsizes size)
896: {
897: /* Could do a modulo operation here... which one is faster? */
898: switch (size) {
899: case sz_long:
900: printf ("\tif (%s >= 33) %s -= 33;\n", var, var);
901: break;
902: case sz_word:
903: printf ("\tif (%s >= 34) %s -= 34;\n", var, var);
904: printf ("\tif (%s >= 17) %s -= 17;\n", var, var);
905: break;
906: case sz_byte:
907: printf ("\tif (%s >= 36) %s -= 36;\n", var, var);
908: printf ("\tif (%s >= 18) %s -= 18;\n", var, var);
909: printf ("\tif (%s >= 9) %s -= 9;\n", var, var);
910: break;
911: }
912: }
913:
914: static const char *cmask (wordsizes size)
915: {
916: switch (size) {
917: case sz_byte: return "0x80";
918: case sz_word: return "0x8000";
919: case sz_long: return "0x80000000";
920: default: abort ();
921: }
922: }
923:
924: static int source_is_imm1_8 (struct instr *i)
925: {
926: return i->stype == 3;
927: }
928:
1.1.1.2 root 929:
930:
1.1 root 931: static void gen_opcode (unsigned long int opcode)
932: {
1.1.1.2 root 933: #if 0
934: char *amodenames[] = { "Dreg", "Areg", "Aind", "Aipi", "Apdi", "Ad16", "Ad8r",
935: "absw", "absl", "PC16", "PC8r", "imm", "imm0", "imm1", "imm2", "immi", "am_unknown", "am_illg"};
936: #endif
937:
1.1 root 938: struct instr *curi = table68k + opcode;
939: insn_n_cycles = 4;
940:
1.1.1.8 root 941: /* Store the family of the instruction (used to check for pairing on ST)
942: * and leave some space for patching in the current cycles later */
943: printf ("\tOpcodeFamily = %d; CurrentInstrCycles = \n", curi->mnemo);
944: nCurInstrCycPos = ftell(stdout) - 5;
945:
1.1 root 946: start_brace ();
947: m68k_pc_offset = 2;
1.1.1.2 root 948:
1.1 root 949: switch (curi->plev) {
950: case 0: /* not privileged */
951: break;
952: case 1: /* unprivileged only on 68000 */
953: if (cpu_level == 0)
954: break;
955: if (next_cpu_level < 0)
956: next_cpu_level = 0;
957:
958: /* fall through */
959: case 2: /* priviledged */
1.1.1.12 root 960: printf ("if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 961: need_endlabel = 1;
962: start_brace ();
963: break;
964: case 3: /* privileged if size == word */
965: if (curi->size == sz_byte)
966: break;
1.1.1.12 root 967: printf ("if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 968: need_endlabel = 1;
969: start_brace ();
970: break;
971: }
1.1.1.2 root 972:
973: /* Build the opcodes: */
1.1 root 974: switch (curi->mnemo) {
975: case i_OR:
976: case i_AND:
977: case i_EOR:
1.1.1.2 root 978: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
979: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
980: printf ("\tsrc %c= dst;\n", curi->mnemo == i_OR ? '|' : curi->mnemo == i_AND ? '&' : '^');
1.1.1.17! root 981:
! 982: if ( ( curi->smode == Dreg ) && ( curi->dmode == absl ) ) // FIXME [NP] eor.x Dn,xxxx.l (Xenon 2 : eor.w d0,$40760)
! 983: printf("\trefill_prefetch (m68k_getpc(), 6);\n"); // FIXME [NP] need better prefetch emulation
! 984: else
! 985: printf("\trefill_prefetch (m68k_getpc(), 2);\n"); // FIXME [NP] eor.w d0,(a2)+ (Operation Clean Streets - Automation 168, need better prefetch emulation)
1.1.1.2 root 986: genflags (flag_logical, curi->size, "src", "", "");
987: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
988: if(curi->size==sz_long && curi->dmode==Dreg)
989: {
990: insn_n_cycles += 2;
991: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
992: insn_n_cycles += 2;
993: }
994: #if 0
995: /* Output the CPU cycles: */
996: fprintf(stderr,"MOVE, size %i: ",curi->size);
997: fprintf(stderr," %s ->",amodenames[curi->smode]);
998: fprintf(stderr," %s ",amodenames[curi->dmode]);
999: fprintf(stderr," Cycles: %i\n",insn_n_cycles);
1000: #endif
1001: break;
1.1 root 1002: case i_ORSR:
1003: case i_EORSR:
1.1.1.2 root 1004: printf ("\tMakeSR();\n");
1005: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1006: if (curi->size == sz_byte) {
1007: printf ("\tsrc &= 0xFF;\n");
1008: }
1009: printf ("\tregs.sr %c= src;\n", curi->mnemo == i_EORSR ? '^' : '|');
1010: printf ("\tMakeFromSR();\n");
1011: insn_n_cycles = 20;
1012: break;
1.1 root 1013: case i_ANDSR:
1.1.1.2 root 1014: printf ("\tMakeSR();\n");
1015: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1016: if (curi->size == sz_byte) {
1017: printf ("\tsrc |= 0xFF00;\n");
1018: }
1019: printf ("\tregs.sr &= src;\n");
1020: printf ("\tMakeFromSR();\n");
1021: insn_n_cycles = 20;
1022: break;
1.1 root 1023: case i_SUB:
1024: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1025: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1026: start_brace ();
1.1.1.17! root 1027: printf("\trefill_prefetch (m68k_getpc(), 2);\n"); // FIXME [NP] similar to i_ADD, need better prefetch emulation
1.1 root 1028: genflags (flag_sub, curi->size, "newv", "src", "dst");
1029: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1030: if(curi->size==sz_long && curi->dmode==Dreg)
1031: {
1032: insn_n_cycles += 2;
1033: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
1034: insn_n_cycles += 2;
1035: }
1.1 root 1036: break;
1037: case i_SUBA:
1038: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1039: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1040: start_brace ();
1041: printf ("\tuae_u32 newv = dst - src;\n");
1042: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.2 root 1043: if(curi->size==sz_long && curi->smode!=Dreg && curi->smode!=Areg && !(curi->smode>=imm && curi->smode<=immi))
1044: insn_n_cycles += 2;
1045: else
1046: insn_n_cycles += 4;
1.1 root 1047: break;
1048: case i_SUBX:
1049: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1050: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1051: start_brace ();
1052: printf ("\tuae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);\n");
1053: genflags (flag_subx, curi->size, "newv", "src", "dst");
1054: genflags (flag_zn, curi->size, "newv", "", "");
1055: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1056: if(curi->smode==Dreg && curi->size==sz_long)
1057: insn_n_cycles=8;
1058: if(curi->smode==Apdi)
1059: {
1060: if(curi->size==sz_long)
1061: insn_n_cycles=30;
1062: else
1063: insn_n_cycles=18;
1064: }
1.1 root 1065: break;
1066: case i_SBCD:
1067: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1068: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1069: start_brace ();
1070: printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
1071: printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
1.1.1.4 root 1072: printf ("\tuae_u16 newv, tmp_newv;\n");
1073: printf ("\tint bcd = 0;\n");
1074: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
1075: printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
1076: printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
1077: printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);\n");
1.1 root 1078: duplicate_carry ();
1079: genflags (flag_zn, curi->size, "newv", "", "");
1.1.1.4 root 1080: printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
1.1 root 1081: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.4 root 1082: if(curi->smode==Dreg) insn_n_cycles=6;
1083: if(curi->smode==Apdi) insn_n_cycles=18;
1.1 root 1084: break;
1085: case i_ADD:
1086: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1087: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1088: start_brace ();
1.1.1.8 root 1089: printf("\trefill_prefetch (m68k_getpc(), 2);\n"); // FIXME [NP] For Transbeauce 2 demo, need better prefetch emulation
1.1 root 1090: genflags (flag_add, curi->size, "newv", "src", "dst");
1091: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1092: if(curi->size==sz_long && curi->dmode==Dreg)
1093: {
1094: insn_n_cycles += 2;
1095: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
1096: insn_n_cycles += 2;
1097: }
1.1 root 1098: break;
1099: case i_ADDA:
1100: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1101: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1102: start_brace ();
1103: printf ("\tuae_u32 newv = dst + src;\n");
1104: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.2 root 1105: if(curi->size==sz_long && curi->smode!=Dreg && curi->smode!=Areg && !(curi->smode>=imm && curi->smode<=immi))
1106: insn_n_cycles += 2;
1107: else
1108: insn_n_cycles += 4;
1.1 root 1109: break;
1110: case i_ADDX:
1111: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1112: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1113: start_brace ();
1114: printf ("\tuae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);\n");
1115: genflags (flag_addx, curi->size, "newv", "src", "dst");
1116: genflags (flag_zn, curi->size, "newv", "", "");
1117: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1118: if(curi->smode==Dreg && curi->size==sz_long)
1119: insn_n_cycles=8;
1120: if(curi->smode==Apdi)
1121: {
1122: if(curi->size==sz_long)
1123: insn_n_cycles=30;
1124: else
1125: insn_n_cycles=18;
1126: }
1.1 root 1127: break;
1128: case i_ABCD:
1129: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1130: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1131: start_brace ();
1132: printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);\n");
1133: printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
1.1.1.4 root 1134: printf ("\tuae_u16 newv, tmp_newv;\n");
1.1 root 1135: printf ("\tint cflg;\n");
1.1.1.4 root 1136: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;");
1137: printf ("\tif (newv_lo > 9) { newv += 6; }\n");
1138: printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
1139: printf ("\tif (cflg) newv += 0x60;\n");
1.1 root 1140: printf ("\tSET_CFLG (cflg);\n");
1141: duplicate_carry ();
1142: genflags (flag_zn, curi->size, "newv", "", "");
1.1.1.4 root 1143: printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
1.1 root 1144: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.4 root 1145: if(curi->smode==Dreg) insn_n_cycles=6;
1146: if(curi->smode==Apdi) insn_n_cycles=18;
1.1 root 1147: break;
1148: case i_NEG:
1149: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1150: start_brace ();
1.1.1.17! root 1151: printf("\trefill_prefetch (m68k_getpc(), 2);\n"); // FIXME [NP] similar to i_ADD/i_EOR, need better prefetch emulation
1.1 root 1152: genflags (flag_sub, curi->size, "dst", "src", "0");
1153: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1154: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1155: break;
1156: case i_NEGX:
1157: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1158: start_brace ();
1.1.1.17! root 1159: printf("\trefill_prefetch (m68k_getpc(), 2);\n"); // FIXME [NP] similar to i_ADD/i_EOR, need better prefetch emulation
1.1 root 1160: printf ("\tuae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);\n");
1161: genflags (flag_subx, curi->size, "newv", "src", "0");
1162: genflags (flag_zn, curi->size, "newv", "", "");
1163: genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1164: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1165: break;
1166: case i_NBCD:
1167: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1168: start_brace ();
1169: printf ("\tuae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
1170: printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
1171: printf ("\tuae_u16 newv;\n");
1172: printf ("\tint cflg;\n");
1.1.1.4 root 1173: printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
1174: printf ("\tnewv = newv_hi + newv_lo;");
1175: printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
1176: printf ("\tif (cflg) newv -= 0x60;\n");
1.1 root 1177: printf ("\tSET_CFLG (cflg);\n");
1178: duplicate_carry();
1179: genflags (flag_zn, curi->size, "newv", "", "");
1180: genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1.1.1.4 root 1181: if(curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1182: break;
1183: case i_CLR:
1184: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1.1.1.8 root 1185:
1186: /* [NP] CLR does a read before the write only on 68000 */
1187: /* but there's no cycle penalty for doing the read */
1188: if ( curi->smode != Dreg ) // only if destination is memory
1189: {
1190: if (curi->size==sz_byte)
1191: printf ("\tuae_s8 src = get_byte(srca);\n");
1192: else if (curi->size==sz_word)
1193: printf ("\tuae_s16 src = get_word(srca);\n");
1194: else if (curi->size==sz_long)
1195: printf ("\tuae_s32 src = get_long(srca);\n");
1196: }
1197:
1.1 root 1198: genflags (flag_logical, curi->size, "0", "", "");
1199: genastore ("0", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1200: if(curi->size==sz_long)
1.1.1.3 root 1201: {
1.1.1.2 root 1202: if(curi->smode==Dreg)
1203: insn_n_cycles += 2;
1204: else
1205: insn_n_cycles += 4;
1.1.1.3 root 1206: }
1.1.1.2 root 1207: if(curi->smode!=Dreg)
1208: insn_n_cycles += 4;
1.1 root 1209: break;
1210: case i_NOT:
1211: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1212: start_brace ();
1.1.1.17! root 1213: printf("\trefill_prefetch (m68k_getpc(), 2);\n"); // FIXME [NP] similar to i_ADD/i_EOR, need better prefetch emulation
1.1 root 1214: printf ("\tuae_u32 dst = ~src;\n");
1215: genflags (flag_logical, curi->size, "dst", "", "");
1216: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1217: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1218: break;
1219: case i_TST:
1220: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1221: genflags (flag_logical, curi->size, "src", "", "");
1222: break;
1223: case i_BTST:
1224: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1225: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1226: if (curi->size == sz_byte)
1227: printf ("\tsrc &= 7;\n");
1228: else
1229: printf ("\tsrc &= 31;\n");
1230: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1.1.1.2 root 1231: if(curi->dmode==Dreg) insn_n_cycles += 2;
1.1 root 1232: break;
1233: case i_BCHG:
1234: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1235: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1236: if (curi->size == sz_byte)
1237: printf ("\tsrc &= 7;\n");
1238: else
1239: printf ("\tsrc &= 31;\n");
1240: printf ("\tdst ^= (1 << src);\n");
1241: printf ("\tSET_ZFLG (((uae_u32)dst & (1 << src)) >> src);\n");
1242: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1243: if(curi->dmode==Dreg) insn_n_cycles += 4;
1.1 root 1244: break;
1245: case i_BCLR:
1246: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1247: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1248: if (curi->size == sz_byte)
1249: printf ("\tsrc &= 7;\n");
1250: else
1251: printf ("\tsrc &= 31;\n");
1252: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1253: printf ("\tdst &= ~(1 << src);\n");
1254: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1255: if(curi->dmode==Dreg) insn_n_cycles += 6;
1.1.1.8 root 1256: /* [NP] BCLR #n,Dx takes 12 cycles instead of 14 if n<16 */
1257: if((curi->smode==imm1) && (curi->dmode==Dreg))
1258: printf ("\tif ( src < 16 ) { m68k_incpc(4); return 12; }\n");
1259: /* [NP] BCLR Dy,Dx takes 8 cycles instead of 10 if Dy<16 */
1260: if((curi->smode==Dreg) && (curi->dmode==Dreg))
1261: printf ("\tif ( src < 16 ) { m68k_incpc(2); return 8; }\n");
1.1 root 1262: break;
1263: case i_BSET:
1264: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1265: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1266: if (curi->size == sz_byte)
1267: printf ("\tsrc &= 7;\n");
1268: else
1269: printf ("\tsrc &= 31;\n");
1270: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1271: printf ("\tdst |= (1 << src);\n");
1272: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1273: if(curi->dmode==Dreg) insn_n_cycles += 4;
1.1 root 1274: break;
1275: case i_CMPM:
1276: case i_CMP:
1277: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1278: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1279: start_brace ();
1280: genflags (flag_cmp, curi->size, "newv", "src", "dst");
1.1.1.2 root 1281: if(curi->size==sz_long && curi->dmode==Dreg)
1282: insn_n_cycles += 2;
1.1 root 1283: break;
1284: case i_CMPA:
1285: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1286: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1287: start_brace ();
1288: genflags (flag_cmp, sz_long, "newv", "src", "dst");
1.1.1.2 root 1289: insn_n_cycles += 2;
1.1 root 1290: break;
1291: /* The next two are coded a little unconventional, but they are doing
1292: * weird things... */
1293: case i_MVPRM:
1294: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1295:
1296: printf ("\tuaecptr memp = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword ());
1.1.1.16 root 1297: /* [NP] Use MovepByteNbr to keep track of each access inside a movep */
1.1 root 1298: if (curi->size == sz_word) {
1.1.1.14 root 1299: printf ("\tMovepByteNbr=1; put_byte(memp, src >> 8); MovepByteNbr=2; put_byte(memp + 2, src);\n");
1.1 root 1300: } else {
1.1.1.14 root 1301: printf ("\tMovepByteNbr=1; put_byte(memp, src >> 24); MovepByteNbr=2; put_byte(memp + 2, src >> 16);\n");
1302: printf ("\tMovepByteNbr=3; put_byte(memp + 4, src >> 8); MovepByteNbr=4; put_byte(memp + 6, src);\n");
1.1 root 1303: }
1.1.1.16 root 1304: printf ("\tMovepByteNbr=0;\n");
1.1.1.2 root 1305: if(curi->size==sz_long) insn_n_cycles=24; else insn_n_cycles=16;
1.1 root 1306: break;
1307: case i_MVPMR:
1308: printf ("\tuaecptr memp = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword ());
1309: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1.1.1.16 root 1310: /* [NP] Use MovepByteNbr to keep track of each access inside a movep */
1.1 root 1311: if (curi->size == sz_word) {
1.1.1.16 root 1312: //printf ("\tuae_u16 val = (get_byte(memp) << 8) + get_byte(memp + 2);\n");
1313: printf ("\tuae_u16 val;\n");
1314: printf ("\tMovepByteNbr=1; val = (get_byte(memp) << 8);\n");
1315: printf ("\tMovepByteNbr=2; val += get_byte(memp + 2);\n");
1.1 root 1316: } else {
1.1.1.16 root 1317: //printf ("\tuae_u32 val = (get_byte(memp) << 24) + (get_byte(memp + 2) << 16)\n");
1318: //printf (" + (get_byte(memp + 4) << 8) + get_byte(memp + 6);\n");
1319: printf ("\tuae_u32 val;\n");
1320: printf ("\tMovepByteNbr=1; val = (get_byte(memp) << 24);\n");
1321: printf ("\tMovepByteNbr=2; val += (get_byte(memp + 2) << 16);\n");
1322: printf ("\tMovepByteNbr=3; val += (get_byte(memp + 4) << 8);\n");
1323: printf ("\tMovepByteNbr=4; val += get_byte(memp + 6);\n");
1.1 root 1324: }
1.1.1.16 root 1325: printf ("\tMovepByteNbr=0;\n");
1.1 root 1326: genastore ("val", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1327: if(curi->size==sz_long) insn_n_cycles=24; else insn_n_cycles=16;
1.1 root 1328: break;
1329: case i_MOVE:
1330: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1331: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1.1.1.8 root 1332:
1333: /* [NP] genamode counts 2 cycles if dest is -(An), this is wrong. */
1334: /* For move dest (An), (An)+ and -(An) take the same time */
1335: /* (for other instr, dest -(An) really takes 2 cycles more) */
1336: if ( curi->dmode == Apdi )
1337: insn_n_cycles -= 2; /* correct the wrong cycle count for -(An) */
1338:
1.1.1.17! root 1339: if ( ( curi->smode == Dreg ) && ( curi->dmode == absl ) ) // FIXME [NP] move.x Dn,xxxx.l (Union Demo : move.w d1,$4c)
! 1340: // FIXME [NP] move.x Dn,xxxx.l (Darkman : move.w d2,$2c04)
! 1341: printf("\trefill_prefetch (m68k_getpc(), 4);\n"); // FIXME [NP] need better prefetch emulation
! 1342:
! 1343: else if ( (curi->size==sz_long) && ( curi->smode == imm ) && ( curi->dmode == Aind ) ) // FIXME [NP] move.l #$xxxx,(An) (Titan : move.l #$b0b0caca,(a4))
! 1344: printf("\trefill_prefetch (m68k_getpc(), 4);\n"); // FIXME [NP] need better prefetch emulation
! 1345:
! 1346: else if ( (curi->size==sz_long) && ( curi->smode == Dreg ) && ( curi->dmode == Aind ) ) // FIXME [NP] move.l Dn,(An) (Int 3D Tennis : move.l d0,(a0))
! 1347: printf("\trefill_prefetch (m68k_getpc(), 0);\n"); // FIXME [NP] need better prefetch emulation
! 1348:
1.1 root 1349: genflags (flag_logical, curi->size, "src", "", "");
1350: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
1351: break;
1352: case i_MOVEA:
1353: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1354: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1355: if (curi->size == sz_word) {
1356: printf ("\tuae_u32 val = (uae_s32)(uae_s16)src;\n");
1357: } else {
1358: printf ("\tuae_u32 val = src;\n");
1359: }
1360: genastore ("val", curi->dmode, "dstreg", sz_long, "dst");
1361: break;
1.1.1.2 root 1362: case i_MVSR2: /* Move from SR */
1.1 root 1363: genamode (curi->smode, "srcreg", sz_word, "src", 2, 0);
1364: printf ("\tMakeSR();\n");
1365: if (curi->size == sz_byte)
1366: genastore ("regs.sr & 0xff", curi->smode, "srcreg", sz_word, "src");
1367: else
1368: genastore ("regs.sr", curi->smode, "srcreg", sz_word, "src");
1.1.1.2 root 1369: if (curi->smode==Dreg) insn_n_cycles += 2; else insn_n_cycles += 4;
1.1 root 1370: break;
1.1.1.2 root 1371: case i_MV2SR: /* Move to SR */
1.1 root 1372: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1373: if (curi->size == sz_byte)
1374: printf ("\tMakeSR();\n\tregs.sr &= 0xFF00;\n\tregs.sr |= src & 0xFF;\n");
1375: else {
1376: printf ("\tregs.sr = src;\n");
1377: }
1378: printf ("\tMakeFromSR();\n");
1.1.1.2 root 1379: insn_n_cycles += 8;
1.1 root 1380: break;
1381: case i_SWAP:
1382: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1383: start_brace ();
1384: printf ("\tuae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);\n");
1385: genflags (flag_logical, sz_long, "dst", "", "");
1386: genastore ("dst", curi->smode, "srcreg", sz_long, "src");
1387: break;
1388: case i_EXG:
1389: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1390: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1391: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1392: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1393: insn_n_cycles = 6;
1.1 root 1394: break;
1395: case i_EXT:
1396: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1397: start_brace ();
1398: switch (curi->size) {
1399: case sz_byte: printf ("\tuae_u32 dst = (uae_s32)(uae_s8)src;\n"); break;
1400: case sz_word: printf ("\tuae_u16 dst = (uae_s16)(uae_s8)src;\n"); break;
1401: case sz_long: printf ("\tuae_u32 dst = (uae_s32)(uae_s16)src;\n"); break;
1402: default: abort ();
1403: }
1404: genflags (flag_logical,
1405: curi->size == sz_word ? sz_word : sz_long, "dst", "", "");
1406: genastore ("dst", curi->smode, "srcreg",
1407: curi->size == sz_word ? sz_word : sz_long, "src");
1408: break;
1409: case i_MVMEL:
1410: genmovemel (opcode);
1411: break;
1412: case i_MVMLE:
1413: genmovemle (opcode);
1414: break;
1415: case i_TRAP:
1416: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1417: sync_m68k_pc ();
1.1.1.12 root 1418: printf ("\tException(src+32,0,M68000_EXC_SRC_CPU);\n");
1.1 root 1419: m68k_pc_offset = 0;
1420: break;
1421: case i_MVR2USP:
1422: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1423: printf ("\tregs.usp = src;\n");
1424: break;
1425: case i_MVUSP2R:
1426: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1427: genastore ("regs.usp", curi->smode, "srcreg", curi->size, "src");
1428: break;
1429: case i_RESET:
1430: printf ("\tcustomreset();\n");
1.1.1.2 root 1431: insn_n_cycles = 132; /* I am not so sure about this!? - Thothy */
1.1 root 1432: break;
1433: case i_NOP:
1434: break;
1435: case i_STOP:
1436: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1437: printf ("\tregs.sr = src;\n");
1438: printf ("\tMakeFromSR();\n");
1439: printf ("\tm68k_setstopped(1);\n");
1.1.1.2 root 1440: insn_n_cycles = 4;
1.1 root 1441: break;
1442: case i_RTE:
1443: if (cpu_level == 0) {
1444: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1445: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1446: printf ("\tregs.sr = sr; m68k_setpc_rte(pc);\n");
1447: fill_prefetch_0 ();
1448: printf ("\tMakeFromSR();\n");
1449: } else {
1450: int old_brace_level = n_braces;
1451: if (next_cpu_level < 0)
1452: next_cpu_level = 0;
1453: printf ("\tuae_u16 newsr; uae_u32 newpc; for (;;) {\n");
1454: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1455: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1456: genamode (Aipi, "7", sz_word, "format", 1, 0);
1457: printf ("\tnewsr = sr; newpc = pc;\n");
1458: printf ("\tif ((format & 0xF000) == 0x0000) { break; }\n");
1459: printf ("\telse if ((format & 0xF000) == 0x1000) { ; }\n");
1460: printf ("\telse if ((format & 0xF000) == 0x2000) { m68k_areg(regs, 7) += 4; break; }\n");
1461: printf ("\telse if ((format & 0xF000) == 0x8000) { m68k_areg(regs, 7) += 50; break; }\n");
1462: printf ("\telse if ((format & 0xF000) == 0x9000) { m68k_areg(regs, 7) += 12; break; }\n");
1463: printf ("\telse if ((format & 0xF000) == 0xa000) { m68k_areg(regs, 7) += 24; break; }\n");
1464: printf ("\telse if ((format & 0xF000) == 0xb000) { m68k_areg(regs, 7) += 84; break; }\n");
1.1.1.12 root 1465: printf ("\telse { Exception(14,0,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 1466: printf ("\tregs.sr = newsr; MakeFromSR();\n}\n");
1467: pop_braces (old_brace_level);
1468: printf ("\tregs.sr = newsr; MakeFromSR();\n");
1469: printf ("\tm68k_setpc_rte(newpc);\n");
1470: fill_prefetch_0 ();
1471: need_endlabel = 1;
1472: }
1473: /* PC is set and prefetch filled. */
1474: m68k_pc_offset = 0;
1.1.1.2 root 1475: insn_n_cycles = 20;
1.1 root 1476: break;
1477: case i_RTD:
1478: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1479: genamode (curi->smode, "srcreg", curi->size, "offs", 1, 0);
1480: printf ("\tm68k_areg(regs, 7) += offs;\n");
1481: printf ("\tm68k_setpc_rte(pc);\n");
1482: fill_prefetch_0 ();
1483: /* PC is set and prefetch filled. */
1484: m68k_pc_offset = 0;
1485: break;
1486: case i_LINK:
1487: genamode (Apdi, "7", sz_long, "old", 2, 0);
1488: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1489: genastore ("src", Apdi, "7", sz_long, "old");
1490: genastore ("m68k_areg(regs, 7)", curi->smode, "srcreg", sz_long, "src");
1491: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0);
1492: printf ("\tm68k_areg(regs, 7) += offs;\n");
1493: break;
1494: case i_UNLK:
1495: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1496: printf ("\tm68k_areg(regs, 7) = src;\n");
1497: genamode (Aipi, "7", sz_long, "old", 1, 0);
1498: genastore ("old", curi->smode, "srcreg", curi->size, "src");
1499: break;
1500: case i_RTS:
1501: printf ("\tm68k_do_rts();\n");
1502: fill_prefetch_0 ();
1503: m68k_pc_offset = 0;
1.1.1.2 root 1504: insn_n_cycles = 16;
1.1 root 1505: break;
1506: case i_TRAPV:
1507: sync_m68k_pc ();
1.1.1.12 root 1508: printf ("\tif (GET_VFLG) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 1509: need_endlabel = 1;
1510: break;
1511: case i_RTR:
1512: printf ("\tMakeSR();\n");
1513: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1514: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1515: printf ("\tregs.sr &= 0xFF00; sr &= 0xFF;\n");
1516: printf ("\tregs.sr |= sr; m68k_setpc(pc);\n");
1517: fill_prefetch_0 ();
1518: printf ("\tMakeFromSR();\n");
1519: m68k_pc_offset = 0;
1.1.1.2 root 1520: insn_n_cycles = 20;
1.1 root 1521: break;
1522: case i_JSR:
1523: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1.1.1.13 root 1524: printf ("\tuaecptr oldpc = m68k_getpc () + %d;\n", m68k_pc_offset);
1525: if (using_exception_3) {
1526: printf ("\tif (srca & 1) {\n");
1527: printf ("\t\tlast_addr_for_exception_3 = oldpc;\n");
1528: printf ("\t\tlast_fault_for_exception_3 = srca;\n");
1529: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
1530: printf ("\t}\n");
1531: need_endlabel = 1;
1532: }
1.1 root 1533: printf ("\tm68k_do_jsr(m68k_getpc() + %d, srca);\n", m68k_pc_offset);
1534: fill_prefetch_0 ();
1535: m68k_pc_offset = 0;
1.1.1.2 root 1536: switch(curi->smode)
1537: {
1538: case Aind: insn_n_cycles=16; break;
1539: case Ad16: insn_n_cycles=18; break;
1540: case Ad8r: insn_n_cycles=22; break;
1541: case absw: insn_n_cycles=18; break;
1542: case absl: insn_n_cycles=20; break;
1543: case PC16: insn_n_cycles=18; break;
1544: case PC8r: insn_n_cycles=22; break;
1545: }
1.1 root 1546: break;
1547: case i_JMP:
1548: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1.1.1.13 root 1549: if (using_exception_3) {
1550: printf ("\tif (srca & 1) {\n");
1.1.1.15 root 1551: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + %d;\n" , m68k_pc_offset); // [NP] last_addr is not pc+6
1.1.1.13 root 1552: printf ("\t\tlast_fault_for_exception_3 = srca;\n");
1553: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
1554: printf ("\t}\n");
1555: need_endlabel = 1;
1556: }
1.1 root 1557: printf ("\tm68k_setpc(srca);\n");
1558: fill_prefetch_0 ();
1559: m68k_pc_offset = 0;
1.1.1.2 root 1560: switch(curi->smode)
1561: {
1562: case Aind: insn_n_cycles=8; break;
1563: case Ad16: insn_n_cycles=10; break;
1564: case Ad8r: insn_n_cycles=14; break;
1565: case absw: insn_n_cycles=10; break;
1566: case absl: insn_n_cycles=12; break;
1567: case PC16: insn_n_cycles=10; break;
1568: case PC8r: insn_n_cycles=14; break;
1569: }
1.1 root 1570: break;
1571: case i_BSR:
1572: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1573: printf ("\tuae_s32 s = (uae_s32)src + 2;\n");
1574: if (using_exception_3) {
1575: printf ("\tif (src & 1) {\n");
1.1.1.13 root 1576: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n"); // [NP] FIXME should be +4, not +2 (same as DBcc) ?
1.1 root 1577: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + s;\n");
1.1.1.12 root 1578: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1579: printf ("\t}\n");
1580: need_endlabel = 1;
1581: }
1582: printf ("\tm68k_do_bsr(m68k_getpc() + %d, s);\n", m68k_pc_offset);
1583: fill_prefetch_0 ();
1584: m68k_pc_offset = 0;
1.1.1.2 root 1585: insn_n_cycles = 18;
1.1 root 1586: break;
1587: case i_Bcc:
1588: if (curi->size == sz_long) {
1589: if (cpu_level < 2) {
1590: printf ("\tm68k_incpc(2);\n");
1591: printf ("\tif (!cctrue(%d)) goto %s;\n", curi->cc, endlabelstr);
1592: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n");
1593: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + 1;\n");
1.1.1.12 root 1594: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1595: need_endlabel = 1;
1596: } else {
1597: if (next_cpu_level < 1)
1598: next_cpu_level = 1;
1599: }
1600: }
1601: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1602: printf ("\tif (!cctrue(%d)) goto didnt_jump;\n", curi->cc);
1603: if (using_exception_3) {
1604: printf ("\tif (src & 1) {\n");
1.1.1.8 root 1605: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n"); // [NP] FIXME should be +4, not +2 (same as DBcc) ?
1.1 root 1606: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;\n");
1.1.1.12 root 1607: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1608: printf ("\t}\n");
1609: need_endlabel = 1;
1610: }
1611: printf ("\tm68k_incpc ((uae_s32)src + 2);\n");
1612: fill_prefetch_0 ();
1.1.1.2 root 1613: printf ("\treturn 10;\n");
1.1 root 1614: printf ("didnt_jump:;\n");
1615: need_endlabel = 1;
1.1.1.2 root 1616: insn_n_cycles = (curi->size == sz_byte) ? 8 : 12;
1.1 root 1617: break;
1618: case i_LEA:
1619: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1620: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1621: genastore ("srca", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.7 root 1622: /* Set correct cycles: According to the M68K User Manual, LEA takes 12
1623: * cycles in Ad8r and PC8r mode, but it takes 14 (or 16) cycles on a real ST: */
1624: if (curi->smode == Ad8r || curi->smode == PC8r)
1625: insn_n_cycles = 14;
1.1 root 1626: break;
1627: case i_PEA:
1628: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1629: genamode (Apdi, "7", sz_long, "dst", 2, 0);
1630: genastore ("srca", Apdi, "7", sz_long, "dst");
1.1.1.7 root 1631: /* Set correct cycles: */
1.1.1.2 root 1632: switch(curi->smode)
1633: {
1634: case Aind: insn_n_cycles=12; break;
1635: case Ad16: insn_n_cycles=16; break;
1.1.1.7 root 1636: /* Note: according to the M68K User Manual, PEA takes 20 cycles for
1637: * the Ad8r mode, but on a real ST, it takes 22 (or 24) cycles! */
1638: case Ad8r: insn_n_cycles=22; break;
1.1.1.2 root 1639: case absw: insn_n_cycles=16; break;
1640: case absl: insn_n_cycles=20; break;
1641: case PC16: insn_n_cycles=16; break;
1.1.1.7 root 1642: /* Note: PEA with PC8r takes 20 cycles according to the User Manual,
1643: * but it takes 22 (or 24) cycles on a real ST: */
1644: case PC8r: insn_n_cycles=22; break;
1.1.1.2 root 1645: }
1.1 root 1646: break;
1647: case i_DBcc:
1648: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1649: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0);
1650:
1.1.1.2 root 1651: printf ("\tif (!cctrue(%d)) {\n\t", curi->cc);
1.1 root 1652: genastore ("(src-1)", curi->smode, "srcreg", curi->size, "src");
1653:
1654: printf ("\t\tif (src) {\n");
1655: if (using_exception_3) {
1656: printf ("\t\t\tif (offs & 1) {\n");
1.1.1.8 root 1657: printf ("\t\t\tlast_addr_for_exception_3 = m68k_getpc() + 2 + 2;\n"); // [NP] last_addr is pc+4, not pc+2
1.1 root 1658: printf ("\t\t\tlast_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;\n");
1.1.1.12 root 1659: printf ("\t\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1660: printf ("\t\t}\n");
1661: need_endlabel = 1;
1662: }
1663: printf ("\t\t\tm68k_incpc((uae_s32)offs + 2);\n");
1664: fill_prefetch_0 ();
1.1.1.2 root 1665: printf ("\t\t\treturn 10;\n");
1666: printf ("\t\t} else {\n\t\t\t");
1667: {
1668: int tmp_offset = m68k_pc_offset;
1669: sync_m68k_pc(); /* not so nice to call it here... */
1670: m68k_pc_offset = tmp_offset;
1671: }
1672: printf ("\t\t\treturn 14;\n");
1673: printf ("\t\t}\n");
1.1 root 1674: printf ("\t}\n");
1675: insn_n_cycles = 12;
1676: need_endlabel = 1;
1677: break;
1678: case i_Scc:
1679: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1.1.1.17! root 1680:
! 1681: /* [NP] Scc does a read before the write only on 68000 */
! 1682: /* but there's no cycle penalty for doing the read */
! 1683: if ( curi->smode != Dreg ) // only if destination is memory
! 1684: {
! 1685: if (curi->size==sz_byte)
! 1686: printf ("\tuae_s8 src = get_byte(srca);\n");
! 1687: else if (curi->size==sz_word)
! 1688: printf ("\tuae_s16 src = get_word(srca);\n");
! 1689: else if (curi->size==sz_long)
! 1690: printf ("\tuae_s32 src = get_long(srca);\n");
! 1691: }
! 1692:
1.1 root 1693: start_brace ();
1694: printf ("\tint val = cctrue(%d) ? 0xff : 0;\n", curi->cc);
1695: genastore ("val", curi->smode, "srcreg", curi->size, "src");
1.1.1.8 root 1696: if (curi->smode!=Dreg) insn_n_cycles += 4;
1697: else
1698: { /* [NP] if result is TRUE, we return 6 instead of 4 */
1699: printf ("\tif (val) { m68k_incpc(2) ; return 4+2; }\n");
1700: }
1.1 root 1701: break;
1702: case i_DIVU:
1703: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1704: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1705: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1706: sync_m68k_pc ();
1707: /* Clear V flag when dividing by zero - Alcatraz Odyssey demo depends
1708: * on this (actually, it's doing a DIVS). */
1.1.1.12 root 1709: printf ("\tif (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto %s; } else {\n", endlabelstr);
1.1 root 1710: printf ("\tuae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
1711: printf ("\tuae_u32 rem = (uae_u32)dst %% (uae_u32)(uae_u16)src;\n");
1712: /* The N flag appears to be set each time there is an overflow.
1713: * Weird. */
1714: printf ("\tif (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
1715: genflags (flag_logical, sz_word, "newv", "", "");
1716: printf ("\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
1717: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1718: printf ("\t}\n");
1719: printf ("\t}\n");
1.1.1.8 root 1720: // insn_n_cycles += 136;
1721: printf ("\tretcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);\n");
1722: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 1723: need_endlabel = 1;
1724: break;
1725: case i_DIVS:
1726: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1727: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1728: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1729: sync_m68k_pc ();
1.1.1.12 root 1730: printf ("\tif (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto %s; } else {\n", endlabelstr);
1.1 root 1731: printf ("\tuae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
1732: printf ("\tuae_u16 rem = (uae_s32)dst %% (uae_s32)(uae_s16)src;\n");
1733: printf ("\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
1734: printf ("\tif (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;\n");
1735: genflags (flag_logical, sz_word, "newv", "", "");
1736: printf ("\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
1737: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1738: printf ("\t}\n");
1739: printf ("\t}\n");
1.1.1.8 root 1740: // insn_n_cycles += 154;
1741: printf ("\tretcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);\n");
1742: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 1743: need_endlabel = 1;
1744: break;
1745: case i_MULU:
1746: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1747: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0);
1748: start_brace ();
1749: printf ("\tuae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;\n");
1750: genflags (flag_logical, sz_long, "newv", "", "");
1751: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.8 root 1752: /* [NP] number of cycles is 38 + 2n + ea time ; n is the number of 1 bits in src */
1753: insn_n_cycles += 38-4; /* insn_n_cycles is already initialized to 4 instead of 0 */
1754: printf ("\twhile (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }\n");
1755: sprintf(exactCpuCycles," return (%i+retcycles*2);", insn_n_cycles);
1.1 root 1756: break;
1757: case i_MULS:
1758: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1759: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0);
1760: start_brace ();
1761: printf ("\tuae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;\n");
1.1.1.8 root 1762: printf ("\tuae_u32 src2;\n");
1.1 root 1763: genflags (flag_logical, sz_long, "newv", "", "");
1764: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.8 root 1765: /* [NP] number of cycles is 38 + 2n + ea time ; n is the number of 01 or 10 patterns in src expanded to 17 bits */
1766: insn_n_cycles += 38-4; /* insn_n_cycles is already initialized to 4 instead of 0 */
1767: printf ("\tsrc2 = ((uae_u32)src) << 1;\n");
1768: printf ("\twhile (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }\n");
1769: sprintf(exactCpuCycles," return (%i+retcycles*2);", insn_n_cycles);
1.1 root 1770: break;
1771: case i_CHK:
1772: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1773: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1774: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1.1.1.8 root 1775: sync_m68k_pc ();
1.1.1.12 root 1776: printf ("\tif ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1777: printf ("\telse if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 1778: need_endlabel = 1;
1.1.1.2 root 1779: insn_n_cycles += 6;
1.1 root 1780: break;
1781:
1782: case i_CHK2:
1783: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1784: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
1785: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1786: printf ("\t{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];\n");
1787: switch (curi->size) {
1788: case sz_byte:
1789: printf ("\tlower=(uae_s32)(uae_s8)get_byte(dsta); upper = (uae_s32)(uae_s8)get_byte(dsta+1);\n");
1790: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;\n");
1791: break;
1792: case sz_word:
1793: printf ("\tlower=(uae_s32)(uae_s16)get_word(dsta); upper = (uae_s32)(uae_s16)get_word(dsta+2);\n");
1794: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;\n");
1795: break;
1796: case sz_long:
1797: printf ("\tlower=get_long(dsta); upper = get_long(dsta+4);\n");
1798: break;
1799: default:
1800: abort ();
1801: }
1802: printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
1803: printf ("\tSET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
1.1.1.8 root 1804: sync_m68k_pc ();
1.1.1.12 root 1805: printf ("\tif ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto %s; }\n}\n", endlabelstr);
1.1 root 1806: need_endlabel = 1;
1807: break;
1808:
1809: case i_ASR:
1810: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1811: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1812: start_brace ();
1813: switch (curi->size) {
1814: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1815: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1816: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1817: default: abort ();
1818: }
1819: printf ("\tuae_u32 sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1);
1820: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1821: printf ("\tretcycles = cnt;\n");
1.1 root 1822: printf ("\tCLEAR_CZNV;\n");
1823: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1824: printf ("\t\tval = %s & (uae_u32)-sign;\n", bit_mask (curi->size));
1825: printf ("\t\tSET_CFLG (sign);\n");
1826: duplicate_carry ();
1827: if (source_is_imm1_8 (curi))
1828: printf ("\t} else {\n");
1829: else
1830: printf ("\t} else if (cnt > 0) {\n");
1831: printf ("\t\tval >>= cnt - 1;\n");
1832: printf ("\t\tSET_CFLG (val & 1);\n");
1833: duplicate_carry ();
1834: printf ("\t\tval >>= 1;\n");
1835: printf ("\t\tval |= (%s << (%d - cnt)) & (uae_u32)-sign;\n",
1836: bit_mask (curi->size),
1837: bit_size (curi->size));
1838: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
1839: printf ("\t}\n");
1840: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1841: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1842: if(curi->size==sz_long)
1843: strcpy(exactCpuCycles," return (8+retcycles*2);");
1844: else
1845: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1846: break;
1847: case i_ASL:
1848: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1849: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1850: start_brace ();
1851: switch (curi->size) {
1852: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1853: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1854: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1855: default: abort ();
1856: }
1857: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1858: printf ("\tretcycles = cnt;\n");
1.1 root 1859: printf ("\tCLEAR_CZNV;\n");
1860: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1861: printf ("\t\tSET_VFLG (val != 0);\n");
1862: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
1863: bit_size (curi->size));
1864: duplicate_carry ();
1865: printf ("\t\tval = 0;\n");
1866: if (source_is_imm1_8 (curi))
1867: printf ("\t} else {\n");
1868: else
1869: printf ("\t} else if (cnt > 0) {\n");
1870: printf ("\t\tuae_u32 mask = (%s << (%d - cnt)) & %s;\n",
1871: bit_mask (curi->size),
1872: bit_size (curi->size) - 1,
1873: bit_mask (curi->size));
1874: printf ("\t\tSET_VFLG ((val & mask) != mask && (val & mask) != 0);\n");
1875: printf ("\t\tval <<= cnt - 1;\n");
1876: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
1877: duplicate_carry ();
1878: printf ("\t\tval <<= 1;\n");
1879: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
1880: printf ("\t}\n");
1881: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1882: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1883: if(curi->size==sz_long)
1884: strcpy(exactCpuCycles," return (8+retcycles*2);");
1885: else
1886: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1887: break;
1888: case i_LSR:
1889: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1890: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1891: start_brace ();
1892: switch (curi->size) {
1893: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1894: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1895: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1896: default: abort ();
1897: }
1898: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1899: printf ("\tretcycles = cnt;\n");
1.1 root 1900: printf ("\tCLEAR_CZNV;\n");
1901: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1902: printf ("\t\tSET_CFLG ((cnt == %d) & (val >> %d));\n",
1903: bit_size (curi->size), bit_size (curi->size) - 1);
1904: duplicate_carry ();
1905: printf ("\t\tval = 0;\n");
1906: if (source_is_imm1_8 (curi))
1907: printf ("\t} else {\n");
1908: else
1909: printf ("\t} else if (cnt > 0) {\n");
1910: printf ("\t\tval >>= cnt - 1;\n");
1911: printf ("\t\tSET_CFLG (val & 1);\n");
1912: duplicate_carry ();
1913: printf ("\t\tval >>= 1;\n");
1914: printf ("\t}\n");
1915: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1916: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1917: if(curi->size==sz_long)
1918: strcpy(exactCpuCycles," return (8+retcycles*2);");
1919: else
1920: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1921: break;
1922: case i_LSL:
1923: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1924: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1925: start_brace ();
1926: switch (curi->size) {
1927: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1928: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1929: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1930: default: abort ();
1931: }
1932: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1933: printf ("\tretcycles = cnt;\n");
1.1 root 1934: printf ("\tCLEAR_CZNV;\n");
1935: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1936: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
1937: bit_size (curi->size));
1938: duplicate_carry ();
1939: printf ("\t\tval = 0;\n");
1940: if (source_is_imm1_8 (curi))
1941: printf ("\t} else {\n");
1942: else
1943: printf ("\t} else if (cnt > 0) {\n");
1944: printf ("\t\tval <<= (cnt - 1);\n");
1945: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
1946: duplicate_carry ();
1947: printf ("\t\tval <<= 1;\n");
1948: printf ("\tval &= %s;\n", bit_mask (curi->size));
1949: printf ("\t}\n");
1950: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1951: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1952: if(curi->size==sz_long)
1953: strcpy(exactCpuCycles," return (8+retcycles*2);");
1954: else
1955: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1956: break;
1957: case i_ROL:
1958: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1959: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1960: start_brace ();
1961: switch (curi->size) {
1962: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1963: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1964: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1965: default: abort ();
1966: }
1967: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1968: printf ("\tretcycles = cnt;\n");
1.1 root 1969: printf ("\tCLEAR_CZNV;\n");
1970: if (source_is_imm1_8 (curi))
1971: printf ("{");
1972: else
1973: printf ("\tif (cnt > 0) {\n");
1974: printf ("\tuae_u32 loval;\n");
1975: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
1976: printf ("\tloval = val >> (%d - cnt);\n", bit_size (curi->size));
1977: printf ("\tval <<= cnt;\n");
1978: printf ("\tval |= loval;\n");
1979: printf ("\tval &= %s;\n", bit_mask (curi->size));
1980: printf ("\tSET_CFLG (val & 1);\n");
1981: printf ("}\n");
1982: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1983: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1984: if(curi->size==sz_long)
1985: strcpy(exactCpuCycles," return (8+retcycles*2);");
1986: else
1987: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1988: break;
1989: case i_ROR:
1990: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1991: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1992: start_brace ();
1993: switch (curi->size) {
1994: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1995: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1996: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1997: default: abort ();
1998: }
1999: printf ("\tcnt &= 63;\n");
1.1.1.2 root 2000: printf ("\tretcycles = cnt;\n");
1.1 root 2001: printf ("\tCLEAR_CZNV;\n");
2002: if (source_is_imm1_8 (curi))
2003: printf ("{");
2004: else
2005: printf ("\tif (cnt > 0) {");
2006: printf ("\tuae_u32 hival;\n");
2007: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
2008: printf ("\thival = val << (%d - cnt);\n", bit_size (curi->size));
2009: printf ("\tval >>= cnt;\n");
2010: printf ("\tval |= hival;\n");
2011: printf ("\tval &= %s;\n", bit_mask (curi->size));
2012: printf ("\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
2013: printf ("\t}\n");
2014: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2015: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 2016: if(curi->size==sz_long)
2017: strcpy(exactCpuCycles," return (8+retcycles*2);");
2018: else
2019: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 2020: break;
2021: case i_ROXL:
2022: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
2023: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
2024: start_brace ();
2025: switch (curi->size) {
2026: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2027: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2028: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2029: default: abort ();
2030: }
2031: printf ("\tcnt &= 63;\n");
1.1.1.2 root 2032: printf ("\tretcycles = cnt;\n");
1.1 root 2033: printf ("\tCLEAR_CZNV;\n");
2034: if (source_is_imm1_8 (curi))
2035: printf ("{");
2036: else {
2037: force_range_for_rox ("cnt", curi->size);
2038: printf ("\tif (cnt > 0) {\n");
2039: }
2040: printf ("\tcnt--;\n");
2041: printf ("\t{\n\tuae_u32 carry;\n");
2042: printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
2043: printf ("\tcarry = loval & 1;\n");
2044: printf ("\tval = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);\n");
2045: printf ("\tSET_XFLG (carry);\n");
2046: printf ("\tval &= %s;\n", bit_mask (curi->size));
2047: printf ("\t} }\n");
2048: printf ("\tSET_CFLG (GET_XFLG);\n");
2049: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2050: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 2051: if(curi->size==sz_long)
2052: strcpy(exactCpuCycles," return (8+retcycles*2);");
2053: else
2054: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 2055: break;
2056: case i_ROXR:
2057: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
2058: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
2059: start_brace ();
2060: switch (curi->size) {
2061: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2062: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2063: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2064: default: abort ();
2065: }
2066: printf ("\tcnt &= 63;\n");
1.1.1.2 root 2067: printf ("\tretcycles = cnt;\n");
1.1 root 2068: printf ("\tCLEAR_CZNV;\n");
2069: if (source_is_imm1_8 (curi))
2070: printf ("{");
2071: else {
2072: force_range_for_rox ("cnt", curi->size);
2073: printf ("\tif (cnt > 0) {\n");
2074: }
2075: printf ("\tcnt--;\n");
2076: printf ("\t{\n\tuae_u32 carry;\n");
2077: printf ("\tuae_u32 hival = (val << 1) | GET_XFLG;\n");
2078: printf ("\thival <<= (%d - cnt);\n", bit_size (curi->size) - 1);
2079: printf ("\tval >>= cnt;\n");
2080: printf ("\tcarry = val & 1;\n");
2081: printf ("\tval >>= 1;\n");
2082: printf ("\tval |= hival;\n");
2083: printf ("\tSET_XFLG (carry);\n");
2084: printf ("\tval &= %s;\n", bit_mask (curi->size));
2085: printf ("\t} }\n");
2086: printf ("\tSET_CFLG (GET_XFLG);\n");
2087: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2088: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 2089: if(curi->size==sz_long)
2090: strcpy(exactCpuCycles," return (8+retcycles*2);");
2091: else
2092: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 2093: break;
2094: case i_ASRW:
2095: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2096: start_brace ();
2097: switch (curi->size) {
2098: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2099: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2100: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2101: default: abort ();
2102: }
2103: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
2104: printf ("\tuae_u32 cflg = val & 1;\n");
2105: printf ("\tval = (val >> 1) | sign;\n");
2106: genflags (flag_logical, curi->size, "val", "", "");
2107: printf ("\tSET_CFLG (cflg);\n");
2108: duplicate_carry ();
2109: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2110: break;
2111: case i_ASLW:
2112: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2113: start_brace ();
2114: switch (curi->size) {
2115: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2116: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2117: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2118: default: abort ();
2119: }
2120: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
2121: printf ("\tuae_u32 sign2;\n");
2122: printf ("\tval <<= 1;\n");
2123: genflags (flag_logical, curi->size, "val", "", "");
2124: printf ("\tsign2 = %s & val;\n", cmask (curi->size));
2125: printf ("\tSET_CFLG (sign != 0);\n");
2126: duplicate_carry ();
2127:
2128: printf ("\tSET_VFLG (GET_VFLG | (sign2 != sign));\n");
2129: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2130: break;
2131: case i_LSRW:
2132: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2133: start_brace ();
2134: switch (curi->size) {
2135: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2136: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2137: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2138: default: abort ();
2139: }
2140: printf ("\tuae_u32 carry = val & 1;\n");
2141: printf ("\tval >>= 1;\n");
2142: genflags (flag_logical, curi->size, "val", "", "");
2143: printf ("SET_CFLG (carry);\n");
2144: duplicate_carry ();
2145: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2146: break;
2147: case i_LSLW:
2148: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2149: start_brace ();
2150: switch (curi->size) {
2151: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2152: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2153: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2154: default: abort ();
2155: }
2156: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2157: printf ("\tval <<= 1;\n");
2158: genflags (flag_logical, curi->size, "val", "", "");
2159: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2160: duplicate_carry ();
2161: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2162: break;
2163: case i_ROLW:
2164: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2165: start_brace ();
2166: switch (curi->size) {
2167: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2168: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2169: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2170: default: abort ();
2171: }
2172: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2173: printf ("\tval <<= 1;\n");
2174: printf ("\tif (carry) val |= 1;\n");
2175: genflags (flag_logical, curi->size, "val", "", "");
2176: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2177: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2178: break;
2179: case i_RORW:
2180: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2181: start_brace ();
2182: switch (curi->size) {
2183: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2184: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2185: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2186: default: abort ();
2187: }
2188: printf ("\tuae_u32 carry = val & 1;\n");
2189: printf ("\tval >>= 1;\n");
2190: printf ("\tif (carry) val |= %s;\n", cmask (curi->size));
2191: genflags (flag_logical, curi->size, "val", "", "");
2192: printf ("SET_CFLG (carry);\n");
2193: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2194: break;
2195: case i_ROXLW:
2196: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2197: start_brace ();
2198: switch (curi->size) {
2199: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2200: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2201: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2202: default: abort ();
2203: }
2204: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2205: printf ("\tval <<= 1;\n");
2206: printf ("\tif (GET_XFLG) val |= 1;\n");
2207: genflags (flag_logical, curi->size, "val", "", "");
2208: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2209: duplicate_carry ();
2210: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2211: break;
2212: case i_ROXRW:
2213: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2214: start_brace ();
2215: switch (curi->size) {
2216: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2217: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2218: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2219: default: abort ();
2220: }
2221: printf ("\tuae_u32 carry = val & 1;\n");
2222: printf ("\tval >>= 1;\n");
2223: printf ("\tif (GET_XFLG) val |= %s;\n", cmask (curi->size));
2224: genflags (flag_logical, curi->size, "val", "", "");
2225: printf ("SET_CFLG (carry);\n");
2226: duplicate_carry ();
2227: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2228: break;
2229: case i_MOVEC2:
2230: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2231: start_brace ();
2232: printf ("\tint regno = (src >> 12) & 15;\n");
2233: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
2234: printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
2235: break;
2236: case i_MOVE2C:
2237: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2238: start_brace ();
2239: printf ("\tint regno = (src >> 12) & 15;\n");
2240: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
2241: printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
2242: break;
2243: case i_CAS:
2244: {
2245: int old_brace_level;
2246: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2247: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2248: start_brace ();
2249: printf ("\tint ru = (src >> 6) & 7;\n");
2250: printf ("\tint rc = src & 7;\n");
2251: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, rc)", "dst");
2252: printf ("\tif (GET_ZFLG)");
2253: old_brace_level = n_braces;
2254: start_brace ();
2255: genastore ("(m68k_dreg(regs, ru))", curi->dmode, "dstreg", curi->size, "dst");
2256: pop_braces (old_brace_level);
2257: printf ("else");
2258: start_brace ();
2259: printf ("m68k_dreg(regs, rc) = dst;\n");
2260: pop_braces (old_brace_level);
2261: }
2262: break;
2263: case i_CAS2:
2264: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2265: printf ("\tuae_u32 rn1 = regs.regs[(extra >> 28) & 15];\n");
2266: printf ("\tuae_u32 rn2 = regs.regs[(extra >> 12) & 15];\n");
2267: if (curi->size == sz_word) {
2268: int old_brace_level = n_braces;
2269: printf ("\tuae_u16 dst1 = get_word(rn1), dst2 = get_word(rn2);\n");
2270: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
2271: printf ("\tif (GET_ZFLG) {\n");
2272: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
2273: printf ("\tif (GET_ZFLG) {\n");
2274: printf ("\tput_word(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n");
2275: printf ("\tput_word(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n");
2276: printf ("\t}}\n");
2277: pop_braces (old_brace_level);
2278: printf ("\tif (! GET_ZFLG) {\n");
2279: printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = (m68k_dreg(regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
2280: printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = (m68k_dreg(regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
2281: printf ("\t}\n");
2282: } else {
2283: int old_brace_level = n_braces;
2284: printf ("\tuae_u32 dst1 = get_long(rn1), dst2 = get_long(rn2);\n");
2285: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
2286: printf ("\tif (GET_ZFLG) {\n");
2287: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
2288: printf ("\tif (GET_ZFLG) {\n");
2289: printf ("\tput_long(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n");
2290: printf ("\tput_long(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n");
2291: printf ("\t}}\n");
2292: pop_braces (old_brace_level);
2293: printf ("\tif (! GET_ZFLG) {\n");
2294: printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = dst1;\n");
2295: printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = dst2;\n");
2296: printf ("\t}\n");
2297: }
2298: break;
2299: case i_MOVES: /* ignore DFC and SFC because we have no MMU */
2300: {
2301: int old_brace_level;
2302: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2303: printf ("\tif (extra & 0x800)\n");
2304: old_brace_level = n_braces;
2305: start_brace ();
2306: printf ("\tuae_u32 src = regs.regs[(extra >> 12) & 15];\n");
2307: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
2308: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
2309: pop_braces (old_brace_level);
2310: printf ("else");
2311: start_brace ();
2312: genamode (curi->dmode, "dstreg", curi->size, "src", 1, 0);
2313: printf ("\tif (extra & 0x8000) {\n");
2314: switch (curi->size) {
2315: case sz_byte: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;\n"); break;
2316: case sz_word: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;\n"); break;
2317: case sz_long: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = src;\n"); break;
2318: default: abort ();
2319: }
2320: printf ("\t} else {\n");
2321: genastore ("src", Dreg, "(extra >> 12) & 7", curi->size, "");
2322: printf ("\t}\n");
2323: pop_braces (old_brace_level);
2324: }
2325: break;
2326: case i_BKPT: /* only needed for hardware emulators */
2327: sync_m68k_pc ();
2328: printf ("\top_illg(opcode);\n");
2329: break;
2330: case i_CALLM: /* not present in 68030 */
2331: sync_m68k_pc ();
2332: printf ("\top_illg(opcode);\n");
2333: break;
2334: case i_RTM: /* not present in 68030 */
2335: sync_m68k_pc ();
2336: printf ("\top_illg(opcode);\n");
2337: break;
2338: case i_TRAPcc:
2339: if (curi->smode != am_unknown && curi->smode != am_illg)
2340: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
1.1.1.12 root 2341: printf ("\tif (cctrue(%d)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto %s; }\n", curi->cc, endlabelstr);
1.1 root 2342: need_endlabel = 1;
2343: break;
2344: case i_DIVL:
2345: sync_m68k_pc ();
2346: start_brace ();
2347: printf ("\tuaecptr oldpc = m68k_getpc();\n");
2348: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2349: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2350: sync_m68k_pc ();
2351: printf ("\tm68k_divl(opcode, dst, extra, oldpc);\n");
2352: break;
2353: case i_MULL:
2354: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2355: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2356: sync_m68k_pc ();
2357: printf ("\tm68k_mull(opcode, dst, extra);\n");
2358: break;
2359: case i_BFTST:
2360: case i_BFEXTU:
2361: case i_BFCHG:
2362: case i_BFEXTS:
2363: case i_BFCLR:
2364: case i_BFFFO:
2365: case i_BFSET:
2366: case i_BFINS:
2367: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2368: genamode (curi->dmode, "dstreg", sz_long, "dst", 2, 0);
2369: start_brace ();
2370: printf ("\tuae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;\n");
2371: printf ("\tint width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;\n");
2372: if (curi->dmode == Dreg) {
2373: printf ("\tuae_u32 tmp = m68k_dreg(regs, dstreg) << (offset & 0x1f);\n");
2374: } else {
2375: printf ("\tuae_u32 tmp,bf0,bf1;\n");
2376: printf ("\tdsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);\n");
2377: printf ("\tbf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;\n");
2378: printf ("\ttmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));\n");
2379: }
2380: printf ("\ttmp >>= (32 - width);\n");
2381: printf ("\tSET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);\n");
2382: printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
2383: switch (curi->mnemo) {
2384: case i_BFTST:
2385: break;
2386: case i_BFEXTU:
2387: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n");
2388: break;
2389: case i_BFCHG:
2390: printf ("\ttmp = ~tmp;\n");
2391: break;
2392: case i_BFEXTS:
2393: printf ("\tif (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);\n");
2394: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n");
2395: break;
2396: case i_BFCLR:
2397: printf ("\ttmp = 0;\n");
2398: break;
2399: case i_BFFFO:
2400: printf ("\t{ uae_u32 mask = 1 << (width-1);\n");
2401: printf ("\twhile (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}\n");
2402: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = offset;\n");
2403: break;
2404: case i_BFSET:
2405: printf ("\ttmp = 0xffffffff;\n");
2406: break;
2407: case i_BFINS:
2408: printf ("\ttmp = m68k_dreg(regs, (extra >> 12) & 7);\n");
1.1.1.4 root 2409: printf ("\tSET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);\n");
2410: printf ("\tSET_ZFLG (tmp == 0);\n");
1.1 root 2411: break;
2412: default:
2413: break;
2414: }
2415: if (curi->mnemo == i_BFCHG
2416: || curi->mnemo == i_BFCLR
2417: || curi->mnemo == i_BFSET
2418: || curi->mnemo == i_BFINS)
2419: {
2420: printf ("\ttmp <<= (32 - width);\n");
2421: if (curi->dmode == Dreg) {
2422: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ((offset & 0x1f) == 0 ? 0 :\n");
2423: printf ("\t\t(0xffffffff << (32 - (offset & 0x1f))))) |\n");
2424: printf ("\t\t(tmp >> (offset & 0x1f)) |\n");
2425: printf ("\t\t(((offset & 0x1f) + width) >= 32 ? 0 :\n");
2426: printf (" (m68k_dreg(regs, dstreg) & ((uae_u32)0xffffffff >> ((offset & 0x1f) + width))));\n");
2427: } else {
2428: printf ("\tbf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |\n");
2429: printf ("\t\t(tmp >> (offset & 7)) |\n");
2430: printf ("\t\t(((offset & 7) + width) >= 32 ? 0 :\n");
2431: printf ("\t\t (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));\n");
2432: printf ("\tput_long(dsta,bf0 );\n");
2433: printf ("\tif (((offset & 7) + width) > 32) {\n");
2434: printf ("\t\tbf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |\n");
2435: printf ("\t\t\t(tmp << (8 - (offset & 7)));\n");
2436: printf ("\t\tput_byte(dsta+4,bf1);\n");
2437: printf ("\t}\n");
2438: }
2439: }
2440: break;
2441: case i_PACK:
2442: if (curi->smode == Dreg) {
2443: printf ("\tuae_u16 val = m68k_dreg(regs, srcreg) + %s;\n", gen_nextiword ());
2444: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);\n");
2445: } else {
2446: printf ("\tuae_u16 val;\n");
2447: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2448: printf ("\tval = (uae_u16)get_byte(m68k_areg(regs, srcreg));\n");
2449: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2450: printf ("\tval = (val | ((uae_u16)get_byte(m68k_areg(regs, srcreg)) << 8)) + %s;\n", gen_nextiword ());
2451: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2452: printf ("\tput_byte(m68k_areg(regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));\n");
2453: }
2454: break;
2455: case i_UNPK:
2456: if (curi->smode == Dreg) {
2457: printf ("\tuae_u16 val = m68k_dreg(regs, srcreg);\n");
2458: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword ());
2459: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffff0000) | (val & 0xffff);\n");
2460: } else {
2461: printf ("\tuae_u16 val;\n");
2462: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2463: printf ("\tval = (uae_u16)get_byte(m68k_areg(regs, srcreg));\n");
2464: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword ());
2465: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2466: printf ("\tput_byte(m68k_areg(regs, dstreg),val);\n");
2467: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2468: printf ("\tput_byte(m68k_areg(regs, dstreg),val >> 8);\n");
2469: }
2470: break;
2471: case i_TAS:
2472: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2473: genflags (flag_logical, curi->size, "src", "", "");
2474: printf ("\tsrc |= 0x80;\n");
2475: genastore ("src", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 2476: if( curi->smode!=Dreg ) insn_n_cycles += 2;
1.1 root 2477: break;
2478: case i_FPP:
2479: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2480: sync_m68k_pc ();
2481: printf ("\tfpp_opp(opcode,extra);\n");
2482: break;
2483: case i_FDBcc:
2484: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2485: sync_m68k_pc ();
2486: printf ("\tfdbcc_opp(opcode,extra);\n");
2487: break;
2488: case i_FScc:
2489: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2490: sync_m68k_pc ();
2491: printf ("\tfscc_opp(opcode,extra);\n");
2492: break;
2493: case i_FTRAPcc:
2494: sync_m68k_pc ();
2495: start_brace ();
2496: printf ("\tuaecptr oldpc = m68k_getpc();\n");
2497: if (curi->smode != am_unknown && curi->smode != am_illg)
2498: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
2499: sync_m68k_pc ();
2500: printf ("\tftrapcc_opp(opcode,oldpc);\n");
2501: break;
2502: case i_FBcc:
2503: sync_m68k_pc ();
2504: start_brace ();
2505: printf ("\tuaecptr pc = m68k_getpc();\n");
2506: genamode (curi->dmode, "srcreg", curi->size, "extra", 1, 0);
2507: sync_m68k_pc ();
2508: printf ("\tfbcc_opp(opcode,pc,extra);\n");
2509: break;
2510: case i_FSAVE:
2511: sync_m68k_pc ();
2512: printf ("\tfsave_opp(opcode);\n");
2513: break;
2514: case i_FRESTORE:
2515: sync_m68k_pc ();
2516: printf ("\tfrestore_opp(opcode);\n");
2517: break;
2518:
2519: case i_CINVL:
2520: case i_CINVP:
2521: case i_CINVA:
2522: case i_CPUSHL:
2523: case i_CPUSHP:
2524: case i_CPUSHA:
2525: break;
2526: case i_MOVE16:
1.1.1.4 root 2527: if ((opcode & 0xfff8) == 0xf620) {
2528: /* MOVE16 (Ax)+,(Ay)+ */
2529: printf ("\tuaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
2530: printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword());
2531: printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n");
2532: printf ("\tput_long(memd, get_long(mems));\n");
2533: printf ("\tput_long(memd+4, get_long(mems+4));\n");
2534: printf ("\tput_long(memd+8, get_long(mems+8));\n");
2535: printf ("\tput_long(memd+12, get_long(mems+12));\n");
2536: printf ("\tif (srcreg != dstreg)\n");
2537: printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2538: printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2539: } else {
2540: /* Other variants */
2541: genamode (curi->smode, "srcreg", curi->size, "mems", 0, 2);
2542: genamode (curi->dmode, "dstreg", curi->size, "memd", 0, 2);
2543: printf ("\tmemsa &= ~15;\n");
2544: printf ("\tmemda &= ~15;\n");
2545: printf ("\tput_long(memda, get_long(memsa));\n");
2546: printf ("\tput_long(memda+4, get_long(memsa+4));\n");
2547: printf ("\tput_long(memda+8, get_long(memsa+8));\n");
2548: printf ("\tput_long(memda+12, get_long(memsa+12));\n");
2549: if ((opcode & 0xfff8) == 0xf600)
2550: printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2551: else if ((opcode & 0xfff8) == 0xf608)
2552: printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2553: }
1.1 root 2554: break;
2555:
2556: case i_MMUOP:
2557: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2558: sync_m68k_pc ();
2559: printf ("\tmmu_op(opcode,extra);\n");
2560: break;
2561: default:
2562: abort ();
2563: break;
2564: }
2565: finish_braces ();
2566: sync_m68k_pc ();
2567: }
2568:
2569: static void generate_includes (FILE * f)
2570: {
2571: fprintf (f, "#include \"sysdeps.h\"\n");
2572: fprintf (f, "#include \"hatari-glue.h\"\n");
2573: fprintf (f, "#include \"maccess.h\"\n");
2574: fprintf (f, "#include \"memory.h\"\n");
2575: fprintf (f, "#include \"newcpu.h\"\n");
2576: fprintf (f, "#include \"cputbl.h\"\n");
2577: fprintf (f, "#define CPUFUNC(x) x##_ff\n"
2578: "#ifdef NOFLAGS\n"
2579: "#include \"noflags.h\"\n"
2580: "#endif\n");
2581: }
2582:
2583: static int postfix;
2584:
2585: static void generate_one_opcode (int rp)
2586: {
2587: int i;
2588: uae_u16 smsk, dmsk;
2589: long int opcode = opcode_map[rp];
2590:
1.1.1.2 root 2591: exactCpuCycles[0] = 0; /* Default: not used */
2592:
1.1 root 2593: if (table68k[opcode].mnemo == i_ILLG
2594: || table68k[opcode].clev > cpu_level)
2595: return;
2596:
2597: for (i = 0; lookuptab[i].name[0]; i++) {
2598: if (table68k[opcode].mnemo == lookuptab[i].mnemo)
2599: break;
2600: }
2601:
2602: if (table68k[opcode].handler != -1)
2603: return;
2604:
2605: if (opcode_next_clev[rp] != cpu_level) {
2606: fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp],
2607: opcode, lookuptab[i].name);
2608: return;
2609: }
2610: fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, postfix, opcode, lookuptab[i].name);
2611: fprintf (headerfile, "extern cpuop_func op_%lx_%d_nf;\n", opcode, postfix);
2612: fprintf (headerfile, "extern cpuop_func op_%lx_%d_ff;\n", opcode, postfix);
2613: printf ("unsigned long REGPARAM2 CPUFUNC(op_%lx_%d)(uae_u32 opcode) /* %s */\n{\n", opcode, postfix, lookuptab[i].name);
2614:
2615: switch (table68k[opcode].stype) {
2616: case 0: smsk = 7; break;
2617: case 1: smsk = 255; break;
2618: case 2: smsk = 15; break;
2619: case 3: smsk = 7; break;
2620: case 4: smsk = 7; break;
2621: case 5: smsk = 63; break;
1.1.1.4 root 2622: case 7: smsk = 3; break;
1.1 root 2623: default: abort ();
2624: }
2625: dmsk = 7;
2626:
2627: next_cpu_level = -1;
2628: if (table68k[opcode].suse
2629: && table68k[opcode].smode != imm && table68k[opcode].smode != imm0
2630: && table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
2631: && table68k[opcode].smode != absw && table68k[opcode].smode != absl
2632: && table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
2633: {
2634: if (table68k[opcode].spos == -1) {
2635: if (((int) table68k[opcode].sreg) >= 128)
2636: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].sreg);
2637: else
2638: printf ("\tuae_u32 srcreg = %d;\n", (int) table68k[opcode].sreg);
2639: } else {
2640: char source[100];
2641: int pos = table68k[opcode].spos;
2642:
2643: if (pos)
2644: sprintf (source, "((opcode >> %d) & %d)", pos, smsk);
2645: else
2646: sprintf (source, "(opcode & %d)", smsk);
2647:
2648: if (table68k[opcode].stype == 3)
2649: printf ("\tuae_u32 srcreg = imm8_table[%s];\n", source);
2650: else if (table68k[opcode].stype == 1)
2651: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%s;\n", source);
2652: else
2653: printf ("\tuae_u32 srcreg = %s;\n", source);
2654: }
2655: }
2656: if (table68k[opcode].duse
2657: /* Yes, the dmode can be imm, in case of LINK or DBcc */
2658: && table68k[opcode].dmode != imm && table68k[opcode].dmode != imm0
2659: && table68k[opcode].dmode != imm1 && table68k[opcode].dmode != imm2
2660: && table68k[opcode].dmode != absw && table68k[opcode].dmode != absl)
2661: {
2662: if (table68k[opcode].dpos == -1) {
2663: if (((int) table68k[opcode].dreg) >= 128)
2664: printf ("\tuae_u32 dstreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].dreg);
2665: else
2666: printf ("\tuae_u32 dstreg = %d;\n", (int) table68k[opcode].dreg);
2667: } else {
2668: int pos = table68k[opcode].dpos;
2669: #if 0
2670: /* Check that we can do the little endian optimization safely. */
2671: if (pos < 8 && (dmsk >> (8 - pos)) != 0)
2672: abort ();
2673: #endif
2674: if (pos)
2675: printf ("\tuae_u32 dstreg = (opcode >> %d) & %d;\n",
2676: pos, dmsk);
2677: else
2678: printf ("\tuae_u32 dstreg = opcode & %d;\n", dmsk);
2679: }
2680: }
2681: need_endlabel = 0;
2682: endlabelno++;
2683: sprintf (endlabelstr, "endlabel%d", endlabelno);
1.1.1.2 root 2684: if(table68k[opcode].mnemo==i_ASR || table68k[opcode].mnemo==i_ASL || table68k[opcode].mnemo==i_LSR || table68k[opcode].mnemo==i_LSL
2685: || table68k[opcode].mnemo==i_ROL || table68k[opcode].mnemo==i_ROR || table68k[opcode].mnemo==i_ROXL || table68k[opcode].mnemo==i_ROXR
1.1.1.8 root 2686: || table68k[opcode].mnemo==i_MVMEL || table68k[opcode].mnemo==i_MVMLE
2687: || table68k[opcode].mnemo==i_MULU || table68k[opcode].mnemo==i_MULS
2688: || table68k[opcode].mnemo==i_DIVU || table68k[opcode].mnemo==i_DIVS )
2689: printf("\tunsigned int retcycles = 0;\n");
1.1 root 2690: gen_opcode (opcode);
2691: if (need_endlabel)
2692: printf ("%s: ;\n", endlabelstr);
1.1.1.8 root 2693:
2694: if (strlen(exactCpuCycles) > 0)
2695: printf("%s\n",exactCpuCycles);
2696: else
2697: printf ("return %d;\n", insn_n_cycles);
2698: /* Now patch in the instruction cycles at the beginning of the function: */
2699: fseek(stdout, nCurInstrCycPos, SEEK_SET);
2700: printf("%d;", insn_n_cycles);
2701: fseek(stdout, 0, SEEK_END);
2702:
1.1 root 2703: printf ("}\n");
2704: opcode_next_clev[rp] = next_cpu_level;
2705: opcode_last_postfix[rp] = postfix;
2706: }
2707:
2708: static void generate_func (void)
2709: {
2710: int i, j, rp;
2711:
2712: using_prefetch = 0;
2713: using_exception_3 = 0;
2714: for (i = 0; i < 6; i++) {
2715: cpu_level = 4 - i;
2716: if (i == 5) {
2717: cpu_level = 0;
2718: using_prefetch = 1;
2719: using_exception_3 = 1;
2720: for (rp = 0; rp < nr_cpuop_funcs; rp++)
2721: opcode_next_clev[rp] = 0;
2722: }
2723:
2724: postfix = i;
1.1.1.7 root 2725: fprintf (stblfile, "const struct cputbl CPUFUNC(op_smalltbl_%d)[] = {\n", postfix);
1.1 root 2726:
2727: /* sam: this is for people with low memory (eg. me :)) */
2728: printf ("\n"
2729: "#if !defined(PART_1) && !defined(PART_2) && "
2730: "!defined(PART_3) && !defined(PART_4) && "
2731: "!defined(PART_5) && !defined(PART_6) && "
2732: "!defined(PART_7) && !defined(PART_8)"
2733: "\n"
2734: "#define PART_1 1\n"
2735: "#define PART_2 1\n"
2736: "#define PART_3 1\n"
2737: "#define PART_4 1\n"
2738: "#define PART_5 1\n"
2739: "#define PART_6 1\n"
2740: "#define PART_7 1\n"
2741: "#define PART_8 1\n"
2742: "#endif\n\n");
2743:
2744: rp = 0;
2745: for(j=1;j<=8;++j) {
2746: int k = (j*nr_cpuop_funcs)/8;
2747: printf ("#ifdef PART_%d\n",j);
2748: for (; rp < k; rp++)
2749: generate_one_opcode (rp);
2750: printf ("#endif\n\n");
2751: }
2752:
2753: fprintf (stblfile, "{ 0, 0, 0 }};\n");
2754: }
2755:
2756: }
2757:
2758: int main (int argc, char **argv)
2759: {
2760: read_table68k ();
2761: do_merges ();
2762:
2763: opcode_map = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2764: opcode_last_postfix = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2765: opcode_next_clev = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2766: counts = (unsigned long *) malloc (65536 * sizeof (unsigned long));
2767: read_counts ();
2768:
2769: /* It would be a lot nicer to put all in one file (we'd also get rid of
2770: * cputbl.h that way), but cpuopti can't cope. That could be fixed, but
2771: * I don't dare to touch the 68k version. */
2772:
2773: headerfile = fopen ("cputbl.h", "wb");
2774: stblfile = fopen ("cpustbl.c", "wb");
1.1.1.11 root 2775: if (freopen ("cpuemu.c", "wb", stdout) == NULL) {
2776: perror("cpuemu.c");
2777: return -1;
2778: }
1.1 root 2779:
2780: generate_includes (stdout);
2781: generate_includes (stblfile);
2782:
2783: generate_func ();
2784:
2785: free (table68k);
2786: return 0;
2787: }
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