![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to gencpu.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [HATARI the Atari ST Emulator] / hatari / src / uae-cpu|
Return to gencpu.c CVS log | Up to [HATARI the Atari ST Emulator] / hatari / src / uae-cpu |
1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation generator
5: *
6: * This is a fairly stupid program that generates a lot of case labels that
7: * can be #included in a switch statement.
8: * As an alternative, it can generate functions that handle specific
9: * MC68000 instructions, plus a prototype header file and a function pointer
10: * array to look up the function for an opcode.
11: * Error checking is bad, an illegal table68k file will cause the program to
12: * call abort().
13: * The generated code is sometimes sub-optimal, an optimizing compiler should
14: * take care of this.
15: *
16: * The source for the insn timings is Markt & Technik's Amiga Magazin 8/1992.
17: *
18: * Copyright 1995, 1996, 1997, 1998, 1999, 2000 Bernd Schmidt
1.1.1.2 root 19: *
20: * Adaptation to Hatari and better cpu timings by Thomas Huth
21: *
1.1.1.16 root 22: * This file is distributed under the GNU General Public License, version 2
23: * or at your option any later version. Read the file gpl.txt for details.
1.1 root 24: */
1.1.1.8 root 25:
26:
27: /* 2007/03/xx [NP] Use add_cycles.pl to set 'CurrentInstrCycles' in each opcode. */
28: /* 2007/04/09 [NP] Correct CLR : on 68000, CLR reads the memory before clearing it (but we should */
29: /* not add cycles for reading). This means CLR can give 2 wait states (one for */
30: /* read and one for right) (clr.b $fa1b.w in Decade's Demo Main Menu). */
31: /* 2007/04/14 [NP] - Although dest -(an) normally takes 2 cycles, this is not the case for move : */
32: /* move dest (an), (an)+ and -(an) all take the same time (curi->dmode == Apdi) */
33: /* (Syntax Terror Demo Reset). */
34: /* - Scc takes 6 cycles instead of 4 if the result is true (Ventura Demo Loader). */
35: /* - Store the family of the current opcode into OpcodeFamily : used to check */
36: /* instruction pairing on ST into m68000.c */
37: /* 2007/04/17 [NP] Add support for cycle accurate MULU (No Cooper Greeting Screen). */
38: /* 2007/04/24 [NP] BCLR #n,Dx takes 12 cycles instead of 14 if n<16 (ULM Demo Menu). */
39: /* 2007/04/25 [NP] On ST, d8(An,Xn) and d8(PC,Xn) take 2 cycles more than the official 68000's */
40: /* table (ULM Demo Menu). */
41: /* 2007/11/12 [NP] Add refill_prefetch for i_ADD to fix Transbeauce 2 demo self modified code. */
42: /* Ugly hack, we need better prefetch emulation (switch to winuae gencpu.c) */
43: /* 2007/11/25 [NP] In i_DBcc, in case of address error, last_addr_for_exception_3 should be */
44: /* pc+4, not pc+2 (Transbeauce 2 demo) (e.g. 'dbf d0,#$fff5'). */
45: /* This means the value pushed on the frame stack should be the address of the */
46: /* instruction following the one generating the address error. */
47: /* FIXME : this should be the case for i_BSR and i_BCC too (need to check on */
48: /* a real 68000). */
49: /* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */
50: /* Cwik, [email protected]). */
51: /* 2007/12/08 [NP] In case of CHK/CHK2 exception, PC stored on the stack wasn't pointing to the */
52: /* next instruction but to the current CHK/CHK2 instruction (Transbeauce 2 demo). */
53: /* We need to call 'sync_m68k_pc' before calling 'Exception'. */
54: /* 2007/12/09 [NP] CHK.L (e.g. $4700) doesn't exist on 68000 and should be considered as an illegal*/
55: /* instruction (Transbeauce 2 demo) -> change in table68k. */
56: /* 2008/01/24 [NP] BCLR Dy,Dx takes 8 cycles instead of 10 if Dy<16 (Fullshade in Anomaly Demos). */
57: /* 2008/01/26 [NP] On ST, d8(An,Xn) takes 2 cycles more when used with ADDA/SUBA (ULM Demo Menu) */
58: /* but not when used with MOVE (e.g. 'move.l 0(a5,d1),(a4)' takes 26 cycles and so */
59: /* can pair with a lsr) (Anomaly Demo Intro). */
1.1.1.9 root 60: /* 2008/04/26 [NP] Handle sz_byte for Areg in genamode, as 'move.b a1,(a0)' ($1089) is possible */
61: /* on ST (fix Blood Money on Superior 65) */
1.1.1.12 root 62: /* 2010/04/05 [NP] On ST, d8(An,Xn) takes 2 cycles more (which can generate pairing). */
63: /* Use BusCyclePenalty to properly handle the 2/4 cycles added in that case when */
64: /* addressing mode is Ad8r or PC8r (ULM Demo Menu, Anomaly Demo Intro, DHS */
65: /* Sommarhack 2010) (see m68000.h) */
1.1.1.15 root 66: /* 2012/01/29 [NP] Add refill_prefetch for i_EOR to fix Operation Clean Streets self modified code.*/
67: /* Ugly hack, we need better prefetch emulation (switch to winuae gencpu.c) */
68: /* 2012/05/05 [NP] In i_JMP, in case of address error, last_addr_for_exception_3 should not always */
69: /* be pc+6, (Sherman Cracktro in No Extra V2 compilation) (e.g. 'jmp (a2)' : pc+2) */
1.1.1.17 root 70: /* 2013/03/17 [NP] Add refill_prefetch for i_SUB, i_NEG, i_NEGX, i_NOT (similar to i_ADD/i_EOR) */
71: /* 2014/03/07 [NP] Add refill_prefetch for i_Move Dn,xxxx.l (Union Demo, Darkman, Parasol Stars) */
72: /* Add refill_prefetch for i_Move #xxxx,(An) (Titan) */
73: /* 2014/04/09 [NP] Similar to CLR on 68000, Scc should do a read before doing the write and can */
74: /* give 2 wait states (sf $fffa07 in Chart Attack compilation by Gremlin) */
75: /* 2014/04/11 [NP] Add refill_prefetch for i_Move Dn,(An) (International 3D Tennis) */
1.1.1.18! root 76: /* 2014/08/15 [NP] Cancel change from 2008/04/26, sz_byte for Areg is not valid for MOVE, */
! 77: /* 'move.b a1,(a0)' should give an illegal exception */
! 78: /* 2012/05/05 [NP] In i_JMP, in case of address error with jmp xxx.w, last_addr_for_exception_3 */
! 79: /* should be pc+2 (The Teller, 'jmp $201.w') */
! 80: /* 2015/07/29 [NP] In the case of an address error, correctly set last_writeaccess_for_exception_3 */
! 81: /* to 0 (read) or 1 (write) (War Heli) */
! 82: /* 2015/07/29 [NP] Add refill_prefetch for i_Bcc (War Heli, 'bra.s -2' ($60fe)) */
1.1.1.8 root 83:
84:
1.1.1.11 root 85: const char GenCpu_fileid[] = "Hatari gencpu.c : " __DATE__ " " __TIME__;
1.1 root 86:
87: #include <ctype.h>
1.1.1.3 root 88: #include <string.h>
1.1 root 89:
90: #include "sysdeps.h"
91: #include "readcpu.h"
92:
93: #define BOOL_TYPE "int"
94:
95: static FILE *headerfile;
96: static FILE *stblfile;
97:
98: static int using_prefetch;
99: static int using_exception_3;
100: static int cpu_level;
101:
1.1.1.2 root 102: char exactCpuCycles[256]; /* Space to store return string for exact cpu cycles */
103:
1.1.1.8 root 104: long nCurInstrCycPos; /* Stores where we have to patch in the current cycles value */
1.1.1.2 root 105:
1.1 root 106: /* For the current opcode, the next lower level that will have different code.
107: * Initialized to -1 for each opcode. If it remains unchanged, indicates we
108: * are done with that opcode. */
109: static int next_cpu_level;
110: static int *opcode_map;
111: static int *opcode_next_clev;
112: static int *opcode_last_postfix;
113: static unsigned long *counts;
114:
1.1.1.6 root 115:
1.1 root 116: static void read_counts (void)
117: {
118: FILE *file;
119: unsigned long opcode, count, total;
120: char name[20];
121: int nr = 0;
122: memset (counts, 0, 65536 * sizeof *counts);
123:
124: file = fopen ("frequent.68k", "r");
125: if (file) {
1.1.1.11 root 126: if (fscanf (file, "Total: %lu\n", &total) == EOF) {
127: perror("read_counts");
128: }
1.1 root 129: while (fscanf (file, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
130: opcode_next_clev[nr] = 4;
131: opcode_last_postfix[nr] = -1;
132: opcode_map[nr++] = opcode;
133: counts[opcode] = count;
134: }
135: fclose (file);
136: }
137: if (nr == nr_cpuop_funcs)
138: return;
139: for (opcode = 0; opcode < 0x10000; opcode++) {
140: if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
141: && counts[opcode] == 0)
142: {
143: opcode_next_clev[nr] = 4;
144: opcode_last_postfix[nr] = -1;
145: opcode_map[nr++] = opcode;
146: counts[opcode] = count;
147: }
148: }
149: if (nr != nr_cpuop_funcs)
150: abort ();
151: }
152:
153: static char endlabelstr[80];
154: static int endlabelno = 0;
155: static int need_endlabel;
156:
157: static int n_braces = 0;
158: static int m68k_pc_offset = 0;
159: static int insn_n_cycles;
160:
161: static void start_brace (void)
162: {
163: n_braces++;
164: printf ("{");
165: }
166:
167: static void close_brace (void)
168: {
169: assert (n_braces > 0);
170: n_braces--;
171: printf ("}");
172: }
173:
174: static void finish_braces (void)
175: {
176: while (n_braces > 0)
177: close_brace ();
178: }
179:
180: static void pop_braces (int to)
181: {
182: while (n_braces > to)
183: close_brace ();
184: }
185:
186: static int bit_size (int size)
187: {
188: switch (size) {
189: case sz_byte: return 8;
190: case sz_word: return 16;
191: case sz_long: return 32;
192: default: abort ();
193: }
194: return 0;
195: }
196:
197: static const char *bit_mask (int size)
198: {
199: switch (size) {
200: case sz_byte: return "0xff";
201: case sz_word: return "0xffff";
202: case sz_long: return "0xffffffff";
203: default: abort ();
204: }
205: return 0;
206: }
207:
208: static const char *gen_nextilong (void)
209: {
210: static char buffer[80];
211: int r = m68k_pc_offset;
212: m68k_pc_offset += 4;
213:
214: insn_n_cycles += 8;
215:
216: if (using_prefetch)
217: sprintf (buffer, "get_ilong_prefetch(%d)", r);
218: else
219: sprintf (buffer, "get_ilong(%d)", r);
220: return buffer;
221: }
222:
223: static const char *gen_nextiword (void)
224: {
225: static char buffer[80];
226: int r = m68k_pc_offset;
227: m68k_pc_offset += 2;
228:
229: insn_n_cycles += 4;
230:
231: if (using_prefetch)
232: sprintf (buffer, "get_iword_prefetch(%d)", r);
233: else
234: sprintf (buffer, "get_iword(%d)", r);
235: return buffer;
236: }
237:
238: static const char *gen_nextibyte (void)
239: {
240: static char buffer[80];
241: int r = m68k_pc_offset;
242: m68k_pc_offset += 2;
243:
244: insn_n_cycles += 4;
245:
246: if (using_prefetch)
247: sprintf (buffer, "get_ibyte_prefetch(%d)", r);
248: else
249: sprintf (buffer, "get_ibyte(%d)", r);
250: return buffer;
251: }
252:
253: static void fill_prefetch_0 (void)
254: {
255: if (using_prefetch)
256: printf ("fill_prefetch_0 ();\n");
257: }
258:
259: static void fill_prefetch_2 (void)
260: {
261: if (using_prefetch)
262: printf ("fill_prefetch_2 ();\n");
263: }
264:
265: static void sync_m68k_pc (void)
266: {
267: if (m68k_pc_offset == 0)
268: return;
269: printf ("m68k_incpc(%d);\n", m68k_pc_offset);
270: switch (m68k_pc_offset) {
271: case 0:
272: /*fprintf (stderr, "refilling prefetch at 0\n"); */
273: break;
274: case 2:
275: fill_prefetch_2 ();
276: break;
277: default:
278: fill_prefetch_0 ();
279: break;
280: }
281: m68k_pc_offset = 0;
282: }
283:
284: /* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
1.1.1.4 root 285: * the calling routine handles Apdi and Aipi modes.
286: * gb-- movem == 2 means the same thing but for a MOVE16 instruction */
1.1.1.12 root 287: static void genamode (amodes mode, const char *reg, wordsizes size,
288: const char *name, int getv, int movem)
1.1 root 289: {
290: start_brace ();
291: switch (mode) {
292: case Dreg:
293: if (movem)
294: abort ();
295: if (getv == 1)
296: switch (size) {
297: case sz_byte:
298: printf ("\tuae_s8 %s = m68k_dreg(regs, %s);\n", name, reg);
299: break;
300: case sz_word:
301: printf ("\tuae_s16 %s = m68k_dreg(regs, %s);\n", name, reg);
302: break;
303: case sz_long:
304: printf ("\tuae_s32 %s = m68k_dreg(regs, %s);\n", name, reg);
305: break;
306: default:
307: abort ();
308: }
309: return;
310: case Areg:
311: if (movem)
312: abort ();
313: if (getv == 1)
314: switch (size) {
315: case sz_word:
316: printf ("\tuae_s16 %s = m68k_areg(regs, %s);\n", name, reg);
317: break;
318: case sz_long:
319: printf ("\tuae_s32 %s = m68k_areg(regs, %s);\n", name, reg);
320: break;
321: default:
322: abort ();
323: }
324: return;
325: case Aind:
326: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
327: break;
328: case Aipi:
329: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
330: break;
331: case Apdi:
332: insn_n_cycles += 2;
333: switch (size) {
334: case sz_byte:
335: if (movem)
336: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
337: else
338: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - areg_byteinc[%s];\n", name, reg, reg);
339: break;
340: case sz_word:
341: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 2);
342: break;
343: case sz_long:
344: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 4);
345: break;
346: default:
347: abort ();
348: }
349: break;
350: case Ad16:
351: printf ("\tuaecptr %sa = m68k_areg(regs, %s) + (uae_s32)(uae_s16)%s;\n", name, reg, gen_nextiword ());
352: break;
353: case Ad8r:
354: insn_n_cycles += 2;
355: if (cpu_level > 1) {
356: if (next_cpu_level < 1)
357: next_cpu_level = 1;
358: sync_m68k_pc ();
359: start_brace ();
360: /* This would ordinarily be done in gen_nextiword, which we bypass. */
361: insn_n_cycles += 4;
362: printf ("\tuaecptr %sa = get_disp_ea_020(m68k_areg(regs, %s), next_iword());\n", name, reg);
1.1.1.8 root 363: } else {
1.1 root 364: printf ("\tuaecptr %sa = get_disp_ea_000(m68k_areg(regs, %s), %s);\n", name, reg, gen_nextiword ());
1.1.1.8 root 365: }
1.1.1.12 root 366: printf ("\tBusCyclePenalty += 2;\n");
1.1 root 367:
368: break;
369: case PC16:
370: printf ("\tuaecptr %sa = m68k_getpc () + %d;\n", name, m68k_pc_offset);
371: printf ("\t%sa += (uae_s32)(uae_s16)%s;\n", name, gen_nextiword ());
372: break;
373: case PC8r:
374: insn_n_cycles += 2;
375: if (cpu_level > 1) {
376: if (next_cpu_level < 1)
377: next_cpu_level = 1;
378: sync_m68k_pc ();
379: start_brace ();
380: /* This would ordinarily be done in gen_nextiword, which we bypass. */
381: insn_n_cycles += 4;
382: printf ("\tuaecptr tmppc = m68k_getpc();\n");
383: printf ("\tuaecptr %sa = get_disp_ea_020(tmppc, next_iword());\n", name);
384: } else {
385: printf ("\tuaecptr tmppc = m68k_getpc() + %d;\n", m68k_pc_offset);
386: printf ("\tuaecptr %sa = get_disp_ea_000(tmppc, %s);\n", name, gen_nextiword ());
387: }
1.1.1.12 root 388: printf ("\tBusCyclePenalty += 2;\n");
1.1 root 389:
390: break;
391: case absw:
392: printf ("\tuaecptr %sa = (uae_s32)(uae_s16)%s;\n", name, gen_nextiword ());
393: break;
394: case absl:
395: printf ("\tuaecptr %sa = %s;\n", name, gen_nextilong ());
396: break;
397: case imm:
398: if (getv != 1)
399: abort ();
400: switch (size) {
401: case sz_byte:
402: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte ());
403: break;
404: case sz_word:
405: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword ());
406: break;
407: case sz_long:
408: printf ("\tuae_s32 %s = %s;\n", name, gen_nextilong ());
409: break;
410: default:
411: abort ();
412: }
413: return;
414: case imm0:
415: if (getv != 1)
416: abort ();
417: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte ());
418: return;
419: case imm1:
420: if (getv != 1)
421: abort ();
422: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword ());
423: return;
424: case imm2:
425: if (getv != 1)
426: abort ();
427: printf ("\tuae_s32 %s = %s;\n", name, gen_nextilong ());
428: return;
429: case immi:
430: if (getv != 1)
431: abort ();
432: printf ("\tuae_u32 %s = %s;\n", name, reg);
433: return;
434: default:
435: abort ();
436: }
437:
438: /* We get here for all non-reg non-immediate addressing modes to
439: * actually fetch the value. */
440:
441: if (using_exception_3 && getv != 0 && size != sz_byte) {
442: printf ("\tif ((%sa & 1) != 0) {\n", name);
443: printf ("\t\tlast_fault_for_exception_3 = %sa;\n", name);
444: printf ("\t\tlast_op_for_exception_3 = opcode;\n");
1.1.1.18! root 445: printf ("\t\tlast_instructionaccess_for_exception_3 = 0;\n");
! 446: if ( getv == 2 )
! 447: printf ("\t\tlast_writeaccess_for_exception_3 = 1;\n"); /* write */
! 448: else
! 449: printf ("\t\tlast_writeaccess_for_exception_3 = 0;\n"); /* read */
1.1 root 450: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + %d;\n", m68k_pc_offset);
1.1.1.12 root 451: printf ("\t\tException(3, 0, M68000_EXC_SRC_CPU);\n");
1.1 root 452: printf ("\t\tgoto %s;\n", endlabelstr);
453: printf ("\t}\n");
454: need_endlabel = 1;
455: start_brace ();
456: }
457:
458: if (getv == 1) {
459: switch (size) {
460: case sz_byte: insn_n_cycles += 4; break;
461: case sz_word: insn_n_cycles += 4; break;
462: case sz_long: insn_n_cycles += 8; break;
463: default: abort ();
464: }
465: start_brace ();
466: switch (size) {
467: case sz_byte: printf ("\tuae_s8 %s = get_byte(%sa);\n", name, name); break;
468: case sz_word: printf ("\tuae_s16 %s = get_word(%sa);\n", name, name); break;
469: case sz_long: printf ("\tuae_s32 %s = get_long(%sa);\n", name, name); break;
470: default: abort ();
471: }
472: }
473:
474: /* We now might have to fix up the register for pre-dec or post-inc
475: * addressing modes. */
476: if (!movem)
477: switch (mode) {
478: case Aipi:
479: switch (size) {
480: case sz_byte:
481: printf ("\tm68k_areg(regs, %s) += areg_byteinc[%s];\n", reg, reg);
482: break;
483: case sz_word:
484: printf ("\tm68k_areg(regs, %s) += 2;\n", reg);
485: break;
486: case sz_long:
487: printf ("\tm68k_areg(regs, %s) += 4;\n", reg);
488: break;
489: default:
490: abort ();
491: }
492: break;
493: case Apdi:
494: printf ("\tm68k_areg (regs, %s) = %sa;\n", reg, name);
495: break;
496: default:
497: break;
498: }
499: }
500:
1.1.1.12 root 501: static void genastore (const char *from, amodes mode, const char *reg,
502: wordsizes size, const char *to)
1.1 root 503: {
504: switch (mode) {
505: case Dreg:
506: switch (size) {
507: case sz_byte:
508: printf ("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from);
509: break;
510: case sz_word:
511: printf ("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from);
512: break;
513: case sz_long:
514: printf ("\tm68k_dreg(regs, %s) = (%s);\n", reg, from);
515: break;
516: default:
517: abort ();
518: }
519: break;
520: case Areg:
521: switch (size) {
522: case sz_word:
523: fprintf (stderr, "Foo\n");
524: printf ("\tm68k_areg(regs, %s) = (uae_s32)(uae_s16)(%s);\n", reg, from);
525: break;
526: case sz_long:
527: printf ("\tm68k_areg(regs, %s) = (%s);\n", reg, from);
528: break;
529: default:
530: abort ();
531: }
532: break;
533: case Aind:
534: case Aipi:
535: case Apdi:
536: case Ad16:
537: case Ad8r:
538: case absw:
539: case absl:
540: case PC16:
541: case PC8r:
542: if (using_prefetch)
543: sync_m68k_pc ();
544: switch (size) {
545: case sz_byte:
546: insn_n_cycles += 4;
547: printf ("\tput_byte(%sa,%s);\n", to, from);
548: break;
549: case sz_word:
550: insn_n_cycles += 4;
551: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
552: abort ();
553: printf ("\tput_word(%sa,%s);\n", to, from);
554: break;
555: case sz_long:
556: insn_n_cycles += 8;
557: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
558: abort ();
559: printf ("\tput_long(%sa,%s);\n", to, from);
560: break;
561: default:
562: abort ();
563: }
564: break;
565: case imm:
566: case imm0:
567: case imm1:
568: case imm2:
569: case immi:
570: abort ();
571: break;
572: default:
573: abort ();
574: }
575: }
576:
1.1.1.2 root 577:
1.1 root 578: static void genmovemel (uae_u16 opcode)
579: {
580: char getcode[100];
1.1.1.3 root 581: int bMovemLong = (table68k[opcode].size == sz_long);
582: int size = bMovemLong ? 4 : 2;
1.1 root 583:
1.1.1.3 root 584: if (bMovemLong) {
1.1 root 585: strcpy (getcode, "get_long(srca)");
586: } else {
587: strcpy (getcode, "(uae_s32)(uae_s16)get_word(srca)");
588: }
589:
590: printf ("\tuae_u16 mask = %s;\n", gen_nextiword ());
591: printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1.1.1.2 root 592: printf ("\tretcycles = 0;\n");
1.1.1.3 root 593: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1);
1.1 root 594: start_brace ();
1.1.1.2 root 595: printf ("\twhile (dmask) { m68k_dreg(regs, movem_index1[dmask]) = %s;"
1.1.1.3 root 596: " srca += %d; dmask = movem_next[dmask]; retcycles+=%d; }\n",
597: getcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 598: printf ("\twhile (amask) { m68k_areg(regs, movem_index1[amask]) = %s;"
1.1.1.3 root 599: " srca += %d; amask = movem_next[amask]; retcycles+=%d; }\n",
600: getcode, size, (bMovemLong ? 8 : 4));
1.1 root 601:
602: if (table68k[opcode].dmode == Aipi)
603: printf ("\tm68k_areg(regs, dstreg) = srca;\n");
1.1.1.2 root 604:
605: /* Better cycles - experimental! (Thothy) */
606: switch(table68k[opcode].dmode)
1.1.1.3 root 607: {
1.1.1.2 root 608: case Aind: insn_n_cycles=12; break;
609: case Aipi: insn_n_cycles=12; break;
610: case Ad16: insn_n_cycles=16; break;
611: case Ad8r: insn_n_cycles=18; break;
612: case absw: insn_n_cycles=16; break;
613: case absl: insn_n_cycles=20; break;
614: case PC16: insn_n_cycles=16; break;
615: case PC8r: insn_n_cycles=18; break;
1.1.1.3 root 616: }
617: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 618: }
619:
620: static void genmovemle (uae_u16 opcode)
621: {
622: char putcode[100];
1.1.1.3 root 623: int bMovemLong = (table68k[opcode].size == sz_long);
624: int size = bMovemLong ? 4 : 2;
625:
626: if (bMovemLong) {
1.1 root 627: strcpy (putcode, "put_long(srca,");
628: } else {
629: strcpy (putcode, "put_word(srca,");
630: }
631:
632: printf ("\tuae_u16 mask = %s;\n", gen_nextiword ());
1.1.1.3 root 633: printf ("\tretcycles = 0;\n");
1.1 root 634: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1);
635: if (using_prefetch)
636: sync_m68k_pc ();
637:
638: start_brace ();
639: if (table68k[opcode].dmode == Apdi) {
1.1.1.2 root 640: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
641: printf ("\twhile (amask) { srca -= %d; %s m68k_areg(regs, movem_index2[amask]));"
1.1.1.3 root 642: " amask = movem_next[amask]; retcycles+=%d; }\n",
643: size, putcode, (bMovemLong ? 8 : 4));
1.1.1.2 root 644: printf ("\twhile (dmask) { srca -= %d; %s m68k_dreg(regs, movem_index2[dmask]));"
1.1.1.3 root 645: " dmask = movem_next[dmask]; retcycles+=%d; }\n",
646: size, putcode, (bMovemLong ? 8 : 4));
1.1.1.2 root 647: printf ("\tm68k_areg(regs, dstreg) = srca;\n");
1.1 root 648: } else {
1.1.1.2 root 649: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
650: printf ("\twhile (dmask) { %s m68k_dreg(regs, movem_index1[dmask])); srca += %d;"
1.1.1.3 root 651: " dmask = movem_next[dmask]; retcycles+=%d; }\n",
652: putcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 653: printf ("\twhile (amask) { %s m68k_areg(regs, movem_index1[amask])); srca += %d;"
1.1.1.3 root 654: " amask = movem_next[amask]; retcycles+=%d; }\n",
655: putcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 656: }
657:
658: /* Better cycles - experimental! (Thothy) */
659: switch(table68k[opcode].dmode)
1.1.1.3 root 660: {
1.1.1.2 root 661: case Aind: insn_n_cycles=8; break;
662: case Apdi: insn_n_cycles=8; break;
663: case Ad16: insn_n_cycles=12; break;
664: case Ad8r: insn_n_cycles=14; break;
665: case absw: insn_n_cycles=12; break;
666: case absl: insn_n_cycles=16; break;
1.1.1.3 root 667: }
668: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 669: }
670:
1.1.1.2 root 671:
1.1 root 672: static void duplicate_carry (void)
673: {
674: printf ("\tCOPY_CARRY;\n");
675: }
676:
677: typedef enum
678: {
679: flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_zn,
680: flag_av, flag_sv
681: }
682: flagtypes;
683:
1.1.1.12 root 684: static void genflags_normal (flagtypes type, wordsizes size, const char *value,
685: const char *src, const char *dst)
1.1 root 686: {
687: char vstr[100], sstr[100], dstr[100];
688: char usstr[100], udstr[100];
689: char unsstr[100], undstr[100];
690:
691: switch (size) {
692: case sz_byte:
693: strcpy (vstr, "((uae_s8)(");
694: strcpy (usstr, "((uae_u8)(");
695: break;
696: case sz_word:
697: strcpy (vstr, "((uae_s16)(");
698: strcpy (usstr, "((uae_u16)(");
699: break;
700: case sz_long:
701: strcpy (vstr, "((uae_s32)(");
702: strcpy (usstr, "((uae_u32)(");
703: break;
704: default:
705: abort ();
706: }
707: strcpy (unsstr, usstr);
708:
709: strcpy (sstr, vstr);
710: strcpy (dstr, vstr);
711: strcat (vstr, value);
712: strcat (vstr, "))");
713: strcat (dstr, dst);
714: strcat (dstr, "))");
715: strcat (sstr, src);
716: strcat (sstr, "))");
717:
718: strcpy (udstr, usstr);
719: strcat (udstr, dst);
720: strcat (udstr, "))");
721: strcat (usstr, src);
722: strcat (usstr, "))");
723:
724: strcpy (undstr, unsstr);
725: strcat (unsstr, "-");
726: strcat (undstr, "~");
727: strcat (undstr, dst);
728: strcat (undstr, "))");
729: strcat (unsstr, src);
730: strcat (unsstr, "))");
731:
732: switch (type) {
733: case flag_logical_noclobber:
734: case flag_logical:
735: case flag_zn:
736: case flag_av:
737: case flag_sv:
738: case flag_addx:
739: case flag_subx:
740: break;
741:
742: case flag_add:
743: start_brace ();
744: printf ("uae_u32 %s = %s + %s;\n", value, dstr, sstr);
745: break;
746: case flag_sub:
747: case flag_cmp:
748: start_brace ();
749: printf ("uae_u32 %s = %s - %s;\n", value, dstr, sstr);
750: break;
751: }
752:
753: switch (type) {
754: case flag_logical_noclobber:
755: case flag_logical:
756: case flag_zn:
757: break;
758:
759: case flag_add:
760: case flag_sub:
761: case flag_addx:
762: case flag_subx:
763: case flag_cmp:
764: case flag_av:
765: case flag_sv:
766: start_brace ();
767: printf ("\t" BOOL_TYPE " flgs = %s < 0;\n", sstr);
768: printf ("\t" BOOL_TYPE " flgo = %s < 0;\n", dstr);
769: printf ("\t" BOOL_TYPE " flgn = %s < 0;\n", vstr);
770: break;
771: }
772:
773: switch (type) {
774: case flag_logical:
775: printf ("\tCLEAR_CZNV;\n");
776: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
777: printf ("\tSET_NFLG (%s < 0);\n", vstr);
778: break;
779: case flag_logical_noclobber:
780: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
781: printf ("\tSET_NFLG (%s < 0);\n", vstr);
782: break;
783: case flag_av:
784: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
785: break;
786: case flag_sv:
787: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
788: break;
789: case flag_zn:
790: printf ("\tSET_ZFLG (GET_ZFLG & (%s == 0));\n", vstr);
791: printf ("\tSET_NFLG (%s < 0);\n", vstr);
792: break;
793: case flag_add:
794: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
795: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
796: printf ("\tSET_CFLG (%s < %s);\n", undstr, usstr);
797: duplicate_carry ();
798: printf ("\tSET_NFLG (flgn != 0);\n");
799: break;
800: case flag_sub:
801: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
802: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
803: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
804: duplicate_carry ();
805: printf ("\tSET_NFLG (flgn != 0);\n");
806: break;
807: case flag_addx:
808: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n"); /* minterm SON: 0x42 */
809: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));\n"); /* minterm SON: 0xD4 */
810: duplicate_carry ();
811: break;
812: case flag_subx:
813: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));\n"); /* minterm SON: 0x24 */
814: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));\n"); /* minterm SON: 0xB2 */
815: duplicate_carry ();
816: break;
817: case flag_cmp:
818: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
819: printf ("\tSET_VFLG ((flgs != flgo) && (flgn != flgo));\n");
820: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
821: printf ("\tSET_NFLG (flgn != 0);\n");
822: break;
823: }
824: }
825:
1.1.1.12 root 826: static void genflags (flagtypes type, wordsizes size, const char *value,
827: const char *src, const char *dst)
1.1 root 828: {
829: /* Temporarily deleted 68k/ARM flag optimizations. I'd prefer to have
830: them in the appropriate m68k.h files and use just one copy of this
831: code here. The API can be changed if necessary. */
832: #ifdef OPTIMIZED_FLAGS
833: switch (type) {
834: case flag_add:
835: case flag_sub:
836: start_brace ();
837: printf ("\tuae_u32 %s;\n", value);
838: break;
839:
840: default:
841: break;
842: }
843:
844: /* At least some of those casts are fairly important! */
845: switch (type) {
846: case flag_logical_noclobber:
847: printf ("\t{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
848: if (strcmp (value, "0") == 0) {
849: printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n");
850: } else {
851: switch (size) {
852: case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
853: case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
854: case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
855: }
856: printf ("\tIOR_CZNV (oldcznv);\n");
857: }
858: printf ("\t}\n");
859: return;
860: case flag_logical:
861: if (strcmp (value, "0") == 0) {
862: printf ("\tSET_CZNV (FLAGVAL_Z);\n");
863: } else {
864: switch (size) {
865: case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
866: case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
867: case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
868: }
869: }
870: return;
871:
872: case flag_add:
873: switch (size) {
874: case sz_byte: printf ("\toptflag_addb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
875: case sz_word: printf ("\toptflag_addw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
876: case sz_long: printf ("\toptflag_addl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
877: }
878: return;
879:
880: case flag_sub:
881: switch (size) {
882: case sz_byte: printf ("\toptflag_subb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
883: case sz_word: printf ("\toptflag_subw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
884: case sz_long: printf ("\toptflag_subl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
885: }
886: return;
887:
888: case flag_cmp:
889: switch (size) {
890: case sz_byte: printf ("\toptflag_cmpb ((uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
891: case sz_word: printf ("\toptflag_cmpw ((uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
892: case sz_long: printf ("\toptflag_cmpl ((uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
893: }
894: return;
895:
896: default:
897: break;
898: }
899: #endif
900:
901: genflags_normal (type, size, value, src, dst);
902: }
903:
904: static void force_range_for_rox (const char *var, wordsizes size)
905: {
906: /* Could do a modulo operation here... which one is faster? */
907: switch (size) {
908: case sz_long:
909: printf ("\tif (%s >= 33) %s -= 33;\n", var, var);
910: break;
911: case sz_word:
912: printf ("\tif (%s >= 34) %s -= 34;\n", var, var);
913: printf ("\tif (%s >= 17) %s -= 17;\n", var, var);
914: break;
915: case sz_byte:
916: printf ("\tif (%s >= 36) %s -= 36;\n", var, var);
917: printf ("\tif (%s >= 18) %s -= 18;\n", var, var);
918: printf ("\tif (%s >= 9) %s -= 9;\n", var, var);
919: break;
920: }
921: }
922:
923: static const char *cmask (wordsizes size)
924: {
925: switch (size) {
926: case sz_byte: return "0x80";
927: case sz_word: return "0x8000";
928: case sz_long: return "0x80000000";
929: default: abort ();
930: }
931: }
932:
933: static int source_is_imm1_8 (struct instr *i)
934: {
935: return i->stype == 3;
936: }
937:
1.1.1.2 root 938:
939:
1.1 root 940: static void gen_opcode (unsigned long int opcode)
941: {
1.1.1.2 root 942: #if 0
943: char *amodenames[] = { "Dreg", "Areg", "Aind", "Aipi", "Apdi", "Ad16", "Ad8r",
944: "absw", "absl", "PC16", "PC8r", "imm", "imm0", "imm1", "imm2", "immi", "am_unknown", "am_illg"};
945: #endif
946:
1.1 root 947: struct instr *curi = table68k + opcode;
948: insn_n_cycles = 4;
949:
1.1.1.8 root 950: /* Store the family of the instruction (used to check for pairing on ST)
951: * and leave some space for patching in the current cycles later */
952: printf ("\tOpcodeFamily = %d; CurrentInstrCycles = \n", curi->mnemo);
953: nCurInstrCycPos = ftell(stdout) - 5;
954:
1.1 root 955: start_brace ();
956: m68k_pc_offset = 2;
1.1.1.2 root 957:
1.1 root 958: switch (curi->plev) {
959: case 0: /* not privileged */
960: break;
961: case 1: /* unprivileged only on 68000 */
962: if (cpu_level == 0)
963: break;
964: if (next_cpu_level < 0)
965: next_cpu_level = 0;
966:
967: /* fall through */
968: case 2: /* priviledged */
1.1.1.12 root 969: printf ("if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 970: need_endlabel = 1;
971: start_brace ();
972: break;
973: case 3: /* privileged if size == word */
974: if (curi->size == sz_byte)
975: break;
1.1.1.12 root 976: printf ("if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 977: need_endlabel = 1;
978: start_brace ();
979: break;
980: }
1.1.1.2 root 981:
982: /* Build the opcodes: */
1.1 root 983: switch (curi->mnemo) {
984: case i_OR:
985: case i_AND:
986: case i_EOR:
1.1.1.2 root 987: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
988: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
989: printf ("\tsrc %c= dst;\n", curi->mnemo == i_OR ? '|' : curi->mnemo == i_AND ? '&' : '^');
1.1.1.17 root 990:
991: if ( ( curi->smode == Dreg ) && ( curi->dmode == absl ) ) // FIXME [NP] eor.x Dn,xxxx.l (Xenon 2 : eor.w d0,$40760)
992: printf("\trefill_prefetch (m68k_getpc(), 6);\n"); // FIXME [NP] need better prefetch emulation
993: else
994: printf("\trefill_prefetch (m68k_getpc(), 2);\n"); // FIXME [NP] eor.w d0,(a2)+ (Operation Clean Streets - Automation 168, need better prefetch emulation)
1.1.1.2 root 995: genflags (flag_logical, curi->size, "src", "", "");
996: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
997: if(curi->size==sz_long && curi->dmode==Dreg)
998: {
999: insn_n_cycles += 2;
1000: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
1001: insn_n_cycles += 2;
1002: }
1003: #if 0
1004: /* Output the CPU cycles: */
1005: fprintf(stderr,"MOVE, size %i: ",curi->size);
1006: fprintf(stderr," %s ->",amodenames[curi->smode]);
1007: fprintf(stderr," %s ",amodenames[curi->dmode]);
1008: fprintf(stderr," Cycles: %i\n",insn_n_cycles);
1009: #endif
1010: break;
1.1 root 1011: case i_ORSR:
1012: case i_EORSR:
1.1.1.2 root 1013: printf ("\tMakeSR();\n");
1014: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1015: if (curi->size == sz_byte) {
1016: printf ("\tsrc &= 0xFF;\n");
1017: }
1018: printf ("\tregs.sr %c= src;\n", curi->mnemo == i_EORSR ? '^' : '|');
1019: printf ("\tMakeFromSR();\n");
1020: insn_n_cycles = 20;
1021: break;
1.1 root 1022: case i_ANDSR:
1.1.1.2 root 1023: printf ("\tMakeSR();\n");
1024: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1025: if (curi->size == sz_byte) {
1026: printf ("\tsrc |= 0xFF00;\n");
1027: }
1028: printf ("\tregs.sr &= src;\n");
1029: printf ("\tMakeFromSR();\n");
1030: insn_n_cycles = 20;
1031: break;
1.1 root 1032: case i_SUB:
1033: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1034: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1035: start_brace ();
1.1.1.17 root 1036: printf("\trefill_prefetch (m68k_getpc(), 2);\n"); // FIXME [NP] similar to i_ADD, need better prefetch emulation
1.1 root 1037: genflags (flag_sub, curi->size, "newv", "src", "dst");
1038: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1039: if(curi->size==sz_long && curi->dmode==Dreg)
1040: {
1041: insn_n_cycles += 2;
1042: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
1043: insn_n_cycles += 2;
1044: }
1.1 root 1045: break;
1046: case i_SUBA:
1047: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1048: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1049: start_brace ();
1050: printf ("\tuae_u32 newv = dst - src;\n");
1051: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.2 root 1052: if(curi->size==sz_long && curi->smode!=Dreg && curi->smode!=Areg && !(curi->smode>=imm && curi->smode<=immi))
1053: insn_n_cycles += 2;
1054: else
1055: insn_n_cycles += 4;
1.1 root 1056: break;
1057: case i_SUBX:
1058: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1059: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1060: start_brace ();
1061: printf ("\tuae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);\n");
1062: genflags (flag_subx, curi->size, "newv", "src", "dst");
1063: genflags (flag_zn, curi->size, "newv", "", "");
1064: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1065: if(curi->smode==Dreg && curi->size==sz_long)
1066: insn_n_cycles=8;
1067: if(curi->smode==Apdi)
1068: {
1069: if(curi->size==sz_long)
1070: insn_n_cycles=30;
1071: else
1072: insn_n_cycles=18;
1073: }
1.1 root 1074: break;
1075: case i_SBCD:
1076: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1077: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1078: start_brace ();
1079: printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
1080: printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
1.1.1.4 root 1081: printf ("\tuae_u16 newv, tmp_newv;\n");
1082: printf ("\tint bcd = 0;\n");
1083: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
1084: printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
1085: printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
1086: printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);\n");
1.1 root 1087: duplicate_carry ();
1088: genflags (flag_zn, curi->size, "newv", "", "");
1.1.1.4 root 1089: printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
1.1 root 1090: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.4 root 1091: if(curi->smode==Dreg) insn_n_cycles=6;
1092: if(curi->smode==Apdi) insn_n_cycles=18;
1.1 root 1093: break;
1094: case i_ADD:
1095: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1096: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1097: start_brace ();
1.1.1.8 root 1098: printf("\trefill_prefetch (m68k_getpc(), 2);\n"); // FIXME [NP] For Transbeauce 2 demo, need better prefetch emulation
1.1 root 1099: genflags (flag_add, curi->size, "newv", "src", "dst");
1100: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1101: if(curi->size==sz_long && curi->dmode==Dreg)
1102: {
1103: insn_n_cycles += 2;
1104: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
1105: insn_n_cycles += 2;
1106: }
1.1 root 1107: break;
1108: case i_ADDA:
1109: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1110: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1111: start_brace ();
1112: printf ("\tuae_u32 newv = dst + src;\n");
1113: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.2 root 1114: if(curi->size==sz_long && curi->smode!=Dreg && curi->smode!=Areg && !(curi->smode>=imm && curi->smode<=immi))
1115: insn_n_cycles += 2;
1116: else
1117: insn_n_cycles += 4;
1.1 root 1118: break;
1119: case i_ADDX:
1120: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1121: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1122: start_brace ();
1123: printf ("\tuae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);\n");
1124: genflags (flag_addx, curi->size, "newv", "src", "dst");
1125: genflags (flag_zn, curi->size, "newv", "", "");
1126: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1127: if(curi->smode==Dreg && curi->size==sz_long)
1128: insn_n_cycles=8;
1129: if(curi->smode==Apdi)
1130: {
1131: if(curi->size==sz_long)
1132: insn_n_cycles=30;
1133: else
1134: insn_n_cycles=18;
1135: }
1.1 root 1136: break;
1137: case i_ABCD:
1138: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1139: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1140: start_brace ();
1141: printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);\n");
1142: printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
1.1.1.4 root 1143: printf ("\tuae_u16 newv, tmp_newv;\n");
1.1 root 1144: printf ("\tint cflg;\n");
1.1.1.4 root 1145: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;");
1146: printf ("\tif (newv_lo > 9) { newv += 6; }\n");
1147: printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
1148: printf ("\tif (cflg) newv += 0x60;\n");
1.1 root 1149: printf ("\tSET_CFLG (cflg);\n");
1150: duplicate_carry ();
1151: genflags (flag_zn, curi->size, "newv", "", "");
1.1.1.4 root 1152: printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
1.1 root 1153: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.4 root 1154: if(curi->smode==Dreg) insn_n_cycles=6;
1155: if(curi->smode==Apdi) insn_n_cycles=18;
1.1 root 1156: break;
1157: case i_NEG:
1158: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1159: start_brace ();
1.1.1.17 root 1160: printf("\trefill_prefetch (m68k_getpc(), 2);\n"); // FIXME [NP] similar to i_ADD/i_EOR, need better prefetch emulation
1.1 root 1161: genflags (flag_sub, curi->size, "dst", "src", "0");
1162: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1163: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1164: break;
1165: case i_NEGX:
1166: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1167: start_brace ();
1.1.1.17 root 1168: printf("\trefill_prefetch (m68k_getpc(), 2);\n"); // FIXME [NP] similar to i_ADD/i_EOR, need better prefetch emulation
1.1 root 1169: printf ("\tuae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);\n");
1170: genflags (flag_subx, curi->size, "newv", "src", "0");
1171: genflags (flag_zn, curi->size, "newv", "", "");
1172: genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1173: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1174: break;
1175: case i_NBCD:
1176: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1177: start_brace ();
1178: printf ("\tuae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
1179: printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
1180: printf ("\tuae_u16 newv;\n");
1181: printf ("\tint cflg;\n");
1.1.1.4 root 1182: printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
1183: printf ("\tnewv = newv_hi + newv_lo;");
1184: printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
1185: printf ("\tif (cflg) newv -= 0x60;\n");
1.1 root 1186: printf ("\tSET_CFLG (cflg);\n");
1187: duplicate_carry();
1188: genflags (flag_zn, curi->size, "newv", "", "");
1189: genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1.1.1.4 root 1190: if(curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1191: break;
1192: case i_CLR:
1193: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1.1.1.8 root 1194:
1195: /* [NP] CLR does a read before the write only on 68000 */
1196: /* but there's no cycle penalty for doing the read */
1197: if ( curi->smode != Dreg ) // only if destination is memory
1198: {
1199: if (curi->size==sz_byte)
1200: printf ("\tuae_s8 src = get_byte(srca);\n");
1201: else if (curi->size==sz_word)
1202: printf ("\tuae_s16 src = get_word(srca);\n");
1203: else if (curi->size==sz_long)
1204: printf ("\tuae_s32 src = get_long(srca);\n");
1205: }
1206:
1.1 root 1207: genflags (flag_logical, curi->size, "0", "", "");
1208: genastore ("0", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1209: if(curi->size==sz_long)
1.1.1.3 root 1210: {
1.1.1.2 root 1211: if(curi->smode==Dreg)
1212: insn_n_cycles += 2;
1213: else
1214: insn_n_cycles += 4;
1.1.1.3 root 1215: }
1.1.1.2 root 1216: if(curi->smode!=Dreg)
1217: insn_n_cycles += 4;
1.1 root 1218: break;
1219: case i_NOT:
1220: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1221: start_brace ();
1.1.1.17 root 1222: printf("\trefill_prefetch (m68k_getpc(), 2);\n"); // FIXME [NP] similar to i_ADD/i_EOR, need better prefetch emulation
1.1 root 1223: printf ("\tuae_u32 dst = ~src;\n");
1224: genflags (flag_logical, curi->size, "dst", "", "");
1225: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1226: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1227: break;
1228: case i_TST:
1229: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1230: genflags (flag_logical, curi->size, "src", "", "");
1231: break;
1232: case i_BTST:
1233: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1234: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1235: if (curi->size == sz_byte)
1236: printf ("\tsrc &= 7;\n");
1237: else
1238: printf ("\tsrc &= 31;\n");
1239: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1.1.1.2 root 1240: if(curi->dmode==Dreg) insn_n_cycles += 2;
1.1 root 1241: break;
1242: case i_BCHG:
1243: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1244: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1245: if (curi->size == sz_byte)
1246: printf ("\tsrc &= 7;\n");
1247: else
1248: printf ("\tsrc &= 31;\n");
1249: printf ("\tdst ^= (1 << src);\n");
1250: printf ("\tSET_ZFLG (((uae_u32)dst & (1 << src)) >> src);\n");
1251: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1252: if(curi->dmode==Dreg) insn_n_cycles += 4;
1.1 root 1253: break;
1254: case i_BCLR:
1255: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1256: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1257: if (curi->size == sz_byte)
1258: printf ("\tsrc &= 7;\n");
1259: else
1260: printf ("\tsrc &= 31;\n");
1261: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1262: printf ("\tdst &= ~(1 << src);\n");
1263: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1264: if(curi->dmode==Dreg) insn_n_cycles += 6;
1.1.1.8 root 1265: /* [NP] BCLR #n,Dx takes 12 cycles instead of 14 if n<16 */
1266: if((curi->smode==imm1) && (curi->dmode==Dreg))
1267: printf ("\tif ( src < 16 ) { m68k_incpc(4); return 12; }\n");
1268: /* [NP] BCLR Dy,Dx takes 8 cycles instead of 10 if Dy<16 */
1269: if((curi->smode==Dreg) && (curi->dmode==Dreg))
1270: printf ("\tif ( src < 16 ) { m68k_incpc(2); return 8; }\n");
1.1 root 1271: break;
1272: case i_BSET:
1273: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1274: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1275: if (curi->size == sz_byte)
1276: printf ("\tsrc &= 7;\n");
1277: else
1278: printf ("\tsrc &= 31;\n");
1279: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1280: printf ("\tdst |= (1 << src);\n");
1281: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1282: if(curi->dmode==Dreg) insn_n_cycles += 4;
1.1 root 1283: break;
1284: case i_CMPM:
1285: case i_CMP:
1286: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1287: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1288: start_brace ();
1289: genflags (flag_cmp, curi->size, "newv", "src", "dst");
1.1.1.2 root 1290: if(curi->size==sz_long && curi->dmode==Dreg)
1291: insn_n_cycles += 2;
1.1 root 1292: break;
1293: case i_CMPA:
1294: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1295: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1296: start_brace ();
1297: genflags (flag_cmp, sz_long, "newv", "src", "dst");
1.1.1.2 root 1298: insn_n_cycles += 2;
1.1 root 1299: break;
1300: /* The next two are coded a little unconventional, but they are doing
1301: * weird things... */
1302: case i_MVPRM:
1303: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1304:
1305: printf ("\tuaecptr memp = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword ());
1.1.1.16 root 1306: /* [NP] Use MovepByteNbr to keep track of each access inside a movep */
1.1 root 1307: if (curi->size == sz_word) {
1.1.1.14 root 1308: printf ("\tMovepByteNbr=1; put_byte(memp, src >> 8); MovepByteNbr=2; put_byte(memp + 2, src);\n");
1.1 root 1309: } else {
1.1.1.14 root 1310: printf ("\tMovepByteNbr=1; put_byte(memp, src >> 24); MovepByteNbr=2; put_byte(memp + 2, src >> 16);\n");
1311: printf ("\tMovepByteNbr=3; put_byte(memp + 4, src >> 8); MovepByteNbr=4; put_byte(memp + 6, src);\n");
1.1 root 1312: }
1.1.1.16 root 1313: printf ("\tMovepByteNbr=0;\n");
1.1.1.2 root 1314: if(curi->size==sz_long) insn_n_cycles=24; else insn_n_cycles=16;
1.1 root 1315: break;
1316: case i_MVPMR:
1317: printf ("\tuaecptr memp = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword ());
1318: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1.1.1.16 root 1319: /* [NP] Use MovepByteNbr to keep track of each access inside a movep */
1.1 root 1320: if (curi->size == sz_word) {
1.1.1.16 root 1321: //printf ("\tuae_u16 val = (get_byte(memp) << 8) + get_byte(memp + 2);\n");
1322: printf ("\tuae_u16 val;\n");
1323: printf ("\tMovepByteNbr=1; val = (get_byte(memp) << 8);\n");
1324: printf ("\tMovepByteNbr=2; val += get_byte(memp + 2);\n");
1.1 root 1325: } else {
1.1.1.16 root 1326: //printf ("\tuae_u32 val = (get_byte(memp) << 24) + (get_byte(memp + 2) << 16)\n");
1327: //printf (" + (get_byte(memp + 4) << 8) + get_byte(memp + 6);\n");
1328: printf ("\tuae_u32 val;\n");
1329: printf ("\tMovepByteNbr=1; val = (get_byte(memp) << 24);\n");
1330: printf ("\tMovepByteNbr=2; val += (get_byte(memp + 2) << 16);\n");
1331: printf ("\tMovepByteNbr=3; val += (get_byte(memp + 4) << 8);\n");
1332: printf ("\tMovepByteNbr=4; val += get_byte(memp + 6);\n");
1.1 root 1333: }
1.1.1.16 root 1334: printf ("\tMovepByteNbr=0;\n");
1.1 root 1335: genastore ("val", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1336: if(curi->size==sz_long) insn_n_cycles=24; else insn_n_cycles=16;
1.1 root 1337: break;
1338: case i_MOVE:
1339: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1340: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1.1.1.8 root 1341:
1342: /* [NP] genamode counts 2 cycles if dest is -(An), this is wrong. */
1343: /* For move dest (An), (An)+ and -(An) take the same time */
1344: /* (for other instr, dest -(An) really takes 2 cycles more) */
1345: if ( curi->dmode == Apdi )
1346: insn_n_cycles -= 2; /* correct the wrong cycle count for -(An) */
1347:
1.1.1.17 root 1348: if ( ( curi->smode == Dreg ) && ( curi->dmode == absl ) ) // FIXME [NP] move.x Dn,xxxx.l (Union Demo : move.w d1,$4c)
1349: // FIXME [NP] move.x Dn,xxxx.l (Darkman : move.w d2,$2c04)
1350: printf("\trefill_prefetch (m68k_getpc(), 4);\n"); // FIXME [NP] need better prefetch emulation
1351:
1352: else if ( (curi->size==sz_long) && ( curi->smode == imm ) && ( curi->dmode == Aind ) ) // FIXME [NP] move.l #$xxxx,(An) (Titan : move.l #$b0b0caca,(a4))
1353: printf("\trefill_prefetch (m68k_getpc(), 4);\n"); // FIXME [NP] need better prefetch emulation
1354:
1355: else if ( (curi->size==sz_long) && ( curi->smode == Dreg ) && ( curi->dmode == Aind ) ) // FIXME [NP] move.l Dn,(An) (Int 3D Tennis : move.l d0,(a0))
1356: printf("\trefill_prefetch (m68k_getpc(), 0);\n"); // FIXME [NP] need better prefetch emulation
1357:
1.1 root 1358: genflags (flag_logical, curi->size, "src", "", "");
1359: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
1360: break;
1361: case i_MOVEA:
1362: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1363: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1364: if (curi->size == sz_word) {
1365: printf ("\tuae_u32 val = (uae_s32)(uae_s16)src;\n");
1366: } else {
1367: printf ("\tuae_u32 val = src;\n");
1368: }
1369: genastore ("val", curi->dmode, "dstreg", sz_long, "dst");
1370: break;
1.1.1.2 root 1371: case i_MVSR2: /* Move from SR */
1.1 root 1372: genamode (curi->smode, "srcreg", sz_word, "src", 2, 0);
1373: printf ("\tMakeSR();\n");
1374: if (curi->size == sz_byte)
1375: genastore ("regs.sr & 0xff", curi->smode, "srcreg", sz_word, "src");
1376: else
1377: genastore ("regs.sr", curi->smode, "srcreg", sz_word, "src");
1.1.1.2 root 1378: if (curi->smode==Dreg) insn_n_cycles += 2; else insn_n_cycles += 4;
1.1 root 1379: break;
1.1.1.2 root 1380: case i_MV2SR: /* Move to SR */
1.1 root 1381: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1382: if (curi->size == sz_byte)
1383: printf ("\tMakeSR();\n\tregs.sr &= 0xFF00;\n\tregs.sr |= src & 0xFF;\n");
1384: else {
1385: printf ("\tregs.sr = src;\n");
1386: }
1387: printf ("\tMakeFromSR();\n");
1.1.1.2 root 1388: insn_n_cycles += 8;
1.1 root 1389: break;
1390: case i_SWAP:
1391: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1392: start_brace ();
1393: printf ("\tuae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);\n");
1394: genflags (flag_logical, sz_long, "dst", "", "");
1395: genastore ("dst", curi->smode, "srcreg", sz_long, "src");
1396: break;
1397: case i_EXG:
1398: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1399: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1400: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1401: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1402: insn_n_cycles = 6;
1.1 root 1403: break;
1404: case i_EXT:
1405: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1406: start_brace ();
1407: switch (curi->size) {
1408: case sz_byte: printf ("\tuae_u32 dst = (uae_s32)(uae_s8)src;\n"); break;
1409: case sz_word: printf ("\tuae_u16 dst = (uae_s16)(uae_s8)src;\n"); break;
1410: case sz_long: printf ("\tuae_u32 dst = (uae_s32)(uae_s16)src;\n"); break;
1411: default: abort ();
1412: }
1413: genflags (flag_logical,
1414: curi->size == sz_word ? sz_word : sz_long, "dst", "", "");
1415: genastore ("dst", curi->smode, "srcreg",
1416: curi->size == sz_word ? sz_word : sz_long, "src");
1417: break;
1418: case i_MVMEL:
1419: genmovemel (opcode);
1420: break;
1421: case i_MVMLE:
1422: genmovemle (opcode);
1423: break;
1424: case i_TRAP:
1425: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1426: sync_m68k_pc ();
1.1.1.12 root 1427: printf ("\tException(src+32,0,M68000_EXC_SRC_CPU);\n");
1.1 root 1428: m68k_pc_offset = 0;
1429: break;
1430: case i_MVR2USP:
1431: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1432: printf ("\tregs.usp = src;\n");
1433: break;
1434: case i_MVUSP2R:
1435: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1436: genastore ("regs.usp", curi->smode, "srcreg", curi->size, "src");
1437: break;
1438: case i_RESET:
1439: printf ("\tcustomreset();\n");
1.1.1.2 root 1440: insn_n_cycles = 132; /* I am not so sure about this!? - Thothy */
1.1 root 1441: break;
1442: case i_NOP:
1443: break;
1444: case i_STOP:
1445: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1446: printf ("\tregs.sr = src;\n");
1447: printf ("\tMakeFromSR();\n");
1448: printf ("\tm68k_setstopped(1);\n");
1.1.1.2 root 1449: insn_n_cycles = 4;
1.1 root 1450: break;
1451: case i_RTE:
1452: if (cpu_level == 0) {
1453: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1454: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1.1.1.18! root 1455: printf ("\tregs.sr = sr;\n");
1.1 root 1456: printf ("\tMakeFromSR();\n");
1.1.1.18! root 1457: if (using_exception_3) {
! 1458: printf ("\tif (pc & 1) {\n");
! 1459: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc ();\n");
! 1460: printf ("\t\tlast_fault_for_exception_3 = pc;\n");
! 1461: printf ("\t\tlast_instructionaccess_for_exception_3 = 1;\n");
! 1462: printf ("\t\tlast_writeaccess_for_exception_3 = 0;\n");
! 1463: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
! 1464: printf ("\t}\n");
! 1465: need_endlabel = 1;
! 1466: }
! 1467: printf ("\tm68k_setpc_rte(pc);\n");
! 1468: fill_prefetch_0 ();
1.1 root 1469: } else {
1470: int old_brace_level = n_braces;
1471: if (next_cpu_level < 0)
1472: next_cpu_level = 0;
1473: printf ("\tuae_u16 newsr; uae_u32 newpc; for (;;) {\n");
1474: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1475: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1476: genamode (Aipi, "7", sz_word, "format", 1, 0);
1477: printf ("\tnewsr = sr; newpc = pc;\n");
1478: printf ("\tif ((format & 0xF000) == 0x0000) { break; }\n");
1479: printf ("\telse if ((format & 0xF000) == 0x1000) { ; }\n");
1480: printf ("\telse if ((format & 0xF000) == 0x2000) { m68k_areg(regs, 7) += 4; break; }\n");
1481: printf ("\telse if ((format & 0xF000) == 0x8000) { m68k_areg(regs, 7) += 50; break; }\n");
1482: printf ("\telse if ((format & 0xF000) == 0x9000) { m68k_areg(regs, 7) += 12; break; }\n");
1483: printf ("\telse if ((format & 0xF000) == 0xa000) { m68k_areg(regs, 7) += 24; break; }\n");
1484: printf ("\telse if ((format & 0xF000) == 0xb000) { m68k_areg(regs, 7) += 84; break; }\n");
1.1.1.12 root 1485: printf ("\telse { Exception(14,0,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 1486: printf ("\tregs.sr = newsr; MakeFromSR();\n}\n");
1487: pop_braces (old_brace_level);
1488: printf ("\tregs.sr = newsr; MakeFromSR();\n");
1.1.1.18! root 1489: if (using_exception_3) {
! 1490: printf ("\tif (newpc & 1) {\n");
! 1491: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc ();\n");
! 1492: printf ("\t\tlast_fault_for_exception_3 = newpc;\n");
! 1493: printf ("\t\tlast_instructionaccess_for_exception_3 = 1;\n");
! 1494: printf ("\t\tlast_writeaccess_for_exception_3 = 0;\n");
! 1495: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
! 1496: printf ("\t}\n");
! 1497: need_endlabel = 1;
! 1498: }
1.1 root 1499: printf ("\tm68k_setpc_rte(newpc);\n");
1500: fill_prefetch_0 ();
1501: need_endlabel = 1;
1502: }
1503: /* PC is set and prefetch filled. */
1504: m68k_pc_offset = 0;
1.1.1.2 root 1505: insn_n_cycles = 20;
1.1 root 1506: break;
1507: case i_RTD:
1508: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1509: genamode (curi->smode, "srcreg", curi->size, "offs", 1, 0);
1510: printf ("\tm68k_areg(regs, 7) += offs;\n");
1.1.1.18! root 1511: if (using_exception_3) {
! 1512: printf ("\tif (pc & 1) {\n");
! 1513: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc ();\n");
! 1514: printf ("\t\tlast_fault_for_exception_3 = pc;\n");
! 1515: printf ("\t\tlast_instructionaccess_for_exception_3 = 1;\n");
! 1516: printf ("\t\tlast_writeaccess_for_exception_3 = 0;\n");
! 1517: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
! 1518: printf ("\t}\n");
! 1519: need_endlabel = 1;
! 1520: }
1.1 root 1521: printf ("\tm68k_setpc_rte(pc);\n");
1522: fill_prefetch_0 ();
1523: /* PC is set and prefetch filled. */
1524: m68k_pc_offset = 0;
1525: break;
1526: case i_LINK:
1527: genamode (Apdi, "7", sz_long, "old", 2, 0);
1528: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1529: genastore ("src", Apdi, "7", sz_long, "old");
1530: genastore ("m68k_areg(regs, 7)", curi->smode, "srcreg", sz_long, "src");
1531: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0);
1532: printf ("\tm68k_areg(regs, 7) += offs;\n");
1533: break;
1534: case i_UNLK:
1535: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1536: printf ("\tm68k_areg(regs, 7) = src;\n");
1537: genamode (Aipi, "7", sz_long, "old", 1, 0);
1538: genastore ("old", curi->smode, "srcreg", curi->size, "src");
1539: break;
1540: case i_RTS:
1.1.1.18! root 1541: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
1.1 root 1542: printf ("\tm68k_do_rts();\n");
1.1.1.18! root 1543: if (using_exception_3) {
! 1544: printf ("\tif (m68k_getpc () & 1) {\n");
! 1545: printf ("\t\tlast_addr_for_exception_3 = oldpc;\n");
! 1546: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc ();\n");
! 1547: printf ("\t\tlast_instructionaccess_for_exception_3 = 1;\n");
! 1548: printf ("\t\tlast_writeaccess_for_exception_3 = 0;\n");
! 1549: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
! 1550: printf ("\t}\n");
! 1551: need_endlabel = 1;
! 1552: }
1.1 root 1553: fill_prefetch_0 ();
1554: m68k_pc_offset = 0;
1.1.1.2 root 1555: insn_n_cycles = 16;
1.1 root 1556: break;
1557: case i_TRAPV:
1558: sync_m68k_pc ();
1.1.1.12 root 1559: printf ("\tif (GET_VFLG) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 1560: need_endlabel = 1;
1561: break;
1562: case i_RTR:
1563: printf ("\tMakeSR();\n");
1564: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1565: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1566: printf ("\tregs.sr &= 0xFF00; sr &= 0xFF;\n");
1.1.1.18! root 1567: printf ("\tregs.sr |= sr;\n");
1.1 root 1568: printf ("\tMakeFromSR();\n");
1.1.1.18! root 1569: if (using_exception_3) {
! 1570: printf ("\tif (pc & 1) {\n");
! 1571: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc ();\n");
! 1572: printf ("\t\tlast_fault_for_exception_3 = pc;\n");
! 1573: printf ("\t\tlast_instructionaccess_for_exception_3 = 1;\n");
! 1574: printf ("\t\tlast_writeaccess_for_exception_3 = 0;\n");
! 1575: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
! 1576: printf ("\t}\n");
! 1577: need_endlabel = 1;
! 1578: }
! 1579: printf ("m68k_setpc(pc);\n");
! 1580: fill_prefetch_0 ();
1.1 root 1581: m68k_pc_offset = 0;
1.1.1.2 root 1582: insn_n_cycles = 20;
1.1 root 1583: break;
1584: case i_JSR:
1585: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1.1.1.13 root 1586: printf ("\tuaecptr oldpc = m68k_getpc () + %d;\n", m68k_pc_offset);
1587: if (using_exception_3) {
1588: printf ("\tif (srca & 1) {\n");
1589: printf ("\t\tlast_addr_for_exception_3 = oldpc;\n");
1590: printf ("\t\tlast_fault_for_exception_3 = srca;\n");
1.1.1.18! root 1591: printf ("\t\tlast_instructionaccess_for_exception_3 = 1;\n");
! 1592: printf ("\t\tlast_writeaccess_for_exception_3 = 0;\n");
1.1.1.13 root 1593: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
1594: printf ("\t}\n");
1595: need_endlabel = 1;
1596: }
1.1 root 1597: printf ("\tm68k_do_jsr(m68k_getpc() + %d, srca);\n", m68k_pc_offset);
1598: fill_prefetch_0 ();
1599: m68k_pc_offset = 0;
1.1.1.2 root 1600: switch(curi->smode)
1601: {
1602: case Aind: insn_n_cycles=16; break;
1603: case Ad16: insn_n_cycles=18; break;
1604: case Ad8r: insn_n_cycles=22; break;
1605: case absw: insn_n_cycles=18; break;
1606: case absl: insn_n_cycles=20; break;
1607: case PC16: insn_n_cycles=18; break;
1608: case PC8r: insn_n_cycles=22; break;
1609: }
1.1 root 1610: break;
1611: case i_JMP:
1612: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1.1.1.13 root 1613: if (using_exception_3) {
1614: printf ("\tif (srca & 1) {\n");
1.1.1.18! root 1615: if ( opcode == 0x4ef8 ) // [NP] jmp xxx.w
! 1616: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n"); // [NP] last_addr is pc+2
! 1617: else
! 1618: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + %d;\n" , m68k_pc_offset); // [NP] last_addr is not pc+6
1.1.1.13 root 1619: printf ("\t\tlast_fault_for_exception_3 = srca;\n");
1.1.1.18! root 1620: printf ("\t\tlast_instructionaccess_for_exception_3 = 1;\n");
! 1621: printf ("\t\tlast_writeaccess_for_exception_3 = 0;\n");
1.1.1.13 root 1622: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
1623: printf ("\t}\n");
1624: need_endlabel = 1;
1625: }
1.1 root 1626: printf ("\tm68k_setpc(srca);\n");
1627: fill_prefetch_0 ();
1628: m68k_pc_offset = 0;
1.1.1.2 root 1629: switch(curi->smode)
1630: {
1631: case Aind: insn_n_cycles=8; break;
1632: case Ad16: insn_n_cycles=10; break;
1633: case Ad8r: insn_n_cycles=14; break;
1634: case absw: insn_n_cycles=10; break;
1635: case absl: insn_n_cycles=12; break;
1636: case PC16: insn_n_cycles=10; break;
1637: case PC8r: insn_n_cycles=14; break;
1638: }
1.1 root 1639: break;
1640: case i_BSR:
1641: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1642: printf ("\tuae_s32 s = (uae_s32)src + 2;\n");
1643: if (using_exception_3) {
1644: printf ("\tif (src & 1) {\n");
1.1.1.13 root 1645: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n"); // [NP] FIXME should be +4, not +2 (same as DBcc) ?
1.1 root 1646: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + s;\n");
1.1.1.18! root 1647: printf ("\t\tlast_instructionaccess_for_exception_3 = 1;\n");
! 1648: printf ("\t\tlast_writeaccess_for_exception_3 = 0;\n");
1.1.1.12 root 1649: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1650: printf ("\t}\n");
1651: need_endlabel = 1;
1652: }
1653: printf ("\tm68k_do_bsr(m68k_getpc() + %d, s);\n", m68k_pc_offset);
1654: fill_prefetch_0 ();
1655: m68k_pc_offset = 0;
1.1.1.2 root 1656: insn_n_cycles = 18;
1.1 root 1657: break;
1658: case i_Bcc:
1659: if (curi->size == sz_long) {
1660: if (cpu_level < 2) {
1661: printf ("\tm68k_incpc(2);\n");
1662: printf ("\tif (!cctrue(%d)) goto %s;\n", curi->cc, endlabelstr);
1663: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n");
1664: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + 1;\n");
1.1.1.18! root 1665: printf ("\t\tlast_instructionaccess_for_exception_3 = 1;\n");
! 1666: printf ("\t\tlast_writeaccess_for_exception_3 = 0;\n");
1.1.1.12 root 1667: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1668: need_endlabel = 1;
1669: } else {
1670: if (next_cpu_level < 1)
1671: next_cpu_level = 1;
1672: }
1673: }
1674: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1675: printf ("\tif (!cctrue(%d)) goto didnt_jump;\n", curi->cc);
1676: if (using_exception_3) {
1677: printf ("\tif (src & 1) {\n");
1.1.1.8 root 1678: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n"); // [NP] FIXME should be +4, not +2 (same as DBcc) ?
1.1 root 1679: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;\n");
1.1.1.18! root 1680: printf ("\t\tlast_instructionaccess_for_exception_3 = 1;\n");
! 1681: printf ("\t\tlast_writeaccess_for_exception_3 = 0;\n");
1.1.1.12 root 1682: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1683: printf ("\t}\n");
1684: need_endlabel = 1;
1685: }
1686: printf ("\tm68k_incpc ((uae_s32)src + 2);\n");
1687: fill_prefetch_0 ();
1.1.1.18! root 1688: printf("\trefill_prefetch (m68k_getpc(), 0);\n"); // FIXME [NP] need better prefetch emulation (needed in War Heli for 60fe : bra.s -2)
1.1.1.2 root 1689: printf ("\treturn 10;\n");
1.1 root 1690: printf ("didnt_jump:;\n");
1691: need_endlabel = 1;
1.1.1.2 root 1692: insn_n_cycles = (curi->size == sz_byte) ? 8 : 12;
1.1 root 1693: break;
1694: case i_LEA:
1695: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1696: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1697: genastore ("srca", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.7 root 1698: /* Set correct cycles: According to the M68K User Manual, LEA takes 12
1699: * cycles in Ad8r and PC8r mode, but it takes 14 (or 16) cycles on a real ST: */
1700: if (curi->smode == Ad8r || curi->smode == PC8r)
1701: insn_n_cycles = 14;
1.1 root 1702: break;
1703: case i_PEA:
1704: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1705: genamode (Apdi, "7", sz_long, "dst", 2, 0);
1706: genastore ("srca", Apdi, "7", sz_long, "dst");
1.1.1.7 root 1707: /* Set correct cycles: */
1.1.1.2 root 1708: switch(curi->smode)
1709: {
1710: case Aind: insn_n_cycles=12; break;
1711: case Ad16: insn_n_cycles=16; break;
1.1.1.7 root 1712: /* Note: according to the M68K User Manual, PEA takes 20 cycles for
1713: * the Ad8r mode, but on a real ST, it takes 22 (or 24) cycles! */
1714: case Ad8r: insn_n_cycles=22; break;
1.1.1.2 root 1715: case absw: insn_n_cycles=16; break;
1716: case absl: insn_n_cycles=20; break;
1717: case PC16: insn_n_cycles=16; break;
1.1.1.7 root 1718: /* Note: PEA with PC8r takes 20 cycles according to the User Manual,
1719: * but it takes 22 (or 24) cycles on a real ST: */
1720: case PC8r: insn_n_cycles=22; break;
1.1.1.2 root 1721: }
1.1 root 1722: break;
1723: case i_DBcc:
1724: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1725: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0);
1726:
1.1.1.2 root 1727: printf ("\tif (!cctrue(%d)) {\n\t", curi->cc);
1.1 root 1728: genastore ("(src-1)", curi->smode, "srcreg", curi->size, "src");
1729:
1730: printf ("\t\tif (src) {\n");
1731: if (using_exception_3) {
1732: printf ("\t\t\tif (offs & 1) {\n");
1.1.1.8 root 1733: printf ("\t\t\tlast_addr_for_exception_3 = m68k_getpc() + 2 + 2;\n"); // [NP] last_addr is pc+4, not pc+2
1.1 root 1734: printf ("\t\t\tlast_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;\n");
1.1.1.18! root 1735: printf ("\t\tlast_instructionaccess_for_exception_3 = 1;\n");
! 1736: printf ("\t\tlast_writeaccess_for_exception_3 = 0;\n");
1.1.1.12 root 1737: printf ("\t\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
1.1 root 1738: printf ("\t\t}\n");
1739: need_endlabel = 1;
1740: }
1741: printf ("\t\t\tm68k_incpc((uae_s32)offs + 2);\n");
1742: fill_prefetch_0 ();
1.1.1.2 root 1743: printf ("\t\t\treturn 10;\n");
1744: printf ("\t\t} else {\n\t\t\t");
1745: {
1746: int tmp_offset = m68k_pc_offset;
1747: sync_m68k_pc(); /* not so nice to call it here... */
1748: m68k_pc_offset = tmp_offset;
1749: }
1750: printf ("\t\t\treturn 14;\n");
1751: printf ("\t\t}\n");
1.1 root 1752: printf ("\t}\n");
1753: insn_n_cycles = 12;
1754: need_endlabel = 1;
1755: break;
1756: case i_Scc:
1757: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1.1.1.17 root 1758:
1759: /* [NP] Scc does a read before the write only on 68000 */
1760: /* but there's no cycle penalty for doing the read */
1761: if ( curi->smode != Dreg ) // only if destination is memory
1762: {
1763: if (curi->size==sz_byte)
1764: printf ("\tuae_s8 src = get_byte(srca);\n");
1765: else if (curi->size==sz_word)
1766: printf ("\tuae_s16 src = get_word(srca);\n");
1767: else if (curi->size==sz_long)
1768: printf ("\tuae_s32 src = get_long(srca);\n");
1769: }
1770:
1.1 root 1771: start_brace ();
1772: printf ("\tint val = cctrue(%d) ? 0xff : 0;\n", curi->cc);
1773: genastore ("val", curi->smode, "srcreg", curi->size, "src");
1.1.1.8 root 1774: if (curi->smode!=Dreg) insn_n_cycles += 4;
1775: else
1776: { /* [NP] if result is TRUE, we return 6 instead of 4 */
1777: printf ("\tif (val) { m68k_incpc(2) ; return 4+2; }\n");
1778: }
1.1 root 1779: break;
1780: case i_DIVU:
1781: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1782: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1783: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1784: sync_m68k_pc ();
1785: /* Clear V flag when dividing by zero - Alcatraz Odyssey demo depends
1786: * on this (actually, it's doing a DIVS). */
1.1.1.12 root 1787: printf ("\tif (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto %s; } else {\n", endlabelstr);
1.1 root 1788: printf ("\tuae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
1789: printf ("\tuae_u32 rem = (uae_u32)dst %% (uae_u32)(uae_u16)src;\n");
1790: /* The N flag appears to be set each time there is an overflow.
1791: * Weird. */
1792: printf ("\tif (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
1793: genflags (flag_logical, sz_word, "newv", "", "");
1794: printf ("\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
1795: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1796: printf ("\t}\n");
1797: printf ("\t}\n");
1.1.1.8 root 1798: // insn_n_cycles += 136;
1799: printf ("\tretcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);\n");
1800: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 1801: need_endlabel = 1;
1802: break;
1803: case i_DIVS:
1804: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1805: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1806: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1807: sync_m68k_pc ();
1.1.1.12 root 1808: printf ("\tif (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto %s; } else {\n", endlabelstr);
1.1 root 1809: printf ("\tuae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
1810: printf ("\tuae_u16 rem = (uae_s32)dst %% (uae_s32)(uae_s16)src;\n");
1811: printf ("\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
1812: printf ("\tif (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;\n");
1813: genflags (flag_logical, sz_word, "newv", "", "");
1814: printf ("\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
1815: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1816: printf ("\t}\n");
1817: printf ("\t}\n");
1.1.1.8 root 1818: // insn_n_cycles += 154;
1819: printf ("\tretcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);\n");
1820: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 1821: need_endlabel = 1;
1822: break;
1823: case i_MULU:
1824: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1825: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0);
1826: start_brace ();
1827: printf ("\tuae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;\n");
1828: genflags (flag_logical, sz_long, "newv", "", "");
1829: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.8 root 1830: /* [NP] number of cycles is 38 + 2n + ea time ; n is the number of 1 bits in src */
1831: insn_n_cycles += 38-4; /* insn_n_cycles is already initialized to 4 instead of 0 */
1832: printf ("\twhile (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }\n");
1833: sprintf(exactCpuCycles," return (%i+retcycles*2);", insn_n_cycles);
1.1 root 1834: break;
1835: case i_MULS:
1836: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1837: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0);
1838: start_brace ();
1839: printf ("\tuae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;\n");
1.1.1.8 root 1840: printf ("\tuae_u32 src2;\n");
1.1 root 1841: genflags (flag_logical, sz_long, "newv", "", "");
1842: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.8 root 1843: /* [NP] number of cycles is 38 + 2n + ea time ; n is the number of 01 or 10 patterns in src expanded to 17 bits */
1844: insn_n_cycles += 38-4; /* insn_n_cycles is already initialized to 4 instead of 0 */
1845: printf ("\tsrc2 = ((uae_u32)src) << 1;\n");
1846: printf ("\twhile (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }\n");
1847: sprintf(exactCpuCycles," return (%i+retcycles*2);", insn_n_cycles);
1.1 root 1848: break;
1849: case i_CHK:
1850: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1851: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1852: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1.1.1.8 root 1853: sync_m68k_pc ();
1.1.1.12 root 1854: printf ("\tif ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1855: printf ("\telse if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1.1 root 1856: need_endlabel = 1;
1.1.1.2 root 1857: insn_n_cycles += 6;
1.1 root 1858: break;
1859:
1860: case i_CHK2:
1861: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1862: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
1863: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1864: printf ("\t{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];\n");
1865: switch (curi->size) {
1866: case sz_byte:
1867: printf ("\tlower=(uae_s32)(uae_s8)get_byte(dsta); upper = (uae_s32)(uae_s8)get_byte(dsta+1);\n");
1868: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;\n");
1869: break;
1870: case sz_word:
1871: printf ("\tlower=(uae_s32)(uae_s16)get_word(dsta); upper = (uae_s32)(uae_s16)get_word(dsta+2);\n");
1872: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;\n");
1873: break;
1874: case sz_long:
1875: printf ("\tlower=get_long(dsta); upper = get_long(dsta+4);\n");
1876: break;
1877: default:
1878: abort ();
1879: }
1880: printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
1881: printf ("\tSET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
1.1.1.8 root 1882: sync_m68k_pc ();
1.1.1.12 root 1883: printf ("\tif ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto %s; }\n}\n", endlabelstr);
1.1 root 1884: need_endlabel = 1;
1885: break;
1886:
1887: case i_ASR:
1888: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1889: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1890: start_brace ();
1891: switch (curi->size) {
1892: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1893: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1894: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1895: default: abort ();
1896: }
1897: printf ("\tuae_u32 sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1);
1898: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1899: printf ("\tretcycles = cnt;\n");
1.1 root 1900: printf ("\tCLEAR_CZNV;\n");
1901: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1902: printf ("\t\tval = %s & (uae_u32)-sign;\n", bit_mask (curi->size));
1903: printf ("\t\tSET_CFLG (sign);\n");
1904: duplicate_carry ();
1905: if (source_is_imm1_8 (curi))
1906: printf ("\t} else {\n");
1907: else
1908: printf ("\t} else if (cnt > 0) {\n");
1909: printf ("\t\tval >>= cnt - 1;\n");
1910: printf ("\t\tSET_CFLG (val & 1);\n");
1911: duplicate_carry ();
1912: printf ("\t\tval >>= 1;\n");
1913: printf ("\t\tval |= (%s << (%d - cnt)) & (uae_u32)-sign;\n",
1914: bit_mask (curi->size),
1915: bit_size (curi->size));
1916: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
1917: printf ("\t}\n");
1918: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1919: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1920: if(curi->size==sz_long)
1921: strcpy(exactCpuCycles," return (8+retcycles*2);");
1922: else
1923: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1924: break;
1925: case i_ASL:
1926: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1927: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1928: start_brace ();
1929: switch (curi->size) {
1930: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1931: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1932: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1933: default: abort ();
1934: }
1935: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1936: printf ("\tretcycles = cnt;\n");
1.1 root 1937: printf ("\tCLEAR_CZNV;\n");
1938: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1939: printf ("\t\tSET_VFLG (val != 0);\n");
1940: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
1941: bit_size (curi->size));
1942: duplicate_carry ();
1943: printf ("\t\tval = 0;\n");
1944: if (source_is_imm1_8 (curi))
1945: printf ("\t} else {\n");
1946: else
1947: printf ("\t} else if (cnt > 0) {\n");
1948: printf ("\t\tuae_u32 mask = (%s << (%d - cnt)) & %s;\n",
1949: bit_mask (curi->size),
1950: bit_size (curi->size) - 1,
1951: bit_mask (curi->size));
1952: printf ("\t\tSET_VFLG ((val & mask) != mask && (val & mask) != 0);\n");
1953: printf ("\t\tval <<= cnt - 1;\n");
1954: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
1955: duplicate_carry ();
1956: printf ("\t\tval <<= 1;\n");
1957: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
1958: printf ("\t}\n");
1959: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1960: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1961: if(curi->size==sz_long)
1962: strcpy(exactCpuCycles," return (8+retcycles*2);");
1963: else
1964: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1965: break;
1966: case i_LSR:
1967: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1968: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1969: start_brace ();
1970: switch (curi->size) {
1971: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1972: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1973: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1974: default: abort ();
1975: }
1976: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1977: printf ("\tretcycles = cnt;\n");
1.1 root 1978: printf ("\tCLEAR_CZNV;\n");
1979: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1980: printf ("\t\tSET_CFLG ((cnt == %d) & (val >> %d));\n",
1981: bit_size (curi->size), bit_size (curi->size) - 1);
1982: duplicate_carry ();
1983: printf ("\t\tval = 0;\n");
1984: if (source_is_imm1_8 (curi))
1985: printf ("\t} else {\n");
1986: else
1987: printf ("\t} else if (cnt > 0) {\n");
1988: printf ("\t\tval >>= cnt - 1;\n");
1989: printf ("\t\tSET_CFLG (val & 1);\n");
1990: duplicate_carry ();
1991: printf ("\t\tval >>= 1;\n");
1992: printf ("\t}\n");
1993: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1994: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1995: if(curi->size==sz_long)
1996: strcpy(exactCpuCycles," return (8+retcycles*2);");
1997: else
1998: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1999: break;
2000: case i_LSL:
2001: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
2002: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
2003: start_brace ();
2004: switch (curi->size) {
2005: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2006: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2007: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2008: default: abort ();
2009: }
2010: printf ("\tcnt &= 63;\n");
1.1.1.2 root 2011: printf ("\tretcycles = cnt;\n");
1.1 root 2012: printf ("\tCLEAR_CZNV;\n");
2013: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
2014: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
2015: bit_size (curi->size));
2016: duplicate_carry ();
2017: printf ("\t\tval = 0;\n");
2018: if (source_is_imm1_8 (curi))
2019: printf ("\t} else {\n");
2020: else
2021: printf ("\t} else if (cnt > 0) {\n");
2022: printf ("\t\tval <<= (cnt - 1);\n");
2023: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
2024: duplicate_carry ();
2025: printf ("\t\tval <<= 1;\n");
2026: printf ("\tval &= %s;\n", bit_mask (curi->size));
2027: printf ("\t}\n");
2028: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2029: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 2030: if(curi->size==sz_long)
2031: strcpy(exactCpuCycles," return (8+retcycles*2);");
2032: else
2033: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 2034: break;
2035: case i_ROL:
2036: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
2037: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
2038: start_brace ();
2039: switch (curi->size) {
2040: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2041: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2042: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2043: default: abort ();
2044: }
2045: printf ("\tcnt &= 63;\n");
1.1.1.2 root 2046: printf ("\tretcycles = cnt;\n");
1.1 root 2047: printf ("\tCLEAR_CZNV;\n");
2048: if (source_is_imm1_8 (curi))
2049: printf ("{");
2050: else
2051: printf ("\tif (cnt > 0) {\n");
2052: printf ("\tuae_u32 loval;\n");
2053: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
2054: printf ("\tloval = val >> (%d - cnt);\n", bit_size (curi->size));
2055: printf ("\tval <<= cnt;\n");
2056: printf ("\tval |= loval;\n");
2057: printf ("\tval &= %s;\n", bit_mask (curi->size));
2058: printf ("\tSET_CFLG (val & 1);\n");
2059: printf ("}\n");
2060: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2061: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 2062: if(curi->size==sz_long)
2063: strcpy(exactCpuCycles," return (8+retcycles*2);");
2064: else
2065: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 2066: break;
2067: case i_ROR:
2068: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
2069: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
2070: start_brace ();
2071: switch (curi->size) {
2072: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2073: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2074: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2075: default: abort ();
2076: }
2077: printf ("\tcnt &= 63;\n");
1.1.1.2 root 2078: printf ("\tretcycles = cnt;\n");
1.1 root 2079: printf ("\tCLEAR_CZNV;\n");
2080: if (source_is_imm1_8 (curi))
2081: printf ("{");
2082: else
2083: printf ("\tif (cnt > 0) {");
2084: printf ("\tuae_u32 hival;\n");
2085: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
2086: printf ("\thival = val << (%d - cnt);\n", bit_size (curi->size));
2087: printf ("\tval >>= cnt;\n");
2088: printf ("\tval |= hival;\n");
2089: printf ("\tval &= %s;\n", bit_mask (curi->size));
2090: printf ("\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
2091: printf ("\t}\n");
2092: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2093: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 2094: if(curi->size==sz_long)
2095: strcpy(exactCpuCycles," return (8+retcycles*2);");
2096: else
2097: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 2098: break;
2099: case i_ROXL:
2100: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
2101: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
2102: start_brace ();
2103: switch (curi->size) {
2104: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2105: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2106: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2107: default: abort ();
2108: }
2109: printf ("\tcnt &= 63;\n");
1.1.1.2 root 2110: printf ("\tretcycles = cnt;\n");
1.1 root 2111: printf ("\tCLEAR_CZNV;\n");
2112: if (source_is_imm1_8 (curi))
2113: printf ("{");
2114: else {
2115: force_range_for_rox ("cnt", curi->size);
2116: printf ("\tif (cnt > 0) {\n");
2117: }
2118: printf ("\tcnt--;\n");
2119: printf ("\t{\n\tuae_u32 carry;\n");
2120: printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
2121: printf ("\tcarry = loval & 1;\n");
2122: printf ("\tval = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);\n");
2123: printf ("\tSET_XFLG (carry);\n");
2124: printf ("\tval &= %s;\n", bit_mask (curi->size));
2125: printf ("\t} }\n");
2126: printf ("\tSET_CFLG (GET_XFLG);\n");
2127: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2128: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 2129: if(curi->size==sz_long)
2130: strcpy(exactCpuCycles," return (8+retcycles*2);");
2131: else
2132: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 2133: break;
2134: case i_ROXR:
2135: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
2136: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
2137: start_brace ();
2138: switch (curi->size) {
2139: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2140: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2141: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2142: default: abort ();
2143: }
2144: printf ("\tcnt &= 63;\n");
1.1.1.2 root 2145: printf ("\tretcycles = cnt;\n");
1.1 root 2146: printf ("\tCLEAR_CZNV;\n");
2147: if (source_is_imm1_8 (curi))
2148: printf ("{");
2149: else {
2150: force_range_for_rox ("cnt", curi->size);
2151: printf ("\tif (cnt > 0) {\n");
2152: }
2153: printf ("\tcnt--;\n");
2154: printf ("\t{\n\tuae_u32 carry;\n");
2155: printf ("\tuae_u32 hival = (val << 1) | GET_XFLG;\n");
2156: printf ("\thival <<= (%d - cnt);\n", bit_size (curi->size) - 1);
2157: printf ("\tval >>= cnt;\n");
2158: printf ("\tcarry = val & 1;\n");
2159: printf ("\tval >>= 1;\n");
2160: printf ("\tval |= hival;\n");
2161: printf ("\tSET_XFLG (carry);\n");
2162: printf ("\tval &= %s;\n", bit_mask (curi->size));
2163: printf ("\t} }\n");
2164: printf ("\tSET_CFLG (GET_XFLG);\n");
2165: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2166: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 2167: if(curi->size==sz_long)
2168: strcpy(exactCpuCycles," return (8+retcycles*2);");
2169: else
2170: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 2171: break;
2172: case i_ASRW:
2173: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2174: start_brace ();
2175: switch (curi->size) {
2176: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2177: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2178: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2179: default: abort ();
2180: }
2181: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
2182: printf ("\tuae_u32 cflg = val & 1;\n");
2183: printf ("\tval = (val >> 1) | sign;\n");
2184: genflags (flag_logical, curi->size, "val", "", "");
2185: printf ("\tSET_CFLG (cflg);\n");
2186: duplicate_carry ();
2187: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2188: break;
2189: case i_ASLW:
2190: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2191: start_brace ();
2192: switch (curi->size) {
2193: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2194: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2195: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2196: default: abort ();
2197: }
2198: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
2199: printf ("\tuae_u32 sign2;\n");
2200: printf ("\tval <<= 1;\n");
2201: genflags (flag_logical, curi->size, "val", "", "");
2202: printf ("\tsign2 = %s & val;\n", cmask (curi->size));
2203: printf ("\tSET_CFLG (sign != 0);\n");
2204: duplicate_carry ();
2205:
2206: printf ("\tSET_VFLG (GET_VFLG | (sign2 != sign));\n");
2207: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2208: break;
2209: case i_LSRW:
2210: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2211: start_brace ();
2212: switch (curi->size) {
2213: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2214: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2215: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2216: default: abort ();
2217: }
2218: printf ("\tuae_u32 carry = val & 1;\n");
2219: printf ("\tval >>= 1;\n");
2220: genflags (flag_logical, curi->size, "val", "", "");
2221: printf ("SET_CFLG (carry);\n");
2222: duplicate_carry ();
2223: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2224: break;
2225: case i_LSLW:
2226: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2227: start_brace ();
2228: switch (curi->size) {
2229: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2230: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2231: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2232: default: abort ();
2233: }
2234: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2235: printf ("\tval <<= 1;\n");
2236: genflags (flag_logical, curi->size, "val", "", "");
2237: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2238: duplicate_carry ();
2239: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2240: break;
2241: case i_ROLW:
2242: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2243: start_brace ();
2244: switch (curi->size) {
2245: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2246: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2247: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2248: default: abort ();
2249: }
2250: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2251: printf ("\tval <<= 1;\n");
2252: printf ("\tif (carry) val |= 1;\n");
2253: genflags (flag_logical, curi->size, "val", "", "");
2254: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2255: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2256: break;
2257: case i_RORW:
2258: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2259: start_brace ();
2260: switch (curi->size) {
2261: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2262: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2263: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2264: default: abort ();
2265: }
2266: printf ("\tuae_u32 carry = val & 1;\n");
2267: printf ("\tval >>= 1;\n");
2268: printf ("\tif (carry) val |= %s;\n", cmask (curi->size));
2269: genflags (flag_logical, curi->size, "val", "", "");
2270: printf ("SET_CFLG (carry);\n");
2271: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2272: break;
2273: case i_ROXLW:
2274: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2275: start_brace ();
2276: switch (curi->size) {
2277: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2278: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2279: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2280: default: abort ();
2281: }
2282: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2283: printf ("\tval <<= 1;\n");
2284: printf ("\tif (GET_XFLG) val |= 1;\n");
2285: genflags (flag_logical, curi->size, "val", "", "");
2286: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2287: duplicate_carry ();
2288: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2289: break;
2290: case i_ROXRW:
2291: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2292: start_brace ();
2293: switch (curi->size) {
2294: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2295: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2296: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2297: default: abort ();
2298: }
2299: printf ("\tuae_u32 carry = val & 1;\n");
2300: printf ("\tval >>= 1;\n");
2301: printf ("\tif (GET_XFLG) val |= %s;\n", cmask (curi->size));
2302: genflags (flag_logical, curi->size, "val", "", "");
2303: printf ("SET_CFLG (carry);\n");
2304: duplicate_carry ();
2305: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2306: break;
2307: case i_MOVEC2:
2308: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2309: start_brace ();
2310: printf ("\tint regno = (src >> 12) & 15;\n");
2311: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
2312: printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
2313: break;
2314: case i_MOVE2C:
2315: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2316: start_brace ();
2317: printf ("\tint regno = (src >> 12) & 15;\n");
2318: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
2319: printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
2320: break;
2321: case i_CAS:
2322: {
2323: int old_brace_level;
2324: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2325: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2326: start_brace ();
2327: printf ("\tint ru = (src >> 6) & 7;\n");
2328: printf ("\tint rc = src & 7;\n");
2329: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, rc)", "dst");
2330: printf ("\tif (GET_ZFLG)");
2331: old_brace_level = n_braces;
2332: start_brace ();
2333: genastore ("(m68k_dreg(regs, ru))", curi->dmode, "dstreg", curi->size, "dst");
2334: pop_braces (old_brace_level);
2335: printf ("else");
2336: start_brace ();
2337: printf ("m68k_dreg(regs, rc) = dst;\n");
2338: pop_braces (old_brace_level);
2339: }
2340: break;
2341: case i_CAS2:
2342: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2343: printf ("\tuae_u32 rn1 = regs.regs[(extra >> 28) & 15];\n");
2344: printf ("\tuae_u32 rn2 = regs.regs[(extra >> 12) & 15];\n");
2345: if (curi->size == sz_word) {
2346: int old_brace_level = n_braces;
2347: printf ("\tuae_u16 dst1 = get_word(rn1), dst2 = get_word(rn2);\n");
2348: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
2349: printf ("\tif (GET_ZFLG) {\n");
2350: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
2351: printf ("\tif (GET_ZFLG) {\n");
2352: printf ("\tput_word(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n");
2353: printf ("\tput_word(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n");
2354: printf ("\t}}\n");
2355: pop_braces (old_brace_level);
2356: printf ("\tif (! GET_ZFLG) {\n");
2357: printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = (m68k_dreg(regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
2358: printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = (m68k_dreg(regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
2359: printf ("\t}\n");
2360: } else {
2361: int old_brace_level = n_braces;
2362: printf ("\tuae_u32 dst1 = get_long(rn1), dst2 = get_long(rn2);\n");
2363: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
2364: printf ("\tif (GET_ZFLG) {\n");
2365: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
2366: printf ("\tif (GET_ZFLG) {\n");
2367: printf ("\tput_long(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n");
2368: printf ("\tput_long(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n");
2369: printf ("\t}}\n");
2370: pop_braces (old_brace_level);
2371: printf ("\tif (! GET_ZFLG) {\n");
2372: printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = dst1;\n");
2373: printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = dst2;\n");
2374: printf ("\t}\n");
2375: }
2376: break;
2377: case i_MOVES: /* ignore DFC and SFC because we have no MMU */
2378: {
2379: int old_brace_level;
2380: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2381: printf ("\tif (extra & 0x800)\n");
2382: old_brace_level = n_braces;
2383: start_brace ();
2384: printf ("\tuae_u32 src = regs.regs[(extra >> 12) & 15];\n");
2385: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
2386: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
2387: pop_braces (old_brace_level);
2388: printf ("else");
2389: start_brace ();
2390: genamode (curi->dmode, "dstreg", curi->size, "src", 1, 0);
2391: printf ("\tif (extra & 0x8000) {\n");
2392: switch (curi->size) {
2393: case sz_byte: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;\n"); break;
2394: case sz_word: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;\n"); break;
2395: case sz_long: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = src;\n"); break;
2396: default: abort ();
2397: }
2398: printf ("\t} else {\n");
2399: genastore ("src", Dreg, "(extra >> 12) & 7", curi->size, "");
2400: printf ("\t}\n");
2401: pop_braces (old_brace_level);
2402: }
2403: break;
2404: case i_BKPT: /* only needed for hardware emulators */
2405: sync_m68k_pc ();
2406: printf ("\top_illg(opcode);\n");
2407: break;
2408: case i_CALLM: /* not present in 68030 */
2409: sync_m68k_pc ();
2410: printf ("\top_illg(opcode);\n");
2411: break;
2412: case i_RTM: /* not present in 68030 */
2413: sync_m68k_pc ();
2414: printf ("\top_illg(opcode);\n");
2415: break;
2416: case i_TRAPcc:
2417: if (curi->smode != am_unknown && curi->smode != am_illg)
2418: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
1.1.1.12 root 2419: printf ("\tif (cctrue(%d)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto %s; }\n", curi->cc, endlabelstr);
1.1 root 2420: need_endlabel = 1;
2421: break;
2422: case i_DIVL:
2423: sync_m68k_pc ();
2424: start_brace ();
2425: printf ("\tuaecptr oldpc = m68k_getpc();\n");
2426: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2427: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2428: sync_m68k_pc ();
2429: printf ("\tm68k_divl(opcode, dst, extra, oldpc);\n");
2430: break;
2431: case i_MULL:
2432: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2433: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2434: sync_m68k_pc ();
2435: printf ("\tm68k_mull(opcode, dst, extra);\n");
2436: break;
2437: case i_BFTST:
2438: case i_BFEXTU:
2439: case i_BFCHG:
2440: case i_BFEXTS:
2441: case i_BFCLR:
2442: case i_BFFFO:
2443: case i_BFSET:
2444: case i_BFINS:
2445: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2446: genamode (curi->dmode, "dstreg", sz_long, "dst", 2, 0);
2447: start_brace ();
2448: printf ("\tuae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;\n");
2449: printf ("\tint width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;\n");
2450: if (curi->dmode == Dreg) {
2451: printf ("\tuae_u32 tmp = m68k_dreg(regs, dstreg) << (offset & 0x1f);\n");
2452: } else {
2453: printf ("\tuae_u32 tmp,bf0,bf1;\n");
2454: printf ("\tdsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);\n");
2455: printf ("\tbf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;\n");
2456: printf ("\ttmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));\n");
2457: }
2458: printf ("\ttmp >>= (32 - width);\n");
2459: printf ("\tSET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);\n");
2460: printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
2461: switch (curi->mnemo) {
2462: case i_BFTST:
2463: break;
2464: case i_BFEXTU:
2465: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n");
2466: break;
2467: case i_BFCHG:
2468: printf ("\ttmp = ~tmp;\n");
2469: break;
2470: case i_BFEXTS:
2471: printf ("\tif (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);\n");
2472: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n");
2473: break;
2474: case i_BFCLR:
2475: printf ("\ttmp = 0;\n");
2476: break;
2477: case i_BFFFO:
2478: printf ("\t{ uae_u32 mask = 1 << (width-1);\n");
2479: printf ("\twhile (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}\n");
2480: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = offset;\n");
2481: break;
2482: case i_BFSET:
2483: printf ("\ttmp = 0xffffffff;\n");
2484: break;
2485: case i_BFINS:
2486: printf ("\ttmp = m68k_dreg(regs, (extra >> 12) & 7);\n");
1.1.1.4 root 2487: printf ("\tSET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);\n");
2488: printf ("\tSET_ZFLG (tmp == 0);\n");
1.1 root 2489: break;
2490: default:
2491: break;
2492: }
2493: if (curi->mnemo == i_BFCHG
2494: || curi->mnemo == i_BFCLR
2495: || curi->mnemo == i_BFSET
2496: || curi->mnemo == i_BFINS)
2497: {
2498: printf ("\ttmp <<= (32 - width);\n");
2499: if (curi->dmode == Dreg) {
2500: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ((offset & 0x1f) == 0 ? 0 :\n");
2501: printf ("\t\t(0xffffffff << (32 - (offset & 0x1f))))) |\n");
2502: printf ("\t\t(tmp >> (offset & 0x1f)) |\n");
2503: printf ("\t\t(((offset & 0x1f) + width) >= 32 ? 0 :\n");
2504: printf (" (m68k_dreg(regs, dstreg) & ((uae_u32)0xffffffff >> ((offset & 0x1f) + width))));\n");
2505: } else {
2506: printf ("\tbf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |\n");
2507: printf ("\t\t(tmp >> (offset & 7)) |\n");
2508: printf ("\t\t(((offset & 7) + width) >= 32 ? 0 :\n");
2509: printf ("\t\t (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));\n");
2510: printf ("\tput_long(dsta,bf0 );\n");
2511: printf ("\tif (((offset & 7) + width) > 32) {\n");
2512: printf ("\t\tbf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |\n");
2513: printf ("\t\t\t(tmp << (8 - (offset & 7)));\n");
2514: printf ("\t\tput_byte(dsta+4,bf1);\n");
2515: printf ("\t}\n");
2516: }
2517: }
2518: break;
2519: case i_PACK:
2520: if (curi->smode == Dreg) {
2521: printf ("\tuae_u16 val = m68k_dreg(regs, srcreg) + %s;\n", gen_nextiword ());
2522: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);\n");
2523: } else {
2524: printf ("\tuae_u16 val;\n");
2525: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2526: printf ("\tval = (uae_u16)get_byte(m68k_areg(regs, srcreg));\n");
2527: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2528: printf ("\tval = (val | ((uae_u16)get_byte(m68k_areg(regs, srcreg)) << 8)) + %s;\n", gen_nextiword ());
2529: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2530: printf ("\tput_byte(m68k_areg(regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));\n");
2531: }
2532: break;
2533: case i_UNPK:
2534: if (curi->smode == Dreg) {
2535: printf ("\tuae_u16 val = m68k_dreg(regs, srcreg);\n");
2536: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword ());
2537: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffff0000) | (val & 0xffff);\n");
2538: } else {
2539: printf ("\tuae_u16 val;\n");
2540: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2541: printf ("\tval = (uae_u16)get_byte(m68k_areg(regs, srcreg));\n");
2542: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword ());
2543: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2544: printf ("\tput_byte(m68k_areg(regs, dstreg),val);\n");
2545: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2546: printf ("\tput_byte(m68k_areg(regs, dstreg),val >> 8);\n");
2547: }
2548: break;
2549: case i_TAS:
2550: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2551: genflags (flag_logical, curi->size, "src", "", "");
2552: printf ("\tsrc |= 0x80;\n");
2553: genastore ("src", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 2554: if( curi->smode!=Dreg ) insn_n_cycles += 2;
1.1 root 2555: break;
2556: case i_FPP:
2557: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2558: sync_m68k_pc ();
2559: printf ("\tfpp_opp(opcode,extra);\n");
2560: break;
2561: case i_FDBcc:
2562: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2563: sync_m68k_pc ();
2564: printf ("\tfdbcc_opp(opcode,extra);\n");
2565: break;
2566: case i_FScc:
2567: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2568: sync_m68k_pc ();
2569: printf ("\tfscc_opp(opcode,extra);\n");
2570: break;
2571: case i_FTRAPcc:
2572: sync_m68k_pc ();
2573: start_brace ();
2574: printf ("\tuaecptr oldpc = m68k_getpc();\n");
2575: if (curi->smode != am_unknown && curi->smode != am_illg)
2576: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
2577: sync_m68k_pc ();
2578: printf ("\tftrapcc_opp(opcode,oldpc);\n");
2579: break;
2580: case i_FBcc:
2581: sync_m68k_pc ();
2582: start_brace ();
2583: printf ("\tuaecptr pc = m68k_getpc();\n");
2584: genamode (curi->dmode, "srcreg", curi->size, "extra", 1, 0);
2585: sync_m68k_pc ();
2586: printf ("\tfbcc_opp(opcode,pc,extra);\n");
2587: break;
2588: case i_FSAVE:
2589: sync_m68k_pc ();
2590: printf ("\tfsave_opp(opcode);\n");
2591: break;
2592: case i_FRESTORE:
2593: sync_m68k_pc ();
2594: printf ("\tfrestore_opp(opcode);\n");
2595: break;
2596:
2597: case i_CINVL:
2598: case i_CINVP:
2599: case i_CINVA:
2600: case i_CPUSHL:
2601: case i_CPUSHP:
2602: case i_CPUSHA:
2603: break;
2604: case i_MOVE16:
1.1.1.4 root 2605: if ((opcode & 0xfff8) == 0xf620) {
2606: /* MOVE16 (Ax)+,(Ay)+ */
2607: printf ("\tuaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
2608: printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword());
2609: printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n");
2610: printf ("\tput_long(memd, get_long(mems));\n");
2611: printf ("\tput_long(memd+4, get_long(mems+4));\n");
2612: printf ("\tput_long(memd+8, get_long(mems+8));\n");
2613: printf ("\tput_long(memd+12, get_long(mems+12));\n");
2614: printf ("\tif (srcreg != dstreg)\n");
2615: printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2616: printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2617: } else {
2618: /* Other variants */
2619: genamode (curi->smode, "srcreg", curi->size, "mems", 0, 2);
2620: genamode (curi->dmode, "dstreg", curi->size, "memd", 0, 2);
2621: printf ("\tmemsa &= ~15;\n");
2622: printf ("\tmemda &= ~15;\n");
2623: printf ("\tput_long(memda, get_long(memsa));\n");
2624: printf ("\tput_long(memda+4, get_long(memsa+4));\n");
2625: printf ("\tput_long(memda+8, get_long(memsa+8));\n");
2626: printf ("\tput_long(memda+12, get_long(memsa+12));\n");
2627: if ((opcode & 0xfff8) == 0xf600)
2628: printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2629: else if ((opcode & 0xfff8) == 0xf608)
2630: printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2631: }
1.1 root 2632: break;
2633:
2634: case i_MMUOP:
2635: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2636: sync_m68k_pc ();
2637: printf ("\tmmu_op(opcode,extra);\n");
2638: break;
2639: default:
2640: abort ();
2641: break;
2642: }
2643: finish_braces ();
2644: sync_m68k_pc ();
2645: }
2646:
2647: static void generate_includes (FILE * f)
2648: {
2649: fprintf (f, "#include \"sysdeps.h\"\n");
2650: fprintf (f, "#include \"hatari-glue.h\"\n");
2651: fprintf (f, "#include \"maccess.h\"\n");
2652: fprintf (f, "#include \"memory.h\"\n");
2653: fprintf (f, "#include \"newcpu.h\"\n");
2654: fprintf (f, "#include \"cputbl.h\"\n");
2655: fprintf (f, "#define CPUFUNC(x) x##_ff\n"
2656: "#ifdef NOFLAGS\n"
2657: "#include \"noflags.h\"\n"
2658: "#endif\n");
2659: }
2660:
2661: static int postfix;
2662:
2663: static void generate_one_opcode (int rp)
2664: {
2665: int i;
2666: uae_u16 smsk, dmsk;
2667: long int opcode = opcode_map[rp];
2668:
1.1.1.2 root 2669: exactCpuCycles[0] = 0; /* Default: not used */
2670:
1.1 root 2671: if (table68k[opcode].mnemo == i_ILLG
2672: || table68k[opcode].clev > cpu_level)
2673: return;
2674:
2675: for (i = 0; lookuptab[i].name[0]; i++) {
2676: if (table68k[opcode].mnemo == lookuptab[i].mnemo)
2677: break;
2678: }
2679:
2680: if (table68k[opcode].handler != -1)
2681: return;
2682:
2683: if (opcode_next_clev[rp] != cpu_level) {
2684: fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp],
2685: opcode, lookuptab[i].name);
2686: return;
2687: }
2688: fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, postfix, opcode, lookuptab[i].name);
2689: fprintf (headerfile, "extern cpuop_func op_%lx_%d_nf;\n", opcode, postfix);
2690: fprintf (headerfile, "extern cpuop_func op_%lx_%d_ff;\n", opcode, postfix);
2691: printf ("unsigned long REGPARAM2 CPUFUNC(op_%lx_%d)(uae_u32 opcode) /* %s */\n{\n", opcode, postfix, lookuptab[i].name);
2692:
2693: switch (table68k[opcode].stype) {
2694: case 0: smsk = 7; break;
2695: case 1: smsk = 255; break;
2696: case 2: smsk = 15; break;
2697: case 3: smsk = 7; break;
2698: case 4: smsk = 7; break;
2699: case 5: smsk = 63; break;
1.1.1.4 root 2700: case 7: smsk = 3; break;
1.1 root 2701: default: abort ();
2702: }
2703: dmsk = 7;
2704:
2705: next_cpu_level = -1;
2706: if (table68k[opcode].suse
2707: && table68k[opcode].smode != imm && table68k[opcode].smode != imm0
2708: && table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
2709: && table68k[opcode].smode != absw && table68k[opcode].smode != absl
2710: && table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
2711: {
2712: if (table68k[opcode].spos == -1) {
2713: if (((int) table68k[opcode].sreg) >= 128)
2714: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].sreg);
2715: else
2716: printf ("\tuae_u32 srcreg = %d;\n", (int) table68k[opcode].sreg);
2717: } else {
2718: char source[100];
2719: int pos = table68k[opcode].spos;
2720:
2721: if (pos)
2722: sprintf (source, "((opcode >> %d) & %d)", pos, smsk);
2723: else
2724: sprintf (source, "(opcode & %d)", smsk);
2725:
2726: if (table68k[opcode].stype == 3)
2727: printf ("\tuae_u32 srcreg = imm8_table[%s];\n", source);
2728: else if (table68k[opcode].stype == 1)
2729: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%s;\n", source);
2730: else
2731: printf ("\tuae_u32 srcreg = %s;\n", source);
2732: }
2733: }
2734: if (table68k[opcode].duse
2735: /* Yes, the dmode can be imm, in case of LINK or DBcc */
2736: && table68k[opcode].dmode != imm && table68k[opcode].dmode != imm0
2737: && table68k[opcode].dmode != imm1 && table68k[opcode].dmode != imm2
2738: && table68k[opcode].dmode != absw && table68k[opcode].dmode != absl)
2739: {
2740: if (table68k[opcode].dpos == -1) {
2741: if (((int) table68k[opcode].dreg) >= 128)
2742: printf ("\tuae_u32 dstreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].dreg);
2743: else
2744: printf ("\tuae_u32 dstreg = %d;\n", (int) table68k[opcode].dreg);
2745: } else {
2746: int pos = table68k[opcode].dpos;
2747: #if 0
2748: /* Check that we can do the little endian optimization safely. */
2749: if (pos < 8 && (dmsk >> (8 - pos)) != 0)
2750: abort ();
2751: #endif
2752: if (pos)
2753: printf ("\tuae_u32 dstreg = (opcode >> %d) & %d;\n",
2754: pos, dmsk);
2755: else
2756: printf ("\tuae_u32 dstreg = opcode & %d;\n", dmsk);
2757: }
2758: }
2759: need_endlabel = 0;
2760: endlabelno++;
2761: sprintf (endlabelstr, "endlabel%d", endlabelno);
1.1.1.2 root 2762: if(table68k[opcode].mnemo==i_ASR || table68k[opcode].mnemo==i_ASL || table68k[opcode].mnemo==i_LSR || table68k[opcode].mnemo==i_LSL
2763: || table68k[opcode].mnemo==i_ROL || table68k[opcode].mnemo==i_ROR || table68k[opcode].mnemo==i_ROXL || table68k[opcode].mnemo==i_ROXR
1.1.1.8 root 2764: || table68k[opcode].mnemo==i_MVMEL || table68k[opcode].mnemo==i_MVMLE
2765: || table68k[opcode].mnemo==i_MULU || table68k[opcode].mnemo==i_MULS
2766: || table68k[opcode].mnemo==i_DIVU || table68k[opcode].mnemo==i_DIVS )
2767: printf("\tunsigned int retcycles = 0;\n");
1.1 root 2768: gen_opcode (opcode);
2769: if (need_endlabel)
2770: printf ("%s: ;\n", endlabelstr);
1.1.1.8 root 2771:
2772: if (strlen(exactCpuCycles) > 0)
2773: printf("%s\n",exactCpuCycles);
2774: else
2775: printf ("return %d;\n", insn_n_cycles);
2776: /* Now patch in the instruction cycles at the beginning of the function: */
2777: fseek(stdout, nCurInstrCycPos, SEEK_SET);
2778: printf("%d;", insn_n_cycles);
2779: fseek(stdout, 0, SEEK_END);
2780:
1.1 root 2781: printf ("}\n");
2782: opcode_next_clev[rp] = next_cpu_level;
2783: opcode_last_postfix[rp] = postfix;
2784: }
2785:
2786: static void generate_func (void)
2787: {
2788: int i, j, rp;
2789:
2790: using_prefetch = 0;
2791: using_exception_3 = 0;
2792: for (i = 0; i < 6; i++) {
2793: cpu_level = 4 - i;
2794: if (i == 5) {
2795: cpu_level = 0;
2796: using_prefetch = 1;
2797: using_exception_3 = 1;
2798: for (rp = 0; rp < nr_cpuop_funcs; rp++)
2799: opcode_next_clev[rp] = 0;
2800: }
2801:
2802: postfix = i;
1.1.1.7 root 2803: fprintf (stblfile, "const struct cputbl CPUFUNC(op_smalltbl_%d)[] = {\n", postfix);
1.1 root 2804:
2805: /* sam: this is for people with low memory (eg. me :)) */
2806: printf ("\n"
2807: "#if !defined(PART_1) && !defined(PART_2) && "
2808: "!defined(PART_3) && !defined(PART_4) && "
2809: "!defined(PART_5) && !defined(PART_6) && "
2810: "!defined(PART_7) && !defined(PART_8)"
2811: "\n"
2812: "#define PART_1 1\n"
2813: "#define PART_2 1\n"
2814: "#define PART_3 1\n"
2815: "#define PART_4 1\n"
2816: "#define PART_5 1\n"
2817: "#define PART_6 1\n"
2818: "#define PART_7 1\n"
2819: "#define PART_8 1\n"
2820: "#endif\n\n");
2821:
2822: rp = 0;
2823: for(j=1;j<=8;++j) {
2824: int k = (j*nr_cpuop_funcs)/8;
2825: printf ("#ifdef PART_%d\n",j);
2826: for (; rp < k; rp++)
2827: generate_one_opcode (rp);
2828: printf ("#endif\n\n");
2829: }
2830:
2831: fprintf (stblfile, "{ 0, 0, 0 }};\n");
2832: }
2833:
2834: }
2835:
2836: int main (int argc, char **argv)
2837: {
2838: read_table68k ();
2839: do_merges ();
2840:
2841: opcode_map = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2842: opcode_last_postfix = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2843: opcode_next_clev = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2844: counts = (unsigned long *) malloc (65536 * sizeof (unsigned long));
2845: read_counts ();
2846:
2847: /* It would be a lot nicer to put all in one file (we'd also get rid of
2848: * cputbl.h that way), but cpuopti can't cope. That could be fixed, but
2849: * I don't dare to touch the 68k version. */
2850:
2851: headerfile = fopen ("cputbl.h", "wb");
2852: stblfile = fopen ("cpustbl.c", "wb");
1.1.1.11 root 2853: if (freopen ("cpuemu.c", "wb", stdout) == NULL) {
2854: perror("cpuemu.c");
2855: return -1;
2856: }
1.1 root 2857:
2858: generate_includes (stdout);
2859: generate_includes (stblfile);
2860:
2861: generate_func ();
2862:
2863: free (table68k);
2864: return 0;
2865: }
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.