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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation generator
5: *
6: * This is a fairly stupid program that generates a lot of case labels that
7: * can be #included in a switch statement.
8: * As an alternative, it can generate functions that handle specific
9: * MC68000 instructions, plus a prototype header file and a function pointer
10: * array to look up the function for an opcode.
11: * Error checking is bad, an illegal table68k file will cause the program to
12: * call abort().
13: * The generated code is sometimes sub-optimal, an optimizing compiler should
14: * take care of this.
15: *
16: * The source for the insn timings is Markt & Technik's Amiga Magazin 8/1992.
17: *
18: * Copyright 1995, 1996, 1997, 1998, 1999, 2000 Bernd Schmidt
1.1.1.2 root 19: *
20: * Adaptation to Hatari and better cpu timings by Thomas Huth
21: *
1.1.1.4 root 22: * This file is distributed under the GNU Public License, version 2 or at
23: * your option any later version. Read the file gpl.txt for details.
1.1 root 24: */
1.1.1.8 ! root 25:
! 26:
! 27: /* 2007/03/xx [NP] Use add_cycles.pl to set 'CurrentInstrCycles' in each opcode. */
! 28: /* 2007/04/09 [NP] Correct CLR : on 68000, CLR reads the memory before clearing it (but we should */
! 29: /* not add cycles for reading). This means CLR can give 2 wait states (one for */
! 30: /* read and one for right) (clr.b $fa1b.w in Decade's Demo Main Menu). */
! 31: /* 2007/04/14 [NP] - Although dest -(an) normally takes 2 cycles, this is not the case for move : */
! 32: /* move dest (an), (an)+ and -(an) all take the same time (curi->dmode == Apdi) */
! 33: /* (Syntax Terror Demo Reset). */
! 34: /* - Scc takes 6 cycles instead of 4 if the result is true (Ventura Demo Loader). */
! 35: /* - Store the family of the current opcode into OpcodeFamily : used to check */
! 36: /* instruction pairing on ST into m68000.c */
! 37: /* 2007/04/17 [NP] Add support for cycle accurate MULU (No Cooper Greeting Screen). */
! 38: /* 2007/04/24 [NP] BCLR #n,Dx takes 12 cycles instead of 14 if n<16 (ULM Demo Menu). */
! 39: /* 2007/04/25 [NP] On ST, d8(An,Xn) and d8(PC,Xn) take 2 cycles more than the official 68000's */
! 40: /* table (ULM Demo Menu). */
! 41: /* 2007/11/12 [NP] Add refill_prefetch for i_ADD to fix Transbeauce 2 demo self modified code. */
! 42: /* Ugly hack, we need better prefetch emulation (switch to winuae gencpu.c) */
! 43: /* 2007/11/25 [NP] In i_DBcc, in case of address error, last_addr_for_exception_3 should be */
! 44: /* pc+4, not pc+2 (Transbeauce 2 demo) (e.g. 'dbf d0,#$fff5'). */
! 45: /* This means the value pushed on the frame stack should be the address of the */
! 46: /* instruction following the one generating the address error. */
! 47: /* FIXME : this should be the case for i_BSR and i_BCC too (need to check on */
! 48: /* a real 68000). */
! 49: /* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */
! 50: /* Cwik, [email protected]). */
! 51: /* 2007/12/08 [NP] In case of CHK/CHK2 exception, PC stored on the stack wasn't pointing to the */
! 52: /* next instruction but to the current CHK/CHK2 instruction (Transbeauce 2 demo). */
! 53: /* We need to call 'sync_m68k_pc' before calling 'Exception'. */
! 54: /* 2007/12/09 [NP] CHK.L (e.g. $4700) doesn't exist on 68000 and should be considered as an illegal*/
! 55: /* instruction (Transbeauce 2 demo) -> change in table68k. */
! 56: /* 2008/01/24 [NP] BCLR Dy,Dx takes 8 cycles instead of 10 if Dy<16 (Fullshade in Anomaly Demos). */
! 57: /* 2008/01/26 [NP] On ST, d8(An,Xn) takes 2 cycles more when used with ADDA/SUBA (ULM Demo Menu) */
! 58: /* but not when used with MOVE (e.g. 'move.l 0(a5,d1),(a4)' takes 26 cycles and so */
! 59: /* can pair with a lsr) (Anomaly Demo Intro). */
! 60:
! 61:
! 62:
! 63: const char GenCpu_rcsid[] = "Hatari $Id: gencpu.c,v 1.15 2008/02/04 21:41:22 thothy Exp $";
1.1 root 64:
65: #include <ctype.h>
1.1.1.3 root 66: #include <string.h>
1.1 root 67:
68: #include "sysdeps.h"
69: #include "readcpu.h"
70:
71: #define BOOL_TYPE "int"
72:
73: static FILE *headerfile;
74: static FILE *stblfile;
75:
76: static int using_prefetch;
77: static int using_exception_3;
78: static int cpu_level;
79:
1.1.1.2 root 80: char exactCpuCycles[256]; /* Space to store return string for exact cpu cycles */
81:
1.1.1.8 ! root 82: long nCurInstrCycPos; /* Stores where we have to patch in the current cycles value */
1.1.1.2 root 83:
1.1 root 84: /* For the current opcode, the next lower level that will have different code.
85: * Initialized to -1 for each opcode. If it remains unchanged, indicates we
86: * are done with that opcode. */
87: static int next_cpu_level;
88: static int *opcode_map;
89: static int *opcode_next_clev;
90: static int *opcode_last_postfix;
91: static unsigned long *counts;
92:
1.1.1.6 root 93:
1.1 root 94: static void read_counts (void)
95: {
96: FILE *file;
97: unsigned long opcode, count, total;
98: char name[20];
99: int nr = 0;
100: memset (counts, 0, 65536 * sizeof *counts);
101:
102: file = fopen ("frequent.68k", "r");
103: if (file) {
104: fscanf (file, "Total: %lu\n", &total);
105: while (fscanf (file, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
106: opcode_next_clev[nr] = 4;
107: opcode_last_postfix[nr] = -1;
108: opcode_map[nr++] = opcode;
109: counts[opcode] = count;
110: }
111: fclose (file);
112: }
113: if (nr == nr_cpuop_funcs)
114: return;
115: for (opcode = 0; opcode < 0x10000; opcode++) {
116: if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
117: && counts[opcode] == 0)
118: {
119: opcode_next_clev[nr] = 4;
120: opcode_last_postfix[nr] = -1;
121: opcode_map[nr++] = opcode;
122: counts[opcode] = count;
123: }
124: }
125: if (nr != nr_cpuop_funcs)
126: abort ();
127: }
128:
129: static char endlabelstr[80];
130: static int endlabelno = 0;
131: static int need_endlabel;
132:
133: static int n_braces = 0;
134: static int m68k_pc_offset = 0;
135: static int insn_n_cycles;
136:
137: static void start_brace (void)
138: {
139: n_braces++;
140: printf ("{");
141: }
142:
143: static void close_brace (void)
144: {
145: assert (n_braces > 0);
146: n_braces--;
147: printf ("}");
148: }
149:
150: static void finish_braces (void)
151: {
152: while (n_braces > 0)
153: close_brace ();
154: }
155:
156: static void pop_braces (int to)
157: {
158: while (n_braces > to)
159: close_brace ();
160: }
161:
162: static int bit_size (int size)
163: {
164: switch (size) {
165: case sz_byte: return 8;
166: case sz_word: return 16;
167: case sz_long: return 32;
168: default: abort ();
169: }
170: return 0;
171: }
172:
173: static const char *bit_mask (int size)
174: {
175: switch (size) {
176: case sz_byte: return "0xff";
177: case sz_word: return "0xffff";
178: case sz_long: return "0xffffffff";
179: default: abort ();
180: }
181: return 0;
182: }
183:
184: static const char *gen_nextilong (void)
185: {
186: static char buffer[80];
187: int r = m68k_pc_offset;
188: m68k_pc_offset += 4;
189:
190: insn_n_cycles += 8;
191:
192: if (using_prefetch)
193: sprintf (buffer, "get_ilong_prefetch(%d)", r);
194: else
195: sprintf (buffer, "get_ilong(%d)", r);
196: return buffer;
197: }
198:
199: static const char *gen_nextiword (void)
200: {
201: static char buffer[80];
202: int r = m68k_pc_offset;
203: m68k_pc_offset += 2;
204:
205: insn_n_cycles += 4;
206:
207: if (using_prefetch)
208: sprintf (buffer, "get_iword_prefetch(%d)", r);
209: else
210: sprintf (buffer, "get_iword(%d)", r);
211: return buffer;
212: }
213:
214: static const char *gen_nextibyte (void)
215: {
216: static char buffer[80];
217: int r = m68k_pc_offset;
218: m68k_pc_offset += 2;
219:
220: insn_n_cycles += 4;
221:
222: if (using_prefetch)
223: sprintf (buffer, "get_ibyte_prefetch(%d)", r);
224: else
225: sprintf (buffer, "get_ibyte(%d)", r);
226: return buffer;
227: }
228:
229: static void fill_prefetch_0 (void)
230: {
231: if (using_prefetch)
232: printf ("fill_prefetch_0 ();\n");
233: }
234:
235: static void fill_prefetch_2 (void)
236: {
237: if (using_prefetch)
238: printf ("fill_prefetch_2 ();\n");
239: }
240:
241: static void sync_m68k_pc (void)
242: {
243: if (m68k_pc_offset == 0)
244: return;
245: printf ("m68k_incpc(%d);\n", m68k_pc_offset);
246: switch (m68k_pc_offset) {
247: case 0:
248: /*fprintf (stderr, "refilling prefetch at 0\n"); */
249: break;
250: case 2:
251: fill_prefetch_2 ();
252: break;
253: default:
254: fill_prefetch_0 ();
255: break;
256: }
257: m68k_pc_offset = 0;
258: }
259:
260: /* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
1.1.1.4 root 261: * the calling routine handles Apdi and Aipi modes.
262: * gb-- movem == 2 means the same thing but for a MOVE16 instruction */
1.1 root 263: static void genamode (amodes mode, char *reg, wordsizes size, char *name, int getv, int movem)
264: {
265: start_brace ();
266: switch (mode) {
267: case Dreg:
268: if (movem)
269: abort ();
270: if (getv == 1)
271: switch (size) {
272: case sz_byte:
273: printf ("\tuae_s8 %s = m68k_dreg(regs, %s);\n", name, reg);
274: break;
275: case sz_word:
276: printf ("\tuae_s16 %s = m68k_dreg(regs, %s);\n", name, reg);
277: break;
278: case sz_long:
279: printf ("\tuae_s32 %s = m68k_dreg(regs, %s);\n", name, reg);
280: break;
281: default:
282: abort ();
283: }
284: return;
285: case Areg:
286: if (movem)
287: abort ();
288: if (getv == 1)
289: switch (size) {
290: case sz_word:
291: printf ("\tuae_s16 %s = m68k_areg(regs, %s);\n", name, reg);
292: break;
293: case sz_long:
294: printf ("\tuae_s32 %s = m68k_areg(regs, %s);\n", name, reg);
295: break;
296: default:
297: abort ();
298: }
299: return;
300: case Aind:
301: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
302: break;
303: case Aipi:
304: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
305: break;
306: case Apdi:
307: insn_n_cycles += 2;
308: switch (size) {
309: case sz_byte:
310: if (movem)
311: printf ("\tuaecptr %sa = m68k_areg(regs, %s);\n", name, reg);
312: else
313: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - areg_byteinc[%s];\n", name, reg, reg);
314: break;
315: case sz_word:
316: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 2);
317: break;
318: case sz_long:
319: printf ("\tuaecptr %sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 4);
320: break;
321: default:
322: abort ();
323: }
324: break;
325: case Ad16:
326: printf ("\tuaecptr %sa = m68k_areg(regs, %s) + (uae_s32)(uae_s16)%s;\n", name, reg, gen_nextiword ());
327: break;
328: case Ad8r:
329: insn_n_cycles += 2;
330: if (cpu_level > 1) {
331: if (next_cpu_level < 1)
332: next_cpu_level = 1;
333: sync_m68k_pc ();
334: start_brace ();
335: /* This would ordinarily be done in gen_nextiword, which we bypass. */
336: insn_n_cycles += 4;
337: printf ("\tuaecptr %sa = get_disp_ea_020(m68k_areg(regs, %s), next_iword());\n", name, reg);
1.1.1.8 ! root 338: } else {
1.1 root 339: printf ("\tuaecptr %sa = get_disp_ea_000(m68k_areg(regs, %s), %s);\n", name, reg, gen_nextiword ());
1.1.1.8 ! root 340: }
1.1 root 341:
342: break;
343: case PC16:
344: printf ("\tuaecptr %sa = m68k_getpc () + %d;\n", name, m68k_pc_offset);
345: printf ("\t%sa += (uae_s32)(uae_s16)%s;\n", name, gen_nextiword ());
346: break;
347: case PC8r:
348: insn_n_cycles += 2;
349: if (cpu_level > 1) {
350: if (next_cpu_level < 1)
351: next_cpu_level = 1;
352: sync_m68k_pc ();
353: start_brace ();
354: /* This would ordinarily be done in gen_nextiword, which we bypass. */
355: insn_n_cycles += 4;
356: printf ("\tuaecptr tmppc = m68k_getpc();\n");
357: printf ("\tuaecptr %sa = get_disp_ea_020(tmppc, next_iword());\n", name);
358: } else {
359: printf ("\tuaecptr tmppc = m68k_getpc() + %d;\n", m68k_pc_offset);
360: printf ("\tuaecptr %sa = get_disp_ea_000(tmppc, %s);\n", name, gen_nextiword ());
361: }
362:
363: break;
364: case absw:
365: printf ("\tuaecptr %sa = (uae_s32)(uae_s16)%s;\n", name, gen_nextiword ());
366: break;
367: case absl:
368: printf ("\tuaecptr %sa = %s;\n", name, gen_nextilong ());
369: break;
370: case imm:
371: if (getv != 1)
372: abort ();
373: switch (size) {
374: case sz_byte:
375: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte ());
376: break;
377: case sz_word:
378: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword ());
379: break;
380: case sz_long:
381: printf ("\tuae_s32 %s = %s;\n", name, gen_nextilong ());
382: break;
383: default:
384: abort ();
385: }
386: return;
387: case imm0:
388: if (getv != 1)
389: abort ();
390: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte ());
391: return;
392: case imm1:
393: if (getv != 1)
394: abort ();
395: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword ());
396: return;
397: case imm2:
398: if (getv != 1)
399: abort ();
400: printf ("\tuae_s32 %s = %s;\n", name, gen_nextilong ());
401: return;
402: case immi:
403: if (getv != 1)
404: abort ();
405: printf ("\tuae_u32 %s = %s;\n", name, reg);
406: return;
407: default:
408: abort ();
409: }
410:
411: /* We get here for all non-reg non-immediate addressing modes to
412: * actually fetch the value. */
413:
414: if (using_exception_3 && getv != 0 && size != sz_byte) {
415: printf ("\tif ((%sa & 1) != 0) {\n", name);
416: printf ("\t\tlast_fault_for_exception_3 = %sa;\n", name);
417: printf ("\t\tlast_op_for_exception_3 = opcode;\n");
418: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + %d;\n", m68k_pc_offset);
419: printf ("\t\tException(3, 0);\n");
420: printf ("\t\tgoto %s;\n", endlabelstr);
421: printf ("\t}\n");
422: need_endlabel = 1;
423: start_brace ();
424: }
425:
426: if (getv == 1) {
427: switch (size) {
428: case sz_byte: insn_n_cycles += 4; break;
429: case sz_word: insn_n_cycles += 4; break;
430: case sz_long: insn_n_cycles += 8; break;
431: default: abort ();
432: }
433: start_brace ();
434: switch (size) {
435: case sz_byte: printf ("\tuae_s8 %s = get_byte(%sa);\n", name, name); break;
436: case sz_word: printf ("\tuae_s16 %s = get_word(%sa);\n", name, name); break;
437: case sz_long: printf ("\tuae_s32 %s = get_long(%sa);\n", name, name); break;
438: default: abort ();
439: }
440: }
441:
442: /* We now might have to fix up the register for pre-dec or post-inc
443: * addressing modes. */
444: if (!movem)
445: switch (mode) {
446: case Aipi:
447: switch (size) {
448: case sz_byte:
449: printf ("\tm68k_areg(regs, %s) += areg_byteinc[%s];\n", reg, reg);
450: break;
451: case sz_word:
452: printf ("\tm68k_areg(regs, %s) += 2;\n", reg);
453: break;
454: case sz_long:
455: printf ("\tm68k_areg(regs, %s) += 4;\n", reg);
456: break;
457: default:
458: abort ();
459: }
460: break;
461: case Apdi:
462: printf ("\tm68k_areg (regs, %s) = %sa;\n", reg, name);
463: break;
464: default:
465: break;
466: }
467: }
468:
469: static void genastore (char *from, amodes mode, char *reg, wordsizes size, char *to)
470: {
471: switch (mode) {
472: case Dreg:
473: switch (size) {
474: case sz_byte:
475: printf ("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from);
476: break;
477: case sz_word:
478: printf ("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from);
479: break;
480: case sz_long:
481: printf ("\tm68k_dreg(regs, %s) = (%s);\n", reg, from);
482: break;
483: default:
484: abort ();
485: }
486: break;
487: case Areg:
488: switch (size) {
489: case sz_word:
490: fprintf (stderr, "Foo\n");
491: printf ("\tm68k_areg(regs, %s) = (uae_s32)(uae_s16)(%s);\n", reg, from);
492: break;
493: case sz_long:
494: printf ("\tm68k_areg(regs, %s) = (%s);\n", reg, from);
495: break;
496: default:
497: abort ();
498: }
499: break;
500: case Aind:
501: case Aipi:
502: case Apdi:
503: case Ad16:
504: case Ad8r:
505: case absw:
506: case absl:
507: case PC16:
508: case PC8r:
509: if (using_prefetch)
510: sync_m68k_pc ();
511: switch (size) {
512: case sz_byte:
513: insn_n_cycles += 4;
514: printf ("\tput_byte(%sa,%s);\n", to, from);
515: break;
516: case sz_word:
517: insn_n_cycles += 4;
518: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
519: abort ();
520: printf ("\tput_word(%sa,%s);\n", to, from);
521: break;
522: case sz_long:
523: insn_n_cycles += 8;
524: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
525: abort ();
526: printf ("\tput_long(%sa,%s);\n", to, from);
527: break;
528: default:
529: abort ();
530: }
531: break;
532: case imm:
533: case imm0:
534: case imm1:
535: case imm2:
536: case immi:
537: abort ();
538: break;
539: default:
540: abort ();
541: }
542: }
543:
1.1.1.2 root 544:
1.1 root 545: static void genmovemel (uae_u16 opcode)
546: {
547: char getcode[100];
1.1.1.3 root 548: int bMovemLong = (table68k[opcode].size == sz_long);
549: int size = bMovemLong ? 4 : 2;
1.1 root 550:
1.1.1.3 root 551: if (bMovemLong) {
1.1 root 552: strcpy (getcode, "get_long(srca)");
553: } else {
554: strcpy (getcode, "(uae_s32)(uae_s16)get_word(srca)");
555: }
556:
557: printf ("\tuae_u16 mask = %s;\n", gen_nextiword ());
558: printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1.1.1.2 root 559: printf ("\tretcycles = 0;\n");
1.1.1.3 root 560: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1);
1.1 root 561: start_brace ();
1.1.1.2 root 562: printf ("\twhile (dmask) { m68k_dreg(regs, movem_index1[dmask]) = %s;"
1.1.1.3 root 563: " srca += %d; dmask = movem_next[dmask]; retcycles+=%d; }\n",
564: getcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 565: printf ("\twhile (amask) { m68k_areg(regs, movem_index1[amask]) = %s;"
1.1.1.3 root 566: " srca += %d; amask = movem_next[amask]; retcycles+=%d; }\n",
567: getcode, size, (bMovemLong ? 8 : 4));
1.1 root 568:
569: if (table68k[opcode].dmode == Aipi)
570: printf ("\tm68k_areg(regs, dstreg) = srca;\n");
1.1.1.2 root 571:
572: /* Better cycles - experimental! (Thothy) */
573: switch(table68k[opcode].dmode)
1.1.1.3 root 574: {
1.1.1.2 root 575: case Aind: insn_n_cycles=12; break;
576: case Aipi: insn_n_cycles=12; break;
577: case Ad16: insn_n_cycles=16; break;
578: case Ad8r: insn_n_cycles=18; break;
579: case absw: insn_n_cycles=16; break;
580: case absl: insn_n_cycles=20; break;
581: case PC16: insn_n_cycles=16; break;
582: case PC8r: insn_n_cycles=18; break;
1.1.1.3 root 583: }
584: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 585: }
586:
587: static void genmovemle (uae_u16 opcode)
588: {
589: char putcode[100];
1.1.1.3 root 590: int bMovemLong = (table68k[opcode].size == sz_long);
591: int size = bMovemLong ? 4 : 2;
592:
593: if (bMovemLong) {
1.1 root 594: strcpy (putcode, "put_long(srca,");
595: } else {
596: strcpy (putcode, "put_word(srca,");
597: }
598:
599: printf ("\tuae_u16 mask = %s;\n", gen_nextiword ());
1.1.1.3 root 600: printf ("\tretcycles = 0;\n");
1.1 root 601: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1);
602: if (using_prefetch)
603: sync_m68k_pc ();
604:
605: start_brace ();
606: if (table68k[opcode].dmode == Apdi) {
1.1.1.2 root 607: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
608: printf ("\twhile (amask) { srca -= %d; %s m68k_areg(regs, movem_index2[amask]));"
1.1.1.3 root 609: " amask = movem_next[amask]; retcycles+=%d; }\n",
610: size, putcode, (bMovemLong ? 8 : 4));
1.1.1.2 root 611: printf ("\twhile (dmask) { srca -= %d; %s m68k_dreg(regs, movem_index2[dmask]));"
1.1.1.3 root 612: " dmask = movem_next[dmask]; retcycles+=%d; }\n",
613: size, putcode, (bMovemLong ? 8 : 4));
1.1.1.2 root 614: printf ("\tm68k_areg(regs, dstreg) = srca;\n");
1.1 root 615: } else {
1.1.1.2 root 616: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
617: printf ("\twhile (dmask) { %s m68k_dreg(regs, movem_index1[dmask])); srca += %d;"
1.1.1.3 root 618: " dmask = movem_next[dmask]; retcycles+=%d; }\n",
619: putcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 620: printf ("\twhile (amask) { %s m68k_areg(regs, movem_index1[amask])); srca += %d;"
1.1.1.3 root 621: " amask = movem_next[amask]; retcycles+=%d; }\n",
622: putcode, size, (bMovemLong ? 8 : 4));
1.1.1.2 root 623: }
624:
625: /* Better cycles - experimental! (Thothy) */
626: switch(table68k[opcode].dmode)
1.1.1.3 root 627: {
1.1.1.2 root 628: case Aind: insn_n_cycles=8; break;
629: case Apdi: insn_n_cycles=8; break;
630: case Ad16: insn_n_cycles=12; break;
631: case Ad8r: insn_n_cycles=14; break;
632: case absw: insn_n_cycles=12; break;
633: case absl: insn_n_cycles=16; break;
1.1.1.3 root 634: }
635: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 636: }
637:
1.1.1.2 root 638:
1.1 root 639: static void duplicate_carry (void)
640: {
641: printf ("\tCOPY_CARRY;\n");
642: }
643:
644: typedef enum
645: {
646: flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_zn,
647: flag_av, flag_sv
648: }
649: flagtypes;
650:
651: static void genflags_normal (flagtypes type, wordsizes size, char *value, char *src, char *dst)
652: {
653: char vstr[100], sstr[100], dstr[100];
654: char usstr[100], udstr[100];
655: char unsstr[100], undstr[100];
656:
657: switch (size) {
658: case sz_byte:
659: strcpy (vstr, "((uae_s8)(");
660: strcpy (usstr, "((uae_u8)(");
661: break;
662: case sz_word:
663: strcpy (vstr, "((uae_s16)(");
664: strcpy (usstr, "((uae_u16)(");
665: break;
666: case sz_long:
667: strcpy (vstr, "((uae_s32)(");
668: strcpy (usstr, "((uae_u32)(");
669: break;
670: default:
671: abort ();
672: }
673: strcpy (unsstr, usstr);
674:
675: strcpy (sstr, vstr);
676: strcpy (dstr, vstr);
677: strcat (vstr, value);
678: strcat (vstr, "))");
679: strcat (dstr, dst);
680: strcat (dstr, "))");
681: strcat (sstr, src);
682: strcat (sstr, "))");
683:
684: strcpy (udstr, usstr);
685: strcat (udstr, dst);
686: strcat (udstr, "))");
687: strcat (usstr, src);
688: strcat (usstr, "))");
689:
690: strcpy (undstr, unsstr);
691: strcat (unsstr, "-");
692: strcat (undstr, "~");
693: strcat (undstr, dst);
694: strcat (undstr, "))");
695: strcat (unsstr, src);
696: strcat (unsstr, "))");
697:
698: switch (type) {
699: case flag_logical_noclobber:
700: case flag_logical:
701: case flag_zn:
702: case flag_av:
703: case flag_sv:
704: case flag_addx:
705: case flag_subx:
706: break;
707:
708: case flag_add:
709: start_brace ();
710: printf ("uae_u32 %s = %s + %s;\n", value, dstr, sstr);
711: break;
712: case flag_sub:
713: case flag_cmp:
714: start_brace ();
715: printf ("uae_u32 %s = %s - %s;\n", value, dstr, sstr);
716: break;
717: }
718:
719: switch (type) {
720: case flag_logical_noclobber:
721: case flag_logical:
722: case flag_zn:
723: break;
724:
725: case flag_add:
726: case flag_sub:
727: case flag_addx:
728: case flag_subx:
729: case flag_cmp:
730: case flag_av:
731: case flag_sv:
732: start_brace ();
733: printf ("\t" BOOL_TYPE " flgs = %s < 0;\n", sstr);
734: printf ("\t" BOOL_TYPE " flgo = %s < 0;\n", dstr);
735: printf ("\t" BOOL_TYPE " flgn = %s < 0;\n", vstr);
736: break;
737: }
738:
739: switch (type) {
740: case flag_logical:
741: printf ("\tCLEAR_CZNV;\n");
742: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
743: printf ("\tSET_NFLG (%s < 0);\n", vstr);
744: break;
745: case flag_logical_noclobber:
746: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
747: printf ("\tSET_NFLG (%s < 0);\n", vstr);
748: break;
749: case flag_av:
750: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
751: break;
752: case flag_sv:
753: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
754: break;
755: case flag_zn:
756: printf ("\tSET_ZFLG (GET_ZFLG & (%s == 0));\n", vstr);
757: printf ("\tSET_NFLG (%s < 0);\n", vstr);
758: break;
759: case flag_add:
760: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
761: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
762: printf ("\tSET_CFLG (%s < %s);\n", undstr, usstr);
763: duplicate_carry ();
764: printf ("\tSET_NFLG (flgn != 0);\n");
765: break;
766: case flag_sub:
767: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
768: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
769: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
770: duplicate_carry ();
771: printf ("\tSET_NFLG (flgn != 0);\n");
772: break;
773: case flag_addx:
774: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n"); /* minterm SON: 0x42 */
775: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));\n"); /* minterm SON: 0xD4 */
776: duplicate_carry ();
777: break;
778: case flag_subx:
779: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));\n"); /* minterm SON: 0x24 */
780: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));\n"); /* minterm SON: 0xB2 */
781: duplicate_carry ();
782: break;
783: case flag_cmp:
784: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
785: printf ("\tSET_VFLG ((flgs != flgo) && (flgn != flgo));\n");
786: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
787: printf ("\tSET_NFLG (flgn != 0);\n");
788: break;
789: }
790: }
791:
792: static void genflags (flagtypes type, wordsizes size, char *value, char *src, char *dst)
793: {
794: /* Temporarily deleted 68k/ARM flag optimizations. I'd prefer to have
795: them in the appropriate m68k.h files and use just one copy of this
796: code here. The API can be changed if necessary. */
797: #ifdef OPTIMIZED_FLAGS
798: switch (type) {
799: case flag_add:
800: case flag_sub:
801: start_brace ();
802: printf ("\tuae_u32 %s;\n", value);
803: break;
804:
805: default:
806: break;
807: }
808:
809: /* At least some of those casts are fairly important! */
810: switch (type) {
811: case flag_logical_noclobber:
812: printf ("\t{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
813: if (strcmp (value, "0") == 0) {
814: printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n");
815: } else {
816: switch (size) {
817: case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
818: case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
819: case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
820: }
821: printf ("\tIOR_CZNV (oldcznv);\n");
822: }
823: printf ("\t}\n");
824: return;
825: case flag_logical:
826: if (strcmp (value, "0") == 0) {
827: printf ("\tSET_CZNV (FLAGVAL_Z);\n");
828: } else {
829: switch (size) {
830: case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
831: case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
832: case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
833: }
834: }
835: return;
836:
837: case flag_add:
838: switch (size) {
839: case sz_byte: printf ("\toptflag_addb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
840: case sz_word: printf ("\toptflag_addw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
841: case sz_long: printf ("\toptflag_addl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
842: }
843: return;
844:
845: case flag_sub:
846: switch (size) {
847: case sz_byte: printf ("\toptflag_subb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
848: case sz_word: printf ("\toptflag_subw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
849: case sz_long: printf ("\toptflag_subl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
850: }
851: return;
852:
853: case flag_cmp:
854: switch (size) {
855: case sz_byte: printf ("\toptflag_cmpb ((uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
856: case sz_word: printf ("\toptflag_cmpw ((uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
857: case sz_long: printf ("\toptflag_cmpl ((uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
858: }
859: return;
860:
861: default:
862: break;
863: }
864: #endif
865:
866: genflags_normal (type, size, value, src, dst);
867: }
868:
869: static void force_range_for_rox (const char *var, wordsizes size)
870: {
871: /* Could do a modulo operation here... which one is faster? */
872: switch (size) {
873: case sz_long:
874: printf ("\tif (%s >= 33) %s -= 33;\n", var, var);
875: break;
876: case sz_word:
877: printf ("\tif (%s >= 34) %s -= 34;\n", var, var);
878: printf ("\tif (%s >= 17) %s -= 17;\n", var, var);
879: break;
880: case sz_byte:
881: printf ("\tif (%s >= 36) %s -= 36;\n", var, var);
882: printf ("\tif (%s >= 18) %s -= 18;\n", var, var);
883: printf ("\tif (%s >= 9) %s -= 9;\n", var, var);
884: break;
885: }
886: }
887:
888: static const char *cmask (wordsizes size)
889: {
890: switch (size) {
891: case sz_byte: return "0x80";
892: case sz_word: return "0x8000";
893: case sz_long: return "0x80000000";
894: default: abort ();
895: }
896: }
897:
898: static int source_is_imm1_8 (struct instr *i)
899: {
900: return i->stype == 3;
901: }
902:
1.1.1.2 root 903:
904:
1.1 root 905: static void gen_opcode (unsigned long int opcode)
906: {
1.1.1.2 root 907: #if 0
908: char *amodenames[] = { "Dreg", "Areg", "Aind", "Aipi", "Apdi", "Ad16", "Ad8r",
909: "absw", "absl", "PC16", "PC8r", "imm", "imm0", "imm1", "imm2", "immi", "am_unknown", "am_illg"};
910: #endif
911:
1.1 root 912: struct instr *curi = table68k + opcode;
913: insn_n_cycles = 4;
914:
1.1.1.8 ! root 915: /* Store the family of the instruction (used to check for pairing on ST)
! 916: * and leave some space for patching in the current cycles later */
! 917: printf ("\tOpcodeFamily = %d; CurrentInstrCycles = \n", curi->mnemo);
! 918: nCurInstrCycPos = ftell(stdout) - 5;
! 919:
1.1 root 920: start_brace ();
921: m68k_pc_offset = 2;
1.1.1.2 root 922:
1.1 root 923: switch (curi->plev) {
924: case 0: /* not privileged */
925: break;
926: case 1: /* unprivileged only on 68000 */
927: if (cpu_level == 0)
928: break;
929: if (next_cpu_level < 0)
930: next_cpu_level = 0;
931:
932: /* fall through */
933: case 2: /* priviledged */
934: printf ("if (!regs.s) { Exception(8,0); goto %s; }\n", endlabelstr);
935: need_endlabel = 1;
936: start_brace ();
937: break;
938: case 3: /* privileged if size == word */
939: if (curi->size == sz_byte)
940: break;
941: printf ("if (!regs.s) { Exception(8,0); goto %s; }\n", endlabelstr);
942: need_endlabel = 1;
943: start_brace ();
944: break;
945: }
1.1.1.2 root 946:
947: /* Build the opcodes: */
1.1 root 948: switch (curi->mnemo) {
949: case i_OR:
950: case i_AND:
951: case i_EOR:
1.1.1.2 root 952: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
953: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
954: printf ("\tsrc %c= dst;\n", curi->mnemo == i_OR ? '|' : curi->mnemo == i_AND ? '&' : '^');
955: genflags (flag_logical, curi->size, "src", "", "");
956: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
957: if(curi->size==sz_long && curi->dmode==Dreg)
958: {
959: insn_n_cycles += 2;
960: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
961: insn_n_cycles += 2;
962: }
963: #if 0
964: /* Output the CPU cycles: */
965: fprintf(stderr,"MOVE, size %i: ",curi->size);
966: fprintf(stderr," %s ->",amodenames[curi->smode]);
967: fprintf(stderr," %s ",amodenames[curi->dmode]);
968: fprintf(stderr," Cycles: %i\n",insn_n_cycles);
969: #endif
970: break;
1.1 root 971: case i_ORSR:
972: case i_EORSR:
1.1.1.2 root 973: printf ("\tMakeSR();\n");
974: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
975: if (curi->size == sz_byte) {
976: printf ("\tsrc &= 0xFF;\n");
977: }
978: printf ("\tregs.sr %c= src;\n", curi->mnemo == i_EORSR ? '^' : '|');
979: printf ("\tMakeFromSR();\n");
980: insn_n_cycles = 20;
981: break;
1.1 root 982: case i_ANDSR:
1.1.1.2 root 983: printf ("\tMakeSR();\n");
984: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
985: if (curi->size == sz_byte) {
986: printf ("\tsrc |= 0xFF00;\n");
987: }
988: printf ("\tregs.sr &= src;\n");
989: printf ("\tMakeFromSR();\n");
990: insn_n_cycles = 20;
991: break;
1.1 root 992: case i_SUB:
993: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
994: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
995: start_brace ();
996: genflags (flag_sub, curi->size, "newv", "src", "dst");
997: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 998: if(curi->size==sz_long && curi->dmode==Dreg)
999: {
1000: insn_n_cycles += 2;
1001: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
1002: insn_n_cycles += 2;
1003: }
1.1 root 1004: break;
1005: case i_SUBA:
1006: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1007: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1008: start_brace ();
1009: printf ("\tuae_u32 newv = dst - src;\n");
1010: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.2 root 1011: if(curi->size==sz_long && curi->smode!=Dreg && curi->smode!=Areg && !(curi->smode>=imm && curi->smode<=immi))
1012: insn_n_cycles += 2;
1013: else
1014: insn_n_cycles += 4;
1.1.1.8 ! root 1015: if( (curi->smode==Ad8r) || (curi->smode==PC8r) ) /* [NP] on 68000 ST, d8(An,Xn) takes 2 cycles more */
! 1016: insn_n_cycles += 2;
1.1 root 1017: break;
1018: case i_SUBX:
1019: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1020: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1021: start_brace ();
1022: printf ("\tuae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);\n");
1023: genflags (flag_subx, curi->size, "newv", "src", "dst");
1024: genflags (flag_zn, curi->size, "newv", "", "");
1025: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1026: if(curi->smode==Dreg && curi->size==sz_long)
1027: insn_n_cycles=8;
1028: if(curi->smode==Apdi)
1029: {
1030: if(curi->size==sz_long)
1031: insn_n_cycles=30;
1032: else
1033: insn_n_cycles=18;
1034: }
1.1 root 1035: break;
1036: case i_SBCD:
1037: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1038: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1039: start_brace ();
1040: printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
1041: printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
1.1.1.4 root 1042: printf ("\tuae_u16 newv, tmp_newv;\n");
1043: printf ("\tint bcd = 0;\n");
1044: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
1045: printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
1046: printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
1047: printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);\n");
1.1 root 1048: duplicate_carry ();
1049: genflags (flag_zn, curi->size, "newv", "", "");
1.1.1.4 root 1050: printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
1.1 root 1051: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.4 root 1052: if(curi->smode==Dreg) insn_n_cycles=6;
1053: if(curi->smode==Apdi) insn_n_cycles=18;
1.1 root 1054: break;
1055: case i_ADD:
1056: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1057: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1058: start_brace ();
1.1.1.8 ! root 1059: printf("\trefill_prefetch (m68k_getpc(), 2);\n"); // FIXME [NP] For Transbeauce 2 demo, need better prefetch emulation
1.1 root 1060: genflags (flag_add, curi->size, "newv", "src", "dst");
1061: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1062: if(curi->size==sz_long && curi->dmode==Dreg)
1063: {
1064: insn_n_cycles += 2;
1065: if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
1066: insn_n_cycles += 2;
1067: }
1.1 root 1068: break;
1069: case i_ADDA:
1070: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1071: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1072: start_brace ();
1073: printf ("\tuae_u32 newv = dst + src;\n");
1074: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.2 root 1075: if(curi->size==sz_long && curi->smode!=Dreg && curi->smode!=Areg && !(curi->smode>=imm && curi->smode<=immi))
1076: insn_n_cycles += 2;
1077: else
1078: insn_n_cycles += 4;
1.1.1.8 ! root 1079: if( (curi->smode==Ad8r) || (curi->smode==PC8r) ) /* [NP] on 68000 ST, d8(An,Xn) takes 2 cycles more */
! 1080: insn_n_cycles += 2;
1.1 root 1081: break;
1082: case i_ADDX:
1083: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1084: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1085: start_brace ();
1086: printf ("\tuae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);\n");
1087: genflags (flag_addx, curi->size, "newv", "src", "dst");
1088: genflags (flag_zn, curi->size, "newv", "", "");
1089: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1090: if(curi->smode==Dreg && curi->size==sz_long)
1091: insn_n_cycles=8;
1092: if(curi->smode==Apdi)
1093: {
1094: if(curi->size==sz_long)
1095: insn_n_cycles=30;
1096: else
1097: insn_n_cycles=18;
1098: }
1.1 root 1099: break;
1100: case i_ABCD:
1101: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1102: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1103: start_brace ();
1104: printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);\n");
1105: printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
1.1.1.4 root 1106: printf ("\tuae_u16 newv, tmp_newv;\n");
1.1 root 1107: printf ("\tint cflg;\n");
1.1.1.4 root 1108: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;");
1109: printf ("\tif (newv_lo > 9) { newv += 6; }\n");
1110: printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
1111: printf ("\tif (cflg) newv += 0x60;\n");
1.1 root 1112: printf ("\tSET_CFLG (cflg);\n");
1113: duplicate_carry ();
1114: genflags (flag_zn, curi->size, "newv", "", "");
1.1.1.4 root 1115: printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
1.1 root 1116: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.4 root 1117: if(curi->smode==Dreg) insn_n_cycles=6;
1118: if(curi->smode==Apdi) insn_n_cycles=18;
1.1 root 1119: break;
1120: case i_NEG:
1121: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1122: start_brace ();
1123: genflags (flag_sub, curi->size, "dst", "src", "0");
1124: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1125: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1126: break;
1127: case i_NEGX:
1128: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1129: start_brace ();
1130: printf ("\tuae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);\n");
1131: genflags (flag_subx, curi->size, "newv", "src", "0");
1132: genflags (flag_zn, curi->size, "newv", "", "");
1133: genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1134: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1135: break;
1136: case i_NBCD:
1137: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1138: start_brace ();
1139: printf ("\tuae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
1140: printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
1141: printf ("\tuae_u16 newv;\n");
1142: printf ("\tint cflg;\n");
1.1.1.4 root 1143: printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
1144: printf ("\tnewv = newv_hi + newv_lo;");
1145: printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
1146: printf ("\tif (cflg) newv -= 0x60;\n");
1.1 root 1147: printf ("\tSET_CFLG (cflg);\n");
1148: duplicate_carry();
1149: genflags (flag_zn, curi->size, "newv", "", "");
1150: genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1.1.1.4 root 1151: if(curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1152: break;
1153: case i_CLR:
1154: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1.1.1.8 ! root 1155:
! 1156: /* [NP] CLR does a read before the write only on 68000 */
! 1157: /* but there's no cycle penalty for doing the read */
! 1158: if ( curi->smode != Dreg ) // only if destination is memory
! 1159: {
! 1160: if (curi->size==sz_byte)
! 1161: printf ("\tuae_s8 src = get_byte(srca);\n");
! 1162: else if (curi->size==sz_word)
! 1163: printf ("\tuae_s16 src = get_word(srca);\n");
! 1164: else if (curi->size==sz_long)
! 1165: printf ("\tuae_s32 src = get_long(srca);\n");
! 1166: }
! 1167:
1.1 root 1168: genflags (flag_logical, curi->size, "0", "", "");
1169: genastore ("0", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1170: if(curi->size==sz_long)
1.1.1.3 root 1171: {
1.1.1.2 root 1172: if(curi->smode==Dreg)
1173: insn_n_cycles += 2;
1174: else
1175: insn_n_cycles += 4;
1.1.1.3 root 1176: }
1.1.1.2 root 1177: if(curi->smode!=Dreg)
1178: insn_n_cycles += 4;
1.1 root 1179: break;
1180: case i_NOT:
1181: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1182: start_brace ();
1183: printf ("\tuae_u32 dst = ~src;\n");
1184: genflags (flag_logical, curi->size, "dst", "", "");
1185: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 1186: if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2;
1.1 root 1187: break;
1188: case i_TST:
1189: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1190: genflags (flag_logical, curi->size, "src", "", "");
1191: break;
1192: case i_BTST:
1193: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1194: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1195: if (curi->size == sz_byte)
1196: printf ("\tsrc &= 7;\n");
1197: else
1198: printf ("\tsrc &= 31;\n");
1199: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1.1.1.2 root 1200: if(curi->dmode==Dreg) insn_n_cycles += 2;
1.1 root 1201: break;
1202: case i_BCHG:
1203: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1204: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1205: if (curi->size == sz_byte)
1206: printf ("\tsrc &= 7;\n");
1207: else
1208: printf ("\tsrc &= 31;\n");
1209: printf ("\tdst ^= (1 << src);\n");
1210: printf ("\tSET_ZFLG (((uae_u32)dst & (1 << src)) >> src);\n");
1211: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1212: if(curi->dmode==Dreg) insn_n_cycles += 4;
1.1 root 1213: break;
1214: case i_BCLR:
1215: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1216: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1217: if (curi->size == sz_byte)
1218: printf ("\tsrc &= 7;\n");
1219: else
1220: printf ("\tsrc &= 31;\n");
1221: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1222: printf ("\tdst &= ~(1 << src);\n");
1223: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1224: if(curi->dmode==Dreg) insn_n_cycles += 6;
1.1.1.8 ! root 1225: /* [NP] BCLR #n,Dx takes 12 cycles instead of 14 if n<16 */
! 1226: if((curi->smode==imm1) && (curi->dmode==Dreg))
! 1227: printf ("\tif ( src < 16 ) { m68k_incpc(4); return 12; }\n");
! 1228: /* [NP] BCLR Dy,Dx takes 8 cycles instead of 10 if Dy<16 */
! 1229: if((curi->smode==Dreg) && (curi->dmode==Dreg))
! 1230: printf ("\tif ( src < 16 ) { m68k_incpc(2); return 8; }\n");
1.1 root 1231: break;
1232: case i_BSET:
1233: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1234: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1235: if (curi->size == sz_byte)
1236: printf ("\tsrc &= 7;\n");
1237: else
1238: printf ("\tsrc &= 31;\n");
1239: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
1240: printf ("\tdst |= (1 << src);\n");
1241: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1242: if(curi->dmode==Dreg) insn_n_cycles += 4;
1.1 root 1243: break;
1244: case i_CMPM:
1245: case i_CMP:
1246: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1247: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1248: start_brace ();
1249: genflags (flag_cmp, curi->size, "newv", "src", "dst");
1.1.1.2 root 1250: if(curi->size==sz_long && curi->dmode==Dreg)
1251: insn_n_cycles += 2;
1.1 root 1252: break;
1253: case i_CMPA:
1254: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1255: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1256: start_brace ();
1257: genflags (flag_cmp, sz_long, "newv", "src", "dst");
1.1.1.2 root 1258: insn_n_cycles += 2;
1.1 root 1259: break;
1260: /* The next two are coded a little unconventional, but they are doing
1261: * weird things... */
1262: case i_MVPRM:
1263: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1264:
1265: printf ("\tuaecptr memp = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword ());
1266: if (curi->size == sz_word) {
1267: printf ("\tput_byte(memp, src >> 8); put_byte(memp + 2, src);\n");
1268: } else {
1269: printf ("\tput_byte(memp, src >> 24); put_byte(memp + 2, src >> 16);\n");
1270: printf ("\tput_byte(memp + 4, src >> 8); put_byte(memp + 6, src);\n");
1271: }
1.1.1.2 root 1272: if(curi->size==sz_long) insn_n_cycles=24; else insn_n_cycles=16;
1.1 root 1273: break;
1274: case i_MVPMR:
1275: printf ("\tuaecptr memp = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword ());
1276: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1277: if (curi->size == sz_word) {
1278: printf ("\tuae_u16 val = (get_byte(memp) << 8) + get_byte(memp + 2);\n");
1279: } else {
1280: printf ("\tuae_u32 val = (get_byte(memp) << 24) + (get_byte(memp + 2) << 16)\n");
1281: printf (" + (get_byte(memp + 4) << 8) + get_byte(memp + 6);\n");
1282: }
1283: genastore ("val", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1284: if(curi->size==sz_long) insn_n_cycles=24; else insn_n_cycles=16;
1.1 root 1285: break;
1286: case i_MOVE:
1287: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1288: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1.1.1.8 ! root 1289:
! 1290: /* [NP] genamode counts 2 cycles if dest is -(An), this is wrong. */
! 1291: /* For move dest (An), (An)+ and -(An) take the same time */
! 1292: /* (for other instr, dest -(An) really takes 2 cycles more) */
! 1293: if ( curi->dmode == Apdi )
! 1294: insn_n_cycles -= 2; /* correct the wrong cycle count for -(An) */
! 1295:
1.1 root 1296: genflags (flag_logical, curi->size, "src", "", "");
1297: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
1298: break;
1299: case i_MOVEA:
1300: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1301: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1302: if (curi->size == sz_word) {
1303: printf ("\tuae_u32 val = (uae_s32)(uae_s16)src;\n");
1304: } else {
1305: printf ("\tuae_u32 val = src;\n");
1306: }
1307: genastore ("val", curi->dmode, "dstreg", sz_long, "dst");
1308: break;
1.1.1.2 root 1309: case i_MVSR2: /* Move from SR */
1.1 root 1310: genamode (curi->smode, "srcreg", sz_word, "src", 2, 0);
1311: printf ("\tMakeSR();\n");
1312: if (curi->size == sz_byte)
1313: genastore ("regs.sr & 0xff", curi->smode, "srcreg", sz_word, "src");
1314: else
1315: genastore ("regs.sr", curi->smode, "srcreg", sz_word, "src");
1.1.1.2 root 1316: if (curi->smode==Dreg) insn_n_cycles += 2; else insn_n_cycles += 4;
1.1 root 1317: break;
1.1.1.2 root 1318: case i_MV2SR: /* Move to SR */
1.1 root 1319: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1320: if (curi->size == sz_byte)
1321: printf ("\tMakeSR();\n\tregs.sr &= 0xFF00;\n\tregs.sr |= src & 0xFF;\n");
1322: else {
1323: printf ("\tregs.sr = src;\n");
1324: }
1325: printf ("\tMakeFromSR();\n");
1.1.1.2 root 1326: insn_n_cycles += 8;
1.1 root 1327: break;
1328: case i_SWAP:
1329: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1330: start_brace ();
1331: printf ("\tuae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);\n");
1332: genflags (flag_logical, sz_long, "dst", "", "");
1333: genastore ("dst", curi->smode, "srcreg", sz_long, "src");
1334: break;
1335: case i_EXG:
1336: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1337: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1338: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
1339: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 1340: insn_n_cycles = 6;
1.1 root 1341: break;
1342: case i_EXT:
1343: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1344: start_brace ();
1345: switch (curi->size) {
1346: case sz_byte: printf ("\tuae_u32 dst = (uae_s32)(uae_s8)src;\n"); break;
1347: case sz_word: printf ("\tuae_u16 dst = (uae_s16)(uae_s8)src;\n"); break;
1348: case sz_long: printf ("\tuae_u32 dst = (uae_s32)(uae_s16)src;\n"); break;
1349: default: abort ();
1350: }
1351: genflags (flag_logical,
1352: curi->size == sz_word ? sz_word : sz_long, "dst", "", "");
1353: genastore ("dst", curi->smode, "srcreg",
1354: curi->size == sz_word ? sz_word : sz_long, "src");
1355: break;
1356: case i_MVMEL:
1357: genmovemel (opcode);
1358: break;
1359: case i_MVMLE:
1360: genmovemle (opcode);
1361: break;
1362: case i_TRAP:
1363: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1364: sync_m68k_pc ();
1365: printf ("\tException(src+32,0);\n");
1366: m68k_pc_offset = 0;
1367: break;
1368: case i_MVR2USP:
1369: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1370: printf ("\tregs.usp = src;\n");
1371: break;
1372: case i_MVUSP2R:
1373: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1374: genastore ("regs.usp", curi->smode, "srcreg", curi->size, "src");
1375: break;
1376: case i_RESET:
1377: printf ("\tcustomreset();\n");
1.1.1.2 root 1378: insn_n_cycles = 132; /* I am not so sure about this!? - Thothy */
1.1 root 1379: break;
1380: case i_NOP:
1381: break;
1382: case i_STOP:
1383: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1384: printf ("\tregs.sr = src;\n");
1385: printf ("\tMakeFromSR();\n");
1386: printf ("\tm68k_setstopped(1);\n");
1.1.1.2 root 1387: insn_n_cycles = 4;
1.1 root 1388: break;
1389: case i_RTE:
1390: if (cpu_level == 0) {
1391: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1392: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1393: printf ("\tregs.sr = sr; m68k_setpc_rte(pc);\n");
1394: fill_prefetch_0 ();
1395: printf ("\tMakeFromSR();\n");
1396: } else {
1397: int old_brace_level = n_braces;
1398: if (next_cpu_level < 0)
1399: next_cpu_level = 0;
1400: printf ("\tuae_u16 newsr; uae_u32 newpc; for (;;) {\n");
1401: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1402: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1403: genamode (Aipi, "7", sz_word, "format", 1, 0);
1404: printf ("\tnewsr = sr; newpc = pc;\n");
1405: printf ("\tif ((format & 0xF000) == 0x0000) { break; }\n");
1406: printf ("\telse if ((format & 0xF000) == 0x1000) { ; }\n");
1407: printf ("\telse if ((format & 0xF000) == 0x2000) { m68k_areg(regs, 7) += 4; break; }\n");
1408: printf ("\telse if ((format & 0xF000) == 0x8000) { m68k_areg(regs, 7) += 50; break; }\n");
1409: printf ("\telse if ((format & 0xF000) == 0x9000) { m68k_areg(regs, 7) += 12; break; }\n");
1410: printf ("\telse if ((format & 0xF000) == 0xa000) { m68k_areg(regs, 7) += 24; break; }\n");
1411: printf ("\telse if ((format & 0xF000) == 0xb000) { m68k_areg(regs, 7) += 84; break; }\n");
1412: printf ("\telse { Exception(14,0); goto %s; }\n", endlabelstr);
1413: printf ("\tregs.sr = newsr; MakeFromSR();\n}\n");
1414: pop_braces (old_brace_level);
1415: printf ("\tregs.sr = newsr; MakeFromSR();\n");
1416: printf ("\tm68k_setpc_rte(newpc);\n");
1417: fill_prefetch_0 ();
1418: need_endlabel = 1;
1419: }
1420: /* PC is set and prefetch filled. */
1421: m68k_pc_offset = 0;
1.1.1.2 root 1422: insn_n_cycles = 20;
1.1 root 1423: break;
1424: case i_RTD:
1425: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1426: genamode (curi->smode, "srcreg", curi->size, "offs", 1, 0);
1427: printf ("\tm68k_areg(regs, 7) += offs;\n");
1428: printf ("\tm68k_setpc_rte(pc);\n");
1429: fill_prefetch_0 ();
1430: /* PC is set and prefetch filled. */
1431: m68k_pc_offset = 0;
1432: break;
1433: case i_LINK:
1434: genamode (Apdi, "7", sz_long, "old", 2, 0);
1435: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
1436: genastore ("src", Apdi, "7", sz_long, "old");
1437: genastore ("m68k_areg(regs, 7)", curi->smode, "srcreg", sz_long, "src");
1438: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0);
1439: printf ("\tm68k_areg(regs, 7) += offs;\n");
1440: break;
1441: case i_UNLK:
1442: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1443: printf ("\tm68k_areg(regs, 7) = src;\n");
1444: genamode (Aipi, "7", sz_long, "old", 1, 0);
1445: genastore ("old", curi->smode, "srcreg", curi->size, "src");
1446: break;
1447: case i_RTS:
1448: printf ("\tm68k_do_rts();\n");
1449: fill_prefetch_0 ();
1450: m68k_pc_offset = 0;
1.1.1.2 root 1451: insn_n_cycles = 16;
1.1 root 1452: break;
1453: case i_TRAPV:
1454: sync_m68k_pc ();
1455: printf ("\tif (GET_VFLG) { Exception(7,m68k_getpc()); goto %s; }\n", endlabelstr);
1456: need_endlabel = 1;
1457: break;
1458: case i_RTR:
1459: printf ("\tMakeSR();\n");
1460: genamode (Aipi, "7", sz_word, "sr", 1, 0);
1461: genamode (Aipi, "7", sz_long, "pc", 1, 0);
1462: printf ("\tregs.sr &= 0xFF00; sr &= 0xFF;\n");
1463: printf ("\tregs.sr |= sr; m68k_setpc(pc);\n");
1464: fill_prefetch_0 ();
1465: printf ("\tMakeFromSR();\n");
1466: m68k_pc_offset = 0;
1.1.1.2 root 1467: insn_n_cycles = 20;
1.1 root 1468: break;
1469: case i_JSR:
1470: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1471: printf ("\tm68k_do_jsr(m68k_getpc() + %d, srca);\n", m68k_pc_offset);
1472: fill_prefetch_0 ();
1473: m68k_pc_offset = 0;
1.1.1.2 root 1474: switch(curi->smode)
1475: {
1476: case Aind: insn_n_cycles=16; break;
1477: case Ad16: insn_n_cycles=18; break;
1478: case Ad8r: insn_n_cycles=22; break;
1479: case absw: insn_n_cycles=18; break;
1480: case absl: insn_n_cycles=20; break;
1481: case PC16: insn_n_cycles=18; break;
1482: case PC8r: insn_n_cycles=22; break;
1483: }
1.1 root 1484: break;
1485: case i_JMP:
1486: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1487: printf ("\tm68k_setpc(srca);\n");
1488: fill_prefetch_0 ();
1489: m68k_pc_offset = 0;
1.1.1.2 root 1490: switch(curi->smode)
1491: {
1492: case Aind: insn_n_cycles=8; break;
1493: case Ad16: insn_n_cycles=10; break;
1494: case Ad8r: insn_n_cycles=14; break;
1495: case absw: insn_n_cycles=10; break;
1496: case absl: insn_n_cycles=12; break;
1497: case PC16: insn_n_cycles=10; break;
1498: case PC8r: insn_n_cycles=14; break;
1499: }
1.1 root 1500: break;
1501: case i_BSR:
1502: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1503: printf ("\tuae_s32 s = (uae_s32)src + 2;\n");
1504: if (using_exception_3) {
1505: printf ("\tif (src & 1) {\n");
1.1.1.8 ! root 1506: printf ("\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n"); // [NP] FIXME should be +4, not +2 (same as DBcc) ?
1.1 root 1507: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + s;\n");
1508: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0); goto %s;\n", endlabelstr);
1509: printf ("\t}\n");
1510: need_endlabel = 1;
1511: }
1512: printf ("\tm68k_do_bsr(m68k_getpc() + %d, s);\n", m68k_pc_offset);
1513: fill_prefetch_0 ();
1514: m68k_pc_offset = 0;
1.1.1.2 root 1515: insn_n_cycles = 18;
1.1 root 1516: break;
1517: case i_Bcc:
1518: if (curi->size == sz_long) {
1519: if (cpu_level < 2) {
1520: printf ("\tm68k_incpc(2);\n");
1521: printf ("\tif (!cctrue(%d)) goto %s;\n", curi->cc, endlabelstr);
1522: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n");
1523: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + 1;\n");
1524: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0); goto %s;\n", endlabelstr);
1525: need_endlabel = 1;
1526: } else {
1527: if (next_cpu_level < 1)
1528: next_cpu_level = 1;
1529: }
1530: }
1531: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1532: printf ("\tif (!cctrue(%d)) goto didnt_jump;\n", curi->cc);
1533: if (using_exception_3) {
1534: printf ("\tif (src & 1) {\n");
1.1.1.8 ! root 1535: printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n"); // [NP] FIXME should be +4, not +2 (same as DBcc) ?
1.1 root 1536: printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)src;\n");
1537: printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0); goto %s;\n", endlabelstr);
1538: printf ("\t}\n");
1539: need_endlabel = 1;
1540: }
1541: printf ("\tm68k_incpc ((uae_s32)src + 2);\n");
1542: fill_prefetch_0 ();
1.1.1.2 root 1543: printf ("\treturn 10;\n");
1.1 root 1544: printf ("didnt_jump:;\n");
1545: need_endlabel = 1;
1.1.1.2 root 1546: insn_n_cycles = (curi->size == sz_byte) ? 8 : 12;
1.1 root 1547: break;
1548: case i_LEA:
1549: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1550: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1551: genastore ("srca", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.7 root 1552: /* Set correct cycles: According to the M68K User Manual, LEA takes 12
1553: * cycles in Ad8r and PC8r mode, but it takes 14 (or 16) cycles on a real ST: */
1554: if (curi->smode == Ad8r || curi->smode == PC8r)
1555: insn_n_cycles = 14;
1.1 root 1556: break;
1557: case i_PEA:
1558: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
1559: genamode (Apdi, "7", sz_long, "dst", 2, 0);
1560: genastore ("srca", Apdi, "7", sz_long, "dst");
1.1.1.7 root 1561: /* Set correct cycles: */
1.1.1.2 root 1562: switch(curi->smode)
1563: {
1564: case Aind: insn_n_cycles=12; break;
1565: case Ad16: insn_n_cycles=16; break;
1.1.1.7 root 1566: /* Note: according to the M68K User Manual, PEA takes 20 cycles for
1567: * the Ad8r mode, but on a real ST, it takes 22 (or 24) cycles! */
1568: case Ad8r: insn_n_cycles=22; break;
1.1.1.2 root 1569: case absw: insn_n_cycles=16; break;
1570: case absl: insn_n_cycles=20; break;
1571: case PC16: insn_n_cycles=16; break;
1.1.1.7 root 1572: /* Note: PEA with PC8r takes 20 cycles according to the User Manual,
1573: * but it takes 22 (or 24) cycles on a real ST: */
1574: case PC8r: insn_n_cycles=22; break;
1.1.1.2 root 1575: }
1.1 root 1576: break;
1577: case i_DBcc:
1578: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1579: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0);
1580:
1.1.1.2 root 1581: printf ("\tif (!cctrue(%d)) {\n\t", curi->cc);
1.1 root 1582: genastore ("(src-1)", curi->smode, "srcreg", curi->size, "src");
1583:
1584: printf ("\t\tif (src) {\n");
1585: if (using_exception_3) {
1586: printf ("\t\t\tif (offs & 1) {\n");
1.1.1.8 ! root 1587: printf ("\t\t\tlast_addr_for_exception_3 = m68k_getpc() + 2 + 2;\n"); // [NP] last_addr is pc+4, not pc+2
1.1 root 1588: printf ("\t\t\tlast_fault_for_exception_3 = m68k_getpc() + 2 + (uae_s32)offs + 2;\n");
1589: printf ("\t\t\tlast_op_for_exception_3 = opcode; Exception(3,0); goto %s;\n", endlabelstr);
1590: printf ("\t\t}\n");
1591: need_endlabel = 1;
1592: }
1593: printf ("\t\t\tm68k_incpc((uae_s32)offs + 2);\n");
1594: fill_prefetch_0 ();
1.1.1.2 root 1595: printf ("\t\t\treturn 10;\n");
1596: printf ("\t\t} else {\n\t\t\t");
1597: {
1598: int tmp_offset = m68k_pc_offset;
1599: sync_m68k_pc(); /* not so nice to call it here... */
1600: m68k_pc_offset = tmp_offset;
1601: }
1602: printf ("\t\t\treturn 14;\n");
1603: printf ("\t\t}\n");
1.1 root 1604: printf ("\t}\n");
1605: insn_n_cycles = 12;
1606: need_endlabel = 1;
1607: break;
1608: case i_Scc:
1609: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
1610: start_brace ();
1611: printf ("\tint val = cctrue(%d) ? 0xff : 0;\n", curi->cc);
1612: genastore ("val", curi->smode, "srcreg", curi->size, "src");
1.1.1.8 ! root 1613: if (curi->smode!=Dreg) insn_n_cycles += 4;
! 1614: else
! 1615: { /* [NP] if result is TRUE, we return 6 instead of 4 */
! 1616: printf ("\tif (val) { m68k_incpc(2) ; return 4+2; }\n");
! 1617: }
1.1 root 1618: break;
1619: case i_DIVU:
1620: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1621: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1622: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1623: sync_m68k_pc ();
1624: /* Clear V flag when dividing by zero - Alcatraz Odyssey demo depends
1625: * on this (actually, it's doing a DIVS). */
1626: printf ("\tif (src == 0) { SET_VFLG (0); Exception (5, oldpc); goto %s; } else {\n", endlabelstr);
1627: printf ("\tuae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
1628: printf ("\tuae_u32 rem = (uae_u32)dst %% (uae_u32)(uae_u16)src;\n");
1629: /* The N flag appears to be set each time there is an overflow.
1630: * Weird. */
1631: printf ("\tif (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
1632: genflags (flag_logical, sz_word, "newv", "", "");
1633: printf ("\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
1634: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1635: printf ("\t}\n");
1636: printf ("\t}\n");
1.1.1.8 ! root 1637: // insn_n_cycles += 136;
! 1638: printf ("\tretcycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);\n");
! 1639: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 1640: need_endlabel = 1;
1641: break;
1642: case i_DIVS:
1643: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1644: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1645: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1646: sync_m68k_pc ();
1647: printf ("\tif (src == 0) { SET_VFLG (0); Exception(5,oldpc); goto %s; } else {\n", endlabelstr);
1648: printf ("\tuae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
1649: printf ("\tuae_u16 rem = (uae_s32)dst %% (uae_s32)(uae_s16)src;\n");
1650: printf ("\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
1651: printf ("\tif (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;\n");
1652: genflags (flag_logical, sz_word, "newv", "", "");
1653: printf ("\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
1654: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1655: printf ("\t}\n");
1656: printf ("\t}\n");
1.1.1.8 ! root 1657: // insn_n_cycles += 154;
! 1658: printf ("\tretcycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);\n");
! 1659: sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
1.1 root 1660: need_endlabel = 1;
1661: break;
1662: case i_MULU:
1663: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1664: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0);
1665: start_brace ();
1666: printf ("\tuae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;\n");
1667: genflags (flag_logical, sz_long, "newv", "", "");
1668: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.8 ! root 1669: /* [NP] number of cycles is 38 + 2n + ea time ; n is the number of 1 bits in src */
! 1670: insn_n_cycles += 38-4; /* insn_n_cycles is already initialized to 4 instead of 0 */
! 1671: printf ("\twhile (src) { if (src & 1) retcycles++; src = (uae_u16)src >> 1; }\n");
! 1672: sprintf(exactCpuCycles," return (%i+retcycles*2);", insn_n_cycles);
1.1 root 1673: break;
1674: case i_MULS:
1675: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1676: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0);
1677: start_brace ();
1678: printf ("\tuae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;\n");
1.1.1.8 ! root 1679: printf ("\tuae_u32 src2;\n");
1.1 root 1680: genflags (flag_logical, sz_long, "newv", "", "");
1681: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1.1.1.8 ! root 1682: /* [NP] number of cycles is 38 + 2n + ea time ; n is the number of 01 or 10 patterns in src expanded to 17 bits */
! 1683: insn_n_cycles += 38-4; /* insn_n_cycles is already initialized to 4 instead of 0 */
! 1684: printf ("\tsrc2 = ((uae_u32)src) << 1;\n");
! 1685: printf ("\twhile (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }\n");
! 1686: sprintf(exactCpuCycles," return (%i+retcycles*2);", insn_n_cycles);
1.1 root 1687: break;
1688: case i_CHK:
1689: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1690: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1691: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
1.1.1.8 ! root 1692: sync_m68k_pc ();
1.1 root 1693: printf ("\tif ((uae_s32)dst < 0) { SET_NFLG (1); Exception(6,oldpc); goto %s; }\n", endlabelstr);
1694: printf ("\telse if (dst > src) { SET_NFLG (0); Exception(6,oldpc); goto %s; }\n", endlabelstr);
1695: need_endlabel = 1;
1.1.1.2 root 1696: insn_n_cycles += 6;
1.1 root 1697: break;
1698:
1699: case i_CHK2:
1700: printf ("\tuaecptr oldpc = m68k_getpc();\n");
1701: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
1702: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
1703: printf ("\t{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];\n");
1704: switch (curi->size) {
1705: case sz_byte:
1706: printf ("\tlower=(uae_s32)(uae_s8)get_byte(dsta); upper = (uae_s32)(uae_s8)get_byte(dsta+1);\n");
1707: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;\n");
1708: break;
1709: case sz_word:
1710: printf ("\tlower=(uae_s32)(uae_s16)get_word(dsta); upper = (uae_s32)(uae_s16)get_word(dsta+2);\n");
1711: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;\n");
1712: break;
1713: case sz_long:
1714: printf ("\tlower=get_long(dsta); upper = get_long(dsta+4);\n");
1715: break;
1716: default:
1717: abort ();
1718: }
1719: printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
1720: printf ("\tSET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
1.1.1.8 ! root 1721: sync_m68k_pc ();
1.1 root 1722: printf ("\tif ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc); goto %s; }\n}\n", endlabelstr);
1723: need_endlabel = 1;
1724: break;
1725:
1726: case i_ASR:
1727: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1728: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1729: start_brace ();
1730: switch (curi->size) {
1731: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1732: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1733: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1734: default: abort ();
1735: }
1736: printf ("\tuae_u32 sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1);
1737: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1738: printf ("\tretcycles = cnt;\n");
1.1 root 1739: printf ("\tCLEAR_CZNV;\n");
1740: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1741: printf ("\t\tval = %s & (uae_u32)-sign;\n", bit_mask (curi->size));
1742: printf ("\t\tSET_CFLG (sign);\n");
1743: duplicate_carry ();
1744: if (source_is_imm1_8 (curi))
1745: printf ("\t} else {\n");
1746: else
1747: printf ("\t} else if (cnt > 0) {\n");
1748: printf ("\t\tval >>= cnt - 1;\n");
1749: printf ("\t\tSET_CFLG (val & 1);\n");
1750: duplicate_carry ();
1751: printf ("\t\tval >>= 1;\n");
1752: printf ("\t\tval |= (%s << (%d - cnt)) & (uae_u32)-sign;\n",
1753: bit_mask (curi->size),
1754: bit_size (curi->size));
1755: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
1756: printf ("\t}\n");
1757: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1758: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1759: if(curi->size==sz_long)
1760: strcpy(exactCpuCycles," return (8+retcycles*2);");
1761: else
1762: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1763: break;
1764: case i_ASL:
1765: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1766: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1767: start_brace ();
1768: switch (curi->size) {
1769: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1770: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1771: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1772: default: abort ();
1773: }
1774: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1775: printf ("\tretcycles = cnt;\n");
1.1 root 1776: printf ("\tCLEAR_CZNV;\n");
1777: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1778: printf ("\t\tSET_VFLG (val != 0);\n");
1779: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
1780: bit_size (curi->size));
1781: duplicate_carry ();
1782: printf ("\t\tval = 0;\n");
1783: if (source_is_imm1_8 (curi))
1784: printf ("\t} else {\n");
1785: else
1786: printf ("\t} else if (cnt > 0) {\n");
1787: printf ("\t\tuae_u32 mask = (%s << (%d - cnt)) & %s;\n",
1788: bit_mask (curi->size),
1789: bit_size (curi->size) - 1,
1790: bit_mask (curi->size));
1791: printf ("\t\tSET_VFLG ((val & mask) != mask && (val & mask) != 0);\n");
1792: printf ("\t\tval <<= cnt - 1;\n");
1793: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
1794: duplicate_carry ();
1795: printf ("\t\tval <<= 1;\n");
1796: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
1797: printf ("\t}\n");
1798: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1799: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1800: if(curi->size==sz_long)
1801: strcpy(exactCpuCycles," return (8+retcycles*2);");
1802: else
1803: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1804: break;
1805: case i_LSR:
1806: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1807: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1808: start_brace ();
1809: switch (curi->size) {
1810: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1811: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1812: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1813: default: abort ();
1814: }
1815: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1816: printf ("\tretcycles = cnt;\n");
1.1 root 1817: printf ("\tCLEAR_CZNV;\n");
1818: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1819: printf ("\t\tSET_CFLG ((cnt == %d) & (val >> %d));\n",
1820: bit_size (curi->size), bit_size (curi->size) - 1);
1821: duplicate_carry ();
1822: printf ("\t\tval = 0;\n");
1823: if (source_is_imm1_8 (curi))
1824: printf ("\t} else {\n");
1825: else
1826: printf ("\t} else if (cnt > 0) {\n");
1827: printf ("\t\tval >>= cnt - 1;\n");
1828: printf ("\t\tSET_CFLG (val & 1);\n");
1829: duplicate_carry ();
1830: printf ("\t\tval >>= 1;\n");
1831: printf ("\t}\n");
1832: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1833: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1834: if(curi->size==sz_long)
1835: strcpy(exactCpuCycles," return (8+retcycles*2);");
1836: else
1837: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1838: break;
1839: case i_LSL:
1840: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1841: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1842: start_brace ();
1843: switch (curi->size) {
1844: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1845: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1846: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1847: default: abort ();
1848: }
1849: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1850: printf ("\tretcycles = cnt;\n");
1.1 root 1851: printf ("\tCLEAR_CZNV;\n");
1852: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
1853: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
1854: bit_size (curi->size));
1855: duplicate_carry ();
1856: printf ("\t\tval = 0;\n");
1857: if (source_is_imm1_8 (curi))
1858: printf ("\t} else {\n");
1859: else
1860: printf ("\t} else if (cnt > 0) {\n");
1861: printf ("\t\tval <<= (cnt - 1);\n");
1862: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
1863: duplicate_carry ();
1864: printf ("\t\tval <<= 1;\n");
1865: printf ("\tval &= %s;\n", bit_mask (curi->size));
1866: printf ("\t}\n");
1867: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1868: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1869: if(curi->size==sz_long)
1870: strcpy(exactCpuCycles," return (8+retcycles*2);");
1871: else
1872: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1873: break;
1874: case i_ROL:
1875: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1876: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1877: start_brace ();
1878: switch (curi->size) {
1879: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1880: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1881: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1882: default: abort ();
1883: }
1884: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1885: printf ("\tretcycles = cnt;\n");
1.1 root 1886: printf ("\tCLEAR_CZNV;\n");
1887: if (source_is_imm1_8 (curi))
1888: printf ("{");
1889: else
1890: printf ("\tif (cnt > 0) {\n");
1891: printf ("\tuae_u32 loval;\n");
1892: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
1893: printf ("\tloval = val >> (%d - cnt);\n", bit_size (curi->size));
1894: printf ("\tval <<= cnt;\n");
1895: printf ("\tval |= loval;\n");
1896: printf ("\tval &= %s;\n", bit_mask (curi->size));
1897: printf ("\tSET_CFLG (val & 1);\n");
1898: printf ("}\n");
1899: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1900: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1901: if(curi->size==sz_long)
1902: strcpy(exactCpuCycles," return (8+retcycles*2);");
1903: else
1904: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1905: break;
1906: case i_ROR:
1907: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1908: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1909: start_brace ();
1910: switch (curi->size) {
1911: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1912: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1913: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1914: default: abort ();
1915: }
1916: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1917: printf ("\tretcycles = cnt;\n");
1.1 root 1918: printf ("\tCLEAR_CZNV;\n");
1919: if (source_is_imm1_8 (curi))
1920: printf ("{");
1921: else
1922: printf ("\tif (cnt > 0) {");
1923: printf ("\tuae_u32 hival;\n");
1924: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
1925: printf ("\thival = val << (%d - cnt);\n", bit_size (curi->size));
1926: printf ("\tval >>= cnt;\n");
1927: printf ("\tval |= hival;\n");
1928: printf ("\tval &= %s;\n", bit_mask (curi->size));
1929: printf ("\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
1930: printf ("\t}\n");
1931: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1932: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1933: if(curi->size==sz_long)
1934: strcpy(exactCpuCycles," return (8+retcycles*2);");
1935: else
1936: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1937: break;
1938: case i_ROXL:
1939: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1940: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1941: start_brace ();
1942: switch (curi->size) {
1943: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1944: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1945: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1946: default: abort ();
1947: }
1948: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1949: printf ("\tretcycles = cnt;\n");
1.1 root 1950: printf ("\tCLEAR_CZNV;\n");
1951: if (source_is_imm1_8 (curi))
1952: printf ("{");
1953: else {
1954: force_range_for_rox ("cnt", curi->size);
1955: printf ("\tif (cnt > 0) {\n");
1956: }
1957: printf ("\tcnt--;\n");
1958: printf ("\t{\n\tuae_u32 carry;\n");
1959: printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
1960: printf ("\tcarry = loval & 1;\n");
1961: printf ("\tval = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);\n");
1962: printf ("\tSET_XFLG (carry);\n");
1963: printf ("\tval &= %s;\n", bit_mask (curi->size));
1964: printf ("\t} }\n");
1965: printf ("\tSET_CFLG (GET_XFLG);\n");
1966: genflags (flag_logical_noclobber, curi->size, "val", "", "");
1967: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 1968: if(curi->size==sz_long)
1969: strcpy(exactCpuCycles," return (8+retcycles*2);");
1970: else
1971: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 1972: break;
1973: case i_ROXR:
1974: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
1975: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
1976: start_brace ();
1977: switch (curi->size) {
1978: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
1979: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
1980: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
1981: default: abort ();
1982: }
1983: printf ("\tcnt &= 63;\n");
1.1.1.2 root 1984: printf ("\tretcycles = cnt;\n");
1.1 root 1985: printf ("\tCLEAR_CZNV;\n");
1986: if (source_is_imm1_8 (curi))
1987: printf ("{");
1988: else {
1989: force_range_for_rox ("cnt", curi->size);
1990: printf ("\tif (cnt > 0) {\n");
1991: }
1992: printf ("\tcnt--;\n");
1993: printf ("\t{\n\tuae_u32 carry;\n");
1994: printf ("\tuae_u32 hival = (val << 1) | GET_XFLG;\n");
1995: printf ("\thival <<= (%d - cnt);\n", bit_size (curi->size) - 1);
1996: printf ("\tval >>= cnt;\n");
1997: printf ("\tcarry = val & 1;\n");
1998: printf ("\tval >>= 1;\n");
1999: printf ("\tval |= hival;\n");
2000: printf ("\tSET_XFLG (carry);\n");
2001: printf ("\tval &= %s;\n", bit_mask (curi->size));
2002: printf ("\t} }\n");
2003: printf ("\tSET_CFLG (GET_XFLG);\n");
2004: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2005: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
1.1.1.2 root 2006: if(curi->size==sz_long)
2007: strcpy(exactCpuCycles," return (8+retcycles*2);");
2008: else
2009: strcpy(exactCpuCycles," return (6+retcycles*2);");
1.1 root 2010: break;
2011: case i_ASRW:
2012: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2013: start_brace ();
2014: switch (curi->size) {
2015: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2016: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2017: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2018: default: abort ();
2019: }
2020: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
2021: printf ("\tuae_u32 cflg = val & 1;\n");
2022: printf ("\tval = (val >> 1) | sign;\n");
2023: genflags (flag_logical, curi->size, "val", "", "");
2024: printf ("\tSET_CFLG (cflg);\n");
2025: duplicate_carry ();
2026: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2027: break;
2028: case i_ASLW:
2029: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2030: start_brace ();
2031: switch (curi->size) {
2032: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2033: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2034: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2035: default: abort ();
2036: }
2037: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
2038: printf ("\tuae_u32 sign2;\n");
2039: printf ("\tval <<= 1;\n");
2040: genflags (flag_logical, curi->size, "val", "", "");
2041: printf ("\tsign2 = %s & val;\n", cmask (curi->size));
2042: printf ("\tSET_CFLG (sign != 0);\n");
2043: duplicate_carry ();
2044:
2045: printf ("\tSET_VFLG (GET_VFLG | (sign2 != sign));\n");
2046: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2047: break;
2048: case i_LSRW:
2049: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2050: start_brace ();
2051: switch (curi->size) {
2052: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2053: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2054: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2055: default: abort ();
2056: }
2057: printf ("\tuae_u32 carry = val & 1;\n");
2058: printf ("\tval >>= 1;\n");
2059: genflags (flag_logical, curi->size, "val", "", "");
2060: printf ("SET_CFLG (carry);\n");
2061: duplicate_carry ();
2062: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2063: break;
2064: case i_LSLW:
2065: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2066: start_brace ();
2067: switch (curi->size) {
2068: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2069: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2070: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2071: default: abort ();
2072: }
2073: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2074: printf ("\tval <<= 1;\n");
2075: genflags (flag_logical, curi->size, "val", "", "");
2076: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2077: duplicate_carry ();
2078: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2079: break;
2080: case i_ROLW:
2081: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2082: start_brace ();
2083: switch (curi->size) {
2084: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2085: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2086: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2087: default: abort ();
2088: }
2089: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2090: printf ("\tval <<= 1;\n");
2091: printf ("\tif (carry) val |= 1;\n");
2092: genflags (flag_logical, curi->size, "val", "", "");
2093: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2094: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2095: break;
2096: case i_RORW:
2097: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2098: start_brace ();
2099: switch (curi->size) {
2100: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2101: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2102: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2103: default: abort ();
2104: }
2105: printf ("\tuae_u32 carry = val & 1;\n");
2106: printf ("\tval >>= 1;\n");
2107: printf ("\tif (carry) val |= %s;\n", cmask (curi->size));
2108: genflags (flag_logical, curi->size, "val", "", "");
2109: printf ("SET_CFLG (carry);\n");
2110: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2111: break;
2112: case i_ROXLW:
2113: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2114: start_brace ();
2115: switch (curi->size) {
2116: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2117: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2118: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2119: default: abort ();
2120: }
2121: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
2122: printf ("\tval <<= 1;\n");
2123: printf ("\tif (GET_XFLG) val |= 1;\n");
2124: genflags (flag_logical, curi->size, "val", "", "");
2125: printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
2126: duplicate_carry ();
2127: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2128: break;
2129: case i_ROXRW:
2130: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
2131: start_brace ();
2132: switch (curi->size) {
2133: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
2134: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
2135: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2136: default: abort ();
2137: }
2138: printf ("\tuae_u32 carry = val & 1;\n");
2139: printf ("\tval >>= 1;\n");
2140: printf ("\tif (GET_XFLG) val |= %s;\n", cmask (curi->size));
2141: genflags (flag_logical, curi->size, "val", "", "");
2142: printf ("SET_CFLG (carry);\n");
2143: duplicate_carry ();
2144: genastore ("val", curi->smode, "srcreg", curi->size, "data");
2145: break;
2146: case i_MOVEC2:
2147: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2148: start_brace ();
2149: printf ("\tint regno = (src >> 12) & 15;\n");
2150: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
2151: printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
2152: break;
2153: case i_MOVE2C:
2154: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2155: start_brace ();
2156: printf ("\tint regno = (src >> 12) & 15;\n");
2157: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
2158: printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
2159: break;
2160: case i_CAS:
2161: {
2162: int old_brace_level;
2163: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2164: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2165: start_brace ();
2166: printf ("\tint ru = (src >> 6) & 7;\n");
2167: printf ("\tint rc = src & 7;\n");
2168: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, rc)", "dst");
2169: printf ("\tif (GET_ZFLG)");
2170: old_brace_level = n_braces;
2171: start_brace ();
2172: genastore ("(m68k_dreg(regs, ru))", curi->dmode, "dstreg", curi->size, "dst");
2173: pop_braces (old_brace_level);
2174: printf ("else");
2175: start_brace ();
2176: printf ("m68k_dreg(regs, rc) = dst;\n");
2177: pop_braces (old_brace_level);
2178: }
2179: break;
2180: case i_CAS2:
2181: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2182: printf ("\tuae_u32 rn1 = regs.regs[(extra >> 28) & 15];\n");
2183: printf ("\tuae_u32 rn2 = regs.regs[(extra >> 12) & 15];\n");
2184: if (curi->size == sz_word) {
2185: int old_brace_level = n_braces;
2186: printf ("\tuae_u16 dst1 = get_word(rn1), dst2 = get_word(rn2);\n");
2187: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
2188: printf ("\tif (GET_ZFLG) {\n");
2189: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
2190: printf ("\tif (GET_ZFLG) {\n");
2191: printf ("\tput_word(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n");
2192: printf ("\tput_word(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n");
2193: printf ("\t}}\n");
2194: pop_braces (old_brace_level);
2195: printf ("\tif (! GET_ZFLG) {\n");
2196: printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = (m68k_dreg(regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
2197: printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = (m68k_dreg(regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
2198: printf ("\t}\n");
2199: } else {
2200: int old_brace_level = n_braces;
2201: printf ("\tuae_u32 dst1 = get_long(rn1), dst2 = get_long(rn2);\n");
2202: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
2203: printf ("\tif (GET_ZFLG) {\n");
2204: genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
2205: printf ("\tif (GET_ZFLG) {\n");
2206: printf ("\tput_long(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n");
2207: printf ("\tput_long(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n");
2208: printf ("\t}}\n");
2209: pop_braces (old_brace_level);
2210: printf ("\tif (! GET_ZFLG) {\n");
2211: printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = dst1;\n");
2212: printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = dst2;\n");
2213: printf ("\t}\n");
2214: }
2215: break;
2216: case i_MOVES: /* ignore DFC and SFC because we have no MMU */
2217: {
2218: int old_brace_level;
2219: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2220: printf ("\tif (extra & 0x800)\n");
2221: old_brace_level = n_braces;
2222: start_brace ();
2223: printf ("\tuae_u32 src = regs.regs[(extra >> 12) & 15];\n");
2224: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
2225: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
2226: pop_braces (old_brace_level);
2227: printf ("else");
2228: start_brace ();
2229: genamode (curi->dmode, "dstreg", curi->size, "src", 1, 0);
2230: printf ("\tif (extra & 0x8000) {\n");
2231: switch (curi->size) {
2232: case sz_byte: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;\n"); break;
2233: case sz_word: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;\n"); break;
2234: case sz_long: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = src;\n"); break;
2235: default: abort ();
2236: }
2237: printf ("\t} else {\n");
2238: genastore ("src", Dreg, "(extra >> 12) & 7", curi->size, "");
2239: printf ("\t}\n");
2240: pop_braces (old_brace_level);
2241: }
2242: break;
2243: case i_BKPT: /* only needed for hardware emulators */
2244: sync_m68k_pc ();
2245: printf ("\top_illg(opcode);\n");
2246: break;
2247: case i_CALLM: /* not present in 68030 */
2248: sync_m68k_pc ();
2249: printf ("\top_illg(opcode);\n");
2250: break;
2251: case i_RTM: /* not present in 68030 */
2252: sync_m68k_pc ();
2253: printf ("\top_illg(opcode);\n");
2254: break;
2255: case i_TRAPcc:
2256: if (curi->smode != am_unknown && curi->smode != am_illg)
2257: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
2258: printf ("\tif (cctrue(%d)) { Exception(7,m68k_getpc()); goto %s; }\n", curi->cc, endlabelstr);
2259: need_endlabel = 1;
2260: break;
2261: case i_DIVL:
2262: sync_m68k_pc ();
2263: start_brace ();
2264: printf ("\tuaecptr oldpc = m68k_getpc();\n");
2265: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2266: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2267: sync_m68k_pc ();
2268: printf ("\tm68k_divl(opcode, dst, extra, oldpc);\n");
2269: break;
2270: case i_MULL:
2271: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2272: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
2273: sync_m68k_pc ();
2274: printf ("\tm68k_mull(opcode, dst, extra);\n");
2275: break;
2276: case i_BFTST:
2277: case i_BFEXTU:
2278: case i_BFCHG:
2279: case i_BFEXTS:
2280: case i_BFCLR:
2281: case i_BFFFO:
2282: case i_BFSET:
2283: case i_BFINS:
2284: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2285: genamode (curi->dmode, "dstreg", sz_long, "dst", 2, 0);
2286: start_brace ();
2287: printf ("\tuae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;\n");
2288: printf ("\tint width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;\n");
2289: if (curi->dmode == Dreg) {
2290: printf ("\tuae_u32 tmp = m68k_dreg(regs, dstreg) << (offset & 0x1f);\n");
2291: } else {
2292: printf ("\tuae_u32 tmp,bf0,bf1;\n");
2293: printf ("\tdsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);\n");
2294: printf ("\tbf0 = get_long(dsta);bf1 = get_byte(dsta+4) & 0xff;\n");
2295: printf ("\ttmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));\n");
2296: }
2297: printf ("\ttmp >>= (32 - width);\n");
2298: printf ("\tSET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);\n");
2299: printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
2300: switch (curi->mnemo) {
2301: case i_BFTST:
2302: break;
2303: case i_BFEXTU:
2304: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n");
2305: break;
2306: case i_BFCHG:
2307: printf ("\ttmp = ~tmp;\n");
2308: break;
2309: case i_BFEXTS:
2310: printf ("\tif (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);\n");
2311: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n");
2312: break;
2313: case i_BFCLR:
2314: printf ("\ttmp = 0;\n");
2315: break;
2316: case i_BFFFO:
2317: printf ("\t{ uae_u32 mask = 1 << (width-1);\n");
2318: printf ("\twhile (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}\n");
2319: printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = offset;\n");
2320: break;
2321: case i_BFSET:
2322: printf ("\ttmp = 0xffffffff;\n");
2323: break;
2324: case i_BFINS:
2325: printf ("\ttmp = m68k_dreg(regs, (extra >> 12) & 7);\n");
1.1.1.4 root 2326: printf ("\tSET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);\n");
2327: printf ("\tSET_ZFLG (tmp == 0);\n");
1.1 root 2328: break;
2329: default:
2330: break;
2331: }
2332: if (curi->mnemo == i_BFCHG
2333: || curi->mnemo == i_BFCLR
2334: || curi->mnemo == i_BFSET
2335: || curi->mnemo == i_BFINS)
2336: {
2337: printf ("\ttmp <<= (32 - width);\n");
2338: if (curi->dmode == Dreg) {
2339: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ((offset & 0x1f) == 0 ? 0 :\n");
2340: printf ("\t\t(0xffffffff << (32 - (offset & 0x1f))))) |\n");
2341: printf ("\t\t(tmp >> (offset & 0x1f)) |\n");
2342: printf ("\t\t(((offset & 0x1f) + width) >= 32 ? 0 :\n");
2343: printf (" (m68k_dreg(regs, dstreg) & ((uae_u32)0xffffffff >> ((offset & 0x1f) + width))));\n");
2344: } else {
2345: printf ("\tbf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |\n");
2346: printf ("\t\t(tmp >> (offset & 7)) |\n");
2347: printf ("\t\t(((offset & 7) + width) >= 32 ? 0 :\n");
2348: printf ("\t\t (bf0 & ((uae_u32)0xffffffff >> ((offset & 7) + width))));\n");
2349: printf ("\tput_long(dsta,bf0 );\n");
2350: printf ("\tif (((offset & 7) + width) > 32) {\n");
2351: printf ("\t\tbf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |\n");
2352: printf ("\t\t\t(tmp << (8 - (offset & 7)));\n");
2353: printf ("\t\tput_byte(dsta+4,bf1);\n");
2354: printf ("\t}\n");
2355: }
2356: }
2357: break;
2358: case i_PACK:
2359: if (curi->smode == Dreg) {
2360: printf ("\tuae_u16 val = m68k_dreg(regs, srcreg) + %s;\n", gen_nextiword ());
2361: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);\n");
2362: } else {
2363: printf ("\tuae_u16 val;\n");
2364: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2365: printf ("\tval = (uae_u16)get_byte(m68k_areg(regs, srcreg));\n");
2366: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2367: printf ("\tval = (val | ((uae_u16)get_byte(m68k_areg(regs, srcreg)) << 8)) + %s;\n", gen_nextiword ());
2368: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2369: printf ("\tput_byte(m68k_areg(regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));\n");
2370: }
2371: break;
2372: case i_UNPK:
2373: if (curi->smode == Dreg) {
2374: printf ("\tuae_u16 val = m68k_dreg(regs, srcreg);\n");
2375: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword ());
2376: printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffff0000) | (val & 0xffff);\n");
2377: } else {
2378: printf ("\tuae_u16 val;\n");
2379: printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
2380: printf ("\tval = (uae_u16)get_byte(m68k_areg(regs, srcreg));\n");
2381: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword ());
2382: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2383: printf ("\tput_byte(m68k_areg(regs, dstreg),val);\n");
2384: printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
2385: printf ("\tput_byte(m68k_areg(regs, dstreg),val >> 8);\n");
2386: }
2387: break;
2388: case i_TAS:
2389: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
2390: genflags (flag_logical, curi->size, "src", "", "");
2391: printf ("\tsrc |= 0x80;\n");
2392: genastore ("src", curi->smode, "srcreg", curi->size, "src");
1.1.1.2 root 2393: if( curi->smode!=Dreg ) insn_n_cycles += 2;
1.1 root 2394: break;
2395: case i_FPP:
2396: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2397: sync_m68k_pc ();
2398: printf ("\tfpp_opp(opcode,extra);\n");
2399: break;
2400: case i_FDBcc:
2401: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2402: sync_m68k_pc ();
2403: printf ("\tfdbcc_opp(opcode,extra);\n");
2404: break;
2405: case i_FScc:
2406: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2407: sync_m68k_pc ();
2408: printf ("\tfscc_opp(opcode,extra);\n");
2409: break;
2410: case i_FTRAPcc:
2411: sync_m68k_pc ();
2412: start_brace ();
2413: printf ("\tuaecptr oldpc = m68k_getpc();\n");
2414: if (curi->smode != am_unknown && curi->smode != am_illg)
2415: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
2416: sync_m68k_pc ();
2417: printf ("\tftrapcc_opp(opcode,oldpc);\n");
2418: break;
2419: case i_FBcc:
2420: sync_m68k_pc ();
2421: start_brace ();
2422: printf ("\tuaecptr pc = m68k_getpc();\n");
2423: genamode (curi->dmode, "srcreg", curi->size, "extra", 1, 0);
2424: sync_m68k_pc ();
2425: printf ("\tfbcc_opp(opcode,pc,extra);\n");
2426: break;
2427: case i_FSAVE:
2428: sync_m68k_pc ();
2429: printf ("\tfsave_opp(opcode);\n");
2430: break;
2431: case i_FRESTORE:
2432: sync_m68k_pc ();
2433: printf ("\tfrestore_opp(opcode);\n");
2434: break;
2435:
2436: case i_CINVL:
2437: case i_CINVP:
2438: case i_CINVA:
2439: case i_CPUSHL:
2440: case i_CPUSHP:
2441: case i_CPUSHA:
2442: break;
2443: case i_MOVE16:
1.1.1.4 root 2444: if ((opcode & 0xfff8) == 0xf620) {
2445: /* MOVE16 (Ax)+,(Ay)+ */
2446: printf ("\tuaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
2447: printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword());
2448: printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n");
2449: printf ("\tput_long(memd, get_long(mems));\n");
2450: printf ("\tput_long(memd+4, get_long(mems+4));\n");
2451: printf ("\tput_long(memd+8, get_long(mems+8));\n");
2452: printf ("\tput_long(memd+12, get_long(mems+12));\n");
2453: printf ("\tif (srcreg != dstreg)\n");
2454: printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2455: printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2456: } else {
2457: /* Other variants */
2458: genamode (curi->smode, "srcreg", curi->size, "mems", 0, 2);
2459: genamode (curi->dmode, "dstreg", curi->size, "memd", 0, 2);
2460: printf ("\tmemsa &= ~15;\n");
2461: printf ("\tmemda &= ~15;\n");
2462: printf ("\tput_long(memda, get_long(memsa));\n");
2463: printf ("\tput_long(memda+4, get_long(memsa+4));\n");
2464: printf ("\tput_long(memda+8, get_long(memsa+8));\n");
2465: printf ("\tput_long(memda+12, get_long(memsa+12));\n");
2466: if ((opcode & 0xfff8) == 0xf600)
2467: printf ("\tm68k_areg(regs, srcreg) += 16;\n");
2468: else if ((opcode & 0xfff8) == 0xf608)
2469: printf ("\tm68k_areg(regs, dstreg) += 16;\n");
2470: }
1.1 root 2471: break;
2472:
2473: case i_MMUOP:
2474: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2475: sync_m68k_pc ();
2476: printf ("\tmmu_op(opcode,extra);\n");
2477: break;
2478: default:
2479: abort ();
2480: break;
2481: }
2482: finish_braces ();
2483: sync_m68k_pc ();
2484: }
2485:
2486: static void generate_includes (FILE * f)
2487: {
2488: fprintf (f, "#include \"sysdeps.h\"\n");
2489: fprintf (f, "#include \"hatari-glue.h\"\n");
2490: fprintf (f, "#include \"maccess.h\"\n");
2491: fprintf (f, "#include \"memory.h\"\n");
2492: fprintf (f, "#include \"newcpu.h\"\n");
2493: fprintf (f, "#include \"cputbl.h\"\n");
2494: fprintf (f, "#define CPUFUNC(x) x##_ff\n"
2495: "#ifdef NOFLAGS\n"
2496: "#include \"noflags.h\"\n"
2497: "#endif\n");
2498: }
2499:
2500: static int postfix;
2501:
2502: static void generate_one_opcode (int rp)
2503: {
2504: int i;
2505: uae_u16 smsk, dmsk;
2506: long int opcode = opcode_map[rp];
2507:
1.1.1.2 root 2508: exactCpuCycles[0] = 0; /* Default: not used */
2509:
1.1 root 2510: if (table68k[opcode].mnemo == i_ILLG
2511: || table68k[opcode].clev > cpu_level)
2512: return;
2513:
2514: for (i = 0; lookuptab[i].name[0]; i++) {
2515: if (table68k[opcode].mnemo == lookuptab[i].mnemo)
2516: break;
2517: }
2518:
2519: if (table68k[opcode].handler != -1)
2520: return;
2521:
2522: if (opcode_next_clev[rp] != cpu_level) {
2523: fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp],
2524: opcode, lookuptab[i].name);
2525: return;
2526: }
2527: fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, postfix, opcode, lookuptab[i].name);
2528: fprintf (headerfile, "extern cpuop_func op_%lx_%d_nf;\n", opcode, postfix);
2529: fprintf (headerfile, "extern cpuop_func op_%lx_%d_ff;\n", opcode, postfix);
2530: printf ("unsigned long REGPARAM2 CPUFUNC(op_%lx_%d)(uae_u32 opcode) /* %s */\n{\n", opcode, postfix, lookuptab[i].name);
2531:
2532: switch (table68k[opcode].stype) {
2533: case 0: smsk = 7; break;
2534: case 1: smsk = 255; break;
2535: case 2: smsk = 15; break;
2536: case 3: smsk = 7; break;
2537: case 4: smsk = 7; break;
2538: case 5: smsk = 63; break;
1.1.1.4 root 2539: case 7: smsk = 3; break;
1.1 root 2540: default: abort ();
2541: }
2542: dmsk = 7;
2543:
2544: next_cpu_level = -1;
2545: if (table68k[opcode].suse
2546: && table68k[opcode].smode != imm && table68k[opcode].smode != imm0
2547: && table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
2548: && table68k[opcode].smode != absw && table68k[opcode].smode != absl
2549: && table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
2550: {
2551: if (table68k[opcode].spos == -1) {
2552: if (((int) table68k[opcode].sreg) >= 128)
2553: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].sreg);
2554: else
2555: printf ("\tuae_u32 srcreg = %d;\n", (int) table68k[opcode].sreg);
2556: } else {
2557: char source[100];
2558: int pos = table68k[opcode].spos;
2559:
2560: if (pos)
2561: sprintf (source, "((opcode >> %d) & %d)", pos, smsk);
2562: else
2563: sprintf (source, "(opcode & %d)", smsk);
2564:
2565: if (table68k[opcode].stype == 3)
2566: printf ("\tuae_u32 srcreg = imm8_table[%s];\n", source);
2567: else if (table68k[opcode].stype == 1)
2568: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%s;\n", source);
2569: else
2570: printf ("\tuae_u32 srcreg = %s;\n", source);
2571: }
2572: }
2573: if (table68k[opcode].duse
2574: /* Yes, the dmode can be imm, in case of LINK or DBcc */
2575: && table68k[opcode].dmode != imm && table68k[opcode].dmode != imm0
2576: && table68k[opcode].dmode != imm1 && table68k[opcode].dmode != imm2
2577: && table68k[opcode].dmode != absw && table68k[opcode].dmode != absl)
2578: {
2579: if (table68k[opcode].dpos == -1) {
2580: if (((int) table68k[opcode].dreg) >= 128)
2581: printf ("\tuae_u32 dstreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].dreg);
2582: else
2583: printf ("\tuae_u32 dstreg = %d;\n", (int) table68k[opcode].dreg);
2584: } else {
2585: int pos = table68k[opcode].dpos;
2586: #if 0
2587: /* Check that we can do the little endian optimization safely. */
2588: if (pos < 8 && (dmsk >> (8 - pos)) != 0)
2589: abort ();
2590: #endif
2591: if (pos)
2592: printf ("\tuae_u32 dstreg = (opcode >> %d) & %d;\n",
2593: pos, dmsk);
2594: else
2595: printf ("\tuae_u32 dstreg = opcode & %d;\n", dmsk);
2596: }
2597: }
2598: need_endlabel = 0;
2599: endlabelno++;
2600: sprintf (endlabelstr, "endlabel%d", endlabelno);
1.1.1.2 root 2601: if(table68k[opcode].mnemo==i_ASR || table68k[opcode].mnemo==i_ASL || table68k[opcode].mnemo==i_LSR || table68k[opcode].mnemo==i_LSL
2602: || table68k[opcode].mnemo==i_ROL || table68k[opcode].mnemo==i_ROR || table68k[opcode].mnemo==i_ROXL || table68k[opcode].mnemo==i_ROXR
1.1.1.8 ! root 2603: || table68k[opcode].mnemo==i_MVMEL || table68k[opcode].mnemo==i_MVMLE
! 2604: || table68k[opcode].mnemo==i_MULU || table68k[opcode].mnemo==i_MULS
! 2605: || table68k[opcode].mnemo==i_DIVU || table68k[opcode].mnemo==i_DIVS )
! 2606: printf("\tunsigned int retcycles = 0;\n");
1.1 root 2607: gen_opcode (opcode);
2608: if (need_endlabel)
2609: printf ("%s: ;\n", endlabelstr);
1.1.1.8 ! root 2610:
! 2611: if (strlen(exactCpuCycles) > 0)
! 2612: printf("%s\n",exactCpuCycles);
! 2613: else
! 2614: printf ("return %d;\n", insn_n_cycles);
! 2615: /* Now patch in the instruction cycles at the beginning of the function: */
! 2616: fseek(stdout, nCurInstrCycPos, SEEK_SET);
! 2617: printf("%d;", insn_n_cycles);
! 2618: fseek(stdout, 0, SEEK_END);
! 2619:
1.1 root 2620: printf ("}\n");
2621: opcode_next_clev[rp] = next_cpu_level;
2622: opcode_last_postfix[rp] = postfix;
2623: }
2624:
2625: static void generate_func (void)
2626: {
2627: int i, j, rp;
2628:
2629: using_prefetch = 0;
2630: using_exception_3 = 0;
2631: for (i = 0; i < 6; i++) {
2632: cpu_level = 4 - i;
2633: if (i == 5) {
2634: cpu_level = 0;
2635: using_prefetch = 1;
2636: using_exception_3 = 1;
2637: for (rp = 0; rp < nr_cpuop_funcs; rp++)
2638: opcode_next_clev[rp] = 0;
2639: }
2640:
2641: postfix = i;
1.1.1.7 root 2642: fprintf (stblfile, "const struct cputbl CPUFUNC(op_smalltbl_%d)[] = {\n", postfix);
1.1 root 2643:
2644: /* sam: this is for people with low memory (eg. me :)) */
2645: printf ("\n"
2646: "#if !defined(PART_1) && !defined(PART_2) && "
2647: "!defined(PART_3) && !defined(PART_4) && "
2648: "!defined(PART_5) && !defined(PART_6) && "
2649: "!defined(PART_7) && !defined(PART_8)"
2650: "\n"
2651: "#define PART_1 1\n"
2652: "#define PART_2 1\n"
2653: "#define PART_3 1\n"
2654: "#define PART_4 1\n"
2655: "#define PART_5 1\n"
2656: "#define PART_6 1\n"
2657: "#define PART_7 1\n"
2658: "#define PART_8 1\n"
2659: "#endif\n\n");
2660:
2661: rp = 0;
2662: for(j=1;j<=8;++j) {
2663: int k = (j*nr_cpuop_funcs)/8;
2664: printf ("#ifdef PART_%d\n",j);
2665: for (; rp < k; rp++)
2666: generate_one_opcode (rp);
2667: printf ("#endif\n\n");
2668: }
2669:
2670: fprintf (stblfile, "{ 0, 0, 0 }};\n");
2671: }
2672:
2673: }
2674:
2675: int main (int argc, char **argv)
2676: {
2677: read_table68k ();
2678: do_merges ();
2679:
2680: opcode_map = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2681: opcode_last_postfix = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2682: opcode_next_clev = (int *) malloc (sizeof (int) * nr_cpuop_funcs);
2683: counts = (unsigned long *) malloc (65536 * sizeof (unsigned long));
2684: read_counts ();
2685:
2686: /* It would be a lot nicer to put all in one file (we'd also get rid of
2687: * cputbl.h that way), but cpuopti can't cope. That could be fixed, but
2688: * I don't dare to touch the 68k version. */
2689:
2690: headerfile = fopen ("cputbl.h", "wb");
2691: stblfile = fopen ("cpustbl.c", "wb");
2692: freopen ("cpuemu.c", "wb", stdout);
2693:
2694: generate_includes (stdout);
2695: generate_includes (stblfile);
2696:
2697: generate_func ();
2698:
2699: free (table68k);
2700: return 0;
2701: }
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