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1.1 root 1: /*
1.1.1.4 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * Memory management
5: *
6: * (c) 1995 Bernd Schmidt
1.1.1.2 root 7: *
8: * Adaptation to Hatari by Thomas Huth
1.1.1.4 root 9: *
10: * This file is distributed under the GNU Public License, version 2 or at
11: * your option any later version. Read the file gpl.txt for details.
1.1 root 12: */
1.1.1.5 ! root 13: static char rcsid[] = "Hatari $Id: memory.c,v 1.12 2003/04/05 22:25:03 thothy Exp $";
1.1 root 14:
15: #include "sysdeps.h"
16: #include "hatari-glue.h"
17: #include "maccess.h"
18: #include "memory.h"
1.1.1.4 root 19: #include "../includes/main.h"
1.1 root 20: #include "../includes/tos.h"
1.1.1.3 root 21: #include "../includes/intercept.h"
22: #include "../includes/reset.h"
1.1.1.5 ! root 23: #include "../includes/decode.h"
! 24: #include "../includes/m68000.h"
! 25: #include "newcpu.h"
1.1 root 26:
27:
1.1.1.5 ! root 28: uae_u32 STmem_size, TTmem_size = 0;
! 29: uae_u32 TTmem_mask;
1.1 root 30:
1.1.1.5 ! root 31: #define STmem_start 0x00000000
! 32: #define ROMmem_start 0x00E00000
! 33: #define IOmem_start 0x00FF0000
! 34: #define TTmem_start 0x01000000
1.1 root 35:
1.1.1.5 ! root 36: #define IOmem_size 65536
! 37: #define ROMmem_size (0x00FF0000 - 0x00E00000) /* So we cover both possible ROM regions + cartridge */
1.1 root 38:
1.1.1.5 ! root 39: #define STmem_mask 0x00ffffff
! 40: #define ROMmem_mask 0x00ffffff
! 41: #define IOmem_mask (IOmem_size - 1)
1.1 root 42:
43:
44: #ifdef SAVE_MEMORY_BANKS
45: addrbank *mem_banks[65536];
46: #else
47: addrbank mem_banks[65536];
48: #endif
49:
50: #ifdef NO_INLINE_MEMORY_ACCESS
51: __inline__ uae_u32 longget (uaecptr addr)
52: {
53: return call_mem_get_func (get_mem_bank (addr).lget, addr);
54: }
55: __inline__ uae_u32 wordget (uaecptr addr)
56: {
57: return call_mem_get_func (get_mem_bank (addr).wget, addr);
58: }
59: __inline__ uae_u32 byteget (uaecptr addr)
60: {
61: return call_mem_get_func (get_mem_bank (addr).bget, addr);
62: }
63: __inline__ void longput (uaecptr addr, uae_u32 l)
64: {
65: call_mem_put_func (get_mem_bank (addr).lput, addr, l);
66: }
67: __inline__ void wordput (uaecptr addr, uae_u32 w)
68: {
69: call_mem_put_func (get_mem_bank (addr).wput, addr, w);
70: }
71: __inline__ void byteput (uaecptr addr, uae_u32 b)
72: {
73: call_mem_put_func (get_mem_bank (addr).bput, addr, b);
74: }
75: #endif
76:
77:
1.1.1.5 ! root 78: /* Some prototypes: */
! 79: static int STmem_check (uaecptr addr, uae_u32 size) REGPARAM;
! 80: static uae_u8 *STmem_xlate (uaecptr addr) REGPARAM;
! 81:
! 82:
1.1 root 83: /* A dummy bank that only contains zeros */
84:
85: static uae_u32 dummy_lget (uaecptr) REGPARAM;
86: static uae_u32 dummy_wget (uaecptr) REGPARAM;
87: static uae_u32 dummy_bget (uaecptr) REGPARAM;
88: static void dummy_lput (uaecptr, uae_u32) REGPARAM;
89: static void dummy_wput (uaecptr, uae_u32) REGPARAM;
90: static void dummy_bput (uaecptr, uae_u32) REGPARAM;
91: static int dummy_check (uaecptr addr, uae_u32 size) REGPARAM;
92:
93: uae_u32 REGPARAM2 dummy_lget (uaecptr addr)
94: {
95: if (illegal_mem)
1.1.1.3 root 96: write_log ("Illegal lget at %08lx\n", (long)addr);
1.1 root 97:
98: return 0;
99: }
100:
101: uae_u32 REGPARAM2 dummy_wget (uaecptr addr)
102: {
103: if (illegal_mem)
1.1.1.3 root 104: write_log ("Illegal wget at %08lx\n", (long)addr);
1.1 root 105:
106: return 0;
107: }
108:
109: uae_u32 REGPARAM2 dummy_bget (uaecptr addr)
110: {
111: if (illegal_mem)
1.1.1.3 root 112: write_log ("Illegal bget at %08lx\n", (long)addr);
1.1 root 113:
114: return 0;
115: }
116:
117: void REGPARAM2 dummy_lput (uaecptr addr, uae_u32 l)
118: {
119: if (illegal_mem)
1.1.1.3 root 120: write_log ("Illegal lput at %08lx\n", (long)addr);
1.1 root 121: }
1.1.1.5 ! root 122:
1.1 root 123: void REGPARAM2 dummy_wput (uaecptr addr, uae_u32 w)
124: {
125: if (illegal_mem)
1.1.1.3 root 126: write_log ("Illegal wput at %08lx\n", (long)addr);
1.1 root 127: }
1.1.1.5 ! root 128:
1.1 root 129: void REGPARAM2 dummy_bput (uaecptr addr, uae_u32 b)
130: {
131: if (illegal_mem)
1.1.1.3 root 132: write_log ("Illegal bput at %08lx\n", (long)addr);
1.1 root 133: }
134:
135: int REGPARAM2 dummy_check (uaecptr addr, uae_u32 size)
136: {
137: if (illegal_mem)
1.1.1.3 root 138: write_log ("Illegal check at %08lx\n", (long)addr);
1.1 root 139:
140: return 0;
141: }
142:
1.1.1.5 ! root 143: uae_u8 REGPARAM2 *dummy_xlate (uaecptr addr)
! 144: {
! 145: write_log("Your Atari program just did something terribly stupid:"
! 146: " dummy_xlate($%x)\n", addr);
! 147: /*Reset_Warm();*/
! 148: return STmem_xlate(addr); /* So we don't crash. */
! 149: }
1.1 root 150:
151:
1.1.1.5 ! root 152: /* **** This memory bank only generates bus errors **** */
1.1 root 153:
1.1.1.5 ! root 154: uae_u32 REGPARAM2 BusErrMem_lget(uaecptr addr)
! 155: {
! 156: if (illegal_mem)
! 157: write_log ("Bus error lget at %08lx\n", (long)addr);
! 158:
! 159: M68000_BusError(addr);
! 160: return 0;
! 161: }
! 162:
! 163: uae_u32 REGPARAM2 BusErrMem_wget(uaecptr addr)
! 164: {
! 165: if (illegal_mem)
! 166: write_log ("Bus error wget at %08lx\n", (long)addr);
! 167:
! 168: M68000_BusError(addr);
! 169: return 0;
! 170: }
! 171:
! 172: uae_u32 REGPARAM2 BusErrMem_bget(uaecptr addr)
! 173: {
! 174: if (illegal_mem)
! 175: write_log ("Bus error bget at %08lx\n", (long)addr);
! 176:
! 177: M68000_BusError(addr);
! 178: return 0;
! 179: }
! 180:
! 181: void REGPARAM2 BusErrMem_lput(uaecptr addr, uae_u32 l)
! 182: {
! 183: if (illegal_mem)
! 184: write_log ("Bus error lput at %08lx\n", (long)addr);
! 185:
! 186: M68000_BusError(addr);
! 187: }
! 188:
! 189: void REGPARAM2 BusErrMem_wput(uaecptr addr, uae_u32 w)
! 190: {
! 191: if (illegal_mem)
! 192: write_log ("Bus error wput at %08lx\n", (long)addr);
! 193:
! 194: M68000_BusError(addr);
! 195: }
! 196:
! 197: void REGPARAM2 BusErrMem_bput(uaecptr addr, uae_u32 b)
! 198: {
! 199: if (illegal_mem)
! 200: write_log ("Bus error bput at %08lx\n", (long)addr);
! 201:
! 202: M68000_BusError(addr);
! 203: }
! 204:
! 205: int REGPARAM2 BusErrMem_check(uaecptr addr, uae_u32 size)
! 206: {
! 207: if (illegal_mem)
! 208: write_log ("Bus error check at %08lx\n", (long)addr);
! 209:
! 210: return 0;
! 211: }
! 212:
! 213: uae_u8 REGPARAM2 *BusErrMem_xlate (uaecptr addr)
! 214: {
! 215: write_log("Your Atari program just did something terribly stupid:"
! 216: " BusErrMem_xlate($%x)\n", addr);
! 217:
! 218: /*M68000_BusError(addr);*/
! 219: return STmem_xlate(addr); /* So we don't crash. */
! 220: }
! 221:
! 222:
! 223: /* **** ST RAM memory **** */
! 224:
! 225: uae_u8 *STmemory;
1.1 root 226:
227: uae_u32 REGPARAM2 STmem_lget (uaecptr addr)
228: {
229: uae_u32 *m;
230:
231: addr -= STmem_start & STmem_mask;
232: addr &= STmem_mask;
233: m = (uae_u32 *)(STmemory + addr);
234: return do_get_mem_long (m);
235: }
236:
237: uae_u32 REGPARAM2 STmem_wget (uaecptr addr)
238: {
239: uae_u16 *m;
240:
241: addr -= STmem_start & STmem_mask;
242: addr &= STmem_mask;
243: m = (uae_u16 *)(STmemory + addr);
244: return do_get_mem_word (m);
245: }
246:
247: uae_u32 REGPARAM2 STmem_bget (uaecptr addr)
248: {
249: addr -= STmem_start & STmem_mask;
250: addr &= STmem_mask;
251: return STmemory[addr];
252: }
253:
254: void REGPARAM2 STmem_lput (uaecptr addr, uae_u32 l)
255: {
256: uae_u32 *m;
257:
258: addr -= STmem_start & STmem_mask;
259: addr &= STmem_mask;
260: m = (uae_u32 *)(STmemory + addr);
261: do_put_mem_long (m, l);
262: }
263:
264: void REGPARAM2 STmem_wput (uaecptr addr, uae_u32 w)
265: {
266: uae_u16 *m;
267:
268: addr -= STmem_start & STmem_mask;
269: addr &= STmem_mask;
270: m = (uae_u16 *)(STmemory + addr);
271: do_put_mem_word (m, w);
272: }
273:
274: void REGPARAM2 STmem_bput (uaecptr addr, uae_u32 b)
275: {
276: addr -= STmem_start & STmem_mask;
277: addr &= STmem_mask;
278: STmemory[addr] = b;
279: }
280:
281: int REGPARAM2 STmem_check (uaecptr addr, uae_u32 size)
282: {
283: addr -= STmem_start & STmem_mask;
284: addr &= STmem_mask;
1.1.1.5 ! root 285: return (addr + size) <= STmem_size;
1.1 root 286: }
287:
288: uae_u8 REGPARAM2 *STmem_xlate (uaecptr addr)
289: {
290: addr -= STmem_start & STmem_mask;
291: addr &= STmem_mask;
292: return STmemory + addr;
293: }
294:
295:
1.1.1.5 ! root 296: /*
! 297: * **** ST RAM system memory ****
! 298: * We need a separate mem bank for this region since the first 0x800 bytes on
! 299: * the ST can only be accessed in supervisor mode. Note that the very first
! 300: * 8 bytes of the ST memory are also a mirror of the TOS ROM, so they are write
! 301: * protected!
! 302: */
! 303: uae_u32 REGPARAM2 SysMem_lget(uaecptr addr)
! 304: {
! 305: uae_u32 *m;
! 306:
! 307: if(addr < 0x800 && !regs.s)
! 308: {
! 309: M68000_BusError(addr);
! 310: return 0;
! 311: }
! 312:
! 313: addr -= STmem_start & STmem_mask;
! 314: addr &= STmem_mask;
! 315: m = (uae_u32 *)(STmemory + addr);
! 316: return do_get_mem_long (m);
! 317: }
! 318:
! 319: uae_u32 REGPARAM2 SysMem_wget(uaecptr addr)
! 320: {
! 321: uae_u16 *m;
! 322:
! 323: if(addr < 0x800 && !regs.s)
! 324: {
! 325: M68000_BusError(addr);
! 326: return 0;
! 327: }
! 328:
! 329: addr -= STmem_start & STmem_mask;
! 330: addr &= STmem_mask;
! 331: m = (uae_u16 *)(STmemory + addr);
! 332: return do_get_mem_word (m);
! 333: }
! 334:
! 335: uae_u32 REGPARAM2 SysMem_bget(uaecptr addr)
! 336: {
! 337: if(addr < 0x800 && !regs.s)
! 338: {
! 339: M68000_BusError(addr);
! 340: return 0;
! 341: }
! 342:
! 343: addr -= STmem_start & STmem_mask;
! 344: addr &= STmem_mask;
! 345: return STmemory[addr];
! 346: }
! 347:
! 348: void REGPARAM2 SysMem_lput(uaecptr addr, uae_u32 l)
! 349: {
! 350: uae_u32 *m;
! 351:
! 352: if(addr < 0x8 || (addr < 0x800 && !regs.s))
! 353: {
! 354: M68000_BusError(addr);
! 355: return;
! 356: }
! 357:
! 358: addr -= STmem_start & STmem_mask;
! 359: addr &= STmem_mask;
! 360: m = (uae_u32 *)(STmemory + addr);
! 361: do_put_mem_long (m, l);
! 362: }
! 363:
! 364: void REGPARAM2 SysMem_wput(uaecptr addr, uae_u32 w)
! 365: {
! 366: uae_u16 *m;
! 367:
! 368: if(addr < 0x8 || (addr < 0x800 && !regs.s))
! 369: {
! 370: M68000_BusError(addr);
! 371: return;
! 372: }
! 373:
! 374: addr -= STmem_start & STmem_mask;
! 375: addr &= STmem_mask;
! 376: m = (uae_u16 *)(STmemory + addr);
! 377: do_put_mem_word (m, w);
! 378: }
! 379:
! 380: void REGPARAM2 SysMem_bput(uaecptr addr, uae_u32 b)
! 381: {
! 382: if(addr < 0x8 || (addr < 0x800 && !regs.s))
! 383: {
! 384: M68000_BusError(addr);
! 385: return;
! 386: }
! 387:
! 388: addr -= STmem_start & STmem_mask;
! 389: addr &= STmem_mask;
! 390: STmemory[addr] = b;
! 391: }
! 392:
! 393:
! 394: /*
! 395: * **** Void memory ****
! 396: * Between the ST-RAM end and the 4 MB barrier, there is a void memory space:
! 397: * Reading always returns the same value and writing does nothing at all.
! 398: */
! 399:
! 400: uae_u32 REGPARAM2 VoidMem_lget(uaecptr addr)
! 401: {
! 402: return 0;
! 403: }
! 404:
! 405: uae_u32 REGPARAM2 VoidMem_wget(uaecptr addr)
! 406: {
! 407: return 0;
! 408: }
! 409:
! 410: uae_u32 REGPARAM2 VoidMem_bget(uaecptr addr)
! 411: {
! 412: return 0;
! 413: }
! 414:
! 415: void REGPARAM2 VoidMem_lput(uaecptr addr, uae_u32 l)
! 416: {
! 417: }
! 418:
! 419: void REGPARAM2 VoidMem_wput(uaecptr addr, uae_u32 w)
! 420: {
! 421: }
! 422:
! 423: void REGPARAM2 VoidMem_bput (uaecptr addr, uae_u32 b)
! 424: {
! 425: }
! 426:
! 427: int REGPARAM2 VoidMem_check(uaecptr addr, uae_u32 size)
! 428: {
! 429: if (illegal_mem)
! 430: write_log ("Void memory check at %08lx\n", (long)addr);
! 431:
! 432: return 0;
! 433: }
! 434:
! 435: uae_u8 REGPARAM2 *VoidMem_xlate (uaecptr addr)
! 436: {
! 437: write_log("Your Atari program just did something terribly stupid:"
! 438: " VoidMem_xlate($%x)\n", addr);
! 439:
! 440: return STmem_xlate(addr); /* So we don't crash. */
! 441: }
! 442:
! 443:
! 444: /* **** TT fast memory (not yet supported) **** */
1.1 root 445:
446: static uae_u8 *TTmemory;
447:
448: static uae_u32 TTmem_lget (uaecptr) REGPARAM;
449: static uae_u32 TTmem_wget (uaecptr) REGPARAM;
450: static uae_u32 TTmem_bget (uaecptr) REGPARAM;
451: static void TTmem_lput (uaecptr, uae_u32) REGPARAM;
452: static void TTmem_wput (uaecptr, uae_u32) REGPARAM;
453: static void TTmem_bput (uaecptr, uae_u32) REGPARAM;
454: static int TTmem_check (uaecptr addr, uae_u32 size) REGPARAM;
455: static uae_u8 *TTmem_xlate (uaecptr addr) REGPARAM;
456:
457: uae_u32 REGPARAM2 TTmem_lget (uaecptr addr)
458: {
459: uae_u32 *m;
460: addr -= TTmem_start & TTmem_mask;
461: addr &= TTmem_mask;
462: m = (uae_u32 *)(TTmemory + addr);
463: return do_get_mem_long (m);
464: }
465:
466: uae_u32 REGPARAM2 TTmem_wget (uaecptr addr)
467: {
468: uae_u16 *m;
469: addr -= TTmem_start & TTmem_mask;
470: addr &= TTmem_mask;
471: m = (uae_u16 *)(TTmemory + addr);
472: return do_get_mem_word (m);
473: }
474:
475: uae_u32 REGPARAM2 TTmem_bget (uaecptr addr)
476: {
477: addr -= TTmem_start & TTmem_mask;
478: addr &= TTmem_mask;
479: return TTmemory[addr];
480: }
481:
482: void REGPARAM2 TTmem_lput (uaecptr addr, uae_u32 l)
483: {
484: uae_u32 *m;
485: addr -= TTmem_start & TTmem_mask;
486: addr &= TTmem_mask;
487: m = (uae_u32 *)(TTmemory + addr);
488: do_put_mem_long (m, l);
489: }
490:
491: void REGPARAM2 TTmem_wput (uaecptr addr, uae_u32 w)
492: {
493: uae_u16 *m;
494: addr -= TTmem_start & TTmem_mask;
495: addr &= TTmem_mask;
496: m = (uae_u16 *)(TTmemory + addr);
497: do_put_mem_word (m, w);
498: }
499:
500: void REGPARAM2 TTmem_bput (uaecptr addr, uae_u32 b)
501: {
502: addr -= TTmem_start & TTmem_mask;
503: addr &= TTmem_mask;
504: TTmemory[addr] = b;
505: }
506:
507: int REGPARAM2 TTmem_check (uaecptr addr, uae_u32 size)
508: {
509: addr -= TTmem_start & TTmem_mask;
510: addr &= TTmem_mask;
1.1.1.5 ! root 511: return (addr + size) <= TTmem_size;
1.1 root 512: }
513:
514: uae_u8 REGPARAM2 *TTmem_xlate(uaecptr addr)
515: {
516: addr -= TTmem_start & TTmem_mask;
517: addr &= TTmem_mask;
518: return TTmemory + addr;
519: }
520:
1.1.1.5 ! root 521:
! 522: /* **** ROM memory **** */
1.1 root 523:
524: uae_u8 *ROMmemory;
525:
526: static uae_u32 ROMmem_lget (uaecptr) REGPARAM;
527: static uae_u32 ROMmem_wget (uaecptr) REGPARAM;
528: static uae_u32 ROMmem_bget (uaecptr) REGPARAM;
529: static void ROMmem_lput (uaecptr, uae_u32) REGPARAM;
530: static void ROMmem_wput (uaecptr, uae_u32) REGPARAM;
531: static void ROMmem_bput (uaecptr, uae_u32) REGPARAM;
532: static int ROMmem_check (uaecptr addr, uae_u32 size) REGPARAM;
533: static uae_u8 *ROMmem_xlate (uaecptr addr) REGPARAM;
534:
535: uae_u32 REGPARAM2 ROMmem_lget (uaecptr addr)
536: {
537: uae_u32 *m;
538: addr -= ROMmem_start & ROMmem_mask;
539: addr &= ROMmem_mask;
540: m = (uae_u32 *)(ROMmemory + addr);
541: return do_get_mem_long (m);
542: }
543:
544: uae_u32 REGPARAM2 ROMmem_wget (uaecptr addr)
545: {
546: uae_u16 *m;
547: addr -= ROMmem_start & ROMmem_mask;
548: addr &= ROMmem_mask;
549: m = (uae_u16 *)(ROMmemory + addr);
550: return do_get_mem_word (m);
551: }
552:
553: uae_u32 REGPARAM2 ROMmem_bget (uaecptr addr)
554: {
555: addr -= ROMmem_start & ROMmem_mask;
556: addr &= ROMmem_mask;
557: return ROMmemory[addr];
558: }
559:
560: void REGPARAM2 ROMmem_lput (uaecptr addr, uae_u32 b)
561: {
562: if (illegal_mem)
1.1.1.3 root 563: write_log ("Illegal ROMmem lput at %08lx\n", (long)addr);
1.1.1.5 ! root 564:
! 565: M68000_BusError(addr);
1.1 root 566: }
567:
568: void REGPARAM2 ROMmem_wput (uaecptr addr, uae_u32 b)
569: {
570: if (illegal_mem)
1.1.1.3 root 571: write_log ("Illegal ROMmem wput at %08lx\n", (long)addr);
1.1.1.5 ! root 572:
! 573: M68000_BusError(addr);
1.1 root 574: }
575:
576: void REGPARAM2 ROMmem_bput (uaecptr addr, uae_u32 b)
577: {
578: if (illegal_mem)
1.1.1.5 ! root 579: write_log ("Illegal ROMmem bput at %08lx\n", (long)addr);
! 580:
! 581: M68000_BusError(addr);
1.1 root 582: }
583:
584: int REGPARAM2 ROMmem_check (uaecptr addr, uae_u32 size)
585: {
586: addr -= ROMmem_start & ROMmem_mask;
587: addr &= ROMmem_mask;
588: return (addr + size) <= ROMmem_size;
589: }
590:
591: uae_u8 REGPARAM2 *ROMmem_xlate (uaecptr addr)
592: {
593: addr -= ROMmem_start & ROMmem_mask;
594: addr &= ROMmem_mask;
595: return ROMmemory + addr;
596: }
597:
598:
599: /* Hardware IO memory */
600: /* see also intercept.c */
601:
602: uae_u8 *IOmemory;
603:
604: static int IOmem_check (uaecptr addr, uae_u32 size) REGPARAM;
605: static uae_u8 *IOmem_xlate (uaecptr addr) REGPARAM;
606:
607: int REGPARAM2 IOmem_check (uaecptr addr, uae_u32 size)
608: {
1.1.1.5 ! root 609: addr -= IOmem_start;
1.1 root 610: addr &= IOmem_mask;
611: return (addr + size) <= IOmem_size;
612: }
613:
614: uae_u8 REGPARAM2 *IOmem_xlate (uaecptr addr)
615: {
1.1.1.5 ! root 616: addr -= IOmem_start;
1.1 root 617: addr &= IOmem_mask;
618: return IOmemory + addr;
619: }
620:
621:
622:
1.1.1.5 ! root 623: /* **** Address banks **** */
1.1 root 624:
625: addrbank dummy_bank = {
626: dummy_lget, dummy_wget, dummy_bget,
627: dummy_lput, dummy_wput, dummy_bput,
1.1.1.5 ! root 628: dummy_xlate, dummy_check
! 629: };
! 630:
! 631: addrbank BusErrMem_bank = {
! 632: BusErrMem_lget, BusErrMem_wget, BusErrMem_bget,
! 633: BusErrMem_lput, BusErrMem_wput, BusErrMem_bput,
! 634: BusErrMem_xlate, BusErrMem_check
1.1 root 635: };
636:
637: addrbank STmem_bank = {
638: STmem_lget, STmem_wget, STmem_bget,
639: STmem_lput, STmem_wput, STmem_bput,
640: STmem_xlate, STmem_check
641: };
642:
1.1.1.5 ! root 643: addrbank SysMem_bank = {
! 644: SysMem_lget, SysMem_wget, SysMem_bget,
! 645: SysMem_lput, SysMem_wput, SysMem_bput,
! 646: STmem_xlate, STmem_check
! 647: };
! 648:
! 649: addrbank VoidMem_bank = {
! 650: VoidMem_lget, VoidMem_wget, VoidMem_bget,
! 651: VoidMem_lput, VoidMem_wput, VoidMem_bput,
! 652: VoidMem_xlate, VoidMem_check
! 653: };
! 654:
1.1 root 655: addrbank TTmem_bank = {
656: TTmem_lget, TTmem_wget, TTmem_bget,
657: TTmem_lput, TTmem_wput, TTmem_bput,
658: TTmem_xlate, TTmem_check
659: };
660:
661: addrbank ROMmem_bank = {
662: ROMmem_lget, ROMmem_wget, ROMmem_bget,
663: ROMmem_lput, ROMmem_wput, ROMmem_bput,
664: ROMmem_xlate, ROMmem_check
665: };
666:
667: addrbank IOmem_bank = {
668: Intercept_ReadLong, Intercept_ReadWord, Intercept_ReadByte,
669: Intercept_WriteLong, Intercept_WriteWord, Intercept_WriteByte,
670: IOmem_xlate, IOmem_check
671: };
672:
673:
674: char *address_space, *good_address_map;
675: int good_address_fd;
676:
1.1.1.5 ! root 677:
1.1 root 678: static void init_mem_banks (void)
679: {
680: int i;
681: for (i = 0; i < 65536; i++)
682: put_mem_bank (i<<16, &dummy_bank);
683: }
684:
685:
686: /*
1.1.1.5 ! root 687: * Initialize the memory banks
! 688: */
! 689: void memory_init(uae_u32 f_STMemSize, uae_u32 f_TTMemSize, uae_u32 f_RomMemStart)
! 690: {
! 691: STmem_size = (f_STMemSize + 65535) & 0xFFFF0000;
! 692: TTmem_size = (f_TTMemSize + 65535) & 0xFFFF0000;
! 693:
! 694: /*write_log("memory_init: STmem_size=$%x, TTmem_size=$%x, ROM-Start=$%x,\n",
! 695: STmem_size, TTmem_size, f_RomMemStart);*/
! 696:
! 697: STmemory = STRam;
! 698: ROMmemory = STRam + ROMmem_start;
! 699: IOmemory = STRam + IOmem_start;
! 700: /*
! 701: while (! STmemory && STmem_size > 512*1024) {
! 702: STmem_size >>= 1;
! 703: STmemory = (uae_u8 *)malloc (STmem_size);
1.1 root 704: if (STmemory)
1.1.1.5 ! root 705: fprintf (stderr, "Reducing STmem size to %dkb\n", STmem_size >> 10);
1.1 root 706: }
707: if (! STmemory) {
708: write_log ("virtual memory exhausted (STmemory)!\n");
709: abort ();
710: }
711: */
712:
1.1.1.5 ! root 713: init_mem_banks();
1.1 root 714:
1.1.1.5 ! root 715: /* Map the ST RAM: */
! 716: map_banks(&SysMem_bank, 0x00, 1);
! 717: map_banks(&VoidMem_bank, 0x08, 0x38); /* Between STRamEnd and 4MB barrier, there is void space! */
! 718: map_banks(&STmem_bank, 0x01, (STmem_size >> 16) - 1);
! 719:
! 720: /* TT memory isn't really supported yet */
! 721: if (TTmem_size > 0)
! 722: TTmemory = (uae_u8 *)malloc (TTmem_size);
1.1 root 723: if (TTmemory != 0)
1.1.1.5 ! root 724: map_banks (&TTmem_bank, TTmem_start >> 16, TTmem_size >> 16);
! 725: else
! 726: TTmem_size = 0;
! 727: TTmem_mask = TTmem_size - 1;
! 728:
! 729: /* ROM memory: */
! 730: /* Depending on which ROM version we are using, the other ROM region is illegal! */
! 731: if(f_RomMemStart == 0xFC0000)
! 732: {
! 733: map_banks(&ROMmem_bank, 0xFC0000 >> 16, 0x3);
! 734: map_banks(&BusErrMem_bank, 0xE00000 >> 16, 0x10);
! 735: }
! 736: else if(f_RomMemStart == 0xE00000)
! 737: {
! 738: map_banks(&ROMmem_bank, 0xE00000 >> 16, 0x10);
! 739: map_banks(&BusErrMem_bank, 0xFC0000 >> 16, 0x3);
! 740: }
1.1 root 741: else
1.1.1.5 ! root 742: {
! 743: write_log("Illegal ROM memory start!\n");
! 744: }
1.1 root 745:
1.1.1.5 ! root 746: /* Cartridge memory: */
! 747: map_banks(&ROMmem_bank, 0xFA0000 >> 16, 0x2);
1.1 root 748:
1.1.1.5 ! root 749: /* IO memory: */
! 750: map_banks(&IOmem_bank, IOmem_start>>16, 0x1);
1.1 root 751:
1.1.1.5 ! root 752: /* Illegal memory regions cause a bus error on the ST: */
! 753: map_banks(&BusErrMem_bank, 0x400000 >> 16, 0xA0); /* Space between 4MB barrier and TOS ROM */
! 754: map_banks(&BusErrMem_bank, 0xF00000 >> 16, 0xA); /* IDE controler on the Falcon */
1.1 root 755: }
756:
1.1.1.5 ! root 757:
! 758: /*
! 759: * Uninitialize the memory banks.
! 760: */
! 761: void memory_uninit (void)
! 762: {
! 763: /* Here, we free allocated memory from memory_init */
! 764: if(TTmem_size > 0)
! 765: {
! 766: free(TTmemory);
! 767: TTmemory = NULL;
! 768: }
! 769: }
! 770:
! 771:
1.1 root 772: void map_banks (addrbank *bank, int start, int size)
773: {
774: int bnr;
775: unsigned long int hioffs = 0, endhioffs = 0x100;
776:
777: if (start >= 0x100) {
778: for (bnr = start; bnr < start + size; bnr++)
779: put_mem_bank (bnr << 16, bank);
780: return;
781: }
782: /* Some ROMs apparently require a 24 bit address space... */
783: if (address_space_24)
784: endhioffs = 0x10000;
785: for (hioffs = 0; hioffs < endhioffs; hioffs += 0x100)
786: for (bnr = start; bnr < start+size; bnr++)
787: put_mem_bank ((bnr + hioffs) << 16, bank);
788: }
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