--- hatari/src/uae-cpu/newcpu.c 2019/04/01 07:09:30 1.1.1.2 +++ hatari/src/uae-cpu/newcpu.c 2019/04/01 07:14:57 1.1.1.13 @@ -7,25 +7,106 @@ * * Adaptation to Hatari by Thomas Huth * + * This file is distributed under the GNU Public License, version 2 or at + * your option any later version. Read the file gpl.txt for details. */ + +/* 2007/11/12 [NP] Add HATARI_TRACE_CPU_DISASM. */ +/* 2007/11/15 [NP] In MakeFromSR, writes to m and t0 should be ignored and set to 0 if cpu < 68020 */ +/* 2007/11/26 [NP] We set BusErrorPC in m68k_run_1 instead of M68000_BusError, else the BusErrorPC */ +/* will not point to the opcode that generated the bus error. */ +/* Huge debug/work on Exceptions 2/3 stack frames, result is more accurate and */ +/* allow to pass the very tricky Transbeauce 2 Demo's protection. */ +/* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */ +/* Cwik, pasti@fxatari.com). */ +/* 2007/12/06 [NP] The PC stored in the stack frame for the bus error is complex to emulate, */ +/* because it doesn't necessarily point to the next instruction after the one that */ +/* triggered the bus error. In the case of the Transbeauce 2 Demo, after */ +/* 'move.l $0.w,$24.w', PC is incremented of 4 bytes, not 6, and stored in the */ +/* stack. Special case to decrement PC of 2 bytes if opcode is '21f8'. */ +/* This should be fixed with a real model. */ +/* 2007/12/07 [NP] If Trace is enabled and a group 2 exception occurs (such as CHK), the trace */ +/* handler should be called after the group 2's handler. If a bus error, address */ +/* error or illegal occurs while Trace is enabled, the trace handler should not be */ +/* called after this instruction (Transbeauce 2 Demo, Phaleon Demo). */ +/* This means that if a CHK is executed while trace bit was set, we must set PC */ +/* to CHK handler, turn trace off in the internal SR, but we must still call the */ +/* trace handler one last time with the PC set to the CHK's handler (even if */ +/* trace mode is internally turned off while processing an exception). Once trace */ +/* handler is finished (RTE), we return to the CHK's handler. */ +/* This is true for DIV BY 0, CHK, TRAPV and TRAP. */ +/* Backport exception_trace() from WinUAE to handle this behaviour (used in */ +/* Transbeauce 2 demo). */ +/* 2007/12/09 [NP] 'dc.w $a' should not be used to call 'OpCode_SysInit' but should give an illegal*/ +/* instruction (Transbeauce 2 demo). */ +/* Instead of always replacing the illegal instructions $8, $a and $c by the */ +/* 3 functions required for HD emulation, we now do it in cart.c only if the */ +/* built-in cartridge image is loaded. */ +/* YEAH! Hatari is now the first emulator to pass the Transbeauce 2 protection :) */ +/* 2007/12/18 [NP] More precise timings for HBL, VBL and MFP interrupts. On ST, these interrupts */ +/* are taking 56 cycles instead of the 44 cycles in the 68000's documentation. */ +/* 2007/12/24 [NP] If an interrupt (HBL, VBL) is pending after intruction 'n' was processed, the */ +/* exception should be called before instr. 'n+1' is processed, not after (else the*/ +/* interrupt's handler is delayed by one 68000's instruction, which could break */ +/* some demos with too strict timings) (ACF's Demo Main Menu). */ +/* We call the interrupt if ( SPCFLAG_INT | SPCFLAG_DOINT ) is set, not only if */ +/* SPCFLAG_DOINT is set (as it was already the case when handling 'STOP'). */ +/* 2007/12/25 [NP] FIXME When handling exceptions' cycles, using nr >= 64 to determine if this is */ +/* an MFP exception could be wrong if the MFP VR was set to another value than the */ +/* default $40 (this could be a problem with programs requiring a precise cycles */ +/* calculation while changing VR, but no such programs were encountered so far). */ +/* -> FIXED, see 2008/10/05 */ +/* 2008/04/17 [NP] In m68k_run_1/m68k_run_2, add the wait state cycles before testing if content */ +/* of PendingInterruptCount is <= 0 (else the int could happen a few cycles earlier*/ +/* than expected in some rare cases (reading $fffa21 in BIG Demo Screen 1)). */ +/* 2008/09/14 [NP] Add the value of the new PC in the exception's log. */ +/* 2008/09/14 [NP] Correct cycles for TRAP are 34 not 38 (4 more cycles were counted because cpuemu*/ +/* returns 4 and Exception() adds 34) (Phaleon / Illusion Demo by Next). */ +/* FIXME : Others exception cycles may be wrong too. */ +/* 2008/10/05 [NP] Add a parameter 'ExceptionSource' to Exception(). This allows to know the source*/ +/* of the exception (video, mfp, cpu) and properly handle MFP interrupts. Since */ +/* it's possible to change the vector base in $fffa17, MFP int vectors can overlap */ +/* the 'normal' 68000 ones and the exception number is not enough to decide. */ +/* We need ExceptionSource to remove the ambiguity. */ +/* Fix High Fidelity Dreams by Aura which sets MFP vector base to $c0 instead of */ +/* $100. In that case, timer B int becomes exception nr 56 and conflicts with the */ +/* 'MMU config error' exception, which takes 4 cycles instead of 56 cycles for MFP.*/ +/* 2008/11/18 [NP] In 'do_specialties()', when the cpu is in the STOP state, we must test all */ +/* possible int handlers while PendingInterruptCount <= 0 without increasing the */ +/* cpu cycle counter. In the case where both an MFP int and an HBL occur at the */ +/* same time for example, the HBL was delayed by 4 bytes if no MFP exception */ +/* was triggered, which was wrong (this happened mainly with the TOS timer D that */ +/* expires very often). Such precision is required for very recent hardscroll */ +/* techniques that use 'stop' to stay in sync with the video shifter. */ + + + +const char NewCpu_rcsid[] = "Hatari $Id: newcpu.c,v 1.1.1.13 2019/04/01 07:14:57 root Exp $"; + #include "sysdeps.h" #include "hatari-glue.h" #include "maccess.h" #include "memory.h" #include "newcpu.h" -#include "compiler.h" -#include "events.h" +#include "../includes/main.h" +#include "../includes/log.h" +#include "../includes/m68000.h" +#include "../includes/int.h" +#include "../includes/mfp.h" #include "../includes/tos.h" +#include "../includes/vdi.h" +#include "../includes/cart.h" +#include "../includes/debugui.h" +#include "../includes/bios.h" +#include "../includes/xbios.h" +#include "../includes/video.h" +#include "../includes/options.h" -/*int crashtrace=0;*/ +//#define DEBUG_PREFETCH -int quit_program = 0; -int debugging = 0; struct flag_struct regflags; -int lastInstructionCycles; /* how many cycles last instruction took to execute */ - /* Opcode of faulting instruction */ uae_u16 last_op_for_exception_3; /* PC at fault time */ @@ -33,8 +114,8 @@ uaecptr last_addr_for_exception_3; /* Address that generated the exception */ uaecptr last_fault_for_exception_3; -int areg_byteinc[] = { 1,1,1,1,1,1,1,2 }; -int imm8_table[] = { 8,1,2,3,4,5,6,7 }; +const int areg_byteinc[] = { 1,1,1,1,1,1,1,2 }; +const int imm8_table[] = { 8,1,2,3,4,5,6,7 }; int movem_index1[256]; int movem_index2[256]; @@ -46,6 +127,8 @@ int fpp_movem_next[256]; cpuop_func *cpufunctbl[65536]; +int OpcodeFamily; + #define COUNT_INSTRS 0 #if COUNT_INSTRS @@ -98,87 +181,57 @@ void dump_counts (void) } #endif -int broken_in; - -static __inline__ unsigned int cft_map (unsigned int f) -{ -#ifndef HAVE_GET_WORD_UNSWAPPED - return f; -#else - return ((f >> 8) & 255) | ((f & 255) << 8); -#endif -} static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM; static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode) { - op_illg (cft_map (opcode)); + op_illg (opcode); return 4; } -static void build_cpufunctbl (void) + +void build_cpufunctbl(void) { int i; unsigned long opcode; - struct cputbl *tbl = (cpu_level == 4 ? op_smalltbl_0_ff - : cpu_level == 3 ? op_smalltbl_1_ff - : cpu_level == 2 ? op_smalltbl_2_ff - : cpu_level == 1 ? op_smalltbl_3_ff - : ! cpu_compatible ? op_smalltbl_4_ff - : op_smalltbl_5_ff); + const struct cputbl *tbl = (currprefs.cpu_level == 4 ? op_smalltbl_0_ff + : currprefs.cpu_level == 3 ? op_smalltbl_1_ff + : currprefs.cpu_level == 2 ? op_smalltbl_2_ff + : currprefs.cpu_level == 1 ? op_smalltbl_3_ff + : ! currprefs.cpu_compatible ? op_smalltbl_4_ff + : op_smalltbl_5_ff); - write_log ("Building CPU function table (%d %d %d).\n", - cpu_level, cpu_compatible, address_space_24); + Log_Printf(LOG_DEBUG, "Building CPU function table (%d %d %d).\n", + currprefs.cpu_level, currprefs.cpu_compatible, currprefs.address_space_24); for (opcode = 0; opcode < 65536; opcode++) - cpufunctbl[cft_map(opcode)] = op_illg_1; + cpufunctbl[opcode] = op_illg_1; for (i = 0; tbl[i].handler != NULL; i++) { if (! tbl[i].specific) - cpufunctbl[cft_map (tbl[i].opcode)] = tbl[i].handler; + cpufunctbl[tbl[i].opcode] = tbl[i].handler; } for (opcode = 0; opcode < 65536; opcode++) { cpuop_func *f; - if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level) + if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > currprefs.cpu_level) continue; if (table68k[opcode].handler != -1) { - f = cpufunctbl[cft_map (table68k[opcode].handler)]; + f = cpufunctbl[table68k[opcode].handler]; if (f == op_illg_1) abort(); - cpufunctbl[cft_map(opcode)] = f; + cpufunctbl[opcode] = f; } } for (i = 0; tbl[i].handler != NULL; i++) { if (tbl[i].specific) - cpufunctbl[cft_map(tbl[i].opcode)] = tbl[i].handler; + cpufunctbl[tbl[i].opcode] = tbl[i].handler; } - - /* Hataris illegal opcodes: */ - cpufunctbl[cft_map(CONDRV_OPCODE)] = OpCode_ConnectedDrive; - cpufunctbl[cft_map(TIMERD_OPCODE)] = OpCode_TimerD; } -/* -void check_prefs_changed_cpu (void) -{ - if (currprefs.cpu_level != changed_prefs.cpu_level - || currprefs.cpu_compatible != changed_prefs.cpu_compatible) { - currprefs.cpu_level = changed_prefs.cpu_level; - currprefs.cpu_compatible = changed_prefs.cpu_compatible; - build_cpufunctbl (); - } - if (currprefs.m68k_speed != changed_prefs.m68k_speed) { - currprefs.m68k_speed = changed_prefs.m68k_speed; - reset_frame_rate_hack (); - update_68k_cycles (); - } -} -*/ - void init_m68k (void) { int i; @@ -218,9 +271,9 @@ void init_m68k (void) } #endif write_log ("Building CPU table for configuration: 68"); - if (address_space_24 && cpu_level > 1) + if (currprefs.address_space_24 && currprefs.cpu_level > 1) write_log ("EC"); - switch (cpu_level) { + switch (currprefs.cpu_level) { case 1: write_log ("010"); break; @@ -238,23 +291,28 @@ void init_m68k (void) write_log ("000"); break; } - if (cpu_compatible) + if (currprefs.cpu_compatible) write_log (" (compatible mode)"); write_log ("\n"); - + read_table68k (); do_merges (); - write_log ("%d CPU functions\n", nr_cpuop_funcs); + Log_Printf(LOG_DEBUG, "%d CPU functions\n", nr_cpuop_funcs); build_cpufunctbl (); } -struct regstruct regs, lastint_regs; + +/* not used ATM: static struct regstruct regs_backup[16]; static int backup_pointer = 0; -static long int m68kpc_offset; +struct regstruct lastint_regs; int lastint_no; +*/ +struct regstruct regs; +static long int m68kpc_offset; + #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1) #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o)) @@ -323,8 +381,7 @@ uae_s32 ShowEA (FILE *f, int reg, amodes sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name, dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3), - disp,outer, - (unsigned long)addr); + (long)disp, (long)outer, (unsigned long)addr); } else { addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg; sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg, @@ -370,8 +427,7 @@ uae_s32 ShowEA (FILE *f, int reg, amodes sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name, dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3), - disp,outer, - (unsigned long)addr); + (long)disp, (long)outer, (unsigned long)addr); } else { addr += (uae_s32)((uae_s8)disp8) + dispreg; sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D', @@ -434,9 +490,11 @@ uae_s32 ShowEA (FILE *f, int reg, amodes return offset; } + /* The plan is that this will take over the job of exception 3 handling - * the CPU emulation functions will just do a longjmp to m68k_go whenever * they hit an odd address. */ +#if 0 static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val) { uae_u16 dp; @@ -445,7 +503,7 @@ static int verify_ea (int reg, amodes mo int r; uae_u32 dispreg; uaecptr addr; - uae_s32 offset = 0; + /*uae_s32 offset = 0;*/ switch (mode){ case Dreg: @@ -557,6 +615,8 @@ static int verify_ea (int reg, amodes mo last_fault_for_exception_3 = addr; return 0; } +#endif + uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp) { @@ -610,6 +670,8 @@ uae_u32 get_disp_ea_000 (uae_u32 base, u #endif } + +/* Create the Status Register from the flags */ void MakeSR (void) { #if 0 @@ -629,6 +691,8 @@ void MakeSR (void) | GET_CFLG); } + +/* Set up the flags from Status Register */ void MakeFromSR (void) { int oldm = regs.m; @@ -644,7 +708,7 @@ void MakeFromSR (void) SET_ZFLG ((regs.sr >> 2) & 1); SET_VFLG ((regs.sr >> 1) & 1); SET_CFLG (regs.sr & 1); - if (cpu_level >= 2) { + if (currprefs.cpu_level >= 2) { if (olds != regs.s) { if (olds) { if (oldm) @@ -666,6 +730,10 @@ void MakeFromSR (void) } } } else { + /* [NP] If cpu < 68020, m and t0 are ignored and should be set to 0 */ + regs.t0 = 0; + regs.m = 0; + if (olds != regs.s) { if (olds) { regs.isp = m68k_areg(regs, 7); @@ -677,32 +745,91 @@ void MakeFromSR (void) } } - set_special (SPCFLAG_INT); + /* Pending interrupts can occur again after a write to the SR: */ + set_special (SPCFLAG_DOINT); if (regs.t1 || regs.t0) set_special (SPCFLAG_TRACE); else - unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE); + /* Keep SPCFLAG_DOTRACE, we still want a trace exception for + SR-modifying instructions (including STOP). */ + unset_special (SPCFLAG_TRACE); +} + + +static void exception_trace (int nr) +{ + unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE); + if (regs.t1 && !regs.t0) { + /* trace stays pending if exception is div by zero, chk, + * trapv or trap #x + */ + if (nr == 5 || nr == 6 || nr == 7 || (nr >= 32 && nr <= 47)) + set_special (SPCFLAG_DOTRACE); + } + regs.t1 = regs.t0 = regs.m = 0; } -void Exception(int nr, uaecptr oldpc) + +/* Handle exceptions. We need a special case to handle MFP exceptions */ +/* on Atari ST, because it's possible to change the MFP's vector base */ +/* and get a conflict with 'normal' cpu exceptions. */ +void Exception(int nr, uaecptr oldpc, int ExceptionSource) { uae_u32 currpc = m68k_getpc (); /*if( nr>=2 && nr<10 ) fprintf(stderr,"Exception (-> %i bombs)!\n",nr);*/ - compiler_flush_jsr_stack(); + /* Intercept VDI exception (Trap #2 with D0 = 0x73) */ + if ( ExceptionSource != M68000_EXCEPTION_SRC_INT_MFP ) + { + if(bUseVDIRes && nr == 0x22 && regs.regs[0] == 0x73) + { + if(!VDI()) + { + /* Set 'PC' as address of 'VDI_OPCODE' illegal instruction + * This will call OpCode_VDI after completion of Trap call! + * Use to modify return structure from VDI */ + VDI_OldPC = currpc; + currpc = CART_VDI_OPCODE_ADDR; + } + } + + if (bBiosIntercept) + { + /* Intercept BIOS or XBIOS trap (Trap #13 or #14) */ + if (nr == 0x2d) + { + /* Intercept BIOS calls */ + if (Bios()) return; + } + else if (nr == 0x2e) + { + /* Intercept XBIOS calls */ + if (XBios()) return; + } + } + } + MakeSR(); + /* Change to supervisor mode if necessary */ if (!regs.s) { regs.usp = m68k_areg(regs, 7); - if (cpu_level >= 2) + if (currprefs.cpu_level >= 2) m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp; else m68k_areg(regs, 7) = regs.isp; regs.s = 1; } - if (cpu_level > 0) { - if (nr == 2 || nr == 3) { + + /* Build additional exception stack frame for 68010 and higher */ + /* (special case for MFP) */ + if (currprefs.cpu_level > 0) { + if (ExceptionSource == M68000_EXCEPTION_SRC_INT_MFP) { + m68k_areg(regs, 7) -= 2; + put_word (m68k_areg(regs, 7), nr * 4); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */ + } + else if (nr == 2 || nr == 3) { int i; /* @@@ this is probably wrong (?) */ for (i = 0 ; i < 12 ; i++) { @@ -732,70 +859,186 @@ void Exception(int nr, uaecptr oldpc) m68k_areg(regs, 7) -= 2; put_word (m68k_areg(regs, 7), nr * 4); } - } else { - if (nr == 2 || nr == 3) { - /*crashtrace=4;*/ - /*sleep(1);*/ - m68k_areg(regs, 7) -= 12; - /* ??????? */ - if (nr == 3) { - put_long (m68k_areg(regs, 7), last_fault_for_exception_3); - put_word (m68k_areg(regs, 7)+4, last_op_for_exception_3); - put_long (m68k_areg(regs, 7)+8, last_addr_for_exception_3); - } - /*write_log ("UAE CPU Exception.\n");*/ - goto kludge_me_do; - } } + + /* Push PC on stack: */ m68k_areg(regs, 7) -= 4; put_long (m68k_areg(regs, 7), currpc); -kludge_me_do: + /* Push SR on stack: */ m68k_areg(regs, 7) -= 2; put_word (m68k_areg(regs, 7), regs.sr); + + HATARI_TRACE ( HATARI_TRACE_CPU_EXCEPTION , "cpu exception %d currpc %x buspc %x newpc %x fault_e3 %x op_e3 %hx addr_e3 %x\n" , + nr, currpc, BusErrorPC, get_long (regs.vbr + 4*nr), last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3 ); + + /* 68000 bus/address errors: */ + if (currprefs.cpu_level==0 && (nr==2 || nr==3) && (ExceptionSource != M68000_EXCEPTION_SRC_INT_MFP) ) { + uae_u16 specialstatus = 1; + + /* Special status word emulation isn't perfect yet... :-( */ + if (regs.sr & 0x2000) + specialstatus |= 0x4; + m68k_areg(regs, 7) -= 8; + if (nr == 3) { /* Address error */ + specialstatus |= ( last_op_for_exception_3 & (~0x1f) ); /* [NP] unused bits of specialstatus are those of the last opcode ! */ + put_word (m68k_areg(regs, 7), specialstatus); + put_long (m68k_areg(regs, 7)+2, last_fault_for_exception_3); + put_word (m68k_areg(regs, 7)+6, last_op_for_exception_3); + put_long (m68k_areg(regs, 7)+10, last_addr_for_exception_3); + if (bEnableDebug) { + fprintf(stderr,"Address Error at address $%x, PC=$%x\n",last_fault_for_exception_3,currpc); + DebugUI(); + } + } + else { /* Bus error */ + specialstatus |= ( get_word(BusErrorPC) & (~0x1f) ); /* [NP] unused bits of special status are those of the last opcode ! */ + if (bBusErrorReadWrite) + specialstatus |= 0x10; + put_word (m68k_areg(regs, 7), specialstatus); + put_long (m68k_areg(regs, 7)+2, BusErrorAddress); + put_word (m68k_areg(regs, 7)+6, get_word(BusErrorPC)); /* Opcode */ + + /* [NP] PC stored in the stack frame is not necessarily pointing to the next instruction ! */ + /* FIXME : we should have a proper model for this, in the meantime we handle specific cases */ + if ( get_word(BusErrorPC) == 0x21f8 ) /* move.l $0.w,$24.w (Transbeauce 2 loader) */ + put_long (m68k_areg(regs, 7)+10, currpc-2); /* correct PC is 2 bytes less than usual value */ + /* Check for double bus errors: */ + if (regs.spcflags & SPCFLAG_BUSERROR) { + fprintf(stderr, "Detected double bus error at address $%x, PC=$%lx => CPU halted!\n", + BusErrorAddress, (long)currpc); + unset_special(SPCFLAG_BUSERROR); + if (bEnableDebug) + DebugUI(); + regs.intmask = 7; + m68k_setstopped(TRUE); + return; + } + if (bEnableDebug && BusErrorAddress!=0xff8a00) { + fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n", BusErrorAddress, (long)currpc); + DebugUI(); + } + } + } + + /* Set PC and flags */ + if (bEnableDebug && get_long (regs.vbr + 4*nr) == 0) { + write_log("Uninitialized exception handler #%i!\n", nr); + DebugUI(); + } m68k_setpc (get_long (regs.vbr + 4*nr)); fill_prefetch_0 (); - regs.t1 = regs.t0 = regs.m = 0; - unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE); + /* Handle trace flags depending on current state */ + exception_trace (nr); + + /* Handle exception cycles (special case for MFP) */ + if ( ExceptionSource == M68000_EXCEPTION_SRC_INT_MFP ) + { + M68000_AddCycles(44+12); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */ + } + else if (nr >= 24 && nr <= 31) + { + if ( ( nr == 26 ) || ( nr == 28 ) ) /* HBL or VBL */ + M68000_AddCycles(44+12); /* Video Interrupt */ + else + M68000_AddCycles(44+4); /* Other Interrupts */ + } + else if(nr >= 32 && nr <= 47) + { + M68000_AddCycles(34-4); /* Trap (total is 34, but cpuemu.c already adds 4) */ + } + else switch(nr) + { + case 2: M68000_AddCycles(50); break; /* Bus error */ + case 3: M68000_AddCycles(50); break; /* Address error */ + case 4: M68000_AddCycles(34); break; /* Illegal instruction */ + case 5: M68000_AddCycles(38); break; /* Div by zero */ + case 6: M68000_AddCycles(40); break; /* CHK */ + case 7: M68000_AddCycles(34); break; /* TRAPV */ + case 8: M68000_AddCycles(34); break; /* Privilege violation */ + case 9: M68000_AddCycles(34); break; /* Trace */ + case 10: M68000_AddCycles(34); break; /* Line-A - probably wrong */ + case 11: M68000_AddCycles(34); break; /* Line-F - probably wrong */ + default: + /* FIXME: Add right cycles value for MFP interrupts and copro exceptions ... */ + if(nr < 64) + M68000_AddCycles(4); /* Coprocessor and unassigned exceptions (???) */ + else + M68000_AddCycles(44+12); /* Must be a MFP interrupt, should be processed above */ + break; + } } + static void Interrupt(int nr) { assert(nr < 8 && nr >= 0); - lastint_regs = regs; - lastint_no = nr; - Exception(nr+24, 0); + /*lastint_regs = regs;*/ + /*lastint_no = nr;*/ + + /* [NP] On Hatari, only video ints are using SPCFLAG_INT (see m68000.c) */ + /* TODO : to be really precise, we should use a global variable to store the last ExceptionSource */ + /* passed to M68000_Exception, instead of hardcoding M68000_EXCEPTION_SRC_INT_VIDEO here */ + Exception(nr+24, 0, M68000_EXCEPTION_SRC_INT_VIDEO); regs.intmask = nr; set_special (SPCFLAG_INT); } -static uae_u32 caar, cacr, itt0, itt1, dtt0, dtt1, tc, mmusr; + +uae_u32 caar, cacr; +static uae_u32 itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp; + + +static int movec_illg (int regno) +{ + int regno2 = regno & 0x7ff; + if (currprefs.cpu_level == 1) { /* 68010 */ + if (regno2 < 2) + return 0; + return 1; + } + if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) { /* 68020 */ + if (regno == 3) return 1; /* 68040 only */ + /* 4 is >=68040, but 0x804 is in 68020 */ + if (regno2 < 4 || regno == 0x804) + return 0; + return 1; + } + if (currprefs.cpu_level >= 4) { /* 68040 */ + if (regno == 0x802) return 1; /* 68020 only */ + if (regno2 < 8) return 0; + if (currprefs.cpu_level == 6 && regno2 == 8) /* 68060 only */ + return 0; + return 1; + } + return 1; +} int m68k_move2c (int regno, uae_u32 *regp) { - if ((cpu_level == 1 && (regno & 0x7FF) > 1) - || (cpu_level < 4 && (regno & 0x7FF) > 2) - || (cpu_level == 4 && regno == 0x802)) - { + if (movec_illg (regno)) { op_illg (0x4E7B); return 0; } else { switch (regno) { case 0: regs.sfc = *regp & 7; break; case 1: regs.dfc = *regp & 7; break; - case 2: cacr = *regp & (cpu_level < 4 ? 0x3 : 0x80008000); break; + case 2: cacr = *regp & (currprefs.cpu_level < 4 ? 0x3 : 0x80008000); break; case 3: tc = *regp & 0xc000; break; /* Mask out fields that should be zero. */ case 4: itt0 = *regp & 0xffffe364; break; case 5: itt1 = *regp & 0xffffe364; break; case 6: dtt0 = *regp & 0xffffe364; break; case 7: dtt1 = *regp & 0xffffe364; break; - + case 0x800: regs.usp = *regp; break; case 0x801: regs.vbr = *regp; break; case 0x802: caar = *regp & 0xfc; break; case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break; case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break; + case 0x805: mmusr = *regp; break; + case 0x806: urp = *regp; break; + case 0x807: srp = *regp; break; default: op_illg (0x4E7B); return 0; @@ -806,10 +1049,7 @@ int m68k_move2c (int regno, uae_u32 *reg int m68k_movec2 (int regno, uae_u32 *regp) { - if ((cpu_level == 1 && (regno & 0x7FF) > 1) - || (cpu_level < 4 && (regno & 0x7FF) > 2) - || (cpu_level == 4 && regno == 0x802)) - { + if (movec_illg (regno)) { op_illg (0x4E7A); return 0; } else { @@ -828,6 +1068,8 @@ int m68k_movec2 (int regno, uae_u32 *reg case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break; case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break; case 0x805: *regp = mmusr; break; + case 0x806: *regp = urp; break; + case 0x807: *regp = srp; break; default: op_illg (0x4E7A); return 0; @@ -837,12 +1079,12 @@ int m68k_movec2 (int regno, uae_u32 *reg } STATIC_INLINE int -div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 div, uae_u32 *quot, uae_u32 *rem) +div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 ndiv, uae_u32 *quot, uae_u32 *rem) { uae_u32 q = 0, cbit = 0; int i; - if (div <= src_hi) { + if (ndiv <= src_hi) { return 1; } for (i = 0 ; i < 32 ; i++) { @@ -851,9 +1093,9 @@ div_unsigned(uae_u32 src_hi, uae_u32 src if (src_lo & 0x80000000ul) src_hi++; src_lo <<= 1; q = q << 1; - if (cbit || div <= src_hi) { + if (cbit || ndiv <= src_hi) { q |= 1; - src_hi -= div; + src_hi -= ndiv; } } *quot = q; @@ -865,7 +1107,7 @@ void m68k_divl (uae_u32 opcode, uae_u32 { #if defined(uae_s64) if (src == 0) { - Exception (5, oldpc); + Exception (5, oldpc,M68000_EXCEPTION_SRC_CPU); return; } if (extra & 0x800) { @@ -920,7 +1162,7 @@ void m68k_divl (uae_u32 opcode, uae_u32 } #else if (src == 0) { - Exception (5, oldpc); + Exception (5, oldpc,M68000_EXCEPTION_SRC_CPU); return; } if (extra & 0x800) { @@ -1087,15 +1329,10 @@ void m68k_mull (uae_u32 opcode, uae_u32 } #endif } -static char* ccnames[] = -{ "T ","F ","HI","LS","CC","CS","NE","EQ", - "VC","VS","PL","MI","GE","LT","GT","LE" }; + void m68k_reset (void) { - m68k_areg (regs, 7) = get_long (ROMmem_start); - m68k_setpc (get_long (ROMmem_start+4)); - fill_prefetch_0 (); regs.s = 1; regs.m = 0; regs.stopped = 0; @@ -1106,80 +1343,38 @@ void m68k_reset (void) SET_CFLG (0); SET_VFLG (0); SET_NFLG (0); - regs.spcflags = 0; + regs.spcflags &= SPCFLAG_MODE_CHANGE; /* Clear specialflags except mode-change */ regs.intmask = 7; regs.vbr = regs.sfc = regs.dfc = 0; regs.fpcr = regs.fpsr = regs.fpiar = 0; + + m68k_areg(regs, 7) = get_long(0); + m68k_setpc(get_long(4)); + refill_prefetch (m68k_getpc(), 0); } + unsigned long REGPARAM2 op_illg (uae_u32 opcode) { +#if 0 uaecptr pc = m68k_getpc (); -/* - if (cloanto_rom && (opcode & 0xF100) == 0x7100) { - m68k_dreg (regs, (opcode >> 9) & 7) = (uae_s8)(opcode & 0xFF); - m68k_incpc (2); - fill_prefetch_0 (); +#endif + if ((opcode & 0xF000) == 0xF000) { + Exception(0xB,0,M68000_EXCEPTION_SRC_CPU); return 4; } -*/ - compiler_flush_jsr_stack (); - if (opcode == 0x4E7B && get_long (0x10) == 0 ) - { - write_log ("This program requires a 68020 CPU!\n"); - broken_in = 1; - set_special (SPCFLAG_BRK); - quit_program = 1; - } -/* - if (opcode == 0xFF0D) { - if ((pc & 0xF80000) == 0xF80000) { - // This is from the dummy Kickstart replacement - uae_u16 arg = get_iword (2); - m68k_incpc (4); - ersatz_perform (arg); - fill_prefetch_0 (); - return 4; - } else if ((pc & 0xF80000) == 0xF00000) { - // User-mode STOP replacement - m68k_setstopped (1); - return 4; - } - } -*/ -/* - if ((opcode & 0xF000) == 0xA000 && (pc & 0xF80000) == 0xF00000) { - // Calltrap. - m68k_incpc(2); - call_calltrap (opcode & 0xFFF); - fill_prefetch_0 (); + if ((opcode & 0xF000) == 0xA000) { + Exception(0xA,0,M68000_EXCEPTION_SRC_CPU); return 4; } -*/ - if ((opcode & 0xF000) == 0xF000) - { - Exception(0xB,0); - return 4; - } - if ((opcode & 0xF000) == 0xA000) - { -/* - if ((pc & 0xF80000) == 0xF00000) { - // Calltrap. - call_calltrap (opcode & 0xFFF); - } -*/ - Exception(0xA,0); - return 4; - } - -#if 1 - write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc); +#if 0 + write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc); #endif - Exception (4,0); + Exception (4,0,M68000_EXCEPTION_SRC_CPU); return 4; } + void mmu_op(uae_u32 opcode, uae_u16 extra) { if ((opcode & 0xFE0) == 0x0500) { @@ -1198,7 +1393,7 @@ static uaecptr last_trace_ad = 0; static void do_trace (void) { - if (regs.t0 && cpu_level >= 2) { + if (regs.t0 && currprefs.cpu_level >= 2) { uae_u16 opcode; /* should also include TRAP, CHK, SR modification FPcc */ /* probably never used so why bother */ @@ -1232,32 +1427,71 @@ static void do_trace (void) } +/* + * Handle special flags + */ static int do_specialties (void) { - run_compiled_code(); + if(regs.spcflags & SPCFLAG_BUSERROR) { + /* We can not execute bus errors directly in the memory handler + * functions since the PC should point to the address of the next + * instruction, so we're executing the bus errors here: */ + unset_special(SPCFLAG_BUSERROR); + Exception(2,0,M68000_EXCEPTION_SRC_CPU); + } + + if(regs.spcflags & SPCFLAG_EXTRA_CYCLES) { + /* Add some extra cycles to simulate a wait state */ + unset_special(SPCFLAG_EXTRA_CYCLES); + M68000_AddCycles(nWaitStateCycles); + nWaitStateCycles = 0; + } + if (regs.spcflags & SPCFLAG_DOTRACE) { - Exception (9,last_trace_ad); + Exception (9,last_trace_ad,M68000_EXCEPTION_SRC_CPU); } + while (regs.spcflags & SPCFLAG_STOP) { - do_cycles (4); - /*if (regs.spcflags & SPCFLAG_COPPER) - do_copper ();*/ - if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)){ - int intr = intlev (); - unset_special (SPCFLAG_INT | SPCFLAG_DOINT); - if (intr != -1 && intr > regs.intmask) { - Interrupt (intr); - regs.stopped = 0; - unset_special (SPCFLAG_STOP); + if (regs.intmask > 5) { + /* We still have to care about events when IPL==7 ! */ + Main_EventHandler(); + if (regs.spcflags & SPCFLAG_BRK) return 1; + } + + M68000_AddCycles(4); + + /* It is possible one or more ints happen at the same time */ + /* We must process them during the same cpu cycle until the special INT flag is set */ + while (PendingInterruptCount<=0 && PendingInterruptFunction) { + /* 1st, we call the interrupt handler */ + CALL_VAR(PendingInterruptFunction); + /* Then we check if this handler triggered an MFP int to process */ + if (regs.spcflags & SPCFLAG_MFP) + MFP_CheckPendingInterrupts(); + + if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) { + int intr = intlev (); + unset_special (SPCFLAG_INT | SPCFLAG_DOINT); + if (intr != -1 && intr > regs.intmask) { + Interrupt (intr); + regs.stopped = 0; + unset_special (SPCFLAG_STOP); + break; + } } } } + if (regs.spcflags & SPCFLAG_TRACE) do_trace (); - if (regs.spcflags & SPCFLAG_DOINT) { +// if (regs.spcflags & SPCFLAG_DOINT) { + /* [NP] pending int should be processed now, not after the current instr */ + if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) { int intr = intlev (); - unset_special (SPCFLAG_DOINT); + /* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */ +// unset_special (SPCFLAG_DOINT); + unset_special (SPCFLAG_INT | SPCFLAG_DOINT); if (intr != -1 && intr > regs.intmask) { Interrupt (intr); regs.stopped = 0; @@ -1267,13 +1501,20 @@ static int do_specialties (void) unset_special (SPCFLAG_INT); set_special (SPCFLAG_DOINT); } + + if (regs.spcflags & SPCFLAG_MFP) { /* Check for MFP interrupts */ + MFP_CheckPendingInterrupts(); + } + if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) { - unset_special (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE); + unset_special(SPCFLAG_MODE_CHANGE); return 1; } + return 0; } + /* It's really sad to have two almost identical functions for this, but we do it all for performance... :( */ static void m68k_run_1 (void) @@ -1282,9 +1523,11 @@ static void m68k_run_1 (void) uae_u8 saved_bytes[20]; uae_u16 *oldpcp; #endif - while(!quit_program) { + + for (;;) { int cycles; uae_u32 opcode = get_iword_prefetch (0); + #ifdef DEBUG_PREFETCH if (get_ilong (0) != do_get_mem_long (®s.prefetch)) { fprintf (stderr, "Prefetch differs from memory.\n"); @@ -1296,8 +1539,13 @@ static void m68k_run_1 (void) #endif /*m68k_dumpstate(stderr, NULL);*/ - m68k_disasm(stderr, m68k_getpc (), NULL, 1); - /*if( opcode == 0 ) sleep(1);*/ + if ( HATARI_TRACE_LEVEL ( HATARI_TRACE_CPU_DISASM ) ) + { + int nFrameCycles = Cycles_GetCounter(CYCLES_COUNTER_VIDEO);; + int nLineCycles = nFrameCycles % nCyclesPerLine; + HATARI_TRACE_PRINT ( "video_cyc=%6d %3d@%3d : " , nFrameCycles, nLineCycles, nHBL ); + m68k_disasm(stderr, m68k_getpc (), NULL, 1); + } /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */ /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/ @@ -1308,17 +1556,31 @@ static void m68k_run_1 (void) instrcount[opcode]++; #endif - cycles = (*cpufunctbl[cft_map(opcode)])(opcode); + /* In case of a Bus Error, we need the PC of the instruction that caused */ + /* the error to build the exception stack frame */ + BusErrorPC = m68k_getpc(); + + cycles = (*cpufunctbl[opcode])(opcode); #ifdef DEBUG_PREFETCH if (memcmp (saved_bytes, oldpcp, 20) != 0) { - fprintf (stderr, "Self-modifying code detected.\n"); + fprintf (stderr, "Self-modifying code detected %x.\n" , m68k_getpc() ); set_special (SPCFLAG_BRK); debugging = 1; } #endif - do_cycles (cycles); + M68000_AddCyclesWithPairing(cycles); + if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) { + /* Add some extra cycles to simulate a wait state */ + unset_special(SPCFLAG_EXTRA_CYCLES); + M68000_AddCycles(nWaitStateCycles); + nWaitStateCycles = 0; + } + + while (PendingInterruptCount <= 0 && PendingInterruptFunction) + CALL_VAR(PendingInterruptFunction); + if (regs.spcflags) { if (do_specialties ()) return; @@ -1326,23 +1588,22 @@ static void m68k_run_1 (void) } } -#define DEBUG_PREFETCH /* Same thing, but don't use prefetch to get opcode. */ static void m68k_run_2 (void) { - while(!quit_program) { + for (;;) { int cycles; -#ifdef HAVE_GET_WORD_UNSWAPPED - uae_u32 opcode = do_get_mem_word_unswapped (regs.pc_p); -#else uae_u32 opcode = get_iword (0); -#endif /*m68k_dumpstate(stderr, NULL);*/ - /*if(crashtrace) - { --crashtrace ; m68k_disasm(stderr, m68k_getpc (), NULL, 1); }*/ - /*if( opcode == 0 ) sleep(1); */ + if ( HATARI_TRACE_LEVEL ( HATARI_TRACE_CPU_DISASM ) ) + { + int nFrameCycles = Cycles_GetCounter(CYCLES_COUNTER_VIDEO);; + int nLineCycles = nFrameCycles % nCyclesPerLine; + HATARI_TRACE_PRINT ( "video_cyc=%6d %3d@%3d : " , nFrameCycles, nLineCycles, nHBL ); + m68k_disasm(stderr, m68k_getpc (), NULL, 1); + } /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */ /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/ @@ -1353,9 +1614,19 @@ static void m68k_run_2 (void) instrcount[opcode]++; #endif - cycles = (*cpufunctbl[cft_map(opcode)])(opcode); + cycles = (*cpufunctbl[opcode])(opcode); + + M68000_AddCycles(cycles); + if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) { + /* Add some extra cycles to simulate a wait state */ + unset_special(SPCFLAG_EXTRA_CYCLES); + M68000_AddCycles(nWaitStateCycles); + nWaitStateCycles = 0; + } + + while (PendingInterruptCount <= 0 && PendingInterruptFunction) + CALL_VAR(PendingInterruptFunction); - do_cycles (cycles); if (regs.spcflags) { if (do_specialties ()) return; @@ -1364,39 +1635,28 @@ static void m68k_run_2 (void) } -int in_m68k_go = 0; - void m68k_go (int may_quit) { + static int in_m68k_go = 0; + if (in_m68k_go || !may_quit) { write_log ("Bug! m68k_go is not reentrant.\n"); abort (); } in_m68k_go++; - while(!quit_program) { -/* - if (quit_program > 0) { - if (quit_program == 1) - break; - quit_program = 0; - m68k_reset (); - //reset_all_systems (); - customreset (); - } -*/ -/* - if (debugging) - debug (); -*/ - if(cpu_compatible) + while (!(regs.spcflags & SPCFLAG_BRK)) { + if(currprefs.cpu_compatible) m68k_run_1(); else m68k_run_2(); } + unset_special(SPCFLAG_BRK); in_m68k_go--; } + +/* static void m68k_verify (uaecptr addr, uaecptr *nextpc) { uae_u32 opcode, val; @@ -1406,34 +1666,40 @@ static void m68k_verify (uaecptr addr, u last_op_for_exception_3 = opcode; m68kpc_offset = 2; - if (cpufunctbl[cft_map(opcode)] == op_illg_1) { + if (cpufunctbl[opcode] == op_illg_1) { opcode = 0x4AFC; } dp = table68k + opcode; if (dp->suse) { if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) { - Exception (3, 0); + Exception (3, 0,M68000_EXCEPTION_SRC_CPU); return; } } if (dp->duse) { if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) { - Exception (3, 0); + Exception (3, 0,M68000_EXCEPTION_SRC_CPU); return; } } } +*/ + void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt) { + static const char * const ccnames[] = + { "T ","F ","HI","LS","CC","CS","NE","EQ", + "VC","VS","PL","MI","GE","LT","GT","LE" }; + uaecptr newpc = 0; m68kpc_offset = addr - m68k_getpc (); while (cnt-- > 0) { char instrname[20],*ccpt; int opwords; uae_u32 opcode; - struct mnemolookup *lookup; + const struct mnemolookup *lookup; struct instr *dp; fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset); for (opwords = 0; opwords < 5; opwords++){ @@ -1441,7 +1707,7 @@ void m68k_disasm (FILE *f, uaecptr addr, } opcode = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; - if (cpufunctbl[cft_map(opcode)] == op_illg_1) { + if (cpufunctbl[opcode] == op_illg_1) { opcode = 0x4AFC; } dp = table68k + opcode; @@ -1473,11 +1739,11 @@ void m68k_disasm (FILE *f, uaecptr addr, } if (ccpt != 0) { if (cctrue(dp->cc)) - fprintf (f, " == %08lx (TRUE)", newpc); + fprintf (f, " == %08lx (TRUE)", (long)newpc); else - fprintf (f, " == %08lx (FALSE)", newpc); + fprintf (f, " == %08lx (FALSE)", (long)newpc); } else if ((opcode & 0xff00) == 0x6100) /* BSR */ - fprintf (f, " == %08lx", newpc); + fprintf (f, " == %08lx", (long)newpc); fprintf (f, "\n"); } if (nextpc) @@ -1488,18 +1754,18 @@ void m68k_dumpstate (FILE *f, uaecptr *n { int i; for (i = 0; i < 8; i++){ - fprintf (f, "D%d: %08lx ", i, m68k_dreg(regs, i)); + fprintf (f, "D%d: %08lx ", i, (long)m68k_dreg(regs, i)); if ((i & 3) == 3) fprintf (f, "\n"); } for (i = 0; i < 8; i++){ - fprintf (f, "A%d: %08lx ", i, m68k_areg(regs, i)); + fprintf (f, "A%d: %08lx ", i, (long)m68k_areg(regs, i)); if ((i & 3) == 3) fprintf (f, "\n"); } if (regs.s == 0) regs.usp = m68k_areg(regs, 7); if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7); if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7); fprintf (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n", - regs.usp,regs.isp,regs.msp,regs.vbr); + (long)regs.usp,(long)regs.isp,(long)regs.msp,(long)regs.vbr); fprintf (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n", regs.t1, regs.t0, regs.s, regs.m, GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask); @@ -1512,10 +1778,146 @@ void m68k_dumpstate (FILE *f, uaecptr *n (regs.fpsr & 0x4000000) != 0, (regs.fpsr & 0x2000000) != 0, (regs.fpsr & 0x1000000) != 0); - if (cpu_compatible) + if (currprefs.cpu_compatible) fprintf (f, "prefetch %08lx\n", (unsigned long)do_get_mem_long(®s.prefetch)); m68k_disasm (f, m68k_getpc (), nextpc, 1); if (nextpc) - fprintf (f, "next PC: %08lx\n", *nextpc); + fprintf (f, "next PC: %08lx\n", (long)*nextpc); +} + + +/* + + The routines below take dividend and divisor as parameters. + They return 0 if division by zero, or exact number of cycles otherwise. + + The number of cycles returned assumes a register operand. + Effective address time must be added if memory operand. + + For 68000 only (not 68010, 68012, 68020, etc). + Probably valid for 68008 after adding the extra prefetch cycle. + + + Best and worst cases are for register operand: + (Note the difference with the documented range.) + + + DIVU: + + Overflow (always): 10 cycles. + Worst case: 136 cycles. + Best case: 76 cycles. + + + DIVS: + + Absolute overflow: 16-18 cycles. + Signed overflow is not detected prematurely. + + Worst case: 156 cycles. + Best case without signed overflow: 122 cycles. + Best case with signed overflow: 120 cycles + + + */ + + +// +// DIVU +// Unsigned division +// + +STATIC_INLINE int getDivu68kCycles_2 (uae_u32 dividend, uae_u16 divisor) +{ + int mcycles; + uae_u32 hdivisor; + int i; + + if (divisor == 0) + return 0; + + // Overflow + if ((dividend >> 16) >= divisor) + return (mcycles = 5) * 2; + + mcycles = 38; + hdivisor = divisor << 16; + + for (i = 0; i < 15; i++) { + uae_u32 temp; + temp = dividend; + + dividend <<= 1; + + // If carry from shift + if ((uae_s32)temp < 0) + dividend -= hdivisor; + else { + mcycles += 2; + if (dividend >= hdivisor) { + dividend -= hdivisor; + mcycles--; + } + } + } + return mcycles * 2; +} +int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor) +{ + int v = getDivu68kCycles_2 (dividend, divisor) - 4; +// write_log ("U%d ", v); + return v; +} + +// +// DIVS +// Signed division +// + +STATIC_INLINE int getDivs68kCycles_2 (uae_s32 dividend, uae_s16 divisor) +{ + int mcycles; + uae_u32 aquot; + int i; + + if (divisor == 0) + return 0; + + mcycles = 6; + + if (dividend < 0) + mcycles++; + + // Check for absolute overflow + if (((uae_u32)abs (dividend) >> 16) >= (uae_u16)abs (divisor)) + return (mcycles + 2) * 2; + + // Absolute quotient + aquot = (uae_u32) abs (dividend) / (uae_u16)abs (divisor); + + mcycles += 55; + + if (divisor >= 0) { + if (dividend >= 0) + mcycles--; + else + mcycles++; + } + + // Count 15 msbits in absolute of quotient + + for (i = 0; i < 15; i++) { + if ((uae_s16)aquot >= 0) + mcycles++; + aquot <<= 1; + } + + return mcycles * 2; +} +int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor) +{ + int v = getDivs68kCycles_2 (dividend, divisor) - 4; +// write_log ("S%d ", v); + return v; }