--- hatari/src/uae-cpu/newcpu.c 2019/04/01 07:11:55 1.1.1.9 +++ hatari/src/uae-cpu/newcpu.c 2019/04/01 07:13:48 1.1.1.12 @@ -10,7 +10,56 @@ * This file is distributed under the GNU Public License, version 2 or at * your option any later version. Read the file gpl.txt for details. */ -char NewCpu_rcsid[] = "Hatari $Id: newcpu.c,v 1.1.1.9 2019/04/01 07:11:55 root Exp $"; + + +/* 2007/11/12 [NP] Add HATARI_TRACE_CPU_DISASM. */ +/* 2007/11/15 [NP] In MakeFromSR, writes to m and t0 should be ignored and set to 0 if cpu < 68020 */ +/* 2007/11/26 [NP] We set BusErrorPC in m68k_run_1 instead of M68000_BusError, else the BusErrorPC */ +/* will not point to the opcode that generated the bus error. */ +/* Huge debug/work on Exceptions 2/3 stack frames, result is more accurate and */ +/* allow to pass the very tricky Transbeauce 2 Demo's protection. */ +/* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */ +/* Cwik, pasti@fxatari.com). */ +/* 2007/12/06 [NP] The PC stored in the stack frame for the bus error is complex to emulate, */ +/* because it doesn't necessarily point to the next instruction after the one that */ +/* triggered the bus error. In the case of the Transbeauce 2 Demo, after */ +/* 'move.l $0.w,$24.w', PC is incremented of 4 bytes, not 6, and stored in the */ +/* stack. Special case to decrement PC of 2 bytes if opcode is '21f8'. */ +/* This should be fixed with a real model. */ +/* 2007/12/07 [NP] If Trace is enabled and a group 2 exception occurs (such as CHK), the trace */ +/* handler should be called after the group 2's handler. If a bus error, address */ +/* error or illegal occurs while Trace is enabled, the trace handler should not be */ +/* called after this instruction (Transbeauce 2 Demo, Phaleon Demo). */ +/* This means that if a CHK is executed while trace bit was set, we must set PC */ +/* to CHK handler, turn trace off in the internal SR, but we must still call the */ +/* trace handler one last time with the PC set to the CHK's handler (even if */ +/* trace mode is internally turned off while processing an exception). Once trace */ +/* handler is finished (RTE), we return to the CHK's handler. */ +/* This is true for DIV BY 0, CHK, TRAPV and TRAP. */ +/* Backport exception_trace() from WinUAE to handle this behaviour (used in */ +/* Transbeauce 2 demo). */ +/* 2007/12/09 [NP] 'dc.w $a' should not be used to call 'OpCode_SysInit' but should give an illegal*/ +/* instruction (Transbeauce 2 demo). */ +/* Instead of always replacing the illegal instructions $8, $a and $c by the */ +/* 3 functions required for HD emulation, we now do it in cart.c only if the */ +/* built-in cartridge image is loaded. */ +/* YEAH! Hatari is now the first emulator to pass the Transbeauce 2 protection :) */ +/* 2007/12/18 [NP] More precise timings for HBL, VBL and MFP interrupts. On ST, these interrupts */ +/* are taking 56 cycles instead of the 44 cycles in the 68000's documentation. */ +/* 2007/12/24 [NP] If an interrupt (HBL, VBL) is pending after intruction 'n' was processed, the */ +/* exception should be called before instr. 'n+1' is processed, not after (else the*/ +/* interrupt's handler is delayed by one 68000's instruction, which could break */ +/* some demos with too strict timings) (ACF's Demo Main Menu). */ +/* We call the interrupt if ( SPCFLAG_INT | SPCFLAG_DOINT ) is set, not only if */ +/* SPCFLAG_DOINT is set (as it was already the case when handling 'STOP'). */ +/* 2007/12/25 [NP] FIXME When handling exceptions' cycles, using nr >= 64 to determine if this is */ +/* an MFP exception could be wrong if the MFP VR was set to another value than the */ +/* default $40 (this could be a problem with programs requiring a precise cycles */ +/* calculation while changing VR, but no such programs were encountered so far). */ + + + +const char NewCpu_rcsid[] = "Hatari $Id: newcpu.c,v 1.1.1.12 2019/04/01 07:13:48 root Exp $"; #include "sysdeps.h" #include "hatari-glue.h" @@ -18,7 +67,9 @@ char NewCpu_rcsid[] = "Hatari $Id: newcp #include "memory.h" #include "newcpu.h" #include "../includes/main.h" +#include "../includes/log.h" #include "../includes/m68000.h" +#include "../includes/int.h" #include "../includes/mfp.h" #include "../includes/tos.h" #include "../includes/vdi.h" @@ -26,7 +77,10 @@ char NewCpu_rcsid[] = "Hatari $Id: newcp #include "../includes/debugui.h" #include "../includes/bios.h" #include "../includes/xbios.h" +#include "../includes/video.h" +#include "../includes/trace.h" +//#define DEBUG_PREFETCH struct flag_struct regflags; @@ -37,8 +91,8 @@ uaecptr last_addr_for_exception_3; /* Address that generated the exception */ uaecptr last_fault_for_exception_3; -int areg_byteinc[] = { 1,1,1,1,1,1,1,2 }; -int imm8_table[] = { 8,1,2,3,4,5,6,7 }; +const int areg_byteinc[] = { 1,1,1,1,1,1,1,2 }; +const int imm8_table[] = { 8,1,2,3,4,5,6,7 }; int movem_index1[256]; int movem_index2[256]; @@ -50,6 +104,7 @@ int fpp_movem_next[256]; cpuop_func *cpufunctbl[65536]; +int OpcodeFamily; #define COUNT_INSTRS 0 @@ -117,15 +172,15 @@ void build_cpufunctbl(void) { int i; unsigned long opcode; - struct cputbl *tbl = (cpu_level == 4 ? op_smalltbl_0_ff - : cpu_level == 3 ? op_smalltbl_1_ff - : cpu_level == 2 ? op_smalltbl_2_ff - : cpu_level == 1 ? op_smalltbl_3_ff - : ! cpu_compatible ? op_smalltbl_4_ff - : op_smalltbl_5_ff); + const struct cputbl *tbl = (currprefs.cpu_level == 4 ? op_smalltbl_0_ff + : currprefs.cpu_level == 3 ? op_smalltbl_1_ff + : currprefs.cpu_level == 2 ? op_smalltbl_2_ff + : currprefs.cpu_level == 1 ? op_smalltbl_3_ff + : ! currprefs.cpu_compatible ? op_smalltbl_4_ff + : op_smalltbl_5_ff); - write_log ("Building CPU function table (%d %d %d).\n", - cpu_level, cpu_compatible, address_space_24); + Log_Printf(LOG_DEBUG, "Building CPU function table (%d %d %d).\n", + currprefs.cpu_level, currprefs.cpu_compatible, currprefs.address_space_24); for (opcode = 0; opcode < 65536; opcode++) cpufunctbl[opcode] = op_illg_1; @@ -136,7 +191,7 @@ void build_cpufunctbl(void) for (opcode = 0; opcode < 65536; opcode++) { cpuop_func *f; - if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level) + if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > currprefs.cpu_level) continue; if (table68k[opcode].handler != -1) { @@ -150,11 +205,6 @@ void build_cpufunctbl(void) if (tbl[i].specific) cpufunctbl[tbl[i].opcode] = tbl[i].handler; } - - /* Hatari's illegal opcodes: */ - cpufunctbl[GEMDOS_OPCODE] = OpCode_GemDos; - cpufunctbl[SYSINIT_OPCODE] = OpCode_SysInit; - cpufunctbl[VDI_OPCODE] = OpCode_VDI; } @@ -198,9 +248,9 @@ void init_m68k (void) } #endif write_log ("Building CPU table for configuration: 68"); - if (address_space_24 && cpu_level > 1) + if (currprefs.address_space_24 && currprefs.cpu_level > 1) write_log ("EC"); - switch (cpu_level) { + switch (currprefs.cpu_level) { case 1: write_log ("010"); break; @@ -218,26 +268,28 @@ void init_m68k (void) write_log ("000"); break; } - if (cpu_compatible) + if (currprefs.cpu_compatible) write_log (" (compatible mode)"); write_log ("\n"); read_table68k (); do_merges (); - write_log ("%d CPU functions\n", nr_cpuop_funcs); + Log_Printf(LOG_DEBUG, "%d CPU functions\n", nr_cpuop_funcs); build_cpufunctbl (); } -struct regstruct regs, lastint_regs; /* not used ATM: static struct regstruct regs_backup[16]; static int backup_pointer = 0; +struct regstruct lastint_regs; +int lastint_no; */ +struct regstruct regs; static long int m68kpc_offset; -int lastint_no; + #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1) #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o)) @@ -633,7 +685,7 @@ void MakeFromSR (void) SET_ZFLG ((regs.sr >> 2) & 1); SET_VFLG ((regs.sr >> 1) & 1); SET_CFLG (regs.sr & 1); - if (cpu_level >= 2) { + if (currprefs.cpu_level >= 2) { if (olds != regs.s) { if (olds) { if (oldm) @@ -655,6 +707,10 @@ void MakeFromSR (void) } } } else { + /* [NP] If cpu < 68020, m and t0 are ignored and should be set to 0 */ + regs.t0 = 0; + regs.m = 0; + if (olds != regs.s) { if (olds) { regs.isp = m68k_areg(regs, 7); @@ -677,6 +733,20 @@ void MakeFromSR (void) } +static void exception_trace (int nr) +{ + unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE); + if (regs.t1 && !regs.t0) { + /* trace stays pending if exception is div by zero, chk, + * trapv or trap #x + */ + if (nr == 5 || nr == 6 || nr == 7 || (nr >= 32 && nr <= 47)) + set_special (SPCFLAG_DOTRACE); + } + regs.t1 = regs.t0 = regs.m = 0; +} + + void Exception(int nr, uaecptr oldpc) { uae_u32 currpc = m68k_getpc (); @@ -715,7 +785,7 @@ void Exception(int nr, uaecptr oldpc) /* Change to supervisor mode if necessary */ if (!regs.s) { regs.usp = m68k_areg(regs, 7); - if (cpu_level >= 2) + if (currprefs.cpu_level >= 2) m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp; else m68k_areg(regs, 7) = regs.isp; @@ -723,7 +793,7 @@ void Exception(int nr, uaecptr oldpc) } /* Build additional exception stack frame for 68010 and higher */ - if (cpu_level > 0) { + if (currprefs.cpu_level > 0) { if (nr == 2 || nr == 3) { int i; /* @@@ this is probably wrong (?) */ @@ -763,14 +833,19 @@ void Exception(int nr, uaecptr oldpc) m68k_areg(regs, 7) -= 2; put_word (m68k_areg(regs, 7), regs.sr); + HATARI_TRACE ( HATARI_TRACE_CPU_EXCEPTION , "cpu exception %d currpc %x buspc %x fault_e3 %x op_e3 %hx addr_e3 %x\n" , + nr, currpc, BusErrorPC, last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3 ); + /* 68000 bus/address errors: */ - if (cpu_level==0 && (nr==2 || nr==3)) { - uae_u16 specialstatus = 0x2001; + if (currprefs.cpu_level==0 && (nr==2 || nr==3)) { + uae_u16 specialstatus = 1; + /* Special status word emulation isn't perfect yet... :-( */ if (regs.sr & 0x2000) specialstatus |= 0x4; m68k_areg(regs, 7) -= 8; if (nr == 3) { /* Address error */ + specialstatus |= ( last_op_for_exception_3 & (~0x1f) ); /* [NP] unused bits of specialstatus are those of the last opcode ! */ put_word (m68k_areg(regs, 7), specialstatus); put_long (m68k_areg(regs, 7)+2, last_fault_for_exception_3); put_word (m68k_areg(regs, 7)+6, last_op_for_exception_3); @@ -781,15 +856,21 @@ void Exception(int nr, uaecptr oldpc) } } else { /* Bus error */ + specialstatus |= ( get_word(BusErrorPC) & (~0x1f) ); /* [NP] unused bits of special status are those of the last opcode ! */ if (bBusErrorReadWrite) specialstatus |= 0x10; put_word (m68k_areg(regs, 7), specialstatus); - put_long (m68k_areg(regs, 7)+2, BusAddressLocation); - put_word (m68k_areg(regs, 7)+6, get_word(BusErrorPC)); /* Opcode */ + put_long (m68k_areg(regs, 7)+2, BusErrorAddress); + put_word (m68k_areg(regs, 7)+6, get_word(BusErrorPC)); /* Opcode */ + + /* [NP] PC stored in the stack frame is not necessarily pointing to the next instruction ! */ + /* FIXME : we should have a proper model for this, in the meantime we handle specific cases */ + if ( get_word(BusErrorPC) == 0x21f8 ) /* move.l $0.w,$24.w (Transbeauce 2 loader) */ + put_long (m68k_areg(regs, 7)+10, currpc-2); /* correct PC is 2 bytes less than usual value */ /* Check for double bus errors: */ if (regs.spcflags & SPCFLAG_BUSERROR) { fprintf(stderr, "Detected double bus error at address $%x, PC=$%lx => CPU halted!\n", - BusAddressLocation, (long)currpc); + BusErrorAddress, (long)currpc); unset_special(SPCFLAG_BUSERROR); if (bEnableDebug) DebugUI(); @@ -797,8 +878,8 @@ void Exception(int nr, uaecptr oldpc) m68k_setstopped(TRUE); return; } - if (bEnableDebug && BusAddressLocation!=0xff8a00) { - fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n",BusAddressLocation,(long)currpc); + if (bEnableDebug && BusErrorAddress!=0xff8a00) { + fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n", BusErrorAddress, (long)currpc); DebugUI(); } } @@ -807,39 +888,44 @@ void Exception(int nr, uaecptr oldpc) /* Set PC and flags */ if (bEnableDebug && get_long (regs.vbr + 4*nr) == 0) { write_log("Uninitialized exception handler #%i!\n", nr); + if (bEnableDebug) + DebugUI(); } m68k_setpc (get_long (regs.vbr + 4*nr)); fill_prefetch_0 (); - regs.t1 = regs.t0 = regs.m = 0; - unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE); + /* Handle trace flags depending on current state */ + exception_trace (nr); - /* Handle exception cycles: */ + /* Handle exception cycles */ if(nr >= 24 && nr <= 31) { - M68000_AddCycles(44+4); /* Interrupt */ + if ( ( nr == 26 ) || ( nr == 28 ) ) /* HBL or VBL */ + M68000_AddCycles(44+12); /* Video Interrupt */ + else + M68000_AddCycles(44+4); /* Other Interrupts */ } else if(nr >= 32 && nr <= 47) { - M68000_AddCycles(34); /* Trap */ + M68000_AddCycles(34); /* Trap */ } else switch(nr) { - case 2: M68000_AddCycles(50); break; /* Bus error */ - case 3: M68000_AddCycles(50); break; /* Address error */ - case 4: M68000_AddCycles(34); break; /* Illegal instruction */ - case 5: M68000_AddCycles(38); break; /* Div by zero */ - case 6: M68000_AddCycles(40); break; /* CHK */ - case 7: M68000_AddCycles(34); break; /* TRAPV */ - case 8: M68000_AddCycles(34); break; /* Privilege violation */ - case 9: M68000_AddCycles(34); break; /* Trace */ - case 10: M68000_AddCycles(34); break; /* Line-A - probably wrong */ - case 11: M68000_AddCycles(34); break; /* Line-F - probably wrong */ + case 2: M68000_AddCycles(50); break; /* Bus error */ + case 3: M68000_AddCycles(50); break; /* Address error */ + case 4: M68000_AddCycles(34); break; /* Illegal instruction */ + case 5: M68000_AddCycles(38); break; /* Div by zero */ + case 6: M68000_AddCycles(40); break; /* CHK */ + case 7: M68000_AddCycles(34); break; /* TRAPV */ + case 8: M68000_AddCycles(34); break; /* Privilege violation */ + case 9: M68000_AddCycles(34); break; /* Trace */ + case 10: M68000_AddCycles(34); break; /* Line-A - probably wrong */ + case 11: M68000_AddCycles(34); break; /* Line-F - probably wrong */ default: /* FIXME: Add right cycles value for MFP interrupts and copro exceptions ... */ if(nr < 64) - M68000_AddCycles(4); /* Coprocessor and unassigned exceptions (???) */ + M68000_AddCycles(4); /* Coprocessor and unassigned exceptions (???) */ else - M68000_AddCycles(24); /* Must be a MFP interrupt */ + M68000_AddCycles(44+12); /* Must be a MFP interrupt */ break; } } @@ -848,8 +934,8 @@ void Exception(int nr, uaecptr oldpc) static void Interrupt(int nr) { assert(nr < 8 && nr >= 0); - lastint_regs = regs; - lastint_no = nr; + /*lastint_regs = regs;*/ + /*lastint_no = nr;*/ Exception(nr+24, 0); regs.intmask = nr; @@ -857,23 +943,45 @@ static void Interrupt(int nr) } -uae_u32 reg_caar, reg_cacr; +uae_u32 caar, cacr; static uae_u32 itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp; +static int movec_illg (int regno) +{ + int regno2 = regno & 0x7ff; + if (currprefs.cpu_level == 1) { /* 68010 */ + if (regno2 < 2) + return 0; + return 1; + } + if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) { /* 68020 */ + if (regno == 3) return 1; /* 68040 only */ + /* 4 is >=68040, but 0x804 is in 68020 */ + if (regno2 < 4 || regno == 0x804) + return 0; + return 1; + } + if (currprefs.cpu_level >= 4) { /* 68040 */ + if (regno == 0x802) return 1; /* 68020 only */ + if (regno2 < 8) return 0; + if (currprefs.cpu_level == 6 && regno2 == 8) /* 68060 only */ + return 0; + return 1; + } + return 1; +} + int m68k_move2c (int regno, uae_u32 *regp) { - if ((cpu_level == 1 && (regno & 0x7FF) > 1) - || (cpu_level < 4 && (regno & 0x7FF) > 2) - || (cpu_level == 4 && regno == 0x802)) - { + if (movec_illg (regno)) { op_illg (0x4E7B); return 0; } else { switch (regno) { case 0: regs.sfc = *regp & 7; break; case 1: regs.dfc = *regp & 7; break; - case 2: reg_cacr = *regp & (cpu_level < 4 ? 0x3 : 0x80008000); break; + case 2: cacr = *regp & (currprefs.cpu_level < 4 ? 0x3 : 0x80008000); break; case 3: tc = *regp & 0xc000; break; /* Mask out fields that should be zero. */ case 4: itt0 = *regp & 0xffffe364; break; @@ -883,7 +991,7 @@ int m68k_move2c (int regno, uae_u32 *reg case 0x800: regs.usp = *regp; break; case 0x801: regs.vbr = *regp; break; - case 0x802: reg_caar = *regp & 0xfc; break; + case 0x802: caar = *regp & 0xfc; break; case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break; case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break; case 0x805: mmusr = *regp; break; @@ -899,17 +1007,14 @@ int m68k_move2c (int regno, uae_u32 *reg int m68k_movec2 (int regno, uae_u32 *regp) { - if ((cpu_level == 1 && (regno & 0x7FF) > 1) - || (cpu_level < 4 && (regno & 0x7FF) > 2) - || (cpu_level == 4 && regno == 0x802)) - { + if (movec_illg (regno)) { op_illg (0x4E7A); return 0; } else { switch (regno) { case 0: *regp = regs.sfc; break; case 1: *regp = regs.dfc; break; - case 2: *regp = reg_cacr; break; + case 2: *regp = cacr; break; case 3: *regp = tc; break; case 4: *regp = itt0; break; case 5: *regp = itt1; break; @@ -917,7 +1022,7 @@ int m68k_movec2 (int regno, uae_u32 *reg case 7: *regp = dtt1; break; case 0x800: *regp = regs.usp; break; case 0x801: *regp = regs.vbr; break; - case 0x802: *regp = reg_caar; break; + case 0x802: *regp = caar; break; case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break; case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break; case 0x805: *regp = mmusr; break; @@ -932,12 +1037,12 @@ int m68k_movec2 (int regno, uae_u32 *reg } STATIC_INLINE int -div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 div, uae_u32 *quot, uae_u32 *rem) +div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 ndiv, uae_u32 *quot, uae_u32 *rem) { uae_u32 q = 0, cbit = 0; int i; - if (div <= src_hi) { + if (ndiv <= src_hi) { return 1; } for (i = 0 ; i < 32 ; i++) { @@ -946,9 +1051,9 @@ div_unsigned(uae_u32 src_hi, uae_u32 src if (src_lo & 0x80000000ul) src_hi++; src_lo <<= 1; q = q << 1; - if (cbit || div <= src_hi) { + if (cbit || ndiv <= src_hi) { q |= 1; - src_hi -= div; + src_hi -= ndiv; } } *quot = q; @@ -1246,7 +1351,7 @@ static uaecptr last_trace_ad = 0; static void do_trace (void) { - if (regs.t0 && cpu_level >= 2) { + if (regs.t0 && currprefs.cpu_level >= 2) { uae_u16 opcode; /* should also include TRAP, CHK, SR modification FPcc */ /* probably never used so why bother */ @@ -1296,7 +1401,8 @@ static int do_specialties (void) if(regs.spcflags & SPCFLAG_EXTRA_CYCLES) { /* Add some extra cycles to simulate a wait state */ unset_special(SPCFLAG_EXTRA_CYCLES); - M68000_AddCycles(4); + M68000_AddCycles(nWaitStateCycles); + nWaitStateCycles = 0; } if (regs.spcflags & SPCFLAG_DOTRACE) { @@ -1330,10 +1436,13 @@ static int do_specialties (void) if (regs.spcflags & SPCFLAG_TRACE) do_trace (); - if (regs.spcflags & SPCFLAG_DOINT) { +// if (regs.spcflags & SPCFLAG_DOINT) { + /* [NP] pending int should be processed now, not after the current instr */ + if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) { int intr = intlev (); /* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */ - unset_special (SPCFLAG_DOINT); +// unset_special (SPCFLAG_DOINT); + unset_special (SPCFLAG_INT | SPCFLAG_DOINT); if (intr != -1 && intr > regs.intmask) { Interrupt (intr); regs.stopped = 0; @@ -1381,7 +1490,13 @@ static void m68k_run_1 (void) #endif /*m68k_dumpstate(stderr, NULL);*/ - /*m68k_disasm(stderr, m68k_getpc (), NULL, 1);*/ + if ( HATARI_TRACE_LEVEL ( HATARI_TRACE_CPU_DISASM ) ) + { + int nFrameCycles = Cycles_GetCounter(CYCLES_COUNTER_VIDEO);; + int nLineCycles = nFrameCycles % nCyclesPerLine; + HATARI_TRACE_PRINT ( "video_cyc=%6d %3d@%3d : " , nFrameCycles, nLineCycles, nHBL ); + m68k_disasm(stderr, m68k_getpc (), NULL, 1); + } /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */ /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/ @@ -1392,18 +1507,22 @@ static void m68k_run_1 (void) instrcount[opcode]++; #endif + /* In case of a Bus Error, we need the PC of the instruction that caused */ + /* the error to build the exception stack frame */ + BusErrorPC = m68k_getpc(); + cycles = (*cpufunctbl[opcode])(opcode); #ifdef DEBUG_PREFETCH if (memcmp (saved_bytes, oldpcp, 20) != 0) { - fprintf (stderr, "Self-modifying code detected.\n"); + fprintf (stderr, "Self-modifying code detected %x.\n" , m68k_getpc() ); set_special (SPCFLAG_BRK); debugging = 1; } #endif - M68000_AddCycles(cycles); - if (PendingInterruptCount<=0 && PendingInterruptFunction) + M68000_AddCyclesWithPairing(cycles); + while (PendingInterruptCount <= 0 && PendingInterruptFunction) CALL_VAR(PendingInterruptFunction); if (regs.spcflags) { @@ -1422,7 +1541,14 @@ static void m68k_run_2 (void) uae_u32 opcode = get_iword (0); /*m68k_dumpstate(stderr, NULL);*/ - /*m68k_disasm(stderr, m68k_getpc (), NULL, 1);*/ + if ( HATARI_TRACE_LEVEL ( HATARI_TRACE_CPU_DISASM ) ) + { + int nFrameCycles = Cycles_GetCounter(CYCLES_COUNTER_VIDEO);; + int nLineCycles = nFrameCycles % nCyclesPerLine; + HATARI_TRACE_PRINT ( "video_cyc=%6d %3d@%3d : " , nFrameCycles, nLineCycles, nHBL ); + m68k_disasm(stderr, m68k_getpc (), NULL, 1); + } + /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */ /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/ @@ -1436,7 +1562,7 @@ static void m68k_run_2 (void) cycles = (*cpufunctbl[opcode])(opcode); M68000_AddCycles(cycles); - if (PendingInterruptCount<=0 && PendingInterruptFunction) + while (PendingInterruptCount <= 0 && PendingInterruptFunction) CALL_VAR(PendingInterruptFunction); if (regs.spcflags) { @@ -1458,7 +1584,7 @@ void m68k_go (int may_quit) in_m68k_go++; while (!(regs.spcflags & SPCFLAG_BRK)) { - if(cpu_compatible) + if(currprefs.cpu_compatible) m68k_run_1(); else m68k_run_2(); @@ -1501,7 +1627,7 @@ static void m68k_verify (uaecptr addr, u void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt) { - static const char* ccnames[] = + static const char * const ccnames[] = { "T ","F ","HI","LS","CC","CS","NE","EQ", "VC","VS","PL","MI","GE","LT","GT","LE" }; @@ -1511,7 +1637,7 @@ void m68k_disasm (FILE *f, uaecptr addr, char instrname[20],*ccpt; int opwords; uae_u32 opcode; - struct mnemolookup *lookup; + const struct mnemolookup *lookup; struct instr *dp; fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset); for (opwords = 0; opwords < 5; opwords++){ @@ -1590,10 +1716,146 @@ void m68k_dumpstate (FILE *f, uaecptr *n (regs.fpsr & 0x4000000) != 0, (regs.fpsr & 0x2000000) != 0, (regs.fpsr & 0x1000000) != 0); - if (cpu_compatible) + if (currprefs.cpu_compatible) fprintf (f, "prefetch %08lx\n", (unsigned long)do_get_mem_long(®s.prefetch)); m68k_disasm (f, m68k_getpc (), nextpc, 1); if (nextpc) fprintf (f, "next PC: %08lx\n", (long)*nextpc); } + + +/* + + The routines below take dividend and divisor as parameters. + They return 0 if division by zero, or exact number of cycles otherwise. + + The number of cycles returned assumes a register operand. + Effective address time must be added if memory operand. + + For 68000 only (not 68010, 68012, 68020, etc). + Probably valid for 68008 after adding the extra prefetch cycle. + + + Best and worst cases are for register operand: + (Note the difference with the documented range.) + + + DIVU: + + Overflow (always): 10 cycles. + Worst case: 136 cycles. + Best case: 76 cycles. + + + DIVS: + + Absolute overflow: 16-18 cycles. + Signed overflow is not detected prematurely. + + Worst case: 156 cycles. + Best case without signed overflow: 122 cycles. + Best case with signed overflow: 120 cycles + + + */ + + +// +// DIVU +// Unsigned division +// + +STATIC_INLINE int getDivu68kCycles_2 (uae_u32 dividend, uae_u16 divisor) +{ + int mcycles; + uae_u32 hdivisor; + int i; + + if (divisor == 0) + return 0; + + // Overflow + if ((dividend >> 16) >= divisor) + return (mcycles = 5) * 2; + + mcycles = 38; + hdivisor = divisor << 16; + + for (i = 0; i < 15; i++) { + uae_u32 temp; + temp = dividend; + + dividend <<= 1; + + // If carry from shift + if ((uae_s32)temp < 0) + dividend -= hdivisor; + else { + mcycles += 2; + if (dividend >= hdivisor) { + dividend -= hdivisor; + mcycles--; + } + } + } + return mcycles * 2; +} +int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor) +{ + int v = getDivu68kCycles_2 (dividend, divisor) - 4; +// write_log ("U%d ", v); + return v; +} + +// +// DIVS +// Signed division +// + +STATIC_INLINE int getDivs68kCycles_2 (uae_s32 dividend, uae_s16 divisor) +{ + int mcycles; + uae_u32 aquot; + int i; + + if (divisor == 0) + return 0; + + mcycles = 6; + + if (dividend < 0) + mcycles++; + + // Check for absolute overflow + if (((uae_u32)abs (dividend) >> 16) >= (uae_u16)abs (divisor)) + return (mcycles + 2) * 2; + + // Absolute quotient + aquot = (uae_u32) abs (dividend) / (uae_u16)abs (divisor); + + mcycles += 55; + + if (divisor >= 0) { + if (dividend >= 0) + mcycles--; + else + mcycles++; + } + + // Count 15 msbits in absolute of quotient + + for (i = 0; i < 15; i++) { + if ((uae_s16)aquot >= 0) + mcycles++; + aquot <<= 1; + } + + return mcycles * 2; +} +int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor) +{ + int v = getDivs68kCycles_2 (dividend, divisor) - 4; +// write_log ("S%d ", v); + return v; +}