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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation
5: *
6: * (c) 1995 Bernd Schmidt
1.1.1.2 root 7: *
8: * Adaptation to Hatari by Thomas Huth
9: *
1.1.1.6 root 10: * This file is distributed under the GNU Public License, version 2 or at
11: * your option any later version. Read the file gpl.txt for details.
1.1 root 12: */
1.1.1.10! root 13: char NewCpu_rcsid[] = "Hatari $Id: newcpu.c,v 1.39 2005/06/05 14:19:40 thothy Exp $";
1.1 root 14:
15: #include "sysdeps.h"
16: #include "hatari-glue.h"
17: #include "maccess.h"
18: #include "memory.h"
19: #include "newcpu.h"
1.1.1.5 root 20: #include "../includes/main.h"
1.1.1.10! root 21: #include "../includes/log.h"
1.1.1.7 root 22: #include "../includes/m68000.h"
1.1.1.8 root 23: #include "../includes/mfp.h"
1.1 root 24: #include "../includes/tos.h"
1.1.1.5 root 25: #include "../includes/vdi.h"
26: #include "../includes/cart.h"
27: #include "../includes/debugui.h"
1.1.1.8 root 28: #include "../includes/bios.h"
29: #include "../includes/xbios.h"
1.1 root 30:
31:
32: struct flag_struct regflags;
33:
34: /* Opcode of faulting instruction */
35: uae_u16 last_op_for_exception_3;
36: /* PC at fault time */
37: uaecptr last_addr_for_exception_3;
38: /* Address that generated the exception */
39: uaecptr last_fault_for_exception_3;
40:
41: int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
42: int imm8_table[] = { 8,1,2,3,4,5,6,7 };
43:
44: int movem_index1[256];
45: int movem_index2[256];
46: int movem_next[256];
47:
48: int fpp_movem_index1[256];
49: int fpp_movem_index2[256];
50: int fpp_movem_next[256];
51:
52: cpuop_func *cpufunctbl[65536];
53:
1.1.1.6 root 54:
1.1 root 55: #define COUNT_INSTRS 0
56:
57: #if COUNT_INSTRS
58: static unsigned long int instrcount[65536];
59: static uae_u16 opcodenums[65536];
60:
61: static int compfn (const void *el1, const void *el2)
62: {
63: return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
64: }
65:
66: static char *icountfilename (void)
67: {
68: char *name = getenv ("INSNCOUNT");
69: if (name)
70: return name;
71: return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
72: }
73:
74: void dump_counts (void)
75: {
76: FILE *f = fopen (icountfilename (), "w");
77: unsigned long int total;
78: int i;
79:
80: write_log ("Writing instruction count file...\n");
81: for (i = 0; i < 65536; i++) {
82: opcodenums[i] = i;
83: total += instrcount[i];
84: }
85: qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
86:
87: fprintf (f, "Total: %lu\n", total);
88: for (i=0; i < 65536; i++) {
89: unsigned long int cnt = instrcount[opcodenums[i]];
90: struct instr *dp;
91: struct mnemolookup *lookup;
92: if (!cnt)
93: break;
94: dp = table68k + opcodenums[i];
95: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
96: ;
97: fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
98: }
99: fclose (f);
100: }
101: #else
102: void dump_counts (void)
103: {
104: }
105: #endif
106:
107:
108: static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM;
109:
110: static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
111: {
1.1.1.6 root 112: op_illg (opcode);
1.1 root 113: return 4;
114: }
115:
1.1.1.4 root 116:
117: void build_cpufunctbl(void)
1.1 root 118: {
119: int i;
120: unsigned long opcode;
121: struct cputbl *tbl = (cpu_level == 4 ? op_smalltbl_0_ff
122: : cpu_level == 3 ? op_smalltbl_1_ff
123: : cpu_level == 2 ? op_smalltbl_2_ff
124: : cpu_level == 1 ? op_smalltbl_3_ff
125: : ! cpu_compatible ? op_smalltbl_4_ff
126: : op_smalltbl_5_ff);
127:
1.1.1.10! root 128: Log_Printf(LOG_DEBUG, "Building CPU function table (%d %d %d).\n",
! 129: cpu_level, cpu_compatible, address_space_24);
1.1 root 130:
131: for (opcode = 0; opcode < 65536; opcode++)
1.1.1.6 root 132: cpufunctbl[opcode] = op_illg_1;
1.1 root 133: for (i = 0; tbl[i].handler != NULL; i++) {
134: if (! tbl[i].specific)
1.1.1.6 root 135: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 136: }
137: for (opcode = 0; opcode < 65536; opcode++) {
138: cpuop_func *f;
139:
140: if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level)
141: continue;
142:
143: if (table68k[opcode].handler != -1) {
1.1.1.6 root 144: f = cpufunctbl[table68k[opcode].handler];
1.1 root 145: if (f == op_illg_1)
146: abort();
1.1.1.6 root 147: cpufunctbl[opcode] = f;
1.1 root 148: }
149: }
150: for (i = 0; tbl[i].handler != NULL; i++) {
151: if (tbl[i].specific)
1.1.1.6 root 152: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 153: }
154:
1.1.1.6 root 155: /* Hatari's illegal opcodes: */
156: cpufunctbl[GEMDOS_OPCODE] = OpCode_GemDos;
1.1.1.7 root 157: cpufunctbl[SYSINIT_OPCODE] = OpCode_SysInit;
1.1.1.6 root 158: cpufunctbl[VDI_OPCODE] = OpCode_VDI;
1.1 root 159: }
160:
161:
162:
163: void init_m68k (void)
164: {
165: int i;
166:
167: for (i = 0 ; i < 256 ; i++) {
168: int j;
169: for (j = 0 ; j < 8 ; j++) {
170: if (i & (1 << j)) break;
171: }
172: movem_index1[i] = j;
173: movem_index2[i] = 7-j;
174: movem_next[i] = i & (~(1 << j));
175: }
176: for (i = 0 ; i < 256 ; i++) {
177: int j;
178: for (j = 7 ; j >= 0 ; j--) {
179: if (i & (1 << j)) break;
180: }
181: fpp_movem_index1[i] = 7-j;
182: fpp_movem_index2[i] = j;
183: fpp_movem_next[i] = i & (~(1 << j));
184: }
185: #if COUNT_INSTRS
186: {
187: FILE *f = fopen (icountfilename (), "r");
188: memset (instrcount, 0, sizeof instrcount);
189: if (f) {
190: uae_u32 opcode, count, total;
191: char name[20];
192: write_log ("Reading instruction count file...\n");
193: fscanf (f, "Total: %lu\n", &total);
194: while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
195: instrcount[opcode] = count;
196: }
197: fclose(f);
198: }
199: }
200: #endif
201: write_log ("Building CPU table for configuration: 68");
202: if (address_space_24 && cpu_level > 1)
203: write_log ("EC");
204: switch (cpu_level) {
205: case 1:
206: write_log ("010");
207: break;
208: case 2:
209: write_log ("020");
210: break;
211: case 3:
212: write_log ("020/881");
213: break;
214: case 4:
215: /* Who is going to miss the MMU anyway...? :-) */
216: write_log ("040");
217: break;
218: default:
219: write_log ("000");
220: break;
221: }
222: if (cpu_compatible)
223: write_log (" (compatible mode)");
224: write_log ("\n");
1.1.1.7 root 225:
1.1 root 226: read_table68k ();
227: do_merges ();
228:
1.1.1.10! root 229: Log_Printf(LOG_DEBUG, "%d CPU functions\n", nr_cpuop_funcs);
1.1 root 230:
231: build_cpufunctbl ();
232: }
233:
1.1.1.4 root 234:
1.1.1.8 root 235: /* not used ATM:
1.1 root 236: static struct regstruct regs_backup[16];
237: static int backup_pointer = 0;
1.1.1.10! root 238: struct regstruct lastint_regs;
! 239: int lastint_no;
1.1.1.8 root 240: */
1.1.1.10! root 241: struct regstruct regs;
1.1 root 242: static long int m68kpc_offset;
1.1.1.10! root 243:
1.1 root 244:
245: #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
246: #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
247: #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
248:
249: uae_s32 ShowEA (FILE *f, int reg, amodes mode, wordsizes size, char *buf)
250: {
251: uae_u16 dp;
252: uae_s8 disp8;
253: uae_s16 disp16;
254: int r;
255: uae_u32 dispreg;
256: uaecptr addr;
257: uae_s32 offset = 0;
258: char buffer[80];
259:
260: switch (mode){
261: case Dreg:
262: sprintf (buffer,"D%d", reg);
263: break;
264: case Areg:
265: sprintf (buffer,"A%d", reg);
266: break;
267: case Aind:
268: sprintf (buffer,"(A%d)", reg);
269: break;
270: case Aipi:
271: sprintf (buffer,"(A%d)+", reg);
272: break;
273: case Apdi:
274: sprintf (buffer,"-(A%d)", reg);
275: break;
276: case Ad16:
277: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
278: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
279: sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
280: (unsigned long)addr);
281: break;
282: case Ad8r:
283: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
284: disp8 = dp & 0xFF;
285: r = (dp & 0x7000) >> 12;
286: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
287: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
288: dispreg <<= (dp >> 9) & 3;
289:
290: if (dp & 0x100) {
291: uae_s32 outer = 0, disp = 0;
292: uae_s32 base = m68k_areg(regs,reg);
293: char name[10];
294: sprintf (name,"A%d, ",reg);
295: if (dp & 0x80) { base = 0; name[0] = 0; }
296: if (dp & 0x40) dispreg = 0;
297: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
298: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
299: base += disp;
300:
301: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
302: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
303:
304: if (!(dp & 4)) base += dispreg;
305: if (dp & 3) base = get_long (base);
306: if (dp & 4) base += dispreg;
307:
308: addr = base + outer;
309: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
310: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
311: 1 << ((dp >> 9) & 3),
1.1.1.5 root 312: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 313: } else {
314: addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
315: sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
316: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
317: 1 << ((dp >> 9) & 3), disp8,
318: (unsigned long)addr);
319: }
320: break;
321: case PC16:
322: addr = m68k_getpc () + m68kpc_offset;
323: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
324: addr += (uae_s16)disp16;
325: sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
326: break;
327: case PC8r:
328: addr = m68k_getpc () + m68kpc_offset;
329: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
330: disp8 = dp & 0xFF;
331: r = (dp & 0x7000) >> 12;
332: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
333: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
334: dispreg <<= (dp >> 9) & 3;
335:
336: if (dp & 0x100) {
337: uae_s32 outer = 0,disp = 0;
338: uae_s32 base = addr;
339: char name[10];
340: sprintf (name,"PC, ");
341: if (dp & 0x80) { base = 0; name[0] = 0; }
342: if (dp & 0x40) dispreg = 0;
343: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
344: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
345: base += disp;
346:
347: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
348: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
349:
350: if (!(dp & 4)) base += dispreg;
351: if (dp & 3) base = get_long (base);
352: if (dp & 4) base += dispreg;
353:
354: addr = base + outer;
355: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
356: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
357: 1 << ((dp >> 9) & 3),
1.1.1.5 root 358: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 359: } else {
360: addr += (uae_s32)((uae_s8)disp8) + dispreg;
361: sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
362: (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
363: disp8, (unsigned long)addr);
364: }
365: break;
366: case absw:
367: sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
368: m68kpc_offset += 2;
369: break;
370: case absl:
371: sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
372: m68kpc_offset += 4;
373: break;
374: case imm:
375: switch (size){
376: case sz_byte:
377: sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
378: m68kpc_offset += 2;
379: break;
380: case sz_word:
381: sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
382: m68kpc_offset += 2;
383: break;
384: case sz_long:
385: sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
386: m68kpc_offset += 4;
387: break;
388: default:
389: break;
390: }
391: break;
392: case imm0:
393: offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
394: m68kpc_offset += 2;
395: sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
396: break;
397: case imm1:
398: offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
399: m68kpc_offset += 2;
400: sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
401: break;
402: case imm2:
403: offset = (uae_s32)get_ilong_1 (m68kpc_offset);
404: m68kpc_offset += 4;
405: sprintf (buffer,"#$%08lx", (unsigned long)offset);
406: break;
407: case immi:
408: offset = (uae_s32)(uae_s8)(reg & 0xff);
409: sprintf (buffer,"#$%08lx", (unsigned long)offset);
410: break;
411: default:
412: break;
413: }
414: if (buf == 0)
415: fprintf (f, "%s", buffer);
416: else
417: strcat (buf, buffer);
418: return offset;
419: }
420:
1.1.1.8 root 421:
1.1 root 422: /* The plan is that this will take over the job of exception 3 handling -
423: * the CPU emulation functions will just do a longjmp to m68k_go whenever
424: * they hit an odd address. */
1.1.1.8 root 425: #if 0
1.1 root 426: static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
427: {
428: uae_u16 dp;
429: uae_s8 disp8;
430: uae_s16 disp16;
431: int r;
432: uae_u32 dispreg;
433: uaecptr addr;
1.1.1.5 root 434: /*uae_s32 offset = 0;*/
1.1 root 435:
436: switch (mode){
437: case Dreg:
438: *val = m68k_dreg (regs, reg);
439: return 1;
440: case Areg:
441: *val = m68k_areg (regs, reg);
442: return 1;
443:
444: case Aind:
445: case Aipi:
446: addr = m68k_areg (regs, reg);
447: break;
448: case Apdi:
449: addr = m68k_areg (regs, reg);
450: break;
451: case Ad16:
452: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
453: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
454: break;
455: case Ad8r:
456: addr = m68k_areg (regs, reg);
457: d8r_common:
458: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
459: disp8 = dp & 0xFF;
460: r = (dp & 0x7000) >> 12;
461: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
462: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
463: dispreg <<= (dp >> 9) & 3;
464:
465: if (dp & 0x100) {
466: uae_s32 outer = 0, disp = 0;
467: uae_s32 base = addr;
468: if (dp & 0x80) base = 0;
469: if (dp & 0x40) dispreg = 0;
470: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
471: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
472: base += disp;
473:
474: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
475: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
476:
477: if (!(dp & 4)) base += dispreg;
478: if (dp & 3) base = get_long (base);
479: if (dp & 4) base += dispreg;
480:
481: addr = base + outer;
482: } else {
483: addr += (uae_s32)((uae_s8)disp8) + dispreg;
484: }
485: break;
486: case PC16:
487: addr = m68k_getpc () + m68kpc_offset;
488: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
489: addr += (uae_s16)disp16;
490: break;
491: case PC8r:
492: addr = m68k_getpc () + m68kpc_offset;
493: goto d8r_common;
494: case absw:
495: addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
496: m68kpc_offset += 2;
497: break;
498: case absl:
499: addr = get_ilong_1 (m68kpc_offset);
500: m68kpc_offset += 4;
501: break;
502: case imm:
503: switch (size){
504: case sz_byte:
505: *val = get_iword_1 (m68kpc_offset) & 0xff;
506: m68kpc_offset += 2;
507: break;
508: case sz_word:
509: *val = get_iword_1 (m68kpc_offset) & 0xffff;
510: m68kpc_offset += 2;
511: break;
512: case sz_long:
513: *val = get_ilong_1 (m68kpc_offset);
514: m68kpc_offset += 4;
515: break;
516: default:
517: break;
518: }
519: return 1;
520: case imm0:
521: *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
522: m68kpc_offset += 2;
523: return 1;
524: case imm1:
525: *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
526: m68kpc_offset += 2;
527: return 1;
528: case imm2:
529: *val = get_ilong_1 (m68kpc_offset);
530: m68kpc_offset += 4;
531: return 1;
532: case immi:
533: *val = (uae_s32)(uae_s8)(reg & 0xff);
534: return 1;
535: default:
536: addr = 0;
537: break;
538: }
539: if ((addr & 1) == 0)
540: return 1;
541:
542: last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
543: last_fault_for_exception_3 = addr;
544: return 0;
545: }
1.1.1.8 root 546: #endif
547:
1.1 root 548:
549: uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
550: {
551: int reg = (dp >> 12) & 15;
552: uae_s32 regd = regs.regs[reg];
553: if ((dp & 0x800) == 0)
554: regd = (uae_s32)(uae_s16)regd;
555: regd <<= (dp >> 9) & 3;
556: if (dp & 0x100) {
557: uae_s32 outer = 0;
558: if (dp & 0x80) base = 0;
559: if (dp & 0x40) regd = 0;
560:
561: if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
562: if ((dp & 0x30) == 0x30) base += next_ilong();
563:
564: if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
565: if ((dp & 0x3) == 0x3) outer = next_ilong();
566:
567: if ((dp & 0x4) == 0) base += regd;
568: if (dp & 0x3) base = get_long (base);
569: if (dp & 0x4) base += regd;
570:
571: return base + outer;
572: } else {
573: return base + (uae_s32)((uae_s8)dp) + regd;
574: }
575: }
576:
577: uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
578: {
579: int reg = (dp >> 12) & 15;
580: uae_s32 regd = regs.regs[reg];
581: #if 1
582: if ((dp & 0x800) == 0)
583: regd = (uae_s32)(uae_s16)regd;
584: return base + (uae_s8)dp + regd;
585: #else
586: /* Branch-free code... benchmark this again now that
587: * things are no longer inline. */
588: uae_s32 regd16;
589: uae_u32 mask;
590: mask = ((dp & 0x800) >> 11) - 1;
591: regd16 = (uae_s32)(uae_s16)regd;
592: regd16 &= mask;
593: mask = ~mask;
594: base += (uae_s8)dp;
595: regd &= mask;
596: regd |= regd16;
597: return base + regd;
598: #endif
599: }
600:
1.1.1.8 root 601:
602: /* Create the Status Register from the flags */
1.1 root 603: void MakeSR (void)
604: {
605: #if 0
606: assert((regs.t1 & 1) == regs.t1);
607: assert((regs.t0 & 1) == regs.t0);
608: assert((regs.s & 1) == regs.s);
609: assert((regs.m & 1) == regs.m);
610: assert((XFLG & 1) == XFLG);
611: assert((NFLG & 1) == NFLG);
612: assert((ZFLG & 1) == ZFLG);
613: assert((VFLG & 1) == VFLG);
614: assert((CFLG & 1) == CFLG);
615: #endif
616: regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
617: | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
618: | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
619: | GET_CFLG);
620: }
621:
1.1.1.8 root 622:
623: /* Set up the flags from Status Register */
1.1 root 624: void MakeFromSR (void)
625: {
626: int oldm = regs.m;
627: int olds = regs.s;
628:
629: regs.t1 = (regs.sr >> 15) & 1;
630: regs.t0 = (regs.sr >> 14) & 1;
631: regs.s = (regs.sr >> 13) & 1;
632: regs.m = (regs.sr >> 12) & 1;
633: regs.intmask = (regs.sr >> 8) & 7;
634: SET_XFLG ((regs.sr >> 4) & 1);
635: SET_NFLG ((regs.sr >> 3) & 1);
636: SET_ZFLG ((regs.sr >> 2) & 1);
637: SET_VFLG ((regs.sr >> 1) & 1);
638: SET_CFLG (regs.sr & 1);
639: if (cpu_level >= 2) {
640: if (olds != regs.s) {
641: if (olds) {
642: if (oldm)
643: regs.msp = m68k_areg(regs, 7);
644: else
645: regs.isp = m68k_areg(regs, 7);
646: m68k_areg(regs, 7) = regs.usp;
647: } else {
648: regs.usp = m68k_areg(regs, 7);
649: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
650: }
651: } else if (olds && oldm != regs.m) {
652: if (oldm) {
653: regs.msp = m68k_areg(regs, 7);
654: m68k_areg(regs, 7) = regs.isp;
655: } else {
656: regs.isp = m68k_areg(regs, 7);
657: m68k_areg(regs, 7) = regs.msp;
658: }
659: }
660: } else {
661: if (olds != regs.s) {
662: if (olds) {
663: regs.isp = m68k_areg(regs, 7);
664: m68k_areg(regs, 7) = regs.usp;
665: } else {
666: regs.usp = m68k_areg(regs, 7);
667: m68k_areg(regs, 7) = regs.isp;
668: }
669: }
670: }
671:
1.1.1.8 root 672: /* Pending interrupts can occur again after a write to the SR: */
673: set_special (SPCFLAG_DOINT);
1.1 root 674: if (regs.t1 || regs.t0)
675: set_special (SPCFLAG_TRACE);
676: else
1.1.1.6 root 677: /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
678: SR-modifying instructions (including STOP). */
679: unset_special (SPCFLAG_TRACE);
1.1 root 680: }
681:
1.1.1.5 root 682:
1.1 root 683: void Exception(int nr, uaecptr oldpc)
684: {
685: uae_u32 currpc = m68k_getpc ();
686:
1.1.1.2 root 687: /*if( nr>=2 && nr<10 ) fprintf(stderr,"Exception (-> %i bombs)!\n",nr);*/
1.1 root 688:
1.1.1.7 root 689: /* Intercept VDI exception (Trap #2 with D0 = 0x73) */
690: if(bUseVDIRes && nr == 0x22 && regs.regs[0] == 0x73)
1.1.1.5 root 691: {
1.1.1.6 root 692: if(!VDI())
1.1.1.5 root 693: {
1.1.1.6 root 694: /* Set 'PC' as address of 'VDI_OPCODE' illegal instruction
695: * This will call OpCode_VDI after completion of Trap call!
696: * Use to modify return structure from VDI */
697: VDI_OldPC = currpc;
698: currpc = CART_VDI_OPCODE_ADDR;
1.1.1.5 root 699: }
700: }
701:
1.1.1.8 root 702: #if 0
703: /* Intercept BIOS or XBIOS trap (Trap #13 or #14) */
704: if (nr == 0x2d)
705: {
706: /* Intercept BIOS calls */
707: if (Bios()) return;
708: }
709: else if (nr == 0x2e)
710: {
711: /* Intercept XBIOS calls */
712: if (XBios()) return;
713: }
714: #endif
715:
1.1 root 716: MakeSR();
717:
1.1.1.8 root 718: /* Change to supervisor mode if necessary */
1.1 root 719: if (!regs.s) {
720: regs.usp = m68k_areg(regs, 7);
721: if (cpu_level >= 2)
722: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
723: else
724: m68k_areg(regs, 7) = regs.isp;
725: regs.s = 1;
726: }
1.1.1.8 root 727:
728: /* Build additional exception stack frame for 68010 and higher */
1.1 root 729: if (cpu_level > 0) {
730: if (nr == 2 || nr == 3) {
731: int i;
732: /* @@@ this is probably wrong (?) */
733: for (i = 0 ; i < 12 ; i++) {
734: m68k_areg(regs, 7) -= 2;
735: put_word (m68k_areg(regs, 7), 0);
736: }
737: m68k_areg(regs, 7) -= 2;
738: put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
739: } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
740: m68k_areg(regs, 7) -= 4;
741: put_long (m68k_areg(regs, 7), oldpc);
742: m68k_areg(regs, 7) -= 2;
743: put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
744: } else if (regs.m && nr >= 24 && nr < 32) {
745: m68k_areg(regs, 7) -= 2;
746: put_word (m68k_areg(regs, 7), nr * 4);
747: m68k_areg(regs, 7) -= 4;
748: put_long (m68k_areg(regs, 7), currpc);
749: m68k_areg(regs, 7) -= 2;
750: put_word (m68k_areg(regs, 7), regs.sr);
751: regs.sr |= (1 << 13);
752: regs.msp = m68k_areg(regs, 7);
753: m68k_areg(regs, 7) = regs.isp;
754: m68k_areg(regs, 7) -= 2;
755: put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
756: } else {
757: m68k_areg(regs, 7) -= 2;
758: put_word (m68k_areg(regs, 7), nr * 4);
759: }
760: }
1.1.1.3 root 761:
762: /* Push PC on stack: */
1.1 root 763: m68k_areg(regs, 7) -= 4;
764: put_long (m68k_areg(regs, 7), currpc);
1.1.1.3 root 765: /* Push SR on stack: */
1.1 root 766: m68k_areg(regs, 7) -= 2;
767: put_word (m68k_areg(regs, 7), regs.sr);
1.1.1.3 root 768:
769: /* 68000 bus/address errors: */
770: if (cpu_level==0 && (nr==2 || nr==3)) {
1.1.1.8 root 771: uae_u16 specialstatus = 0x2001;
772: /* Special status word emulation isn't perfect yet... :-( */
773: if (regs.sr & 0x2000)
774: specialstatus |= 0x4;
1.1.1.3 root 775: m68k_areg(regs, 7) -= 8;
776: if (nr == 3) { /* Address error */
1.1.1.8 root 777: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.3 root 778: put_long (m68k_areg(regs, 7)+2, last_fault_for_exception_3);
779: put_word (m68k_areg(regs, 7)+6, last_op_for_exception_3);
780: put_long (m68k_areg(regs, 7)+10, last_addr_for_exception_3);
1.1.1.8 root 781: if (bEnableDebug) {
782: fprintf(stderr,"Address Error at address $%x, PC=$%x\n",last_fault_for_exception_3,currpc);
783: DebugUI();
784: }
1.1.1.3 root 785: }
1.1.1.8 root 786: else { /* Bus error */
787: if (bBusErrorReadWrite)
788: specialstatus |= 0x10;
789: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.10! root 790: put_long (m68k_areg(regs, 7)+2, BusErrorAddress);
1.1.1.8 root 791: put_word (m68k_areg(regs, 7)+6, get_word(BusErrorPC)); /* Opcode */
792: /* Check for double bus errors: */
793: if (regs.spcflags & SPCFLAG_BUSERROR) {
794: fprintf(stderr, "Detected double bus error at address $%x, PC=$%lx => CPU halted!\n",
1.1.1.10! root 795: BusErrorAddress, (long)currpc);
1.1.1.8 root 796: unset_special(SPCFLAG_BUSERROR);
797: if (bEnableDebug)
798: DebugUI();
799: regs.intmask = 7;
800: m68k_setstopped(TRUE);
801: return;
802: }
1.1.1.10! root 803: if (bEnableDebug && BusErrorAddress!=0xff8a00) {
! 804: fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n", BusErrorAddress, (long)currpc);
1.1.1.8 root 805: DebugUI();
806: }
807: }
1.1.1.3 root 808: }
809:
1.1.1.8 root 810: /* Set PC and flags */
811: if (bEnableDebug && get_long (regs.vbr + 4*nr) == 0) {
812: write_log("Uninitialized exception handler #%i!\n", nr);
813: }
1.1 root 814: m68k_setpc (get_long (regs.vbr + 4*nr));
815: fill_prefetch_0 ();
816: regs.t1 = regs.t0 = regs.m = 0;
817: unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
1.1.1.6 root 818:
1.1.1.7 root 819: /* Handle exception cycles: */
820: if(nr >= 24 && nr <= 31)
821: {
1.1.1.8 root 822: M68000_AddCycles(44+4); /* Interrupt */
1.1.1.7 root 823: }
824: else if(nr >= 32 && nr <= 47)
825: {
1.1.1.8 root 826: M68000_AddCycles(34); /* Trap */
1.1.1.7 root 827: }
828: else switch(nr)
829: {
1.1.1.8 root 830: case 2: M68000_AddCycles(50); break; /* Bus error */
831: case 3: M68000_AddCycles(50); break; /* Address error */
832: case 4: M68000_AddCycles(34); break; /* Illegal instruction */
833: case 5: M68000_AddCycles(38); break; /* Div by zero */
834: case 6: M68000_AddCycles(40); break; /* CHK */
835: case 7: M68000_AddCycles(34); break; /* TRAPV */
836: case 8: M68000_AddCycles(34); break; /* Privilege violation */
837: case 9: M68000_AddCycles(34); break; /* Trace */
838: case 10: M68000_AddCycles(34); break; /* Line-A - probably wrong */
839: case 11: M68000_AddCycles(34); break; /* Line-F - probably wrong */
1.1.1.7 root 840: default:
1.1.1.8 root 841: /* FIXME: Add right cycles value for MFP interrupts and copro exceptions ... */
1.1.1.7 root 842: if(nr < 64)
1.1.1.8 root 843: M68000_AddCycles(4); /* Coprocessor and unassigned exceptions (???) */
1.1.1.7 root 844: else
1.1.1.8 root 845: M68000_AddCycles(24); /* Must be a MFP interrupt */
1.1.1.7 root 846: break;
1.1.1.6 root 847: }
1.1 root 848: }
849:
1.1.1.7 root 850:
1.1 root 851: static void Interrupt(int nr)
852: {
853: assert(nr < 8 && nr >= 0);
1.1.1.10! root 854: /*lastint_regs = regs;*/
! 855: /*lastint_no = nr;*/
1.1 root 856: Exception(nr+24, 0);
857:
858: regs.intmask = nr;
859: set_special (SPCFLAG_INT);
860: }
861:
1.1.1.7 root 862:
1.1.1.8 root 863: uae_u32 reg_caar, reg_cacr;
864: static uae_u32 itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp;
1.1 root 865:
1.1.1.7 root 866:
1.1 root 867: int m68k_move2c (int regno, uae_u32 *regp)
868: {
869: if ((cpu_level == 1 && (regno & 0x7FF) > 1)
870: || (cpu_level < 4 && (regno & 0x7FF) > 2)
871: || (cpu_level == 4 && regno == 0x802))
872: {
873: op_illg (0x4E7B);
874: return 0;
875: } else {
876: switch (regno) {
877: case 0: regs.sfc = *regp & 7; break;
878: case 1: regs.dfc = *regp & 7; break;
1.1.1.8 root 879: case 2: reg_cacr = *regp & (cpu_level < 4 ? 0x3 : 0x80008000); break;
1.1 root 880: case 3: tc = *regp & 0xc000; break;
881: /* Mask out fields that should be zero. */
882: case 4: itt0 = *regp & 0xffffe364; break;
883: case 5: itt1 = *regp & 0xffffe364; break;
884: case 6: dtt0 = *regp & 0xffffe364; break;
885: case 7: dtt1 = *regp & 0xffffe364; break;
1.1.1.7 root 886:
1.1 root 887: case 0x800: regs.usp = *regp; break;
888: case 0x801: regs.vbr = *regp; break;
1.1.1.8 root 889: case 0x802: reg_caar = *regp & 0xfc; break;
1.1 root 890: case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
891: case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
1.1.1.6 root 892: case 0x805: mmusr = *regp; break;
893: case 0x806: urp = *regp; break;
894: case 0x807: srp = *regp; break;
1.1 root 895: default:
896: op_illg (0x4E7B);
897: return 0;
898: }
899: }
900: return 1;
901: }
902:
903: int m68k_movec2 (int regno, uae_u32 *regp)
904: {
905: if ((cpu_level == 1 && (regno & 0x7FF) > 1)
906: || (cpu_level < 4 && (regno & 0x7FF) > 2)
907: || (cpu_level == 4 && regno == 0x802))
908: {
909: op_illg (0x4E7A);
910: return 0;
911: } else {
912: switch (regno) {
913: case 0: *regp = regs.sfc; break;
914: case 1: *regp = regs.dfc; break;
1.1.1.8 root 915: case 2: *regp = reg_cacr; break;
1.1 root 916: case 3: *regp = tc; break;
917: case 4: *regp = itt0; break;
918: case 5: *regp = itt1; break;
919: case 6: *regp = dtt0; break;
920: case 7: *regp = dtt1; break;
921: case 0x800: *regp = regs.usp; break;
922: case 0x801: *regp = regs.vbr; break;
1.1.1.8 root 923: case 0x802: *regp = reg_caar; break;
1.1 root 924: case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
925: case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
926: case 0x805: *regp = mmusr; break;
1.1.1.6 root 927: case 0x806: *regp = urp; break;
928: case 0x807: *regp = srp; break;
1.1 root 929: default:
930: op_illg (0x4E7A);
931: return 0;
932: }
933: }
934: return 1;
935: }
936:
937: STATIC_INLINE int
1.1.1.10! root 938: div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 ndiv, uae_u32 *quot, uae_u32 *rem)
1.1 root 939: {
940: uae_u32 q = 0, cbit = 0;
941: int i;
942:
1.1.1.10! root 943: if (ndiv <= src_hi) {
1.1 root 944: return 1;
945: }
946: for (i = 0 ; i < 32 ; i++) {
947: cbit = src_hi & 0x80000000ul;
948: src_hi <<= 1;
949: if (src_lo & 0x80000000ul) src_hi++;
950: src_lo <<= 1;
951: q = q << 1;
1.1.1.10! root 952: if (cbit || ndiv <= src_hi) {
1.1 root 953: q |= 1;
1.1.1.10! root 954: src_hi -= ndiv;
1.1 root 955: }
956: }
957: *quot = q;
958: *rem = src_hi;
959: return 0;
960: }
961:
962: void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
963: {
964: #if defined(uae_s64)
965: if (src == 0) {
966: Exception (5, oldpc);
967: return;
968: }
969: if (extra & 0x800) {
970: /* signed variant */
971: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
972: uae_s64 quot, rem;
973:
974: if (extra & 0x400) {
975: a &= 0xffffffffu;
976: a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
977: }
978: rem = a % (uae_s64)(uae_s32)src;
979: quot = a / (uae_s64)(uae_s32)src;
980: if ((quot & UVAL64(0xffffffff80000000)) != 0
981: && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
982: {
983: SET_VFLG (1);
984: SET_NFLG (1);
985: SET_CFLG (0);
986: } else {
987: if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
988: SET_VFLG (0);
989: SET_CFLG (0);
990: SET_ZFLG (((uae_s32)quot) == 0);
991: SET_NFLG (((uae_s32)quot) < 0);
992: m68k_dreg(regs, extra & 7) = rem;
993: m68k_dreg(regs, (extra >> 12) & 7) = quot;
994: }
995: } else {
996: /* unsigned */
997: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
998: uae_u64 quot, rem;
999:
1000: if (extra & 0x400) {
1001: a &= 0xffffffffu;
1002: a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
1003: }
1004: rem = a % (uae_u64)src;
1005: quot = a / (uae_u64)src;
1006: if (quot > 0xffffffffu) {
1007: SET_VFLG (1);
1008: SET_NFLG (1);
1009: SET_CFLG (0);
1010: } else {
1011: SET_VFLG (0);
1012: SET_CFLG (0);
1013: SET_ZFLG (((uae_s32)quot) == 0);
1014: SET_NFLG (((uae_s32)quot) < 0);
1015: m68k_dreg(regs, extra & 7) = rem;
1016: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1017: }
1018: }
1019: #else
1020: if (src == 0) {
1021: Exception (5, oldpc);
1022: return;
1023: }
1024: if (extra & 0x800) {
1025: /* signed variant */
1026: uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1027: uae_s32 hi = lo < 0 ? -1 : 0;
1028: uae_s32 save_high;
1029: uae_u32 quot, rem;
1030: uae_u32 sign;
1031:
1032: if (extra & 0x400) {
1033: hi = (uae_s32)m68k_dreg(regs, extra & 7);
1034: }
1035: save_high = hi;
1036: sign = (hi ^ src);
1037: if (hi < 0) {
1038: hi = ~hi;
1039: lo = -lo;
1040: if (lo == 0) hi++;
1041: }
1042: if ((uae_s32)src < 0) src = -src;
1043: if (div_unsigned(hi, lo, src, ", &rem) ||
1044: (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
1045: SET_VFLG (1);
1046: SET_NFLG (1);
1047: SET_CFLG (0);
1048: } else {
1049: if (sign & 0x80000000) quot = -quot;
1050: if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
1051: SET_VFLG (0);
1052: SET_CFLG (0);
1053: SET_ZFLG (((uae_s32)quot) == 0);
1054: SET_NFLG (((uae_s32)quot) < 0);
1055: m68k_dreg(regs, extra & 7) = rem;
1056: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1057: }
1058: } else {
1059: /* unsigned */
1060: uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1061: uae_u32 hi = 0;
1062: uae_u32 quot, rem;
1063:
1064: if (extra & 0x400) {
1065: hi = (uae_u32)m68k_dreg(regs, extra & 7);
1066: }
1067: if (div_unsigned(hi, lo, src, ", &rem)) {
1068: SET_VFLG (1);
1069: SET_NFLG (1);
1070: SET_CFLG (0);
1071: } else {
1072: SET_VFLG (0);
1073: SET_CFLG (0);
1074: SET_ZFLG (((uae_s32)quot) == 0);
1075: SET_NFLG (((uae_s32)quot) < 0);
1076: m68k_dreg(regs, extra & 7) = rem;
1077: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1078: }
1079: }
1080: #endif
1081: }
1082:
1083: STATIC_INLINE void
1084: mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1085: {
1086: uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1087: uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1088: uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1089: uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1090: uae_u32 lo;
1091:
1092: lo = r0 + ((r1 << 16) & 0xffff0000ul);
1093: if (lo < r0) r3++;
1094: r0 = lo;
1095: lo = r0 + ((r2 << 16) & 0xffff0000ul);
1096: if (lo < r0) r3++;
1097: r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1098: *dst_lo = lo;
1099: *dst_hi = r3;
1100: }
1101:
1102: void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1103: {
1104: #if defined(uae_s64)
1105: if (extra & 0x800) {
1106: /* signed variant */
1107: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1108:
1109: a *= (uae_s64)(uae_s32)src;
1110: SET_VFLG (0);
1111: SET_CFLG (0);
1112: SET_ZFLG (a == 0);
1113: SET_NFLG (a < 0);
1114: if (extra & 0x400)
1115: m68k_dreg(regs, extra & 7) = a >> 32;
1116: else if ((a & UVAL64(0xffffffff80000000)) != 0
1117: && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1118: {
1119: SET_VFLG (1);
1120: }
1121: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1122: } else {
1123: /* unsigned */
1124: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1125:
1126: a *= (uae_u64)src;
1127: SET_VFLG (0);
1128: SET_CFLG (0);
1129: SET_ZFLG (a == 0);
1130: SET_NFLG (((uae_s64)a) < 0);
1131: if (extra & 0x400)
1132: m68k_dreg(regs, extra & 7) = a >> 32;
1133: else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1134: SET_VFLG (1);
1135: }
1136: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1137: }
1138: #else
1139: if (extra & 0x800) {
1140: /* signed variant */
1141: uae_s32 src1,src2;
1142: uae_u32 dst_lo,dst_hi;
1143: uae_u32 sign;
1144:
1145: src1 = (uae_s32)src;
1146: src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1147: sign = (src1 ^ src2);
1148: if (src1 < 0) src1 = -src1;
1149: if (src2 < 0) src2 = -src2;
1150: mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1151: if (sign & 0x80000000) {
1152: dst_hi = ~dst_hi;
1153: dst_lo = -dst_lo;
1154: if (dst_lo == 0) dst_hi++;
1155: }
1156: SET_VFLG (0);
1157: SET_CFLG (0);
1158: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1159: SET_NFLG (((uae_s32)dst_hi) < 0);
1160: if (extra & 0x400)
1161: m68k_dreg(regs, extra & 7) = dst_hi;
1162: else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1163: && ((dst_hi & 0xffffffff) != 0xffffffff
1164: || (dst_lo & 0x80000000) != 0x80000000))
1165: {
1166: SET_VFLG (1);
1167: }
1168: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1169: } else {
1170: /* unsigned */
1171: uae_u32 dst_lo,dst_hi;
1172:
1173: mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1174:
1175: SET_VFLG (0);
1176: SET_CFLG (0);
1177: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1178: SET_NFLG (((uae_s32)dst_hi) < 0);
1179: if (extra & 0x400)
1180: m68k_dreg(regs, extra & 7) = dst_hi;
1181: else if (dst_hi != 0) {
1182: SET_VFLG (1);
1183: }
1184: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1185: }
1186: #endif
1187: }
1.1.1.6 root 1188:
1.1 root 1189:
1190: void m68k_reset (void)
1191: {
1192: regs.s = 1;
1193: regs.m = 0;
1194: regs.stopped = 0;
1195: regs.t1 = 0;
1196: regs.t0 = 0;
1197: SET_ZFLG (0);
1198: SET_XFLG (0);
1199: SET_CFLG (0);
1200: SET_VFLG (0);
1201: SET_NFLG (0);
1.1.1.7 root 1202: regs.spcflags &= SPCFLAG_MODE_CHANGE; /* Clear specialflags except mode-change */
1.1 root 1203: regs.intmask = 7;
1204: regs.vbr = regs.sfc = regs.dfc = 0;
1205: regs.fpcr = regs.fpsr = regs.fpiar = 0;
1.1.1.7 root 1206:
1207: m68k_areg(regs, 7) = get_long(0);
1208: m68k_setpc(get_long(4));
1209: refill_prefetch (m68k_getpc(), 0);
1.1 root 1210: }
1211:
1.1.1.8 root 1212:
1.1 root 1213: unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1214: {
1.1.1.8 root 1215: #if 0
1.1 root 1216: uaecptr pc = m68k_getpc ();
1.1.1.8 root 1217: #endif
1.1.1.6 root 1218: if ((opcode & 0xF000) == 0xF000) {
1.1 root 1219: Exception(0xB,0);
1220: return 4;
1.1.1.6 root 1221: }
1222: if ((opcode & 0xF000) == 0xA000) {
1.1 root 1223: Exception(0xA,0);
1224: return 4;
1.1.1.6 root 1225: }
1.1.1.3 root 1226: #if 0
1.1.1.6 root 1227: write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc);
1.1 root 1228: #endif
1229: Exception (4,0);
1230: return 4;
1231: }
1232:
1.1.1.8 root 1233:
1.1 root 1234: void mmu_op(uae_u32 opcode, uae_u16 extra)
1235: {
1236: if ((opcode & 0xFE0) == 0x0500) {
1237: /* PFLUSH */
1238: mmusr = 0;
1239: write_log ("PFLUSH\n");
1240: } else if ((opcode & 0x0FD8) == 0x548) {
1241: /* PTEST */
1242: write_log ("PTEST\n");
1243: } else
1244: op_illg (opcode);
1245: }
1246:
1247:
1248: static uaecptr last_trace_ad = 0;
1249:
1250: static void do_trace (void)
1251: {
1252: if (regs.t0 && cpu_level >= 2) {
1253: uae_u16 opcode;
1254: /* should also include TRAP, CHK, SR modification FPcc */
1255: /* probably never used so why bother */
1256: /* We can afford this to be inefficient... */
1257: m68k_setpc (m68k_getpc ());
1258: fill_prefetch_0 ();
1259: opcode = get_word (regs.pc);
1260: if (opcode == 0x4e72 /* RTE */
1261: || opcode == 0x4e74 /* RTD */
1262: || opcode == 0x4e75 /* RTS */
1263: || opcode == 0x4e77 /* RTR */
1264: || opcode == 0x4e76 /* TRAPV */
1265: || (opcode & 0xffc0) == 0x4e80 /* JSR */
1266: || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1267: || (opcode & 0xff00) == 0x6100 /* BSR */
1268: || ((opcode & 0xf000) == 0x6000 /* Bcc */
1269: && cctrue((opcode >> 8) & 0xf))
1270: || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1271: && !cctrue((opcode >> 8) & 0xf)
1272: && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1273: {
1274: last_trace_ad = m68k_getpc ();
1275: unset_special (SPCFLAG_TRACE);
1276: set_special (SPCFLAG_DOTRACE);
1277: }
1278: } else if (regs.t1) {
1279: last_trace_ad = m68k_getpc ();
1280: unset_special (SPCFLAG_TRACE);
1281: set_special (SPCFLAG_DOTRACE);
1282: }
1283: }
1284:
1285:
1.1.1.8 root 1286: /*
1287: * Handle special flags
1288: */
1.1 root 1289: static int do_specialties (void)
1290: {
1.1.1.7 root 1291: if(regs.spcflags & SPCFLAG_BUSERROR) {
1292: /* We can not execute bus errors directly in the memory handler
1293: * functions since the PC should point to the address of the next
1294: * instruction, so we're executing the bus errors here: */
1.1.1.8 root 1295: unset_special(SPCFLAG_BUSERROR);
1.1.1.7 root 1296: Exception(2,0);
1297: }
1298:
1.1.1.8 root 1299: if(regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1300: /* Add some extra cycles to simulate a wait state */
1301: unset_special(SPCFLAG_EXTRA_CYCLES);
1302: M68000_AddCycles(4);
1303: }
1304:
1.1 root 1305: if (regs.spcflags & SPCFLAG_DOTRACE) {
1306: Exception (9,last_trace_ad);
1307: }
1.1.1.8 root 1308:
1.1 root 1309: while (regs.spcflags & SPCFLAG_STOP) {
1.1.1.8 root 1310: if (regs.intmask > 5) {
1311: /* We still have to care about events when IPL==7 ! */
1312: Main_EventHandler();
1313: if (regs.spcflags & SPCFLAG_BRK) return 1;
1314: }
1315: M68000_AddCycles(4);
1316: if (PendingInterruptCount<=0 && PendingInterruptFunction) {
1317: CALL_VAR(PendingInterruptFunction);
1318: }
1319: if (regs.spcflags & SPCFLAG_MFP) {
1320: MFP_CheckPendingInterrupts();
1321: }
1.1.1.5 root 1322: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1.1.1.6 root 1323: int intr = intlev ();
1.1 root 1324: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1.1.1.6 root 1325: if (intr != -1 && intr > regs.intmask) {
1.1 root 1326: Interrupt (intr);
1327: regs.stopped = 0;
1328: unset_special (SPCFLAG_STOP);
1.1.1.6 root 1329: }
1.1 root 1330: }
1331: }
1.1.1.8 root 1332:
1.1 root 1333: if (regs.spcflags & SPCFLAG_TRACE)
1334: do_trace ();
1335:
1336: if (regs.spcflags & SPCFLAG_DOINT) {
1.1.1.6 root 1337: int intr = intlev ();
1.1.1.8 root 1338: /* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */
1.1 root 1339: unset_special (SPCFLAG_DOINT);
1.1.1.6 root 1340: if (intr != -1 && intr > regs.intmask) {
1.1 root 1341: Interrupt (intr);
1342: regs.stopped = 0;
1.1.1.6 root 1343: }
1.1 root 1344: }
1345: if (regs.spcflags & SPCFLAG_INT) {
1346: unset_special (SPCFLAG_INT);
1347: set_special (SPCFLAG_DOINT);
1348: }
1.1.1.8 root 1349:
1350: if (regs.spcflags & SPCFLAG_MFP) { /* Check for MFP interrupts */
1351: MFP_CheckPendingInterrupts();
1352: }
1353:
1.1 root 1354: if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1.1.1.8 root 1355: unset_special(SPCFLAG_MODE_CHANGE);
1.1 root 1356: return 1;
1357: }
1.1.1.8 root 1358:
1.1 root 1359: return 0;
1360: }
1361:
1.1.1.3 root 1362:
1.1 root 1363: /* It's really sad to have two almost identical functions for this, but we
1364: do it all for performance... :( */
1365: static void m68k_run_1 (void)
1366: {
1367: #ifdef DEBUG_PREFETCH
1368: uae_u8 saved_bytes[20];
1369: uae_u16 *oldpcp;
1370: #endif
1.1.1.8 root 1371:
1372: for (;;) {
1.1 root 1373: int cycles;
1374: uae_u32 opcode = get_iword_prefetch (0);
1.1.1.8 root 1375:
1.1 root 1376: #ifdef DEBUG_PREFETCH
1377: if (get_ilong (0) != do_get_mem_long (®s.prefetch)) {
1378: fprintf (stderr, "Prefetch differs from memory.\n");
1379: debugging = 1;
1380: return;
1381: }
1382: oldpcp = regs.pc_p;
1383: memcpy (saved_bytes, regs.pc_p, 20);
1384: #endif
1385:
1386: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.3 root 1387: /*m68k_disasm(stderr, m68k_getpc (), NULL, 1);*/
1.1 root 1388:
1389: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1390: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1391: #if COUNT_INSTRS == 2
1392: if (table68k[opcode].handler != -1)
1393: instrcount[table68k[opcode].handler]++;
1394: #elif COUNT_INSTRS == 1
1395: instrcount[opcode]++;
1396: #endif
1.1.1.2 root 1397:
1.1.1.6 root 1398: cycles = (*cpufunctbl[opcode])(opcode);
1399:
1.1 root 1400: #ifdef DEBUG_PREFETCH
1401: if (memcmp (saved_bytes, oldpcp, 20) != 0) {
1402: fprintf (stderr, "Self-modifying code detected.\n");
1403: set_special (SPCFLAG_BRK);
1404: debugging = 1;
1405: }
1406: #endif
1.1.1.2 root 1407:
1.1.1.8 root 1408: M68000_AddCycles(cycles);
1409: if (PendingInterruptCount<=0 && PendingInterruptFunction)
1410: CALL_VAR(PendingInterruptFunction);
1411:
1.1 root 1412: if (regs.spcflags) {
1413: if (do_specialties ())
1414: return;
1415: }
1416: }
1417: }
1418:
1419:
1420: /* Same thing, but don't use prefetch to get opcode. */
1421: static void m68k_run_2 (void)
1422: {
1.1.1.8 root 1423: for (;;) {
1.1 root 1424: int cycles;
1425: uae_u32 opcode = get_iword (0);
1426:
1427: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.3 root 1428: /*m68k_disasm(stderr, m68k_getpc (), NULL, 1);*/
1.1 root 1429:
1430: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1431: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1432: #if COUNT_INSTRS == 2
1433: if (table68k[opcode].handler != -1)
1434: instrcount[table68k[opcode].handler]++;
1435: #elif COUNT_INSTRS == 1
1436: instrcount[opcode]++;
1437: #endif
1.1.1.2 root 1438:
1.1.1.6 root 1439: cycles = (*cpufunctbl[opcode])(opcode);
1440:
1.1.1.8 root 1441: M68000_AddCycles(cycles);
1442: if (PendingInterruptCount<=0 && PendingInterruptFunction)
1443: CALL_VAR(PendingInterruptFunction);
1444:
1.1 root 1445: if (regs.spcflags) {
1446: if (do_specialties ())
1447: return;
1448: }
1449: }
1450: }
1451:
1452:
1453: void m68k_go (int may_quit)
1454: {
1.1.1.8 root 1455: static int in_m68k_go = 0;
1456:
1.1 root 1457: if (in_m68k_go || !may_quit) {
1458: write_log ("Bug! m68k_go is not reentrant.\n");
1459: abort ();
1460: }
1461:
1462: in_m68k_go++;
1.1.1.8 root 1463: while (!(regs.spcflags & SPCFLAG_BRK)) {
1.1.1.2 root 1464: if(cpu_compatible)
1465: m68k_run_1();
1466: else
1467: m68k_run_2();
1.1 root 1468: }
1.1.1.8 root 1469: unset_special(SPCFLAG_BRK);
1.1 root 1470: in_m68k_go--;
1471: }
1472:
1.1.1.8 root 1473:
1474: /*
1.1 root 1475: static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1476: {
1477: uae_u32 opcode, val;
1478: struct instr *dp;
1479:
1480: opcode = get_iword_1(0);
1481: last_op_for_exception_3 = opcode;
1482: m68kpc_offset = 2;
1483:
1.1.1.6 root 1484: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1485: opcode = 0x4AFC;
1486: }
1487: dp = table68k + opcode;
1488:
1489: if (dp->suse) {
1490: if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) {
1491: Exception (3, 0);
1492: return;
1493: }
1494: }
1495: if (dp->duse) {
1496: if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) {
1497: Exception (3, 0);
1498: return;
1499: }
1500: }
1501: }
1.1.1.8 root 1502: */
1503:
1.1 root 1504:
1505: void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1506: {
1.1.1.8 root 1507: static const char* ccnames[] =
1508: { "T ","F ","HI","LS","CC","CS","NE","EQ",
1509: "VC","VS","PL","MI","GE","LT","GT","LE" };
1510:
1.1 root 1511: uaecptr newpc = 0;
1512: m68kpc_offset = addr - m68k_getpc ();
1513: while (cnt-- > 0) {
1514: char instrname[20],*ccpt;
1515: int opwords;
1516: uae_u32 opcode;
1517: struct mnemolookup *lookup;
1518: struct instr *dp;
1519: fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset);
1520: for (opwords = 0; opwords < 5; opwords++){
1521: fprintf (f, "%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1522: }
1523: opcode = get_iword_1 (m68kpc_offset);
1524: m68kpc_offset += 2;
1.1.1.6 root 1525: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1526: opcode = 0x4AFC;
1527: }
1528: dp = table68k + opcode;
1529: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1530: ;
1531:
1532: strcpy (instrname, lookup->name);
1533: ccpt = strstr (instrname, "cc");
1534: if (ccpt != 0) {
1535: strncpy (ccpt, ccnames[dp->cc], 2);
1536: }
1537: fprintf (f, "%s", instrname);
1538: switch (dp->size){
1539: case sz_byte: fprintf (f, ".B "); break;
1540: case sz_word: fprintf (f, ".W "); break;
1541: case sz_long: fprintf (f, ".L "); break;
1542: default: fprintf (f, " "); break;
1543: }
1544:
1545: if (dp->suse) {
1546: newpc = m68k_getpc () + m68kpc_offset;
1547: newpc += ShowEA (f, dp->sreg, dp->smode, dp->size, 0);
1548: }
1549: if (dp->suse && dp->duse)
1550: fprintf (f, ",");
1551: if (dp->duse) {
1552: newpc = m68k_getpc () + m68kpc_offset;
1553: newpc += ShowEA (f, dp->dreg, dp->dmode, dp->size, 0);
1554: }
1555: if (ccpt != 0) {
1556: if (cctrue(dp->cc))
1.1.1.5 root 1557: fprintf (f, " == %08lx (TRUE)", (long)newpc);
1.1 root 1558: else
1.1.1.5 root 1559: fprintf (f, " == %08lx (FALSE)", (long)newpc);
1.1 root 1560: } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1.1.1.5 root 1561: fprintf (f, " == %08lx", (long)newpc);
1.1 root 1562: fprintf (f, "\n");
1563: }
1564: if (nextpc)
1565: *nextpc = m68k_getpc () + m68kpc_offset;
1566: }
1567:
1568: void m68k_dumpstate (FILE *f, uaecptr *nextpc)
1569: {
1570: int i;
1571: for (i = 0; i < 8; i++){
1.1.1.5 root 1572: fprintf (f, "D%d: %08lx ", i, (long)m68k_dreg(regs, i));
1.1 root 1573: if ((i & 3) == 3) fprintf (f, "\n");
1574: }
1575: for (i = 0; i < 8; i++){
1.1.1.5 root 1576: fprintf (f, "A%d: %08lx ", i, (long)m68k_areg(regs, i));
1.1 root 1577: if ((i & 3) == 3) fprintf (f, "\n");
1578: }
1579: if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1580: if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1581: if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1582: fprintf (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1.1.1.5 root 1583: (long)regs.usp,(long)regs.isp,(long)regs.msp,(long)regs.vbr);
1.1 root 1584: fprintf (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1585: regs.t1, regs.t0, regs.s, regs.m,
1586: GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1587: for (i = 0; i < 8; i++){
1588: fprintf (f, "FP%d: %g ", i, regs.fp[i]);
1589: if ((i & 3) == 3) fprintf (f, "\n");
1590: }
1591: fprintf (f, "N=%d Z=%d I=%d NAN=%d\n",
1592: (regs.fpsr & 0x8000000) != 0,
1593: (regs.fpsr & 0x4000000) != 0,
1594: (regs.fpsr & 0x2000000) != 0,
1595: (regs.fpsr & 0x1000000) != 0);
1596: if (cpu_compatible)
1597: fprintf (f, "prefetch %08lx\n", (unsigned long)do_get_mem_long(®s.prefetch));
1598:
1599: m68k_disasm (f, m68k_getpc (), nextpc, 1);
1600: if (nextpc)
1.1.1.5 root 1601: fprintf (f, "next PC: %08lx\n", (long)*nextpc);
1.1 root 1602: }
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