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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation
5: *
6: * (c) 1995 Bernd Schmidt
1.1.1.2 root 7: *
8: * Adaptation to Hatari by Thomas Huth
9: *
1.1.1.6 root 10: * This file is distributed under the GNU Public License, version 2 or at
11: * your option any later version. Read the file gpl.txt for details.
1.1 root 12: */
1.1.1.12! root 13:
! 14:
! 15: /* 2007/11/12 [NP] Add HATARI_TRACE_CPU_DISASM. */
! 16: /* 2007/11/15 [NP] In MakeFromSR, writes to m and t0 should be ignored and set to 0 if cpu < 68020 */
! 17: /* 2007/11/26 [NP] We set BusErrorPC in m68k_run_1 instead of M68000_BusError, else the BusErrorPC */
! 18: /* will not point to the opcode that generated the bus error. */
! 19: /* Huge debug/work on Exceptions 2/3 stack frames, result is more accurate and */
! 20: /* allow to pass the very tricky Transbeauce 2 Demo's protection. */
! 21: /* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */
! 22: /* Cwik, [email protected]). */
! 23: /* 2007/12/06 [NP] The PC stored in the stack frame for the bus error is complex to emulate, */
! 24: /* because it doesn't necessarily point to the next instruction after the one that */
! 25: /* triggered the bus error. In the case of the Transbeauce 2 Demo, after */
! 26: /* 'move.l $0.w,$24.w', PC is incremented of 4 bytes, not 6, and stored in the */
! 27: /* stack. Special case to decrement PC of 2 bytes if opcode is '21f8'. */
! 28: /* This should be fixed with a real model. */
! 29: /* 2007/12/07 [NP] If Trace is enabled and a group 2 exception occurs (such as CHK), the trace */
! 30: /* handler should be called after the group 2's handler. If a bus error, address */
! 31: /* error or illegal occurs while Trace is enabled, the trace handler should not be */
! 32: /* called after this instruction (Transbeauce 2 Demo, Phaleon Demo). */
! 33: /* This means that if a CHK is executed while trace bit was set, we must set PC */
! 34: /* to CHK handler, turn trace off in the internal SR, but we must still call the */
! 35: /* trace handler one last time with the PC set to the CHK's handler (even if */
! 36: /* trace mode is internally turned off while processing an exception). Once trace */
! 37: /* handler is finished (RTE), we return to the CHK's handler. */
! 38: /* This is true for DIV BY 0, CHK, TRAPV and TRAP. */
! 39: /* Backport exception_trace() from WinUAE to handle this behaviour (used in */
! 40: /* Transbeauce 2 demo). */
! 41: /* 2007/12/09 [NP] 'dc.w $a' should not be used to call 'OpCode_SysInit' but should give an illegal*/
! 42: /* instruction (Transbeauce 2 demo). */
! 43: /* Instead of always replacing the illegal instructions $8, $a and $c by the */
! 44: /* 3 functions required for HD emulation, we now do it in cart.c only if the */
! 45: /* built-in cartridge image is loaded. */
! 46: /* YEAH! Hatari is now the first emulator to pass the Transbeauce 2 protection :) */
! 47: /* 2007/12/18 [NP] More precise timings for HBL, VBL and MFP interrupts. On ST, these interrupts */
! 48: /* are taking 56 cycles instead of the 44 cycles in the 68000's documentation. */
! 49: /* 2007/12/24 [NP] If an interrupt (HBL, VBL) is pending after intruction 'n' was processed, the */
! 50: /* exception should be called before instr. 'n+1' is processed, not after (else the*/
! 51: /* interrupt's handler is delayed by one 68000's instruction, which could break */
! 52: /* some demos with too strict timings) (ACF's Demo Main Menu). */
! 53: /* We call the interrupt if ( SPCFLAG_INT | SPCFLAG_DOINT ) is set, not only if */
! 54: /* SPCFLAG_DOINT is set (as it was already the case when handling 'STOP'). */
! 55: /* 2007/12/25 [NP] FIXME When handling exceptions' cycles, using nr >= 64 to determine if this is */
! 56: /* an MFP exception could be wrong if the MFP VR was set to another value than the */
! 57: /* default $40 (this could be a problem with programs requiring a precise cycles */
! 58: /* calculation while changing VR, but no such programs were encountered so far). */
! 59:
! 60:
! 61:
! 62: const char NewCpu_rcsid[] = "Hatari $Id: newcpu.c,v 1.51 2008/03/11 13:50:18 thothy Exp $";
1.1 root 63:
64: #include "sysdeps.h"
65: #include "hatari-glue.h"
66: #include "maccess.h"
67: #include "memory.h"
68: #include "newcpu.h"
1.1.1.5 root 69: #include "../includes/main.h"
1.1.1.10 root 70: #include "../includes/log.h"
1.1.1.7 root 71: #include "../includes/m68000.h"
1.1.1.12! root 72: #include "../includes/int.h"
1.1.1.8 root 73: #include "../includes/mfp.h"
1.1 root 74: #include "../includes/tos.h"
1.1.1.5 root 75: #include "../includes/vdi.h"
76: #include "../includes/cart.h"
77: #include "../includes/debugui.h"
1.1.1.8 root 78: #include "../includes/bios.h"
79: #include "../includes/xbios.h"
1.1.1.12! root 80: #include "../includes/video.h"
! 81: #include "../includes/trace.h"
1.1 root 82:
1.1.1.12! root 83: //#define DEBUG_PREFETCH
1.1 root 84:
85: struct flag_struct regflags;
86:
87: /* Opcode of faulting instruction */
88: uae_u16 last_op_for_exception_3;
89: /* PC at fault time */
90: uaecptr last_addr_for_exception_3;
91: /* Address that generated the exception */
92: uaecptr last_fault_for_exception_3;
93:
1.1.1.11 root 94: const int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
95: const int imm8_table[] = { 8,1,2,3,4,5,6,7 };
1.1 root 96:
97: int movem_index1[256];
98: int movem_index2[256];
99: int movem_next[256];
100:
101: int fpp_movem_index1[256];
102: int fpp_movem_index2[256];
103: int fpp_movem_next[256];
104:
105: cpuop_func *cpufunctbl[65536];
106:
1.1.1.12! root 107: int OpcodeFamily;
1.1.1.6 root 108:
1.1 root 109: #define COUNT_INSTRS 0
110:
111: #if COUNT_INSTRS
112: static unsigned long int instrcount[65536];
113: static uae_u16 opcodenums[65536];
114:
115: static int compfn (const void *el1, const void *el2)
116: {
117: return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
118: }
119:
120: static char *icountfilename (void)
121: {
122: char *name = getenv ("INSNCOUNT");
123: if (name)
124: return name;
125: return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
126: }
127:
128: void dump_counts (void)
129: {
130: FILE *f = fopen (icountfilename (), "w");
131: unsigned long int total;
132: int i;
133:
134: write_log ("Writing instruction count file...\n");
135: for (i = 0; i < 65536; i++) {
136: opcodenums[i] = i;
137: total += instrcount[i];
138: }
139: qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
140:
141: fprintf (f, "Total: %lu\n", total);
142: for (i=0; i < 65536; i++) {
143: unsigned long int cnt = instrcount[opcodenums[i]];
144: struct instr *dp;
145: struct mnemolookup *lookup;
146: if (!cnt)
147: break;
148: dp = table68k + opcodenums[i];
149: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
150: ;
151: fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
152: }
153: fclose (f);
154: }
155: #else
156: void dump_counts (void)
157: {
158: }
159: #endif
160:
161:
162: static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM;
163:
164: static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
165: {
1.1.1.6 root 166: op_illg (opcode);
1.1 root 167: return 4;
168: }
169:
1.1.1.4 root 170:
171: void build_cpufunctbl(void)
1.1 root 172: {
173: int i;
174: unsigned long opcode;
1.1.1.12! root 175: const struct cputbl *tbl = (currprefs.cpu_level == 4 ? op_smalltbl_0_ff
! 176: : currprefs.cpu_level == 3 ? op_smalltbl_1_ff
! 177: : currprefs.cpu_level == 2 ? op_smalltbl_2_ff
! 178: : currprefs.cpu_level == 1 ? op_smalltbl_3_ff
! 179: : ! currprefs.cpu_compatible ? op_smalltbl_4_ff
1.1.1.11 root 180: : op_smalltbl_5_ff);
1.1 root 181:
1.1.1.10 root 182: Log_Printf(LOG_DEBUG, "Building CPU function table (%d %d %d).\n",
1.1.1.12! root 183: currprefs.cpu_level, currprefs.cpu_compatible, currprefs.address_space_24);
1.1 root 184:
185: for (opcode = 0; opcode < 65536; opcode++)
1.1.1.6 root 186: cpufunctbl[opcode] = op_illg_1;
1.1 root 187: for (i = 0; tbl[i].handler != NULL; i++) {
188: if (! tbl[i].specific)
1.1.1.6 root 189: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 190: }
191: for (opcode = 0; opcode < 65536; opcode++) {
192: cpuop_func *f;
193:
1.1.1.12! root 194: if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > currprefs.cpu_level)
1.1 root 195: continue;
196:
197: if (table68k[opcode].handler != -1) {
1.1.1.6 root 198: f = cpufunctbl[table68k[opcode].handler];
1.1 root 199: if (f == op_illg_1)
200: abort();
1.1.1.6 root 201: cpufunctbl[opcode] = f;
1.1 root 202: }
203: }
204: for (i = 0; tbl[i].handler != NULL; i++) {
205: if (tbl[i].specific)
1.1.1.6 root 206: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 207: }
208: }
209:
210:
211:
212: void init_m68k (void)
213: {
214: int i;
215:
216: for (i = 0 ; i < 256 ; i++) {
217: int j;
218: for (j = 0 ; j < 8 ; j++) {
219: if (i & (1 << j)) break;
220: }
221: movem_index1[i] = j;
222: movem_index2[i] = 7-j;
223: movem_next[i] = i & (~(1 << j));
224: }
225: for (i = 0 ; i < 256 ; i++) {
226: int j;
227: for (j = 7 ; j >= 0 ; j--) {
228: if (i & (1 << j)) break;
229: }
230: fpp_movem_index1[i] = 7-j;
231: fpp_movem_index2[i] = j;
232: fpp_movem_next[i] = i & (~(1 << j));
233: }
234: #if COUNT_INSTRS
235: {
236: FILE *f = fopen (icountfilename (), "r");
237: memset (instrcount, 0, sizeof instrcount);
238: if (f) {
239: uae_u32 opcode, count, total;
240: char name[20];
241: write_log ("Reading instruction count file...\n");
242: fscanf (f, "Total: %lu\n", &total);
243: while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
244: instrcount[opcode] = count;
245: }
246: fclose(f);
247: }
248: }
249: #endif
250: write_log ("Building CPU table for configuration: 68");
1.1.1.12! root 251: if (currprefs.address_space_24 && currprefs.cpu_level > 1)
1.1 root 252: write_log ("EC");
1.1.1.12! root 253: switch (currprefs.cpu_level) {
1.1 root 254: case 1:
255: write_log ("010");
256: break;
257: case 2:
258: write_log ("020");
259: break;
260: case 3:
261: write_log ("020/881");
262: break;
263: case 4:
264: /* Who is going to miss the MMU anyway...? :-) */
265: write_log ("040");
266: break;
267: default:
268: write_log ("000");
269: break;
270: }
1.1.1.12! root 271: if (currprefs.cpu_compatible)
1.1 root 272: write_log (" (compatible mode)");
273: write_log ("\n");
1.1.1.7 root 274:
1.1 root 275: read_table68k ();
276: do_merges ();
277:
1.1.1.10 root 278: Log_Printf(LOG_DEBUG, "%d CPU functions\n", nr_cpuop_funcs);
1.1 root 279:
280: build_cpufunctbl ();
281: }
282:
1.1.1.4 root 283:
1.1.1.8 root 284: /* not used ATM:
1.1 root 285: static struct regstruct regs_backup[16];
286: static int backup_pointer = 0;
1.1.1.10 root 287: struct regstruct lastint_regs;
288: int lastint_no;
1.1.1.8 root 289: */
1.1.1.10 root 290: struct regstruct regs;
1.1 root 291: static long int m68kpc_offset;
1.1.1.10 root 292:
1.1 root 293:
294: #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
295: #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
296: #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
297:
298: uae_s32 ShowEA (FILE *f, int reg, amodes mode, wordsizes size, char *buf)
299: {
300: uae_u16 dp;
301: uae_s8 disp8;
302: uae_s16 disp16;
303: int r;
304: uae_u32 dispreg;
305: uaecptr addr;
306: uae_s32 offset = 0;
307: char buffer[80];
308:
309: switch (mode){
310: case Dreg:
311: sprintf (buffer,"D%d", reg);
312: break;
313: case Areg:
314: sprintf (buffer,"A%d", reg);
315: break;
316: case Aind:
317: sprintf (buffer,"(A%d)", reg);
318: break;
319: case Aipi:
320: sprintf (buffer,"(A%d)+", reg);
321: break;
322: case Apdi:
323: sprintf (buffer,"-(A%d)", reg);
324: break;
325: case Ad16:
326: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
327: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
328: sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
329: (unsigned long)addr);
330: break;
331: case Ad8r:
332: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
333: disp8 = dp & 0xFF;
334: r = (dp & 0x7000) >> 12;
335: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
336: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
337: dispreg <<= (dp >> 9) & 3;
338:
339: if (dp & 0x100) {
340: uae_s32 outer = 0, disp = 0;
341: uae_s32 base = m68k_areg(regs,reg);
342: char name[10];
343: sprintf (name,"A%d, ",reg);
344: if (dp & 0x80) { base = 0; name[0] = 0; }
345: if (dp & 0x40) dispreg = 0;
346: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
347: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
348: base += disp;
349:
350: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
351: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
352:
353: if (!(dp & 4)) base += dispreg;
354: if (dp & 3) base = get_long (base);
355: if (dp & 4) base += dispreg;
356:
357: addr = base + outer;
358: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
359: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
360: 1 << ((dp >> 9) & 3),
1.1.1.5 root 361: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 362: } else {
363: addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
364: sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
365: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
366: 1 << ((dp >> 9) & 3), disp8,
367: (unsigned long)addr);
368: }
369: break;
370: case PC16:
371: addr = m68k_getpc () + m68kpc_offset;
372: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
373: addr += (uae_s16)disp16;
374: sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
375: break;
376: case PC8r:
377: addr = m68k_getpc () + m68kpc_offset;
378: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
379: disp8 = dp & 0xFF;
380: r = (dp & 0x7000) >> 12;
381: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
382: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
383: dispreg <<= (dp >> 9) & 3;
384:
385: if (dp & 0x100) {
386: uae_s32 outer = 0,disp = 0;
387: uae_s32 base = addr;
388: char name[10];
389: sprintf (name,"PC, ");
390: if (dp & 0x80) { base = 0; name[0] = 0; }
391: if (dp & 0x40) dispreg = 0;
392: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
393: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
394: base += disp;
395:
396: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
397: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
398:
399: if (!(dp & 4)) base += dispreg;
400: if (dp & 3) base = get_long (base);
401: if (dp & 4) base += dispreg;
402:
403: addr = base + outer;
404: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
405: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
406: 1 << ((dp >> 9) & 3),
1.1.1.5 root 407: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 408: } else {
409: addr += (uae_s32)((uae_s8)disp8) + dispreg;
410: sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
411: (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
412: disp8, (unsigned long)addr);
413: }
414: break;
415: case absw:
416: sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
417: m68kpc_offset += 2;
418: break;
419: case absl:
420: sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
421: m68kpc_offset += 4;
422: break;
423: case imm:
424: switch (size){
425: case sz_byte:
426: sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
427: m68kpc_offset += 2;
428: break;
429: case sz_word:
430: sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
431: m68kpc_offset += 2;
432: break;
433: case sz_long:
434: sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
435: m68kpc_offset += 4;
436: break;
437: default:
438: break;
439: }
440: break;
441: case imm0:
442: offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
443: m68kpc_offset += 2;
444: sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
445: break;
446: case imm1:
447: offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
448: m68kpc_offset += 2;
449: sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
450: break;
451: case imm2:
452: offset = (uae_s32)get_ilong_1 (m68kpc_offset);
453: m68kpc_offset += 4;
454: sprintf (buffer,"#$%08lx", (unsigned long)offset);
455: break;
456: case immi:
457: offset = (uae_s32)(uae_s8)(reg & 0xff);
458: sprintf (buffer,"#$%08lx", (unsigned long)offset);
459: break;
460: default:
461: break;
462: }
463: if (buf == 0)
464: fprintf (f, "%s", buffer);
465: else
466: strcat (buf, buffer);
467: return offset;
468: }
469:
1.1.1.8 root 470:
1.1 root 471: /* The plan is that this will take over the job of exception 3 handling -
472: * the CPU emulation functions will just do a longjmp to m68k_go whenever
473: * they hit an odd address. */
1.1.1.8 root 474: #if 0
1.1 root 475: static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
476: {
477: uae_u16 dp;
478: uae_s8 disp8;
479: uae_s16 disp16;
480: int r;
481: uae_u32 dispreg;
482: uaecptr addr;
1.1.1.5 root 483: /*uae_s32 offset = 0;*/
1.1 root 484:
485: switch (mode){
486: case Dreg:
487: *val = m68k_dreg (regs, reg);
488: return 1;
489: case Areg:
490: *val = m68k_areg (regs, reg);
491: return 1;
492:
493: case Aind:
494: case Aipi:
495: addr = m68k_areg (regs, reg);
496: break;
497: case Apdi:
498: addr = m68k_areg (regs, reg);
499: break;
500: case Ad16:
501: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
502: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
503: break;
504: case Ad8r:
505: addr = m68k_areg (regs, reg);
506: d8r_common:
507: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
508: disp8 = dp & 0xFF;
509: r = (dp & 0x7000) >> 12;
510: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
511: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
512: dispreg <<= (dp >> 9) & 3;
513:
514: if (dp & 0x100) {
515: uae_s32 outer = 0, disp = 0;
516: uae_s32 base = addr;
517: if (dp & 0x80) base = 0;
518: if (dp & 0x40) dispreg = 0;
519: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
520: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
521: base += disp;
522:
523: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
524: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
525:
526: if (!(dp & 4)) base += dispreg;
527: if (dp & 3) base = get_long (base);
528: if (dp & 4) base += dispreg;
529:
530: addr = base + outer;
531: } else {
532: addr += (uae_s32)((uae_s8)disp8) + dispreg;
533: }
534: break;
535: case PC16:
536: addr = m68k_getpc () + m68kpc_offset;
537: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
538: addr += (uae_s16)disp16;
539: break;
540: case PC8r:
541: addr = m68k_getpc () + m68kpc_offset;
542: goto d8r_common;
543: case absw:
544: addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
545: m68kpc_offset += 2;
546: break;
547: case absl:
548: addr = get_ilong_1 (m68kpc_offset);
549: m68kpc_offset += 4;
550: break;
551: case imm:
552: switch (size){
553: case sz_byte:
554: *val = get_iword_1 (m68kpc_offset) & 0xff;
555: m68kpc_offset += 2;
556: break;
557: case sz_word:
558: *val = get_iword_1 (m68kpc_offset) & 0xffff;
559: m68kpc_offset += 2;
560: break;
561: case sz_long:
562: *val = get_ilong_1 (m68kpc_offset);
563: m68kpc_offset += 4;
564: break;
565: default:
566: break;
567: }
568: return 1;
569: case imm0:
570: *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
571: m68kpc_offset += 2;
572: return 1;
573: case imm1:
574: *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
575: m68kpc_offset += 2;
576: return 1;
577: case imm2:
578: *val = get_ilong_1 (m68kpc_offset);
579: m68kpc_offset += 4;
580: return 1;
581: case immi:
582: *val = (uae_s32)(uae_s8)(reg & 0xff);
583: return 1;
584: default:
585: addr = 0;
586: break;
587: }
588: if ((addr & 1) == 0)
589: return 1;
590:
591: last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
592: last_fault_for_exception_3 = addr;
593: return 0;
594: }
1.1.1.8 root 595: #endif
596:
1.1 root 597:
598: uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
599: {
600: int reg = (dp >> 12) & 15;
601: uae_s32 regd = regs.regs[reg];
602: if ((dp & 0x800) == 0)
603: regd = (uae_s32)(uae_s16)regd;
604: regd <<= (dp >> 9) & 3;
605: if (dp & 0x100) {
606: uae_s32 outer = 0;
607: if (dp & 0x80) base = 0;
608: if (dp & 0x40) regd = 0;
609:
610: if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
611: if ((dp & 0x30) == 0x30) base += next_ilong();
612:
613: if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
614: if ((dp & 0x3) == 0x3) outer = next_ilong();
615:
616: if ((dp & 0x4) == 0) base += regd;
617: if (dp & 0x3) base = get_long (base);
618: if (dp & 0x4) base += regd;
619:
620: return base + outer;
621: } else {
622: return base + (uae_s32)((uae_s8)dp) + regd;
623: }
624: }
625:
626: uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
627: {
628: int reg = (dp >> 12) & 15;
629: uae_s32 regd = regs.regs[reg];
630: #if 1
631: if ((dp & 0x800) == 0)
632: regd = (uae_s32)(uae_s16)regd;
633: return base + (uae_s8)dp + regd;
634: #else
635: /* Branch-free code... benchmark this again now that
636: * things are no longer inline. */
637: uae_s32 regd16;
638: uae_u32 mask;
639: mask = ((dp & 0x800) >> 11) - 1;
640: regd16 = (uae_s32)(uae_s16)regd;
641: regd16 &= mask;
642: mask = ~mask;
643: base += (uae_s8)dp;
644: regd &= mask;
645: regd |= regd16;
646: return base + regd;
647: #endif
648: }
649:
1.1.1.8 root 650:
651: /* Create the Status Register from the flags */
1.1 root 652: void MakeSR (void)
653: {
654: #if 0
655: assert((regs.t1 & 1) == regs.t1);
656: assert((regs.t0 & 1) == regs.t0);
657: assert((regs.s & 1) == regs.s);
658: assert((regs.m & 1) == regs.m);
659: assert((XFLG & 1) == XFLG);
660: assert((NFLG & 1) == NFLG);
661: assert((ZFLG & 1) == ZFLG);
662: assert((VFLG & 1) == VFLG);
663: assert((CFLG & 1) == CFLG);
664: #endif
665: regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
666: | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
667: | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
668: | GET_CFLG);
669: }
670:
1.1.1.8 root 671:
672: /* Set up the flags from Status Register */
1.1 root 673: void MakeFromSR (void)
674: {
675: int oldm = regs.m;
676: int olds = regs.s;
677:
678: regs.t1 = (regs.sr >> 15) & 1;
679: regs.t0 = (regs.sr >> 14) & 1;
680: regs.s = (regs.sr >> 13) & 1;
681: regs.m = (regs.sr >> 12) & 1;
682: regs.intmask = (regs.sr >> 8) & 7;
683: SET_XFLG ((regs.sr >> 4) & 1);
684: SET_NFLG ((regs.sr >> 3) & 1);
685: SET_ZFLG ((regs.sr >> 2) & 1);
686: SET_VFLG ((regs.sr >> 1) & 1);
687: SET_CFLG (regs.sr & 1);
1.1.1.12! root 688: if (currprefs.cpu_level >= 2) {
1.1 root 689: if (olds != regs.s) {
690: if (olds) {
691: if (oldm)
692: regs.msp = m68k_areg(regs, 7);
693: else
694: regs.isp = m68k_areg(regs, 7);
695: m68k_areg(regs, 7) = regs.usp;
696: } else {
697: regs.usp = m68k_areg(regs, 7);
698: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
699: }
700: } else if (olds && oldm != regs.m) {
701: if (oldm) {
702: regs.msp = m68k_areg(regs, 7);
703: m68k_areg(regs, 7) = regs.isp;
704: } else {
705: regs.isp = m68k_areg(regs, 7);
706: m68k_areg(regs, 7) = regs.msp;
707: }
708: }
709: } else {
1.1.1.12! root 710: /* [NP] If cpu < 68020, m and t0 are ignored and should be set to 0 */
! 711: regs.t0 = 0;
! 712: regs.m = 0;
! 713:
1.1 root 714: if (olds != regs.s) {
715: if (olds) {
716: regs.isp = m68k_areg(regs, 7);
717: m68k_areg(regs, 7) = regs.usp;
718: } else {
719: regs.usp = m68k_areg(regs, 7);
720: m68k_areg(regs, 7) = regs.isp;
721: }
722: }
723: }
724:
1.1.1.8 root 725: /* Pending interrupts can occur again after a write to the SR: */
726: set_special (SPCFLAG_DOINT);
1.1 root 727: if (regs.t1 || regs.t0)
728: set_special (SPCFLAG_TRACE);
729: else
1.1.1.6 root 730: /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
731: SR-modifying instructions (including STOP). */
732: unset_special (SPCFLAG_TRACE);
1.1 root 733: }
734:
1.1.1.5 root 735:
1.1.1.12! root 736: static void exception_trace (int nr)
! 737: {
! 738: unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
! 739: if (regs.t1 && !regs.t0) {
! 740: /* trace stays pending if exception is div by zero, chk,
! 741: * trapv or trap #x
! 742: */
! 743: if (nr == 5 || nr == 6 || nr == 7 || (nr >= 32 && nr <= 47))
! 744: set_special (SPCFLAG_DOTRACE);
! 745: }
! 746: regs.t1 = regs.t0 = regs.m = 0;
! 747: }
! 748:
! 749:
1.1 root 750: void Exception(int nr, uaecptr oldpc)
751: {
752: uae_u32 currpc = m68k_getpc ();
753:
1.1.1.2 root 754: /*if( nr>=2 && nr<10 ) fprintf(stderr,"Exception (-> %i bombs)!\n",nr);*/
1.1 root 755:
1.1.1.7 root 756: /* Intercept VDI exception (Trap #2 with D0 = 0x73) */
757: if(bUseVDIRes && nr == 0x22 && regs.regs[0] == 0x73)
1.1.1.5 root 758: {
1.1.1.6 root 759: if(!VDI())
1.1.1.5 root 760: {
1.1.1.6 root 761: /* Set 'PC' as address of 'VDI_OPCODE' illegal instruction
762: * This will call OpCode_VDI after completion of Trap call!
763: * Use to modify return structure from VDI */
764: VDI_OldPC = currpc;
765: currpc = CART_VDI_OPCODE_ADDR;
1.1.1.5 root 766: }
767: }
768:
1.1.1.8 root 769: #if 0
770: /* Intercept BIOS or XBIOS trap (Trap #13 or #14) */
771: if (nr == 0x2d)
772: {
773: /* Intercept BIOS calls */
774: if (Bios()) return;
775: }
776: else if (nr == 0x2e)
777: {
778: /* Intercept XBIOS calls */
779: if (XBios()) return;
780: }
781: #endif
782:
1.1 root 783: MakeSR();
784:
1.1.1.8 root 785: /* Change to supervisor mode if necessary */
1.1 root 786: if (!regs.s) {
787: regs.usp = m68k_areg(regs, 7);
1.1.1.12! root 788: if (currprefs.cpu_level >= 2)
1.1 root 789: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
790: else
791: m68k_areg(regs, 7) = regs.isp;
792: regs.s = 1;
793: }
1.1.1.8 root 794:
795: /* Build additional exception stack frame for 68010 and higher */
1.1.1.12! root 796: if (currprefs.cpu_level > 0) {
1.1 root 797: if (nr == 2 || nr == 3) {
798: int i;
799: /* @@@ this is probably wrong (?) */
800: for (i = 0 ; i < 12 ; i++) {
801: m68k_areg(regs, 7) -= 2;
802: put_word (m68k_areg(regs, 7), 0);
803: }
804: m68k_areg(regs, 7) -= 2;
805: put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
806: } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
807: m68k_areg(regs, 7) -= 4;
808: put_long (m68k_areg(regs, 7), oldpc);
809: m68k_areg(regs, 7) -= 2;
810: put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
811: } else if (regs.m && nr >= 24 && nr < 32) {
812: m68k_areg(regs, 7) -= 2;
813: put_word (m68k_areg(regs, 7), nr * 4);
814: m68k_areg(regs, 7) -= 4;
815: put_long (m68k_areg(regs, 7), currpc);
816: m68k_areg(regs, 7) -= 2;
817: put_word (m68k_areg(regs, 7), regs.sr);
818: regs.sr |= (1 << 13);
819: regs.msp = m68k_areg(regs, 7);
820: m68k_areg(regs, 7) = regs.isp;
821: m68k_areg(regs, 7) -= 2;
822: put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
823: } else {
824: m68k_areg(regs, 7) -= 2;
825: put_word (m68k_areg(regs, 7), nr * 4);
826: }
827: }
1.1.1.3 root 828:
829: /* Push PC on stack: */
1.1 root 830: m68k_areg(regs, 7) -= 4;
831: put_long (m68k_areg(regs, 7), currpc);
1.1.1.3 root 832: /* Push SR on stack: */
1.1 root 833: m68k_areg(regs, 7) -= 2;
834: put_word (m68k_areg(regs, 7), regs.sr);
1.1.1.3 root 835:
1.1.1.12! root 836: HATARI_TRACE ( HATARI_TRACE_CPU_EXCEPTION , "cpu exception %d currpc %x buspc %x fault_e3 %x op_e3 %hx addr_e3 %x\n" ,
! 837: nr, currpc, BusErrorPC, last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3 );
! 838:
1.1.1.3 root 839: /* 68000 bus/address errors: */
1.1.1.12! root 840: if (currprefs.cpu_level==0 && (nr==2 || nr==3)) {
! 841: uae_u16 specialstatus = 1;
! 842:
1.1.1.8 root 843: /* Special status word emulation isn't perfect yet... :-( */
844: if (regs.sr & 0x2000)
845: specialstatus |= 0x4;
1.1.1.3 root 846: m68k_areg(regs, 7) -= 8;
847: if (nr == 3) { /* Address error */
1.1.1.12! root 848: specialstatus |= ( last_op_for_exception_3 & (~0x1f) ); /* [NP] unused bits of specialstatus are those of the last opcode ! */
1.1.1.8 root 849: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.3 root 850: put_long (m68k_areg(regs, 7)+2, last_fault_for_exception_3);
851: put_word (m68k_areg(regs, 7)+6, last_op_for_exception_3);
852: put_long (m68k_areg(regs, 7)+10, last_addr_for_exception_3);
1.1.1.8 root 853: if (bEnableDebug) {
854: fprintf(stderr,"Address Error at address $%x, PC=$%x\n",last_fault_for_exception_3,currpc);
855: DebugUI();
856: }
1.1.1.3 root 857: }
1.1.1.8 root 858: else { /* Bus error */
1.1.1.12! root 859: specialstatus |= ( get_word(BusErrorPC) & (~0x1f) ); /* [NP] unused bits of special status are those of the last opcode ! */
1.1.1.8 root 860: if (bBusErrorReadWrite)
861: specialstatus |= 0x10;
862: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.10 root 863: put_long (m68k_areg(regs, 7)+2, BusErrorAddress);
1.1.1.12! root 864: put_word (m68k_areg(regs, 7)+6, get_word(BusErrorPC)); /* Opcode */
! 865:
! 866: /* [NP] PC stored in the stack frame is not necessarily pointing to the next instruction ! */
! 867: /* FIXME : we should have a proper model for this, in the meantime we handle specific cases */
! 868: if ( get_word(BusErrorPC) == 0x21f8 ) /* move.l $0.w,$24.w (Transbeauce 2 loader) */
! 869: put_long (m68k_areg(regs, 7)+10, currpc-2); /* correct PC is 2 bytes less than usual value */
1.1.1.8 root 870: /* Check for double bus errors: */
871: if (regs.spcflags & SPCFLAG_BUSERROR) {
872: fprintf(stderr, "Detected double bus error at address $%x, PC=$%lx => CPU halted!\n",
1.1.1.10 root 873: BusErrorAddress, (long)currpc);
1.1.1.8 root 874: unset_special(SPCFLAG_BUSERROR);
875: if (bEnableDebug)
876: DebugUI();
877: regs.intmask = 7;
878: m68k_setstopped(TRUE);
879: return;
880: }
1.1.1.10 root 881: if (bEnableDebug && BusErrorAddress!=0xff8a00) {
882: fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n", BusErrorAddress, (long)currpc);
1.1.1.8 root 883: DebugUI();
884: }
885: }
1.1.1.3 root 886: }
887:
1.1.1.8 root 888: /* Set PC and flags */
889: if (bEnableDebug && get_long (regs.vbr + 4*nr) == 0) {
890: write_log("Uninitialized exception handler #%i!\n", nr);
1.1.1.12! root 891: if (bEnableDebug)
! 892: DebugUI();
1.1.1.8 root 893: }
1.1 root 894: m68k_setpc (get_long (regs.vbr + 4*nr));
895: fill_prefetch_0 ();
1.1.1.12! root 896: /* Handle trace flags depending on current state */
! 897: exception_trace (nr);
1.1.1.6 root 898:
1.1.1.12! root 899: /* Handle exception cycles */
1.1.1.7 root 900: if(nr >= 24 && nr <= 31)
901: {
1.1.1.12! root 902: if ( ( nr == 26 ) || ( nr == 28 ) ) /* HBL or VBL */
! 903: M68000_AddCycles(44+12); /* Video Interrupt */
! 904: else
! 905: M68000_AddCycles(44+4); /* Other Interrupts */
1.1.1.7 root 906: }
907: else if(nr >= 32 && nr <= 47)
908: {
1.1.1.12! root 909: M68000_AddCycles(34); /* Trap */
1.1.1.7 root 910: }
911: else switch(nr)
912: {
1.1.1.12! root 913: case 2: M68000_AddCycles(50); break; /* Bus error */
! 914: case 3: M68000_AddCycles(50); break; /* Address error */
! 915: case 4: M68000_AddCycles(34); break; /* Illegal instruction */
! 916: case 5: M68000_AddCycles(38); break; /* Div by zero */
! 917: case 6: M68000_AddCycles(40); break; /* CHK */
! 918: case 7: M68000_AddCycles(34); break; /* TRAPV */
! 919: case 8: M68000_AddCycles(34); break; /* Privilege violation */
! 920: case 9: M68000_AddCycles(34); break; /* Trace */
! 921: case 10: M68000_AddCycles(34); break; /* Line-A - probably wrong */
! 922: case 11: M68000_AddCycles(34); break; /* Line-F - probably wrong */
1.1.1.7 root 923: default:
1.1.1.8 root 924: /* FIXME: Add right cycles value for MFP interrupts and copro exceptions ... */
1.1.1.7 root 925: if(nr < 64)
1.1.1.12! root 926: M68000_AddCycles(4); /* Coprocessor and unassigned exceptions (???) */
1.1.1.7 root 927: else
1.1.1.12! root 928: M68000_AddCycles(44+12); /* Must be a MFP interrupt */
1.1.1.7 root 929: break;
1.1.1.6 root 930: }
1.1 root 931: }
932:
1.1.1.7 root 933:
1.1 root 934: static void Interrupt(int nr)
935: {
936: assert(nr < 8 && nr >= 0);
1.1.1.10 root 937: /*lastint_regs = regs;*/
938: /*lastint_no = nr;*/
1.1 root 939: Exception(nr+24, 0);
940:
941: regs.intmask = nr;
942: set_special (SPCFLAG_INT);
943: }
944:
1.1.1.7 root 945:
1.1.1.12! root 946: uae_u32 caar, cacr;
1.1.1.8 root 947: static uae_u32 itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp;
1.1 root 948:
1.1.1.7 root 949:
1.1.1.12! root 950: static int movec_illg (int regno)
! 951: {
! 952: int regno2 = regno & 0x7ff;
! 953: if (currprefs.cpu_level == 1) { /* 68010 */
! 954: if (regno2 < 2)
! 955: return 0;
! 956: return 1;
! 957: }
! 958: if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) { /* 68020 */
! 959: if (regno == 3) return 1; /* 68040 only */
! 960: /* 4 is >=68040, but 0x804 is in 68020 */
! 961: if (regno2 < 4 || regno == 0x804)
! 962: return 0;
! 963: return 1;
! 964: }
! 965: if (currprefs.cpu_level >= 4) { /* 68040 */
! 966: if (regno == 0x802) return 1; /* 68020 only */
! 967: if (regno2 < 8) return 0;
! 968: if (currprefs.cpu_level == 6 && regno2 == 8) /* 68060 only */
! 969: return 0;
! 970: return 1;
! 971: }
! 972: return 1;
! 973: }
! 974:
1.1 root 975: int m68k_move2c (int regno, uae_u32 *regp)
976: {
1.1.1.12! root 977: if (movec_illg (regno)) {
1.1 root 978: op_illg (0x4E7B);
979: return 0;
980: } else {
981: switch (regno) {
982: case 0: regs.sfc = *regp & 7; break;
983: case 1: regs.dfc = *regp & 7; break;
1.1.1.12! root 984: case 2: cacr = *regp & (currprefs.cpu_level < 4 ? 0x3 : 0x80008000); break;
1.1 root 985: case 3: tc = *regp & 0xc000; break;
986: /* Mask out fields that should be zero. */
987: case 4: itt0 = *regp & 0xffffe364; break;
988: case 5: itt1 = *regp & 0xffffe364; break;
989: case 6: dtt0 = *regp & 0xffffe364; break;
990: case 7: dtt1 = *regp & 0xffffe364; break;
1.1.1.7 root 991:
1.1 root 992: case 0x800: regs.usp = *regp; break;
993: case 0x801: regs.vbr = *regp; break;
1.1.1.12! root 994: case 0x802: caar = *regp & 0xfc; break;
1.1 root 995: case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
996: case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
1.1.1.6 root 997: case 0x805: mmusr = *regp; break;
998: case 0x806: urp = *regp; break;
999: case 0x807: srp = *regp; break;
1.1 root 1000: default:
1001: op_illg (0x4E7B);
1002: return 0;
1003: }
1004: }
1005: return 1;
1006: }
1007:
1008: int m68k_movec2 (int regno, uae_u32 *regp)
1009: {
1.1.1.12! root 1010: if (movec_illg (regno)) {
1.1 root 1011: op_illg (0x4E7A);
1012: return 0;
1013: } else {
1014: switch (regno) {
1015: case 0: *regp = regs.sfc; break;
1016: case 1: *regp = regs.dfc; break;
1.1.1.12! root 1017: case 2: *regp = cacr; break;
1.1 root 1018: case 3: *regp = tc; break;
1019: case 4: *regp = itt0; break;
1020: case 5: *regp = itt1; break;
1021: case 6: *regp = dtt0; break;
1022: case 7: *regp = dtt1; break;
1023: case 0x800: *regp = regs.usp; break;
1024: case 0x801: *regp = regs.vbr; break;
1.1.1.12! root 1025: case 0x802: *regp = caar; break;
1.1 root 1026: case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
1027: case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
1028: case 0x805: *regp = mmusr; break;
1.1.1.6 root 1029: case 0x806: *regp = urp; break;
1030: case 0x807: *regp = srp; break;
1.1 root 1031: default:
1032: op_illg (0x4E7A);
1033: return 0;
1034: }
1035: }
1036: return 1;
1037: }
1038:
1039: STATIC_INLINE int
1.1.1.10 root 1040: div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 ndiv, uae_u32 *quot, uae_u32 *rem)
1.1 root 1041: {
1042: uae_u32 q = 0, cbit = 0;
1043: int i;
1044:
1.1.1.10 root 1045: if (ndiv <= src_hi) {
1.1 root 1046: return 1;
1047: }
1048: for (i = 0 ; i < 32 ; i++) {
1049: cbit = src_hi & 0x80000000ul;
1050: src_hi <<= 1;
1051: if (src_lo & 0x80000000ul) src_hi++;
1052: src_lo <<= 1;
1053: q = q << 1;
1.1.1.10 root 1054: if (cbit || ndiv <= src_hi) {
1.1 root 1055: q |= 1;
1.1.1.10 root 1056: src_hi -= ndiv;
1.1 root 1057: }
1058: }
1059: *quot = q;
1060: *rem = src_hi;
1061: return 0;
1062: }
1063:
1064: void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
1065: {
1066: #if defined(uae_s64)
1067: if (src == 0) {
1068: Exception (5, oldpc);
1069: return;
1070: }
1071: if (extra & 0x800) {
1072: /* signed variant */
1073: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1074: uae_s64 quot, rem;
1075:
1076: if (extra & 0x400) {
1077: a &= 0xffffffffu;
1078: a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
1079: }
1080: rem = a % (uae_s64)(uae_s32)src;
1081: quot = a / (uae_s64)(uae_s32)src;
1082: if ((quot & UVAL64(0xffffffff80000000)) != 0
1083: && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1084: {
1085: SET_VFLG (1);
1086: SET_NFLG (1);
1087: SET_CFLG (0);
1088: } else {
1089: if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
1090: SET_VFLG (0);
1091: SET_CFLG (0);
1092: SET_ZFLG (((uae_s32)quot) == 0);
1093: SET_NFLG (((uae_s32)quot) < 0);
1094: m68k_dreg(regs, extra & 7) = rem;
1095: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1096: }
1097: } else {
1098: /* unsigned */
1099: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1100: uae_u64 quot, rem;
1101:
1102: if (extra & 0x400) {
1103: a &= 0xffffffffu;
1104: a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
1105: }
1106: rem = a % (uae_u64)src;
1107: quot = a / (uae_u64)src;
1108: if (quot > 0xffffffffu) {
1109: SET_VFLG (1);
1110: SET_NFLG (1);
1111: SET_CFLG (0);
1112: } else {
1113: SET_VFLG (0);
1114: SET_CFLG (0);
1115: SET_ZFLG (((uae_s32)quot) == 0);
1116: SET_NFLG (((uae_s32)quot) < 0);
1117: m68k_dreg(regs, extra & 7) = rem;
1118: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1119: }
1120: }
1121: #else
1122: if (src == 0) {
1123: Exception (5, oldpc);
1124: return;
1125: }
1126: if (extra & 0x800) {
1127: /* signed variant */
1128: uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1129: uae_s32 hi = lo < 0 ? -1 : 0;
1130: uae_s32 save_high;
1131: uae_u32 quot, rem;
1132: uae_u32 sign;
1133:
1134: if (extra & 0x400) {
1135: hi = (uae_s32)m68k_dreg(regs, extra & 7);
1136: }
1137: save_high = hi;
1138: sign = (hi ^ src);
1139: if (hi < 0) {
1140: hi = ~hi;
1141: lo = -lo;
1142: if (lo == 0) hi++;
1143: }
1144: if ((uae_s32)src < 0) src = -src;
1145: if (div_unsigned(hi, lo, src, ", &rem) ||
1146: (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
1147: SET_VFLG (1);
1148: SET_NFLG (1);
1149: SET_CFLG (0);
1150: } else {
1151: if (sign & 0x80000000) quot = -quot;
1152: if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
1153: SET_VFLG (0);
1154: SET_CFLG (0);
1155: SET_ZFLG (((uae_s32)quot) == 0);
1156: SET_NFLG (((uae_s32)quot) < 0);
1157: m68k_dreg(regs, extra & 7) = rem;
1158: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1159: }
1160: } else {
1161: /* unsigned */
1162: uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1163: uae_u32 hi = 0;
1164: uae_u32 quot, rem;
1165:
1166: if (extra & 0x400) {
1167: hi = (uae_u32)m68k_dreg(regs, extra & 7);
1168: }
1169: if (div_unsigned(hi, lo, src, ", &rem)) {
1170: SET_VFLG (1);
1171: SET_NFLG (1);
1172: SET_CFLG (0);
1173: } else {
1174: SET_VFLG (0);
1175: SET_CFLG (0);
1176: SET_ZFLG (((uae_s32)quot) == 0);
1177: SET_NFLG (((uae_s32)quot) < 0);
1178: m68k_dreg(regs, extra & 7) = rem;
1179: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1180: }
1181: }
1182: #endif
1183: }
1184:
1185: STATIC_INLINE void
1186: mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1187: {
1188: uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1189: uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1190: uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1191: uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1192: uae_u32 lo;
1193:
1194: lo = r0 + ((r1 << 16) & 0xffff0000ul);
1195: if (lo < r0) r3++;
1196: r0 = lo;
1197: lo = r0 + ((r2 << 16) & 0xffff0000ul);
1198: if (lo < r0) r3++;
1199: r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1200: *dst_lo = lo;
1201: *dst_hi = r3;
1202: }
1203:
1204: void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1205: {
1206: #if defined(uae_s64)
1207: if (extra & 0x800) {
1208: /* signed variant */
1209: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1210:
1211: a *= (uae_s64)(uae_s32)src;
1212: SET_VFLG (0);
1213: SET_CFLG (0);
1214: SET_ZFLG (a == 0);
1215: SET_NFLG (a < 0);
1216: if (extra & 0x400)
1217: m68k_dreg(regs, extra & 7) = a >> 32;
1218: else if ((a & UVAL64(0xffffffff80000000)) != 0
1219: && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1220: {
1221: SET_VFLG (1);
1222: }
1223: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1224: } else {
1225: /* unsigned */
1226: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1227:
1228: a *= (uae_u64)src;
1229: SET_VFLG (0);
1230: SET_CFLG (0);
1231: SET_ZFLG (a == 0);
1232: SET_NFLG (((uae_s64)a) < 0);
1233: if (extra & 0x400)
1234: m68k_dreg(regs, extra & 7) = a >> 32;
1235: else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1236: SET_VFLG (1);
1237: }
1238: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1239: }
1240: #else
1241: if (extra & 0x800) {
1242: /* signed variant */
1243: uae_s32 src1,src2;
1244: uae_u32 dst_lo,dst_hi;
1245: uae_u32 sign;
1246:
1247: src1 = (uae_s32)src;
1248: src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1249: sign = (src1 ^ src2);
1250: if (src1 < 0) src1 = -src1;
1251: if (src2 < 0) src2 = -src2;
1252: mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1253: if (sign & 0x80000000) {
1254: dst_hi = ~dst_hi;
1255: dst_lo = -dst_lo;
1256: if (dst_lo == 0) dst_hi++;
1257: }
1258: SET_VFLG (0);
1259: SET_CFLG (0);
1260: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1261: SET_NFLG (((uae_s32)dst_hi) < 0);
1262: if (extra & 0x400)
1263: m68k_dreg(regs, extra & 7) = dst_hi;
1264: else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1265: && ((dst_hi & 0xffffffff) != 0xffffffff
1266: || (dst_lo & 0x80000000) != 0x80000000))
1267: {
1268: SET_VFLG (1);
1269: }
1270: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1271: } else {
1272: /* unsigned */
1273: uae_u32 dst_lo,dst_hi;
1274:
1275: mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1276:
1277: SET_VFLG (0);
1278: SET_CFLG (0);
1279: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1280: SET_NFLG (((uae_s32)dst_hi) < 0);
1281: if (extra & 0x400)
1282: m68k_dreg(regs, extra & 7) = dst_hi;
1283: else if (dst_hi != 0) {
1284: SET_VFLG (1);
1285: }
1286: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1287: }
1288: #endif
1289: }
1.1.1.6 root 1290:
1.1 root 1291:
1292: void m68k_reset (void)
1293: {
1294: regs.s = 1;
1295: regs.m = 0;
1296: regs.stopped = 0;
1297: regs.t1 = 0;
1298: regs.t0 = 0;
1299: SET_ZFLG (0);
1300: SET_XFLG (0);
1301: SET_CFLG (0);
1302: SET_VFLG (0);
1303: SET_NFLG (0);
1.1.1.7 root 1304: regs.spcflags &= SPCFLAG_MODE_CHANGE; /* Clear specialflags except mode-change */
1.1 root 1305: regs.intmask = 7;
1306: regs.vbr = regs.sfc = regs.dfc = 0;
1307: regs.fpcr = regs.fpsr = regs.fpiar = 0;
1.1.1.7 root 1308:
1309: m68k_areg(regs, 7) = get_long(0);
1310: m68k_setpc(get_long(4));
1311: refill_prefetch (m68k_getpc(), 0);
1.1 root 1312: }
1313:
1.1.1.8 root 1314:
1.1 root 1315: unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1316: {
1.1.1.8 root 1317: #if 0
1.1 root 1318: uaecptr pc = m68k_getpc ();
1.1.1.8 root 1319: #endif
1.1.1.6 root 1320: if ((opcode & 0xF000) == 0xF000) {
1.1 root 1321: Exception(0xB,0);
1322: return 4;
1.1.1.6 root 1323: }
1324: if ((opcode & 0xF000) == 0xA000) {
1.1 root 1325: Exception(0xA,0);
1326: return 4;
1.1.1.6 root 1327: }
1.1.1.3 root 1328: #if 0
1.1.1.6 root 1329: write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc);
1.1 root 1330: #endif
1331: Exception (4,0);
1332: return 4;
1333: }
1334:
1.1.1.8 root 1335:
1.1 root 1336: void mmu_op(uae_u32 opcode, uae_u16 extra)
1337: {
1338: if ((opcode & 0xFE0) == 0x0500) {
1339: /* PFLUSH */
1340: mmusr = 0;
1341: write_log ("PFLUSH\n");
1342: } else if ((opcode & 0x0FD8) == 0x548) {
1343: /* PTEST */
1344: write_log ("PTEST\n");
1345: } else
1346: op_illg (opcode);
1347: }
1348:
1349:
1350: static uaecptr last_trace_ad = 0;
1351:
1352: static void do_trace (void)
1353: {
1.1.1.12! root 1354: if (regs.t0 && currprefs.cpu_level >= 2) {
1.1 root 1355: uae_u16 opcode;
1356: /* should also include TRAP, CHK, SR modification FPcc */
1357: /* probably never used so why bother */
1358: /* We can afford this to be inefficient... */
1359: m68k_setpc (m68k_getpc ());
1360: fill_prefetch_0 ();
1361: opcode = get_word (regs.pc);
1362: if (opcode == 0x4e72 /* RTE */
1363: || opcode == 0x4e74 /* RTD */
1364: || opcode == 0x4e75 /* RTS */
1365: || opcode == 0x4e77 /* RTR */
1366: || opcode == 0x4e76 /* TRAPV */
1367: || (opcode & 0xffc0) == 0x4e80 /* JSR */
1368: || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1369: || (opcode & 0xff00) == 0x6100 /* BSR */
1370: || ((opcode & 0xf000) == 0x6000 /* Bcc */
1371: && cctrue((opcode >> 8) & 0xf))
1372: || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1373: && !cctrue((opcode >> 8) & 0xf)
1374: && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1375: {
1376: last_trace_ad = m68k_getpc ();
1377: unset_special (SPCFLAG_TRACE);
1378: set_special (SPCFLAG_DOTRACE);
1379: }
1380: } else if (regs.t1) {
1381: last_trace_ad = m68k_getpc ();
1382: unset_special (SPCFLAG_TRACE);
1383: set_special (SPCFLAG_DOTRACE);
1384: }
1385: }
1386:
1387:
1.1.1.8 root 1388: /*
1389: * Handle special flags
1390: */
1.1 root 1391: static int do_specialties (void)
1392: {
1.1.1.7 root 1393: if(regs.spcflags & SPCFLAG_BUSERROR) {
1394: /* We can not execute bus errors directly in the memory handler
1395: * functions since the PC should point to the address of the next
1396: * instruction, so we're executing the bus errors here: */
1.1.1.8 root 1397: unset_special(SPCFLAG_BUSERROR);
1.1.1.7 root 1398: Exception(2,0);
1399: }
1400:
1.1.1.8 root 1401: if(regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1402: /* Add some extra cycles to simulate a wait state */
1403: unset_special(SPCFLAG_EXTRA_CYCLES);
1.1.1.11 root 1404: M68000_AddCycles(nWaitStateCycles);
1.1.1.12! root 1405: nWaitStateCycles = 0;
1.1.1.8 root 1406: }
1407:
1.1 root 1408: if (regs.spcflags & SPCFLAG_DOTRACE) {
1409: Exception (9,last_trace_ad);
1410: }
1.1.1.8 root 1411:
1.1 root 1412: while (regs.spcflags & SPCFLAG_STOP) {
1.1.1.8 root 1413: if (regs.intmask > 5) {
1414: /* We still have to care about events when IPL==7 ! */
1415: Main_EventHandler();
1416: if (regs.spcflags & SPCFLAG_BRK) return 1;
1417: }
1418: M68000_AddCycles(4);
1419: if (PendingInterruptCount<=0 && PendingInterruptFunction) {
1420: CALL_VAR(PendingInterruptFunction);
1421: }
1422: if (regs.spcflags & SPCFLAG_MFP) {
1423: MFP_CheckPendingInterrupts();
1424: }
1.1.1.5 root 1425: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1.1.1.6 root 1426: int intr = intlev ();
1.1 root 1427: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1.1.1.6 root 1428: if (intr != -1 && intr > regs.intmask) {
1.1 root 1429: Interrupt (intr);
1430: regs.stopped = 0;
1431: unset_special (SPCFLAG_STOP);
1.1.1.6 root 1432: }
1.1 root 1433: }
1434: }
1.1.1.8 root 1435:
1.1 root 1436: if (regs.spcflags & SPCFLAG_TRACE)
1437: do_trace ();
1438:
1.1.1.12! root 1439: // if (regs.spcflags & SPCFLAG_DOINT) {
! 1440: /* [NP] pending int should be processed now, not after the current instr */
! 1441: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1.1.1.6 root 1442: int intr = intlev ();
1.1.1.8 root 1443: /* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */
1.1.1.12! root 1444: // unset_special (SPCFLAG_DOINT);
! 1445: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1.1.1.6 root 1446: if (intr != -1 && intr > regs.intmask) {
1.1 root 1447: Interrupt (intr);
1448: regs.stopped = 0;
1.1.1.6 root 1449: }
1.1 root 1450: }
1451: if (regs.spcflags & SPCFLAG_INT) {
1452: unset_special (SPCFLAG_INT);
1453: set_special (SPCFLAG_DOINT);
1454: }
1.1.1.8 root 1455:
1456: if (regs.spcflags & SPCFLAG_MFP) { /* Check for MFP interrupts */
1457: MFP_CheckPendingInterrupts();
1458: }
1459:
1.1 root 1460: if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1.1.1.8 root 1461: unset_special(SPCFLAG_MODE_CHANGE);
1.1 root 1462: return 1;
1463: }
1.1.1.8 root 1464:
1.1 root 1465: return 0;
1466: }
1467:
1.1.1.3 root 1468:
1.1 root 1469: /* It's really sad to have two almost identical functions for this, but we
1470: do it all for performance... :( */
1471: static void m68k_run_1 (void)
1472: {
1473: #ifdef DEBUG_PREFETCH
1474: uae_u8 saved_bytes[20];
1475: uae_u16 *oldpcp;
1476: #endif
1.1.1.8 root 1477:
1478: for (;;) {
1.1 root 1479: int cycles;
1480: uae_u32 opcode = get_iword_prefetch (0);
1.1.1.8 root 1481:
1.1 root 1482: #ifdef DEBUG_PREFETCH
1483: if (get_ilong (0) != do_get_mem_long (®s.prefetch)) {
1484: fprintf (stderr, "Prefetch differs from memory.\n");
1485: debugging = 1;
1486: return;
1487: }
1488: oldpcp = regs.pc_p;
1489: memcpy (saved_bytes, regs.pc_p, 20);
1490: #endif
1491:
1492: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.12! root 1493: if ( HATARI_TRACE_LEVEL ( HATARI_TRACE_CPU_DISASM ) )
! 1494: {
! 1495: int nFrameCycles = Cycles_GetCounter(CYCLES_COUNTER_VIDEO);;
! 1496: int nLineCycles = nFrameCycles % nCyclesPerLine;
! 1497: HATARI_TRACE_PRINT ( "video_cyc=%6d %3d@%3d : " , nFrameCycles, nLineCycles, nHBL );
! 1498: m68k_disasm(stderr, m68k_getpc (), NULL, 1);
! 1499: }
1.1 root 1500:
1501: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1502: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1503: #if COUNT_INSTRS == 2
1504: if (table68k[opcode].handler != -1)
1505: instrcount[table68k[opcode].handler]++;
1506: #elif COUNT_INSTRS == 1
1507: instrcount[opcode]++;
1508: #endif
1.1.1.2 root 1509:
1.1.1.12! root 1510: /* In case of a Bus Error, we need the PC of the instruction that caused */
! 1511: /* the error to build the exception stack frame */
! 1512: BusErrorPC = m68k_getpc();
! 1513:
1.1.1.6 root 1514: cycles = (*cpufunctbl[opcode])(opcode);
1515:
1.1 root 1516: #ifdef DEBUG_PREFETCH
1517: if (memcmp (saved_bytes, oldpcp, 20) != 0) {
1.1.1.12! root 1518: fprintf (stderr, "Self-modifying code detected %x.\n" , m68k_getpc() );
1.1 root 1519: set_special (SPCFLAG_BRK);
1520: debugging = 1;
1521: }
1522: #endif
1.1.1.2 root 1523:
1.1.1.12! root 1524: M68000_AddCyclesWithPairing(cycles);
! 1525: while (PendingInterruptCount <= 0 && PendingInterruptFunction)
1.1.1.8 root 1526: CALL_VAR(PendingInterruptFunction);
1527:
1.1 root 1528: if (regs.spcflags) {
1529: if (do_specialties ())
1530: return;
1531: }
1532: }
1533: }
1534:
1535:
1536: /* Same thing, but don't use prefetch to get opcode. */
1537: static void m68k_run_2 (void)
1538: {
1.1.1.8 root 1539: for (;;) {
1.1 root 1540: int cycles;
1541: uae_u32 opcode = get_iword (0);
1542:
1543: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.12! root 1544: if ( HATARI_TRACE_LEVEL ( HATARI_TRACE_CPU_DISASM ) )
! 1545: {
! 1546: int nFrameCycles = Cycles_GetCounter(CYCLES_COUNTER_VIDEO);;
! 1547: int nLineCycles = nFrameCycles % nCyclesPerLine;
! 1548: HATARI_TRACE_PRINT ( "video_cyc=%6d %3d@%3d : " , nFrameCycles, nLineCycles, nHBL );
! 1549: m68k_disasm(stderr, m68k_getpc (), NULL, 1);
! 1550: }
! 1551:
1.1 root 1552:
1553: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1554: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1555: #if COUNT_INSTRS == 2
1556: if (table68k[opcode].handler != -1)
1557: instrcount[table68k[opcode].handler]++;
1558: #elif COUNT_INSTRS == 1
1559: instrcount[opcode]++;
1560: #endif
1.1.1.2 root 1561:
1.1.1.6 root 1562: cycles = (*cpufunctbl[opcode])(opcode);
1563:
1.1.1.8 root 1564: M68000_AddCycles(cycles);
1.1.1.12! root 1565: while (PendingInterruptCount <= 0 && PendingInterruptFunction)
1.1.1.8 root 1566: CALL_VAR(PendingInterruptFunction);
1567:
1.1 root 1568: if (regs.spcflags) {
1569: if (do_specialties ())
1570: return;
1571: }
1572: }
1573: }
1574:
1575:
1576: void m68k_go (int may_quit)
1577: {
1.1.1.8 root 1578: static int in_m68k_go = 0;
1579:
1.1 root 1580: if (in_m68k_go || !may_quit) {
1581: write_log ("Bug! m68k_go is not reentrant.\n");
1582: abort ();
1583: }
1584:
1585: in_m68k_go++;
1.1.1.8 root 1586: while (!(regs.spcflags & SPCFLAG_BRK)) {
1.1.1.12! root 1587: if(currprefs.cpu_compatible)
1.1.1.2 root 1588: m68k_run_1();
1589: else
1590: m68k_run_2();
1.1 root 1591: }
1.1.1.8 root 1592: unset_special(SPCFLAG_BRK);
1.1 root 1593: in_m68k_go--;
1594: }
1595:
1.1.1.8 root 1596:
1597: /*
1.1 root 1598: static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1599: {
1600: uae_u32 opcode, val;
1601: struct instr *dp;
1602:
1603: opcode = get_iword_1(0);
1604: last_op_for_exception_3 = opcode;
1605: m68kpc_offset = 2;
1606:
1.1.1.6 root 1607: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1608: opcode = 0x4AFC;
1609: }
1610: dp = table68k + opcode;
1611:
1612: if (dp->suse) {
1613: if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) {
1614: Exception (3, 0);
1615: return;
1616: }
1617: }
1618: if (dp->duse) {
1619: if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) {
1620: Exception (3, 0);
1621: return;
1622: }
1623: }
1624: }
1.1.1.8 root 1625: */
1626:
1.1 root 1627:
1628: void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1629: {
1.1.1.11 root 1630: static const char * const ccnames[] =
1.1.1.8 root 1631: { "T ","F ","HI","LS","CC","CS","NE","EQ",
1632: "VC","VS","PL","MI","GE","LT","GT","LE" };
1633:
1.1 root 1634: uaecptr newpc = 0;
1635: m68kpc_offset = addr - m68k_getpc ();
1636: while (cnt-- > 0) {
1637: char instrname[20],*ccpt;
1638: int opwords;
1639: uae_u32 opcode;
1.1.1.11 root 1640: const struct mnemolookup *lookup;
1.1 root 1641: struct instr *dp;
1642: fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset);
1643: for (opwords = 0; opwords < 5; opwords++){
1644: fprintf (f, "%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1645: }
1646: opcode = get_iword_1 (m68kpc_offset);
1647: m68kpc_offset += 2;
1.1.1.6 root 1648: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1649: opcode = 0x4AFC;
1650: }
1651: dp = table68k + opcode;
1652: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1653: ;
1654:
1655: strcpy (instrname, lookup->name);
1656: ccpt = strstr (instrname, "cc");
1657: if (ccpt != 0) {
1658: strncpy (ccpt, ccnames[dp->cc], 2);
1659: }
1660: fprintf (f, "%s", instrname);
1661: switch (dp->size){
1662: case sz_byte: fprintf (f, ".B "); break;
1663: case sz_word: fprintf (f, ".W "); break;
1664: case sz_long: fprintf (f, ".L "); break;
1665: default: fprintf (f, " "); break;
1666: }
1667:
1668: if (dp->suse) {
1669: newpc = m68k_getpc () + m68kpc_offset;
1670: newpc += ShowEA (f, dp->sreg, dp->smode, dp->size, 0);
1671: }
1672: if (dp->suse && dp->duse)
1673: fprintf (f, ",");
1674: if (dp->duse) {
1675: newpc = m68k_getpc () + m68kpc_offset;
1676: newpc += ShowEA (f, dp->dreg, dp->dmode, dp->size, 0);
1677: }
1678: if (ccpt != 0) {
1679: if (cctrue(dp->cc))
1.1.1.5 root 1680: fprintf (f, " == %08lx (TRUE)", (long)newpc);
1.1 root 1681: else
1.1.1.5 root 1682: fprintf (f, " == %08lx (FALSE)", (long)newpc);
1.1 root 1683: } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1.1.1.5 root 1684: fprintf (f, " == %08lx", (long)newpc);
1.1 root 1685: fprintf (f, "\n");
1686: }
1687: if (nextpc)
1688: *nextpc = m68k_getpc () + m68kpc_offset;
1689: }
1690:
1691: void m68k_dumpstate (FILE *f, uaecptr *nextpc)
1692: {
1693: int i;
1694: for (i = 0; i < 8; i++){
1.1.1.5 root 1695: fprintf (f, "D%d: %08lx ", i, (long)m68k_dreg(regs, i));
1.1 root 1696: if ((i & 3) == 3) fprintf (f, "\n");
1697: }
1698: for (i = 0; i < 8; i++){
1.1.1.5 root 1699: fprintf (f, "A%d: %08lx ", i, (long)m68k_areg(regs, i));
1.1 root 1700: if ((i & 3) == 3) fprintf (f, "\n");
1701: }
1702: if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1703: if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1704: if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1705: fprintf (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1.1.1.5 root 1706: (long)regs.usp,(long)regs.isp,(long)regs.msp,(long)regs.vbr);
1.1 root 1707: fprintf (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1708: regs.t1, regs.t0, regs.s, regs.m,
1709: GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1710: for (i = 0; i < 8; i++){
1711: fprintf (f, "FP%d: %g ", i, regs.fp[i]);
1712: if ((i & 3) == 3) fprintf (f, "\n");
1713: }
1714: fprintf (f, "N=%d Z=%d I=%d NAN=%d\n",
1715: (regs.fpsr & 0x8000000) != 0,
1716: (regs.fpsr & 0x4000000) != 0,
1717: (regs.fpsr & 0x2000000) != 0,
1718: (regs.fpsr & 0x1000000) != 0);
1.1.1.12! root 1719: if (currprefs.cpu_compatible)
1.1 root 1720: fprintf (f, "prefetch %08lx\n", (unsigned long)do_get_mem_long(®s.prefetch));
1721:
1722: m68k_disasm (f, m68k_getpc (), nextpc, 1);
1723: if (nextpc)
1.1.1.5 root 1724: fprintf (f, "next PC: %08lx\n", (long)*nextpc);
1.1 root 1725: }
1.1.1.12! root 1726:
! 1727:
! 1728: /*
! 1729:
! 1730: The routines below take dividend and divisor as parameters.
! 1731: They return 0 if division by zero, or exact number of cycles otherwise.
! 1732:
! 1733: The number of cycles returned assumes a register operand.
! 1734: Effective address time must be added if memory operand.
! 1735:
! 1736: For 68000 only (not 68010, 68012, 68020, etc).
! 1737: Probably valid for 68008 after adding the extra prefetch cycle.
! 1738:
! 1739:
! 1740: Best and worst cases are for register operand:
! 1741: (Note the difference with the documented range.)
! 1742:
! 1743:
! 1744: DIVU:
! 1745:
! 1746: Overflow (always): 10 cycles.
! 1747: Worst case: 136 cycles.
! 1748: Best case: 76 cycles.
! 1749:
! 1750:
! 1751: DIVS:
! 1752:
! 1753: Absolute overflow: 16-18 cycles.
! 1754: Signed overflow is not detected prematurely.
! 1755:
! 1756: Worst case: 156 cycles.
! 1757: Best case without signed overflow: 122 cycles.
! 1758: Best case with signed overflow: 120 cycles
! 1759:
! 1760:
! 1761: */
! 1762:
! 1763:
! 1764: //
! 1765: // DIVU
! 1766: // Unsigned division
! 1767: //
! 1768:
! 1769: STATIC_INLINE int getDivu68kCycles_2 (uae_u32 dividend, uae_u16 divisor)
! 1770: {
! 1771: int mcycles;
! 1772: uae_u32 hdivisor;
! 1773: int i;
! 1774:
! 1775: if (divisor == 0)
! 1776: return 0;
! 1777:
! 1778: // Overflow
! 1779: if ((dividend >> 16) >= divisor)
! 1780: return (mcycles = 5) * 2;
! 1781:
! 1782: mcycles = 38;
! 1783: hdivisor = divisor << 16;
! 1784:
! 1785: for (i = 0; i < 15; i++) {
! 1786: uae_u32 temp;
! 1787: temp = dividend;
! 1788:
! 1789: dividend <<= 1;
! 1790:
! 1791: // If carry from shift
! 1792: if ((uae_s32)temp < 0)
! 1793: dividend -= hdivisor;
! 1794: else {
! 1795: mcycles += 2;
! 1796: if (dividend >= hdivisor) {
! 1797: dividend -= hdivisor;
! 1798: mcycles--;
! 1799: }
! 1800: }
! 1801: }
! 1802: return mcycles * 2;
! 1803: }
! 1804: int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor)
! 1805: {
! 1806: int v = getDivu68kCycles_2 (dividend, divisor) - 4;
! 1807: // write_log ("U%d ", v);
! 1808: return v;
! 1809: }
! 1810:
! 1811: //
! 1812: // DIVS
! 1813: // Signed division
! 1814: //
! 1815:
! 1816: STATIC_INLINE int getDivs68kCycles_2 (uae_s32 dividend, uae_s16 divisor)
! 1817: {
! 1818: int mcycles;
! 1819: uae_u32 aquot;
! 1820: int i;
! 1821:
! 1822: if (divisor == 0)
! 1823: return 0;
! 1824:
! 1825: mcycles = 6;
! 1826:
! 1827: if (dividend < 0)
! 1828: mcycles++;
! 1829:
! 1830: // Check for absolute overflow
! 1831: if (((uae_u32)abs (dividend) >> 16) >= (uae_u16)abs (divisor))
! 1832: return (mcycles + 2) * 2;
! 1833:
! 1834: // Absolute quotient
! 1835: aquot = (uae_u32) abs (dividend) / (uae_u16)abs (divisor);
! 1836:
! 1837: mcycles += 55;
! 1838:
! 1839: if (divisor >= 0) {
! 1840: if (dividend >= 0)
! 1841: mcycles--;
! 1842: else
! 1843: mcycles++;
! 1844: }
! 1845:
! 1846: // Count 15 msbits in absolute of quotient
! 1847:
! 1848: for (i = 0; i < 15; i++) {
! 1849: if ((uae_s16)aquot >= 0)
! 1850: mcycles++;
! 1851: aquot <<= 1;
! 1852: }
! 1853:
! 1854: return mcycles * 2;
! 1855: }
! 1856: int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor)
! 1857: {
! 1858: int v = getDivs68kCycles_2 (dividend, divisor) - 4;
! 1859: // write_log ("S%d ", v);
! 1860: return v;
! 1861: }
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