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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation
5: *
6: * (c) 1995 Bernd Schmidt
1.1.1.2 root 7: *
8: * Adaptation to Hatari by Thomas Huth
9: *
1.1.1.6 root 10: * This file is distributed under the GNU Public License, version 2 or at
11: * your option any later version. Read the file gpl.txt for details.
1.1 root 12: */
1.1.1.12 root 13:
14:
15: /* 2007/11/12 [NP] Add HATARI_TRACE_CPU_DISASM. */
16: /* 2007/11/15 [NP] In MakeFromSR, writes to m and t0 should be ignored and set to 0 if cpu < 68020 */
17: /* 2007/11/26 [NP] We set BusErrorPC in m68k_run_1 instead of M68000_BusError, else the BusErrorPC */
18: /* will not point to the opcode that generated the bus error. */
19: /* Huge debug/work on Exceptions 2/3 stack frames, result is more accurate and */
20: /* allow to pass the very tricky Transbeauce 2 Demo's protection. */
21: /* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */
22: /* Cwik, [email protected]). */
23: /* 2007/12/06 [NP] The PC stored in the stack frame for the bus error is complex to emulate, */
24: /* because it doesn't necessarily point to the next instruction after the one that */
25: /* triggered the bus error. In the case of the Transbeauce 2 Demo, after */
26: /* 'move.l $0.w,$24.w', PC is incremented of 4 bytes, not 6, and stored in the */
27: /* stack. Special case to decrement PC of 2 bytes if opcode is '21f8'. */
28: /* This should be fixed with a real model. */
29: /* 2007/12/07 [NP] If Trace is enabled and a group 2 exception occurs (such as CHK), the trace */
30: /* handler should be called after the group 2's handler. If a bus error, address */
31: /* error or illegal occurs while Trace is enabled, the trace handler should not be */
32: /* called after this instruction (Transbeauce 2 Demo, Phaleon Demo). */
33: /* This means that if a CHK is executed while trace bit was set, we must set PC */
34: /* to CHK handler, turn trace off in the internal SR, but we must still call the */
35: /* trace handler one last time with the PC set to the CHK's handler (even if */
36: /* trace mode is internally turned off while processing an exception). Once trace */
37: /* handler is finished (RTE), we return to the CHK's handler. */
38: /* This is true for DIV BY 0, CHK, TRAPV and TRAP. */
39: /* Backport exception_trace() from WinUAE to handle this behaviour (used in */
40: /* Transbeauce 2 demo). */
41: /* 2007/12/09 [NP] 'dc.w $a' should not be used to call 'OpCode_SysInit' but should give an illegal*/
42: /* instruction (Transbeauce 2 demo). */
43: /* Instead of always replacing the illegal instructions $8, $a and $c by the */
44: /* 3 functions required for HD emulation, we now do it in cart.c only if the */
45: /* built-in cartridge image is loaded. */
46: /* YEAH! Hatari is now the first emulator to pass the Transbeauce 2 protection :) */
47: /* 2007/12/18 [NP] More precise timings for HBL, VBL and MFP interrupts. On ST, these interrupts */
48: /* are taking 56 cycles instead of the 44 cycles in the 68000's documentation. */
49: /* 2007/12/24 [NP] If an interrupt (HBL, VBL) is pending after intruction 'n' was processed, the */
50: /* exception should be called before instr. 'n+1' is processed, not after (else the*/
51: /* interrupt's handler is delayed by one 68000's instruction, which could break */
52: /* some demos with too strict timings) (ACF's Demo Main Menu). */
53: /* We call the interrupt if ( SPCFLAG_INT | SPCFLAG_DOINT ) is set, not only if */
54: /* SPCFLAG_DOINT is set (as it was already the case when handling 'STOP'). */
55: /* 2007/12/25 [NP] FIXME When handling exceptions' cycles, using nr >= 64 to determine if this is */
56: /* an MFP exception could be wrong if the MFP VR was set to another value than the */
57: /* default $40 (this could be a problem with programs requiring a precise cycles */
58: /* calculation while changing VR, but no such programs were encountered so far). */
1.1.1.13! root 59: /* -> FIXED, see 2008/10/05 */
! 60: /* 2008/04/17 [NP] In m68k_run_1/m68k_run_2, add the wait state cycles before testing if content */
! 61: /* of PendingInterruptCount is <= 0 (else the int could happen a few cycles earlier*/
! 62: /* than expected in some rare cases (reading $fffa21 in BIG Demo Screen 1)). */
! 63: /* 2008/09/14 [NP] Add the value of the new PC in the exception's log. */
! 64: /* 2008/09/14 [NP] Correct cycles for TRAP are 34 not 38 (4 more cycles were counted because cpuemu*/
! 65: /* returns 4 and Exception() adds 34) (Phaleon / Illusion Demo by Next). */
! 66: /* FIXME : Others exception cycles may be wrong too. */
! 67: /* 2008/10/05 [NP] Add a parameter 'ExceptionSource' to Exception(). This allows to know the source*/
! 68: /* of the exception (video, mfp, cpu) and properly handle MFP interrupts. Since */
! 69: /* it's possible to change the vector base in $fffa17, MFP int vectors can overlap */
! 70: /* the 'normal' 68000 ones and the exception number is not enough to decide. */
! 71: /* We need ExceptionSource to remove the ambiguity. */
! 72: /* Fix High Fidelity Dreams by Aura which sets MFP vector base to $c0 instead of */
! 73: /* $100. In that case, timer B int becomes exception nr 56 and conflicts with the */
! 74: /* 'MMU config error' exception, which takes 4 cycles instead of 56 cycles for MFP.*/
! 75: /* 2008/11/18 [NP] In 'do_specialties()', when the cpu is in the STOP state, we must test all */
! 76: /* possible int handlers while PendingInterruptCount <= 0 without increasing the */
! 77: /* cpu cycle counter. In the case where both an MFP int and an HBL occur at the */
! 78: /* same time for example, the HBL was delayed by 4 bytes if no MFP exception */
! 79: /* was triggered, which was wrong (this happened mainly with the TOS timer D that */
! 80: /* expires very often). Such precision is required for very recent hardscroll */
! 81: /* techniques that use 'stop' to stay in sync with the video shifter. */
1.1.1.12 root 82:
83:
84:
1.1.1.13! root 85: const char NewCpu_rcsid[] = "Hatari $Id: newcpu.c,v 1.61 2008/11/17 23:13:01 npomarede Exp $";
1.1 root 86:
87: #include "sysdeps.h"
88: #include "hatari-glue.h"
89: #include "maccess.h"
90: #include "memory.h"
91: #include "newcpu.h"
1.1.1.5 root 92: #include "../includes/main.h"
1.1.1.10 root 93: #include "../includes/log.h"
1.1.1.7 root 94: #include "../includes/m68000.h"
1.1.1.12 root 95: #include "../includes/int.h"
1.1.1.8 root 96: #include "../includes/mfp.h"
1.1 root 97: #include "../includes/tos.h"
1.1.1.5 root 98: #include "../includes/vdi.h"
99: #include "../includes/cart.h"
100: #include "../includes/debugui.h"
1.1.1.8 root 101: #include "../includes/bios.h"
102: #include "../includes/xbios.h"
1.1.1.12 root 103: #include "../includes/video.h"
1.1.1.13! root 104: #include "../includes/options.h"
1.1 root 105:
1.1.1.12 root 106: //#define DEBUG_PREFETCH
1.1 root 107:
108: struct flag_struct regflags;
109:
110: /* Opcode of faulting instruction */
111: uae_u16 last_op_for_exception_3;
112: /* PC at fault time */
113: uaecptr last_addr_for_exception_3;
114: /* Address that generated the exception */
115: uaecptr last_fault_for_exception_3;
116:
1.1.1.11 root 117: const int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
118: const int imm8_table[] = { 8,1,2,3,4,5,6,7 };
1.1 root 119:
120: int movem_index1[256];
121: int movem_index2[256];
122: int movem_next[256];
123:
124: int fpp_movem_index1[256];
125: int fpp_movem_index2[256];
126: int fpp_movem_next[256];
127:
128: cpuop_func *cpufunctbl[65536];
129:
1.1.1.12 root 130: int OpcodeFamily;
1.1.1.6 root 131:
1.1 root 132: #define COUNT_INSTRS 0
133:
134: #if COUNT_INSTRS
135: static unsigned long int instrcount[65536];
136: static uae_u16 opcodenums[65536];
137:
138: static int compfn (const void *el1, const void *el2)
139: {
140: return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
141: }
142:
143: static char *icountfilename (void)
144: {
145: char *name = getenv ("INSNCOUNT");
146: if (name)
147: return name;
148: return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
149: }
150:
151: void dump_counts (void)
152: {
153: FILE *f = fopen (icountfilename (), "w");
154: unsigned long int total;
155: int i;
156:
157: write_log ("Writing instruction count file...\n");
158: for (i = 0; i < 65536; i++) {
159: opcodenums[i] = i;
160: total += instrcount[i];
161: }
162: qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
163:
164: fprintf (f, "Total: %lu\n", total);
165: for (i=0; i < 65536; i++) {
166: unsigned long int cnt = instrcount[opcodenums[i]];
167: struct instr *dp;
168: struct mnemolookup *lookup;
169: if (!cnt)
170: break;
171: dp = table68k + opcodenums[i];
172: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
173: ;
174: fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
175: }
176: fclose (f);
177: }
178: #else
179: void dump_counts (void)
180: {
181: }
182: #endif
183:
184:
185: static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM;
186:
187: static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
188: {
1.1.1.6 root 189: op_illg (opcode);
1.1 root 190: return 4;
191: }
192:
1.1.1.4 root 193:
194: void build_cpufunctbl(void)
1.1 root 195: {
196: int i;
197: unsigned long opcode;
1.1.1.12 root 198: const struct cputbl *tbl = (currprefs.cpu_level == 4 ? op_smalltbl_0_ff
199: : currprefs.cpu_level == 3 ? op_smalltbl_1_ff
200: : currprefs.cpu_level == 2 ? op_smalltbl_2_ff
201: : currprefs.cpu_level == 1 ? op_smalltbl_3_ff
202: : ! currprefs.cpu_compatible ? op_smalltbl_4_ff
1.1.1.11 root 203: : op_smalltbl_5_ff);
1.1 root 204:
1.1.1.10 root 205: Log_Printf(LOG_DEBUG, "Building CPU function table (%d %d %d).\n",
1.1.1.12 root 206: currprefs.cpu_level, currprefs.cpu_compatible, currprefs.address_space_24);
1.1 root 207:
208: for (opcode = 0; opcode < 65536; opcode++)
1.1.1.6 root 209: cpufunctbl[opcode] = op_illg_1;
1.1 root 210: for (i = 0; tbl[i].handler != NULL; i++) {
211: if (! tbl[i].specific)
1.1.1.6 root 212: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 213: }
214: for (opcode = 0; opcode < 65536; opcode++) {
215: cpuop_func *f;
216:
1.1.1.12 root 217: if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > currprefs.cpu_level)
1.1 root 218: continue;
219:
220: if (table68k[opcode].handler != -1) {
1.1.1.6 root 221: f = cpufunctbl[table68k[opcode].handler];
1.1 root 222: if (f == op_illg_1)
223: abort();
1.1.1.6 root 224: cpufunctbl[opcode] = f;
1.1 root 225: }
226: }
227: for (i = 0; tbl[i].handler != NULL; i++) {
228: if (tbl[i].specific)
1.1.1.6 root 229: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 230: }
231: }
232:
233:
234:
235: void init_m68k (void)
236: {
237: int i;
238:
239: for (i = 0 ; i < 256 ; i++) {
240: int j;
241: for (j = 0 ; j < 8 ; j++) {
242: if (i & (1 << j)) break;
243: }
244: movem_index1[i] = j;
245: movem_index2[i] = 7-j;
246: movem_next[i] = i & (~(1 << j));
247: }
248: for (i = 0 ; i < 256 ; i++) {
249: int j;
250: for (j = 7 ; j >= 0 ; j--) {
251: if (i & (1 << j)) break;
252: }
253: fpp_movem_index1[i] = 7-j;
254: fpp_movem_index2[i] = j;
255: fpp_movem_next[i] = i & (~(1 << j));
256: }
257: #if COUNT_INSTRS
258: {
259: FILE *f = fopen (icountfilename (), "r");
260: memset (instrcount, 0, sizeof instrcount);
261: if (f) {
262: uae_u32 opcode, count, total;
263: char name[20];
264: write_log ("Reading instruction count file...\n");
265: fscanf (f, "Total: %lu\n", &total);
266: while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
267: instrcount[opcode] = count;
268: }
269: fclose(f);
270: }
271: }
272: #endif
273: write_log ("Building CPU table for configuration: 68");
1.1.1.12 root 274: if (currprefs.address_space_24 && currprefs.cpu_level > 1)
1.1 root 275: write_log ("EC");
1.1.1.12 root 276: switch (currprefs.cpu_level) {
1.1 root 277: case 1:
278: write_log ("010");
279: break;
280: case 2:
281: write_log ("020");
282: break;
283: case 3:
284: write_log ("020/881");
285: break;
286: case 4:
287: /* Who is going to miss the MMU anyway...? :-) */
288: write_log ("040");
289: break;
290: default:
291: write_log ("000");
292: break;
293: }
1.1.1.12 root 294: if (currprefs.cpu_compatible)
1.1 root 295: write_log (" (compatible mode)");
296: write_log ("\n");
1.1.1.7 root 297:
1.1 root 298: read_table68k ();
299: do_merges ();
300:
1.1.1.10 root 301: Log_Printf(LOG_DEBUG, "%d CPU functions\n", nr_cpuop_funcs);
1.1 root 302:
303: build_cpufunctbl ();
304: }
305:
1.1.1.4 root 306:
1.1.1.8 root 307: /* not used ATM:
1.1 root 308: static struct regstruct regs_backup[16];
309: static int backup_pointer = 0;
1.1.1.10 root 310: struct regstruct lastint_regs;
311: int lastint_no;
1.1.1.8 root 312: */
1.1.1.10 root 313: struct regstruct regs;
1.1 root 314: static long int m68kpc_offset;
1.1.1.10 root 315:
1.1 root 316:
317: #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
318: #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
319: #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
320:
321: uae_s32 ShowEA (FILE *f, int reg, amodes mode, wordsizes size, char *buf)
322: {
323: uae_u16 dp;
324: uae_s8 disp8;
325: uae_s16 disp16;
326: int r;
327: uae_u32 dispreg;
328: uaecptr addr;
329: uae_s32 offset = 0;
330: char buffer[80];
331:
332: switch (mode){
333: case Dreg:
334: sprintf (buffer,"D%d", reg);
335: break;
336: case Areg:
337: sprintf (buffer,"A%d", reg);
338: break;
339: case Aind:
340: sprintf (buffer,"(A%d)", reg);
341: break;
342: case Aipi:
343: sprintf (buffer,"(A%d)+", reg);
344: break;
345: case Apdi:
346: sprintf (buffer,"-(A%d)", reg);
347: break;
348: case Ad16:
349: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
350: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
351: sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
352: (unsigned long)addr);
353: break;
354: case Ad8r:
355: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
356: disp8 = dp & 0xFF;
357: r = (dp & 0x7000) >> 12;
358: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
359: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
360: dispreg <<= (dp >> 9) & 3;
361:
362: if (dp & 0x100) {
363: uae_s32 outer = 0, disp = 0;
364: uae_s32 base = m68k_areg(regs,reg);
365: char name[10];
366: sprintf (name,"A%d, ",reg);
367: if (dp & 0x80) { base = 0; name[0] = 0; }
368: if (dp & 0x40) dispreg = 0;
369: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
370: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
371: base += disp;
372:
373: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
374: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
375:
376: if (!(dp & 4)) base += dispreg;
377: if (dp & 3) base = get_long (base);
378: if (dp & 4) base += dispreg;
379:
380: addr = base + outer;
381: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
382: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
383: 1 << ((dp >> 9) & 3),
1.1.1.5 root 384: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 385: } else {
386: addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
387: sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
388: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
389: 1 << ((dp >> 9) & 3), disp8,
390: (unsigned long)addr);
391: }
392: break;
393: case PC16:
394: addr = m68k_getpc () + m68kpc_offset;
395: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
396: addr += (uae_s16)disp16;
397: sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
398: break;
399: case PC8r:
400: addr = m68k_getpc () + m68kpc_offset;
401: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
402: disp8 = dp & 0xFF;
403: r = (dp & 0x7000) >> 12;
404: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
405: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
406: dispreg <<= (dp >> 9) & 3;
407:
408: if (dp & 0x100) {
409: uae_s32 outer = 0,disp = 0;
410: uae_s32 base = addr;
411: char name[10];
412: sprintf (name,"PC, ");
413: if (dp & 0x80) { base = 0; name[0] = 0; }
414: if (dp & 0x40) dispreg = 0;
415: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
416: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
417: base += disp;
418:
419: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
420: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
421:
422: if (!(dp & 4)) base += dispreg;
423: if (dp & 3) base = get_long (base);
424: if (dp & 4) base += dispreg;
425:
426: addr = base + outer;
427: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
428: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
429: 1 << ((dp >> 9) & 3),
1.1.1.5 root 430: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 431: } else {
432: addr += (uae_s32)((uae_s8)disp8) + dispreg;
433: sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
434: (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
435: disp8, (unsigned long)addr);
436: }
437: break;
438: case absw:
439: sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
440: m68kpc_offset += 2;
441: break;
442: case absl:
443: sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
444: m68kpc_offset += 4;
445: break;
446: case imm:
447: switch (size){
448: case sz_byte:
449: sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
450: m68kpc_offset += 2;
451: break;
452: case sz_word:
453: sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
454: m68kpc_offset += 2;
455: break;
456: case sz_long:
457: sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
458: m68kpc_offset += 4;
459: break;
460: default:
461: break;
462: }
463: break;
464: case imm0:
465: offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
466: m68kpc_offset += 2;
467: sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
468: break;
469: case imm1:
470: offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
471: m68kpc_offset += 2;
472: sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
473: break;
474: case imm2:
475: offset = (uae_s32)get_ilong_1 (m68kpc_offset);
476: m68kpc_offset += 4;
477: sprintf (buffer,"#$%08lx", (unsigned long)offset);
478: break;
479: case immi:
480: offset = (uae_s32)(uae_s8)(reg & 0xff);
481: sprintf (buffer,"#$%08lx", (unsigned long)offset);
482: break;
483: default:
484: break;
485: }
486: if (buf == 0)
487: fprintf (f, "%s", buffer);
488: else
489: strcat (buf, buffer);
490: return offset;
491: }
492:
1.1.1.8 root 493:
1.1 root 494: /* The plan is that this will take over the job of exception 3 handling -
495: * the CPU emulation functions will just do a longjmp to m68k_go whenever
496: * they hit an odd address. */
1.1.1.8 root 497: #if 0
1.1 root 498: static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
499: {
500: uae_u16 dp;
501: uae_s8 disp8;
502: uae_s16 disp16;
503: int r;
504: uae_u32 dispreg;
505: uaecptr addr;
1.1.1.5 root 506: /*uae_s32 offset = 0;*/
1.1 root 507:
508: switch (mode){
509: case Dreg:
510: *val = m68k_dreg (regs, reg);
511: return 1;
512: case Areg:
513: *val = m68k_areg (regs, reg);
514: return 1;
515:
516: case Aind:
517: case Aipi:
518: addr = m68k_areg (regs, reg);
519: break;
520: case Apdi:
521: addr = m68k_areg (regs, reg);
522: break;
523: case Ad16:
524: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
525: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
526: break;
527: case Ad8r:
528: addr = m68k_areg (regs, reg);
529: d8r_common:
530: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
531: disp8 = dp & 0xFF;
532: r = (dp & 0x7000) >> 12;
533: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
534: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
535: dispreg <<= (dp >> 9) & 3;
536:
537: if (dp & 0x100) {
538: uae_s32 outer = 0, disp = 0;
539: uae_s32 base = addr;
540: if (dp & 0x80) base = 0;
541: if (dp & 0x40) dispreg = 0;
542: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
543: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
544: base += disp;
545:
546: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
547: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
548:
549: if (!(dp & 4)) base += dispreg;
550: if (dp & 3) base = get_long (base);
551: if (dp & 4) base += dispreg;
552:
553: addr = base + outer;
554: } else {
555: addr += (uae_s32)((uae_s8)disp8) + dispreg;
556: }
557: break;
558: case PC16:
559: addr = m68k_getpc () + m68kpc_offset;
560: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
561: addr += (uae_s16)disp16;
562: break;
563: case PC8r:
564: addr = m68k_getpc () + m68kpc_offset;
565: goto d8r_common;
566: case absw:
567: addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
568: m68kpc_offset += 2;
569: break;
570: case absl:
571: addr = get_ilong_1 (m68kpc_offset);
572: m68kpc_offset += 4;
573: break;
574: case imm:
575: switch (size){
576: case sz_byte:
577: *val = get_iword_1 (m68kpc_offset) & 0xff;
578: m68kpc_offset += 2;
579: break;
580: case sz_word:
581: *val = get_iword_1 (m68kpc_offset) & 0xffff;
582: m68kpc_offset += 2;
583: break;
584: case sz_long:
585: *val = get_ilong_1 (m68kpc_offset);
586: m68kpc_offset += 4;
587: break;
588: default:
589: break;
590: }
591: return 1;
592: case imm0:
593: *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
594: m68kpc_offset += 2;
595: return 1;
596: case imm1:
597: *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
598: m68kpc_offset += 2;
599: return 1;
600: case imm2:
601: *val = get_ilong_1 (m68kpc_offset);
602: m68kpc_offset += 4;
603: return 1;
604: case immi:
605: *val = (uae_s32)(uae_s8)(reg & 0xff);
606: return 1;
607: default:
608: addr = 0;
609: break;
610: }
611: if ((addr & 1) == 0)
612: return 1;
613:
614: last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
615: last_fault_for_exception_3 = addr;
616: return 0;
617: }
1.1.1.8 root 618: #endif
619:
1.1 root 620:
621: uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
622: {
623: int reg = (dp >> 12) & 15;
624: uae_s32 regd = regs.regs[reg];
625: if ((dp & 0x800) == 0)
626: regd = (uae_s32)(uae_s16)regd;
627: regd <<= (dp >> 9) & 3;
628: if (dp & 0x100) {
629: uae_s32 outer = 0;
630: if (dp & 0x80) base = 0;
631: if (dp & 0x40) regd = 0;
632:
633: if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
634: if ((dp & 0x30) == 0x30) base += next_ilong();
635:
636: if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
637: if ((dp & 0x3) == 0x3) outer = next_ilong();
638:
639: if ((dp & 0x4) == 0) base += regd;
640: if (dp & 0x3) base = get_long (base);
641: if (dp & 0x4) base += regd;
642:
643: return base + outer;
644: } else {
645: return base + (uae_s32)((uae_s8)dp) + regd;
646: }
647: }
648:
649: uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
650: {
651: int reg = (dp >> 12) & 15;
652: uae_s32 regd = regs.regs[reg];
653: #if 1
654: if ((dp & 0x800) == 0)
655: regd = (uae_s32)(uae_s16)regd;
656: return base + (uae_s8)dp + regd;
657: #else
658: /* Branch-free code... benchmark this again now that
659: * things are no longer inline. */
660: uae_s32 regd16;
661: uae_u32 mask;
662: mask = ((dp & 0x800) >> 11) - 1;
663: regd16 = (uae_s32)(uae_s16)regd;
664: regd16 &= mask;
665: mask = ~mask;
666: base += (uae_s8)dp;
667: regd &= mask;
668: regd |= regd16;
669: return base + regd;
670: #endif
671: }
672:
1.1.1.8 root 673:
674: /* Create the Status Register from the flags */
1.1 root 675: void MakeSR (void)
676: {
677: #if 0
678: assert((regs.t1 & 1) == regs.t1);
679: assert((regs.t0 & 1) == regs.t0);
680: assert((regs.s & 1) == regs.s);
681: assert((regs.m & 1) == regs.m);
682: assert((XFLG & 1) == XFLG);
683: assert((NFLG & 1) == NFLG);
684: assert((ZFLG & 1) == ZFLG);
685: assert((VFLG & 1) == VFLG);
686: assert((CFLG & 1) == CFLG);
687: #endif
688: regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
689: | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
690: | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
691: | GET_CFLG);
692: }
693:
1.1.1.8 root 694:
695: /* Set up the flags from Status Register */
1.1 root 696: void MakeFromSR (void)
697: {
698: int oldm = regs.m;
699: int olds = regs.s;
700:
701: regs.t1 = (regs.sr >> 15) & 1;
702: regs.t0 = (regs.sr >> 14) & 1;
703: regs.s = (regs.sr >> 13) & 1;
704: regs.m = (regs.sr >> 12) & 1;
705: regs.intmask = (regs.sr >> 8) & 7;
706: SET_XFLG ((regs.sr >> 4) & 1);
707: SET_NFLG ((regs.sr >> 3) & 1);
708: SET_ZFLG ((regs.sr >> 2) & 1);
709: SET_VFLG ((regs.sr >> 1) & 1);
710: SET_CFLG (regs.sr & 1);
1.1.1.12 root 711: if (currprefs.cpu_level >= 2) {
1.1 root 712: if (olds != regs.s) {
713: if (olds) {
714: if (oldm)
715: regs.msp = m68k_areg(regs, 7);
716: else
717: regs.isp = m68k_areg(regs, 7);
718: m68k_areg(regs, 7) = regs.usp;
719: } else {
720: regs.usp = m68k_areg(regs, 7);
721: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
722: }
723: } else if (olds && oldm != regs.m) {
724: if (oldm) {
725: regs.msp = m68k_areg(regs, 7);
726: m68k_areg(regs, 7) = regs.isp;
727: } else {
728: regs.isp = m68k_areg(regs, 7);
729: m68k_areg(regs, 7) = regs.msp;
730: }
731: }
732: } else {
1.1.1.12 root 733: /* [NP] If cpu < 68020, m and t0 are ignored and should be set to 0 */
734: regs.t0 = 0;
735: regs.m = 0;
736:
1.1 root 737: if (olds != regs.s) {
738: if (olds) {
739: regs.isp = m68k_areg(regs, 7);
740: m68k_areg(regs, 7) = regs.usp;
741: } else {
742: regs.usp = m68k_areg(regs, 7);
743: m68k_areg(regs, 7) = regs.isp;
744: }
745: }
746: }
747:
1.1.1.8 root 748: /* Pending interrupts can occur again after a write to the SR: */
749: set_special (SPCFLAG_DOINT);
1.1 root 750: if (regs.t1 || regs.t0)
751: set_special (SPCFLAG_TRACE);
752: else
1.1.1.6 root 753: /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
754: SR-modifying instructions (including STOP). */
755: unset_special (SPCFLAG_TRACE);
1.1 root 756: }
757:
1.1.1.5 root 758:
1.1.1.12 root 759: static void exception_trace (int nr)
760: {
761: unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
762: if (regs.t1 && !regs.t0) {
763: /* trace stays pending if exception is div by zero, chk,
764: * trapv or trap #x
765: */
766: if (nr == 5 || nr == 6 || nr == 7 || (nr >= 32 && nr <= 47))
767: set_special (SPCFLAG_DOTRACE);
768: }
769: regs.t1 = regs.t0 = regs.m = 0;
770: }
771:
772:
1.1.1.13! root 773: /* Handle exceptions. We need a special case to handle MFP exceptions */
! 774: /* on Atari ST, because it's possible to change the MFP's vector base */
! 775: /* and get a conflict with 'normal' cpu exceptions. */
! 776: void Exception(int nr, uaecptr oldpc, int ExceptionSource)
1.1 root 777: {
778: uae_u32 currpc = m68k_getpc ();
779:
1.1.1.2 root 780: /*if( nr>=2 && nr<10 ) fprintf(stderr,"Exception (-> %i bombs)!\n",nr);*/
1.1 root 781:
1.1.1.7 root 782: /* Intercept VDI exception (Trap #2 with D0 = 0x73) */
1.1.1.13! root 783: if ( ExceptionSource != M68000_EXCEPTION_SRC_INT_MFP )
1.1.1.5 root 784: {
1.1.1.13! root 785: if(bUseVDIRes && nr == 0x22 && regs.regs[0] == 0x73)
! 786: {
! 787: if(!VDI())
! 788: {
! 789: /* Set 'PC' as address of 'VDI_OPCODE' illegal instruction
! 790: * This will call OpCode_VDI after completion of Trap call!
! 791: * Use to modify return structure from VDI */
! 792: VDI_OldPC = currpc;
! 793: currpc = CART_VDI_OPCODE_ADDR;
! 794: }
! 795: }
! 796:
! 797: if (bBiosIntercept)
! 798: {
! 799: /* Intercept BIOS or XBIOS trap (Trap #13 or #14) */
! 800: if (nr == 0x2d)
! 801: {
! 802: /* Intercept BIOS calls */
! 803: if (Bios()) return;
! 804: }
! 805: else if (nr == 0x2e)
! 806: {
! 807: /* Intercept XBIOS calls */
! 808: if (XBios()) return;
! 809: }
! 810: }
1.1.1.5 root 811: }
1.1.1.8 root 812:
1.1 root 813: MakeSR();
814:
1.1.1.8 root 815: /* Change to supervisor mode if necessary */
1.1 root 816: if (!regs.s) {
817: regs.usp = m68k_areg(regs, 7);
1.1.1.12 root 818: if (currprefs.cpu_level >= 2)
1.1 root 819: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
820: else
821: m68k_areg(regs, 7) = regs.isp;
822: regs.s = 1;
823: }
1.1.1.8 root 824:
825: /* Build additional exception stack frame for 68010 and higher */
1.1.1.13! root 826: /* (special case for MFP) */
1.1.1.12 root 827: if (currprefs.cpu_level > 0) {
1.1.1.13! root 828: if (ExceptionSource == M68000_EXCEPTION_SRC_INT_MFP) {
! 829: m68k_areg(regs, 7) -= 2;
! 830: put_word (m68k_areg(regs, 7), nr * 4); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
! 831: }
! 832: else if (nr == 2 || nr == 3) {
1.1 root 833: int i;
834: /* @@@ this is probably wrong (?) */
835: for (i = 0 ; i < 12 ; i++) {
836: m68k_areg(regs, 7) -= 2;
837: put_word (m68k_areg(regs, 7), 0);
838: }
839: m68k_areg(regs, 7) -= 2;
840: put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
841: } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
842: m68k_areg(regs, 7) -= 4;
843: put_long (m68k_areg(regs, 7), oldpc);
844: m68k_areg(regs, 7) -= 2;
845: put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
846: } else if (regs.m && nr >= 24 && nr < 32) {
847: m68k_areg(regs, 7) -= 2;
848: put_word (m68k_areg(regs, 7), nr * 4);
849: m68k_areg(regs, 7) -= 4;
850: put_long (m68k_areg(regs, 7), currpc);
851: m68k_areg(regs, 7) -= 2;
852: put_word (m68k_areg(regs, 7), regs.sr);
853: regs.sr |= (1 << 13);
854: regs.msp = m68k_areg(regs, 7);
855: m68k_areg(regs, 7) = regs.isp;
856: m68k_areg(regs, 7) -= 2;
857: put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
858: } else {
859: m68k_areg(regs, 7) -= 2;
860: put_word (m68k_areg(regs, 7), nr * 4);
861: }
862: }
1.1.1.3 root 863:
864: /* Push PC on stack: */
1.1 root 865: m68k_areg(regs, 7) -= 4;
866: put_long (m68k_areg(regs, 7), currpc);
1.1.1.3 root 867: /* Push SR on stack: */
1.1 root 868: m68k_areg(regs, 7) -= 2;
869: put_word (m68k_areg(regs, 7), regs.sr);
1.1.1.3 root 870:
1.1.1.13! root 871: HATARI_TRACE ( HATARI_TRACE_CPU_EXCEPTION , "cpu exception %d currpc %x buspc %x newpc %x fault_e3 %x op_e3 %hx addr_e3 %x\n" ,
! 872: nr, currpc, BusErrorPC, get_long (regs.vbr + 4*nr), last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3 );
1.1.1.12 root 873:
1.1.1.3 root 874: /* 68000 bus/address errors: */
1.1.1.13! root 875: if (currprefs.cpu_level==0 && (nr==2 || nr==3) && (ExceptionSource != M68000_EXCEPTION_SRC_INT_MFP) ) {
1.1.1.12 root 876: uae_u16 specialstatus = 1;
877:
1.1.1.8 root 878: /* Special status word emulation isn't perfect yet... :-( */
879: if (regs.sr & 0x2000)
880: specialstatus |= 0x4;
1.1.1.3 root 881: m68k_areg(regs, 7) -= 8;
882: if (nr == 3) { /* Address error */
1.1.1.12 root 883: specialstatus |= ( last_op_for_exception_3 & (~0x1f) ); /* [NP] unused bits of specialstatus are those of the last opcode ! */
1.1.1.8 root 884: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.3 root 885: put_long (m68k_areg(regs, 7)+2, last_fault_for_exception_3);
886: put_word (m68k_areg(regs, 7)+6, last_op_for_exception_3);
887: put_long (m68k_areg(regs, 7)+10, last_addr_for_exception_3);
1.1.1.8 root 888: if (bEnableDebug) {
889: fprintf(stderr,"Address Error at address $%x, PC=$%x\n",last_fault_for_exception_3,currpc);
890: DebugUI();
891: }
1.1.1.3 root 892: }
1.1.1.8 root 893: else { /* Bus error */
1.1.1.12 root 894: specialstatus |= ( get_word(BusErrorPC) & (~0x1f) ); /* [NP] unused bits of special status are those of the last opcode ! */
1.1.1.8 root 895: if (bBusErrorReadWrite)
896: specialstatus |= 0x10;
897: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.10 root 898: put_long (m68k_areg(regs, 7)+2, BusErrorAddress);
1.1.1.12 root 899: put_word (m68k_areg(regs, 7)+6, get_word(BusErrorPC)); /* Opcode */
900:
901: /* [NP] PC stored in the stack frame is not necessarily pointing to the next instruction ! */
902: /* FIXME : we should have a proper model for this, in the meantime we handle specific cases */
903: if ( get_word(BusErrorPC) == 0x21f8 ) /* move.l $0.w,$24.w (Transbeauce 2 loader) */
904: put_long (m68k_areg(regs, 7)+10, currpc-2); /* correct PC is 2 bytes less than usual value */
1.1.1.8 root 905: /* Check for double bus errors: */
906: if (regs.spcflags & SPCFLAG_BUSERROR) {
907: fprintf(stderr, "Detected double bus error at address $%x, PC=$%lx => CPU halted!\n",
1.1.1.10 root 908: BusErrorAddress, (long)currpc);
1.1.1.8 root 909: unset_special(SPCFLAG_BUSERROR);
910: if (bEnableDebug)
911: DebugUI();
912: regs.intmask = 7;
913: m68k_setstopped(TRUE);
914: return;
915: }
1.1.1.10 root 916: if (bEnableDebug && BusErrorAddress!=0xff8a00) {
917: fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n", BusErrorAddress, (long)currpc);
1.1.1.8 root 918: DebugUI();
919: }
920: }
1.1.1.3 root 921: }
922:
1.1.1.8 root 923: /* Set PC and flags */
924: if (bEnableDebug && get_long (regs.vbr + 4*nr) == 0) {
925: write_log("Uninitialized exception handler #%i!\n", nr);
1.1.1.13! root 926: DebugUI();
1.1.1.8 root 927: }
1.1 root 928: m68k_setpc (get_long (regs.vbr + 4*nr));
929: fill_prefetch_0 ();
1.1.1.12 root 930: /* Handle trace flags depending on current state */
931: exception_trace (nr);
1.1.1.6 root 932:
1.1.1.13! root 933: /* Handle exception cycles (special case for MFP) */
! 934: if ( ExceptionSource == M68000_EXCEPTION_SRC_INT_MFP )
! 935: {
! 936: M68000_AddCycles(44+12); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
! 937: }
! 938: else if (nr >= 24 && nr <= 31)
1.1.1.7 root 939: {
1.1.1.12 root 940: if ( ( nr == 26 ) || ( nr == 28 ) ) /* HBL or VBL */
941: M68000_AddCycles(44+12); /* Video Interrupt */
942: else
943: M68000_AddCycles(44+4); /* Other Interrupts */
1.1.1.7 root 944: }
945: else if(nr >= 32 && nr <= 47)
946: {
1.1.1.13! root 947: M68000_AddCycles(34-4); /* Trap (total is 34, but cpuemu.c already adds 4) */
1.1.1.7 root 948: }
949: else switch(nr)
950: {
1.1.1.12 root 951: case 2: M68000_AddCycles(50); break; /* Bus error */
952: case 3: M68000_AddCycles(50); break; /* Address error */
953: case 4: M68000_AddCycles(34); break; /* Illegal instruction */
954: case 5: M68000_AddCycles(38); break; /* Div by zero */
955: case 6: M68000_AddCycles(40); break; /* CHK */
956: case 7: M68000_AddCycles(34); break; /* TRAPV */
957: case 8: M68000_AddCycles(34); break; /* Privilege violation */
958: case 9: M68000_AddCycles(34); break; /* Trace */
959: case 10: M68000_AddCycles(34); break; /* Line-A - probably wrong */
960: case 11: M68000_AddCycles(34); break; /* Line-F - probably wrong */
1.1.1.7 root 961: default:
1.1.1.8 root 962: /* FIXME: Add right cycles value for MFP interrupts and copro exceptions ... */
1.1.1.7 root 963: if(nr < 64)
1.1.1.12 root 964: M68000_AddCycles(4); /* Coprocessor and unassigned exceptions (???) */
1.1.1.7 root 965: else
1.1.1.13! root 966: M68000_AddCycles(44+12); /* Must be a MFP interrupt, should be processed above */
1.1.1.7 root 967: break;
1.1.1.6 root 968: }
1.1 root 969: }
970:
1.1.1.7 root 971:
1.1 root 972: static void Interrupt(int nr)
973: {
974: assert(nr < 8 && nr >= 0);
1.1.1.10 root 975: /*lastint_regs = regs;*/
976: /*lastint_no = nr;*/
1.1.1.13! root 977:
! 978: /* [NP] On Hatari, only video ints are using SPCFLAG_INT (see m68000.c) */
! 979: /* TODO : to be really precise, we should use a global variable to store the last ExceptionSource */
! 980: /* passed to M68000_Exception, instead of hardcoding M68000_EXCEPTION_SRC_INT_VIDEO here */
! 981: Exception(nr+24, 0, M68000_EXCEPTION_SRC_INT_VIDEO);
1.1 root 982:
983: regs.intmask = nr;
984: set_special (SPCFLAG_INT);
985: }
986:
1.1.1.7 root 987:
1.1.1.12 root 988: uae_u32 caar, cacr;
1.1.1.8 root 989: static uae_u32 itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp;
1.1 root 990:
1.1.1.7 root 991:
1.1.1.12 root 992: static int movec_illg (int regno)
993: {
994: int regno2 = regno & 0x7ff;
995: if (currprefs.cpu_level == 1) { /* 68010 */
996: if (regno2 < 2)
997: return 0;
998: return 1;
999: }
1000: if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) { /* 68020 */
1001: if (regno == 3) return 1; /* 68040 only */
1002: /* 4 is >=68040, but 0x804 is in 68020 */
1003: if (regno2 < 4 || regno == 0x804)
1004: return 0;
1005: return 1;
1006: }
1007: if (currprefs.cpu_level >= 4) { /* 68040 */
1008: if (regno == 0x802) return 1; /* 68020 only */
1009: if (regno2 < 8) return 0;
1010: if (currprefs.cpu_level == 6 && regno2 == 8) /* 68060 only */
1011: return 0;
1012: return 1;
1013: }
1014: return 1;
1015: }
1016:
1.1 root 1017: int m68k_move2c (int regno, uae_u32 *regp)
1018: {
1.1.1.12 root 1019: if (movec_illg (regno)) {
1.1 root 1020: op_illg (0x4E7B);
1021: return 0;
1022: } else {
1023: switch (regno) {
1024: case 0: regs.sfc = *regp & 7; break;
1025: case 1: regs.dfc = *regp & 7; break;
1.1.1.12 root 1026: case 2: cacr = *regp & (currprefs.cpu_level < 4 ? 0x3 : 0x80008000); break;
1.1 root 1027: case 3: tc = *regp & 0xc000; break;
1028: /* Mask out fields that should be zero. */
1029: case 4: itt0 = *regp & 0xffffe364; break;
1030: case 5: itt1 = *regp & 0xffffe364; break;
1031: case 6: dtt0 = *regp & 0xffffe364; break;
1032: case 7: dtt1 = *regp & 0xffffe364; break;
1.1.1.7 root 1033:
1.1 root 1034: case 0x800: regs.usp = *regp; break;
1035: case 0x801: regs.vbr = *regp; break;
1.1.1.12 root 1036: case 0x802: caar = *regp & 0xfc; break;
1.1 root 1037: case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
1038: case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
1.1.1.6 root 1039: case 0x805: mmusr = *regp; break;
1040: case 0x806: urp = *regp; break;
1041: case 0x807: srp = *regp; break;
1.1 root 1042: default:
1043: op_illg (0x4E7B);
1044: return 0;
1045: }
1046: }
1047: return 1;
1048: }
1049:
1050: int m68k_movec2 (int regno, uae_u32 *regp)
1051: {
1.1.1.12 root 1052: if (movec_illg (regno)) {
1.1 root 1053: op_illg (0x4E7A);
1054: return 0;
1055: } else {
1056: switch (regno) {
1057: case 0: *regp = regs.sfc; break;
1058: case 1: *regp = regs.dfc; break;
1.1.1.12 root 1059: case 2: *regp = cacr; break;
1.1 root 1060: case 3: *regp = tc; break;
1061: case 4: *regp = itt0; break;
1062: case 5: *regp = itt1; break;
1063: case 6: *regp = dtt0; break;
1064: case 7: *regp = dtt1; break;
1065: case 0x800: *regp = regs.usp; break;
1066: case 0x801: *regp = regs.vbr; break;
1.1.1.12 root 1067: case 0x802: *regp = caar; break;
1.1 root 1068: case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
1069: case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
1070: case 0x805: *regp = mmusr; break;
1.1.1.6 root 1071: case 0x806: *regp = urp; break;
1072: case 0x807: *regp = srp; break;
1.1 root 1073: default:
1074: op_illg (0x4E7A);
1075: return 0;
1076: }
1077: }
1078: return 1;
1079: }
1080:
1081: STATIC_INLINE int
1.1.1.10 root 1082: div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 ndiv, uae_u32 *quot, uae_u32 *rem)
1.1 root 1083: {
1084: uae_u32 q = 0, cbit = 0;
1085: int i;
1086:
1.1.1.10 root 1087: if (ndiv <= src_hi) {
1.1 root 1088: return 1;
1089: }
1090: for (i = 0 ; i < 32 ; i++) {
1091: cbit = src_hi & 0x80000000ul;
1092: src_hi <<= 1;
1093: if (src_lo & 0x80000000ul) src_hi++;
1094: src_lo <<= 1;
1095: q = q << 1;
1.1.1.10 root 1096: if (cbit || ndiv <= src_hi) {
1.1 root 1097: q |= 1;
1.1.1.10 root 1098: src_hi -= ndiv;
1.1 root 1099: }
1100: }
1101: *quot = q;
1102: *rem = src_hi;
1103: return 0;
1104: }
1105:
1106: void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
1107: {
1108: #if defined(uae_s64)
1109: if (src == 0) {
1.1.1.13! root 1110: Exception (5, oldpc,M68000_EXCEPTION_SRC_CPU);
1.1 root 1111: return;
1112: }
1113: if (extra & 0x800) {
1114: /* signed variant */
1115: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1116: uae_s64 quot, rem;
1117:
1118: if (extra & 0x400) {
1119: a &= 0xffffffffu;
1120: a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
1121: }
1122: rem = a % (uae_s64)(uae_s32)src;
1123: quot = a / (uae_s64)(uae_s32)src;
1124: if ((quot & UVAL64(0xffffffff80000000)) != 0
1125: && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1126: {
1127: SET_VFLG (1);
1128: SET_NFLG (1);
1129: SET_CFLG (0);
1130: } else {
1131: if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
1132: SET_VFLG (0);
1133: SET_CFLG (0);
1134: SET_ZFLG (((uae_s32)quot) == 0);
1135: SET_NFLG (((uae_s32)quot) < 0);
1136: m68k_dreg(regs, extra & 7) = rem;
1137: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1138: }
1139: } else {
1140: /* unsigned */
1141: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1142: uae_u64 quot, rem;
1143:
1144: if (extra & 0x400) {
1145: a &= 0xffffffffu;
1146: a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
1147: }
1148: rem = a % (uae_u64)src;
1149: quot = a / (uae_u64)src;
1150: if (quot > 0xffffffffu) {
1151: SET_VFLG (1);
1152: SET_NFLG (1);
1153: SET_CFLG (0);
1154: } else {
1155: SET_VFLG (0);
1156: SET_CFLG (0);
1157: SET_ZFLG (((uae_s32)quot) == 0);
1158: SET_NFLG (((uae_s32)quot) < 0);
1159: m68k_dreg(regs, extra & 7) = rem;
1160: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1161: }
1162: }
1163: #else
1164: if (src == 0) {
1.1.1.13! root 1165: Exception (5, oldpc,M68000_EXCEPTION_SRC_CPU);
1.1 root 1166: return;
1167: }
1168: if (extra & 0x800) {
1169: /* signed variant */
1170: uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1171: uae_s32 hi = lo < 0 ? -1 : 0;
1172: uae_s32 save_high;
1173: uae_u32 quot, rem;
1174: uae_u32 sign;
1175:
1176: if (extra & 0x400) {
1177: hi = (uae_s32)m68k_dreg(regs, extra & 7);
1178: }
1179: save_high = hi;
1180: sign = (hi ^ src);
1181: if (hi < 0) {
1182: hi = ~hi;
1183: lo = -lo;
1184: if (lo == 0) hi++;
1185: }
1186: if ((uae_s32)src < 0) src = -src;
1187: if (div_unsigned(hi, lo, src, ", &rem) ||
1188: (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
1189: SET_VFLG (1);
1190: SET_NFLG (1);
1191: SET_CFLG (0);
1192: } else {
1193: if (sign & 0x80000000) quot = -quot;
1194: if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
1195: SET_VFLG (0);
1196: SET_CFLG (0);
1197: SET_ZFLG (((uae_s32)quot) == 0);
1198: SET_NFLG (((uae_s32)quot) < 0);
1199: m68k_dreg(regs, extra & 7) = rem;
1200: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1201: }
1202: } else {
1203: /* unsigned */
1204: uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1205: uae_u32 hi = 0;
1206: uae_u32 quot, rem;
1207:
1208: if (extra & 0x400) {
1209: hi = (uae_u32)m68k_dreg(regs, extra & 7);
1210: }
1211: if (div_unsigned(hi, lo, src, ", &rem)) {
1212: SET_VFLG (1);
1213: SET_NFLG (1);
1214: SET_CFLG (0);
1215: } else {
1216: SET_VFLG (0);
1217: SET_CFLG (0);
1218: SET_ZFLG (((uae_s32)quot) == 0);
1219: SET_NFLG (((uae_s32)quot) < 0);
1220: m68k_dreg(regs, extra & 7) = rem;
1221: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1222: }
1223: }
1224: #endif
1225: }
1226:
1227: STATIC_INLINE void
1228: mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1229: {
1230: uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1231: uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1232: uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1233: uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1234: uae_u32 lo;
1235:
1236: lo = r0 + ((r1 << 16) & 0xffff0000ul);
1237: if (lo < r0) r3++;
1238: r0 = lo;
1239: lo = r0 + ((r2 << 16) & 0xffff0000ul);
1240: if (lo < r0) r3++;
1241: r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1242: *dst_lo = lo;
1243: *dst_hi = r3;
1244: }
1245:
1246: void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1247: {
1248: #if defined(uae_s64)
1249: if (extra & 0x800) {
1250: /* signed variant */
1251: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1252:
1253: a *= (uae_s64)(uae_s32)src;
1254: SET_VFLG (0);
1255: SET_CFLG (0);
1256: SET_ZFLG (a == 0);
1257: SET_NFLG (a < 0);
1258: if (extra & 0x400)
1259: m68k_dreg(regs, extra & 7) = a >> 32;
1260: else if ((a & UVAL64(0xffffffff80000000)) != 0
1261: && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1262: {
1263: SET_VFLG (1);
1264: }
1265: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1266: } else {
1267: /* unsigned */
1268: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1269:
1270: a *= (uae_u64)src;
1271: SET_VFLG (0);
1272: SET_CFLG (0);
1273: SET_ZFLG (a == 0);
1274: SET_NFLG (((uae_s64)a) < 0);
1275: if (extra & 0x400)
1276: m68k_dreg(regs, extra & 7) = a >> 32;
1277: else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1278: SET_VFLG (1);
1279: }
1280: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1281: }
1282: #else
1283: if (extra & 0x800) {
1284: /* signed variant */
1285: uae_s32 src1,src2;
1286: uae_u32 dst_lo,dst_hi;
1287: uae_u32 sign;
1288:
1289: src1 = (uae_s32)src;
1290: src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1291: sign = (src1 ^ src2);
1292: if (src1 < 0) src1 = -src1;
1293: if (src2 < 0) src2 = -src2;
1294: mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1295: if (sign & 0x80000000) {
1296: dst_hi = ~dst_hi;
1297: dst_lo = -dst_lo;
1298: if (dst_lo == 0) dst_hi++;
1299: }
1300: SET_VFLG (0);
1301: SET_CFLG (0);
1302: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1303: SET_NFLG (((uae_s32)dst_hi) < 0);
1304: if (extra & 0x400)
1305: m68k_dreg(regs, extra & 7) = dst_hi;
1306: else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1307: && ((dst_hi & 0xffffffff) != 0xffffffff
1308: || (dst_lo & 0x80000000) != 0x80000000))
1309: {
1310: SET_VFLG (1);
1311: }
1312: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1313: } else {
1314: /* unsigned */
1315: uae_u32 dst_lo,dst_hi;
1316:
1317: mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1318:
1319: SET_VFLG (0);
1320: SET_CFLG (0);
1321: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1322: SET_NFLG (((uae_s32)dst_hi) < 0);
1323: if (extra & 0x400)
1324: m68k_dreg(regs, extra & 7) = dst_hi;
1325: else if (dst_hi != 0) {
1326: SET_VFLG (1);
1327: }
1328: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1329: }
1330: #endif
1331: }
1.1.1.6 root 1332:
1.1 root 1333:
1334: void m68k_reset (void)
1335: {
1336: regs.s = 1;
1337: regs.m = 0;
1338: regs.stopped = 0;
1339: regs.t1 = 0;
1340: regs.t0 = 0;
1341: SET_ZFLG (0);
1342: SET_XFLG (0);
1343: SET_CFLG (0);
1344: SET_VFLG (0);
1345: SET_NFLG (0);
1.1.1.7 root 1346: regs.spcflags &= SPCFLAG_MODE_CHANGE; /* Clear specialflags except mode-change */
1.1 root 1347: regs.intmask = 7;
1348: regs.vbr = regs.sfc = regs.dfc = 0;
1349: regs.fpcr = regs.fpsr = regs.fpiar = 0;
1.1.1.7 root 1350:
1351: m68k_areg(regs, 7) = get_long(0);
1352: m68k_setpc(get_long(4));
1353: refill_prefetch (m68k_getpc(), 0);
1.1 root 1354: }
1355:
1.1.1.8 root 1356:
1.1 root 1357: unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1358: {
1.1.1.8 root 1359: #if 0
1.1 root 1360: uaecptr pc = m68k_getpc ();
1.1.1.8 root 1361: #endif
1.1.1.6 root 1362: if ((opcode & 0xF000) == 0xF000) {
1.1.1.13! root 1363: Exception(0xB,0,M68000_EXCEPTION_SRC_CPU);
1.1 root 1364: return 4;
1.1.1.6 root 1365: }
1366: if ((opcode & 0xF000) == 0xA000) {
1.1.1.13! root 1367: Exception(0xA,0,M68000_EXCEPTION_SRC_CPU);
1.1 root 1368: return 4;
1.1.1.6 root 1369: }
1.1.1.3 root 1370: #if 0
1.1.1.6 root 1371: write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc);
1.1 root 1372: #endif
1.1.1.13! root 1373: Exception (4,0,M68000_EXCEPTION_SRC_CPU);
1.1 root 1374: return 4;
1375: }
1376:
1.1.1.8 root 1377:
1.1 root 1378: void mmu_op(uae_u32 opcode, uae_u16 extra)
1379: {
1380: if ((opcode & 0xFE0) == 0x0500) {
1381: /* PFLUSH */
1382: mmusr = 0;
1383: write_log ("PFLUSH\n");
1384: } else if ((opcode & 0x0FD8) == 0x548) {
1385: /* PTEST */
1386: write_log ("PTEST\n");
1387: } else
1388: op_illg (opcode);
1389: }
1390:
1391:
1392: static uaecptr last_trace_ad = 0;
1393:
1394: static void do_trace (void)
1395: {
1.1.1.12 root 1396: if (regs.t0 && currprefs.cpu_level >= 2) {
1.1 root 1397: uae_u16 opcode;
1398: /* should also include TRAP, CHK, SR modification FPcc */
1399: /* probably never used so why bother */
1400: /* We can afford this to be inefficient... */
1401: m68k_setpc (m68k_getpc ());
1402: fill_prefetch_0 ();
1403: opcode = get_word (regs.pc);
1404: if (opcode == 0x4e72 /* RTE */
1405: || opcode == 0x4e74 /* RTD */
1406: || opcode == 0x4e75 /* RTS */
1407: || opcode == 0x4e77 /* RTR */
1408: || opcode == 0x4e76 /* TRAPV */
1409: || (opcode & 0xffc0) == 0x4e80 /* JSR */
1410: || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1411: || (opcode & 0xff00) == 0x6100 /* BSR */
1412: || ((opcode & 0xf000) == 0x6000 /* Bcc */
1413: && cctrue((opcode >> 8) & 0xf))
1414: || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1415: && !cctrue((opcode >> 8) & 0xf)
1416: && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1417: {
1418: last_trace_ad = m68k_getpc ();
1419: unset_special (SPCFLAG_TRACE);
1420: set_special (SPCFLAG_DOTRACE);
1421: }
1422: } else if (regs.t1) {
1423: last_trace_ad = m68k_getpc ();
1424: unset_special (SPCFLAG_TRACE);
1425: set_special (SPCFLAG_DOTRACE);
1426: }
1427: }
1428:
1429:
1.1.1.8 root 1430: /*
1431: * Handle special flags
1432: */
1.1 root 1433: static int do_specialties (void)
1434: {
1.1.1.7 root 1435: if(regs.spcflags & SPCFLAG_BUSERROR) {
1436: /* We can not execute bus errors directly in the memory handler
1437: * functions since the PC should point to the address of the next
1438: * instruction, so we're executing the bus errors here: */
1.1.1.8 root 1439: unset_special(SPCFLAG_BUSERROR);
1.1.1.13! root 1440: Exception(2,0,M68000_EXCEPTION_SRC_CPU);
1.1.1.7 root 1441: }
1442:
1.1.1.8 root 1443: if(regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1444: /* Add some extra cycles to simulate a wait state */
1445: unset_special(SPCFLAG_EXTRA_CYCLES);
1.1.1.11 root 1446: M68000_AddCycles(nWaitStateCycles);
1.1.1.12 root 1447: nWaitStateCycles = 0;
1.1.1.8 root 1448: }
1449:
1.1 root 1450: if (regs.spcflags & SPCFLAG_DOTRACE) {
1.1.1.13! root 1451: Exception (9,last_trace_ad,M68000_EXCEPTION_SRC_CPU);
1.1 root 1452: }
1.1.1.8 root 1453:
1.1 root 1454: while (regs.spcflags & SPCFLAG_STOP) {
1.1.1.8 root 1455: if (regs.intmask > 5) {
1456: /* We still have to care about events when IPL==7 ! */
1457: Main_EventHandler();
1458: if (regs.spcflags & SPCFLAG_BRK) return 1;
1459: }
1.1.1.13! root 1460:
1.1.1.8 root 1461: M68000_AddCycles(4);
1.1.1.13! root 1462:
! 1463: /* It is possible one or more ints happen at the same time */
! 1464: /* We must process them during the same cpu cycle until the special INT flag is set */
! 1465: while (PendingInterruptCount<=0 && PendingInterruptFunction) {
! 1466: /* 1st, we call the interrupt handler */
1.1.1.8 root 1467: CALL_VAR(PendingInterruptFunction);
1.1.1.13! root 1468: /* Then we check if this handler triggered an MFP int to process */
! 1469: if (regs.spcflags & SPCFLAG_MFP)
! 1470: MFP_CheckPendingInterrupts();
! 1471:
! 1472: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
! 1473: int intr = intlev ();
! 1474: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
! 1475: if (intr != -1 && intr > regs.intmask) {
! 1476: Interrupt (intr);
! 1477: regs.stopped = 0;
! 1478: unset_special (SPCFLAG_STOP);
! 1479: break;
! 1480: }
1.1.1.6 root 1481: }
1.1 root 1482: }
1483: }
1.1.1.8 root 1484:
1.1 root 1485: if (regs.spcflags & SPCFLAG_TRACE)
1486: do_trace ();
1487:
1.1.1.12 root 1488: // if (regs.spcflags & SPCFLAG_DOINT) {
1489: /* [NP] pending int should be processed now, not after the current instr */
1490: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1.1.1.6 root 1491: int intr = intlev ();
1.1.1.8 root 1492: /* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */
1.1.1.12 root 1493: // unset_special (SPCFLAG_DOINT);
1494: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1.1.1.6 root 1495: if (intr != -1 && intr > regs.intmask) {
1.1 root 1496: Interrupt (intr);
1497: regs.stopped = 0;
1.1.1.6 root 1498: }
1.1 root 1499: }
1500: if (regs.spcflags & SPCFLAG_INT) {
1501: unset_special (SPCFLAG_INT);
1502: set_special (SPCFLAG_DOINT);
1503: }
1.1.1.8 root 1504:
1505: if (regs.spcflags & SPCFLAG_MFP) { /* Check for MFP interrupts */
1506: MFP_CheckPendingInterrupts();
1507: }
1508:
1.1 root 1509: if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1.1.1.8 root 1510: unset_special(SPCFLAG_MODE_CHANGE);
1.1 root 1511: return 1;
1512: }
1.1.1.8 root 1513:
1.1 root 1514: return 0;
1515: }
1516:
1.1.1.3 root 1517:
1.1 root 1518: /* It's really sad to have two almost identical functions for this, but we
1519: do it all for performance... :( */
1520: static void m68k_run_1 (void)
1521: {
1522: #ifdef DEBUG_PREFETCH
1523: uae_u8 saved_bytes[20];
1524: uae_u16 *oldpcp;
1525: #endif
1.1.1.8 root 1526:
1527: for (;;) {
1.1 root 1528: int cycles;
1529: uae_u32 opcode = get_iword_prefetch (0);
1.1.1.8 root 1530:
1.1 root 1531: #ifdef DEBUG_PREFETCH
1532: if (get_ilong (0) != do_get_mem_long (®s.prefetch)) {
1533: fprintf (stderr, "Prefetch differs from memory.\n");
1534: debugging = 1;
1535: return;
1536: }
1537: oldpcp = regs.pc_p;
1538: memcpy (saved_bytes, regs.pc_p, 20);
1539: #endif
1540:
1541: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.12 root 1542: if ( HATARI_TRACE_LEVEL ( HATARI_TRACE_CPU_DISASM ) )
1543: {
1544: int nFrameCycles = Cycles_GetCounter(CYCLES_COUNTER_VIDEO);;
1545: int nLineCycles = nFrameCycles % nCyclesPerLine;
1546: HATARI_TRACE_PRINT ( "video_cyc=%6d %3d@%3d : " , nFrameCycles, nLineCycles, nHBL );
1547: m68k_disasm(stderr, m68k_getpc (), NULL, 1);
1548: }
1.1 root 1549:
1550: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1551: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1552: #if COUNT_INSTRS == 2
1553: if (table68k[opcode].handler != -1)
1554: instrcount[table68k[opcode].handler]++;
1555: #elif COUNT_INSTRS == 1
1556: instrcount[opcode]++;
1557: #endif
1.1.1.2 root 1558:
1.1.1.12 root 1559: /* In case of a Bus Error, we need the PC of the instruction that caused */
1560: /* the error to build the exception stack frame */
1561: BusErrorPC = m68k_getpc();
1562:
1.1.1.6 root 1563: cycles = (*cpufunctbl[opcode])(opcode);
1564:
1.1 root 1565: #ifdef DEBUG_PREFETCH
1566: if (memcmp (saved_bytes, oldpcp, 20) != 0) {
1.1.1.12 root 1567: fprintf (stderr, "Self-modifying code detected %x.\n" , m68k_getpc() );
1.1 root 1568: set_special (SPCFLAG_BRK);
1569: debugging = 1;
1570: }
1571: #endif
1.1.1.2 root 1572:
1.1.1.12 root 1573: M68000_AddCyclesWithPairing(cycles);
1.1.1.13! root 1574: if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
! 1575: /* Add some extra cycles to simulate a wait state */
! 1576: unset_special(SPCFLAG_EXTRA_CYCLES);
! 1577: M68000_AddCycles(nWaitStateCycles);
! 1578: nWaitStateCycles = 0;
! 1579: }
! 1580:
! 1581: while (PendingInterruptCount <= 0 && PendingInterruptFunction)
1.1.1.8 root 1582: CALL_VAR(PendingInterruptFunction);
1583:
1.1 root 1584: if (regs.spcflags) {
1585: if (do_specialties ())
1586: return;
1587: }
1588: }
1589: }
1590:
1591:
1592: /* Same thing, but don't use prefetch to get opcode. */
1593: static void m68k_run_2 (void)
1594: {
1.1.1.8 root 1595: for (;;) {
1.1 root 1596: int cycles;
1597: uae_u32 opcode = get_iword (0);
1598:
1599: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.12 root 1600: if ( HATARI_TRACE_LEVEL ( HATARI_TRACE_CPU_DISASM ) )
1601: {
1602: int nFrameCycles = Cycles_GetCounter(CYCLES_COUNTER_VIDEO);;
1603: int nLineCycles = nFrameCycles % nCyclesPerLine;
1604: HATARI_TRACE_PRINT ( "video_cyc=%6d %3d@%3d : " , nFrameCycles, nLineCycles, nHBL );
1605: m68k_disasm(stderr, m68k_getpc (), NULL, 1);
1606: }
1607:
1.1 root 1608: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1609: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1610: #if COUNT_INSTRS == 2
1611: if (table68k[opcode].handler != -1)
1612: instrcount[table68k[opcode].handler]++;
1613: #elif COUNT_INSTRS == 1
1614: instrcount[opcode]++;
1615: #endif
1.1.1.2 root 1616:
1.1.1.6 root 1617: cycles = (*cpufunctbl[opcode])(opcode);
1618:
1.1.1.8 root 1619: M68000_AddCycles(cycles);
1.1.1.13! root 1620: if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
! 1621: /* Add some extra cycles to simulate a wait state */
! 1622: unset_special(SPCFLAG_EXTRA_CYCLES);
! 1623: M68000_AddCycles(nWaitStateCycles);
! 1624: nWaitStateCycles = 0;
! 1625: }
! 1626:
1.1.1.12 root 1627: while (PendingInterruptCount <= 0 && PendingInterruptFunction)
1.1.1.8 root 1628: CALL_VAR(PendingInterruptFunction);
1629:
1.1 root 1630: if (regs.spcflags) {
1631: if (do_specialties ())
1632: return;
1633: }
1634: }
1635: }
1636:
1637:
1638: void m68k_go (int may_quit)
1639: {
1.1.1.8 root 1640: static int in_m68k_go = 0;
1641:
1.1 root 1642: if (in_m68k_go || !may_quit) {
1643: write_log ("Bug! m68k_go is not reentrant.\n");
1644: abort ();
1645: }
1646:
1647: in_m68k_go++;
1.1.1.8 root 1648: while (!(regs.spcflags & SPCFLAG_BRK)) {
1.1.1.12 root 1649: if(currprefs.cpu_compatible)
1.1.1.2 root 1650: m68k_run_1();
1651: else
1652: m68k_run_2();
1.1 root 1653: }
1.1.1.8 root 1654: unset_special(SPCFLAG_BRK);
1.1 root 1655: in_m68k_go--;
1656: }
1657:
1.1.1.8 root 1658:
1659: /*
1.1 root 1660: static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1661: {
1662: uae_u32 opcode, val;
1663: struct instr *dp;
1664:
1665: opcode = get_iword_1(0);
1666: last_op_for_exception_3 = opcode;
1667: m68kpc_offset = 2;
1668:
1.1.1.6 root 1669: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1670: opcode = 0x4AFC;
1671: }
1672: dp = table68k + opcode;
1673:
1674: if (dp->suse) {
1675: if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) {
1.1.1.13! root 1676: Exception (3, 0,M68000_EXCEPTION_SRC_CPU);
1.1 root 1677: return;
1678: }
1679: }
1680: if (dp->duse) {
1681: if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) {
1.1.1.13! root 1682: Exception (3, 0,M68000_EXCEPTION_SRC_CPU);
1.1 root 1683: return;
1684: }
1685: }
1686: }
1.1.1.8 root 1687: */
1688:
1.1 root 1689:
1690: void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1691: {
1.1.1.11 root 1692: static const char * const ccnames[] =
1.1.1.8 root 1693: { "T ","F ","HI","LS","CC","CS","NE","EQ",
1694: "VC","VS","PL","MI","GE","LT","GT","LE" };
1695:
1.1 root 1696: uaecptr newpc = 0;
1697: m68kpc_offset = addr - m68k_getpc ();
1698: while (cnt-- > 0) {
1699: char instrname[20],*ccpt;
1700: int opwords;
1701: uae_u32 opcode;
1.1.1.11 root 1702: const struct mnemolookup *lookup;
1.1 root 1703: struct instr *dp;
1704: fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset);
1705: for (opwords = 0; opwords < 5; opwords++){
1706: fprintf (f, "%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1707: }
1708: opcode = get_iword_1 (m68kpc_offset);
1709: m68kpc_offset += 2;
1.1.1.6 root 1710: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1711: opcode = 0x4AFC;
1712: }
1713: dp = table68k + opcode;
1714: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1715: ;
1716:
1717: strcpy (instrname, lookup->name);
1718: ccpt = strstr (instrname, "cc");
1719: if (ccpt != 0) {
1720: strncpy (ccpt, ccnames[dp->cc], 2);
1721: }
1722: fprintf (f, "%s", instrname);
1723: switch (dp->size){
1724: case sz_byte: fprintf (f, ".B "); break;
1725: case sz_word: fprintf (f, ".W "); break;
1726: case sz_long: fprintf (f, ".L "); break;
1727: default: fprintf (f, " "); break;
1728: }
1729:
1730: if (dp->suse) {
1731: newpc = m68k_getpc () + m68kpc_offset;
1732: newpc += ShowEA (f, dp->sreg, dp->smode, dp->size, 0);
1733: }
1734: if (dp->suse && dp->duse)
1735: fprintf (f, ",");
1736: if (dp->duse) {
1737: newpc = m68k_getpc () + m68kpc_offset;
1738: newpc += ShowEA (f, dp->dreg, dp->dmode, dp->size, 0);
1739: }
1740: if (ccpt != 0) {
1741: if (cctrue(dp->cc))
1.1.1.5 root 1742: fprintf (f, " == %08lx (TRUE)", (long)newpc);
1.1 root 1743: else
1.1.1.5 root 1744: fprintf (f, " == %08lx (FALSE)", (long)newpc);
1.1 root 1745: } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1.1.1.5 root 1746: fprintf (f, " == %08lx", (long)newpc);
1.1 root 1747: fprintf (f, "\n");
1748: }
1749: if (nextpc)
1750: *nextpc = m68k_getpc () + m68kpc_offset;
1751: }
1752:
1753: void m68k_dumpstate (FILE *f, uaecptr *nextpc)
1754: {
1755: int i;
1756: for (i = 0; i < 8; i++){
1.1.1.5 root 1757: fprintf (f, "D%d: %08lx ", i, (long)m68k_dreg(regs, i));
1.1 root 1758: if ((i & 3) == 3) fprintf (f, "\n");
1759: }
1760: for (i = 0; i < 8; i++){
1.1.1.5 root 1761: fprintf (f, "A%d: %08lx ", i, (long)m68k_areg(regs, i));
1.1 root 1762: if ((i & 3) == 3) fprintf (f, "\n");
1763: }
1764: if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1765: if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1766: if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1767: fprintf (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1.1.1.5 root 1768: (long)regs.usp,(long)regs.isp,(long)regs.msp,(long)regs.vbr);
1.1 root 1769: fprintf (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1770: regs.t1, regs.t0, regs.s, regs.m,
1771: GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1772: for (i = 0; i < 8; i++){
1773: fprintf (f, "FP%d: %g ", i, regs.fp[i]);
1774: if ((i & 3) == 3) fprintf (f, "\n");
1775: }
1776: fprintf (f, "N=%d Z=%d I=%d NAN=%d\n",
1777: (regs.fpsr & 0x8000000) != 0,
1778: (regs.fpsr & 0x4000000) != 0,
1779: (regs.fpsr & 0x2000000) != 0,
1780: (regs.fpsr & 0x1000000) != 0);
1.1.1.12 root 1781: if (currprefs.cpu_compatible)
1.1 root 1782: fprintf (f, "prefetch %08lx\n", (unsigned long)do_get_mem_long(®s.prefetch));
1783:
1784: m68k_disasm (f, m68k_getpc (), nextpc, 1);
1785: if (nextpc)
1.1.1.5 root 1786: fprintf (f, "next PC: %08lx\n", (long)*nextpc);
1.1 root 1787: }
1.1.1.12 root 1788:
1789:
1790: /*
1791:
1792: The routines below take dividend and divisor as parameters.
1793: They return 0 if division by zero, or exact number of cycles otherwise.
1794:
1795: The number of cycles returned assumes a register operand.
1796: Effective address time must be added if memory operand.
1797:
1798: For 68000 only (not 68010, 68012, 68020, etc).
1799: Probably valid for 68008 after adding the extra prefetch cycle.
1800:
1801:
1802: Best and worst cases are for register operand:
1803: (Note the difference with the documented range.)
1804:
1805:
1806: DIVU:
1807:
1808: Overflow (always): 10 cycles.
1809: Worst case: 136 cycles.
1810: Best case: 76 cycles.
1811:
1812:
1813: DIVS:
1814:
1815: Absolute overflow: 16-18 cycles.
1816: Signed overflow is not detected prematurely.
1817:
1818: Worst case: 156 cycles.
1819: Best case without signed overflow: 122 cycles.
1820: Best case with signed overflow: 120 cycles
1821:
1822:
1823: */
1824:
1825:
1826: //
1827: // DIVU
1828: // Unsigned division
1829: //
1830:
1831: STATIC_INLINE int getDivu68kCycles_2 (uae_u32 dividend, uae_u16 divisor)
1832: {
1833: int mcycles;
1834: uae_u32 hdivisor;
1835: int i;
1836:
1837: if (divisor == 0)
1838: return 0;
1839:
1840: // Overflow
1841: if ((dividend >> 16) >= divisor)
1842: return (mcycles = 5) * 2;
1843:
1844: mcycles = 38;
1845: hdivisor = divisor << 16;
1846:
1847: for (i = 0; i < 15; i++) {
1848: uae_u32 temp;
1849: temp = dividend;
1850:
1851: dividend <<= 1;
1852:
1853: // If carry from shift
1854: if ((uae_s32)temp < 0)
1855: dividend -= hdivisor;
1856: else {
1857: mcycles += 2;
1858: if (dividend >= hdivisor) {
1859: dividend -= hdivisor;
1860: mcycles--;
1861: }
1862: }
1863: }
1864: return mcycles * 2;
1865: }
1866: int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor)
1867: {
1868: int v = getDivu68kCycles_2 (dividend, divisor) - 4;
1869: // write_log ("U%d ", v);
1870: return v;
1871: }
1872:
1873: //
1874: // DIVS
1875: // Signed division
1876: //
1877:
1878: STATIC_INLINE int getDivs68kCycles_2 (uae_s32 dividend, uae_s16 divisor)
1879: {
1880: int mcycles;
1881: uae_u32 aquot;
1882: int i;
1883:
1884: if (divisor == 0)
1885: return 0;
1886:
1887: mcycles = 6;
1888:
1889: if (dividend < 0)
1890: mcycles++;
1891:
1892: // Check for absolute overflow
1893: if (((uae_u32)abs (dividend) >> 16) >= (uae_u16)abs (divisor))
1894: return (mcycles + 2) * 2;
1895:
1896: // Absolute quotient
1897: aquot = (uae_u32) abs (dividend) / (uae_u16)abs (divisor);
1898:
1899: mcycles += 55;
1900:
1901: if (divisor >= 0) {
1902: if (dividend >= 0)
1903: mcycles--;
1904: else
1905: mcycles++;
1906: }
1907:
1908: // Count 15 msbits in absolute of quotient
1909:
1910: for (i = 0; i < 15; i++) {
1911: if ((uae_s16)aquot >= 0)
1912: mcycles++;
1913: aquot <<= 1;
1914: }
1915:
1916: return mcycles * 2;
1917: }
1918: int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor)
1919: {
1920: int v = getDivs68kCycles_2 (dividend, divisor) - 4;
1921: // write_log ("S%d ", v);
1922: return v;
1923: }
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