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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation
5: *
6: * (c) 1995 Bernd Schmidt
1.1.1.2 root 7: *
8: * Adaptation to Hatari by Thomas Huth
9: *
1.1.1.6 root 10: * This file is distributed under the GNU Public License, version 2 or at
11: * your option any later version. Read the file gpl.txt for details.
1.1 root 12: */
1.1.1.12 root 13:
14:
15: /* 2007/11/12 [NP] Add HATARI_TRACE_CPU_DISASM. */
16: /* 2007/11/15 [NP] In MakeFromSR, writes to m and t0 should be ignored and set to 0 if cpu < 68020 */
17: /* 2007/11/26 [NP] We set BusErrorPC in m68k_run_1 instead of M68000_BusError, else the BusErrorPC */
18: /* will not point to the opcode that generated the bus error. */
19: /* Huge debug/work on Exceptions 2/3 stack frames, result is more accurate and */
20: /* allow to pass the very tricky Transbeauce 2 Demo's protection. */
21: /* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */
22: /* Cwik, [email protected]). */
23: /* 2007/12/06 [NP] The PC stored in the stack frame for the bus error is complex to emulate, */
24: /* because it doesn't necessarily point to the next instruction after the one that */
25: /* triggered the bus error. In the case of the Transbeauce 2 Demo, after */
26: /* 'move.l $0.w,$24.w', PC is incremented of 4 bytes, not 6, and stored in the */
27: /* stack. Special case to decrement PC of 2 bytes if opcode is '21f8'. */
28: /* This should be fixed with a real model. */
29: /* 2007/12/07 [NP] If Trace is enabled and a group 2 exception occurs (such as CHK), the trace */
30: /* handler should be called after the group 2's handler. If a bus error, address */
31: /* error or illegal occurs while Trace is enabled, the trace handler should not be */
32: /* called after this instruction (Transbeauce 2 Demo, Phaleon Demo). */
33: /* This means that if a CHK is executed while trace bit was set, we must set PC */
34: /* to CHK handler, turn trace off in the internal SR, but we must still call the */
35: /* trace handler one last time with the PC set to the CHK's handler (even if */
36: /* trace mode is internally turned off while processing an exception). Once trace */
37: /* handler is finished (RTE), we return to the CHK's handler. */
38: /* This is true for DIV BY 0, CHK, TRAPV and TRAP. */
39: /* Backport exception_trace() from WinUAE to handle this behaviour (used in */
40: /* Transbeauce 2 demo). */
41: /* 2007/12/09 [NP] 'dc.w $a' should not be used to call 'OpCode_SysInit' but should give an illegal*/
42: /* instruction (Transbeauce 2 demo). */
43: /* Instead of always replacing the illegal instructions $8, $a and $c by the */
44: /* 3 functions required for HD emulation, we now do it in cart.c only if the */
45: /* built-in cartridge image is loaded. */
46: /* YEAH! Hatari is now the first emulator to pass the Transbeauce 2 protection :) */
47: /* 2007/12/18 [NP] More precise timings for HBL, VBL and MFP interrupts. On ST, these interrupts */
48: /* are taking 56 cycles instead of the 44 cycles in the 68000's documentation. */
49: /* 2007/12/24 [NP] If an interrupt (HBL, VBL) is pending after intruction 'n' was processed, the */
50: /* exception should be called before instr. 'n+1' is processed, not after (else the*/
51: /* interrupt's handler is delayed by one 68000's instruction, which could break */
52: /* some demos with too strict timings) (ACF's Demo Main Menu). */
53: /* We call the interrupt if ( SPCFLAG_INT | SPCFLAG_DOINT ) is set, not only if */
54: /* SPCFLAG_DOINT is set (as it was already the case when handling 'STOP'). */
55: /* 2007/12/25 [NP] FIXME When handling exceptions' cycles, using nr >= 64 to determine if this is */
56: /* an MFP exception could be wrong if the MFP VR was set to another value than the */
57: /* default $40 (this could be a problem with programs requiring a precise cycles */
58: /* calculation while changing VR, but no such programs were encountered so far). */
1.1.1.13 root 59: /* -> FIXED, see 2008/10/05 */
60: /* 2008/04/17 [NP] In m68k_run_1/m68k_run_2, add the wait state cycles before testing if content */
61: /* of PendingInterruptCount is <= 0 (else the int could happen a few cycles earlier*/
62: /* than expected in some rare cases (reading $fffa21 in BIG Demo Screen 1)). */
63: /* 2008/09/14 [NP] Add the value of the new PC in the exception's log. */
64: /* 2008/09/14 [NP] Correct cycles for TRAP are 34 not 38 (4 more cycles were counted because cpuemu*/
65: /* returns 4 and Exception() adds 34) (Phaleon / Illusion Demo by Next). */
66: /* FIXME : Others exception cycles may be wrong too. */
67: /* 2008/10/05 [NP] Add a parameter 'ExceptionSource' to Exception(). This allows to know the source*/
68: /* of the exception (video, mfp, cpu) and properly handle MFP interrupts. Since */
69: /* it's possible to change the vector base in $fffa17, MFP int vectors can overlap */
70: /* the 'normal' 68000 ones and the exception number is not enough to decide. */
71: /* We need ExceptionSource to remove the ambiguity. */
72: /* Fix High Fidelity Dreams by Aura which sets MFP vector base to $c0 instead of */
73: /* $100. In that case, timer B int becomes exception nr 56 and conflicts with the */
74: /* 'MMU config error' exception, which takes 4 cycles instead of 56 cycles for MFP.*/
75: /* 2008/11/18 [NP] In 'do_specialties()', when the cpu is in the STOP state, we must test all */
76: /* possible int handlers while PendingInterruptCount <= 0 without increasing the */
77: /* cpu cycle counter. In the case where both an MFP int and an HBL occur at the */
1.1.1.14 root 78: /* same time for example, the HBL was delayed by 4 cycles if no MFP exception */
1.1.1.13 root 79: /* was triggered, which was wrong (this happened mainly with the TOS timer D that */
80: /* expires very often). Such precision is required for very recent hardscroll */
81: /* techniques that use 'stop' to stay in sync with the video shifter. */
1.1.1.14 root 82: /* 2008/11/23 [NP] In 'do_specialties()', when in STOP state, we must first test for a pending */
83: /* interrupt that would exit the STOP state immediatly, without doing a 'while' */
84: /* loop until 'SPCFLAG_INT' or 'SPCFLAG_DOINT' are set. */
85: /* 2008/11/29 [NP] Call 'InterruptAddJitter()' when a video interrupt happens to precisely emulate */
86: /* the jitter happening on the Atari (see video.c for the jitter patterns). */
87: /* FIXME : Pattern is not always correct when handling pending interrupt in STOP */
88: /* state, but this should be harmless as no program has been found using this. */
89: /* 2008/12/05 [NP] On Atari it takes 56 cycles to process an interrupt. During that time, a higher */
90: /* level interrupt could happen and we must execute it before the previous int */
91: /* (see m68k_run_1()). */
92: /* This is the case for the VBL which can interrupt the last HBL of a screen */
93: /* (end of line 312) at various point (from 0 to 8 cycles). */
94: /* This fixes the fullscreen tunnel in Suretrip 49% by Checkpoint, which uses a */
95: /* really buggy vbl/hbl combination, even on a real ST. Also fixes sample sound */
96: /* in Swedish New Year's TCB screen. */
97: /* 2008/12/11 [NP] Extract interrupt handling from do_specialties() in do_specialties_interrupt() */
98: /* and factorize some code. In m68k_run_1 when testing for multiple interrupts at */
99: /* the same time, call do_specialties_interrupt() to check only the special flags */
100: /* related to interrupts (MFP and video) (else, this caused problem when the TRACE */
101: /* flag was set). */
102: /* 2008/12/14 [NP] In m68k_run_1(), we should check for simultaneous ints only if the cpu is not */
103: /* in the STOP state after the last instruction was executed. Else, the call to */
104: /* do_specialties_interrupt() could acknowledge the interrupt and we would never */
105: /* exit the STOP state in do_specialties() just after (the problem can happen if */
106: /* the TOS timer D expires just at the same time as the STOP instruction). */
107: /* Fix regression since 2008/12/11 in the hidden screen from ULM in Oh Crickey... */
108: /* 2008/12/20 [NP] In m68k_run_1(), when checking interrupts and STOP mode, we should test */
109: /* PendingInterruptCount before regs.spcflags to have a faster evaluation of the */
110: /* 'while' condition (PendingInterruptCount <= 0 is true less often than STOP==0) */
1.1.1.12 root 111:
112:
1.1.1.15! root 113: const char NewCpu_fileid[] = "Hatari newcpu.c : " __DATE__ " " __TIME__;
1.1 root 114:
115: #include "sysdeps.h"
116: #include "hatari-glue.h"
117: #include "maccess.h"
118: #include "memory.h"
119: #include "newcpu.h"
1.1.1.5 root 120: #include "../includes/main.h"
1.1.1.10 root 121: #include "../includes/log.h"
1.1.1.7 root 122: #include "../includes/m68000.h"
1.1.1.12 root 123: #include "../includes/int.h"
1.1.1.8 root 124: #include "../includes/mfp.h"
1.1 root 125: #include "../includes/tos.h"
1.1.1.5 root 126: #include "../includes/vdi.h"
127: #include "../includes/cart.h"
128: #include "../includes/debugui.h"
1.1.1.15! root 129: #include "../includes/dialog.h"
1.1.1.8 root 130: #include "../includes/bios.h"
131: #include "../includes/xbios.h"
1.1.1.12 root 132: #include "../includes/video.h"
1.1.1.13 root 133: #include "../includes/options.h"
1.1.1.15! root 134: #include "../falcon/dsp.h"
1.1 root 135:
1.1.1.12 root 136: //#define DEBUG_PREFETCH
1.1 root 137:
138: struct flag_struct regflags;
139:
140: /* Opcode of faulting instruction */
141: uae_u16 last_op_for_exception_3;
142: /* PC at fault time */
143: uaecptr last_addr_for_exception_3;
144: /* Address that generated the exception */
145: uaecptr last_fault_for_exception_3;
146:
1.1.1.11 root 147: const int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
148: const int imm8_table[] = { 8,1,2,3,4,5,6,7 };
1.1 root 149:
150: int movem_index1[256];
151: int movem_index2[256];
152: int movem_next[256];
153:
154: int fpp_movem_index1[256];
155: int fpp_movem_index2[256];
156: int fpp_movem_next[256];
157:
158: cpuop_func *cpufunctbl[65536];
159:
1.1.1.12 root 160: int OpcodeFamily;
1.1.1.6 root 161:
1.1 root 162: #define COUNT_INSTRS 0
163:
164: #if COUNT_INSTRS
165: static unsigned long int instrcount[65536];
166: static uae_u16 opcodenums[65536];
167:
168: static int compfn (const void *el1, const void *el2)
169: {
170: return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
171: }
172:
173: static char *icountfilename (void)
174: {
175: char *name = getenv ("INSNCOUNT");
176: if (name)
177: return name;
178: return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
179: }
180:
181: void dump_counts (void)
182: {
183: FILE *f = fopen (icountfilename (), "w");
184: unsigned long int total;
185: int i;
186:
187: write_log ("Writing instruction count file...\n");
188: for (i = 0; i < 65536; i++) {
189: opcodenums[i] = i;
190: total += instrcount[i];
191: }
192: qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
193:
194: fprintf (f, "Total: %lu\n", total);
195: for (i=0; i < 65536; i++) {
196: unsigned long int cnt = instrcount[opcodenums[i]];
197: struct instr *dp;
198: struct mnemolookup *lookup;
199: if (!cnt)
200: break;
201: dp = table68k + opcodenums[i];
202: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
203: ;
204: fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
205: }
206: fclose (f);
207: }
208: #else
209: void dump_counts (void)
210: {
211: }
212: #endif
213:
214:
215: static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM;
216:
217: static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
218: {
1.1.1.6 root 219: op_illg (opcode);
1.1 root 220: return 4;
221: }
222:
1.1.1.4 root 223:
224: void build_cpufunctbl(void)
1.1 root 225: {
226: int i;
227: unsigned long opcode;
1.1.1.12 root 228: const struct cputbl *tbl = (currprefs.cpu_level == 4 ? op_smalltbl_0_ff
229: : currprefs.cpu_level == 3 ? op_smalltbl_1_ff
230: : currprefs.cpu_level == 2 ? op_smalltbl_2_ff
231: : currprefs.cpu_level == 1 ? op_smalltbl_3_ff
232: : ! currprefs.cpu_compatible ? op_smalltbl_4_ff
1.1.1.11 root 233: : op_smalltbl_5_ff);
1.1 root 234:
1.1.1.10 root 235: Log_Printf(LOG_DEBUG, "Building CPU function table (%d %d %d).\n",
1.1.1.12 root 236: currprefs.cpu_level, currprefs.cpu_compatible, currprefs.address_space_24);
1.1 root 237:
238: for (opcode = 0; opcode < 65536; opcode++)
1.1.1.6 root 239: cpufunctbl[opcode] = op_illg_1;
1.1 root 240: for (i = 0; tbl[i].handler != NULL; i++) {
241: if (! tbl[i].specific)
1.1.1.6 root 242: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 243: }
244: for (opcode = 0; opcode < 65536; opcode++) {
245: cpuop_func *f;
246:
1.1.1.12 root 247: if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > currprefs.cpu_level)
1.1 root 248: continue;
249:
250: if (table68k[opcode].handler != -1) {
1.1.1.6 root 251: f = cpufunctbl[table68k[opcode].handler];
1.1 root 252: if (f == op_illg_1)
253: abort();
1.1.1.6 root 254: cpufunctbl[opcode] = f;
1.1 root 255: }
256: }
257: for (i = 0; tbl[i].handler != NULL; i++) {
258: if (tbl[i].specific)
1.1.1.6 root 259: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 260: }
261: }
262:
263:
264:
265: void init_m68k (void)
266: {
267: int i;
268:
269: for (i = 0 ; i < 256 ; i++) {
270: int j;
271: for (j = 0 ; j < 8 ; j++) {
272: if (i & (1 << j)) break;
273: }
274: movem_index1[i] = j;
275: movem_index2[i] = 7-j;
276: movem_next[i] = i & (~(1 << j));
277: }
278: for (i = 0 ; i < 256 ; i++) {
279: int j;
280: for (j = 7 ; j >= 0 ; j--) {
281: if (i & (1 << j)) break;
282: }
283: fpp_movem_index1[i] = 7-j;
284: fpp_movem_index2[i] = j;
285: fpp_movem_next[i] = i & (~(1 << j));
286: }
287: #if COUNT_INSTRS
288: {
289: FILE *f = fopen (icountfilename (), "r");
290: memset (instrcount, 0, sizeof instrcount);
291: if (f) {
292: uae_u32 opcode, count, total;
293: char name[20];
294: write_log ("Reading instruction count file...\n");
295: fscanf (f, "Total: %lu\n", &total);
296: while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
297: instrcount[opcode] = count;
298: }
299: fclose(f);
300: }
301: }
302: #endif
303: write_log ("Building CPU table for configuration: 68");
1.1.1.12 root 304: if (currprefs.address_space_24 && currprefs.cpu_level > 1)
1.1 root 305: write_log ("EC");
1.1.1.12 root 306: switch (currprefs.cpu_level) {
1.1 root 307: case 1:
308: write_log ("010");
309: break;
310: case 2:
311: write_log ("020");
312: break;
313: case 3:
314: write_log ("020/881");
315: break;
316: case 4:
317: /* Who is going to miss the MMU anyway...? :-) */
318: write_log ("040");
319: break;
320: default:
321: write_log ("000");
322: break;
323: }
1.1.1.12 root 324: if (currprefs.cpu_compatible)
1.1 root 325: write_log (" (compatible mode)");
326: write_log ("\n");
1.1.1.7 root 327:
1.1 root 328: read_table68k ();
329: do_merges ();
330:
1.1.1.10 root 331: Log_Printf(LOG_DEBUG, "%d CPU functions\n", nr_cpuop_funcs);
1.1 root 332:
333: build_cpufunctbl ();
334: }
335:
1.1.1.4 root 336:
1.1.1.8 root 337: /* not used ATM:
1.1 root 338: static struct regstruct regs_backup[16];
339: static int backup_pointer = 0;
1.1.1.10 root 340: struct regstruct lastint_regs;
341: int lastint_no;
1.1.1.8 root 342: */
1.1.1.10 root 343: struct regstruct regs;
1.1 root 344: static long int m68kpc_offset;
1.1.1.10 root 345:
1.1 root 346:
347: #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
348: #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
349: #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
350:
351: uae_s32 ShowEA (FILE *f, int reg, amodes mode, wordsizes size, char *buf)
352: {
353: uae_u16 dp;
354: uae_s8 disp8;
355: uae_s16 disp16;
356: int r;
357: uae_u32 dispreg;
358: uaecptr addr;
359: uae_s32 offset = 0;
360: char buffer[80];
361:
362: switch (mode){
363: case Dreg:
364: sprintf (buffer,"D%d", reg);
365: break;
366: case Areg:
367: sprintf (buffer,"A%d", reg);
368: break;
369: case Aind:
370: sprintf (buffer,"(A%d)", reg);
371: break;
372: case Aipi:
373: sprintf (buffer,"(A%d)+", reg);
374: break;
375: case Apdi:
376: sprintf (buffer,"-(A%d)", reg);
377: break;
378: case Ad16:
379: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
380: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
381: sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
382: (unsigned long)addr);
383: break;
384: case Ad8r:
385: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
386: disp8 = dp & 0xFF;
387: r = (dp & 0x7000) >> 12;
388: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
389: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
390: dispreg <<= (dp >> 9) & 3;
391:
392: if (dp & 0x100) {
393: uae_s32 outer = 0, disp = 0;
394: uae_s32 base = m68k_areg(regs,reg);
395: char name[10];
396: sprintf (name,"A%d, ",reg);
397: if (dp & 0x80) { base = 0; name[0] = 0; }
398: if (dp & 0x40) dispreg = 0;
399: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
400: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
401: base += disp;
402:
403: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
404: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
405:
406: if (!(dp & 4)) base += dispreg;
407: if (dp & 3) base = get_long (base);
408: if (dp & 4) base += dispreg;
409:
410: addr = base + outer;
411: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
412: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
413: 1 << ((dp >> 9) & 3),
1.1.1.5 root 414: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 415: } else {
416: addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
417: sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
418: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
419: 1 << ((dp >> 9) & 3), disp8,
420: (unsigned long)addr);
421: }
422: break;
423: case PC16:
424: addr = m68k_getpc () + m68kpc_offset;
425: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
426: addr += (uae_s16)disp16;
427: sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
428: break;
429: case PC8r:
430: addr = m68k_getpc () + m68kpc_offset;
431: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
432: disp8 = dp & 0xFF;
433: r = (dp & 0x7000) >> 12;
434: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
435: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
436: dispreg <<= (dp >> 9) & 3;
437:
438: if (dp & 0x100) {
439: uae_s32 outer = 0,disp = 0;
440: uae_s32 base = addr;
441: char name[10];
442: sprintf (name,"PC, ");
443: if (dp & 0x80) { base = 0; name[0] = 0; }
444: if (dp & 0x40) dispreg = 0;
445: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
446: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
447: base += disp;
448:
449: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
450: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
451:
452: if (!(dp & 4)) base += dispreg;
453: if (dp & 3) base = get_long (base);
454: if (dp & 4) base += dispreg;
455:
456: addr = base + outer;
457: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
458: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
459: 1 << ((dp >> 9) & 3),
1.1.1.5 root 460: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 461: } else {
462: addr += (uae_s32)((uae_s8)disp8) + dispreg;
463: sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
464: (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
465: disp8, (unsigned long)addr);
466: }
467: break;
468: case absw:
469: sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
470: m68kpc_offset += 2;
471: break;
472: case absl:
473: sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
474: m68kpc_offset += 4;
475: break;
476: case imm:
477: switch (size){
478: case sz_byte:
479: sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
480: m68kpc_offset += 2;
481: break;
482: case sz_word:
483: sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
484: m68kpc_offset += 2;
485: break;
486: case sz_long:
487: sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
488: m68kpc_offset += 4;
489: break;
490: default:
491: break;
492: }
493: break;
494: case imm0:
495: offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
496: m68kpc_offset += 2;
497: sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
498: break;
499: case imm1:
500: offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
501: m68kpc_offset += 2;
502: sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
503: break;
504: case imm2:
505: offset = (uae_s32)get_ilong_1 (m68kpc_offset);
506: m68kpc_offset += 4;
507: sprintf (buffer,"#$%08lx", (unsigned long)offset);
508: break;
509: case immi:
510: offset = (uae_s32)(uae_s8)(reg & 0xff);
511: sprintf (buffer,"#$%08lx", (unsigned long)offset);
512: break;
513: default:
514: break;
515: }
516: if (buf == 0)
517: fprintf (f, "%s", buffer);
518: else
519: strcat (buf, buffer);
520: return offset;
521: }
522:
1.1.1.8 root 523:
1.1 root 524: /* The plan is that this will take over the job of exception 3 handling -
525: * the CPU emulation functions will just do a longjmp to m68k_go whenever
526: * they hit an odd address. */
1.1.1.8 root 527: #if 0
1.1 root 528: static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
529: {
530: uae_u16 dp;
531: uae_s8 disp8;
532: uae_s16 disp16;
533: int r;
534: uae_u32 dispreg;
535: uaecptr addr;
1.1.1.5 root 536: /*uae_s32 offset = 0;*/
1.1 root 537:
538: switch (mode){
539: case Dreg:
540: *val = m68k_dreg (regs, reg);
541: return 1;
542: case Areg:
543: *val = m68k_areg (regs, reg);
544: return 1;
545:
546: case Aind:
547: case Aipi:
548: addr = m68k_areg (regs, reg);
549: break;
550: case Apdi:
551: addr = m68k_areg (regs, reg);
552: break;
553: case Ad16:
554: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
555: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
556: break;
557: case Ad8r:
558: addr = m68k_areg (regs, reg);
559: d8r_common:
560: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
561: disp8 = dp & 0xFF;
562: r = (dp & 0x7000) >> 12;
563: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
564: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
565: dispreg <<= (dp >> 9) & 3;
566:
567: if (dp & 0x100) {
568: uae_s32 outer = 0, disp = 0;
569: uae_s32 base = addr;
570: if (dp & 0x80) base = 0;
571: if (dp & 0x40) dispreg = 0;
572: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
573: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
574: base += disp;
575:
576: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
577: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
578:
579: if (!(dp & 4)) base += dispreg;
580: if (dp & 3) base = get_long (base);
581: if (dp & 4) base += dispreg;
582:
583: addr = base + outer;
584: } else {
585: addr += (uae_s32)((uae_s8)disp8) + dispreg;
586: }
587: break;
588: case PC16:
589: addr = m68k_getpc () + m68kpc_offset;
590: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
591: addr += (uae_s16)disp16;
592: break;
593: case PC8r:
594: addr = m68k_getpc () + m68kpc_offset;
595: goto d8r_common;
596: case absw:
597: addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
598: m68kpc_offset += 2;
599: break;
600: case absl:
601: addr = get_ilong_1 (m68kpc_offset);
602: m68kpc_offset += 4;
603: break;
604: case imm:
605: switch (size){
606: case sz_byte:
607: *val = get_iword_1 (m68kpc_offset) & 0xff;
608: m68kpc_offset += 2;
609: break;
610: case sz_word:
611: *val = get_iword_1 (m68kpc_offset) & 0xffff;
612: m68kpc_offset += 2;
613: break;
614: case sz_long:
615: *val = get_ilong_1 (m68kpc_offset);
616: m68kpc_offset += 4;
617: break;
618: default:
619: break;
620: }
621: return 1;
622: case imm0:
623: *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
624: m68kpc_offset += 2;
625: return 1;
626: case imm1:
627: *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
628: m68kpc_offset += 2;
629: return 1;
630: case imm2:
631: *val = get_ilong_1 (m68kpc_offset);
632: m68kpc_offset += 4;
633: return 1;
634: case immi:
635: *val = (uae_s32)(uae_s8)(reg & 0xff);
636: return 1;
637: default:
638: addr = 0;
639: break;
640: }
641: if ((addr & 1) == 0)
642: return 1;
643:
644: last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
645: last_fault_for_exception_3 = addr;
646: return 0;
647: }
1.1.1.8 root 648: #endif
649:
1.1 root 650:
651: uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
652: {
653: int reg = (dp >> 12) & 15;
654: uae_s32 regd = regs.regs[reg];
655: if ((dp & 0x800) == 0)
656: regd = (uae_s32)(uae_s16)regd;
657: regd <<= (dp >> 9) & 3;
658: if (dp & 0x100) {
659: uae_s32 outer = 0;
660: if (dp & 0x80) base = 0;
661: if (dp & 0x40) regd = 0;
662:
663: if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
664: if ((dp & 0x30) == 0x30) base += next_ilong();
665:
666: if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
667: if ((dp & 0x3) == 0x3) outer = next_ilong();
668:
669: if ((dp & 0x4) == 0) base += regd;
670: if (dp & 0x3) base = get_long (base);
671: if (dp & 0x4) base += regd;
672:
673: return base + outer;
674: } else {
675: return base + (uae_s32)((uae_s8)dp) + regd;
676: }
677: }
678:
679: uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
680: {
681: int reg = (dp >> 12) & 15;
682: uae_s32 regd = regs.regs[reg];
683: #if 1
684: if ((dp & 0x800) == 0)
685: regd = (uae_s32)(uae_s16)regd;
686: return base + (uae_s8)dp + regd;
687: #else
688: /* Branch-free code... benchmark this again now that
689: * things are no longer inline. */
690: uae_s32 regd16;
691: uae_u32 mask;
692: mask = ((dp & 0x800) >> 11) - 1;
693: regd16 = (uae_s32)(uae_s16)regd;
694: regd16 &= mask;
695: mask = ~mask;
696: base += (uae_s8)dp;
697: regd &= mask;
698: regd |= regd16;
699: return base + regd;
700: #endif
701: }
702:
1.1.1.8 root 703:
704: /* Create the Status Register from the flags */
1.1 root 705: void MakeSR (void)
706: {
707: #if 0
708: assert((regs.t1 & 1) == regs.t1);
709: assert((regs.t0 & 1) == regs.t0);
710: assert((regs.s & 1) == regs.s);
711: assert((regs.m & 1) == regs.m);
712: assert((XFLG & 1) == XFLG);
713: assert((NFLG & 1) == NFLG);
714: assert((ZFLG & 1) == ZFLG);
715: assert((VFLG & 1) == VFLG);
716: assert((CFLG & 1) == CFLG);
717: #endif
718: regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
719: | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
720: | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
721: | GET_CFLG);
722: }
723:
1.1.1.8 root 724:
725: /* Set up the flags from Status Register */
1.1 root 726: void MakeFromSR (void)
727: {
728: int oldm = regs.m;
729: int olds = regs.s;
730:
731: regs.t1 = (regs.sr >> 15) & 1;
732: regs.t0 = (regs.sr >> 14) & 1;
733: regs.s = (regs.sr >> 13) & 1;
734: regs.m = (regs.sr >> 12) & 1;
735: regs.intmask = (regs.sr >> 8) & 7;
736: SET_XFLG ((regs.sr >> 4) & 1);
737: SET_NFLG ((regs.sr >> 3) & 1);
738: SET_ZFLG ((regs.sr >> 2) & 1);
739: SET_VFLG ((regs.sr >> 1) & 1);
740: SET_CFLG (regs.sr & 1);
1.1.1.12 root 741: if (currprefs.cpu_level >= 2) {
1.1 root 742: if (olds != regs.s) {
743: if (olds) {
744: if (oldm)
745: regs.msp = m68k_areg(regs, 7);
746: else
747: regs.isp = m68k_areg(regs, 7);
748: m68k_areg(regs, 7) = regs.usp;
749: } else {
750: regs.usp = m68k_areg(regs, 7);
751: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
752: }
753: } else if (olds && oldm != regs.m) {
754: if (oldm) {
755: regs.msp = m68k_areg(regs, 7);
756: m68k_areg(regs, 7) = regs.isp;
757: } else {
758: regs.isp = m68k_areg(regs, 7);
759: m68k_areg(regs, 7) = regs.msp;
760: }
761: }
762: } else {
1.1.1.12 root 763: /* [NP] If cpu < 68020, m and t0 are ignored and should be set to 0 */
764: regs.t0 = 0;
765: regs.m = 0;
766:
1.1 root 767: if (olds != regs.s) {
768: if (olds) {
769: regs.isp = m68k_areg(regs, 7);
770: m68k_areg(regs, 7) = regs.usp;
771: } else {
772: regs.usp = m68k_areg(regs, 7);
773: m68k_areg(regs, 7) = regs.isp;
774: }
775: }
776: }
777:
1.1.1.8 root 778: /* Pending interrupts can occur again after a write to the SR: */
779: set_special (SPCFLAG_DOINT);
1.1 root 780: if (regs.t1 || regs.t0)
781: set_special (SPCFLAG_TRACE);
782: else
1.1.1.6 root 783: /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
784: SR-modifying instructions (including STOP). */
785: unset_special (SPCFLAG_TRACE);
1.1 root 786: }
787:
1.1.1.5 root 788:
1.1.1.12 root 789: static void exception_trace (int nr)
790: {
791: unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
792: if (regs.t1 && !regs.t0) {
793: /* trace stays pending if exception is div by zero, chk,
794: * trapv or trap #x
795: */
796: if (nr == 5 || nr == 6 || nr == 7 || (nr >= 32 && nr <= 47))
797: set_special (SPCFLAG_DOTRACE);
798: }
799: regs.t1 = regs.t0 = regs.m = 0;
800: }
801:
802:
1.1.1.14 root 803: /*
804: * Compute the number of jitter cycles to add when a video interrupt occurs
805: * (this is specific to the Atari ST)
806: */
807: static void InterruptAddJitter (int Level , int Pending)
808: {
809: int cycles = 0;
810:
811: if ( Level == 2 ) /* HBL */
812: {
813: if ( Pending )
814: cycles = HblJitterArrayPending[ HblJitterIndex ];
815: else
816: cycles = HblJitterArray[ HblJitterIndex ];
817: }
818:
819: else if ( Level == 4 ) /* VBL */
820: {
821: if ( Pending )
822: cycles = VblJitterArrayPending[ VblJitterIndex ];
823: else
824: cycles = VblJitterArray[ VblJitterIndex ];
825: }
826:
827: //fprintf ( stderr , "jitter %d\n" , cycles );
828: //cycles=0;
829: if ( cycles > 0 ) /* no need to call M68000_AddCycles if cycles == 0 */
830: M68000_AddCycles ( cycles );
831: }
832:
833:
1.1.1.13 root 834: /* Handle exceptions. We need a special case to handle MFP exceptions */
835: /* on Atari ST, because it's possible to change the MFP's vector base */
836: /* and get a conflict with 'normal' cpu exceptions. */
837: void Exception(int nr, uaecptr oldpc, int ExceptionSource)
1.1 root 838: {
839: uae_u32 currpc = m68k_getpc ();
840:
1.1.1.2 root 841: /*if( nr>=2 && nr<10 ) fprintf(stderr,"Exception (-> %i bombs)!\n",nr);*/
1.1 root 842:
1.1.1.7 root 843: /* Intercept VDI exception (Trap #2 with D0 = 0x73) */
1.1.1.13 root 844: if ( ExceptionSource != M68000_EXCEPTION_SRC_INT_MFP )
1.1.1.5 root 845: {
1.1.1.13 root 846: if(bUseVDIRes && nr == 0x22 && regs.regs[0] == 0x73)
847: {
848: if(!VDI())
849: {
850: /* Set 'PC' as address of 'VDI_OPCODE' illegal instruction
851: * This will call OpCode_VDI after completion of Trap call!
852: * Use to modify return structure from VDI */
853: VDI_OldPC = currpc;
854: currpc = CART_VDI_OPCODE_ADDR;
855: }
856: }
857:
858: if (bBiosIntercept)
859: {
860: /* Intercept BIOS or XBIOS trap (Trap #13 or #14) */
861: if (nr == 0x2d)
862: {
863: /* Intercept BIOS calls */
864: if (Bios()) return;
865: }
866: else if (nr == 0x2e)
867: {
868: /* Intercept XBIOS calls */
869: if (XBios()) return;
870: }
871: }
1.1.1.5 root 872: }
1.1.1.8 root 873:
1.1 root 874: MakeSR();
875:
1.1.1.8 root 876: /* Change to supervisor mode if necessary */
1.1 root 877: if (!regs.s) {
878: regs.usp = m68k_areg(regs, 7);
1.1.1.12 root 879: if (currprefs.cpu_level >= 2)
1.1 root 880: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
881: else
882: m68k_areg(regs, 7) = regs.isp;
883: regs.s = 1;
884: }
1.1.1.8 root 885:
886: /* Build additional exception stack frame for 68010 and higher */
1.1.1.13 root 887: /* (special case for MFP) */
1.1.1.12 root 888: if (currprefs.cpu_level > 0) {
1.1.1.13 root 889: if (ExceptionSource == M68000_EXCEPTION_SRC_INT_MFP) {
890: m68k_areg(regs, 7) -= 2;
891: put_word (m68k_areg(regs, 7), nr * 4); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
892: }
893: else if (nr == 2 || nr == 3) {
1.1 root 894: int i;
895: /* @@@ this is probably wrong (?) */
896: for (i = 0 ; i < 12 ; i++) {
897: m68k_areg(regs, 7) -= 2;
898: put_word (m68k_areg(regs, 7), 0);
899: }
900: m68k_areg(regs, 7) -= 2;
901: put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
902: } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
903: m68k_areg(regs, 7) -= 4;
904: put_long (m68k_areg(regs, 7), oldpc);
905: m68k_areg(regs, 7) -= 2;
906: put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
907: } else if (regs.m && nr >= 24 && nr < 32) {
908: m68k_areg(regs, 7) -= 2;
909: put_word (m68k_areg(regs, 7), nr * 4);
910: m68k_areg(regs, 7) -= 4;
911: put_long (m68k_areg(regs, 7), currpc);
912: m68k_areg(regs, 7) -= 2;
913: put_word (m68k_areg(regs, 7), regs.sr);
914: regs.sr |= (1 << 13);
915: regs.msp = m68k_areg(regs, 7);
916: m68k_areg(regs, 7) = regs.isp;
917: m68k_areg(regs, 7) -= 2;
918: put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
919: } else {
920: m68k_areg(regs, 7) -= 2;
921: put_word (m68k_areg(regs, 7), nr * 4);
922: }
923: }
1.1.1.3 root 924:
925: /* Push PC on stack: */
1.1 root 926: m68k_areg(regs, 7) -= 4;
927: put_long (m68k_areg(regs, 7), currpc);
1.1.1.3 root 928: /* Push SR on stack: */
1.1 root 929: m68k_areg(regs, 7) -= 2;
930: put_word (m68k_areg(regs, 7), regs.sr);
1.1.1.3 root 931:
1.1.1.15! root 932: LOG_TRACE(TRACE_CPU_EXCEPTION, "cpu exception %d currpc %x buspc %x newpc %x fault_e3 %x op_e3 %hx addr_e3 %x\n",
! 933: nr, currpc, BusErrorPC, get_long (regs.vbr + 4*nr), last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3);
1.1.1.12 root 934:
1.1.1.3 root 935: /* 68000 bus/address errors: */
1.1.1.13 root 936: if (currprefs.cpu_level==0 && (nr==2 || nr==3) && (ExceptionSource != M68000_EXCEPTION_SRC_INT_MFP) ) {
1.1.1.12 root 937: uae_u16 specialstatus = 1;
938:
1.1.1.8 root 939: /* Special status word emulation isn't perfect yet... :-( */
940: if (regs.sr & 0x2000)
941: specialstatus |= 0x4;
1.1.1.3 root 942: m68k_areg(regs, 7) -= 8;
943: if (nr == 3) { /* Address error */
1.1.1.12 root 944: specialstatus |= ( last_op_for_exception_3 & (~0x1f) ); /* [NP] unused bits of specialstatus are those of the last opcode ! */
1.1.1.8 root 945: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.3 root 946: put_long (m68k_areg(regs, 7)+2, last_fault_for_exception_3);
947: put_word (m68k_areg(regs, 7)+6, last_op_for_exception_3);
948: put_long (m68k_areg(regs, 7)+10, last_addr_for_exception_3);
1.1.1.15! root 949: if (bExceptionDebugging) {
1.1.1.8 root 950: fprintf(stderr,"Address Error at address $%x, PC=$%x\n",last_fault_for_exception_3,currpc);
951: DebugUI();
952: }
1.1.1.3 root 953: }
1.1.1.8 root 954: else { /* Bus error */
1.1.1.12 root 955: specialstatus |= ( get_word(BusErrorPC) & (~0x1f) ); /* [NP] unused bits of special status are those of the last opcode ! */
1.1.1.8 root 956: if (bBusErrorReadWrite)
957: specialstatus |= 0x10;
958: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.10 root 959: put_long (m68k_areg(regs, 7)+2, BusErrorAddress);
1.1.1.12 root 960: put_word (m68k_areg(regs, 7)+6, get_word(BusErrorPC)); /* Opcode */
961:
962: /* [NP] PC stored in the stack frame is not necessarily pointing to the next instruction ! */
963: /* FIXME : we should have a proper model for this, in the meantime we handle specific cases */
964: if ( get_word(BusErrorPC) == 0x21f8 ) /* move.l $0.w,$24.w (Transbeauce 2 loader) */
965: put_long (m68k_areg(regs, 7)+10, currpc-2); /* correct PC is 2 bytes less than usual value */
1.1.1.8 root 966: /* Check for double bus errors: */
967: if (regs.spcflags & SPCFLAG_BUSERROR) {
968: fprintf(stderr, "Detected double bus error at address $%x, PC=$%lx => CPU halted!\n",
1.1.1.10 root 969: BusErrorAddress, (long)currpc);
1.1.1.8 root 970: unset_special(SPCFLAG_BUSERROR);
1.1.1.15! root 971: if (bExceptionDebugging)
1.1.1.8 root 972: DebugUI();
1.1.1.15! root 973: else
! 974: DlgAlert_Notice("Detected double bus error => CPU halted!\nEmulation needs to be reseted.\n");
1.1.1.8 root 975: regs.intmask = 7;
1.1.1.15! root 976: m68k_setstopped(true);
1.1.1.8 root 977: return;
978: }
1.1.1.15! root 979: if (bExceptionDebugging && BusErrorAddress!=0xff8a00) {
1.1.1.10 root 980: fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n", BusErrorAddress, (long)currpc);
1.1.1.8 root 981: DebugUI();
982: }
983: }
1.1.1.3 root 984: }
985:
1.1.1.8 root 986: /* Set PC and flags */
1.1.1.15! root 987: if (bExceptionDebugging && get_long (regs.vbr + 4*nr) == 0) {
1.1.1.8 root 988: write_log("Uninitialized exception handler #%i!\n", nr);
1.1.1.13 root 989: DebugUI();
1.1.1.8 root 990: }
1.1 root 991: m68k_setpc (get_long (regs.vbr + 4*nr));
992: fill_prefetch_0 ();
1.1.1.12 root 993: /* Handle trace flags depending on current state */
994: exception_trace (nr);
1.1.1.6 root 995:
1.1.1.13 root 996: /* Handle exception cycles (special case for MFP) */
997: if ( ExceptionSource == M68000_EXCEPTION_SRC_INT_MFP )
998: {
999: M68000_AddCycles(44+12); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
1000: }
1001: else if (nr >= 24 && nr <= 31)
1.1.1.7 root 1002: {
1.1.1.15! root 1003: if ( nr == 26 ) /* HBL */
! 1004: {
! 1005: /* store current cycle pos when then interrupt was received (see video.c) */
! 1006: LastCycleHblException = Cycles_GetCounter(CYCLES_COUNTER_VIDEO);
! 1007: M68000_AddCycles(44+12); /* Video Interrupt */
! 1008: }
! 1009: else if ( nr == 28 ) /* VBL */
1.1.1.12 root 1010: M68000_AddCycles(44+12); /* Video Interrupt */
1011: else
1012: M68000_AddCycles(44+4); /* Other Interrupts */
1.1.1.7 root 1013: }
1014: else if(nr >= 32 && nr <= 47)
1015: {
1.1.1.13 root 1016: M68000_AddCycles(34-4); /* Trap (total is 34, but cpuemu.c already adds 4) */
1.1.1.7 root 1017: }
1018: else switch(nr)
1019: {
1.1.1.12 root 1020: case 2: M68000_AddCycles(50); break; /* Bus error */
1021: case 3: M68000_AddCycles(50); break; /* Address error */
1022: case 4: M68000_AddCycles(34); break; /* Illegal instruction */
1023: case 5: M68000_AddCycles(38); break; /* Div by zero */
1024: case 6: M68000_AddCycles(40); break; /* CHK */
1025: case 7: M68000_AddCycles(34); break; /* TRAPV */
1026: case 8: M68000_AddCycles(34); break; /* Privilege violation */
1027: case 9: M68000_AddCycles(34); break; /* Trace */
1028: case 10: M68000_AddCycles(34); break; /* Line-A - probably wrong */
1029: case 11: M68000_AddCycles(34); break; /* Line-F - probably wrong */
1.1.1.7 root 1030: default:
1.1.1.8 root 1031: /* FIXME: Add right cycles value for MFP interrupts and copro exceptions ... */
1.1.1.7 root 1032: if(nr < 64)
1.1.1.12 root 1033: M68000_AddCycles(4); /* Coprocessor and unassigned exceptions (???) */
1.1.1.7 root 1034: else
1.1.1.13 root 1035: M68000_AddCycles(44+12); /* Must be a MFP interrupt, should be processed above */
1.1.1.7 root 1036: break;
1.1.1.6 root 1037: }
1.1.1.14 root 1038:
1.1 root 1039: }
1040:
1.1.1.7 root 1041:
1.1.1.14 root 1042: static void Interrupt(int nr , int Pending)
1.1 root 1043: {
1044: assert(nr < 8 && nr >= 0);
1.1.1.10 root 1045: /*lastint_regs = regs;*/
1046: /*lastint_no = nr;*/
1.1.1.13 root 1047:
1048: /* [NP] On Hatari, only video ints are using SPCFLAG_INT (see m68000.c) */
1049: /* TODO : to be really precise, we should use a global variable to store the last ExceptionSource */
1050: /* passed to M68000_Exception, instead of hardcoding M68000_EXCEPTION_SRC_INT_VIDEO here */
1051: Exception(nr+24, 0, M68000_EXCEPTION_SRC_INT_VIDEO);
1.1 root 1052:
1053: regs.intmask = nr;
1054: set_special (SPCFLAG_INT);
1.1.1.14 root 1055:
1056: /* Handle Atari ST's specific jitter for hbl/vbl */
1057: InterruptAddJitter ( nr , Pending );
1.1 root 1058: }
1059:
1.1.1.7 root 1060:
1.1.1.12 root 1061: uae_u32 caar, cacr;
1.1.1.8 root 1062: static uae_u32 itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp;
1.1 root 1063:
1.1.1.7 root 1064:
1.1.1.12 root 1065: static int movec_illg (int regno)
1066: {
1067: int regno2 = regno & 0x7ff;
1068: if (currprefs.cpu_level == 1) { /* 68010 */
1069: if (regno2 < 2)
1070: return 0;
1071: return 1;
1072: }
1073: if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) { /* 68020 */
1074: if (regno == 3) return 1; /* 68040 only */
1075: /* 4 is >=68040, but 0x804 is in 68020 */
1076: if (regno2 < 4 || regno == 0x804)
1077: return 0;
1078: return 1;
1079: }
1080: if (currprefs.cpu_level >= 4) { /* 68040 */
1081: if (regno == 0x802) return 1; /* 68020 only */
1082: if (regno2 < 8) return 0;
1083: if (currprefs.cpu_level == 6 && regno2 == 8) /* 68060 only */
1084: return 0;
1085: return 1;
1086: }
1087: return 1;
1088: }
1089:
1.1 root 1090: int m68k_move2c (int regno, uae_u32 *regp)
1091: {
1.1.1.12 root 1092: if (movec_illg (regno)) {
1.1 root 1093: op_illg (0x4E7B);
1094: return 0;
1095: } else {
1096: switch (regno) {
1097: case 0: regs.sfc = *regp & 7; break;
1098: case 1: regs.dfc = *regp & 7; break;
1.1.1.12 root 1099: case 2: cacr = *regp & (currprefs.cpu_level < 4 ? 0x3 : 0x80008000); break;
1.1 root 1100: case 3: tc = *regp & 0xc000; break;
1101: /* Mask out fields that should be zero. */
1102: case 4: itt0 = *regp & 0xffffe364; break;
1103: case 5: itt1 = *regp & 0xffffe364; break;
1104: case 6: dtt0 = *regp & 0xffffe364; break;
1105: case 7: dtt1 = *regp & 0xffffe364; break;
1.1.1.7 root 1106:
1.1 root 1107: case 0x800: regs.usp = *regp; break;
1108: case 0x801: regs.vbr = *regp; break;
1.1.1.12 root 1109: case 0x802: caar = *regp & 0xfc; break;
1.1 root 1110: case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
1111: case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
1.1.1.6 root 1112: case 0x805: mmusr = *regp; break;
1113: case 0x806: urp = *regp; break;
1114: case 0x807: srp = *regp; break;
1.1 root 1115: default:
1116: op_illg (0x4E7B);
1117: return 0;
1118: }
1119: }
1120: return 1;
1121: }
1122:
1123: int m68k_movec2 (int regno, uae_u32 *regp)
1124: {
1.1.1.12 root 1125: if (movec_illg (regno)) {
1.1 root 1126: op_illg (0x4E7A);
1127: return 0;
1128: } else {
1129: switch (regno) {
1130: case 0: *regp = regs.sfc; break;
1131: case 1: *regp = regs.dfc; break;
1.1.1.12 root 1132: case 2: *regp = cacr; break;
1.1 root 1133: case 3: *regp = tc; break;
1134: case 4: *regp = itt0; break;
1135: case 5: *regp = itt1; break;
1136: case 6: *regp = dtt0; break;
1137: case 7: *regp = dtt1; break;
1138: case 0x800: *regp = regs.usp; break;
1139: case 0x801: *regp = regs.vbr; break;
1.1.1.12 root 1140: case 0x802: *regp = caar; break;
1.1 root 1141: case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
1142: case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
1143: case 0x805: *regp = mmusr; break;
1.1.1.6 root 1144: case 0x806: *regp = urp; break;
1145: case 0x807: *regp = srp; break;
1.1 root 1146: default:
1147: op_illg (0x4E7A);
1148: return 0;
1149: }
1150: }
1151: return 1;
1152: }
1153:
1154: STATIC_INLINE int
1.1.1.10 root 1155: div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 ndiv, uae_u32 *quot, uae_u32 *rem)
1.1 root 1156: {
1157: uae_u32 q = 0, cbit = 0;
1158: int i;
1159:
1.1.1.10 root 1160: if (ndiv <= src_hi) {
1.1 root 1161: return 1;
1162: }
1163: for (i = 0 ; i < 32 ; i++) {
1164: cbit = src_hi & 0x80000000ul;
1165: src_hi <<= 1;
1166: if (src_lo & 0x80000000ul) src_hi++;
1167: src_lo <<= 1;
1168: q = q << 1;
1.1.1.10 root 1169: if (cbit || ndiv <= src_hi) {
1.1 root 1170: q |= 1;
1.1.1.10 root 1171: src_hi -= ndiv;
1.1 root 1172: }
1173: }
1174: *quot = q;
1175: *rem = src_hi;
1176: return 0;
1177: }
1178:
1179: void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
1180: {
1181: #if defined(uae_s64)
1182: if (src == 0) {
1.1.1.13 root 1183: Exception (5, oldpc,M68000_EXCEPTION_SRC_CPU);
1.1 root 1184: return;
1185: }
1186: if (extra & 0x800) {
1187: /* signed variant */
1188: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1189: uae_s64 quot, rem;
1190:
1191: if (extra & 0x400) {
1192: a &= 0xffffffffu;
1193: a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
1194: }
1195: rem = a % (uae_s64)(uae_s32)src;
1196: quot = a / (uae_s64)(uae_s32)src;
1197: if ((quot & UVAL64(0xffffffff80000000)) != 0
1198: && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1199: {
1200: SET_VFLG (1);
1201: SET_NFLG (1);
1202: SET_CFLG (0);
1203: } else {
1204: if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
1205: SET_VFLG (0);
1206: SET_CFLG (0);
1207: SET_ZFLG (((uae_s32)quot) == 0);
1208: SET_NFLG (((uae_s32)quot) < 0);
1209: m68k_dreg(regs, extra & 7) = rem;
1210: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1211: }
1212: } else {
1213: /* unsigned */
1214: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1215: uae_u64 quot, rem;
1216:
1217: if (extra & 0x400) {
1218: a &= 0xffffffffu;
1219: a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
1220: }
1221: rem = a % (uae_u64)src;
1222: quot = a / (uae_u64)src;
1223: if (quot > 0xffffffffu) {
1224: SET_VFLG (1);
1225: SET_NFLG (1);
1226: SET_CFLG (0);
1227: } else {
1228: SET_VFLG (0);
1229: SET_CFLG (0);
1230: SET_ZFLG (((uae_s32)quot) == 0);
1231: SET_NFLG (((uae_s32)quot) < 0);
1232: m68k_dreg(regs, extra & 7) = rem;
1233: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1234: }
1235: }
1236: #else
1237: if (src == 0) {
1.1.1.13 root 1238: Exception (5, oldpc,M68000_EXCEPTION_SRC_CPU);
1.1 root 1239: return;
1240: }
1241: if (extra & 0x800) {
1242: /* signed variant */
1243: uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1244: uae_s32 hi = lo < 0 ? -1 : 0;
1245: uae_s32 save_high;
1246: uae_u32 quot, rem;
1247: uae_u32 sign;
1248:
1249: if (extra & 0x400) {
1250: hi = (uae_s32)m68k_dreg(regs, extra & 7);
1251: }
1252: save_high = hi;
1253: sign = (hi ^ src);
1254: if (hi < 0) {
1255: hi = ~hi;
1256: lo = -lo;
1257: if (lo == 0) hi++;
1258: }
1259: if ((uae_s32)src < 0) src = -src;
1260: if (div_unsigned(hi, lo, src, ", &rem) ||
1261: (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
1262: SET_VFLG (1);
1263: SET_NFLG (1);
1264: SET_CFLG (0);
1265: } else {
1266: if (sign & 0x80000000) quot = -quot;
1267: if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
1268: SET_VFLG (0);
1269: SET_CFLG (0);
1270: SET_ZFLG (((uae_s32)quot) == 0);
1271: SET_NFLG (((uae_s32)quot) < 0);
1272: m68k_dreg(regs, extra & 7) = rem;
1273: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1274: }
1275: } else {
1276: /* unsigned */
1277: uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1278: uae_u32 hi = 0;
1279: uae_u32 quot, rem;
1280:
1281: if (extra & 0x400) {
1282: hi = (uae_u32)m68k_dreg(regs, extra & 7);
1283: }
1284: if (div_unsigned(hi, lo, src, ", &rem)) {
1285: SET_VFLG (1);
1286: SET_NFLG (1);
1287: SET_CFLG (0);
1288: } else {
1289: SET_VFLG (0);
1290: SET_CFLG (0);
1291: SET_ZFLG (((uae_s32)quot) == 0);
1292: SET_NFLG (((uae_s32)quot) < 0);
1293: m68k_dreg(regs, extra & 7) = rem;
1294: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1295: }
1296: }
1297: #endif
1298: }
1299:
1300: STATIC_INLINE void
1301: mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1302: {
1303: uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1304: uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1305: uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1306: uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1307: uae_u32 lo;
1308:
1309: lo = r0 + ((r1 << 16) & 0xffff0000ul);
1310: if (lo < r0) r3++;
1311: r0 = lo;
1312: lo = r0 + ((r2 << 16) & 0xffff0000ul);
1313: if (lo < r0) r3++;
1314: r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1315: *dst_lo = lo;
1316: *dst_hi = r3;
1317: }
1318:
1319: void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1320: {
1321: #if defined(uae_s64)
1322: if (extra & 0x800) {
1323: /* signed variant */
1324: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1325:
1326: a *= (uae_s64)(uae_s32)src;
1327: SET_VFLG (0);
1328: SET_CFLG (0);
1329: SET_ZFLG (a == 0);
1330: SET_NFLG (a < 0);
1331: if (extra & 0x400)
1332: m68k_dreg(regs, extra & 7) = a >> 32;
1333: else if ((a & UVAL64(0xffffffff80000000)) != 0
1334: && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1335: {
1336: SET_VFLG (1);
1337: }
1338: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1339: } else {
1340: /* unsigned */
1341: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1342:
1343: a *= (uae_u64)src;
1344: SET_VFLG (0);
1345: SET_CFLG (0);
1346: SET_ZFLG (a == 0);
1347: SET_NFLG (((uae_s64)a) < 0);
1348: if (extra & 0x400)
1349: m68k_dreg(regs, extra & 7) = a >> 32;
1350: else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1351: SET_VFLG (1);
1352: }
1353: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1354: }
1355: #else
1356: if (extra & 0x800) {
1357: /* signed variant */
1358: uae_s32 src1,src2;
1359: uae_u32 dst_lo,dst_hi;
1360: uae_u32 sign;
1361:
1362: src1 = (uae_s32)src;
1363: src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1364: sign = (src1 ^ src2);
1365: if (src1 < 0) src1 = -src1;
1366: if (src2 < 0) src2 = -src2;
1367: mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1368: if (sign & 0x80000000) {
1369: dst_hi = ~dst_hi;
1370: dst_lo = -dst_lo;
1371: if (dst_lo == 0) dst_hi++;
1372: }
1373: SET_VFLG (0);
1374: SET_CFLG (0);
1375: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1376: SET_NFLG (((uae_s32)dst_hi) < 0);
1377: if (extra & 0x400)
1378: m68k_dreg(regs, extra & 7) = dst_hi;
1379: else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1380: && ((dst_hi & 0xffffffff) != 0xffffffff
1381: || (dst_lo & 0x80000000) != 0x80000000))
1382: {
1383: SET_VFLG (1);
1384: }
1385: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1386: } else {
1387: /* unsigned */
1388: uae_u32 dst_lo,dst_hi;
1389:
1390: mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1391:
1392: SET_VFLG (0);
1393: SET_CFLG (0);
1394: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1395: SET_NFLG (((uae_s32)dst_hi) < 0);
1396: if (extra & 0x400)
1397: m68k_dreg(regs, extra & 7) = dst_hi;
1398: else if (dst_hi != 0) {
1399: SET_VFLG (1);
1400: }
1401: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1402: }
1403: #endif
1404: }
1.1.1.6 root 1405:
1.1 root 1406:
1407: void m68k_reset (void)
1408: {
1409: regs.s = 1;
1410: regs.m = 0;
1411: regs.stopped = 0;
1412: regs.t1 = 0;
1413: regs.t0 = 0;
1414: SET_ZFLG (0);
1415: SET_XFLG (0);
1416: SET_CFLG (0);
1417: SET_VFLG (0);
1418: SET_NFLG (0);
1.1.1.7 root 1419: regs.spcflags &= SPCFLAG_MODE_CHANGE; /* Clear specialflags except mode-change */
1.1 root 1420: regs.intmask = 7;
1421: regs.vbr = regs.sfc = regs.dfc = 0;
1422: regs.fpcr = regs.fpsr = regs.fpiar = 0;
1.1.1.7 root 1423:
1424: m68k_areg(regs, 7) = get_long(0);
1425: m68k_setpc(get_long(4));
1426: refill_prefetch (m68k_getpc(), 0);
1.1 root 1427: }
1428:
1.1.1.8 root 1429:
1.1 root 1430: unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1431: {
1.1.1.8 root 1432: #if 0
1.1 root 1433: uaecptr pc = m68k_getpc ();
1.1.1.8 root 1434: #endif
1.1.1.6 root 1435: if ((opcode & 0xF000) == 0xF000) {
1.1.1.13 root 1436: Exception(0xB,0,M68000_EXCEPTION_SRC_CPU);
1.1 root 1437: return 4;
1.1.1.6 root 1438: }
1439: if ((opcode & 0xF000) == 0xA000) {
1.1.1.13 root 1440: Exception(0xA,0,M68000_EXCEPTION_SRC_CPU);
1.1 root 1441: return 4;
1.1.1.6 root 1442: }
1.1.1.3 root 1443: #if 0
1.1.1.6 root 1444: write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc);
1.1 root 1445: #endif
1.1.1.13 root 1446: Exception (4,0,M68000_EXCEPTION_SRC_CPU);
1.1 root 1447: return 4;
1448: }
1449:
1.1.1.8 root 1450:
1.1 root 1451: void mmu_op(uae_u32 opcode, uae_u16 extra)
1452: {
1453: if ((opcode & 0xFE0) == 0x0500) {
1454: /* PFLUSH */
1455: mmusr = 0;
1456: write_log ("PFLUSH\n");
1457: } else if ((opcode & 0x0FD8) == 0x548) {
1458: /* PTEST */
1459: write_log ("PTEST\n");
1460: } else
1461: op_illg (opcode);
1462: }
1463:
1464:
1465: static uaecptr last_trace_ad = 0;
1466:
1467: static void do_trace (void)
1468: {
1.1.1.12 root 1469: if (regs.t0 && currprefs.cpu_level >= 2) {
1.1 root 1470: uae_u16 opcode;
1471: /* should also include TRAP, CHK, SR modification FPcc */
1472: /* probably never used so why bother */
1473: /* We can afford this to be inefficient... */
1474: m68k_setpc (m68k_getpc ());
1475: fill_prefetch_0 ();
1476: opcode = get_word (regs.pc);
1477: if (opcode == 0x4e72 /* RTE */
1478: || opcode == 0x4e74 /* RTD */
1479: || opcode == 0x4e75 /* RTS */
1480: || opcode == 0x4e77 /* RTR */
1481: || opcode == 0x4e76 /* TRAPV */
1482: || (opcode & 0xffc0) == 0x4e80 /* JSR */
1483: || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1484: || (opcode & 0xff00) == 0x6100 /* BSR */
1485: || ((opcode & 0xf000) == 0x6000 /* Bcc */
1486: && cctrue((opcode >> 8) & 0xf))
1487: || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1488: && !cctrue((opcode >> 8) & 0xf)
1489: && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1490: {
1491: last_trace_ad = m68k_getpc ();
1492: unset_special (SPCFLAG_TRACE);
1493: set_special (SPCFLAG_DOTRACE);
1494: }
1495: } else if (regs.t1) {
1496: last_trace_ad = m68k_getpc ();
1497: unset_special (SPCFLAG_TRACE);
1498: set_special (SPCFLAG_DOTRACE);
1499: }
1500: }
1501:
1502:
1.1.1.8 root 1503: /*
1504: * Handle special flags
1505: */
1.1.1.14 root 1506:
1507: static bool do_specialties_interrupt (int Pending)
1508: {
1509: /* Check for MFP ints first (level 6) */
1510: if (regs.spcflags & SPCFLAG_MFP) {
1.1.1.15! root 1511: if (MFP_CheckPendingInterrupts() == true)
! 1512: return true; /* MFP exception was generated, no higher interrupt can happen */
1.1.1.14 root 1513: }
1514:
1515: /* No MFP int, check for VBL/HBL ints (levels 4/2) */
1516: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1517: int intr = intlev ();
1518: /* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */
1519: // unset_special (SPCFLAG_DOINT);
1520: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1521: if (intr != -1 && intr > regs.intmask) {
1522: Interrupt (intr , Pending); /* process the interrupt and add pending jitter if necessary */
1.1.1.15! root 1523: return true;
1.1.1.14 root 1524: }
1525: }
1526:
1.1.1.15! root 1527: return false; /* no interrupt was found */
1.1.1.14 root 1528: }
1529:
1530:
1.1 root 1531: static int do_specialties (void)
1532: {
1.1.1.7 root 1533: if(regs.spcflags & SPCFLAG_BUSERROR) {
1534: /* We can not execute bus errors directly in the memory handler
1535: * functions since the PC should point to the address of the next
1536: * instruction, so we're executing the bus errors here: */
1.1.1.8 root 1537: unset_special(SPCFLAG_BUSERROR);
1.1.1.13 root 1538: Exception(2,0,M68000_EXCEPTION_SRC_CPU);
1.1.1.7 root 1539: }
1540:
1.1.1.8 root 1541: if(regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1542: /* Add some extra cycles to simulate a wait state */
1543: unset_special(SPCFLAG_EXTRA_CYCLES);
1.1.1.11 root 1544: M68000_AddCycles(nWaitStateCycles);
1.1.1.12 root 1545: nWaitStateCycles = 0;
1.1.1.8 root 1546: }
1547:
1.1 root 1548: if (regs.spcflags & SPCFLAG_DOTRACE) {
1.1.1.13 root 1549: Exception (9,last_trace_ad,M68000_EXCEPTION_SRC_CPU);
1.1 root 1550: }
1.1.1.8 root 1551:
1.1.1.14 root 1552:
1553: /* Handle the STOP instruction */
1554: if ( regs.spcflags & SPCFLAG_STOP ) {
1555: /* We first test if there's a pending interrupt that would */
1556: /* allow to immediatly leave the STOP state */
1.1.1.15! root 1557: if ( do_specialties_interrupt(true) ) { /* test if there's an interrupt and add pending jitter */
1.1.1.14 root 1558: regs.stopped = 0;
1559: unset_special (SPCFLAG_STOP);
1560: }
1561: #if 0
1562: if (regs.spcflags & SPCFLAG_MFP) /* MFP int */
1563: MFP_CheckPendingInterrupts();
1564:
1565: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) { /* VBL/HBL ints */
1566: int intr = intlev ();
1567: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1568: if (intr != -1 && intr > regs.intmask) {
1.1.1.15! root 1569: Interrupt (intr , true); /* process the interrupt and add pending jitter */
1.1.1.14 root 1570: regs.stopped = 0;
1571: unset_special (SPCFLAG_STOP);
1572: }
1573: }
1574: #endif
1575:
1576: /* No pending int, we have to wait for the next matching int */
1577: while (regs.spcflags & SPCFLAG_STOP) {
1578:
1579: /* Take care of quit event if needed */
1580: if (regs.spcflags & SPCFLAG_BRK)
1581: return 1;
1582:
1583: M68000_AddCycles(4);
1584:
1585: /* It is possible one or more ints happen at the same time */
1586: /* We must process them during the same cpu cycle until the special INT flag is set */
1587: while (PendingInterruptCount<=0 && PendingInterruptFunction) {
1588: /* 1st, we call the interrupt handler */
1589: CALL_VAR(PendingInterruptFunction);
1590:
1591: /* Then we check if this handler triggered an interrupt to process */
1.1.1.15! root 1592: if ( do_specialties_interrupt(false) ) { /* test if there's an interrupt and add non pending jitter */
1.1.1.13 root 1593: regs.stopped = 0;
1594: unset_special (SPCFLAG_STOP);
1.1.1.14 root 1595: break;
1596: }
1597: #if 0
1598: /* Then we check if this handler triggered an MFP int to process */
1599: if (regs.spcflags & SPCFLAG_MFP)
1600: MFP_CheckPendingInterrupts();
1601:
1602: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1603: int intr = intlev ();
1604: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1605: if (intr != -1 && intr > regs.intmask) {
1.1.1.15! root 1606: Interrupt (intr , false); /* process the interrupt and add non pending jitter */
1.1.1.14 root 1607: regs.stopped = 0;
1608: unset_special (SPCFLAG_STOP);
1609: break;
1610: }
1611: }
1612: #endif
1.1.1.6 root 1613: }
1.1 root 1614: }
1615: }
1.1.1.8 root 1616:
1.1.1.14 root 1617:
1.1 root 1618: if (regs.spcflags & SPCFLAG_TRACE)
1619: do_trace ();
1620:
1.1.1.12 root 1621: // if (regs.spcflags & SPCFLAG_DOINT) {
1622: /* [NP] pending int should be processed now, not after the current instr */
1.1.1.14 root 1623: /* so we check for (SPCFLAG_INT | SPCFLAG_DOINT), not just for SPCFLAG_DOINT */
1.1.1.15! root 1624:
! 1625: if ( do_specialties_interrupt(false) ) { /* test if there's an interrupt and add non pending jitter */
1.1.1.14 root 1626: regs.stopped = 0; /* [NP] useless ? */
1627: }
1628: if (regs.spcflags & SPCFLAG_INT) {
1629: unset_special (SPCFLAG_INT);
1630: set_special (SPCFLAG_DOINT);
1631: }
1632: #if 0
1.1.1.12 root 1633: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1.1.1.6 root 1634: int intr = intlev ();
1.1.1.8 root 1635: /* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */
1.1.1.12 root 1636: // unset_special (SPCFLAG_DOINT);
1637: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1.1.1.6 root 1638: if (intr != -1 && intr > regs.intmask) {
1.1.1.15! root 1639: Interrupt (intr , false); /* call Interrupt() with Pending=false, not necessarily true but harmless */
1.1.1.14 root 1640: regs.stopped = 0; /* [NP] useless ? */
1.1.1.6 root 1641: }
1.1 root 1642: }
1643: if (regs.spcflags & SPCFLAG_INT) {
1644: unset_special (SPCFLAG_INT);
1645: set_special (SPCFLAG_DOINT);
1646: }
1.1.1.8 root 1647:
1648: if (regs.spcflags & SPCFLAG_MFP) { /* Check for MFP interrupts */
1649: MFP_CheckPendingInterrupts();
1650: }
1.1.1.14 root 1651: #endif
1.1.1.8 root 1652:
1.1.1.15! root 1653: if (regs.spcflags & SPCFLAG_DEBUGGER)
! 1654: DebugUI_CpuCheck();
! 1655:
1.1 root 1656: if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1.1.1.8 root 1657: unset_special(SPCFLAG_MODE_CHANGE);
1.1 root 1658: return 1;
1659: }
1.1.1.8 root 1660:
1.1 root 1661: return 0;
1662: }
1663:
1.1.1.3 root 1664:
1.1 root 1665: /* It's really sad to have two almost identical functions for this, but we
1666: do it all for performance... :( */
1667: static void m68k_run_1 (void)
1668: {
1669: #ifdef DEBUG_PREFETCH
1670: uae_u8 saved_bytes[20];
1671: uae_u16 *oldpcp;
1672: #endif
1.1.1.8 root 1673:
1674: for (;;) {
1.1 root 1675: int cycles;
1676: uae_u32 opcode = get_iword_prefetch (0);
1.1.1.8 root 1677:
1.1 root 1678: #ifdef DEBUG_PREFETCH
1679: if (get_ilong (0) != do_get_mem_long (®s.prefetch)) {
1680: fprintf (stderr, "Prefetch differs from memory.\n");
1681: debugging = 1;
1682: return;
1683: }
1684: oldpcp = regs.pc_p;
1685: memcpy (saved_bytes, regs.pc_p, 20);
1686: #endif
1687:
1688: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.15! root 1689: if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
! 1690: {
! 1691: int FrameCycles, HblCounterVideo, LineCycles;
! 1692:
! 1693: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
! 1694:
! 1695: LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
1.1.1.12 root 1696: m68k_disasm(stderr, m68k_getpc (), NULL, 1);
1.1.1.15! root 1697: }
1.1 root 1698:
1699: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1700: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1701: #if COUNT_INSTRS == 2
1702: if (table68k[opcode].handler != -1)
1703: instrcount[table68k[opcode].handler]++;
1704: #elif COUNT_INSTRS == 1
1705: instrcount[opcode]++;
1706: #endif
1.1.1.2 root 1707:
1.1.1.12 root 1708: /* In case of a Bus Error, we need the PC of the instruction that caused */
1709: /* the error to build the exception stack frame */
1710: BusErrorPC = m68k_getpc();
1711:
1.1.1.6 root 1712: cycles = (*cpufunctbl[opcode])(opcode);
1713:
1.1 root 1714: #ifdef DEBUG_PREFETCH
1715: if (memcmp (saved_bytes, oldpcp, 20) != 0) {
1.1.1.12 root 1716: fprintf (stderr, "Self-modifying code detected %x.\n" , m68k_getpc() );
1.1 root 1717: set_special (SPCFLAG_BRK);
1718: debugging = 1;
1719: }
1720: #endif
1.1.1.2 root 1721:
1.1.1.12 root 1722: M68000_AddCyclesWithPairing(cycles);
1.1.1.13 root 1723: if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1724: /* Add some extra cycles to simulate a wait state */
1725: unset_special(SPCFLAG_EXTRA_CYCLES);
1726: M68000_AddCycles(nWaitStateCycles);
1727: nWaitStateCycles = 0;
1728: }
1729:
1.1.1.14 root 1730: #if 0
1731: while (PendingInterruptCount <= 0 && PendingInterruptFunction)
1.1.1.8 root 1732: CALL_VAR(PendingInterruptFunction);
1.1.1.14 root 1733: #else
1734: /* We can have several interrupts at the same time before the next CPU instruction */
1735: /* We must check for pending interrupt and call do_specialties_interrupt() only */
1736: /* if the cpu is not in the STOP state. Else, the int could be acknowledged now */
1737: /* and prevent exiting the STOP state when calling do_specialties() after. */
1738: /* For performance, we first test PendingInterruptCount, then regs.spcflags */
1739: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) && ( ( regs.spcflags & SPCFLAG_STOP ) == 0 ) )
1740: {
1741: CALL_VAR(PendingInterruptFunction); /* call the interrupt handler */
1.1.1.15! root 1742: do_specialties_interrupt(false); /* test if there's an mfp/video interrupt and add non pending jitter */
1.1.1.14 root 1743: #if 0
1744: if ( regs.spcflags & ( SPCFLAG_MFP | SPCFLAG_INT ) ) { /* only check mfp/video interrupts */
1745: if (do_specialties ()) /* check if this latest int has higher priority */
1746: return;
1747: }
1748: #endif
1749: }
1.1.1.15! root 1750: #endif
1.1.1.14 root 1751:
1752: if (regs.spcflags) {
1753: if (do_specialties ())
1754: return;
1755: }
1756:
1.1.1.15! root 1757: /* Run DSP 56k code if necessary */
! 1758: if (bDspEnabled) {
! 1759: DSP_Run(cycles);
! 1760: }
1.1 root 1761: }
1762: }
1763:
1764:
1765: /* Same thing, but don't use prefetch to get opcode. */
1766: static void m68k_run_2 (void)
1767: {
1.1.1.8 root 1768: for (;;) {
1.1 root 1769: int cycles;
1770: uae_u32 opcode = get_iword (0);
1771:
1772: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.15! root 1773: if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
! 1774: {
! 1775: int FrameCycles, HblCounterVideo, LineCycles;
! 1776:
! 1777: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
! 1778:
! 1779: LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
1.1.1.12 root 1780: m68k_disasm(stderr, m68k_getpc (), NULL, 1);
1.1.1.15! root 1781: }
1.1.1.12 root 1782:
1.1 root 1783: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1784: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1785: #if COUNT_INSTRS == 2
1786: if (table68k[opcode].handler != -1)
1787: instrcount[table68k[opcode].handler]++;
1788: #elif COUNT_INSTRS == 1
1789: instrcount[opcode]++;
1790: #endif
1.1.1.2 root 1791:
1.1.1.6 root 1792: cycles = (*cpufunctbl[opcode])(opcode);
1793:
1.1.1.8 root 1794: M68000_AddCycles(cycles);
1.1.1.13 root 1795: if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1796: /* Add some extra cycles to simulate a wait state */
1797: unset_special(SPCFLAG_EXTRA_CYCLES);
1798: M68000_AddCycles(nWaitStateCycles);
1799: nWaitStateCycles = 0;
1800: }
1801:
1.1.1.12 root 1802: while (PendingInterruptCount <= 0 && PendingInterruptFunction)
1.1.1.8 root 1803: CALL_VAR(PendingInterruptFunction);
1804:
1.1 root 1805: if (regs.spcflags) {
1806: if (do_specialties ())
1807: return;
1808: }
1.1.1.15! root 1809:
! 1810: /* Run DSP 56k code if necessary */
! 1811: if (bDspEnabled) {
! 1812: DSP_Run(cycles);
! 1813: }
1.1 root 1814: }
1815: }
1816:
1817:
1818: void m68k_go (int may_quit)
1819: {
1.1.1.8 root 1820: static int in_m68k_go = 0;
1821:
1.1 root 1822: if (in_m68k_go || !may_quit) {
1823: write_log ("Bug! m68k_go is not reentrant.\n");
1824: abort ();
1825: }
1826:
1827: in_m68k_go++;
1.1.1.8 root 1828: while (!(regs.spcflags & SPCFLAG_BRK)) {
1.1.1.12 root 1829: if(currprefs.cpu_compatible)
1.1.1.2 root 1830: m68k_run_1();
1831: else
1832: m68k_run_2();
1.1 root 1833: }
1.1.1.8 root 1834: unset_special(SPCFLAG_BRK);
1.1 root 1835: in_m68k_go--;
1836: }
1837:
1.1.1.8 root 1838:
1839: /*
1.1 root 1840: static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1841: {
1842: uae_u32 opcode, val;
1843: struct instr *dp;
1844:
1845: opcode = get_iword_1(0);
1846: last_op_for_exception_3 = opcode;
1847: m68kpc_offset = 2;
1848:
1.1.1.6 root 1849: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1850: opcode = 0x4AFC;
1851: }
1852: dp = table68k + opcode;
1853:
1854: if (dp->suse) {
1855: if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) {
1.1.1.13 root 1856: Exception (3, 0,M68000_EXCEPTION_SRC_CPU);
1.1 root 1857: return;
1858: }
1859: }
1860: if (dp->duse) {
1861: if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) {
1.1.1.13 root 1862: Exception (3, 0,M68000_EXCEPTION_SRC_CPU);
1.1 root 1863: return;
1864: }
1865: }
1866: }
1.1.1.8 root 1867: */
1868:
1.1 root 1869:
1870: void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1871: {
1.1.1.11 root 1872: static const char * const ccnames[] =
1.1.1.8 root 1873: { "T ","F ","HI","LS","CC","CS","NE","EQ",
1874: "VC","VS","PL","MI","GE","LT","GT","LE" };
1875:
1.1 root 1876: uaecptr newpc = 0;
1877: m68kpc_offset = addr - m68k_getpc ();
1878: while (cnt-- > 0) {
1879: char instrname[20],*ccpt;
1880: int opwords;
1881: uae_u32 opcode;
1.1.1.11 root 1882: const struct mnemolookup *lookup;
1.1 root 1883: struct instr *dp;
1884: fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset);
1885: for (opwords = 0; opwords < 5; opwords++){
1886: fprintf (f, "%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1887: }
1888: opcode = get_iword_1 (m68kpc_offset);
1889: m68kpc_offset += 2;
1.1.1.6 root 1890: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1891: opcode = 0x4AFC;
1892: }
1893: dp = table68k + opcode;
1894: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1895: ;
1896:
1897: strcpy (instrname, lookup->name);
1898: ccpt = strstr (instrname, "cc");
1899: if (ccpt != 0) {
1900: strncpy (ccpt, ccnames[dp->cc], 2);
1901: }
1902: fprintf (f, "%s", instrname);
1903: switch (dp->size){
1904: case sz_byte: fprintf (f, ".B "); break;
1905: case sz_word: fprintf (f, ".W "); break;
1906: case sz_long: fprintf (f, ".L "); break;
1907: default: fprintf (f, " "); break;
1908: }
1909:
1910: if (dp->suse) {
1911: newpc = m68k_getpc () + m68kpc_offset;
1912: newpc += ShowEA (f, dp->sreg, dp->smode, dp->size, 0);
1913: }
1914: if (dp->suse && dp->duse)
1915: fprintf (f, ",");
1916: if (dp->duse) {
1917: newpc = m68k_getpc () + m68kpc_offset;
1918: newpc += ShowEA (f, dp->dreg, dp->dmode, dp->size, 0);
1919: }
1920: if (ccpt != 0) {
1921: if (cctrue(dp->cc))
1.1.1.5 root 1922: fprintf (f, " == %08lx (TRUE)", (long)newpc);
1.1 root 1923: else
1.1.1.5 root 1924: fprintf (f, " == %08lx (FALSE)", (long)newpc);
1.1 root 1925: } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1.1.1.5 root 1926: fprintf (f, " == %08lx", (long)newpc);
1.1 root 1927: fprintf (f, "\n");
1928: }
1929: if (nextpc)
1930: *nextpc = m68k_getpc () + m68kpc_offset;
1931: }
1932:
1933: void m68k_dumpstate (FILE *f, uaecptr *nextpc)
1934: {
1935: int i;
1936: for (i = 0; i < 8; i++){
1.1.1.5 root 1937: fprintf (f, "D%d: %08lx ", i, (long)m68k_dreg(regs, i));
1.1 root 1938: if ((i & 3) == 3) fprintf (f, "\n");
1939: }
1940: for (i = 0; i < 8; i++){
1.1.1.5 root 1941: fprintf (f, "A%d: %08lx ", i, (long)m68k_areg(regs, i));
1.1 root 1942: if ((i & 3) == 3) fprintf (f, "\n");
1943: }
1944: if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1945: if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1946: if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1947: fprintf (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1.1.1.5 root 1948: (long)regs.usp,(long)regs.isp,(long)regs.msp,(long)regs.vbr);
1.1 root 1949: fprintf (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1950: regs.t1, regs.t0, regs.s, regs.m,
1951: GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1952: for (i = 0; i < 8; i++){
1953: fprintf (f, "FP%d: %g ", i, regs.fp[i]);
1954: if ((i & 3) == 3) fprintf (f, "\n");
1955: }
1956: fprintf (f, "N=%d Z=%d I=%d NAN=%d\n",
1957: (regs.fpsr & 0x8000000) != 0,
1958: (regs.fpsr & 0x4000000) != 0,
1959: (regs.fpsr & 0x2000000) != 0,
1960: (regs.fpsr & 0x1000000) != 0);
1.1.1.12 root 1961: if (currprefs.cpu_compatible)
1.1 root 1962: fprintf (f, "prefetch %08lx\n", (unsigned long)do_get_mem_long(®s.prefetch));
1963:
1964: m68k_disasm (f, m68k_getpc (), nextpc, 1);
1965: if (nextpc)
1.1.1.5 root 1966: fprintf (f, "next PC: %08lx\n", (long)*nextpc);
1.1 root 1967: }
1.1.1.12 root 1968:
1969:
1970: /*
1971:
1972: The routines below take dividend and divisor as parameters.
1973: They return 0 if division by zero, or exact number of cycles otherwise.
1974:
1975: The number of cycles returned assumes a register operand.
1976: Effective address time must be added if memory operand.
1977:
1978: For 68000 only (not 68010, 68012, 68020, etc).
1979: Probably valid for 68008 after adding the extra prefetch cycle.
1980:
1981:
1982: Best and worst cases are for register operand:
1983: (Note the difference with the documented range.)
1984:
1985:
1986: DIVU:
1987:
1988: Overflow (always): 10 cycles.
1989: Worst case: 136 cycles.
1990: Best case: 76 cycles.
1991:
1992:
1993: DIVS:
1994:
1995: Absolute overflow: 16-18 cycles.
1996: Signed overflow is not detected prematurely.
1997:
1998: Worst case: 156 cycles.
1999: Best case without signed overflow: 122 cycles.
2000: Best case with signed overflow: 120 cycles
2001:
2002:
2003: */
2004:
2005:
2006: //
2007: // DIVU
2008: // Unsigned division
2009: //
2010:
2011: STATIC_INLINE int getDivu68kCycles_2 (uae_u32 dividend, uae_u16 divisor)
2012: {
2013: int mcycles;
2014: uae_u32 hdivisor;
2015: int i;
2016:
2017: if (divisor == 0)
2018: return 0;
2019:
2020: // Overflow
2021: if ((dividend >> 16) >= divisor)
2022: return (mcycles = 5) * 2;
2023:
2024: mcycles = 38;
2025: hdivisor = divisor << 16;
2026:
2027: for (i = 0; i < 15; i++) {
2028: uae_u32 temp;
2029: temp = dividend;
2030:
2031: dividend <<= 1;
2032:
2033: // If carry from shift
2034: if ((uae_s32)temp < 0)
2035: dividend -= hdivisor;
2036: else {
2037: mcycles += 2;
2038: if (dividend >= hdivisor) {
2039: dividend -= hdivisor;
2040: mcycles--;
2041: }
2042: }
2043: }
2044: return mcycles * 2;
2045: }
2046: int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor)
2047: {
2048: int v = getDivu68kCycles_2 (dividend, divisor) - 4;
2049: // write_log ("U%d ", v);
2050: return v;
2051: }
2052:
2053: //
2054: // DIVS
2055: // Signed division
2056: //
2057:
2058: STATIC_INLINE int getDivs68kCycles_2 (uae_s32 dividend, uae_s16 divisor)
2059: {
2060: int mcycles;
2061: uae_u32 aquot;
2062: int i;
2063:
2064: if (divisor == 0)
2065: return 0;
2066:
2067: mcycles = 6;
2068:
2069: if (dividend < 0)
2070: mcycles++;
2071:
2072: // Check for absolute overflow
2073: if (((uae_u32)abs (dividend) >> 16) >= (uae_u16)abs (divisor))
2074: return (mcycles + 2) * 2;
2075:
2076: // Absolute quotient
2077: aquot = (uae_u32) abs (dividend) / (uae_u16)abs (divisor);
2078:
2079: mcycles += 55;
2080:
2081: if (divisor >= 0) {
2082: if (dividend >= 0)
2083: mcycles--;
2084: else
2085: mcycles++;
2086: }
2087:
2088: // Count 15 msbits in absolute of quotient
2089:
2090: for (i = 0; i < 15; i++) {
2091: if ((uae_s16)aquot >= 0)
2092: mcycles++;
2093: aquot <<= 1;
2094: }
2095:
2096: return mcycles * 2;
2097: }
2098: int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor)
2099: {
2100: int v = getDivs68kCycles_2 (dividend, divisor) - 4;
2101: // write_log ("S%d ", v);
2102: return v;
2103: }
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