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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation
5: *
6: * (c) 1995 Bernd Schmidt
1.1.1.2 root 7: *
8: * Adaptation to Hatari by Thomas Huth
9: *
1.1.1.6 root 10: * This file is distributed under the GNU Public License, version 2 or at
11: * your option any later version. Read the file gpl.txt for details.
1.1 root 12: */
1.1.1.12 root 13:
14:
15: /* 2007/11/12 [NP] Add HATARI_TRACE_CPU_DISASM. */
16: /* 2007/11/15 [NP] In MakeFromSR, writes to m and t0 should be ignored and set to 0 if cpu < 68020 */
17: /* 2007/11/26 [NP] We set BusErrorPC in m68k_run_1 instead of M68000_BusError, else the BusErrorPC */
18: /* will not point to the opcode that generated the bus error. */
19: /* Huge debug/work on Exceptions 2/3 stack frames, result is more accurate and */
20: /* allow to pass the very tricky Transbeauce 2 Demo's protection. */
21: /* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */
22: /* Cwik, [email protected]). */
23: /* 2007/12/06 [NP] The PC stored in the stack frame for the bus error is complex to emulate, */
24: /* because it doesn't necessarily point to the next instruction after the one that */
25: /* triggered the bus error. In the case of the Transbeauce 2 Demo, after */
26: /* 'move.l $0.w,$24.w', PC is incremented of 4 bytes, not 6, and stored in the */
27: /* stack. Special case to decrement PC of 2 bytes if opcode is '21f8'. */
28: /* This should be fixed with a real model. */
29: /* 2007/12/07 [NP] If Trace is enabled and a group 2 exception occurs (such as CHK), the trace */
30: /* handler should be called after the group 2's handler. If a bus error, address */
31: /* error or illegal occurs while Trace is enabled, the trace handler should not be */
32: /* called after this instruction (Transbeauce 2 Demo, Phaleon Demo). */
33: /* This means that if a CHK is executed while trace bit was set, we must set PC */
34: /* to CHK handler, turn trace off in the internal SR, but we must still call the */
35: /* trace handler one last time with the PC set to the CHK's handler (even if */
36: /* trace mode is internally turned off while processing an exception). Once trace */
37: /* handler is finished (RTE), we return to the CHK's handler. */
38: /* This is true for DIV BY 0, CHK, TRAPV and TRAP. */
39: /* Backport exception_trace() from WinUAE to handle this behaviour (used in */
40: /* Transbeauce 2 demo). */
41: /* 2007/12/09 [NP] 'dc.w $a' should not be used to call 'OpCode_SysInit' but should give an illegal*/
42: /* instruction (Transbeauce 2 demo). */
43: /* Instead of always replacing the illegal instructions $8, $a and $c by the */
44: /* 3 functions required for HD emulation, we now do it in cart.c only if the */
45: /* built-in cartridge image is loaded. */
46: /* YEAH! Hatari is now the first emulator to pass the Transbeauce 2 protection :) */
47: /* 2007/12/18 [NP] More precise timings for HBL, VBL and MFP interrupts. On ST, these interrupts */
48: /* are taking 56 cycles instead of the 44 cycles in the 68000's documentation. */
49: /* 2007/12/24 [NP] If an interrupt (HBL, VBL) is pending after intruction 'n' was processed, the */
50: /* exception should be called before instr. 'n+1' is processed, not after (else the*/
51: /* interrupt's handler is delayed by one 68000's instruction, which could break */
52: /* some demos with too strict timings) (ACF's Demo Main Menu). */
53: /* We call the interrupt if ( SPCFLAG_INT | SPCFLAG_DOINT ) is set, not only if */
54: /* SPCFLAG_DOINT is set (as it was already the case when handling 'STOP'). */
55: /* 2007/12/25 [NP] FIXME When handling exceptions' cycles, using nr >= 64 to determine if this is */
56: /* an MFP exception could be wrong if the MFP VR was set to another value than the */
57: /* default $40 (this could be a problem with programs requiring a precise cycles */
58: /* calculation while changing VR, but no such programs were encountered so far). */
1.1.1.13 root 59: /* -> FIXED, see 2008/10/05 */
60: /* 2008/04/17 [NP] In m68k_run_1/m68k_run_2, add the wait state cycles before testing if content */
61: /* of PendingInterruptCount is <= 0 (else the int could happen a few cycles earlier*/
62: /* than expected in some rare cases (reading $fffa21 in BIG Demo Screen 1)). */
63: /* 2008/09/14 [NP] Add the value of the new PC in the exception's log. */
64: /* 2008/09/14 [NP] Correct cycles for TRAP are 34 not 38 (4 more cycles were counted because cpuemu*/
65: /* returns 4 and Exception() adds 34) (Phaleon / Illusion Demo by Next). */
66: /* FIXME : Others exception cycles may be wrong too. */
67: /* 2008/10/05 [NP] Add a parameter 'ExceptionSource' to Exception(). This allows to know the source*/
68: /* of the exception (video, mfp, cpu) and properly handle MFP interrupts. Since */
69: /* it's possible to change the vector base in $fffa17, MFP int vectors can overlap */
70: /* the 'normal' 68000 ones and the exception number is not enough to decide. */
71: /* We need ExceptionSource to remove the ambiguity. */
72: /* Fix High Fidelity Dreams by Aura which sets MFP vector base to $c0 instead of */
73: /* $100. In that case, timer B int becomes exception nr 56 and conflicts with the */
74: /* 'MMU config error' exception, which takes 4 cycles instead of 56 cycles for MFP.*/
75: /* 2008/11/18 [NP] In 'do_specialties()', when the cpu is in the STOP state, we must test all */
76: /* possible int handlers while PendingInterruptCount <= 0 without increasing the */
77: /* cpu cycle counter. In the case where both an MFP int and an HBL occur at the */
1.1.1.14 root 78: /* same time for example, the HBL was delayed by 4 cycles if no MFP exception */
1.1.1.13 root 79: /* was triggered, which was wrong (this happened mainly with the TOS timer D that */
80: /* expires very often). Such precision is required for very recent hardscroll */
81: /* techniques that use 'stop' to stay in sync with the video shifter. */
1.1.1.14 root 82: /* 2008/11/23 [NP] In 'do_specialties()', when in STOP state, we must first test for a pending */
83: /* interrupt that would exit the STOP state immediatly, without doing a 'while' */
84: /* loop until 'SPCFLAG_INT' or 'SPCFLAG_DOINT' are set. */
85: /* 2008/11/29 [NP] Call 'InterruptAddJitter()' when a video interrupt happens to precisely emulate */
86: /* the jitter happening on the Atari (see video.c for the jitter patterns). */
87: /* FIXME : Pattern is not always correct when handling pending interrupt in STOP */
88: /* state, but this should be harmless as no program has been found using this. */
89: /* 2008/12/05 [NP] On Atari it takes 56 cycles to process an interrupt. During that time, a higher */
90: /* level interrupt could happen and we must execute it before the previous int */
91: /* (see m68k_run_1()). */
92: /* This is the case for the VBL which can interrupt the last HBL of a screen */
93: /* (end of line 312) at various point (from 0 to 8 cycles). */
94: /* This fixes the fullscreen tunnel in Suretrip 49% by Checkpoint, which uses a */
95: /* really buggy vbl/hbl combination, even on a real ST. Also fixes sample sound */
96: /* in Swedish New Year's TCB screen. */
97: /* 2008/12/11 [NP] Extract interrupt handling from do_specialties() in do_specialties_interrupt() */
98: /* and factorize some code. In m68k_run_1 when testing for multiple interrupts at */
99: /* the same time, call do_specialties_interrupt() to check only the special flags */
100: /* related to interrupts (MFP and video) (else, this caused problem when the TRACE */
101: /* flag was set). */
102: /* 2008/12/14 [NP] In m68k_run_1(), we should check for simultaneous ints only if the cpu is not */
103: /* in the STOP state after the last instruction was executed. Else, the call to */
104: /* do_specialties_interrupt() could acknowledge the interrupt and we would never */
105: /* exit the STOP state in do_specialties() just after (the problem can happen if */
106: /* the TOS timer D expires just at the same time as the STOP instruction). */
107: /* Fix regression since 2008/12/11 in the hidden screen from ULM in Oh Crickey... */
108: /* 2008/12/20 [NP] In m68k_run_1(), when checking interrupts and STOP mode, we should test */
109: /* PendingInterruptCount before regs.spcflags to have a faster evaluation of the */
110: /* 'while' condition (PendingInterruptCount <= 0 is true less often than STOP==0) */
1.1.1.12 root 111:
112:
1.1.1.15 root 113: const char NewCpu_fileid[] = "Hatari newcpu.c : " __DATE__ " " __TIME__;
1.1 root 114:
115: #include "sysdeps.h"
116: #include "hatari-glue.h"
117: #include "maccess.h"
118: #include "memory.h"
119: #include "newcpu.h"
1.1.1.16! root 120: #include "main.h"
! 121: #include "m68000.h"
! 122: #include "cycInt.h"
! 123: #include "mfp.h"
! 124: #include "tos.h"
! 125: #include "vdi.h"
! 126: #include "cart.h"
! 127: #include "dialog.h"
! 128: #include "bios.h"
! 129: #include "xbios.h"
! 130: #include "video.h"
! 131: #include "options.h"
! 132: #include "dsp.h"
! 133: #include "log.h"
! 134: #include "debugui.h"
! 135: #include "debugcpu.h"
1.1 root 136:
1.1.1.12 root 137: //#define DEBUG_PREFETCH
1.1 root 138:
139: struct flag_struct regflags;
140:
141: /* Opcode of faulting instruction */
142: uae_u16 last_op_for_exception_3;
143: /* PC at fault time */
144: uaecptr last_addr_for_exception_3;
145: /* Address that generated the exception */
146: uaecptr last_fault_for_exception_3;
147:
1.1.1.11 root 148: const int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
149: const int imm8_table[] = { 8,1,2,3,4,5,6,7 };
1.1 root 150:
151: int movem_index1[256];
152: int movem_index2[256];
153: int movem_next[256];
154:
155: int fpp_movem_index1[256];
156: int fpp_movem_index2[256];
157: int fpp_movem_next[256];
158:
159: cpuop_func *cpufunctbl[65536];
160:
1.1.1.12 root 161: int OpcodeFamily;
1.1.1.16! root 162: int BusCyclePenalty = 0;
1.1.1.6 root 163:
1.1 root 164: #define COUNT_INSTRS 0
165:
166: #if COUNT_INSTRS
167: static unsigned long int instrcount[65536];
168: static uae_u16 opcodenums[65536];
169:
170: static int compfn (const void *el1, const void *el2)
171: {
172: return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
173: }
174:
175: static char *icountfilename (void)
176: {
177: char *name = getenv ("INSNCOUNT");
178: if (name)
179: return name;
180: return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
181: }
182:
183: void dump_counts (void)
184: {
185: FILE *f = fopen (icountfilename (), "w");
186: unsigned long int total;
187: int i;
188:
189: write_log ("Writing instruction count file...\n");
190: for (i = 0; i < 65536; i++) {
191: opcodenums[i] = i;
192: total += instrcount[i];
193: }
194: qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
195:
196: fprintf (f, "Total: %lu\n", total);
197: for (i=0; i < 65536; i++) {
198: unsigned long int cnt = instrcount[opcodenums[i]];
199: struct instr *dp;
200: struct mnemolookup *lookup;
201: if (!cnt)
202: break;
203: dp = table68k + opcodenums[i];
204: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
205: ;
206: fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
207: }
208: fclose (f);
209: }
210: #else
211: void dump_counts (void)
212: {
213: }
214: #endif
215:
216:
217: static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM;
218:
219: static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
220: {
1.1.1.6 root 221: op_illg (opcode);
1.1 root 222: return 4;
223: }
224:
1.1.1.4 root 225:
226: void build_cpufunctbl(void)
1.1 root 227: {
228: int i;
229: unsigned long opcode;
1.1.1.12 root 230: const struct cputbl *tbl = (currprefs.cpu_level == 4 ? op_smalltbl_0_ff
231: : currprefs.cpu_level == 3 ? op_smalltbl_1_ff
232: : currprefs.cpu_level == 2 ? op_smalltbl_2_ff
233: : currprefs.cpu_level == 1 ? op_smalltbl_3_ff
234: : ! currprefs.cpu_compatible ? op_smalltbl_4_ff
1.1.1.11 root 235: : op_smalltbl_5_ff);
1.1 root 236:
1.1.1.10 root 237: Log_Printf(LOG_DEBUG, "Building CPU function table (%d %d %d).\n",
1.1.1.12 root 238: currprefs.cpu_level, currprefs.cpu_compatible, currprefs.address_space_24);
1.1 root 239:
240: for (opcode = 0; opcode < 65536; opcode++)
1.1.1.6 root 241: cpufunctbl[opcode] = op_illg_1;
1.1 root 242: for (i = 0; tbl[i].handler != NULL; i++) {
243: if (! tbl[i].specific)
1.1.1.6 root 244: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 245: }
246: for (opcode = 0; opcode < 65536; opcode++) {
247: cpuop_func *f;
248:
1.1.1.12 root 249: if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > currprefs.cpu_level)
1.1 root 250: continue;
251:
252: if (table68k[opcode].handler != -1) {
1.1.1.6 root 253: f = cpufunctbl[table68k[opcode].handler];
1.1 root 254: if (f == op_illg_1)
255: abort();
1.1.1.6 root 256: cpufunctbl[opcode] = f;
1.1 root 257: }
258: }
259: for (i = 0; tbl[i].handler != NULL; i++) {
260: if (tbl[i].specific)
1.1.1.6 root 261: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 262: }
263: }
264:
265:
266:
267: void init_m68k (void)
268: {
269: int i;
270:
271: for (i = 0 ; i < 256 ; i++) {
272: int j;
273: for (j = 0 ; j < 8 ; j++) {
274: if (i & (1 << j)) break;
275: }
276: movem_index1[i] = j;
277: movem_index2[i] = 7-j;
278: movem_next[i] = i & (~(1 << j));
279: }
280: for (i = 0 ; i < 256 ; i++) {
281: int j;
282: for (j = 7 ; j >= 0 ; j--) {
283: if (i & (1 << j)) break;
284: }
285: fpp_movem_index1[i] = 7-j;
286: fpp_movem_index2[i] = j;
287: fpp_movem_next[i] = i & (~(1 << j));
288: }
289: #if COUNT_INSTRS
290: {
291: FILE *f = fopen (icountfilename (), "r");
292: memset (instrcount, 0, sizeof instrcount);
293: if (f) {
294: uae_u32 opcode, count, total;
295: char name[20];
296: write_log ("Reading instruction count file...\n");
297: fscanf (f, "Total: %lu\n", &total);
298: while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
299: instrcount[opcode] = count;
300: }
301: fclose(f);
302: }
303: }
304: #endif
305: write_log ("Building CPU table for configuration: 68");
1.1.1.12 root 306: if (currprefs.address_space_24 && currprefs.cpu_level > 1)
1.1 root 307: write_log ("EC");
1.1.1.12 root 308: switch (currprefs.cpu_level) {
1.1 root 309: case 1:
310: write_log ("010");
311: break;
312: case 2:
313: write_log ("020");
314: break;
315: case 3:
316: write_log ("020/881");
317: break;
318: case 4:
319: /* Who is going to miss the MMU anyway...? :-) */
320: write_log ("040");
321: break;
322: default:
323: write_log ("000");
324: break;
325: }
1.1.1.12 root 326: if (currprefs.cpu_compatible)
1.1 root 327: write_log (" (compatible mode)");
328: write_log ("\n");
1.1.1.7 root 329:
1.1 root 330: read_table68k ();
331: do_merges ();
332:
1.1.1.10 root 333: Log_Printf(LOG_DEBUG, "%d CPU functions\n", nr_cpuop_funcs);
1.1 root 334:
335: build_cpufunctbl ();
336: }
337:
1.1.1.4 root 338:
1.1.1.8 root 339: /* not used ATM:
1.1 root 340: static struct regstruct regs_backup[16];
341: static int backup_pointer = 0;
1.1.1.10 root 342: struct regstruct lastint_regs;
343: int lastint_no;
1.1.1.8 root 344: */
1.1.1.10 root 345: struct regstruct regs;
1.1 root 346: static long int m68kpc_offset;
1.1.1.10 root 347:
1.1 root 348:
349: #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
350: #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
351: #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
352:
353: uae_s32 ShowEA (FILE *f, int reg, amodes mode, wordsizes size, char *buf)
354: {
355: uae_u16 dp;
356: uae_s8 disp8;
357: uae_s16 disp16;
358: int r;
359: uae_u32 dispreg;
360: uaecptr addr;
361: uae_s32 offset = 0;
362: char buffer[80];
363:
364: switch (mode){
365: case Dreg:
366: sprintf (buffer,"D%d", reg);
367: break;
368: case Areg:
369: sprintf (buffer,"A%d", reg);
370: break;
371: case Aind:
372: sprintf (buffer,"(A%d)", reg);
373: break;
374: case Aipi:
375: sprintf (buffer,"(A%d)+", reg);
376: break;
377: case Apdi:
378: sprintf (buffer,"-(A%d)", reg);
379: break;
380: case Ad16:
381: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
382: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
383: sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
384: (unsigned long)addr);
385: break;
386: case Ad8r:
387: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
388: disp8 = dp & 0xFF;
389: r = (dp & 0x7000) >> 12;
390: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
391: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
392: dispreg <<= (dp >> 9) & 3;
393:
394: if (dp & 0x100) {
395: uae_s32 outer = 0, disp = 0;
396: uae_s32 base = m68k_areg(regs,reg);
397: char name[10];
398: sprintf (name,"A%d, ",reg);
399: if (dp & 0x80) { base = 0; name[0] = 0; }
400: if (dp & 0x40) dispreg = 0;
401: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
402: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
403: base += disp;
404:
405: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
406: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
407:
408: if (!(dp & 4)) base += dispreg;
409: if (dp & 3) base = get_long (base);
410: if (dp & 4) base += dispreg;
411:
412: addr = base + outer;
413: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
414: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
415: 1 << ((dp >> 9) & 3),
1.1.1.5 root 416: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 417: } else {
418: addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
419: sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
420: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
421: 1 << ((dp >> 9) & 3), disp8,
422: (unsigned long)addr);
423: }
424: break;
425: case PC16:
426: addr = m68k_getpc () + m68kpc_offset;
427: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
428: addr += (uae_s16)disp16;
429: sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
430: break;
431: case PC8r:
432: addr = m68k_getpc () + m68kpc_offset;
433: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
434: disp8 = dp & 0xFF;
435: r = (dp & 0x7000) >> 12;
436: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
437: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
438: dispreg <<= (dp >> 9) & 3;
439:
440: if (dp & 0x100) {
441: uae_s32 outer = 0,disp = 0;
442: uae_s32 base = addr;
443: char name[10];
444: sprintf (name,"PC, ");
445: if (dp & 0x80) { base = 0; name[0] = 0; }
446: if (dp & 0x40) dispreg = 0;
447: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
448: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
449: base += disp;
450:
451: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
452: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
453:
454: if (!(dp & 4)) base += dispreg;
455: if (dp & 3) base = get_long (base);
456: if (dp & 4) base += dispreg;
457:
458: addr = base + outer;
459: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
460: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
461: 1 << ((dp >> 9) & 3),
1.1.1.5 root 462: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 463: } else {
464: addr += (uae_s32)((uae_s8)disp8) + dispreg;
465: sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
466: (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
467: disp8, (unsigned long)addr);
468: }
469: break;
470: case absw:
471: sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
472: m68kpc_offset += 2;
473: break;
474: case absl:
475: sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
476: m68kpc_offset += 4;
477: break;
478: case imm:
479: switch (size){
480: case sz_byte:
481: sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
482: m68kpc_offset += 2;
483: break;
484: case sz_word:
485: sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
486: m68kpc_offset += 2;
487: break;
488: case sz_long:
489: sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
490: m68kpc_offset += 4;
491: break;
492: default:
493: break;
494: }
495: break;
496: case imm0:
497: offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
498: m68kpc_offset += 2;
499: sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
500: break;
501: case imm1:
502: offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
503: m68kpc_offset += 2;
504: sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
505: break;
506: case imm2:
507: offset = (uae_s32)get_ilong_1 (m68kpc_offset);
508: m68kpc_offset += 4;
509: sprintf (buffer,"#$%08lx", (unsigned long)offset);
510: break;
511: case immi:
512: offset = (uae_s32)(uae_s8)(reg & 0xff);
513: sprintf (buffer,"#$%08lx", (unsigned long)offset);
514: break;
515: default:
516: break;
517: }
518: if (buf == 0)
519: fprintf (f, "%s", buffer);
520: else
521: strcat (buf, buffer);
522: return offset;
523: }
524:
1.1.1.8 root 525:
1.1 root 526: /* The plan is that this will take over the job of exception 3 handling -
527: * the CPU emulation functions will just do a longjmp to m68k_go whenever
528: * they hit an odd address. */
1.1.1.8 root 529: #if 0
1.1 root 530: static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
531: {
532: uae_u16 dp;
533: uae_s8 disp8;
534: uae_s16 disp16;
535: int r;
536: uae_u32 dispreg;
537: uaecptr addr;
1.1.1.5 root 538: /*uae_s32 offset = 0;*/
1.1 root 539:
540: switch (mode){
541: case Dreg:
542: *val = m68k_dreg (regs, reg);
543: return 1;
544: case Areg:
545: *val = m68k_areg (regs, reg);
546: return 1;
547:
548: case Aind:
549: case Aipi:
550: addr = m68k_areg (regs, reg);
551: break;
552: case Apdi:
553: addr = m68k_areg (regs, reg);
554: break;
555: case Ad16:
556: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
557: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
558: break;
559: case Ad8r:
560: addr = m68k_areg (regs, reg);
561: d8r_common:
562: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
563: disp8 = dp & 0xFF;
564: r = (dp & 0x7000) >> 12;
565: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
566: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
567: dispreg <<= (dp >> 9) & 3;
568:
569: if (dp & 0x100) {
570: uae_s32 outer = 0, disp = 0;
571: uae_s32 base = addr;
572: if (dp & 0x80) base = 0;
573: if (dp & 0x40) dispreg = 0;
574: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
575: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
576: base += disp;
577:
578: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
579: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
580:
581: if (!(dp & 4)) base += dispreg;
582: if (dp & 3) base = get_long (base);
583: if (dp & 4) base += dispreg;
584:
585: addr = base + outer;
586: } else {
587: addr += (uae_s32)((uae_s8)disp8) + dispreg;
588: }
589: break;
590: case PC16:
591: addr = m68k_getpc () + m68kpc_offset;
592: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
593: addr += (uae_s16)disp16;
594: break;
595: case PC8r:
596: addr = m68k_getpc () + m68kpc_offset;
597: goto d8r_common;
598: case absw:
599: addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
600: m68kpc_offset += 2;
601: break;
602: case absl:
603: addr = get_ilong_1 (m68kpc_offset);
604: m68kpc_offset += 4;
605: break;
606: case imm:
607: switch (size){
608: case sz_byte:
609: *val = get_iword_1 (m68kpc_offset) & 0xff;
610: m68kpc_offset += 2;
611: break;
612: case sz_word:
613: *val = get_iword_1 (m68kpc_offset) & 0xffff;
614: m68kpc_offset += 2;
615: break;
616: case sz_long:
617: *val = get_ilong_1 (m68kpc_offset);
618: m68kpc_offset += 4;
619: break;
620: default:
621: break;
622: }
623: return 1;
624: case imm0:
625: *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
626: m68kpc_offset += 2;
627: return 1;
628: case imm1:
629: *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
630: m68kpc_offset += 2;
631: return 1;
632: case imm2:
633: *val = get_ilong_1 (m68kpc_offset);
634: m68kpc_offset += 4;
635: return 1;
636: case immi:
637: *val = (uae_s32)(uae_s8)(reg & 0xff);
638: return 1;
639: default:
640: addr = 0;
641: break;
642: }
643: if ((addr & 1) == 0)
644: return 1;
645:
646: last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
647: last_fault_for_exception_3 = addr;
648: return 0;
649: }
1.1.1.8 root 650: #endif
651:
1.1 root 652:
653: uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
654: {
655: int reg = (dp >> 12) & 15;
656: uae_s32 regd = regs.regs[reg];
657: if ((dp & 0x800) == 0)
658: regd = (uae_s32)(uae_s16)regd;
659: regd <<= (dp >> 9) & 3;
660: if (dp & 0x100) {
661: uae_s32 outer = 0;
662: if (dp & 0x80) base = 0;
663: if (dp & 0x40) regd = 0;
664:
665: if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
666: if ((dp & 0x30) == 0x30) base += next_ilong();
667:
668: if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
669: if ((dp & 0x3) == 0x3) outer = next_ilong();
670:
671: if ((dp & 0x4) == 0) base += regd;
672: if (dp & 0x3) base = get_long (base);
673: if (dp & 0x4) base += regd;
674:
675: return base + outer;
676: } else {
677: return base + (uae_s32)((uae_s8)dp) + regd;
678: }
679: }
680:
681: uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
682: {
683: int reg = (dp >> 12) & 15;
684: uae_s32 regd = regs.regs[reg];
685: #if 1
686: if ((dp & 0x800) == 0)
687: regd = (uae_s32)(uae_s16)regd;
688: return base + (uae_s8)dp + regd;
689: #else
690: /* Branch-free code... benchmark this again now that
691: * things are no longer inline. */
692: uae_s32 regd16;
693: uae_u32 mask;
694: mask = ((dp & 0x800) >> 11) - 1;
695: regd16 = (uae_s32)(uae_s16)regd;
696: regd16 &= mask;
697: mask = ~mask;
698: base += (uae_s8)dp;
699: regd &= mask;
700: regd |= regd16;
701: return base + regd;
702: #endif
703: }
704:
1.1.1.8 root 705:
706: /* Create the Status Register from the flags */
1.1 root 707: void MakeSR (void)
708: {
709: #if 0
710: assert((regs.t1 & 1) == regs.t1);
711: assert((regs.t0 & 1) == regs.t0);
712: assert((regs.s & 1) == regs.s);
713: assert((regs.m & 1) == regs.m);
714: assert((XFLG & 1) == XFLG);
715: assert((NFLG & 1) == NFLG);
716: assert((ZFLG & 1) == ZFLG);
717: assert((VFLG & 1) == VFLG);
718: assert((CFLG & 1) == CFLG);
719: #endif
720: regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
721: | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
722: | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
723: | GET_CFLG);
724: }
725:
1.1.1.8 root 726:
727: /* Set up the flags from Status Register */
1.1 root 728: void MakeFromSR (void)
729: {
730: int oldm = regs.m;
731: int olds = regs.s;
732:
733: regs.t1 = (regs.sr >> 15) & 1;
734: regs.t0 = (regs.sr >> 14) & 1;
735: regs.s = (regs.sr >> 13) & 1;
736: regs.m = (regs.sr >> 12) & 1;
737: regs.intmask = (regs.sr >> 8) & 7;
738: SET_XFLG ((regs.sr >> 4) & 1);
739: SET_NFLG ((regs.sr >> 3) & 1);
740: SET_ZFLG ((regs.sr >> 2) & 1);
741: SET_VFLG ((regs.sr >> 1) & 1);
742: SET_CFLG (regs.sr & 1);
1.1.1.12 root 743: if (currprefs.cpu_level >= 2) {
1.1 root 744: if (olds != regs.s) {
745: if (olds) {
746: if (oldm)
747: regs.msp = m68k_areg(regs, 7);
748: else
749: regs.isp = m68k_areg(regs, 7);
750: m68k_areg(regs, 7) = regs.usp;
751: } else {
752: regs.usp = m68k_areg(regs, 7);
753: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
754: }
755: } else if (olds && oldm != regs.m) {
756: if (oldm) {
757: regs.msp = m68k_areg(regs, 7);
758: m68k_areg(regs, 7) = regs.isp;
759: } else {
760: regs.isp = m68k_areg(regs, 7);
761: m68k_areg(regs, 7) = regs.msp;
762: }
763: }
764: } else {
1.1.1.12 root 765: /* [NP] If cpu < 68020, m and t0 are ignored and should be set to 0 */
766: regs.t0 = 0;
767: regs.m = 0;
768:
1.1 root 769: if (olds != regs.s) {
770: if (olds) {
771: regs.isp = m68k_areg(regs, 7);
772: m68k_areg(regs, 7) = regs.usp;
773: } else {
774: regs.usp = m68k_areg(regs, 7);
775: m68k_areg(regs, 7) = regs.isp;
776: }
777: }
778: }
779:
1.1.1.8 root 780: /* Pending interrupts can occur again after a write to the SR: */
781: set_special (SPCFLAG_DOINT);
1.1 root 782: if (regs.t1 || regs.t0)
783: set_special (SPCFLAG_TRACE);
784: else
1.1.1.6 root 785: /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
786: SR-modifying instructions (including STOP). */
787: unset_special (SPCFLAG_TRACE);
1.1 root 788: }
789:
1.1.1.5 root 790:
1.1.1.12 root 791: static void exception_trace (int nr)
792: {
793: unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
794: if (regs.t1 && !regs.t0) {
795: /* trace stays pending if exception is div by zero, chk,
796: * trapv or trap #x
797: */
798: if (nr == 5 || nr == 6 || nr == 7 || (nr >= 32 && nr <= 47))
799: set_special (SPCFLAG_DOTRACE);
800: }
801: regs.t1 = regs.t0 = regs.m = 0;
802: }
803:
804:
1.1.1.14 root 805: /*
806: * Compute the number of jitter cycles to add when a video interrupt occurs
807: * (this is specific to the Atari ST)
808: */
809: static void InterruptAddJitter (int Level , int Pending)
810: {
811: int cycles = 0;
812:
813: if ( Level == 2 ) /* HBL */
814: {
815: if ( Pending )
816: cycles = HblJitterArrayPending[ HblJitterIndex ];
817: else
818: cycles = HblJitterArray[ HblJitterIndex ];
819: }
820:
821: else if ( Level == 4 ) /* VBL */
822: {
823: if ( Pending )
824: cycles = VblJitterArrayPending[ VblJitterIndex ];
825: else
826: cycles = VblJitterArray[ VblJitterIndex ];
827: }
828:
829: //fprintf ( stderr , "jitter %d\n" , cycles );
830: //cycles=0;
831: if ( cycles > 0 ) /* no need to call M68000_AddCycles if cycles == 0 */
832: M68000_AddCycles ( cycles );
833: }
834:
835:
1.1.1.13 root 836: /* Handle exceptions. We need a special case to handle MFP exceptions */
837: /* on Atari ST, because it's possible to change the MFP's vector base */
838: /* and get a conflict with 'normal' cpu exceptions. */
839: void Exception(int nr, uaecptr oldpc, int ExceptionSource)
1.1 root 840: {
841: uae_u32 currpc = m68k_getpc ();
842:
1.1.1.2 root 843: /*if( nr>=2 && nr<10 ) fprintf(stderr,"Exception (-> %i bombs)!\n",nr);*/
1.1 root 844:
1.1.1.7 root 845: /* Intercept VDI exception (Trap #2 with D0 = 0x73) */
1.1.1.16! root 846: if (ExceptionSource == M68000_EXC_SRC_CPU)
1.1.1.5 root 847: {
1.1.1.13 root 848: if(bUseVDIRes && nr == 0x22 && regs.regs[0] == 0x73)
849: {
850: if(!VDI())
851: {
852: /* Set 'PC' as address of 'VDI_OPCODE' illegal instruction
853: * This will call OpCode_VDI after completion of Trap call!
854: * Use to modify return structure from VDI */
855: VDI_OldPC = currpc;
856: currpc = CART_VDI_OPCODE_ADDR;
857: }
858: }
1.1.1.16! root 859:
1.1.1.13 root 860: if (bBiosIntercept)
861: {
862: /* Intercept BIOS or XBIOS trap (Trap #13 or #14) */
863: if (nr == 0x2d)
864: {
865: /* Intercept BIOS calls */
866: if (Bios()) return;
867: }
868: else if (nr == 0x2e)
869: {
870: /* Intercept XBIOS calls */
871: if (XBios()) return;
872: }
873: }
1.1.1.5 root 874: }
1.1.1.8 root 875:
1.1 root 876: MakeSR();
877:
1.1.1.8 root 878: /* Change to supervisor mode if necessary */
1.1 root 879: if (!regs.s) {
880: regs.usp = m68k_areg(regs, 7);
1.1.1.12 root 881: if (currprefs.cpu_level >= 2)
1.1 root 882: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
883: else
884: m68k_areg(regs, 7) = regs.isp;
885: regs.s = 1;
886: }
1.1.1.8 root 887:
888: /* Build additional exception stack frame for 68010 and higher */
1.1.1.13 root 889: /* (special case for MFP) */
1.1.1.12 root 890: if (currprefs.cpu_level > 0) {
1.1.1.16! root 891: if (ExceptionSource == M68000_EXC_SRC_INT_MFP
! 892: || ExceptionSource == M68000_EXC_SRC_INT_DSP) {
1.1.1.13 root 893: m68k_areg(regs, 7) -= 2;
894: put_word (m68k_areg(regs, 7), nr * 4); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
895: }
896: else if (nr == 2 || nr == 3) {
1.1 root 897: int i;
898: /* @@@ this is probably wrong (?) */
899: for (i = 0 ; i < 12 ; i++) {
900: m68k_areg(regs, 7) -= 2;
901: put_word (m68k_areg(regs, 7), 0);
902: }
903: m68k_areg(regs, 7) -= 2;
904: put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
905: } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
906: m68k_areg(regs, 7) -= 4;
907: put_long (m68k_areg(regs, 7), oldpc);
908: m68k_areg(regs, 7) -= 2;
909: put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
910: } else if (regs.m && nr >= 24 && nr < 32) {
911: m68k_areg(regs, 7) -= 2;
912: put_word (m68k_areg(regs, 7), nr * 4);
913: m68k_areg(regs, 7) -= 4;
914: put_long (m68k_areg(regs, 7), currpc);
915: m68k_areg(regs, 7) -= 2;
916: put_word (m68k_areg(regs, 7), regs.sr);
917: regs.sr |= (1 << 13);
918: regs.msp = m68k_areg(regs, 7);
919: m68k_areg(regs, 7) = regs.isp;
920: m68k_areg(regs, 7) -= 2;
921: put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
922: } else {
923: m68k_areg(regs, 7) -= 2;
924: put_word (m68k_areg(regs, 7), nr * 4);
925: }
926: }
1.1.1.3 root 927:
928: /* Push PC on stack: */
1.1 root 929: m68k_areg(regs, 7) -= 4;
930: put_long (m68k_areg(regs, 7), currpc);
1.1.1.3 root 931: /* Push SR on stack: */
1.1 root 932: m68k_areg(regs, 7) -= 2;
933: put_word (m68k_areg(regs, 7), regs.sr);
1.1.1.3 root 934:
1.1.1.15 root 935: LOG_TRACE(TRACE_CPU_EXCEPTION, "cpu exception %d currpc %x buspc %x newpc %x fault_e3 %x op_e3 %hx addr_e3 %x\n",
936: nr, currpc, BusErrorPC, get_long (regs.vbr + 4*nr), last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3);
1.1.1.12 root 937:
1.1.1.3 root 938: /* 68000 bus/address errors: */
1.1.1.16! root 939: if (currprefs.cpu_level==0 && (nr==2 || nr==3) && ExceptionSource == M68000_EXC_SRC_CPU) {
1.1.1.12 root 940: uae_u16 specialstatus = 1;
941:
1.1.1.8 root 942: /* Special status word emulation isn't perfect yet... :-( */
943: if (regs.sr & 0x2000)
944: specialstatus |= 0x4;
1.1.1.3 root 945: m68k_areg(regs, 7) -= 8;
946: if (nr == 3) { /* Address error */
1.1.1.12 root 947: specialstatus |= ( last_op_for_exception_3 & (~0x1f) ); /* [NP] unused bits of specialstatus are those of the last opcode ! */
1.1.1.8 root 948: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.3 root 949: put_long (m68k_areg(regs, 7)+2, last_fault_for_exception_3);
950: put_word (m68k_areg(regs, 7)+6, last_op_for_exception_3);
951: put_long (m68k_areg(regs, 7)+10, last_addr_for_exception_3);
1.1.1.15 root 952: if (bExceptionDebugging) {
1.1.1.8 root 953: fprintf(stderr,"Address Error at address $%x, PC=$%x\n",last_fault_for_exception_3,currpc);
954: DebugUI();
955: }
1.1.1.3 root 956: }
1.1.1.8 root 957: else { /* Bus error */
1.1.1.12 root 958: specialstatus |= ( get_word(BusErrorPC) & (~0x1f) ); /* [NP] unused bits of special status are those of the last opcode ! */
1.1.1.8 root 959: if (bBusErrorReadWrite)
960: specialstatus |= 0x10;
961: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.10 root 962: put_long (m68k_areg(regs, 7)+2, BusErrorAddress);
1.1.1.12 root 963: put_word (m68k_areg(regs, 7)+6, get_word(BusErrorPC)); /* Opcode */
964:
965: /* [NP] PC stored in the stack frame is not necessarily pointing to the next instruction ! */
966: /* FIXME : we should have a proper model for this, in the meantime we handle specific cases */
1.1.1.16! root 967: if ( get_word(BusErrorPC) == 0x21f8 ) /* move.l $0.w,$24.w (Transbeauce 2 loader) */
1.1.1.12 root 968: put_long (m68k_areg(regs, 7)+10, currpc-2); /* correct PC is 2 bytes less than usual value */
1.1.1.8 root 969: /* Check for double bus errors: */
970: if (regs.spcflags & SPCFLAG_BUSERROR) {
971: fprintf(stderr, "Detected double bus error at address $%x, PC=$%lx => CPU halted!\n",
1.1.1.10 root 972: BusErrorAddress, (long)currpc);
1.1.1.8 root 973: unset_special(SPCFLAG_BUSERROR);
1.1.1.15 root 974: if (bExceptionDebugging)
1.1.1.8 root 975: DebugUI();
1.1.1.15 root 976: else
977: DlgAlert_Notice("Detected double bus error => CPU halted!\nEmulation needs to be reseted.\n");
1.1.1.8 root 978: regs.intmask = 7;
1.1.1.15 root 979: m68k_setstopped(true);
1.1.1.8 root 980: return;
981: }
1.1.1.15 root 982: if (bExceptionDebugging && BusErrorAddress!=0xff8a00) {
1.1.1.10 root 983: fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n", BusErrorAddress, (long)currpc);
1.1.1.8 root 984: DebugUI();
985: }
986: }
1.1.1.3 root 987: }
988:
1.1.1.8 root 989: /* Set PC and flags */
1.1.1.15 root 990: if (bExceptionDebugging && get_long (regs.vbr + 4*nr) == 0) {
1.1.1.8 root 991: write_log("Uninitialized exception handler #%i!\n", nr);
1.1.1.13 root 992: DebugUI();
1.1.1.8 root 993: }
1.1 root 994: m68k_setpc (get_long (regs.vbr + 4*nr));
995: fill_prefetch_0 ();
1.1.1.12 root 996: /* Handle trace flags depending on current state */
997: exception_trace (nr);
1.1.1.6 root 998:
1.1.1.13 root 999: /* Handle exception cycles (special case for MFP) */
1.1.1.16! root 1000: if (ExceptionSource == M68000_EXC_SRC_INT_MFP)
1.1.1.13 root 1001: {
1002: M68000_AddCycles(44+12); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
1003: }
1004: else if (nr >= 24 && nr <= 31)
1.1.1.7 root 1005: {
1.1.1.15 root 1006: if ( nr == 26 ) /* HBL */
1007: {
1008: /* store current cycle pos when then interrupt was received (see video.c) */
1009: LastCycleHblException = Cycles_GetCounter(CYCLES_COUNTER_VIDEO);
1010: M68000_AddCycles(44+12); /* Video Interrupt */
1011: }
1012: else if ( nr == 28 ) /* VBL */
1.1.1.12 root 1013: M68000_AddCycles(44+12); /* Video Interrupt */
1014: else
1015: M68000_AddCycles(44+4); /* Other Interrupts */
1.1.1.7 root 1016: }
1017: else if(nr >= 32 && nr <= 47)
1018: {
1.1.1.13 root 1019: M68000_AddCycles(34-4); /* Trap (total is 34, but cpuemu.c already adds 4) */
1.1.1.7 root 1020: }
1021: else switch(nr)
1022: {
1.1.1.12 root 1023: case 2: M68000_AddCycles(50); break; /* Bus error */
1024: case 3: M68000_AddCycles(50); break; /* Address error */
1025: case 4: M68000_AddCycles(34); break; /* Illegal instruction */
1026: case 5: M68000_AddCycles(38); break; /* Div by zero */
1027: case 6: M68000_AddCycles(40); break; /* CHK */
1028: case 7: M68000_AddCycles(34); break; /* TRAPV */
1029: case 8: M68000_AddCycles(34); break; /* Privilege violation */
1030: case 9: M68000_AddCycles(34); break; /* Trace */
1031: case 10: M68000_AddCycles(34); break; /* Line-A - probably wrong */
1032: case 11: M68000_AddCycles(34); break; /* Line-F - probably wrong */
1.1.1.7 root 1033: default:
1.1.1.8 root 1034: /* FIXME: Add right cycles value for MFP interrupts and copro exceptions ... */
1.1.1.7 root 1035: if(nr < 64)
1.1.1.12 root 1036: M68000_AddCycles(4); /* Coprocessor and unassigned exceptions (???) */
1.1.1.7 root 1037: else
1.1.1.16! root 1038: M68000_AddCycles(44+12); /* Must be a MFP or DSP interrupt */
1.1.1.7 root 1039: break;
1.1.1.6 root 1040: }
1.1.1.14 root 1041:
1.1 root 1042: }
1043:
1.1.1.7 root 1044:
1.1.1.14 root 1045: static void Interrupt(int nr , int Pending)
1.1 root 1046: {
1047: assert(nr < 8 && nr >= 0);
1.1.1.10 root 1048: /*lastint_regs = regs;*/
1049: /*lastint_no = nr;*/
1.1.1.13 root 1050:
1.1.1.16! root 1051: /* On Hatari, only video ints are using SPCFLAG_INT (see m68000.c) */
! 1052: Exception(nr+24, 0, M68000_EXC_SRC_AUTOVEC);
1.1 root 1053:
1054: regs.intmask = nr;
1055: set_special (SPCFLAG_INT);
1.1.1.14 root 1056:
1057: /* Handle Atari ST's specific jitter for hbl/vbl */
1058: InterruptAddJitter ( nr , Pending );
1.1 root 1059: }
1060:
1.1.1.7 root 1061:
1.1.1.12 root 1062: uae_u32 caar, cacr;
1.1.1.8 root 1063: static uae_u32 itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp;
1.1 root 1064:
1.1.1.7 root 1065:
1.1.1.12 root 1066: static int movec_illg (int regno)
1067: {
1068: int regno2 = regno & 0x7ff;
1069: if (currprefs.cpu_level == 1) { /* 68010 */
1070: if (regno2 < 2)
1071: return 0;
1072: return 1;
1073: }
1074: if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) { /* 68020 */
1075: if (regno == 3) return 1; /* 68040 only */
1076: /* 4 is >=68040, but 0x804 is in 68020 */
1077: if (regno2 < 4 || regno == 0x804)
1078: return 0;
1079: return 1;
1080: }
1081: if (currprefs.cpu_level >= 4) { /* 68040 */
1082: if (regno == 0x802) return 1; /* 68020 only */
1083: if (regno2 < 8) return 0;
1084: if (currprefs.cpu_level == 6 && regno2 == 8) /* 68060 only */
1085: return 0;
1086: return 1;
1087: }
1088: return 1;
1089: }
1090:
1.1 root 1091: int m68k_move2c (int regno, uae_u32 *regp)
1092: {
1.1.1.12 root 1093: if (movec_illg (regno)) {
1.1 root 1094: op_illg (0x4E7B);
1095: return 0;
1096: } else {
1097: switch (regno) {
1098: case 0: regs.sfc = *regp & 7; break;
1099: case 1: regs.dfc = *regp & 7; break;
1.1.1.16! root 1100: case 2:
! 1101: {
! 1102: uae_u32 cacr_mask = 0;
! 1103: if (currprefs.cpu_level == 2) // 68020
! 1104: cacr_mask = 0x0000000f;
! 1105: else if (currprefs.cpu_level == 3) // Fake 68030
! 1106: cacr_mask = 0x00003f1f;
! 1107: else if (currprefs.cpu_level == 4) // 68040
! 1108: cacr_mask = 0x80008000;
! 1109: cacr = *regp & cacr_mask;
! 1110: }
1.1 root 1111: case 3: tc = *regp & 0xc000; break;
1112: /* Mask out fields that should be zero. */
1113: case 4: itt0 = *regp & 0xffffe364; break;
1114: case 5: itt1 = *regp & 0xffffe364; break;
1115: case 6: dtt0 = *regp & 0xffffe364; break;
1116: case 7: dtt1 = *regp & 0xffffe364; break;
1.1.1.7 root 1117:
1.1 root 1118: case 0x800: regs.usp = *regp; break;
1119: case 0x801: regs.vbr = *regp; break;
1.1.1.12 root 1120: case 0x802: caar = *regp & 0xfc; break;
1.1 root 1121: case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
1122: case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
1.1.1.6 root 1123: case 0x805: mmusr = *regp; break;
1124: case 0x806: urp = *regp; break;
1125: case 0x807: srp = *regp; break;
1.1 root 1126: default:
1127: op_illg (0x4E7B);
1128: return 0;
1129: }
1130: }
1131: return 1;
1132: }
1133:
1134: int m68k_movec2 (int regno, uae_u32 *regp)
1135: {
1.1.1.12 root 1136: if (movec_illg (regno)) {
1.1 root 1137: op_illg (0x4E7A);
1138: return 0;
1139: } else {
1140: switch (regno) {
1141: case 0: *regp = regs.sfc; break;
1142: case 1: *regp = regs.dfc; break;
1.1.1.12 root 1143: case 2: *regp = cacr; break;
1.1 root 1144: case 3: *regp = tc; break;
1145: case 4: *regp = itt0; break;
1146: case 5: *regp = itt1; break;
1147: case 6: *regp = dtt0; break;
1148: case 7: *regp = dtt1; break;
1149: case 0x800: *regp = regs.usp; break;
1150: case 0x801: *regp = regs.vbr; break;
1.1.1.12 root 1151: case 0x802: *regp = caar; break;
1.1 root 1152: case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
1153: case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
1154: case 0x805: *regp = mmusr; break;
1.1.1.6 root 1155: case 0x806: *regp = urp; break;
1156: case 0x807: *regp = srp; break;
1.1 root 1157: default:
1158: op_illg (0x4E7A);
1159: return 0;
1160: }
1161: }
1162: return 1;
1163: }
1164:
1165: STATIC_INLINE int
1.1.1.10 root 1166: div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 ndiv, uae_u32 *quot, uae_u32 *rem)
1.1 root 1167: {
1168: uae_u32 q = 0, cbit = 0;
1169: int i;
1170:
1.1.1.10 root 1171: if (ndiv <= src_hi) {
1.1 root 1172: return 1;
1173: }
1174: for (i = 0 ; i < 32 ; i++) {
1175: cbit = src_hi & 0x80000000ul;
1176: src_hi <<= 1;
1177: if (src_lo & 0x80000000ul) src_hi++;
1178: src_lo <<= 1;
1179: q = q << 1;
1.1.1.10 root 1180: if (cbit || ndiv <= src_hi) {
1.1 root 1181: q |= 1;
1.1.1.10 root 1182: src_hi -= ndiv;
1.1 root 1183: }
1184: }
1185: *quot = q;
1186: *rem = src_hi;
1187: return 0;
1188: }
1189:
1190: void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
1191: {
1192: #if defined(uae_s64)
1193: if (src == 0) {
1.1.1.16! root 1194: Exception (5, oldpc,M68000_EXC_SRC_CPU);
1.1 root 1195: return;
1196: }
1197: if (extra & 0x800) {
1198: /* signed variant */
1199: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1200: uae_s64 quot, rem;
1201:
1202: if (extra & 0x400) {
1203: a &= 0xffffffffu;
1204: a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
1205: }
1206: rem = a % (uae_s64)(uae_s32)src;
1207: quot = a / (uae_s64)(uae_s32)src;
1208: if ((quot & UVAL64(0xffffffff80000000)) != 0
1209: && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1210: {
1211: SET_VFLG (1);
1212: SET_NFLG (1);
1213: SET_CFLG (0);
1214: } else {
1215: if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
1216: SET_VFLG (0);
1217: SET_CFLG (0);
1218: SET_ZFLG (((uae_s32)quot) == 0);
1219: SET_NFLG (((uae_s32)quot) < 0);
1220: m68k_dreg(regs, extra & 7) = rem;
1221: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1222: }
1223: } else {
1224: /* unsigned */
1225: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1226: uae_u64 quot, rem;
1227:
1228: if (extra & 0x400) {
1229: a &= 0xffffffffu;
1230: a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
1231: }
1232: rem = a % (uae_u64)src;
1233: quot = a / (uae_u64)src;
1234: if (quot > 0xffffffffu) {
1235: SET_VFLG (1);
1236: SET_NFLG (1);
1237: SET_CFLG (0);
1238: } else {
1239: SET_VFLG (0);
1240: SET_CFLG (0);
1241: SET_ZFLG (((uae_s32)quot) == 0);
1242: SET_NFLG (((uae_s32)quot) < 0);
1243: m68k_dreg(regs, extra & 7) = rem;
1244: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1245: }
1246: }
1247: #else
1248: if (src == 0) {
1.1.1.16! root 1249: Exception (5, oldpc,M68000_EXC_SRC_CPU);
1.1 root 1250: return;
1251: }
1252: if (extra & 0x800) {
1253: /* signed variant */
1254: uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1255: uae_s32 hi = lo < 0 ? -1 : 0;
1256: uae_s32 save_high;
1257: uae_u32 quot, rem;
1258: uae_u32 sign;
1259:
1260: if (extra & 0x400) {
1261: hi = (uae_s32)m68k_dreg(regs, extra & 7);
1262: }
1263: save_high = hi;
1264: sign = (hi ^ src);
1265: if (hi < 0) {
1266: hi = ~hi;
1267: lo = -lo;
1268: if (lo == 0) hi++;
1269: }
1270: if ((uae_s32)src < 0) src = -src;
1271: if (div_unsigned(hi, lo, src, ", &rem) ||
1272: (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
1273: SET_VFLG (1);
1274: SET_NFLG (1);
1275: SET_CFLG (0);
1276: } else {
1277: if (sign & 0x80000000) quot = -quot;
1278: if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
1279: SET_VFLG (0);
1280: SET_CFLG (0);
1281: SET_ZFLG (((uae_s32)quot) == 0);
1282: SET_NFLG (((uae_s32)quot) < 0);
1283: m68k_dreg(regs, extra & 7) = rem;
1284: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1285: }
1286: } else {
1287: /* unsigned */
1288: uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1289: uae_u32 hi = 0;
1290: uae_u32 quot, rem;
1291:
1292: if (extra & 0x400) {
1293: hi = (uae_u32)m68k_dreg(regs, extra & 7);
1294: }
1295: if (div_unsigned(hi, lo, src, ", &rem)) {
1296: SET_VFLG (1);
1297: SET_NFLG (1);
1298: SET_CFLG (0);
1299: } else {
1300: SET_VFLG (0);
1301: SET_CFLG (0);
1302: SET_ZFLG (((uae_s32)quot) == 0);
1303: SET_NFLG (((uae_s32)quot) < 0);
1304: m68k_dreg(regs, extra & 7) = rem;
1305: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1306: }
1307: }
1308: #endif
1309: }
1310:
1311: STATIC_INLINE void
1312: mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1313: {
1314: uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1315: uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1316: uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1317: uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1318: uae_u32 lo;
1319:
1320: lo = r0 + ((r1 << 16) & 0xffff0000ul);
1321: if (lo < r0) r3++;
1322: r0 = lo;
1323: lo = r0 + ((r2 << 16) & 0xffff0000ul);
1324: if (lo < r0) r3++;
1325: r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1326: *dst_lo = lo;
1327: *dst_hi = r3;
1328: }
1329:
1330: void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1331: {
1332: #if defined(uae_s64)
1333: if (extra & 0x800) {
1334: /* signed variant */
1335: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1336:
1337: a *= (uae_s64)(uae_s32)src;
1338: SET_VFLG (0);
1339: SET_CFLG (0);
1340: SET_ZFLG (a == 0);
1341: SET_NFLG (a < 0);
1342: if (extra & 0x400)
1343: m68k_dreg(regs, extra & 7) = a >> 32;
1344: else if ((a & UVAL64(0xffffffff80000000)) != 0
1345: && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1346: {
1347: SET_VFLG (1);
1348: }
1349: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1350: } else {
1351: /* unsigned */
1352: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1353:
1354: a *= (uae_u64)src;
1355: SET_VFLG (0);
1356: SET_CFLG (0);
1357: SET_ZFLG (a == 0);
1358: SET_NFLG (((uae_s64)a) < 0);
1359: if (extra & 0x400)
1360: m68k_dreg(regs, extra & 7) = a >> 32;
1361: else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1362: SET_VFLG (1);
1363: }
1364: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1365: }
1366: #else
1367: if (extra & 0x800) {
1368: /* signed variant */
1369: uae_s32 src1,src2;
1370: uae_u32 dst_lo,dst_hi;
1371: uae_u32 sign;
1372:
1373: src1 = (uae_s32)src;
1374: src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1375: sign = (src1 ^ src2);
1376: if (src1 < 0) src1 = -src1;
1377: if (src2 < 0) src2 = -src2;
1378: mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1379: if (sign & 0x80000000) {
1380: dst_hi = ~dst_hi;
1381: dst_lo = -dst_lo;
1382: if (dst_lo == 0) dst_hi++;
1383: }
1384: SET_VFLG (0);
1385: SET_CFLG (0);
1386: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1387: SET_NFLG (((uae_s32)dst_hi) < 0);
1388: if (extra & 0x400)
1389: m68k_dreg(regs, extra & 7) = dst_hi;
1390: else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1391: && ((dst_hi & 0xffffffff) != 0xffffffff
1392: || (dst_lo & 0x80000000) != 0x80000000))
1393: {
1394: SET_VFLG (1);
1395: }
1396: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1397: } else {
1398: /* unsigned */
1399: uae_u32 dst_lo,dst_hi;
1400:
1401: mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1402:
1403: SET_VFLG (0);
1404: SET_CFLG (0);
1405: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1406: SET_NFLG (((uae_s32)dst_hi) < 0);
1407: if (extra & 0x400)
1408: m68k_dreg(regs, extra & 7) = dst_hi;
1409: else if (dst_hi != 0) {
1410: SET_VFLG (1);
1411: }
1412: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1413: }
1414: #endif
1415: }
1.1.1.6 root 1416:
1.1 root 1417:
1418: void m68k_reset (void)
1419: {
1420: regs.s = 1;
1421: regs.m = 0;
1422: regs.stopped = 0;
1423: regs.t1 = 0;
1424: regs.t0 = 0;
1425: SET_ZFLG (0);
1426: SET_XFLG (0);
1427: SET_CFLG (0);
1428: SET_VFLG (0);
1429: SET_NFLG (0);
1.1.1.16! root 1430: regs.spcflags &= ( SPCFLAG_MODE_CHANGE | SPCFLAG_DEBUGGER ); /* Clear specialflags except mode-change and debugger */
1.1 root 1431: regs.intmask = 7;
1432: regs.vbr = regs.sfc = regs.dfc = 0;
1433: regs.fpcr = regs.fpsr = regs.fpiar = 0;
1.1.1.7 root 1434:
1435: m68k_areg(regs, 7) = get_long(0);
1436: m68k_setpc(get_long(4));
1437: refill_prefetch (m68k_getpc(), 0);
1.1 root 1438: }
1439:
1.1.1.8 root 1440:
1.1 root 1441: unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1442: {
1.1.1.8 root 1443: #if 0
1.1 root 1444: uaecptr pc = m68k_getpc ();
1.1.1.8 root 1445: #endif
1.1.1.6 root 1446: if ((opcode & 0xF000) == 0xF000) {
1.1.1.16! root 1447: Exception(0xB,0,M68000_EXC_SRC_CPU);
1.1 root 1448: return 4;
1.1.1.6 root 1449: }
1450: if ((opcode & 0xF000) == 0xA000) {
1.1.1.16! root 1451: Exception(0xA,0,M68000_EXC_SRC_CPU);
1.1 root 1452: return 4;
1.1.1.6 root 1453: }
1.1.1.3 root 1454: #if 0
1.1.1.6 root 1455: write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc);
1.1 root 1456: #endif
1.1.1.16! root 1457: Exception (4,0,M68000_EXC_SRC_CPU);
1.1 root 1458: return 4;
1459: }
1460:
1.1.1.8 root 1461:
1.1 root 1462: void mmu_op(uae_u32 opcode, uae_u16 extra)
1463: {
1464: if ((opcode & 0xFE0) == 0x0500) {
1465: /* PFLUSH */
1466: mmusr = 0;
1467: write_log ("PFLUSH\n");
1468: } else if ((opcode & 0x0FD8) == 0x548) {
1469: /* PTEST */
1470: write_log ("PTEST\n");
1471: } else
1472: op_illg (opcode);
1473: }
1474:
1475:
1476: static uaecptr last_trace_ad = 0;
1477:
1478: static void do_trace (void)
1479: {
1.1.1.12 root 1480: if (regs.t0 && currprefs.cpu_level >= 2) {
1.1 root 1481: uae_u16 opcode;
1482: /* should also include TRAP, CHK, SR modification FPcc */
1483: /* probably never used so why bother */
1484: /* We can afford this to be inefficient... */
1485: m68k_setpc (m68k_getpc ());
1486: fill_prefetch_0 ();
1487: opcode = get_word (regs.pc);
1488: if (opcode == 0x4e72 /* RTE */
1489: || opcode == 0x4e74 /* RTD */
1490: || opcode == 0x4e75 /* RTS */
1491: || opcode == 0x4e77 /* RTR */
1492: || opcode == 0x4e76 /* TRAPV */
1493: || (opcode & 0xffc0) == 0x4e80 /* JSR */
1494: || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1495: || (opcode & 0xff00) == 0x6100 /* BSR */
1496: || ((opcode & 0xf000) == 0x6000 /* Bcc */
1497: && cctrue((opcode >> 8) & 0xf))
1498: || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1499: && !cctrue((opcode >> 8) & 0xf)
1500: && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1501: {
1502: last_trace_ad = m68k_getpc ();
1503: unset_special (SPCFLAG_TRACE);
1504: set_special (SPCFLAG_DOTRACE);
1505: }
1506: } else if (regs.t1) {
1507: last_trace_ad = m68k_getpc ();
1508: unset_special (SPCFLAG_TRACE);
1509: set_special (SPCFLAG_DOTRACE);
1510: }
1511: }
1512:
1513:
1.1.1.8 root 1514: /*
1515: * Handle special flags
1516: */
1.1.1.14 root 1517:
1518: static bool do_specialties_interrupt (int Pending)
1519: {
1520: /* Check for MFP ints first (level 6) */
1521: if (regs.spcflags & SPCFLAG_MFP) {
1.1.1.15 root 1522: if (MFP_CheckPendingInterrupts() == true)
1523: return true; /* MFP exception was generated, no higher interrupt can happen */
1.1.1.14 root 1524: }
1525:
1526: /* No MFP int, check for VBL/HBL ints (levels 4/2) */
1527: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1528: int intr = intlev ();
1529: /* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */
1530: // unset_special (SPCFLAG_DOINT);
1531: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1532: if (intr != -1 && intr > regs.intmask) {
1533: Interrupt (intr , Pending); /* process the interrupt and add pending jitter if necessary */
1.1.1.15 root 1534: return true;
1.1.1.14 root 1535: }
1536: }
1537:
1.1.1.15 root 1538: return false; /* no interrupt was found */
1.1.1.14 root 1539: }
1540:
1541:
1.1 root 1542: static int do_specialties (void)
1543: {
1.1.1.7 root 1544: if(regs.spcflags & SPCFLAG_BUSERROR) {
1545: /* We can not execute bus errors directly in the memory handler
1546: * functions since the PC should point to the address of the next
1547: * instruction, so we're executing the bus errors here: */
1.1.1.8 root 1548: unset_special(SPCFLAG_BUSERROR);
1.1.1.16! root 1549: Exception(2,0,M68000_EXC_SRC_CPU);
1.1.1.7 root 1550: }
1551:
1.1.1.8 root 1552: if(regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1553: /* Add some extra cycles to simulate a wait state */
1554: unset_special(SPCFLAG_EXTRA_CYCLES);
1.1.1.11 root 1555: M68000_AddCycles(nWaitStateCycles);
1.1.1.12 root 1556: nWaitStateCycles = 0;
1.1.1.8 root 1557: }
1558:
1.1 root 1559: if (regs.spcflags & SPCFLAG_DOTRACE) {
1.1.1.16! root 1560: Exception (9,last_trace_ad,M68000_EXC_SRC_CPU);
1.1 root 1561: }
1.1.1.8 root 1562:
1.1.1.14 root 1563:
1564: /* Handle the STOP instruction */
1565: if ( regs.spcflags & SPCFLAG_STOP ) {
1566: /* We first test if there's a pending interrupt that would */
1567: /* allow to immediatly leave the STOP state */
1.1.1.15 root 1568: if ( do_specialties_interrupt(true) ) { /* test if there's an interrupt and add pending jitter */
1.1.1.14 root 1569: regs.stopped = 0;
1570: unset_special (SPCFLAG_STOP);
1571: }
1572: #if 0
1573: if (regs.spcflags & SPCFLAG_MFP) /* MFP int */
1574: MFP_CheckPendingInterrupts();
1575:
1576: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) { /* VBL/HBL ints */
1577: int intr = intlev ();
1578: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1579: if (intr != -1 && intr > regs.intmask) {
1.1.1.15 root 1580: Interrupt (intr , true); /* process the interrupt and add pending jitter */
1.1.1.14 root 1581: regs.stopped = 0;
1582: unset_special (SPCFLAG_STOP);
1583: }
1584: }
1585: #endif
1586:
1587: /* No pending int, we have to wait for the next matching int */
1588: while (regs.spcflags & SPCFLAG_STOP) {
1589:
1590: /* Take care of quit event if needed */
1591: if (regs.spcflags & SPCFLAG_BRK)
1592: return 1;
1593:
1594: M68000_AddCycles(4);
1595:
1596: /* It is possible one or more ints happen at the same time */
1597: /* We must process them during the same cpu cycle until the special INT flag is set */
1598: while (PendingInterruptCount<=0 && PendingInterruptFunction) {
1599: /* 1st, we call the interrupt handler */
1600: CALL_VAR(PendingInterruptFunction);
1601:
1602: /* Then we check if this handler triggered an interrupt to process */
1.1.1.15 root 1603: if ( do_specialties_interrupt(false) ) { /* test if there's an interrupt and add non pending jitter */
1.1.1.13 root 1604: regs.stopped = 0;
1605: unset_special (SPCFLAG_STOP);
1.1.1.14 root 1606: break;
1607: }
1608: #if 0
1609: /* Then we check if this handler triggered an MFP int to process */
1610: if (regs.spcflags & SPCFLAG_MFP)
1611: MFP_CheckPendingInterrupts();
1612:
1613: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1614: int intr = intlev ();
1615: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1616: if (intr != -1 && intr > regs.intmask) {
1.1.1.15 root 1617: Interrupt (intr , false); /* process the interrupt and add non pending jitter */
1.1.1.14 root 1618: regs.stopped = 0;
1619: unset_special (SPCFLAG_STOP);
1620: break;
1621: }
1622: }
1623: #endif
1.1.1.6 root 1624: }
1.1 root 1625: }
1626: }
1.1.1.8 root 1627:
1.1.1.14 root 1628:
1.1 root 1629: if (regs.spcflags & SPCFLAG_TRACE)
1630: do_trace ();
1631:
1.1.1.12 root 1632: // if (regs.spcflags & SPCFLAG_DOINT) {
1633: /* [NP] pending int should be processed now, not after the current instr */
1.1.1.14 root 1634: /* so we check for (SPCFLAG_INT | SPCFLAG_DOINT), not just for SPCFLAG_DOINT */
1.1.1.15 root 1635:
1636: if ( do_specialties_interrupt(false) ) { /* test if there's an interrupt and add non pending jitter */
1.1.1.14 root 1637: regs.stopped = 0; /* [NP] useless ? */
1638: }
1639: if (regs.spcflags & SPCFLAG_INT) {
1640: unset_special (SPCFLAG_INT);
1641: set_special (SPCFLAG_DOINT);
1642: }
1643: #if 0
1.1.1.12 root 1644: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1.1.1.6 root 1645: int intr = intlev ();
1.1.1.8 root 1646: /* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */
1.1.1.12 root 1647: // unset_special (SPCFLAG_DOINT);
1648: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1.1.1.6 root 1649: if (intr != -1 && intr > regs.intmask) {
1.1.1.15 root 1650: Interrupt (intr , false); /* call Interrupt() with Pending=false, not necessarily true but harmless */
1.1.1.14 root 1651: regs.stopped = 0; /* [NP] useless ? */
1.1.1.6 root 1652: }
1.1 root 1653: }
1654: if (regs.spcflags & SPCFLAG_INT) {
1655: unset_special (SPCFLAG_INT);
1656: set_special (SPCFLAG_DOINT);
1657: }
1.1.1.8 root 1658:
1659: if (regs.spcflags & SPCFLAG_MFP) { /* Check for MFP interrupts */
1660: MFP_CheckPendingInterrupts();
1661: }
1.1.1.14 root 1662: #endif
1.1.1.8 root 1663:
1.1.1.15 root 1664: if (regs.spcflags & SPCFLAG_DEBUGGER)
1.1.1.16! root 1665: DebugCpu_Check();
1.1.1.15 root 1666:
1.1 root 1667: if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1.1.1.8 root 1668: unset_special(SPCFLAG_MODE_CHANGE);
1.1 root 1669: return 1;
1670: }
1.1.1.8 root 1671:
1.1 root 1672: return 0;
1673: }
1674:
1.1.1.3 root 1675:
1.1 root 1676: /* It's really sad to have two almost identical functions for this, but we
1677: do it all for performance... :( */
1678: static void m68k_run_1 (void)
1679: {
1680: #ifdef DEBUG_PREFETCH
1681: uae_u8 saved_bytes[20];
1682: uae_u16 *oldpcp;
1683: #endif
1.1.1.8 root 1684:
1685: for (;;) {
1.1 root 1686: int cycles;
1687: uae_u32 opcode = get_iword_prefetch (0);
1.1.1.8 root 1688:
1.1 root 1689: #ifdef DEBUG_PREFETCH
1690: if (get_ilong (0) != do_get_mem_long (®s.prefetch)) {
1691: fprintf (stderr, "Prefetch differs from memory.\n");
1692: debugging = 1;
1693: return;
1694: }
1695: oldpcp = regs.pc_p;
1696: memcpy (saved_bytes, regs.pc_p, 20);
1697: #endif
1698:
1699: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.15 root 1700: if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
1701: {
1702: int FrameCycles, HblCounterVideo, LineCycles;
1703:
1704: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
1705:
1706: LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
1.1.1.12 root 1707: m68k_disasm(stderr, m68k_getpc (), NULL, 1);
1.1.1.15 root 1708: }
1.1 root 1709:
1710: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1711: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1712: #if COUNT_INSTRS == 2
1713: if (table68k[opcode].handler != -1)
1714: instrcount[table68k[opcode].handler]++;
1715: #elif COUNT_INSTRS == 1
1716: instrcount[opcode]++;
1717: #endif
1.1.1.2 root 1718:
1.1.1.12 root 1719: /* In case of a Bus Error, we need the PC of the instruction that caused */
1720: /* the error to build the exception stack frame */
1721: BusErrorPC = m68k_getpc();
1722:
1.1.1.6 root 1723: cycles = (*cpufunctbl[opcode])(opcode);
1724:
1.1 root 1725: #ifdef DEBUG_PREFETCH
1726: if (memcmp (saved_bytes, oldpcp, 20) != 0) {
1.1.1.12 root 1727: fprintf (stderr, "Self-modifying code detected %x.\n" , m68k_getpc() );
1.1 root 1728: set_special (SPCFLAG_BRK);
1729: debugging = 1;
1730: }
1731: #endif
1.1.1.2 root 1732:
1.1.1.16! root 1733: if (bDspEnabled)
! 1734: Cycles_SetCounter(CYCLES_COUNTER_CPU, 0); /* to measure the total number of cycles spent in the cpu */
! 1735:
1.1.1.12 root 1736: M68000_AddCyclesWithPairing(cycles);
1.1.1.13 root 1737: if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1738: /* Add some extra cycles to simulate a wait state */
1739: unset_special(SPCFLAG_EXTRA_CYCLES);
1740: M68000_AddCycles(nWaitStateCycles);
1741: nWaitStateCycles = 0;
1742: }
1743:
1.1.1.14 root 1744: #if 0
1745: while (PendingInterruptCount <= 0 && PendingInterruptFunction)
1.1.1.8 root 1746: CALL_VAR(PendingInterruptFunction);
1.1.1.14 root 1747: #else
1748: /* We can have several interrupts at the same time before the next CPU instruction */
1749: /* We must check for pending interrupt and call do_specialties_interrupt() only */
1750: /* if the cpu is not in the STOP state. Else, the int could be acknowledged now */
1751: /* and prevent exiting the STOP state when calling do_specialties() after. */
1752: /* For performance, we first test PendingInterruptCount, then regs.spcflags */
1753: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) && ( ( regs.spcflags & SPCFLAG_STOP ) == 0 ) )
1754: {
1755: CALL_VAR(PendingInterruptFunction); /* call the interrupt handler */
1.1.1.15 root 1756: do_specialties_interrupt(false); /* test if there's an mfp/video interrupt and add non pending jitter */
1.1.1.14 root 1757: #if 0
1758: if ( regs.spcflags & ( SPCFLAG_MFP | SPCFLAG_INT ) ) { /* only check mfp/video interrupts */
1759: if (do_specialties ()) /* check if this latest int has higher priority */
1760: return;
1761: }
1762: #endif
1763: }
1.1.1.15 root 1764: #endif
1.1.1.14 root 1765:
1766: if (regs.spcflags) {
1767: if (do_specialties ())
1768: return;
1769: }
1770:
1.1.1.15 root 1771: /* Run DSP 56k code if necessary */
1772: if (bDspEnabled) {
1.1.1.16! root 1773: DSP_Run( Cycles_GetCounter(CYCLES_COUNTER_CPU) );
1.1.1.15 root 1774: }
1.1 root 1775: }
1776: }
1777:
1778:
1779: /* Same thing, but don't use prefetch to get opcode. */
1780: static void m68k_run_2 (void)
1781: {
1.1.1.8 root 1782: for (;;) {
1.1 root 1783: int cycles;
1784: uae_u32 opcode = get_iword (0);
1785:
1786: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.15 root 1787: if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
1788: {
1789: int FrameCycles, HblCounterVideo, LineCycles;
1790:
1791: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
1792:
1793: LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
1.1.1.12 root 1794: m68k_disasm(stderr, m68k_getpc (), NULL, 1);
1.1.1.15 root 1795: }
1.1.1.12 root 1796:
1.1 root 1797: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1798: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1799: #if COUNT_INSTRS == 2
1800: if (table68k[opcode].handler != -1)
1801: instrcount[table68k[opcode].handler]++;
1802: #elif COUNT_INSTRS == 1
1803: instrcount[opcode]++;
1804: #endif
1.1.1.2 root 1805:
1.1.1.6 root 1806: cycles = (*cpufunctbl[opcode])(opcode);
1807:
1.1.1.16! root 1808: if (bDspEnabled)
! 1809: Cycles_SetCounter(CYCLES_COUNTER_CPU, 0); /* to measure the total number of cycles spent in the cpu */
! 1810:
1.1.1.8 root 1811: M68000_AddCycles(cycles);
1.1.1.13 root 1812: if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1813: /* Add some extra cycles to simulate a wait state */
1814: unset_special(SPCFLAG_EXTRA_CYCLES);
1815: M68000_AddCycles(nWaitStateCycles);
1816: nWaitStateCycles = 0;
1817: }
1818:
1.1.1.12 root 1819: while (PendingInterruptCount <= 0 && PendingInterruptFunction)
1.1.1.8 root 1820: CALL_VAR(PendingInterruptFunction);
1821:
1.1 root 1822: if (regs.spcflags) {
1823: if (do_specialties ())
1824: return;
1825: }
1.1.1.15 root 1826:
1827: /* Run DSP 56k code if necessary */
1828: if (bDspEnabled) {
1.1.1.16! root 1829: DSP_Run( Cycles_GetCounter(CYCLES_COUNTER_CPU) );
1.1.1.15 root 1830: }
1.1 root 1831: }
1832: }
1833:
1834:
1835: void m68k_go (int may_quit)
1836: {
1.1.1.8 root 1837: static int in_m68k_go = 0;
1838:
1.1 root 1839: if (in_m68k_go || !may_quit) {
1840: write_log ("Bug! m68k_go is not reentrant.\n");
1841: abort ();
1842: }
1843:
1844: in_m68k_go++;
1.1.1.8 root 1845: while (!(regs.spcflags & SPCFLAG_BRK)) {
1.1.1.12 root 1846: if(currprefs.cpu_compatible)
1.1.1.2 root 1847: m68k_run_1();
1848: else
1849: m68k_run_2();
1.1 root 1850: }
1.1.1.8 root 1851: unset_special(SPCFLAG_BRK);
1.1 root 1852: in_m68k_go--;
1853: }
1854:
1.1.1.8 root 1855:
1856: /*
1.1 root 1857: static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1858: {
1859: uae_u32 opcode, val;
1860: struct instr *dp;
1861:
1862: opcode = get_iword_1(0);
1863: last_op_for_exception_3 = opcode;
1864: m68kpc_offset = 2;
1865:
1.1.1.6 root 1866: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1867: opcode = 0x4AFC;
1868: }
1869: dp = table68k + opcode;
1870:
1871: if (dp->suse) {
1872: if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) {
1.1.1.16! root 1873: Exception (3, 0,M68000_EXC_SRC_CPU);
1.1 root 1874: return;
1875: }
1876: }
1877: if (dp->duse) {
1878: if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) {
1.1.1.16! root 1879: Exception (3, 0,M68000_EXC_SRC_CPU);
1.1 root 1880: return;
1881: }
1882: }
1883: }
1.1.1.8 root 1884: */
1885:
1.1 root 1886:
1887: void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1888: {
1.1.1.11 root 1889: static const char * const ccnames[] =
1.1.1.8 root 1890: { "T ","F ","HI","LS","CC","CS","NE","EQ",
1891: "VC","VS","PL","MI","GE","LT","GT","LE" };
1892:
1.1 root 1893: uaecptr newpc = 0;
1894: m68kpc_offset = addr - m68k_getpc ();
1895: while (cnt-- > 0) {
1896: char instrname[20],*ccpt;
1897: int opwords;
1898: uae_u32 opcode;
1.1.1.11 root 1899: const struct mnemolookup *lookup;
1.1 root 1900: struct instr *dp;
1901: fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset);
1902: for (opwords = 0; opwords < 5; opwords++){
1903: fprintf (f, "%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1904: }
1905: opcode = get_iword_1 (m68kpc_offset);
1906: m68kpc_offset += 2;
1.1.1.6 root 1907: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1908: opcode = 0x4AFC;
1909: }
1910: dp = table68k + opcode;
1911: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1912: ;
1913:
1914: strcpy (instrname, lookup->name);
1915: ccpt = strstr (instrname, "cc");
1916: if (ccpt != 0) {
1917: strncpy (ccpt, ccnames[dp->cc], 2);
1918: }
1919: fprintf (f, "%s", instrname);
1920: switch (dp->size){
1921: case sz_byte: fprintf (f, ".B "); break;
1922: case sz_word: fprintf (f, ".W "); break;
1923: case sz_long: fprintf (f, ".L "); break;
1924: default: fprintf (f, " "); break;
1925: }
1926:
1927: if (dp->suse) {
1928: newpc = m68k_getpc () + m68kpc_offset;
1929: newpc += ShowEA (f, dp->sreg, dp->smode, dp->size, 0);
1930: }
1931: if (dp->suse && dp->duse)
1932: fprintf (f, ",");
1933: if (dp->duse) {
1934: newpc = m68k_getpc () + m68kpc_offset;
1935: newpc += ShowEA (f, dp->dreg, dp->dmode, dp->size, 0);
1936: }
1937: if (ccpt != 0) {
1938: if (cctrue(dp->cc))
1.1.1.5 root 1939: fprintf (f, " == %08lx (TRUE)", (long)newpc);
1.1 root 1940: else
1.1.1.5 root 1941: fprintf (f, " == %08lx (FALSE)", (long)newpc);
1.1 root 1942: } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1.1.1.5 root 1943: fprintf (f, " == %08lx", (long)newpc);
1.1 root 1944: fprintf (f, "\n");
1945: }
1946: if (nextpc)
1947: *nextpc = m68k_getpc () + m68kpc_offset;
1948: }
1949:
1950: void m68k_dumpstate (FILE *f, uaecptr *nextpc)
1951: {
1952: int i;
1953: for (i = 0; i < 8; i++){
1.1.1.5 root 1954: fprintf (f, "D%d: %08lx ", i, (long)m68k_dreg(regs, i));
1.1 root 1955: if ((i & 3) == 3) fprintf (f, "\n");
1956: }
1957: for (i = 0; i < 8; i++){
1.1.1.5 root 1958: fprintf (f, "A%d: %08lx ", i, (long)m68k_areg(regs, i));
1.1 root 1959: if ((i & 3) == 3) fprintf (f, "\n");
1960: }
1961: if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1962: if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1963: if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1964: fprintf (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1.1.1.5 root 1965: (long)regs.usp,(long)regs.isp,(long)regs.msp,(long)regs.vbr);
1.1 root 1966: fprintf (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1967: regs.t1, regs.t0, regs.s, regs.m,
1968: GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1969: for (i = 0; i < 8; i++){
1970: fprintf (f, "FP%d: %g ", i, regs.fp[i]);
1971: if ((i & 3) == 3) fprintf (f, "\n");
1972: }
1973: fprintf (f, "N=%d Z=%d I=%d NAN=%d\n",
1974: (regs.fpsr & 0x8000000) != 0,
1975: (regs.fpsr & 0x4000000) != 0,
1976: (regs.fpsr & 0x2000000) != 0,
1977: (regs.fpsr & 0x1000000) != 0);
1.1.1.12 root 1978: if (currprefs.cpu_compatible)
1.1 root 1979: fprintf (f, "prefetch %08lx\n", (unsigned long)do_get_mem_long(®s.prefetch));
1980:
1981: m68k_disasm (f, m68k_getpc (), nextpc, 1);
1982: if (nextpc)
1.1.1.5 root 1983: fprintf (f, "next PC: %08lx\n", (long)*nextpc);
1.1 root 1984: }
1.1.1.12 root 1985:
1986:
1987: /*
1988:
1989: The routines below take dividend and divisor as parameters.
1990: They return 0 if division by zero, or exact number of cycles otherwise.
1991:
1992: The number of cycles returned assumes a register operand.
1993: Effective address time must be added if memory operand.
1994:
1995: For 68000 only (not 68010, 68012, 68020, etc).
1996: Probably valid for 68008 after adding the extra prefetch cycle.
1997:
1998:
1999: Best and worst cases are for register operand:
2000: (Note the difference with the documented range.)
2001:
2002:
2003: DIVU:
2004:
2005: Overflow (always): 10 cycles.
2006: Worst case: 136 cycles.
2007: Best case: 76 cycles.
2008:
2009:
2010: DIVS:
2011:
2012: Absolute overflow: 16-18 cycles.
2013: Signed overflow is not detected prematurely.
2014:
2015: Worst case: 156 cycles.
2016: Best case without signed overflow: 122 cycles.
2017: Best case with signed overflow: 120 cycles
2018:
2019:
2020: */
2021:
2022:
2023: //
2024: // DIVU
2025: // Unsigned division
2026: //
2027:
2028: STATIC_INLINE int getDivu68kCycles_2 (uae_u32 dividend, uae_u16 divisor)
2029: {
2030: int mcycles;
2031: uae_u32 hdivisor;
2032: int i;
2033:
2034: if (divisor == 0)
2035: return 0;
2036:
2037: // Overflow
2038: if ((dividend >> 16) >= divisor)
2039: return (mcycles = 5) * 2;
2040:
2041: mcycles = 38;
2042: hdivisor = divisor << 16;
2043:
2044: for (i = 0; i < 15; i++) {
2045: uae_u32 temp;
2046: temp = dividend;
2047:
2048: dividend <<= 1;
2049:
2050: // If carry from shift
2051: if ((uae_s32)temp < 0)
2052: dividend -= hdivisor;
2053: else {
2054: mcycles += 2;
2055: if (dividend >= hdivisor) {
2056: dividend -= hdivisor;
2057: mcycles--;
2058: }
2059: }
2060: }
2061: return mcycles * 2;
2062: }
2063: int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor)
2064: {
2065: int v = getDivu68kCycles_2 (dividend, divisor) - 4;
2066: // write_log ("U%d ", v);
2067: return v;
2068: }
2069:
2070: //
2071: // DIVS
2072: // Signed division
2073: //
2074:
2075: STATIC_INLINE int getDivs68kCycles_2 (uae_s32 dividend, uae_s16 divisor)
2076: {
2077: int mcycles;
2078: uae_u32 aquot;
2079: int i;
2080:
2081: if (divisor == 0)
2082: return 0;
2083:
2084: mcycles = 6;
2085:
2086: if (dividend < 0)
2087: mcycles++;
2088:
2089: // Check for absolute overflow
2090: if (((uae_u32)abs (dividend) >> 16) >= (uae_u16)abs (divisor))
2091: return (mcycles + 2) * 2;
2092:
2093: // Absolute quotient
2094: aquot = (uae_u32) abs (dividend) / (uae_u16)abs (divisor);
2095:
2096: mcycles += 55;
2097:
2098: if (divisor >= 0) {
2099: if (dividend >= 0)
2100: mcycles--;
2101: else
2102: mcycles++;
2103: }
2104:
2105: // Count 15 msbits in absolute of quotient
2106:
2107: for (i = 0; i < 15; i++) {
2108: if ((uae_s16)aquot >= 0)
2109: mcycles++;
2110: aquot <<= 1;
2111: }
2112:
2113: return mcycles * 2;
2114: }
2115: int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor)
2116: {
2117: int v = getDivs68kCycles_2 (dividend, divisor) - 4;
2118: // write_log ("S%d ", v);
2119: return v;
2120: }
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