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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation
5: *
6: * (c) 1995 Bernd Schmidt
1.1.1.2 root 7: *
8: * Adaptation to Hatari by Thomas Huth
9: *
1.1.1.6 root 10: * This file is distributed under the GNU Public License, version 2 or at
11: * your option any later version. Read the file gpl.txt for details.
1.1 root 12: */
1.1.1.12 root 13:
14:
15: /* 2007/11/12 [NP] Add HATARI_TRACE_CPU_DISASM. */
16: /* 2007/11/15 [NP] In MakeFromSR, writes to m and t0 should be ignored and set to 0 if cpu < 68020 */
17: /* 2007/11/26 [NP] We set BusErrorPC in m68k_run_1 instead of M68000_BusError, else the BusErrorPC */
18: /* will not point to the opcode that generated the bus error. */
19: /* Huge debug/work on Exceptions 2/3 stack frames, result is more accurate and */
20: /* allow to pass the very tricky Transbeauce 2 Demo's protection. */
21: /* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */
22: /* Cwik, [email protected]). */
23: /* 2007/12/06 [NP] The PC stored in the stack frame for the bus error is complex to emulate, */
24: /* because it doesn't necessarily point to the next instruction after the one that */
25: /* triggered the bus error. In the case of the Transbeauce 2 Demo, after */
26: /* 'move.l $0.w,$24.w', PC is incremented of 4 bytes, not 6, and stored in the */
27: /* stack. Special case to decrement PC of 2 bytes if opcode is '21f8'. */
28: /* This should be fixed with a real model. */
29: /* 2007/12/07 [NP] If Trace is enabled and a group 2 exception occurs (such as CHK), the trace */
30: /* handler should be called after the group 2's handler. If a bus error, address */
31: /* error or illegal occurs while Trace is enabled, the trace handler should not be */
32: /* called after this instruction (Transbeauce 2 Demo, Phaleon Demo). */
33: /* This means that if a CHK is executed while trace bit was set, we must set PC */
34: /* to CHK handler, turn trace off in the internal SR, but we must still call the */
35: /* trace handler one last time with the PC set to the CHK's handler (even if */
36: /* trace mode is internally turned off while processing an exception). Once trace */
37: /* handler is finished (RTE), we return to the CHK's handler. */
38: /* This is true for DIV BY 0, CHK, TRAPV and TRAP. */
39: /* Backport exception_trace() from WinUAE to handle this behaviour (used in */
40: /* Transbeauce 2 demo). */
41: /* 2007/12/09 [NP] 'dc.w $a' should not be used to call 'OpCode_SysInit' but should give an illegal*/
42: /* instruction (Transbeauce 2 demo). */
43: /* Instead of always replacing the illegal instructions $8, $a and $c by the */
44: /* 3 functions required for HD emulation, we now do it in cart.c only if the */
45: /* built-in cartridge image is loaded. */
46: /* YEAH! Hatari is now the first emulator to pass the Transbeauce 2 protection :) */
47: /* 2007/12/18 [NP] More precise timings for HBL, VBL and MFP interrupts. On ST, these interrupts */
48: /* are taking 56 cycles instead of the 44 cycles in the 68000's documentation. */
49: /* 2007/12/24 [NP] If an interrupt (HBL, VBL) is pending after intruction 'n' was processed, the */
50: /* exception should be called before instr. 'n+1' is processed, not after (else the*/
51: /* interrupt's handler is delayed by one 68000's instruction, which could break */
52: /* some demos with too strict timings) (ACF's Demo Main Menu). */
53: /* We call the interrupt if ( SPCFLAG_INT | SPCFLAG_DOINT ) is set, not only if */
54: /* SPCFLAG_DOINT is set (as it was already the case when handling 'STOP'). */
55: /* 2007/12/25 [NP] FIXME When handling exceptions' cycles, using nr >= 64 to determine if this is */
56: /* an MFP exception could be wrong if the MFP VR was set to another value than the */
57: /* default $40 (this could be a problem with programs requiring a precise cycles */
58: /* calculation while changing VR, but no such programs were encountered so far). */
1.1.1.13 root 59: /* -> FIXED, see 2008/10/05 */
60: /* 2008/04/17 [NP] In m68k_run_1/m68k_run_2, add the wait state cycles before testing if content */
61: /* of PendingInterruptCount is <= 0 (else the int could happen a few cycles earlier*/
62: /* than expected in some rare cases (reading $fffa21 in BIG Demo Screen 1)). */
63: /* 2008/09/14 [NP] Add the value of the new PC in the exception's log. */
64: /* 2008/09/14 [NP] Correct cycles for TRAP are 34 not 38 (4 more cycles were counted because cpuemu*/
65: /* returns 4 and Exception() adds 34) (Phaleon / Illusion Demo by Next). */
66: /* FIXME : Others exception cycles may be wrong too. */
67: /* 2008/10/05 [NP] Add a parameter 'ExceptionSource' to Exception(). This allows to know the source*/
68: /* of the exception (video, mfp, cpu) and properly handle MFP interrupts. Since */
69: /* it's possible to change the vector base in $fffa17, MFP int vectors can overlap */
70: /* the 'normal' 68000 ones and the exception number is not enough to decide. */
71: /* We need ExceptionSource to remove the ambiguity. */
72: /* Fix High Fidelity Dreams by Aura which sets MFP vector base to $c0 instead of */
73: /* $100. In that case, timer B int becomes exception nr 56 and conflicts with the */
74: /* 'MMU config error' exception, which takes 4 cycles instead of 56 cycles for MFP.*/
75: /* 2008/11/18 [NP] In 'do_specialties()', when the cpu is in the STOP state, we must test all */
76: /* possible int handlers while PendingInterruptCount <= 0 without increasing the */
77: /* cpu cycle counter. In the case where both an MFP int and an HBL occur at the */
1.1.1.14 root 78: /* same time for example, the HBL was delayed by 4 cycles if no MFP exception */
1.1.1.13 root 79: /* was triggered, which was wrong (this happened mainly with the TOS timer D that */
80: /* expires very often). Such precision is required for very recent hardscroll */
81: /* techniques that use 'stop' to stay in sync with the video shifter. */
1.1.1.14 root 82: /* 2008/11/23 [NP] In 'do_specialties()', when in STOP state, we must first test for a pending */
83: /* interrupt that would exit the STOP state immediatly, without doing a 'while' */
84: /* loop until 'SPCFLAG_INT' or 'SPCFLAG_DOINT' are set. */
85: /* 2008/11/29 [NP] Call 'InterruptAddJitter()' when a video interrupt happens to precisely emulate */
86: /* the jitter happening on the Atari (see video.c for the jitter patterns). */
87: /* FIXME : Pattern is not always correct when handling pending interrupt in STOP */
88: /* state, but this should be harmless as no program has been found using this. */
89: /* 2008/12/05 [NP] On Atari it takes 56 cycles to process an interrupt. During that time, a higher */
90: /* level interrupt could happen and we must execute it before the previous int */
91: /* (see m68k_run_1()). */
92: /* This is the case for the VBL which can interrupt the last HBL of a screen */
93: /* (end of line 312) at various point (from 0 to 8 cycles). */
94: /* This fixes the fullscreen tunnel in Suretrip 49% by Checkpoint, which uses a */
95: /* really buggy vbl/hbl combination, even on a real ST. Also fixes sample sound */
96: /* in Swedish New Year's TCB screen. */
97: /* 2008/12/11 [NP] Extract interrupt handling from do_specialties() in do_specialties_interrupt() */
98: /* and factorize some code. In m68k_run_1 when testing for multiple interrupts at */
99: /* the same time, call do_specialties_interrupt() to check only the special flags */
100: /* related to interrupts (MFP and video) (else, this caused problem when the TRACE */
101: /* flag was set). */
102: /* 2008/12/14 [NP] In m68k_run_1(), we should check for simultaneous ints only if the cpu is not */
103: /* in the STOP state after the last instruction was executed. Else, the call to */
104: /* do_specialties_interrupt() could acknowledge the interrupt and we would never */
105: /* exit the STOP state in do_specialties() just after (the problem can happen if */
106: /* the TOS timer D expires just at the same time as the STOP instruction). */
107: /* Fix regression since 2008/12/11 in the hidden screen from ULM in Oh Crickey... */
108: /* 2008/12/20 [NP] In m68k_run_1(), when checking interrupts and STOP mode, we should test */
109: /* PendingInterruptCount before regs.spcflags to have a faster evaluation of the */
110: /* 'while' condition (PendingInterruptCount <= 0 is true less often than STOP==0) */
1.1.1.17 root 111: /* 2011/04/29 [NP] In Exception(), check the new PC is not on odd address ; raise an address error */
112: /* exception if it's the case. */
1.1.1.12 root 113:
114:
1.1.1.15 root 115: const char NewCpu_fileid[] = "Hatari newcpu.c : " __DATE__ " " __TIME__;
1.1 root 116:
117: #include "sysdeps.h"
118: #include "hatari-glue.h"
119: #include "maccess.h"
120: #include "memory.h"
121: #include "newcpu.h"
1.1.1.16 root 122: #include "main.h"
123: #include "m68000.h"
124: #include "cycInt.h"
125: #include "mfp.h"
126: #include "tos.h"
127: #include "vdi.h"
128: #include "cart.h"
129: #include "dialog.h"
130: #include "bios.h"
131: #include "xbios.h"
1.1.1.17 root 132: #include "screen.h"
1.1.1.16 root 133: #include "video.h"
134: #include "options.h"
135: #include "dsp.h"
136: #include "log.h"
137: #include "debugui.h"
138: #include "debugcpu.h"
1.1.1.17 root 139: #include "68kDisass.h"
1.1 root 140:
1.1.1.12 root 141: //#define DEBUG_PREFETCH
1.1 root 142:
143: struct flag_struct regflags;
144:
145: /* Opcode of faulting instruction */
146: uae_u16 last_op_for_exception_3;
147: /* PC at fault time */
148: uaecptr last_addr_for_exception_3;
149: /* Address that generated the exception */
150: uaecptr last_fault_for_exception_3;
151:
1.1.1.11 root 152: const int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
153: const int imm8_table[] = { 8,1,2,3,4,5,6,7 };
1.1 root 154:
155: int movem_index1[256];
156: int movem_index2[256];
157: int movem_next[256];
158:
159: int fpp_movem_index1[256];
160: int fpp_movem_index2[256];
161: int fpp_movem_next[256];
162:
163: cpuop_func *cpufunctbl[65536];
164:
1.1.1.12 root 165: int OpcodeFamily;
1.1.1.16 root 166: int BusCyclePenalty = 0;
1.1.1.6 root 167:
1.1 root 168: #define COUNT_INSTRS 0
169:
170: #if COUNT_INSTRS
171: static unsigned long int instrcount[65536];
172: static uae_u16 opcodenums[65536];
173:
174: static int compfn (const void *el1, const void *el2)
175: {
176: return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
177: }
178:
179: static char *icountfilename (void)
180: {
181: char *name = getenv ("INSNCOUNT");
182: if (name)
183: return name;
184: return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
185: }
186:
187: void dump_counts (void)
188: {
189: FILE *f = fopen (icountfilename (), "w");
190: unsigned long int total;
191: int i;
192:
193: write_log ("Writing instruction count file...\n");
194: for (i = 0; i < 65536; i++) {
195: opcodenums[i] = i;
196: total += instrcount[i];
197: }
198: qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
199:
200: fprintf (f, "Total: %lu\n", total);
201: for (i=0; i < 65536; i++) {
202: unsigned long int cnt = instrcount[opcodenums[i]];
203: struct instr *dp;
204: struct mnemolookup *lookup;
205: if (!cnt)
206: break;
207: dp = table68k + opcodenums[i];
208: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
209: ;
210: fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
211: }
212: fclose (f);
213: }
214: #else
215: void dump_counts (void)
216: {
217: }
218: #endif
219:
220:
221: static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM;
222:
223: static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
224: {
1.1.1.6 root 225: op_illg (opcode);
1.1 root 226: return 4;
227: }
228:
1.1.1.4 root 229:
230: void build_cpufunctbl(void)
1.1 root 231: {
232: int i;
233: unsigned long opcode;
1.1.1.12 root 234: const struct cputbl *tbl = (currprefs.cpu_level == 4 ? op_smalltbl_0_ff
235: : currprefs.cpu_level == 3 ? op_smalltbl_1_ff
236: : currprefs.cpu_level == 2 ? op_smalltbl_2_ff
237: : currprefs.cpu_level == 1 ? op_smalltbl_3_ff
238: : ! currprefs.cpu_compatible ? op_smalltbl_4_ff
1.1.1.11 root 239: : op_smalltbl_5_ff);
1.1 root 240:
1.1.1.10 root 241: Log_Printf(LOG_DEBUG, "Building CPU function table (%d %d %d).\n",
1.1.1.12 root 242: currprefs.cpu_level, currprefs.cpu_compatible, currprefs.address_space_24);
1.1 root 243:
244: for (opcode = 0; opcode < 65536; opcode++)
1.1.1.6 root 245: cpufunctbl[opcode] = op_illg_1;
1.1 root 246: for (i = 0; tbl[i].handler != NULL; i++) {
247: if (! tbl[i].specific)
1.1.1.6 root 248: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 249: }
250: for (opcode = 0; opcode < 65536; opcode++) {
251: cpuop_func *f;
252:
1.1.1.12 root 253: if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > currprefs.cpu_level)
1.1 root 254: continue;
255:
256: if (table68k[opcode].handler != -1) {
1.1.1.6 root 257: f = cpufunctbl[table68k[opcode].handler];
1.1 root 258: if (f == op_illg_1)
259: abort();
1.1.1.6 root 260: cpufunctbl[opcode] = f;
1.1 root 261: }
262: }
263: for (i = 0; tbl[i].handler != NULL; i++) {
264: if (tbl[i].specific)
1.1.1.6 root 265: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 266: }
267: }
268:
269:
270:
271: void init_m68k (void)
272: {
273: int i;
274:
275: for (i = 0 ; i < 256 ; i++) {
276: int j;
277: for (j = 0 ; j < 8 ; j++) {
278: if (i & (1 << j)) break;
279: }
280: movem_index1[i] = j;
281: movem_index2[i] = 7-j;
282: movem_next[i] = i & (~(1 << j));
283: }
284: for (i = 0 ; i < 256 ; i++) {
285: int j;
286: for (j = 7 ; j >= 0 ; j--) {
287: if (i & (1 << j)) break;
288: }
289: fpp_movem_index1[i] = 7-j;
290: fpp_movem_index2[i] = j;
291: fpp_movem_next[i] = i & (~(1 << j));
292: }
293: #if COUNT_INSTRS
294: {
295: FILE *f = fopen (icountfilename (), "r");
296: memset (instrcount, 0, sizeof instrcount);
297: if (f) {
298: uae_u32 opcode, count, total;
299: char name[20];
300: write_log ("Reading instruction count file...\n");
301: fscanf (f, "Total: %lu\n", &total);
302: while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
303: instrcount[opcode] = count;
304: }
305: fclose(f);
306: }
307: }
308: #endif
309: write_log ("Building CPU table for configuration: 68");
1.1.1.12 root 310: if (currprefs.address_space_24 && currprefs.cpu_level > 1)
1.1 root 311: write_log ("EC");
1.1.1.12 root 312: switch (currprefs.cpu_level) {
1.1 root 313: case 1:
314: write_log ("010");
315: break;
316: case 2:
317: write_log ("020");
318: break;
319: case 3:
320: write_log ("020/881");
321: break;
322: case 4:
323: /* Who is going to miss the MMU anyway...? :-) */
324: write_log ("040");
325: break;
326: default:
327: write_log ("000");
328: break;
329: }
1.1.1.12 root 330: if (currprefs.cpu_compatible)
1.1 root 331: write_log (" (compatible mode)");
332: write_log ("\n");
1.1.1.7 root 333:
1.1 root 334: read_table68k ();
335: do_merges ();
336:
1.1.1.10 root 337: Log_Printf(LOG_DEBUG, "%d CPU functions\n", nr_cpuop_funcs);
1.1 root 338:
339: build_cpufunctbl ();
340: }
341:
1.1.1.4 root 342:
1.1.1.8 root 343: /* not used ATM:
1.1 root 344: static struct regstruct regs_backup[16];
345: static int backup_pointer = 0;
1.1.1.10 root 346: struct regstruct lastint_regs;
347: int lastint_no;
1.1.1.8 root 348: */
1.1.1.10 root 349: struct regstruct regs;
1.1 root 350: static long int m68kpc_offset;
1.1.1.10 root 351:
1.1 root 352:
353: #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
354: #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
355: #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
356:
357: uae_s32 ShowEA (FILE *f, int reg, amodes mode, wordsizes size, char *buf)
358: {
359: uae_u16 dp;
360: uae_s8 disp8;
361: uae_s16 disp16;
362: int r;
363: uae_u32 dispreg;
364: uaecptr addr;
365: uae_s32 offset = 0;
366: char buffer[80];
367:
368: switch (mode){
369: case Dreg:
370: sprintf (buffer,"D%d", reg);
371: break;
372: case Areg:
373: sprintf (buffer,"A%d", reg);
374: break;
375: case Aind:
376: sprintf (buffer,"(A%d)", reg);
377: break;
378: case Aipi:
379: sprintf (buffer,"(A%d)+", reg);
380: break;
381: case Apdi:
382: sprintf (buffer,"-(A%d)", reg);
383: break;
384: case Ad16:
385: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
386: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
387: sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
388: (unsigned long)addr);
389: break;
390: case Ad8r:
391: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
392: disp8 = dp & 0xFF;
393: r = (dp & 0x7000) >> 12;
394: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
395: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
396: dispreg <<= (dp >> 9) & 3;
397:
398: if (dp & 0x100) {
399: uae_s32 outer = 0, disp = 0;
400: uae_s32 base = m68k_areg(regs,reg);
401: char name[10];
402: sprintf (name,"A%d, ",reg);
403: if (dp & 0x80) { base = 0; name[0] = 0; }
404: if (dp & 0x40) dispreg = 0;
405: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
406: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
407: base += disp;
408:
409: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
410: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
411:
412: if (!(dp & 4)) base += dispreg;
413: if (dp & 3) base = get_long (base);
414: if (dp & 4) base += dispreg;
415:
416: addr = base + outer;
417: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
418: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
419: 1 << ((dp >> 9) & 3),
1.1.1.5 root 420: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 421: } else {
422: addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
423: sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
424: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
425: 1 << ((dp >> 9) & 3), disp8,
426: (unsigned long)addr);
427: }
428: break;
429: case PC16:
430: addr = m68k_getpc () + m68kpc_offset;
431: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
432: addr += (uae_s16)disp16;
433: sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
434: break;
435: case PC8r:
436: addr = m68k_getpc () + m68kpc_offset;
437: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
438: disp8 = dp & 0xFF;
439: r = (dp & 0x7000) >> 12;
440: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
441: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
442: dispreg <<= (dp >> 9) & 3;
443:
444: if (dp & 0x100) {
445: uae_s32 outer = 0,disp = 0;
446: uae_s32 base = addr;
447: char name[10];
448: sprintf (name,"PC, ");
449: if (dp & 0x80) { base = 0; name[0] = 0; }
450: if (dp & 0x40) dispreg = 0;
451: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
452: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
453: base += disp;
454:
455: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
456: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
457:
458: if (!(dp & 4)) base += dispreg;
459: if (dp & 3) base = get_long (base);
460: if (dp & 4) base += dispreg;
461:
462: addr = base + outer;
463: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
464: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
465: 1 << ((dp >> 9) & 3),
1.1.1.5 root 466: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 467: } else {
468: addr += (uae_s32)((uae_s8)disp8) + dispreg;
469: sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
470: (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
471: disp8, (unsigned long)addr);
472: }
473: break;
474: case absw:
475: sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
476: m68kpc_offset += 2;
477: break;
478: case absl:
479: sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
480: m68kpc_offset += 4;
481: break;
482: case imm:
483: switch (size){
484: case sz_byte:
485: sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
486: m68kpc_offset += 2;
487: break;
488: case sz_word:
489: sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
490: m68kpc_offset += 2;
491: break;
492: case sz_long:
493: sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
494: m68kpc_offset += 4;
495: break;
496: default:
497: break;
498: }
499: break;
500: case imm0:
501: offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
502: m68kpc_offset += 2;
503: sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
504: break;
505: case imm1:
506: offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
507: m68kpc_offset += 2;
508: sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
509: break;
510: case imm2:
511: offset = (uae_s32)get_ilong_1 (m68kpc_offset);
512: m68kpc_offset += 4;
513: sprintf (buffer,"#$%08lx", (unsigned long)offset);
514: break;
515: case immi:
516: offset = (uae_s32)(uae_s8)(reg & 0xff);
517: sprintf (buffer,"#$%08lx", (unsigned long)offset);
518: break;
519: default:
520: break;
521: }
522: if (buf == 0)
523: fprintf (f, "%s", buffer);
524: else
525: strcat (buf, buffer);
526: return offset;
527: }
528:
1.1.1.8 root 529:
1.1 root 530: /* The plan is that this will take over the job of exception 3 handling -
531: * the CPU emulation functions will just do a longjmp to m68k_go whenever
532: * they hit an odd address. */
1.1.1.8 root 533: #if 0
1.1 root 534: static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
535: {
536: uae_u16 dp;
537: uae_s8 disp8;
538: uae_s16 disp16;
539: int r;
540: uae_u32 dispreg;
541: uaecptr addr;
1.1.1.5 root 542: /*uae_s32 offset = 0;*/
1.1 root 543:
544: switch (mode){
545: case Dreg:
546: *val = m68k_dreg (regs, reg);
547: return 1;
548: case Areg:
549: *val = m68k_areg (regs, reg);
550: return 1;
551:
552: case Aind:
553: case Aipi:
554: addr = m68k_areg (regs, reg);
555: break;
556: case Apdi:
557: addr = m68k_areg (regs, reg);
558: break;
559: case Ad16:
560: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
561: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
562: break;
563: case Ad8r:
564: addr = m68k_areg (regs, reg);
565: d8r_common:
566: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
567: disp8 = dp & 0xFF;
568: r = (dp & 0x7000) >> 12;
569: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
570: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
571: dispreg <<= (dp >> 9) & 3;
572:
573: if (dp & 0x100) {
574: uae_s32 outer = 0, disp = 0;
575: uae_s32 base = addr;
576: if (dp & 0x80) base = 0;
577: if (dp & 0x40) dispreg = 0;
578: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
579: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
580: base += disp;
581:
582: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
583: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
584:
585: if (!(dp & 4)) base += dispreg;
586: if (dp & 3) base = get_long (base);
587: if (dp & 4) base += dispreg;
588:
589: addr = base + outer;
590: } else {
591: addr += (uae_s32)((uae_s8)disp8) + dispreg;
592: }
593: break;
594: case PC16:
595: addr = m68k_getpc () + m68kpc_offset;
596: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
597: addr += (uae_s16)disp16;
598: break;
599: case PC8r:
600: addr = m68k_getpc () + m68kpc_offset;
601: goto d8r_common;
602: case absw:
603: addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
604: m68kpc_offset += 2;
605: break;
606: case absl:
607: addr = get_ilong_1 (m68kpc_offset);
608: m68kpc_offset += 4;
609: break;
610: case imm:
611: switch (size){
612: case sz_byte:
613: *val = get_iword_1 (m68kpc_offset) & 0xff;
614: m68kpc_offset += 2;
615: break;
616: case sz_word:
617: *val = get_iword_1 (m68kpc_offset) & 0xffff;
618: m68kpc_offset += 2;
619: break;
620: case sz_long:
621: *val = get_ilong_1 (m68kpc_offset);
622: m68kpc_offset += 4;
623: break;
624: default:
625: break;
626: }
627: return 1;
628: case imm0:
629: *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
630: m68kpc_offset += 2;
631: return 1;
632: case imm1:
633: *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
634: m68kpc_offset += 2;
635: return 1;
636: case imm2:
637: *val = get_ilong_1 (m68kpc_offset);
638: m68kpc_offset += 4;
639: return 1;
640: case immi:
641: *val = (uae_s32)(uae_s8)(reg & 0xff);
642: return 1;
643: default:
644: addr = 0;
645: break;
646: }
647: if ((addr & 1) == 0)
648: return 1;
649:
650: last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
651: last_fault_for_exception_3 = addr;
652: return 0;
653: }
1.1.1.8 root 654: #endif
655:
1.1 root 656:
657: uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
658: {
659: int reg = (dp >> 12) & 15;
660: uae_s32 regd = regs.regs[reg];
661: if ((dp & 0x800) == 0)
662: regd = (uae_s32)(uae_s16)regd;
663: regd <<= (dp >> 9) & 3;
664: if (dp & 0x100) {
665: uae_s32 outer = 0;
666: if (dp & 0x80) base = 0;
667: if (dp & 0x40) regd = 0;
668:
669: if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
670: if ((dp & 0x30) == 0x30) base += next_ilong();
671:
672: if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
673: if ((dp & 0x3) == 0x3) outer = next_ilong();
674:
675: if ((dp & 0x4) == 0) base += regd;
676: if (dp & 0x3) base = get_long (base);
677: if (dp & 0x4) base += regd;
678:
679: return base + outer;
680: } else {
681: return base + (uae_s32)((uae_s8)dp) + regd;
682: }
683: }
684:
685: uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
686: {
687: int reg = (dp >> 12) & 15;
688: uae_s32 regd = regs.regs[reg];
689: #if 1
690: if ((dp & 0x800) == 0)
691: regd = (uae_s32)(uae_s16)regd;
692: return base + (uae_s8)dp + regd;
693: #else
694: /* Branch-free code... benchmark this again now that
695: * things are no longer inline. */
696: uae_s32 regd16;
697: uae_u32 mask;
698: mask = ((dp & 0x800) >> 11) - 1;
699: regd16 = (uae_s32)(uae_s16)regd;
700: regd16 &= mask;
701: mask = ~mask;
702: base += (uae_s8)dp;
703: regd &= mask;
704: regd |= regd16;
705: return base + regd;
706: #endif
707: }
708:
1.1.1.8 root 709:
710: /* Create the Status Register from the flags */
1.1 root 711: void MakeSR (void)
712: {
713: #if 0
714: assert((regs.t1 & 1) == regs.t1);
715: assert((regs.t0 & 1) == regs.t0);
716: assert((regs.s & 1) == regs.s);
717: assert((regs.m & 1) == regs.m);
718: assert((XFLG & 1) == XFLG);
719: assert((NFLG & 1) == NFLG);
720: assert((ZFLG & 1) == ZFLG);
721: assert((VFLG & 1) == VFLG);
722: assert((CFLG & 1) == CFLG);
723: #endif
724: regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
725: | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
726: | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
727: | GET_CFLG);
728: }
729:
1.1.1.8 root 730:
731: /* Set up the flags from Status Register */
1.1 root 732: void MakeFromSR (void)
733: {
734: int oldm = regs.m;
735: int olds = regs.s;
736:
737: regs.t1 = (regs.sr >> 15) & 1;
738: regs.t0 = (regs.sr >> 14) & 1;
739: regs.s = (regs.sr >> 13) & 1;
740: regs.m = (regs.sr >> 12) & 1;
741: regs.intmask = (regs.sr >> 8) & 7;
742: SET_XFLG ((regs.sr >> 4) & 1);
743: SET_NFLG ((regs.sr >> 3) & 1);
744: SET_ZFLG ((regs.sr >> 2) & 1);
745: SET_VFLG ((regs.sr >> 1) & 1);
746: SET_CFLG (regs.sr & 1);
1.1.1.12 root 747: if (currprefs.cpu_level >= 2) {
1.1 root 748: if (olds != regs.s) {
749: if (olds) {
750: if (oldm)
751: regs.msp = m68k_areg(regs, 7);
752: else
753: regs.isp = m68k_areg(regs, 7);
754: m68k_areg(regs, 7) = regs.usp;
755: } else {
756: regs.usp = m68k_areg(regs, 7);
757: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
758: }
759: } else if (olds && oldm != regs.m) {
760: if (oldm) {
761: regs.msp = m68k_areg(regs, 7);
762: m68k_areg(regs, 7) = regs.isp;
763: } else {
764: regs.isp = m68k_areg(regs, 7);
765: m68k_areg(regs, 7) = regs.msp;
766: }
767: }
768: } else {
1.1.1.12 root 769: /* [NP] If cpu < 68020, m and t0 are ignored and should be set to 0 */
770: regs.t0 = 0;
771: regs.m = 0;
772:
1.1 root 773: if (olds != regs.s) {
774: if (olds) {
775: regs.isp = m68k_areg(regs, 7);
776: m68k_areg(regs, 7) = regs.usp;
777: } else {
778: regs.usp = m68k_areg(regs, 7);
779: m68k_areg(regs, 7) = regs.isp;
780: }
781: }
782: }
783:
1.1.1.8 root 784: /* Pending interrupts can occur again after a write to the SR: */
785: set_special (SPCFLAG_DOINT);
1.1 root 786: if (regs.t1 || regs.t0)
787: set_special (SPCFLAG_TRACE);
788: else
1.1.1.6 root 789: /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
790: SR-modifying instructions (including STOP). */
791: unset_special (SPCFLAG_TRACE);
1.1 root 792: }
793:
1.1.1.5 root 794:
1.1.1.12 root 795: static void exception_trace (int nr)
796: {
797: unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
798: if (regs.t1 && !regs.t0) {
799: /* trace stays pending if exception is div by zero, chk,
800: * trapv or trap #x
801: */
802: if (nr == 5 || nr == 6 || nr == 7 || (nr >= 32 && nr <= 47))
803: set_special (SPCFLAG_DOTRACE);
804: }
805: regs.t1 = regs.t0 = regs.m = 0;
806: }
807:
808:
1.1.1.14 root 809: /*
810: * Compute the number of jitter cycles to add when a video interrupt occurs
811: * (this is specific to the Atari ST)
812: */
813: static void InterruptAddJitter (int Level , int Pending)
814: {
815: int cycles = 0;
816:
817: if ( Level == 2 ) /* HBL */
818: {
819: if ( Pending )
820: cycles = HblJitterArrayPending[ HblJitterIndex ];
821: else
822: cycles = HblJitterArray[ HblJitterIndex ];
823: }
824:
825: else if ( Level == 4 ) /* VBL */
826: {
827: if ( Pending )
828: cycles = VblJitterArrayPending[ VblJitterIndex ];
829: else
830: cycles = VblJitterArray[ VblJitterIndex ];
831: }
832:
833: //fprintf ( stderr , "jitter %d\n" , cycles );
834: //cycles=0;
835: if ( cycles > 0 ) /* no need to call M68000_AddCycles if cycles == 0 */
836: M68000_AddCycles ( cycles );
837: }
838:
839:
1.1.1.13 root 840: /* Handle exceptions. We need a special case to handle MFP exceptions */
841: /* on Atari ST, because it's possible to change the MFP's vector base */
842: /* and get a conflict with 'normal' cpu exceptions. */
843: void Exception(int nr, uaecptr oldpc, int ExceptionSource)
1.1 root 844: {
1.1.1.17 root 845: uae_u32 currpc = m68k_getpc () , newpc;
1.1 root 846:
1.1.1.2 root 847: /*if( nr>=2 && nr<10 ) fprintf(stderr,"Exception (-> %i bombs)!\n",nr);*/
1.1 root 848:
1.1.1.16 root 849: if (ExceptionSource == M68000_EXC_SRC_CPU)
1.1.1.5 root 850: {
1.1.1.17 root 851: if (bVdiAesIntercept && nr == 0x22)
1.1.1.13 root 852: {
1.1.1.17 root 853: /* Intercept VDI & AES exceptions (Trap #2) */
854: if(VDI_AES_Entry())
1.1.1.13 root 855: {
1.1.1.17 root 856: /* Set 'PC' to address of 'VDI_OPCODE' illegal instruction.
857: * This will call OpCode_VDI() after completion of Trap call!
858: * This is used to modify specific VDI return vectors contents.
859: */
1.1.1.13 root 860: VDI_OldPC = currpc;
861: currpc = CART_VDI_OPCODE_ADDR;
862: }
863: }
1.1.1.16 root 864:
1.1.1.13 root 865: if (bBiosIntercept)
866: {
867: /* Intercept BIOS or XBIOS trap (Trap #13 or #14) */
868: if (nr == 0x2d)
869: {
870: /* Intercept BIOS calls */
871: if (Bios()) return;
872: }
873: else if (nr == 0x2e)
874: {
875: /* Intercept XBIOS calls */
876: if (XBios()) return;
877: }
878: }
1.1.1.5 root 879: }
1.1.1.8 root 880:
1.1 root 881: MakeSR();
882:
1.1.1.8 root 883: /* Change to supervisor mode if necessary */
1.1 root 884: if (!regs.s) {
885: regs.usp = m68k_areg(regs, 7);
1.1.1.12 root 886: if (currprefs.cpu_level >= 2)
1.1 root 887: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
888: else
889: m68k_areg(regs, 7) = regs.isp;
890: regs.s = 1;
891: }
1.1.1.8 root 892:
893: /* Build additional exception stack frame for 68010 and higher */
1.1.1.13 root 894: /* (special case for MFP) */
1.1.1.12 root 895: if (currprefs.cpu_level > 0) {
1.1.1.16 root 896: if (ExceptionSource == M68000_EXC_SRC_INT_MFP
897: || ExceptionSource == M68000_EXC_SRC_INT_DSP) {
1.1.1.13 root 898: m68k_areg(regs, 7) -= 2;
899: put_word (m68k_areg(regs, 7), nr * 4); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
900: }
901: else if (nr == 2 || nr == 3) {
1.1 root 902: int i;
903: /* @@@ this is probably wrong (?) */
904: for (i = 0 ; i < 12 ; i++) {
905: m68k_areg(regs, 7) -= 2;
906: put_word (m68k_areg(regs, 7), 0);
907: }
908: m68k_areg(regs, 7) -= 2;
909: put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
910: } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
911: m68k_areg(regs, 7) -= 4;
912: put_long (m68k_areg(regs, 7), oldpc);
913: m68k_areg(regs, 7) -= 2;
914: put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
915: } else if (regs.m && nr >= 24 && nr < 32) {
916: m68k_areg(regs, 7) -= 2;
917: put_word (m68k_areg(regs, 7), nr * 4);
918: m68k_areg(regs, 7) -= 4;
919: put_long (m68k_areg(regs, 7), currpc);
920: m68k_areg(regs, 7) -= 2;
921: put_word (m68k_areg(regs, 7), regs.sr);
922: regs.sr |= (1 << 13);
923: regs.msp = m68k_areg(regs, 7);
924: m68k_areg(regs, 7) = regs.isp;
925: m68k_areg(regs, 7) -= 2;
926: put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
927: } else {
928: m68k_areg(regs, 7) -= 2;
929: put_word (m68k_areg(regs, 7), nr * 4);
930: }
931: }
1.1.1.3 root 932:
933: /* Push PC on stack: */
1.1 root 934: m68k_areg(regs, 7) -= 4;
935: put_long (m68k_areg(regs, 7), currpc);
1.1.1.3 root 936: /* Push SR on stack: */
1.1 root 937: m68k_areg(regs, 7) -= 2;
938: put_word (m68k_areg(regs, 7), regs.sr);
1.1.1.3 root 939:
1.1.1.15 root 940: LOG_TRACE(TRACE_CPU_EXCEPTION, "cpu exception %d currpc %x buspc %x newpc %x fault_e3 %x op_e3 %hx addr_e3 %x\n",
941: nr, currpc, BusErrorPC, get_long (regs.vbr + 4*nr), last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3);
1.1.1.12 root 942:
1.1.1.3 root 943: /* 68000 bus/address errors: */
1.1.1.16 root 944: if (currprefs.cpu_level==0 && (nr==2 || nr==3) && ExceptionSource == M68000_EXC_SRC_CPU) {
1.1.1.12 root 945: uae_u16 specialstatus = 1;
946:
1.1.1.8 root 947: /* Special status word emulation isn't perfect yet... :-( */
948: if (regs.sr & 0x2000)
949: specialstatus |= 0x4;
1.1.1.3 root 950: m68k_areg(regs, 7) -= 8;
951: if (nr == 3) { /* Address error */
1.1.1.12 root 952: specialstatus |= ( last_op_for_exception_3 & (~0x1f) ); /* [NP] unused bits of specialstatus are those of the last opcode ! */
1.1.1.8 root 953: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.3 root 954: put_long (m68k_areg(regs, 7)+2, last_fault_for_exception_3);
955: put_word (m68k_areg(regs, 7)+6, last_op_for_exception_3);
956: put_long (m68k_areg(regs, 7)+10, last_addr_for_exception_3);
1.1.1.15 root 957: if (bExceptionDebugging) {
1.1.1.8 root 958: fprintf(stderr,"Address Error at address $%x, PC=$%x\n",last_fault_for_exception_3,currpc);
1.1.1.18! root 959: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.8 root 960: }
1.1.1.3 root 961: }
1.1.1.8 root 962: else { /* Bus error */
1.1.1.12 root 963: specialstatus |= ( get_word(BusErrorPC) & (~0x1f) ); /* [NP] unused bits of special status are those of the last opcode ! */
1.1.1.8 root 964: if (bBusErrorReadWrite)
965: specialstatus |= 0x10;
966: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.10 root 967: put_long (m68k_areg(regs, 7)+2, BusErrorAddress);
1.1.1.12 root 968: put_word (m68k_areg(regs, 7)+6, get_word(BusErrorPC)); /* Opcode */
969:
970: /* [NP] PC stored in the stack frame is not necessarily pointing to the next instruction ! */
971: /* FIXME : we should have a proper model for this, in the meantime we handle specific cases */
1.1.1.16 root 972: if ( get_word(BusErrorPC) == 0x21f8 ) /* move.l $0.w,$24.w (Transbeauce 2 loader) */
1.1.1.12 root 973: put_long (m68k_areg(regs, 7)+10, currpc-2); /* correct PC is 2 bytes less than usual value */
1.1.1.8 root 974: /* Check for double bus errors: */
975: if (regs.spcflags & SPCFLAG_BUSERROR) {
976: fprintf(stderr, "Detected double bus error at address $%x, PC=$%lx => CPU halted!\n",
1.1.1.10 root 977: BusErrorAddress, (long)currpc);
1.1.1.8 root 978: unset_special(SPCFLAG_BUSERROR);
1.1.1.15 root 979: if (bExceptionDebugging)
1.1.1.18! root 980: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.15 root 981: else
1.1.1.17 root 982: DlgAlert_Notice("Detected double bus error => CPU halted!\nEmulation needs to be reset.\n");
1.1.1.8 root 983: regs.intmask = 7;
1.1.1.15 root 984: m68k_setstopped(true);
1.1.1.8 root 985: return;
986: }
1.1.1.15 root 987: if (bExceptionDebugging && BusErrorAddress!=0xff8a00) {
1.1.1.10 root 988: fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n", BusErrorAddress, (long)currpc);
1.1.1.18! root 989: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.8 root 990: }
991: }
1.1.1.3 root 992: }
993:
1.1.1.8 root 994: /* Set PC and flags */
1.1.1.15 root 995: if (bExceptionDebugging && get_long (regs.vbr + 4*nr) == 0) {
1.1.1.8 root 996: write_log("Uninitialized exception handler #%i!\n", nr);
1.1.1.18! root 997: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.8 root 998: }
1.1.1.17 root 999: newpc = get_long (regs.vbr + 4*nr);
1000: if ( newpc & 1) /* check new pc is even */
1001: {
1002: if ( nr==2 || nr==3 ) /* address error during bus/address error -> stop emulation */
1003: {
1004: fprintf(stderr,"Address Error during exception 2/3, aborting new PC=$%x\n",newpc);
1.1.1.18! root 1005: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.17 root 1006: }
1007: else
1008: {
1009: fprintf(stderr,"Address Error during exception, new PC=$%x\n",newpc);
1010: Exception ( 3 , m68k_getpc() , M68000_EXC_SRC_CPU );
1011: }
1012: return;
1013: }
1014:
1.1 root 1015: m68k_setpc (get_long (regs.vbr + 4*nr));
1016: fill_prefetch_0 ();
1.1.1.12 root 1017: /* Handle trace flags depending on current state */
1018: exception_trace (nr);
1.1.1.6 root 1019:
1.1.1.13 root 1020: /* Handle exception cycles (special case for MFP) */
1.1.1.16 root 1021: if (ExceptionSource == M68000_EXC_SRC_INT_MFP)
1.1.1.13 root 1022: {
1023: M68000_AddCycles(44+12); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
1024: }
1025: else if (nr >= 24 && nr <= 31)
1.1.1.7 root 1026: {
1.1.1.15 root 1027: if ( nr == 26 ) /* HBL */
1028: {
1029: /* store current cycle pos when then interrupt was received (see video.c) */
1030: LastCycleHblException = Cycles_GetCounter(CYCLES_COUNTER_VIDEO);
1031: M68000_AddCycles(44+12); /* Video Interrupt */
1032: }
1033: else if ( nr == 28 ) /* VBL */
1.1.1.12 root 1034: M68000_AddCycles(44+12); /* Video Interrupt */
1035: else
1036: M68000_AddCycles(44+4); /* Other Interrupts */
1.1.1.7 root 1037: }
1038: else if(nr >= 32 && nr <= 47)
1039: {
1.1.1.13 root 1040: M68000_AddCycles(34-4); /* Trap (total is 34, but cpuemu.c already adds 4) */
1.1.1.7 root 1041: }
1042: else switch(nr)
1043: {
1.1.1.12 root 1044: case 2: M68000_AddCycles(50); break; /* Bus error */
1045: case 3: M68000_AddCycles(50); break; /* Address error */
1046: case 4: M68000_AddCycles(34); break; /* Illegal instruction */
1047: case 5: M68000_AddCycles(38); break; /* Div by zero */
1048: case 6: M68000_AddCycles(40); break; /* CHK */
1049: case 7: M68000_AddCycles(34); break; /* TRAPV */
1050: case 8: M68000_AddCycles(34); break; /* Privilege violation */
1051: case 9: M68000_AddCycles(34); break; /* Trace */
1052: case 10: M68000_AddCycles(34); break; /* Line-A - probably wrong */
1053: case 11: M68000_AddCycles(34); break; /* Line-F - probably wrong */
1.1.1.7 root 1054: default:
1.1.1.8 root 1055: /* FIXME: Add right cycles value for MFP interrupts and copro exceptions ... */
1.1.1.7 root 1056: if(nr < 64)
1.1.1.12 root 1057: M68000_AddCycles(4); /* Coprocessor and unassigned exceptions (???) */
1.1.1.7 root 1058: else
1.1.1.16 root 1059: M68000_AddCycles(44+12); /* Must be a MFP or DSP interrupt */
1.1.1.7 root 1060: break;
1.1.1.6 root 1061: }
1.1.1.14 root 1062:
1.1 root 1063: }
1064:
1.1.1.7 root 1065:
1.1.1.14 root 1066: static void Interrupt(int nr , int Pending)
1.1 root 1067: {
1068: assert(nr < 8 && nr >= 0);
1.1.1.10 root 1069: /*lastint_regs = regs;*/
1070: /*lastint_no = nr;*/
1.1.1.13 root 1071:
1.1.1.16 root 1072: /* On Hatari, only video ints are using SPCFLAG_INT (see m68000.c) */
1073: Exception(nr+24, 0, M68000_EXC_SRC_AUTOVEC);
1.1 root 1074:
1075: regs.intmask = nr;
1076: set_special (SPCFLAG_INT);
1.1.1.14 root 1077:
1078: /* Handle Atari ST's specific jitter for hbl/vbl */
1079: InterruptAddJitter ( nr , Pending );
1.1 root 1080: }
1081:
1.1.1.7 root 1082:
1.1.1.12 root 1083: uae_u32 caar, cacr;
1.1.1.8 root 1084: static uae_u32 itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp;
1.1 root 1085:
1.1.1.7 root 1086:
1.1.1.12 root 1087: static int movec_illg (int regno)
1088: {
1089: int regno2 = regno & 0x7ff;
1090: if (currprefs.cpu_level == 1) { /* 68010 */
1091: if (regno2 < 2)
1092: return 0;
1093: return 1;
1094: }
1095: if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) { /* 68020 */
1096: if (regno == 3) return 1; /* 68040 only */
1097: /* 4 is >=68040, but 0x804 is in 68020 */
1098: if (regno2 < 4 || regno == 0x804)
1099: return 0;
1100: return 1;
1101: }
1102: if (currprefs.cpu_level >= 4) { /* 68040 */
1103: if (regno == 0x802) return 1; /* 68020 only */
1104: if (regno2 < 8) return 0;
1105: if (currprefs.cpu_level == 6 && regno2 == 8) /* 68060 only */
1106: return 0;
1107: return 1;
1108: }
1109: return 1;
1110: }
1111:
1.1 root 1112: int m68k_move2c (int regno, uae_u32 *regp)
1113: {
1.1.1.12 root 1114: if (movec_illg (regno)) {
1.1 root 1115: op_illg (0x4E7B);
1116: return 0;
1117: } else {
1118: switch (regno) {
1119: case 0: regs.sfc = *regp & 7; break;
1120: case 1: regs.dfc = *regp & 7; break;
1.1.1.16 root 1121: case 2:
1122: {
1123: uae_u32 cacr_mask = 0;
1124: if (currprefs.cpu_level == 2) // 68020
1125: cacr_mask = 0x0000000f;
1126: else if (currprefs.cpu_level == 3) // Fake 68030
1127: cacr_mask = 0x00003f1f;
1128: else if (currprefs.cpu_level == 4) // 68040
1129: cacr_mask = 0x80008000;
1130: cacr = *regp & cacr_mask;
1131: }
1.1 root 1132: case 3: tc = *regp & 0xc000; break;
1133: /* Mask out fields that should be zero. */
1134: case 4: itt0 = *regp & 0xffffe364; break;
1135: case 5: itt1 = *regp & 0xffffe364; break;
1136: case 6: dtt0 = *regp & 0xffffe364; break;
1137: case 7: dtt1 = *regp & 0xffffe364; break;
1.1.1.7 root 1138:
1.1 root 1139: case 0x800: regs.usp = *regp; break;
1140: case 0x801: regs.vbr = *regp; break;
1.1.1.12 root 1141: case 0x802: caar = *regp & 0xfc; break;
1.1 root 1142: case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
1143: case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
1.1.1.6 root 1144: case 0x805: mmusr = *regp; break;
1145: case 0x806: urp = *regp; break;
1146: case 0x807: srp = *regp; break;
1.1 root 1147: default:
1148: op_illg (0x4E7B);
1149: return 0;
1150: }
1151: }
1152: return 1;
1153: }
1154:
1155: int m68k_movec2 (int regno, uae_u32 *regp)
1156: {
1.1.1.12 root 1157: if (movec_illg (regno)) {
1.1 root 1158: op_illg (0x4E7A);
1159: return 0;
1160: } else {
1161: switch (regno) {
1162: case 0: *regp = regs.sfc; break;
1163: case 1: *regp = regs.dfc; break;
1.1.1.12 root 1164: case 2: *regp = cacr; break;
1.1 root 1165: case 3: *regp = tc; break;
1166: case 4: *regp = itt0; break;
1167: case 5: *regp = itt1; break;
1168: case 6: *regp = dtt0; break;
1169: case 7: *regp = dtt1; break;
1170: case 0x800: *regp = regs.usp; break;
1171: case 0x801: *regp = regs.vbr; break;
1.1.1.12 root 1172: case 0x802: *regp = caar; break;
1.1 root 1173: case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
1174: case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
1175: case 0x805: *regp = mmusr; break;
1.1.1.6 root 1176: case 0x806: *regp = urp; break;
1177: case 0x807: *regp = srp; break;
1.1 root 1178: default:
1179: op_illg (0x4E7A);
1180: return 0;
1181: }
1182: }
1183: return 1;
1184: }
1185:
1186: STATIC_INLINE int
1.1.1.10 root 1187: div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 ndiv, uae_u32 *quot, uae_u32 *rem)
1.1 root 1188: {
1189: uae_u32 q = 0, cbit = 0;
1190: int i;
1191:
1.1.1.10 root 1192: if (ndiv <= src_hi) {
1.1 root 1193: return 1;
1194: }
1195: for (i = 0 ; i < 32 ; i++) {
1196: cbit = src_hi & 0x80000000ul;
1197: src_hi <<= 1;
1198: if (src_lo & 0x80000000ul) src_hi++;
1199: src_lo <<= 1;
1200: q = q << 1;
1.1.1.10 root 1201: if (cbit || ndiv <= src_hi) {
1.1 root 1202: q |= 1;
1.1.1.10 root 1203: src_hi -= ndiv;
1.1 root 1204: }
1205: }
1206: *quot = q;
1207: *rem = src_hi;
1208: return 0;
1209: }
1210:
1211: void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
1212: {
1213: #if defined(uae_s64)
1214: if (src == 0) {
1.1.1.16 root 1215: Exception (5, oldpc,M68000_EXC_SRC_CPU);
1.1 root 1216: return;
1217: }
1218: if (extra & 0x800) {
1219: /* signed variant */
1220: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1221: uae_s64 quot, rem;
1222:
1223: if (extra & 0x400) {
1224: a &= 0xffffffffu;
1225: a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
1226: }
1227: rem = a % (uae_s64)(uae_s32)src;
1228: quot = a / (uae_s64)(uae_s32)src;
1229: if ((quot & UVAL64(0xffffffff80000000)) != 0
1230: && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1231: {
1232: SET_VFLG (1);
1233: SET_NFLG (1);
1234: SET_CFLG (0);
1235: } else {
1236: if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
1237: SET_VFLG (0);
1238: SET_CFLG (0);
1239: SET_ZFLG (((uae_s32)quot) == 0);
1240: SET_NFLG (((uae_s32)quot) < 0);
1241: m68k_dreg(regs, extra & 7) = rem;
1242: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1243: }
1244: } else {
1245: /* unsigned */
1246: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1247: uae_u64 quot, rem;
1248:
1249: if (extra & 0x400) {
1250: a &= 0xffffffffu;
1251: a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
1252: }
1253: rem = a % (uae_u64)src;
1254: quot = a / (uae_u64)src;
1255: if (quot > 0xffffffffu) {
1256: SET_VFLG (1);
1257: SET_NFLG (1);
1258: SET_CFLG (0);
1259: } else {
1260: SET_VFLG (0);
1261: SET_CFLG (0);
1262: SET_ZFLG (((uae_s32)quot) == 0);
1263: SET_NFLG (((uae_s32)quot) < 0);
1264: m68k_dreg(regs, extra & 7) = rem;
1265: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1266: }
1267: }
1268: #else
1269: if (src == 0) {
1.1.1.16 root 1270: Exception (5, oldpc,M68000_EXC_SRC_CPU);
1.1 root 1271: return;
1272: }
1273: if (extra & 0x800) {
1274: /* signed variant */
1275: uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1276: uae_s32 hi = lo < 0 ? -1 : 0;
1277: uae_s32 save_high;
1278: uae_u32 quot, rem;
1279: uae_u32 sign;
1280:
1281: if (extra & 0x400) {
1282: hi = (uae_s32)m68k_dreg(regs, extra & 7);
1283: }
1284: save_high = hi;
1285: sign = (hi ^ src);
1286: if (hi < 0) {
1287: hi = ~hi;
1288: lo = -lo;
1289: if (lo == 0) hi++;
1290: }
1291: if ((uae_s32)src < 0) src = -src;
1292: if (div_unsigned(hi, lo, src, ", &rem) ||
1293: (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
1294: SET_VFLG (1);
1295: SET_NFLG (1);
1296: SET_CFLG (0);
1297: } else {
1298: if (sign & 0x80000000) quot = -quot;
1299: if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
1300: SET_VFLG (0);
1301: SET_CFLG (0);
1302: SET_ZFLG (((uae_s32)quot) == 0);
1303: SET_NFLG (((uae_s32)quot) < 0);
1304: m68k_dreg(regs, extra & 7) = rem;
1305: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1306: }
1307: } else {
1308: /* unsigned */
1309: uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1310: uae_u32 hi = 0;
1311: uae_u32 quot, rem;
1312:
1313: if (extra & 0x400) {
1314: hi = (uae_u32)m68k_dreg(regs, extra & 7);
1315: }
1316: if (div_unsigned(hi, lo, src, ", &rem)) {
1317: SET_VFLG (1);
1318: SET_NFLG (1);
1319: SET_CFLG (0);
1320: } else {
1321: SET_VFLG (0);
1322: SET_CFLG (0);
1323: SET_ZFLG (((uae_s32)quot) == 0);
1324: SET_NFLG (((uae_s32)quot) < 0);
1325: m68k_dreg(regs, extra & 7) = rem;
1326: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1327: }
1328: }
1329: #endif
1330: }
1331:
1332: STATIC_INLINE void
1333: mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1334: {
1335: uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1336: uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1337: uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1338: uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1339: uae_u32 lo;
1340:
1341: lo = r0 + ((r1 << 16) & 0xffff0000ul);
1342: if (lo < r0) r3++;
1343: r0 = lo;
1344: lo = r0 + ((r2 << 16) & 0xffff0000ul);
1345: if (lo < r0) r3++;
1346: r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1347: *dst_lo = lo;
1348: *dst_hi = r3;
1349: }
1350:
1351: void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1352: {
1353: #if defined(uae_s64)
1354: if (extra & 0x800) {
1355: /* signed variant */
1356: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1357:
1358: a *= (uae_s64)(uae_s32)src;
1359: SET_VFLG (0);
1360: SET_CFLG (0);
1361: SET_ZFLG (a == 0);
1362: SET_NFLG (a < 0);
1363: if (extra & 0x400)
1364: m68k_dreg(regs, extra & 7) = a >> 32;
1365: else if ((a & UVAL64(0xffffffff80000000)) != 0
1366: && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1367: {
1368: SET_VFLG (1);
1369: }
1370: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1371: } else {
1372: /* unsigned */
1373: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1374:
1375: a *= (uae_u64)src;
1376: SET_VFLG (0);
1377: SET_CFLG (0);
1378: SET_ZFLG (a == 0);
1379: SET_NFLG (((uae_s64)a) < 0);
1380: if (extra & 0x400)
1381: m68k_dreg(regs, extra & 7) = a >> 32;
1382: else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1383: SET_VFLG (1);
1384: }
1385: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1386: }
1387: #else
1388: if (extra & 0x800) {
1389: /* signed variant */
1390: uae_s32 src1,src2;
1391: uae_u32 dst_lo,dst_hi;
1392: uae_u32 sign;
1393:
1394: src1 = (uae_s32)src;
1395: src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1396: sign = (src1 ^ src2);
1397: if (src1 < 0) src1 = -src1;
1398: if (src2 < 0) src2 = -src2;
1399: mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1400: if (sign & 0x80000000) {
1401: dst_hi = ~dst_hi;
1402: dst_lo = -dst_lo;
1403: if (dst_lo == 0) dst_hi++;
1404: }
1405: SET_VFLG (0);
1406: SET_CFLG (0);
1407: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1408: SET_NFLG (((uae_s32)dst_hi) < 0);
1409: if (extra & 0x400)
1410: m68k_dreg(regs, extra & 7) = dst_hi;
1411: else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1412: && ((dst_hi & 0xffffffff) != 0xffffffff
1413: || (dst_lo & 0x80000000) != 0x80000000))
1414: {
1415: SET_VFLG (1);
1416: }
1417: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1418: } else {
1419: /* unsigned */
1420: uae_u32 dst_lo,dst_hi;
1421:
1422: mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1423:
1424: SET_VFLG (0);
1425: SET_CFLG (0);
1426: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1427: SET_NFLG (((uae_s32)dst_hi) < 0);
1428: if (extra & 0x400)
1429: m68k_dreg(regs, extra & 7) = dst_hi;
1430: else if (dst_hi != 0) {
1431: SET_VFLG (1);
1432: }
1433: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1434: }
1435: #endif
1436: }
1.1.1.6 root 1437:
1.1 root 1438:
1439: void m68k_reset (void)
1440: {
1441: regs.s = 1;
1442: regs.m = 0;
1443: regs.stopped = 0;
1444: regs.t1 = 0;
1445: regs.t0 = 0;
1446: SET_ZFLG (0);
1447: SET_XFLG (0);
1448: SET_CFLG (0);
1449: SET_VFLG (0);
1450: SET_NFLG (0);
1.1.1.16 root 1451: regs.spcflags &= ( SPCFLAG_MODE_CHANGE | SPCFLAG_DEBUGGER ); /* Clear specialflags except mode-change and debugger */
1.1 root 1452: regs.intmask = 7;
1453: regs.vbr = regs.sfc = regs.dfc = 0;
1454: regs.fpcr = regs.fpsr = regs.fpiar = 0;
1.1.1.7 root 1455:
1456: m68k_areg(regs, 7) = get_long(0);
1457: m68k_setpc(get_long(4));
1458: refill_prefetch (m68k_getpc(), 0);
1.1 root 1459: }
1460:
1.1.1.8 root 1461:
1.1 root 1462: unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1463: {
1.1.1.8 root 1464: #if 0
1.1 root 1465: uaecptr pc = m68k_getpc ();
1.1.1.8 root 1466: #endif
1.1.1.6 root 1467: if ((opcode & 0xF000) == 0xF000) {
1.1.1.16 root 1468: Exception(0xB,0,M68000_EXC_SRC_CPU);
1.1 root 1469: return 4;
1.1.1.6 root 1470: }
1471: if ((opcode & 0xF000) == 0xA000) {
1.1.1.16 root 1472: Exception(0xA,0,M68000_EXC_SRC_CPU);
1.1 root 1473: return 4;
1.1.1.6 root 1474: }
1.1.1.3 root 1475: #if 0
1.1.1.6 root 1476: write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc);
1.1 root 1477: #endif
1.1.1.16 root 1478: Exception (4,0,M68000_EXC_SRC_CPU);
1.1 root 1479: return 4;
1480: }
1481:
1.1.1.8 root 1482:
1.1 root 1483: void mmu_op(uae_u32 opcode, uae_u16 extra)
1484: {
1485: if ((opcode & 0xFE0) == 0x0500) {
1486: /* PFLUSH */
1487: mmusr = 0;
1488: write_log ("PFLUSH\n");
1489: } else if ((opcode & 0x0FD8) == 0x548) {
1490: /* PTEST */
1491: write_log ("PTEST\n");
1492: } else
1493: op_illg (opcode);
1494: }
1495:
1496:
1497: static uaecptr last_trace_ad = 0;
1498:
1499: static void do_trace (void)
1500: {
1.1.1.12 root 1501: if (regs.t0 && currprefs.cpu_level >= 2) {
1.1 root 1502: uae_u16 opcode;
1503: /* should also include TRAP, CHK, SR modification FPcc */
1504: /* probably never used so why bother */
1505: /* We can afford this to be inefficient... */
1506: m68k_setpc (m68k_getpc ());
1507: fill_prefetch_0 ();
1508: opcode = get_word (regs.pc);
1509: if (opcode == 0x4e72 /* RTE */
1510: || opcode == 0x4e74 /* RTD */
1511: || opcode == 0x4e75 /* RTS */
1512: || opcode == 0x4e77 /* RTR */
1513: || opcode == 0x4e76 /* TRAPV */
1514: || (opcode & 0xffc0) == 0x4e80 /* JSR */
1515: || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1516: || (opcode & 0xff00) == 0x6100 /* BSR */
1517: || ((opcode & 0xf000) == 0x6000 /* Bcc */
1518: && cctrue((opcode >> 8) & 0xf))
1519: || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1520: && !cctrue((opcode >> 8) & 0xf)
1521: && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1522: {
1523: last_trace_ad = m68k_getpc ();
1524: unset_special (SPCFLAG_TRACE);
1525: set_special (SPCFLAG_DOTRACE);
1526: }
1527: } else if (regs.t1) {
1528: last_trace_ad = m68k_getpc ();
1529: unset_special (SPCFLAG_TRACE);
1530: set_special (SPCFLAG_DOTRACE);
1531: }
1532: }
1533:
1534:
1.1.1.8 root 1535: /*
1536: * Handle special flags
1537: */
1.1.1.14 root 1538:
1539: static bool do_specialties_interrupt (int Pending)
1540: {
1541: /* Check for MFP ints first (level 6) */
1542: if (regs.spcflags & SPCFLAG_MFP) {
1.1.1.15 root 1543: if (MFP_CheckPendingInterrupts() == true)
1544: return true; /* MFP exception was generated, no higher interrupt can happen */
1.1.1.14 root 1545: }
1546:
1547: /* No MFP int, check for VBL/HBL ints (levels 4/2) */
1548: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1549: int intr = intlev ();
1550: /* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */
1551: // unset_special (SPCFLAG_DOINT);
1552: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1553: if (intr != -1 && intr > regs.intmask) {
1554: Interrupt (intr , Pending); /* process the interrupt and add pending jitter if necessary */
1.1.1.15 root 1555: return true;
1.1.1.14 root 1556: }
1557: }
1558:
1.1.1.15 root 1559: return false; /* no interrupt was found */
1.1.1.14 root 1560: }
1561:
1562:
1.1 root 1563: static int do_specialties (void)
1564: {
1.1.1.7 root 1565: if(regs.spcflags & SPCFLAG_BUSERROR) {
1566: /* We can not execute bus errors directly in the memory handler
1567: * functions since the PC should point to the address of the next
1568: * instruction, so we're executing the bus errors here: */
1.1.1.8 root 1569: unset_special(SPCFLAG_BUSERROR);
1.1.1.16 root 1570: Exception(2,0,M68000_EXC_SRC_CPU);
1.1.1.7 root 1571: }
1572:
1.1.1.8 root 1573: if(regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1574: /* Add some extra cycles to simulate a wait state */
1575: unset_special(SPCFLAG_EXTRA_CYCLES);
1.1.1.11 root 1576: M68000_AddCycles(nWaitStateCycles);
1.1.1.12 root 1577: nWaitStateCycles = 0;
1.1.1.8 root 1578: }
1579:
1.1 root 1580: if (regs.spcflags & SPCFLAG_DOTRACE) {
1.1.1.16 root 1581: Exception (9,last_trace_ad,M68000_EXC_SRC_CPU);
1.1 root 1582: }
1.1.1.8 root 1583:
1.1.1.14 root 1584:
1585: /* Handle the STOP instruction */
1586: if ( regs.spcflags & SPCFLAG_STOP ) {
1587: /* We first test if there's a pending interrupt that would */
1588: /* allow to immediatly leave the STOP state */
1.1.1.15 root 1589: if ( do_specialties_interrupt(true) ) { /* test if there's an interrupt and add pending jitter */
1.1.1.14 root 1590: regs.stopped = 0;
1591: unset_special (SPCFLAG_STOP);
1592: }
1593: #if 0
1594: if (regs.spcflags & SPCFLAG_MFP) /* MFP int */
1595: MFP_CheckPendingInterrupts();
1596:
1597: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) { /* VBL/HBL ints */
1598: int intr = intlev ();
1599: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1600: if (intr != -1 && intr > regs.intmask) {
1.1.1.15 root 1601: Interrupt (intr , true); /* process the interrupt and add pending jitter */
1.1.1.14 root 1602: regs.stopped = 0;
1603: unset_special (SPCFLAG_STOP);
1604: }
1605: }
1606: #endif
1607:
1608: /* No pending int, we have to wait for the next matching int */
1609: while (regs.spcflags & SPCFLAG_STOP) {
1610:
1611: /* Take care of quit event if needed */
1612: if (regs.spcflags & SPCFLAG_BRK)
1613: return 1;
1614:
1615: M68000_AddCycles(4);
1616:
1617: /* It is possible one or more ints happen at the same time */
1618: /* We must process them during the same cpu cycle until the special INT flag is set */
1619: while (PendingInterruptCount<=0 && PendingInterruptFunction) {
1620: /* 1st, we call the interrupt handler */
1621: CALL_VAR(PendingInterruptFunction);
1622:
1623: /* Then we check if this handler triggered an interrupt to process */
1.1.1.15 root 1624: if ( do_specialties_interrupt(false) ) { /* test if there's an interrupt and add non pending jitter */
1.1.1.13 root 1625: regs.stopped = 0;
1626: unset_special (SPCFLAG_STOP);
1.1.1.14 root 1627: break;
1628: }
1629: #if 0
1630: /* Then we check if this handler triggered an MFP int to process */
1631: if (regs.spcflags & SPCFLAG_MFP)
1632: MFP_CheckPendingInterrupts();
1633:
1634: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1635: int intr = intlev ();
1636: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1637: if (intr != -1 && intr > regs.intmask) {
1.1.1.15 root 1638: Interrupt (intr , false); /* process the interrupt and add non pending jitter */
1.1.1.14 root 1639: regs.stopped = 0;
1640: unset_special (SPCFLAG_STOP);
1641: break;
1642: }
1643: }
1644: #endif
1.1.1.6 root 1645: }
1.1 root 1646: }
1647: }
1.1.1.8 root 1648:
1.1.1.14 root 1649:
1.1 root 1650: if (regs.spcflags & SPCFLAG_TRACE)
1651: do_trace ();
1652:
1.1.1.12 root 1653: // if (regs.spcflags & SPCFLAG_DOINT) {
1654: /* [NP] pending int should be processed now, not after the current instr */
1.1.1.14 root 1655: /* so we check for (SPCFLAG_INT | SPCFLAG_DOINT), not just for SPCFLAG_DOINT */
1.1.1.15 root 1656:
1657: if ( do_specialties_interrupt(false) ) { /* test if there's an interrupt and add non pending jitter */
1.1.1.14 root 1658: regs.stopped = 0; /* [NP] useless ? */
1659: }
1660: if (regs.spcflags & SPCFLAG_INT) {
1661: unset_special (SPCFLAG_INT);
1662: set_special (SPCFLAG_DOINT);
1663: }
1664: #if 0
1.1.1.12 root 1665: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1.1.1.6 root 1666: int intr = intlev ();
1.1.1.8 root 1667: /* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */
1.1.1.12 root 1668: // unset_special (SPCFLAG_DOINT);
1669: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1.1.1.6 root 1670: if (intr != -1 && intr > regs.intmask) {
1.1.1.15 root 1671: Interrupt (intr , false); /* call Interrupt() with Pending=false, not necessarily true but harmless */
1.1.1.14 root 1672: regs.stopped = 0; /* [NP] useless ? */
1.1.1.6 root 1673: }
1.1 root 1674: }
1675: if (regs.spcflags & SPCFLAG_INT) {
1676: unset_special (SPCFLAG_INT);
1677: set_special (SPCFLAG_DOINT);
1678: }
1.1.1.8 root 1679:
1680: if (regs.spcflags & SPCFLAG_MFP) { /* Check for MFP interrupts */
1681: MFP_CheckPendingInterrupts();
1682: }
1.1.1.14 root 1683: #endif
1.1.1.8 root 1684:
1.1.1.15 root 1685: if (regs.spcflags & SPCFLAG_DEBUGGER)
1.1.1.16 root 1686: DebugCpu_Check();
1.1.1.15 root 1687:
1.1 root 1688: if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1.1.1.8 root 1689: unset_special(SPCFLAG_MODE_CHANGE);
1.1 root 1690: return 1;
1691: }
1.1.1.8 root 1692:
1.1 root 1693: return 0;
1694: }
1695:
1.1.1.3 root 1696:
1.1 root 1697: /* It's really sad to have two almost identical functions for this, but we
1698: do it all for performance... :( */
1699: static void m68k_run_1 (void)
1700: {
1701: #ifdef DEBUG_PREFETCH
1702: uae_u8 saved_bytes[20];
1703: uae_u16 *oldpcp;
1704: #endif
1.1.1.8 root 1705:
1706: for (;;) {
1.1 root 1707: int cycles;
1708: uae_u32 opcode = get_iword_prefetch (0);
1.1.1.8 root 1709:
1.1 root 1710: #ifdef DEBUG_PREFETCH
1711: if (get_ilong (0) != do_get_mem_long (®s.prefetch)) {
1712: fprintf (stderr, "Prefetch differs from memory.\n");
1713: debugging = 1;
1714: return;
1715: }
1716: oldpcp = regs.pc_p;
1717: memcpy (saved_bytes, regs.pc_p, 20);
1718: #endif
1719:
1720: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.15 root 1721: if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
1722: {
1723: int FrameCycles, HblCounterVideo, LineCycles;
1724:
1725: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
1726:
1727: LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
1.1.1.17 root 1728: Disasm(stderr, m68k_getpc (), NULL, 1, DISASM_ENGINE_EXT);
1.1.1.15 root 1729: }
1.1 root 1730:
1731: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1732: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1733: #if COUNT_INSTRS == 2
1734: if (table68k[opcode].handler != -1)
1735: instrcount[table68k[opcode].handler]++;
1736: #elif COUNT_INSTRS == 1
1737: instrcount[opcode]++;
1738: #endif
1.1.1.2 root 1739:
1.1.1.12 root 1740: /* In case of a Bus Error, we need the PC of the instruction that caused */
1741: /* the error to build the exception stack frame */
1742: BusErrorPC = m68k_getpc();
1743:
1.1.1.18! root 1744: if (bDspEnabled)
! 1745: Cycles_SetCounter(CYCLES_COUNTER_CPU, 0); /* to measure the total number of cycles spent in the cpu */
! 1746:
1.1.1.6 root 1747: cycles = (*cpufunctbl[opcode])(opcode);
1748:
1.1 root 1749: #ifdef DEBUG_PREFETCH
1750: if (memcmp (saved_bytes, oldpcp, 20) != 0) {
1.1.1.12 root 1751: fprintf (stderr, "Self-modifying code detected %x.\n" , m68k_getpc() );
1.1 root 1752: set_special (SPCFLAG_BRK);
1753: debugging = 1;
1754: }
1755: #endif
1.1.1.2 root 1756:
1.1.1.12 root 1757: M68000_AddCyclesWithPairing(cycles);
1.1.1.13 root 1758: if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1759: /* Add some extra cycles to simulate a wait state */
1760: unset_special(SPCFLAG_EXTRA_CYCLES);
1761: M68000_AddCycles(nWaitStateCycles);
1762: nWaitStateCycles = 0;
1763: }
1764:
1.1.1.14 root 1765: #if 0
1766: while (PendingInterruptCount <= 0 && PendingInterruptFunction)
1.1.1.8 root 1767: CALL_VAR(PendingInterruptFunction);
1.1.1.14 root 1768: #else
1769: /* We can have several interrupts at the same time before the next CPU instruction */
1770: /* We must check for pending interrupt and call do_specialties_interrupt() only */
1771: /* if the cpu is not in the STOP state. Else, the int could be acknowledged now */
1772: /* and prevent exiting the STOP state when calling do_specialties() after. */
1773: /* For performance, we first test PendingInterruptCount, then regs.spcflags */
1774: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) && ( ( regs.spcflags & SPCFLAG_STOP ) == 0 ) )
1775: {
1776: CALL_VAR(PendingInterruptFunction); /* call the interrupt handler */
1.1.1.15 root 1777: do_specialties_interrupt(false); /* test if there's an mfp/video interrupt and add non pending jitter */
1.1.1.14 root 1778: #if 0
1779: if ( regs.spcflags & ( SPCFLAG_MFP | SPCFLAG_INT ) ) { /* only check mfp/video interrupts */
1780: if (do_specialties ()) /* check if this latest int has higher priority */
1781: return;
1782: }
1783: #endif
1784: }
1.1.1.15 root 1785: #endif
1.1.1.14 root 1786:
1787: if (regs.spcflags) {
1788: if (do_specialties ())
1789: return;
1790: }
1791:
1.1.1.15 root 1792: /* Run DSP 56k code if necessary */
1793: if (bDspEnabled) {
1.1.1.18! root 1794: DSP_Run( Cycles_GetCounter(CYCLES_COUNTER_CPU) * 2);
1.1.1.15 root 1795: }
1.1 root 1796: }
1797: }
1798:
1799:
1800: /* Same thing, but don't use prefetch to get opcode. */
1801: static void m68k_run_2 (void)
1802: {
1.1.1.8 root 1803: for (;;) {
1.1 root 1804: int cycles;
1805: uae_u32 opcode = get_iword (0);
1806:
1807: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.15 root 1808: if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
1809: {
1810: int FrameCycles, HblCounterVideo, LineCycles;
1811:
1812: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
1813:
1814: LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
1.1.1.17 root 1815: Disasm(stderr, m68k_getpc (), NULL, 1, DISASM_ENGINE_EXT);
1.1.1.15 root 1816: }
1.1.1.12 root 1817:
1.1 root 1818: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1819: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1820: #if COUNT_INSTRS == 2
1821: if (table68k[opcode].handler != -1)
1822: instrcount[table68k[opcode].handler]++;
1823: #elif COUNT_INSTRS == 1
1824: instrcount[opcode]++;
1825: #endif
1.1.1.2 root 1826:
1.1.1.17 root 1827: /* In case of a Bus Error, we need the PC of the instruction that caused */
1828: /* the error to build the exception stack frame */
1829: BusErrorPC = m68k_getpc();
1830:
1.1.1.6 root 1831: cycles = (*cpufunctbl[opcode])(opcode);
1832:
1.1.1.16 root 1833: if (bDspEnabled)
1834: Cycles_SetCounter(CYCLES_COUNTER_CPU, 0); /* to measure the total number of cycles spent in the cpu */
1835:
1.1.1.8 root 1836: M68000_AddCycles(cycles);
1.1.1.13 root 1837: if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1838: /* Add some extra cycles to simulate a wait state */
1839: unset_special(SPCFLAG_EXTRA_CYCLES);
1840: M68000_AddCycles(nWaitStateCycles);
1841: nWaitStateCycles = 0;
1842: }
1843:
1.1.1.12 root 1844: while (PendingInterruptCount <= 0 && PendingInterruptFunction)
1.1.1.8 root 1845: CALL_VAR(PendingInterruptFunction);
1846:
1.1 root 1847: if (regs.spcflags) {
1848: if (do_specialties ())
1849: return;
1850: }
1.1.1.15 root 1851:
1852: /* Run DSP 56k code if necessary */
1853: if (bDspEnabled) {
1.1.1.16 root 1854: DSP_Run( Cycles_GetCounter(CYCLES_COUNTER_CPU) );
1.1.1.15 root 1855: }
1.1 root 1856: }
1857: }
1858:
1859:
1860: void m68k_go (int may_quit)
1861: {
1.1.1.8 root 1862: static int in_m68k_go = 0;
1863:
1.1 root 1864: if (in_m68k_go || !may_quit) {
1865: write_log ("Bug! m68k_go is not reentrant.\n");
1866: abort ();
1867: }
1868:
1869: in_m68k_go++;
1.1.1.8 root 1870: while (!(regs.spcflags & SPCFLAG_BRK)) {
1.1.1.12 root 1871: if(currprefs.cpu_compatible)
1.1.1.2 root 1872: m68k_run_1();
1873: else
1874: m68k_run_2();
1.1 root 1875: }
1.1.1.8 root 1876: unset_special(SPCFLAG_BRK);
1.1 root 1877: in_m68k_go--;
1878: }
1879:
1.1.1.8 root 1880:
1881: /*
1.1 root 1882: static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1883: {
1884: uae_u32 opcode, val;
1885: struct instr *dp;
1886:
1887: opcode = get_iword_1(0);
1888: last_op_for_exception_3 = opcode;
1889: m68kpc_offset = 2;
1890:
1.1.1.6 root 1891: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1892: opcode = 0x4AFC;
1893: }
1894: dp = table68k + opcode;
1895:
1896: if (dp->suse) {
1897: if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) {
1.1.1.16 root 1898: Exception (3, 0,M68000_EXC_SRC_CPU);
1.1 root 1899: return;
1900: }
1901: }
1902: if (dp->duse) {
1903: if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) {
1.1.1.16 root 1904: Exception (3, 0,M68000_EXC_SRC_CPU);
1.1 root 1905: return;
1906: }
1907: }
1908: }
1.1.1.8 root 1909: */
1910:
1.1 root 1911:
1912: void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1913: {
1.1.1.11 root 1914: static const char * const ccnames[] =
1.1.1.8 root 1915: { "T ","F ","HI","LS","CC","CS","NE","EQ",
1916: "VC","VS","PL","MI","GE","LT","GT","LE" };
1917:
1.1 root 1918: uaecptr newpc = 0;
1919: m68kpc_offset = addr - m68k_getpc ();
1920: while (cnt-- > 0) {
1921: char instrname[20],*ccpt;
1922: int opwords;
1923: uae_u32 opcode;
1.1.1.11 root 1924: const struct mnemolookup *lookup;
1.1 root 1925: struct instr *dp;
1926: fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset);
1927: for (opwords = 0; opwords < 5; opwords++){
1928: fprintf (f, "%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1929: }
1930: opcode = get_iword_1 (m68kpc_offset);
1931: m68kpc_offset += 2;
1.1.1.6 root 1932: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1933: opcode = 0x4AFC;
1934: }
1935: dp = table68k + opcode;
1936: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1937: ;
1938:
1939: strcpy (instrname, lookup->name);
1940: ccpt = strstr (instrname, "cc");
1941: if (ccpt != 0) {
1942: strncpy (ccpt, ccnames[dp->cc], 2);
1943: }
1944: fprintf (f, "%s", instrname);
1945: switch (dp->size){
1946: case sz_byte: fprintf (f, ".B "); break;
1947: case sz_word: fprintf (f, ".W "); break;
1948: case sz_long: fprintf (f, ".L "); break;
1949: default: fprintf (f, " "); break;
1950: }
1951:
1952: if (dp->suse) {
1953: newpc = m68k_getpc () + m68kpc_offset;
1954: newpc += ShowEA (f, dp->sreg, dp->smode, dp->size, 0);
1955: }
1956: if (dp->suse && dp->duse)
1957: fprintf (f, ",");
1958: if (dp->duse) {
1959: newpc = m68k_getpc () + m68kpc_offset;
1960: newpc += ShowEA (f, dp->dreg, dp->dmode, dp->size, 0);
1961: }
1962: if (ccpt != 0) {
1963: if (cctrue(dp->cc))
1.1.1.5 root 1964: fprintf (f, " == %08lx (TRUE)", (long)newpc);
1.1 root 1965: else
1.1.1.5 root 1966: fprintf (f, " == %08lx (FALSE)", (long)newpc);
1.1 root 1967: } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1.1.1.5 root 1968: fprintf (f, " == %08lx", (long)newpc);
1.1 root 1969: fprintf (f, "\n");
1970: }
1971: if (nextpc)
1972: *nextpc = m68k_getpc () + m68kpc_offset;
1973: }
1974:
1975: void m68k_dumpstate (FILE *f, uaecptr *nextpc)
1976: {
1977: int i;
1978: for (i = 0; i < 8; i++){
1.1.1.5 root 1979: fprintf (f, "D%d: %08lx ", i, (long)m68k_dreg(regs, i));
1.1 root 1980: if ((i & 3) == 3) fprintf (f, "\n");
1981: }
1982: for (i = 0; i < 8; i++){
1.1.1.5 root 1983: fprintf (f, "A%d: %08lx ", i, (long)m68k_areg(regs, i));
1.1 root 1984: if ((i & 3) == 3) fprintf (f, "\n");
1985: }
1986: if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1987: if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1988: if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1989: fprintf (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1.1.1.5 root 1990: (long)regs.usp,(long)regs.isp,(long)regs.msp,(long)regs.vbr);
1.1 root 1991: fprintf (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1992: regs.t1, regs.t0, regs.s, regs.m,
1993: GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1994: for (i = 0; i < 8; i++){
1995: fprintf (f, "FP%d: %g ", i, regs.fp[i]);
1996: if ((i & 3) == 3) fprintf (f, "\n");
1997: }
1998: fprintf (f, "N=%d Z=%d I=%d NAN=%d\n",
1999: (regs.fpsr & 0x8000000) != 0,
2000: (regs.fpsr & 0x4000000) != 0,
2001: (regs.fpsr & 0x2000000) != 0,
2002: (regs.fpsr & 0x1000000) != 0);
1.1.1.12 root 2003: if (currprefs.cpu_compatible)
1.1 root 2004: fprintf (f, "prefetch %08lx\n", (unsigned long)do_get_mem_long(®s.prefetch));
2005:
2006: m68k_disasm (f, m68k_getpc (), nextpc, 1);
2007: if (nextpc)
1.1.1.5 root 2008: fprintf (f, "next PC: %08lx\n", (long)*nextpc);
1.1 root 2009: }
1.1.1.12 root 2010:
2011:
2012: /*
2013:
2014: The routines below take dividend and divisor as parameters.
2015: They return 0 if division by zero, or exact number of cycles otherwise.
2016:
2017: The number of cycles returned assumes a register operand.
2018: Effective address time must be added if memory operand.
2019:
2020: For 68000 only (not 68010, 68012, 68020, etc).
2021: Probably valid for 68008 after adding the extra prefetch cycle.
2022:
2023:
2024: Best and worst cases are for register operand:
2025: (Note the difference with the documented range.)
2026:
2027:
2028: DIVU:
2029:
2030: Overflow (always): 10 cycles.
2031: Worst case: 136 cycles.
2032: Best case: 76 cycles.
2033:
2034:
2035: DIVS:
2036:
2037: Absolute overflow: 16-18 cycles.
2038: Signed overflow is not detected prematurely.
2039:
2040: Worst case: 156 cycles.
2041: Best case without signed overflow: 122 cycles.
2042: Best case with signed overflow: 120 cycles
2043:
2044:
2045: */
2046:
2047:
2048: //
2049: // DIVU
2050: // Unsigned division
2051: //
2052:
2053: STATIC_INLINE int getDivu68kCycles_2 (uae_u32 dividend, uae_u16 divisor)
2054: {
2055: int mcycles;
2056: uae_u32 hdivisor;
2057: int i;
2058:
2059: if (divisor == 0)
2060: return 0;
2061:
2062: // Overflow
2063: if ((dividend >> 16) >= divisor)
2064: return (mcycles = 5) * 2;
2065:
2066: mcycles = 38;
2067: hdivisor = divisor << 16;
2068:
2069: for (i = 0; i < 15; i++) {
2070: uae_u32 temp;
2071: temp = dividend;
2072:
2073: dividend <<= 1;
2074:
2075: // If carry from shift
2076: if ((uae_s32)temp < 0)
2077: dividend -= hdivisor;
2078: else {
2079: mcycles += 2;
2080: if (dividend >= hdivisor) {
2081: dividend -= hdivisor;
2082: mcycles--;
2083: }
2084: }
2085: }
2086: return mcycles * 2;
2087: }
2088: int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor)
2089: {
2090: int v = getDivu68kCycles_2 (dividend, divisor) - 4;
2091: // write_log ("U%d ", v);
2092: return v;
2093: }
2094:
2095: //
2096: // DIVS
2097: // Signed division
2098: //
2099:
2100: STATIC_INLINE int getDivs68kCycles_2 (uae_s32 dividend, uae_s16 divisor)
2101: {
2102: int mcycles;
2103: uae_u32 aquot;
2104: int i;
2105:
2106: if (divisor == 0)
2107: return 0;
2108:
2109: mcycles = 6;
2110:
2111: if (dividend < 0)
2112: mcycles++;
2113:
2114: // Check for absolute overflow
2115: if (((uae_u32)abs (dividend) >> 16) >= (uae_u16)abs (divisor))
2116: return (mcycles + 2) * 2;
2117:
2118: // Absolute quotient
2119: aquot = (uae_u32) abs (dividend) / (uae_u16)abs (divisor);
2120:
2121: mcycles += 55;
2122:
2123: if (divisor >= 0) {
2124: if (dividend >= 0)
2125: mcycles--;
2126: else
2127: mcycles++;
2128: }
2129:
2130: // Count 15 msbits in absolute of quotient
2131:
2132: for (i = 0; i < 15; i++) {
2133: if ((uae_s16)aquot >= 0)
2134: mcycles++;
2135: aquot <<= 1;
2136: }
2137:
2138: return mcycles * 2;
2139: }
2140: int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor)
2141: {
2142: int v = getDivs68kCycles_2 (dividend, divisor) - 4;
2143: // write_log ("S%d ", v);
2144: return v;
2145: }
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