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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation
5: *
6: * (c) 1995 Bernd Schmidt
1.1.1.2 root 7: *
8: * Adaptation to Hatari by Thomas Huth
9: *
1.1.1.19! root 10: * This file is distributed under the GNU General Public License, version 2
! 11: * or at your option any later version. Read the file gpl.txt for details.
1.1 root 12: */
1.1.1.12 root 13:
14:
15: /* 2007/11/12 [NP] Add HATARI_TRACE_CPU_DISASM. */
16: /* 2007/11/15 [NP] In MakeFromSR, writes to m and t0 should be ignored and set to 0 if cpu < 68020 */
17: /* 2007/11/26 [NP] We set BusErrorPC in m68k_run_1 instead of M68000_BusError, else the BusErrorPC */
18: /* will not point to the opcode that generated the bus error. */
19: /* Huge debug/work on Exceptions 2/3 stack frames, result is more accurate and */
20: /* allow to pass the very tricky Transbeauce 2 Demo's protection. */
21: /* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */
22: /* Cwik, [email protected]). */
23: /* 2007/12/06 [NP] The PC stored in the stack frame for the bus error is complex to emulate, */
24: /* because it doesn't necessarily point to the next instruction after the one that */
25: /* triggered the bus error. In the case of the Transbeauce 2 Demo, after */
26: /* 'move.l $0.w,$24.w', PC is incremented of 4 bytes, not 6, and stored in the */
27: /* stack. Special case to decrement PC of 2 bytes if opcode is '21f8'. */
28: /* This should be fixed with a real model. */
29: /* 2007/12/07 [NP] If Trace is enabled and a group 2 exception occurs (such as CHK), the trace */
30: /* handler should be called after the group 2's handler. If a bus error, address */
31: /* error or illegal occurs while Trace is enabled, the trace handler should not be */
32: /* called after this instruction (Transbeauce 2 Demo, Phaleon Demo). */
33: /* This means that if a CHK is executed while trace bit was set, we must set PC */
34: /* to CHK handler, turn trace off in the internal SR, but we must still call the */
35: /* trace handler one last time with the PC set to the CHK's handler (even if */
36: /* trace mode is internally turned off while processing an exception). Once trace */
37: /* handler is finished (RTE), we return to the CHK's handler. */
38: /* This is true for DIV BY 0, CHK, TRAPV and TRAP. */
39: /* Backport exception_trace() from WinUAE to handle this behaviour (used in */
40: /* Transbeauce 2 demo). */
41: /* 2007/12/09 [NP] 'dc.w $a' should not be used to call 'OpCode_SysInit' but should give an illegal*/
42: /* instruction (Transbeauce 2 demo). */
43: /* Instead of always replacing the illegal instructions $8, $a and $c by the */
44: /* 3 functions required for HD emulation, we now do it in cart.c only if the */
45: /* built-in cartridge image is loaded. */
46: /* YEAH! Hatari is now the first emulator to pass the Transbeauce 2 protection :) */
47: /* 2007/12/18 [NP] More precise timings for HBL, VBL and MFP interrupts. On ST, these interrupts */
48: /* are taking 56 cycles instead of the 44 cycles in the 68000's documentation. */
1.1.1.19! root 49: /* 2007/12/24 [NP] If an interrupt (HBL, VBL) is pending after instruction 'n' was processed, the */
1.1.1.12 root 50: /* exception should be called before instr. 'n+1' is processed, not after (else the*/
51: /* interrupt's handler is delayed by one 68000's instruction, which could break */
52: /* some demos with too strict timings) (ACF's Demo Main Menu). */
53: /* We call the interrupt if ( SPCFLAG_INT | SPCFLAG_DOINT ) is set, not only if */
54: /* SPCFLAG_DOINT is set (as it was already the case when handling 'STOP'). */
55: /* 2007/12/25 [NP] FIXME When handling exceptions' cycles, using nr >= 64 to determine if this is */
56: /* an MFP exception could be wrong if the MFP VR was set to another value than the */
57: /* default $40 (this could be a problem with programs requiring a precise cycles */
58: /* calculation while changing VR, but no such programs were encountered so far). */
1.1.1.13 root 59: /* -> FIXED, see 2008/10/05 */
60: /* 2008/04/17 [NP] In m68k_run_1/m68k_run_2, add the wait state cycles before testing if content */
61: /* of PendingInterruptCount is <= 0 (else the int could happen a few cycles earlier*/
62: /* than expected in some rare cases (reading $fffa21 in BIG Demo Screen 1)). */
63: /* 2008/09/14 [NP] Add the value of the new PC in the exception's log. */
64: /* 2008/09/14 [NP] Correct cycles for TRAP are 34 not 38 (4 more cycles were counted because cpuemu*/
65: /* returns 4 and Exception() adds 34) (Phaleon / Illusion Demo by Next). */
66: /* FIXME : Others exception cycles may be wrong too. */
67: /* 2008/10/05 [NP] Add a parameter 'ExceptionSource' to Exception(). This allows to know the source*/
68: /* of the exception (video, mfp, cpu) and properly handle MFP interrupts. Since */
69: /* it's possible to change the vector base in $fffa17, MFP int vectors can overlap */
70: /* the 'normal' 68000 ones and the exception number is not enough to decide. */
71: /* We need ExceptionSource to remove the ambiguity. */
72: /* Fix High Fidelity Dreams by Aura which sets MFP vector base to $c0 instead of */
73: /* $100. In that case, timer B int becomes exception nr 56 and conflicts with the */
74: /* 'MMU config error' exception, which takes 4 cycles instead of 56 cycles for MFP.*/
75: /* 2008/11/18 [NP] In 'do_specialties()', when the cpu is in the STOP state, we must test all */
76: /* possible int handlers while PendingInterruptCount <= 0 without increasing the */
77: /* cpu cycle counter. In the case where both an MFP int and an HBL occur at the */
1.1.1.14 root 78: /* same time for example, the HBL was delayed by 4 cycles if no MFP exception */
1.1.1.13 root 79: /* was triggered, which was wrong (this happened mainly with the TOS timer D that */
80: /* expires very often). Such precision is required for very recent hardscroll */
81: /* techniques that use 'stop' to stay in sync with the video shifter. */
1.1.1.14 root 82: /* 2008/11/23 [NP] In 'do_specialties()', when in STOP state, we must first test for a pending */
1.1.1.19! root 83: /* interrupt that would exit the STOP state immediately, without doing a 'while' */
1.1.1.14 root 84: /* loop until 'SPCFLAG_INT' or 'SPCFLAG_DOINT' are set. */
85: /* 2008/11/29 [NP] Call 'InterruptAddJitter()' when a video interrupt happens to precisely emulate */
86: /* the jitter happening on the Atari (see video.c for the jitter patterns). */
87: /* FIXME : Pattern is not always correct when handling pending interrupt in STOP */
88: /* state, but this should be harmless as no program has been found using this. */
89: /* 2008/12/05 [NP] On Atari it takes 56 cycles to process an interrupt. During that time, a higher */
90: /* level interrupt could happen and we must execute it before the previous int */
91: /* (see m68k_run_1()). */
92: /* This is the case for the VBL which can interrupt the last HBL of a screen */
93: /* (end of line 312) at various point (from 0 to 8 cycles). */
94: /* This fixes the fullscreen tunnel in Suretrip 49% by Checkpoint, which uses a */
95: /* really buggy vbl/hbl combination, even on a real ST. Also fixes sample sound */
96: /* in Swedish New Year's TCB screen. */
97: /* 2008/12/11 [NP] Extract interrupt handling from do_specialties() in do_specialties_interrupt() */
98: /* and factorize some code. In m68k_run_1 when testing for multiple interrupts at */
99: /* the same time, call do_specialties_interrupt() to check only the special flags */
100: /* related to interrupts (MFP and video) (else, this caused problem when the TRACE */
101: /* flag was set). */
102: /* 2008/12/14 [NP] In m68k_run_1(), we should check for simultaneous ints only if the cpu is not */
103: /* in the STOP state after the last instruction was executed. Else, the call to */
104: /* do_specialties_interrupt() could acknowledge the interrupt and we would never */
105: /* exit the STOP state in do_specialties() just after (the problem can happen if */
106: /* the TOS timer D expires just at the same time as the STOP instruction). */
107: /* Fix regression since 2008/12/11 in the hidden screen from ULM in Oh Crickey... */
108: /* 2008/12/20 [NP] In m68k_run_1(), when checking interrupts and STOP mode, we should test */
109: /* PendingInterruptCount before regs.spcflags to have a faster evaluation of the */
110: /* 'while' condition (PendingInterruptCount <= 0 is true less often than STOP==0) */
1.1.1.17 root 111: /* 2011/04/29 [NP] In Exception(), check the new PC is not on odd address ; raise an address error */
112: /* exception if it's the case. */
1.1.1.19! root 113: /* 2013/04/11 [NP] In Exception(), call MFP_ProcessIACK after 12 cycles to update the MFP's vector */
! 114: /* number used for the exception (see mfp.c). */
! 115: /* 2013/05/03 [NP] In Exception(), handle IACK for HBL and VBL interrupts too, allowing pending bit*/
! 116: /* to be set twice during an active video interrupt (correct fix for Super Monaco */
! 117: /* GP, Super Hang On, Monster Business, European Demo's Intro, BBC Menu 52). */
1.1.1.12 root 118:
119:
1.1.1.15 root 120: const char NewCpu_fileid[] = "Hatari newcpu.c : " __DATE__ " " __TIME__;
1.1 root 121:
122: #include "sysdeps.h"
123: #include "hatari-glue.h"
124: #include "maccess.h"
125: #include "memory.h"
126: #include "newcpu.h"
1.1.1.16 root 127: #include "main.h"
128: #include "m68000.h"
129: #include "cycInt.h"
130: #include "mfp.h"
131: #include "tos.h"
132: #include "vdi.h"
133: #include "cart.h"
134: #include "dialog.h"
135: #include "bios.h"
136: #include "xbios.h"
1.1.1.17 root 137: #include "screen.h"
1.1.1.16 root 138: #include "video.h"
139: #include "options.h"
140: #include "dsp.h"
141: #include "log.h"
142: #include "debugui.h"
143: #include "debugcpu.h"
1.1.1.17 root 144: #include "68kDisass.h"
1.1 root 145:
1.1.1.12 root 146: //#define DEBUG_PREFETCH
1.1 root 147:
148: struct flag_struct regflags;
149:
150: /* Opcode of faulting instruction */
151: uae_u16 last_op_for_exception_3;
152: /* PC at fault time */
153: uaecptr last_addr_for_exception_3;
154: /* Address that generated the exception */
155: uaecptr last_fault_for_exception_3;
156:
1.1.1.11 root 157: const int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
158: const int imm8_table[] = { 8,1,2,3,4,5,6,7 };
1.1 root 159:
160: int movem_index1[256];
161: int movem_index2[256];
162: int movem_next[256];
163:
164: int fpp_movem_index1[256];
165: int fpp_movem_index2[256];
166: int fpp_movem_next[256];
167:
168: cpuop_func *cpufunctbl[65536];
169:
1.1.1.12 root 170: int OpcodeFamily;
1.1.1.16 root 171: int BusCyclePenalty = 0;
1.1.1.6 root 172:
1.1 root 173: #define COUNT_INSTRS 0
174:
175: #if COUNT_INSTRS
176: static unsigned long int instrcount[65536];
177: static uae_u16 opcodenums[65536];
178:
179: static int compfn (const void *el1, const void *el2)
180: {
181: return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
182: }
183:
184: static char *icountfilename (void)
185: {
186: char *name = getenv ("INSNCOUNT");
187: if (name)
188: return name;
189: return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
190: }
191:
192: void dump_counts (void)
193: {
194: FILE *f = fopen (icountfilename (), "w");
195: unsigned long int total;
196: int i;
197:
198: write_log ("Writing instruction count file...\n");
199: for (i = 0; i < 65536; i++) {
200: opcodenums[i] = i;
201: total += instrcount[i];
202: }
203: qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
204:
205: fprintf (f, "Total: %lu\n", total);
206: for (i=0; i < 65536; i++) {
207: unsigned long int cnt = instrcount[opcodenums[i]];
208: struct instr *dp;
209: struct mnemolookup *lookup;
210: if (!cnt)
211: break;
212: dp = table68k + opcodenums[i];
213: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
214: ;
215: fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
216: }
217: fclose (f);
218: }
219: #else
220: void dump_counts (void)
221: {
222: }
223: #endif
224:
225:
226: static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM;
227:
228: static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
229: {
1.1.1.6 root 230: op_illg (opcode);
1.1 root 231: return 4;
232: }
233:
1.1.1.4 root 234:
235: void build_cpufunctbl(void)
1.1 root 236: {
237: int i;
238: unsigned long opcode;
1.1.1.12 root 239: const struct cputbl *tbl = (currprefs.cpu_level == 4 ? op_smalltbl_0_ff
240: : currprefs.cpu_level == 3 ? op_smalltbl_1_ff
241: : currprefs.cpu_level == 2 ? op_smalltbl_2_ff
242: : currprefs.cpu_level == 1 ? op_smalltbl_3_ff
243: : ! currprefs.cpu_compatible ? op_smalltbl_4_ff
1.1.1.11 root 244: : op_smalltbl_5_ff);
1.1 root 245:
1.1.1.10 root 246: Log_Printf(LOG_DEBUG, "Building CPU function table (%d %d %d).\n",
1.1.1.12 root 247: currprefs.cpu_level, currprefs.cpu_compatible, currprefs.address_space_24);
1.1 root 248:
249: for (opcode = 0; opcode < 65536; opcode++)
1.1.1.6 root 250: cpufunctbl[opcode] = op_illg_1;
1.1 root 251: for (i = 0; tbl[i].handler != NULL; i++) {
252: if (! tbl[i].specific)
1.1.1.6 root 253: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 254: }
255: for (opcode = 0; opcode < 65536; opcode++) {
256: cpuop_func *f;
257:
1.1.1.12 root 258: if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > currprefs.cpu_level)
1.1 root 259: continue;
260:
261: if (table68k[opcode].handler != -1) {
1.1.1.6 root 262: f = cpufunctbl[table68k[opcode].handler];
1.1 root 263: if (f == op_illg_1)
264: abort();
1.1.1.6 root 265: cpufunctbl[opcode] = f;
1.1 root 266: }
267: }
268: for (i = 0; tbl[i].handler != NULL; i++) {
269: if (tbl[i].specific)
1.1.1.6 root 270: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 271: }
272: }
273:
274:
275:
276: void init_m68k (void)
277: {
278: int i;
279:
280: for (i = 0 ; i < 256 ; i++) {
281: int j;
282: for (j = 0 ; j < 8 ; j++) {
283: if (i & (1 << j)) break;
284: }
285: movem_index1[i] = j;
286: movem_index2[i] = 7-j;
287: movem_next[i] = i & (~(1 << j));
288: }
289: for (i = 0 ; i < 256 ; i++) {
290: int j;
291: for (j = 7 ; j >= 0 ; j--) {
292: if (i & (1 << j)) break;
293: }
294: fpp_movem_index1[i] = 7-j;
295: fpp_movem_index2[i] = j;
296: fpp_movem_next[i] = i & (~(1 << j));
297: }
298: #if COUNT_INSTRS
299: {
300: FILE *f = fopen (icountfilename (), "r");
301: memset (instrcount, 0, sizeof instrcount);
302: if (f) {
303: uae_u32 opcode, count, total;
304: char name[20];
305: write_log ("Reading instruction count file...\n");
306: fscanf (f, "Total: %lu\n", &total);
307: while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
308: instrcount[opcode] = count;
309: }
310: fclose(f);
311: }
312: }
313: #endif
314: write_log ("Building CPU table for configuration: 68");
1.1.1.12 root 315: if (currprefs.address_space_24 && currprefs.cpu_level > 1)
1.1 root 316: write_log ("EC");
1.1.1.12 root 317: switch (currprefs.cpu_level) {
1.1 root 318: case 1:
319: write_log ("010");
320: break;
321: case 2:
322: write_log ("020");
323: break;
324: case 3:
325: write_log ("020/881");
326: break;
327: case 4:
328: /* Who is going to miss the MMU anyway...? :-) */
329: write_log ("040");
330: break;
331: default:
332: write_log ("000");
333: break;
334: }
1.1.1.12 root 335: if (currprefs.cpu_compatible)
1.1 root 336: write_log (" (compatible mode)");
337: write_log ("\n");
1.1.1.7 root 338:
1.1 root 339: read_table68k ();
340: do_merges ();
341:
1.1.1.10 root 342: Log_Printf(LOG_DEBUG, "%d CPU functions\n", nr_cpuop_funcs);
1.1 root 343:
344: build_cpufunctbl ();
345: }
346:
1.1.1.4 root 347:
1.1.1.8 root 348: /* not used ATM:
1.1 root 349: static struct regstruct regs_backup[16];
350: static int backup_pointer = 0;
1.1.1.10 root 351: struct regstruct lastint_regs;
352: int lastint_no;
1.1.1.8 root 353: */
1.1.1.10 root 354: struct regstruct regs;
1.1 root 355: static long int m68kpc_offset;
1.1.1.10 root 356:
1.1 root 357:
358: #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
359: #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
360: #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
361:
362: uae_s32 ShowEA (FILE *f, int reg, amodes mode, wordsizes size, char *buf)
363: {
364: uae_u16 dp;
365: uae_s8 disp8;
366: uae_s16 disp16;
367: int r;
368: uae_u32 dispreg;
369: uaecptr addr;
370: uae_s32 offset = 0;
371: char buffer[80];
372:
373: switch (mode){
374: case Dreg:
375: sprintf (buffer,"D%d", reg);
376: break;
377: case Areg:
378: sprintf (buffer,"A%d", reg);
379: break;
380: case Aind:
381: sprintf (buffer,"(A%d)", reg);
382: break;
383: case Aipi:
384: sprintf (buffer,"(A%d)+", reg);
385: break;
386: case Apdi:
387: sprintf (buffer,"-(A%d)", reg);
388: break;
389: case Ad16:
390: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
391: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
392: sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
393: (unsigned long)addr);
394: break;
395: case Ad8r:
396: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
397: disp8 = dp & 0xFF;
398: r = (dp & 0x7000) >> 12;
399: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
400: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
401: dispreg <<= (dp >> 9) & 3;
402:
403: if (dp & 0x100) {
404: uae_s32 outer = 0, disp = 0;
405: uae_s32 base = m68k_areg(regs,reg);
406: char name[10];
407: sprintf (name,"A%d, ",reg);
408: if (dp & 0x80) { base = 0; name[0] = 0; }
409: if (dp & 0x40) dispreg = 0;
410: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
411: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
412: base += disp;
413:
414: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
415: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
416:
417: if (!(dp & 4)) base += dispreg;
418: if (dp & 3) base = get_long (base);
419: if (dp & 4) base += dispreg;
420:
421: addr = base + outer;
422: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
423: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
424: 1 << ((dp >> 9) & 3),
1.1.1.5 root 425: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 426: } else {
427: addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
428: sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
429: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
430: 1 << ((dp >> 9) & 3), disp8,
431: (unsigned long)addr);
432: }
433: break;
434: case PC16:
435: addr = m68k_getpc () + m68kpc_offset;
436: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
437: addr += (uae_s16)disp16;
438: sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
439: break;
440: case PC8r:
441: addr = m68k_getpc () + m68kpc_offset;
442: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
443: disp8 = dp & 0xFF;
444: r = (dp & 0x7000) >> 12;
445: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
446: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
447: dispreg <<= (dp >> 9) & 3;
448:
449: if (dp & 0x100) {
450: uae_s32 outer = 0,disp = 0;
451: uae_s32 base = addr;
452: char name[10];
453: sprintf (name,"PC, ");
454: if (dp & 0x80) { base = 0; name[0] = 0; }
455: if (dp & 0x40) dispreg = 0;
456: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
457: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
458: base += disp;
459:
460: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
461: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
462:
463: if (!(dp & 4)) base += dispreg;
464: if (dp & 3) base = get_long (base);
465: if (dp & 4) base += dispreg;
466:
467: addr = base + outer;
468: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
469: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
470: 1 << ((dp >> 9) & 3),
1.1.1.5 root 471: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 472: } else {
473: addr += (uae_s32)((uae_s8)disp8) + dispreg;
474: sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
475: (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
476: disp8, (unsigned long)addr);
477: }
478: break;
479: case absw:
480: sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
481: m68kpc_offset += 2;
482: break;
483: case absl:
484: sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
485: m68kpc_offset += 4;
486: break;
487: case imm:
488: switch (size){
489: case sz_byte:
490: sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
491: m68kpc_offset += 2;
492: break;
493: case sz_word:
494: sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
495: m68kpc_offset += 2;
496: break;
497: case sz_long:
498: sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
499: m68kpc_offset += 4;
500: break;
501: default:
502: break;
503: }
504: break;
505: case imm0:
506: offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
507: m68kpc_offset += 2;
508: sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
509: break;
510: case imm1:
511: offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
512: m68kpc_offset += 2;
513: sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
514: break;
515: case imm2:
516: offset = (uae_s32)get_ilong_1 (m68kpc_offset);
517: m68kpc_offset += 4;
518: sprintf (buffer,"#$%08lx", (unsigned long)offset);
519: break;
520: case immi:
521: offset = (uae_s32)(uae_s8)(reg & 0xff);
522: sprintf (buffer,"#$%08lx", (unsigned long)offset);
523: break;
524: default:
525: break;
526: }
527: if (buf == 0)
528: fprintf (f, "%s", buffer);
529: else
530: strcat (buf, buffer);
531: return offset;
532: }
533:
1.1.1.8 root 534:
1.1 root 535: /* The plan is that this will take over the job of exception 3 handling -
536: * the CPU emulation functions will just do a longjmp to m68k_go whenever
537: * they hit an odd address. */
1.1.1.8 root 538: #if 0
1.1 root 539: static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
540: {
541: uae_u16 dp;
542: uae_s8 disp8;
543: uae_s16 disp16;
544: int r;
545: uae_u32 dispreg;
546: uaecptr addr;
1.1.1.5 root 547: /*uae_s32 offset = 0;*/
1.1 root 548:
549: switch (mode){
550: case Dreg:
551: *val = m68k_dreg (regs, reg);
552: return 1;
553: case Areg:
554: *val = m68k_areg (regs, reg);
555: return 1;
556:
557: case Aind:
558: case Aipi:
559: addr = m68k_areg (regs, reg);
560: break;
561: case Apdi:
562: addr = m68k_areg (regs, reg);
563: break;
564: case Ad16:
565: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
566: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
567: break;
568: case Ad8r:
569: addr = m68k_areg (regs, reg);
570: d8r_common:
571: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
572: disp8 = dp & 0xFF;
573: r = (dp & 0x7000) >> 12;
574: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
575: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
576: dispreg <<= (dp >> 9) & 3;
577:
578: if (dp & 0x100) {
579: uae_s32 outer = 0, disp = 0;
580: uae_s32 base = addr;
581: if (dp & 0x80) base = 0;
582: if (dp & 0x40) dispreg = 0;
583: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
584: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
585: base += disp;
586:
587: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
588: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
589:
590: if (!(dp & 4)) base += dispreg;
591: if (dp & 3) base = get_long (base);
592: if (dp & 4) base += dispreg;
593:
594: addr = base + outer;
595: } else {
596: addr += (uae_s32)((uae_s8)disp8) + dispreg;
597: }
598: break;
599: case PC16:
600: addr = m68k_getpc () + m68kpc_offset;
601: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
602: addr += (uae_s16)disp16;
603: break;
604: case PC8r:
605: addr = m68k_getpc () + m68kpc_offset;
606: goto d8r_common;
607: case absw:
608: addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
609: m68kpc_offset += 2;
610: break;
611: case absl:
612: addr = get_ilong_1 (m68kpc_offset);
613: m68kpc_offset += 4;
614: break;
615: case imm:
616: switch (size){
617: case sz_byte:
618: *val = get_iword_1 (m68kpc_offset) & 0xff;
619: m68kpc_offset += 2;
620: break;
621: case sz_word:
622: *val = get_iword_1 (m68kpc_offset) & 0xffff;
623: m68kpc_offset += 2;
624: break;
625: case sz_long:
626: *val = get_ilong_1 (m68kpc_offset);
627: m68kpc_offset += 4;
628: break;
629: default:
630: break;
631: }
632: return 1;
633: case imm0:
634: *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
635: m68kpc_offset += 2;
636: return 1;
637: case imm1:
638: *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
639: m68kpc_offset += 2;
640: return 1;
641: case imm2:
642: *val = get_ilong_1 (m68kpc_offset);
643: m68kpc_offset += 4;
644: return 1;
645: case immi:
646: *val = (uae_s32)(uae_s8)(reg & 0xff);
647: return 1;
648: default:
649: addr = 0;
650: break;
651: }
652: if ((addr & 1) == 0)
653: return 1;
654:
655: last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
656: last_fault_for_exception_3 = addr;
657: return 0;
658: }
1.1.1.8 root 659: #endif
660:
1.1 root 661:
662: uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
663: {
664: int reg = (dp >> 12) & 15;
665: uae_s32 regd = regs.regs[reg];
666: if ((dp & 0x800) == 0)
667: regd = (uae_s32)(uae_s16)regd;
668: regd <<= (dp >> 9) & 3;
669: if (dp & 0x100) {
670: uae_s32 outer = 0;
671: if (dp & 0x80) base = 0;
672: if (dp & 0x40) regd = 0;
673:
674: if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
675: if ((dp & 0x30) == 0x30) base += next_ilong();
676:
677: if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
678: if ((dp & 0x3) == 0x3) outer = next_ilong();
679:
680: if ((dp & 0x4) == 0) base += regd;
681: if (dp & 0x3) base = get_long (base);
682: if (dp & 0x4) base += regd;
683:
684: return base + outer;
685: } else {
686: return base + (uae_s32)((uae_s8)dp) + regd;
687: }
688: }
689:
690: uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
691: {
692: int reg = (dp >> 12) & 15;
693: uae_s32 regd = regs.regs[reg];
694: #if 1
695: if ((dp & 0x800) == 0)
696: regd = (uae_s32)(uae_s16)regd;
697: return base + (uae_s8)dp + regd;
698: #else
699: /* Branch-free code... benchmark this again now that
700: * things are no longer inline. */
701: uae_s32 regd16;
702: uae_u32 mask;
703: mask = ((dp & 0x800) >> 11) - 1;
704: regd16 = (uae_s32)(uae_s16)regd;
705: regd16 &= mask;
706: mask = ~mask;
707: base += (uae_s8)dp;
708: regd &= mask;
709: regd |= regd16;
710: return base + regd;
711: #endif
712: }
713:
1.1.1.8 root 714:
715: /* Create the Status Register from the flags */
1.1 root 716: void MakeSR (void)
717: {
718: #if 0
719: assert((regs.t1 & 1) == regs.t1);
720: assert((regs.t0 & 1) == regs.t0);
721: assert((regs.s & 1) == regs.s);
722: assert((regs.m & 1) == regs.m);
723: assert((XFLG & 1) == XFLG);
724: assert((NFLG & 1) == NFLG);
725: assert((ZFLG & 1) == ZFLG);
726: assert((VFLG & 1) == VFLG);
727: assert((CFLG & 1) == CFLG);
728: #endif
729: regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
730: | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
731: | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
732: | GET_CFLG);
733: }
734:
1.1.1.8 root 735:
736: /* Set up the flags from Status Register */
1.1 root 737: void MakeFromSR (void)
738: {
739: int oldm = regs.m;
740: int olds = regs.s;
741:
742: regs.t1 = (regs.sr >> 15) & 1;
743: regs.t0 = (regs.sr >> 14) & 1;
744: regs.s = (regs.sr >> 13) & 1;
745: regs.m = (regs.sr >> 12) & 1;
746: regs.intmask = (regs.sr >> 8) & 7;
747: SET_XFLG ((regs.sr >> 4) & 1);
748: SET_NFLG ((regs.sr >> 3) & 1);
749: SET_ZFLG ((regs.sr >> 2) & 1);
750: SET_VFLG ((regs.sr >> 1) & 1);
751: SET_CFLG (regs.sr & 1);
1.1.1.12 root 752: if (currprefs.cpu_level >= 2) {
1.1 root 753: if (olds != regs.s) {
754: if (olds) {
755: if (oldm)
756: regs.msp = m68k_areg(regs, 7);
757: else
758: regs.isp = m68k_areg(regs, 7);
759: m68k_areg(regs, 7) = regs.usp;
760: } else {
761: regs.usp = m68k_areg(regs, 7);
762: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
763: }
764: } else if (olds && oldm != regs.m) {
765: if (oldm) {
766: regs.msp = m68k_areg(regs, 7);
767: m68k_areg(regs, 7) = regs.isp;
768: } else {
769: regs.isp = m68k_areg(regs, 7);
770: m68k_areg(regs, 7) = regs.msp;
771: }
772: }
773: } else {
1.1.1.12 root 774: /* [NP] If cpu < 68020, m and t0 are ignored and should be set to 0 */
775: regs.t0 = 0;
776: regs.m = 0;
777:
1.1 root 778: if (olds != regs.s) {
779: if (olds) {
780: regs.isp = m68k_areg(regs, 7);
781: m68k_areg(regs, 7) = regs.usp;
782: } else {
783: regs.usp = m68k_areg(regs, 7);
784: m68k_areg(regs, 7) = regs.isp;
785: }
786: }
787: }
788:
1.1.1.8 root 789: /* Pending interrupts can occur again after a write to the SR: */
790: set_special (SPCFLAG_DOINT);
1.1 root 791: if (regs.t1 || regs.t0)
792: set_special (SPCFLAG_TRACE);
793: else
1.1.1.6 root 794: /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
795: SR-modifying instructions (including STOP). */
796: unset_special (SPCFLAG_TRACE);
1.1 root 797: }
798:
1.1.1.5 root 799:
1.1.1.12 root 800: static void exception_trace (int nr)
801: {
802: unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
803: if (regs.t1 && !regs.t0) {
804: /* trace stays pending if exception is div by zero, chk,
805: * trapv or trap #x
806: */
807: if (nr == 5 || nr == 6 || nr == 7 || (nr >= 32 && nr <= 47))
808: set_special (SPCFLAG_DOTRACE);
809: }
810: regs.t1 = regs.t0 = regs.m = 0;
811: }
812:
813:
1.1.1.14 root 814: /*
815: * Compute the number of jitter cycles to add when a video interrupt occurs
816: * (this is specific to the Atari ST)
817: */
818: static void InterruptAddJitter (int Level , int Pending)
819: {
820: int cycles = 0;
821:
822: if ( Level == 2 ) /* HBL */
823: {
824: if ( Pending )
825: cycles = HblJitterArrayPending[ HblJitterIndex ];
826: else
827: cycles = HblJitterArray[ HblJitterIndex ];
828: }
829:
830: else if ( Level == 4 ) /* VBL */
831: {
832: if ( Pending )
833: cycles = VblJitterArrayPending[ VblJitterIndex ];
834: else
835: cycles = VblJitterArray[ VblJitterIndex ];
836: }
837:
838: //fprintf ( stderr , "jitter %d\n" , cycles );
839: //cycles=0;
840: if ( cycles > 0 ) /* no need to call M68000_AddCycles if cycles == 0 */
841: M68000_AddCycles ( cycles );
842: }
843:
844:
1.1.1.13 root 845: /* Handle exceptions. We need a special case to handle MFP exceptions */
846: /* on Atari ST, because it's possible to change the MFP's vector base */
847: /* and get a conflict with 'normal' cpu exceptions. */
848: void Exception(int nr, uaecptr oldpc, int ExceptionSource)
1.1 root 849: {
1.1.1.17 root 850: uae_u32 currpc = m68k_getpc () , newpc;
1.1 root 851:
1.1.1.2 root 852: /*if( nr>=2 && nr<10 ) fprintf(stderr,"Exception (-> %i bombs)!\n",nr);*/
1.1 root 853:
1.1.1.19! root 854: /* Pending bits / vector number can change before the end of the IACK sequence. */
! 855: /* We need to handle MFP and HBL/VBL cases for this. */
! 856: if ( ExceptionSource == M68000_EXC_SRC_INT_MFP )
! 857: {
! 858: M68000_AddCycles ( CPU_IACK_CYCLES_MFP );
! 859: CPU_IACK = true;
! 860: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
! 861: CALL_VAR(PendingInterruptFunction);
! 862: nr = MFP_ProcessIACK ( nr );
! 863: CPU_IACK = false;
! 864: }
! 865: else if ( 1 && ( ExceptionSource == M68000_EXC_SRC_AUTOVEC ) && ( ( nr == 26 ) || ( nr == 28 ) ) )
! 866: {
! 867: M68000_AddCycles ( CPU_IACK_CYCLES_VIDEO );
! 868: CPU_IACK = true;
! 869: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
! 870: CALL_VAR(PendingInterruptFunction);
! 871: pendingInterrupts &= ~( 1 << ( nr - 24 ) ); /* clear HBL or VBL pending bit */
! 872: CPU_IACK = false;
! 873: }
! 874:
! 875:
1.1.1.16 root 876: if (ExceptionSource == M68000_EXC_SRC_CPU)
1.1.1.5 root 877: {
1.1.1.17 root 878: if (bVdiAesIntercept && nr == 0x22)
1.1.1.13 root 879: {
1.1.1.17 root 880: /* Intercept VDI & AES exceptions (Trap #2) */
881: if(VDI_AES_Entry())
1.1.1.13 root 882: {
1.1.1.17 root 883: /* Set 'PC' to address of 'VDI_OPCODE' illegal instruction.
884: * This will call OpCode_VDI() after completion of Trap call!
885: * This is used to modify specific VDI return vectors contents.
886: */
1.1.1.13 root 887: VDI_OldPC = currpc;
888: currpc = CART_VDI_OPCODE_ADDR;
889: }
890: }
1.1.1.16 root 891:
1.1.1.13 root 892: if (bBiosIntercept)
893: {
894: /* Intercept BIOS or XBIOS trap (Trap #13 or #14) */
895: if (nr == 0x2d)
896: {
897: /* Intercept BIOS calls */
898: if (Bios()) return;
899: }
900: else if (nr == 0x2e)
901: {
902: /* Intercept XBIOS calls */
903: if (XBios()) return;
904: }
905: }
1.1.1.5 root 906: }
1.1.1.8 root 907:
1.1 root 908: MakeSR();
909:
1.1.1.8 root 910: /* Change to supervisor mode if necessary */
1.1 root 911: if (!regs.s) {
912: regs.usp = m68k_areg(regs, 7);
1.1.1.12 root 913: if (currprefs.cpu_level >= 2)
1.1 root 914: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
915: else
916: m68k_areg(regs, 7) = regs.isp;
917: regs.s = 1;
918: }
1.1.1.8 root 919:
920: /* Build additional exception stack frame for 68010 and higher */
1.1.1.13 root 921: /* (special case for MFP) */
1.1.1.12 root 922: if (currprefs.cpu_level > 0) {
1.1.1.16 root 923: if (ExceptionSource == M68000_EXC_SRC_INT_MFP
924: || ExceptionSource == M68000_EXC_SRC_INT_DSP) {
1.1.1.13 root 925: m68k_areg(regs, 7) -= 2;
926: put_word (m68k_areg(regs, 7), nr * 4); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
927: }
928: else if (nr == 2 || nr == 3) {
1.1 root 929: int i;
930: /* @@@ this is probably wrong (?) */
931: for (i = 0 ; i < 12 ; i++) {
932: m68k_areg(regs, 7) -= 2;
933: put_word (m68k_areg(regs, 7), 0);
934: }
935: m68k_areg(regs, 7) -= 2;
936: put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
937: } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
938: m68k_areg(regs, 7) -= 4;
939: put_long (m68k_areg(regs, 7), oldpc);
940: m68k_areg(regs, 7) -= 2;
941: put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
942: } else if (regs.m && nr >= 24 && nr < 32) {
943: m68k_areg(regs, 7) -= 2;
944: put_word (m68k_areg(regs, 7), nr * 4);
945: m68k_areg(regs, 7) -= 4;
946: put_long (m68k_areg(regs, 7), currpc);
947: m68k_areg(regs, 7) -= 2;
948: put_word (m68k_areg(regs, 7), regs.sr);
949: regs.sr |= (1 << 13);
950: regs.msp = m68k_areg(regs, 7);
951: m68k_areg(regs, 7) = regs.isp;
952: m68k_areg(regs, 7) -= 2;
953: put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
954: } else {
955: m68k_areg(regs, 7) -= 2;
956: put_word (m68k_areg(regs, 7), nr * 4);
957: }
958: }
1.1.1.3 root 959:
960: /* Push PC on stack: */
1.1 root 961: m68k_areg(regs, 7) -= 4;
962: put_long (m68k_areg(regs, 7), currpc);
1.1.1.3 root 963: /* Push SR on stack: */
1.1 root 964: m68k_areg(regs, 7) -= 2;
965: put_word (m68k_areg(regs, 7), regs.sr);
1.1.1.3 root 966:
1.1.1.15 root 967: LOG_TRACE(TRACE_CPU_EXCEPTION, "cpu exception %d currpc %x buspc %x newpc %x fault_e3 %x op_e3 %hx addr_e3 %x\n",
968: nr, currpc, BusErrorPC, get_long (regs.vbr + 4*nr), last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3);
1.1.1.12 root 969:
1.1.1.3 root 970: /* 68000 bus/address errors: */
1.1.1.16 root 971: if (currprefs.cpu_level==0 && (nr==2 || nr==3) && ExceptionSource == M68000_EXC_SRC_CPU) {
1.1.1.12 root 972: uae_u16 specialstatus = 1;
973:
1.1.1.8 root 974: /* Special status word emulation isn't perfect yet... :-( */
975: if (regs.sr & 0x2000)
976: specialstatus |= 0x4;
1.1.1.3 root 977: m68k_areg(regs, 7) -= 8;
978: if (nr == 3) { /* Address error */
1.1.1.12 root 979: specialstatus |= ( last_op_for_exception_3 & (~0x1f) ); /* [NP] unused bits of specialstatus are those of the last opcode ! */
1.1.1.8 root 980: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.3 root 981: put_long (m68k_areg(regs, 7)+2, last_fault_for_exception_3);
982: put_word (m68k_areg(regs, 7)+6, last_op_for_exception_3);
983: put_long (m68k_areg(regs, 7)+10, last_addr_for_exception_3);
1.1.1.15 root 984: if (bExceptionDebugging) {
1.1.1.8 root 985: fprintf(stderr,"Address Error at address $%x, PC=$%x\n",last_fault_for_exception_3,currpc);
1.1.1.18 root 986: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.8 root 987: }
1.1.1.3 root 988: }
1.1.1.8 root 989: else { /* Bus error */
1.1.1.12 root 990: specialstatus |= ( get_word(BusErrorPC) & (~0x1f) ); /* [NP] unused bits of special status are those of the last opcode ! */
1.1.1.8 root 991: if (bBusErrorReadWrite)
992: specialstatus |= 0x10;
993: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.10 root 994: put_long (m68k_areg(regs, 7)+2, BusErrorAddress);
1.1.1.12 root 995: put_word (m68k_areg(regs, 7)+6, get_word(BusErrorPC)); /* Opcode */
996:
997: /* [NP] PC stored in the stack frame is not necessarily pointing to the next instruction ! */
998: /* FIXME : we should have a proper model for this, in the meantime we handle specific cases */
1.1.1.16 root 999: if ( get_word(BusErrorPC) == 0x21f8 ) /* move.l $0.w,$24.w (Transbeauce 2 loader) */
1.1.1.12 root 1000: put_long (m68k_areg(regs, 7)+10, currpc-2); /* correct PC is 2 bytes less than usual value */
1.1.1.8 root 1001: /* Check for double bus errors: */
1002: if (regs.spcflags & SPCFLAG_BUSERROR) {
1003: fprintf(stderr, "Detected double bus error at address $%x, PC=$%lx => CPU halted!\n",
1.1.1.10 root 1004: BusErrorAddress, (long)currpc);
1.1.1.8 root 1005: unset_special(SPCFLAG_BUSERROR);
1.1.1.15 root 1006: if (bExceptionDebugging)
1.1.1.18 root 1007: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.15 root 1008: else
1.1.1.17 root 1009: DlgAlert_Notice("Detected double bus error => CPU halted!\nEmulation needs to be reset.\n");
1.1.1.8 root 1010: regs.intmask = 7;
1.1.1.15 root 1011: m68k_setstopped(true);
1.1.1.8 root 1012: return;
1013: }
1.1.1.15 root 1014: if (bExceptionDebugging && BusErrorAddress!=0xff8a00) {
1.1.1.10 root 1015: fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n", BusErrorAddress, (long)currpc);
1.1.1.18 root 1016: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.8 root 1017: }
1018: }
1.1.1.3 root 1019: }
1020:
1.1.1.8 root 1021: /* Set PC and flags */
1.1.1.15 root 1022: if (bExceptionDebugging && get_long (regs.vbr + 4*nr) == 0) {
1.1.1.8 root 1023: write_log("Uninitialized exception handler #%i!\n", nr);
1.1.1.18 root 1024: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.8 root 1025: }
1.1.1.17 root 1026: newpc = get_long (regs.vbr + 4*nr);
1027: if ( newpc & 1) /* check new pc is even */
1028: {
1029: if ( nr==2 || nr==3 ) /* address error during bus/address error -> stop emulation */
1030: {
1031: fprintf(stderr,"Address Error during exception 2/3, aborting new PC=$%x\n",newpc);
1.1.1.18 root 1032: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.17 root 1033: }
1034: else
1035: {
1036: fprintf(stderr,"Address Error during exception, new PC=$%x\n",newpc);
1037: Exception ( 3 , m68k_getpc() , M68000_EXC_SRC_CPU );
1038: }
1039: return;
1040: }
1041:
1.1 root 1042: m68k_setpc (get_long (regs.vbr + 4*nr));
1043: fill_prefetch_0 ();
1.1.1.12 root 1044: /* Handle trace flags depending on current state */
1045: exception_trace (nr);
1.1.1.6 root 1046:
1.1.1.13 root 1047: /* Handle exception cycles (special case for MFP) */
1.1.1.16 root 1048: if (ExceptionSource == M68000_EXC_SRC_INT_MFP)
1.1.1.13 root 1049: {
1.1.1.19! root 1050: M68000_AddCycles(44+12-CPU_IACK_CYCLES_MFP); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
1.1.1.13 root 1051: }
1052: else if (nr >= 24 && nr <= 31)
1.1.1.7 root 1053: {
1.1.1.19! root 1054: if ( nr == 26 ) /* HBL */
! 1055: M68000_AddCycles(44+12-CPU_IACK_CYCLES_VIDEO); /* Video Interrupt */
! 1056: else if ( nr == 28 ) /* VBL */
! 1057: M68000_AddCycles(44+12-CPU_IACK_CYCLES_VIDEO); /* Video Interrupt */
1.1.1.12 root 1058: else
1.1.1.19! root 1059: M68000_AddCycles(44+4); /* Other Interrupts */
1.1.1.7 root 1060: }
1061: else if(nr >= 32 && nr <= 47)
1062: {
1.1.1.13 root 1063: M68000_AddCycles(34-4); /* Trap (total is 34, but cpuemu.c already adds 4) */
1.1.1.7 root 1064: }
1065: else switch(nr)
1066: {
1.1.1.12 root 1067: case 2: M68000_AddCycles(50); break; /* Bus error */
1068: case 3: M68000_AddCycles(50); break; /* Address error */
1069: case 4: M68000_AddCycles(34); break; /* Illegal instruction */
1070: case 5: M68000_AddCycles(38); break; /* Div by zero */
1071: case 6: M68000_AddCycles(40); break; /* CHK */
1072: case 7: M68000_AddCycles(34); break; /* TRAPV */
1073: case 8: M68000_AddCycles(34); break; /* Privilege violation */
1074: case 9: M68000_AddCycles(34); break; /* Trace */
1075: case 10: M68000_AddCycles(34); break; /* Line-A - probably wrong */
1076: case 11: M68000_AddCycles(34); break; /* Line-F - probably wrong */
1.1.1.7 root 1077: default:
1.1.1.8 root 1078: /* FIXME: Add right cycles value for MFP interrupts and copro exceptions ... */
1.1.1.7 root 1079: if(nr < 64)
1.1.1.12 root 1080: M68000_AddCycles(4); /* Coprocessor and unassigned exceptions (???) */
1.1.1.7 root 1081: else
1.1.1.16 root 1082: M68000_AddCycles(44+12); /* Must be a MFP or DSP interrupt */
1.1.1.7 root 1083: break;
1.1.1.6 root 1084: }
1.1.1.14 root 1085:
1.1 root 1086: }
1087:
1.1.1.7 root 1088:
1.1.1.14 root 1089: static void Interrupt(int nr , int Pending)
1.1 root 1090: {
1091: assert(nr < 8 && nr >= 0);
1.1.1.10 root 1092: /*lastint_regs = regs;*/
1093: /*lastint_no = nr;*/
1.1.1.13 root 1094:
1.1.1.16 root 1095: /* On Hatari, only video ints are using SPCFLAG_INT (see m68000.c) */
1096: Exception(nr+24, 0, M68000_EXC_SRC_AUTOVEC);
1.1 root 1097:
1098: regs.intmask = nr;
1099: set_special (SPCFLAG_INT);
1.1.1.14 root 1100:
1101: /* Handle Atari ST's specific jitter for hbl/vbl */
1102: InterruptAddJitter ( nr , Pending );
1.1 root 1103: }
1104:
1.1.1.7 root 1105:
1.1.1.12 root 1106: uae_u32 caar, cacr;
1.1.1.8 root 1107: static uae_u32 itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp;
1.1 root 1108:
1.1.1.7 root 1109:
1.1.1.12 root 1110: static int movec_illg (int regno)
1111: {
1112: int regno2 = regno & 0x7ff;
1113: if (currprefs.cpu_level == 1) { /* 68010 */
1114: if (regno2 < 2)
1115: return 0;
1116: return 1;
1117: }
1118: if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) { /* 68020 */
1119: if (regno == 3) return 1; /* 68040 only */
1120: /* 4 is >=68040, but 0x804 is in 68020 */
1121: if (regno2 < 4 || regno == 0x804)
1122: return 0;
1123: return 1;
1124: }
1125: if (currprefs.cpu_level >= 4) { /* 68040 */
1126: if (regno == 0x802) return 1; /* 68020 only */
1127: if (regno2 < 8) return 0;
1128: if (currprefs.cpu_level == 6 && regno2 == 8) /* 68060 only */
1129: return 0;
1130: return 1;
1131: }
1132: return 1;
1133: }
1134:
1.1 root 1135: int m68k_move2c (int regno, uae_u32 *regp)
1136: {
1.1.1.12 root 1137: if (movec_illg (regno)) {
1.1 root 1138: op_illg (0x4E7B);
1139: return 0;
1140: } else {
1141: switch (regno) {
1142: case 0: regs.sfc = *regp & 7; break;
1143: case 1: regs.dfc = *regp & 7; break;
1.1.1.16 root 1144: case 2:
1145: {
1146: uae_u32 cacr_mask = 0;
1147: if (currprefs.cpu_level == 2) // 68020
1148: cacr_mask = 0x0000000f;
1149: else if (currprefs.cpu_level == 3) // Fake 68030
1150: cacr_mask = 0x00003f1f;
1151: else if (currprefs.cpu_level == 4) // 68040
1152: cacr_mask = 0x80008000;
1153: cacr = *regp & cacr_mask;
1154: }
1.1 root 1155: case 3: tc = *regp & 0xc000; break;
1156: /* Mask out fields that should be zero. */
1157: case 4: itt0 = *regp & 0xffffe364; break;
1158: case 5: itt1 = *regp & 0xffffe364; break;
1159: case 6: dtt0 = *regp & 0xffffe364; break;
1160: case 7: dtt1 = *regp & 0xffffe364; break;
1.1.1.7 root 1161:
1.1 root 1162: case 0x800: regs.usp = *regp; break;
1163: case 0x801: regs.vbr = *regp; break;
1.1.1.12 root 1164: case 0x802: caar = *regp & 0xfc; break;
1.1 root 1165: case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
1166: case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
1.1.1.6 root 1167: case 0x805: mmusr = *regp; break;
1168: case 0x806: urp = *regp; break;
1169: case 0x807: srp = *regp; break;
1.1 root 1170: default:
1171: op_illg (0x4E7B);
1172: return 0;
1173: }
1174: }
1175: return 1;
1176: }
1177:
1178: int m68k_movec2 (int regno, uae_u32 *regp)
1179: {
1.1.1.12 root 1180: if (movec_illg (regno)) {
1.1 root 1181: op_illg (0x4E7A);
1182: return 0;
1183: } else {
1184: switch (regno) {
1185: case 0: *regp = regs.sfc; break;
1186: case 1: *regp = regs.dfc; break;
1.1.1.12 root 1187: case 2: *regp = cacr; break;
1.1 root 1188: case 3: *regp = tc; break;
1189: case 4: *regp = itt0; break;
1190: case 5: *regp = itt1; break;
1191: case 6: *regp = dtt0; break;
1192: case 7: *regp = dtt1; break;
1193: case 0x800: *regp = regs.usp; break;
1194: case 0x801: *regp = regs.vbr; break;
1.1.1.12 root 1195: case 0x802: *regp = caar; break;
1.1 root 1196: case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
1197: case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
1198: case 0x805: *regp = mmusr; break;
1.1.1.6 root 1199: case 0x806: *regp = urp; break;
1200: case 0x807: *regp = srp; break;
1.1 root 1201: default:
1202: op_illg (0x4E7A);
1203: return 0;
1204: }
1205: }
1206: return 1;
1207: }
1208:
1209: STATIC_INLINE int
1.1.1.10 root 1210: div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 ndiv, uae_u32 *quot, uae_u32 *rem)
1.1 root 1211: {
1212: uae_u32 q = 0, cbit = 0;
1213: int i;
1214:
1.1.1.10 root 1215: if (ndiv <= src_hi) {
1.1 root 1216: return 1;
1217: }
1218: for (i = 0 ; i < 32 ; i++) {
1219: cbit = src_hi & 0x80000000ul;
1220: src_hi <<= 1;
1221: if (src_lo & 0x80000000ul) src_hi++;
1222: src_lo <<= 1;
1223: q = q << 1;
1.1.1.10 root 1224: if (cbit || ndiv <= src_hi) {
1.1 root 1225: q |= 1;
1.1.1.10 root 1226: src_hi -= ndiv;
1.1 root 1227: }
1228: }
1229: *quot = q;
1230: *rem = src_hi;
1231: return 0;
1232: }
1233:
1234: void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
1235: {
1236: #if defined(uae_s64)
1237: if (src == 0) {
1.1.1.16 root 1238: Exception (5, oldpc,M68000_EXC_SRC_CPU);
1.1 root 1239: return;
1240: }
1241: if (extra & 0x800) {
1242: /* signed variant */
1243: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1244: uae_s64 quot, rem;
1245:
1246: if (extra & 0x400) {
1247: a &= 0xffffffffu;
1248: a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
1249: }
1250: rem = a % (uae_s64)(uae_s32)src;
1251: quot = a / (uae_s64)(uae_s32)src;
1252: if ((quot & UVAL64(0xffffffff80000000)) != 0
1253: && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1254: {
1255: SET_VFLG (1);
1256: SET_NFLG (1);
1257: SET_CFLG (0);
1258: } else {
1259: if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
1260: SET_VFLG (0);
1261: SET_CFLG (0);
1262: SET_ZFLG (((uae_s32)quot) == 0);
1263: SET_NFLG (((uae_s32)quot) < 0);
1264: m68k_dreg(regs, extra & 7) = rem;
1265: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1266: }
1267: } else {
1268: /* unsigned */
1269: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1270: uae_u64 quot, rem;
1271:
1272: if (extra & 0x400) {
1273: a &= 0xffffffffu;
1274: a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
1275: }
1276: rem = a % (uae_u64)src;
1277: quot = a / (uae_u64)src;
1278: if (quot > 0xffffffffu) {
1279: SET_VFLG (1);
1280: SET_NFLG (1);
1281: SET_CFLG (0);
1282: } else {
1283: SET_VFLG (0);
1284: SET_CFLG (0);
1285: SET_ZFLG (((uae_s32)quot) == 0);
1286: SET_NFLG (((uae_s32)quot) < 0);
1287: m68k_dreg(regs, extra & 7) = rem;
1288: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1289: }
1290: }
1291: #else
1292: if (src == 0) {
1.1.1.16 root 1293: Exception (5, oldpc,M68000_EXC_SRC_CPU);
1.1 root 1294: return;
1295: }
1296: if (extra & 0x800) {
1297: /* signed variant */
1298: uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1299: uae_s32 hi = lo < 0 ? -1 : 0;
1300: uae_s32 save_high;
1301: uae_u32 quot, rem;
1302: uae_u32 sign;
1303:
1304: if (extra & 0x400) {
1305: hi = (uae_s32)m68k_dreg(regs, extra & 7);
1306: }
1307: save_high = hi;
1308: sign = (hi ^ src);
1309: if (hi < 0) {
1310: hi = ~hi;
1311: lo = -lo;
1312: if (lo == 0) hi++;
1313: }
1314: if ((uae_s32)src < 0) src = -src;
1315: if (div_unsigned(hi, lo, src, ", &rem) ||
1316: (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
1317: SET_VFLG (1);
1318: SET_NFLG (1);
1319: SET_CFLG (0);
1320: } else {
1321: if (sign & 0x80000000) quot = -quot;
1322: if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
1323: SET_VFLG (0);
1324: SET_CFLG (0);
1325: SET_ZFLG (((uae_s32)quot) == 0);
1326: SET_NFLG (((uae_s32)quot) < 0);
1327: m68k_dreg(regs, extra & 7) = rem;
1328: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1329: }
1330: } else {
1331: /* unsigned */
1332: uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1333: uae_u32 hi = 0;
1334: uae_u32 quot, rem;
1335:
1336: if (extra & 0x400) {
1337: hi = (uae_u32)m68k_dreg(regs, extra & 7);
1338: }
1339: if (div_unsigned(hi, lo, src, ", &rem)) {
1340: SET_VFLG (1);
1341: SET_NFLG (1);
1342: SET_CFLG (0);
1343: } else {
1344: SET_VFLG (0);
1345: SET_CFLG (0);
1346: SET_ZFLG (((uae_s32)quot) == 0);
1347: SET_NFLG (((uae_s32)quot) < 0);
1348: m68k_dreg(regs, extra & 7) = rem;
1349: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1350: }
1351: }
1352: #endif
1353: }
1354:
1355: STATIC_INLINE void
1356: mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1357: {
1358: uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1359: uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1360: uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1361: uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1362: uae_u32 lo;
1363:
1364: lo = r0 + ((r1 << 16) & 0xffff0000ul);
1365: if (lo < r0) r3++;
1366: r0 = lo;
1367: lo = r0 + ((r2 << 16) & 0xffff0000ul);
1368: if (lo < r0) r3++;
1369: r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1370: *dst_lo = lo;
1371: *dst_hi = r3;
1372: }
1373:
1374: void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1375: {
1376: #if defined(uae_s64)
1377: if (extra & 0x800) {
1378: /* signed variant */
1379: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1380:
1381: a *= (uae_s64)(uae_s32)src;
1382: SET_VFLG (0);
1383: SET_CFLG (0);
1384: SET_ZFLG (a == 0);
1385: SET_NFLG (a < 0);
1386: if (extra & 0x400)
1387: m68k_dreg(regs, extra & 7) = a >> 32;
1388: else if ((a & UVAL64(0xffffffff80000000)) != 0
1389: && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1390: {
1391: SET_VFLG (1);
1392: }
1393: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1394: } else {
1395: /* unsigned */
1396: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1397:
1398: a *= (uae_u64)src;
1399: SET_VFLG (0);
1400: SET_CFLG (0);
1401: SET_ZFLG (a == 0);
1402: SET_NFLG (((uae_s64)a) < 0);
1403: if (extra & 0x400)
1404: m68k_dreg(regs, extra & 7) = a >> 32;
1405: else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1406: SET_VFLG (1);
1407: }
1408: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1409: }
1410: #else
1411: if (extra & 0x800) {
1412: /* signed variant */
1413: uae_s32 src1,src2;
1414: uae_u32 dst_lo,dst_hi;
1415: uae_u32 sign;
1416:
1417: src1 = (uae_s32)src;
1418: src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1419: sign = (src1 ^ src2);
1420: if (src1 < 0) src1 = -src1;
1421: if (src2 < 0) src2 = -src2;
1422: mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1423: if (sign & 0x80000000) {
1424: dst_hi = ~dst_hi;
1425: dst_lo = -dst_lo;
1426: if (dst_lo == 0) dst_hi++;
1427: }
1428: SET_VFLG (0);
1429: SET_CFLG (0);
1430: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1431: SET_NFLG (((uae_s32)dst_hi) < 0);
1432: if (extra & 0x400)
1433: m68k_dreg(regs, extra & 7) = dst_hi;
1434: else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1435: && ((dst_hi & 0xffffffff) != 0xffffffff
1436: || (dst_lo & 0x80000000) != 0x80000000))
1437: {
1438: SET_VFLG (1);
1439: }
1440: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1441: } else {
1442: /* unsigned */
1443: uae_u32 dst_lo,dst_hi;
1444:
1445: mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1446:
1447: SET_VFLG (0);
1448: SET_CFLG (0);
1449: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1450: SET_NFLG (((uae_s32)dst_hi) < 0);
1451: if (extra & 0x400)
1452: m68k_dreg(regs, extra & 7) = dst_hi;
1453: else if (dst_hi != 0) {
1454: SET_VFLG (1);
1455: }
1456: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1457: }
1458: #endif
1459: }
1.1.1.6 root 1460:
1.1 root 1461:
1462: void m68k_reset (void)
1463: {
1464: regs.s = 1;
1465: regs.m = 0;
1466: regs.stopped = 0;
1467: regs.t1 = 0;
1468: regs.t0 = 0;
1469: SET_ZFLG (0);
1470: SET_XFLG (0);
1471: SET_CFLG (0);
1472: SET_VFLG (0);
1473: SET_NFLG (0);
1.1.1.16 root 1474: regs.spcflags &= ( SPCFLAG_MODE_CHANGE | SPCFLAG_DEBUGGER ); /* Clear specialflags except mode-change and debugger */
1.1 root 1475: regs.intmask = 7;
1476: regs.vbr = regs.sfc = regs.dfc = 0;
1477: regs.fpcr = regs.fpsr = regs.fpiar = 0;
1.1.1.7 root 1478:
1479: m68k_areg(regs, 7) = get_long(0);
1480: m68k_setpc(get_long(4));
1481: refill_prefetch (m68k_getpc(), 0);
1.1 root 1482: }
1483:
1.1.1.8 root 1484:
1.1 root 1485: unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1486: {
1.1.1.8 root 1487: #if 0
1.1 root 1488: uaecptr pc = m68k_getpc ();
1.1.1.8 root 1489: #endif
1.1.1.6 root 1490: if ((opcode & 0xF000) == 0xF000) {
1.1.1.16 root 1491: Exception(0xB,0,M68000_EXC_SRC_CPU);
1.1 root 1492: return 4;
1.1.1.6 root 1493: }
1494: if ((opcode & 0xF000) == 0xA000) {
1.1.1.16 root 1495: Exception(0xA,0,M68000_EXC_SRC_CPU);
1.1 root 1496: return 4;
1.1.1.6 root 1497: }
1.1.1.3 root 1498: #if 0
1.1.1.6 root 1499: write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc);
1.1 root 1500: #endif
1.1.1.16 root 1501: Exception (4,0,M68000_EXC_SRC_CPU);
1.1 root 1502: return 4;
1503: }
1504:
1.1.1.8 root 1505:
1.1 root 1506: void mmu_op(uae_u32 opcode, uae_u16 extra)
1507: {
1508: if ((opcode & 0xFE0) == 0x0500) {
1509: /* PFLUSH */
1510: mmusr = 0;
1511: write_log ("PFLUSH\n");
1512: } else if ((opcode & 0x0FD8) == 0x548) {
1513: /* PTEST */
1514: write_log ("PTEST\n");
1515: } else
1516: op_illg (opcode);
1517: }
1518:
1519:
1520: static uaecptr last_trace_ad = 0;
1521:
1522: static void do_trace (void)
1523: {
1.1.1.12 root 1524: if (regs.t0 && currprefs.cpu_level >= 2) {
1.1 root 1525: uae_u16 opcode;
1526: /* should also include TRAP, CHK, SR modification FPcc */
1527: /* probably never used so why bother */
1528: /* We can afford this to be inefficient... */
1529: m68k_setpc (m68k_getpc ());
1530: fill_prefetch_0 ();
1531: opcode = get_word (regs.pc);
1.1.1.19! root 1532: if (opcode == 0x4e73 /* RTE */
1.1 root 1533: || opcode == 0x4e74 /* RTD */
1534: || opcode == 0x4e75 /* RTS */
1535: || opcode == 0x4e77 /* RTR */
1536: || opcode == 0x4e76 /* TRAPV */
1537: || (opcode & 0xffc0) == 0x4e80 /* JSR */
1538: || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1539: || (opcode & 0xff00) == 0x6100 /* BSR */
1540: || ((opcode & 0xf000) == 0x6000 /* Bcc */
1541: && cctrue((opcode >> 8) & 0xf))
1542: || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1543: && !cctrue((opcode >> 8) & 0xf)
1544: && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1545: {
1546: last_trace_ad = m68k_getpc ();
1547: unset_special (SPCFLAG_TRACE);
1548: set_special (SPCFLAG_DOTRACE);
1549: }
1550: } else if (regs.t1) {
1551: last_trace_ad = m68k_getpc ();
1552: unset_special (SPCFLAG_TRACE);
1553: set_special (SPCFLAG_DOTRACE);
1554: }
1555: }
1556:
1557:
1.1.1.8 root 1558: /*
1559: * Handle special flags
1560: */
1.1.1.14 root 1561:
1562: static bool do_specialties_interrupt (int Pending)
1563: {
1.1.1.19! root 1564: #if ENABLE_DSP_EMU
! 1565: /* Check for DSP int first (if enabled) (level 6) */
! 1566: if (regs.spcflags & SPCFLAG_DSP) {
! 1567: if (DSP_ProcessIRQ() == true)
! 1568: return true;
! 1569: }
! 1570: #endif
! 1571:
! 1572: /* Check for MFP ints (level 6) */
1.1.1.14 root 1573: if (regs.spcflags & SPCFLAG_MFP) {
1.1.1.19! root 1574: if (MFP_ProcessIRQ() == true)
1.1.1.15 root 1575: return true; /* MFP exception was generated, no higher interrupt can happen */
1.1.1.14 root 1576: }
1577:
1578: /* No MFP int, check for VBL/HBL ints (levels 4/2) */
1579: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1580: int intr = intlev ();
1581: /* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */
1582: // unset_special (SPCFLAG_DOINT);
1583: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1584: if (intr != -1 && intr > regs.intmask) {
1585: Interrupt (intr , Pending); /* process the interrupt and add pending jitter if necessary */
1.1.1.15 root 1586: return true;
1.1.1.14 root 1587: }
1588: }
1589:
1.1.1.15 root 1590: return false; /* no interrupt was found */
1.1.1.14 root 1591: }
1592:
1593:
1.1 root 1594: static int do_specialties (void)
1595: {
1.1.1.7 root 1596: if(regs.spcflags & SPCFLAG_BUSERROR) {
1597: /* We can not execute bus errors directly in the memory handler
1598: * functions since the PC should point to the address of the next
1599: * instruction, so we're executing the bus errors here: */
1.1.1.8 root 1600: unset_special(SPCFLAG_BUSERROR);
1.1.1.16 root 1601: Exception(2,0,M68000_EXC_SRC_CPU);
1.1.1.7 root 1602: }
1603:
1.1.1.8 root 1604: if(regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1605: /* Add some extra cycles to simulate a wait state */
1606: unset_special(SPCFLAG_EXTRA_CYCLES);
1.1.1.11 root 1607: M68000_AddCycles(nWaitStateCycles);
1.1.1.12 root 1608: nWaitStateCycles = 0;
1.1.1.8 root 1609: }
1610:
1.1 root 1611: if (regs.spcflags & SPCFLAG_DOTRACE) {
1.1.1.16 root 1612: Exception (9,last_trace_ad,M68000_EXC_SRC_CPU);
1.1 root 1613: }
1.1.1.8 root 1614:
1.1.1.14 root 1615:
1616: /* Handle the STOP instruction */
1617: if ( regs.spcflags & SPCFLAG_STOP ) {
1.1.1.19! root 1618: //fprintf ( stderr , "test stop %d\n" , nCyclesMainCounter );
1.1.1.14 root 1619: /* We first test if there's a pending interrupt that would */
1.1.1.19! root 1620: /* allow to immediately leave the STOP state */
1.1.1.15 root 1621: if ( do_specialties_interrupt(true) ) { /* test if there's an interrupt and add pending jitter */
1.1.1.14 root 1622: regs.stopped = 0;
1623: unset_special (SPCFLAG_STOP);
1.1.1.19! root 1624: //fprintf ( stderr , "exit stop %d\n" , nCyclesMainCounter );
1.1.1.14 root 1625: }
1626:
1627: /* No pending int, we have to wait for the next matching int */
1628: while (regs.spcflags & SPCFLAG_STOP) {
1629:
1630: /* Take care of quit event if needed */
1631: if (regs.spcflags & SPCFLAG_BRK)
1632: return 1;
1633:
1634: M68000_AddCycles(4);
1635:
1636: /* It is possible one or more ints happen at the same time */
1.1.1.19! root 1637: /* We must process them during the same cpu cycle then choose the highest priority one */
! 1638: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
1.1.1.14 root 1639: CALL_VAR(PendingInterruptFunction);
1.1.1.19! root 1640: if ( MFP_UpdateNeeded == true )
! 1641: MFP_UpdateIRQ ( 0 );
! 1642:
! 1643: /* Check is there's an interrupt to process (could be a delayed MFP interrupt) */
! 1644: if ( do_specialties_interrupt(false) ) { /* test if there's an interrupt and add non pending jitter */
! 1645: regs.stopped = 0;
! 1646: unset_special (SPCFLAG_STOP);
1.1.1.6 root 1647: }
1.1 root 1648: }
1649: }
1.1.1.8 root 1650:
1.1.1.14 root 1651:
1.1 root 1652: if (regs.spcflags & SPCFLAG_TRACE)
1653: do_trace ();
1654:
1.1.1.12 root 1655: // if (regs.spcflags & SPCFLAG_DOINT) {
1656: /* [NP] pending int should be processed now, not after the current instr */
1.1.1.14 root 1657: /* so we check for (SPCFLAG_INT | SPCFLAG_DOINT), not just for SPCFLAG_DOINT */
1.1.1.15 root 1658:
1659: if ( do_specialties_interrupt(false) ) { /* test if there's an interrupt and add non pending jitter */
1.1.1.14 root 1660: regs.stopped = 0; /* [NP] useless ? */
1661: }
1662: if (regs.spcflags & SPCFLAG_INT) {
1663: unset_special (SPCFLAG_INT);
1664: set_special (SPCFLAG_DOINT);
1665: }
1.1.1.8 root 1666:
1.1.1.15 root 1667: if (regs.spcflags & SPCFLAG_DEBUGGER)
1.1.1.16 root 1668: DebugCpu_Check();
1.1.1.15 root 1669:
1.1 root 1670: if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1.1.1.8 root 1671: unset_special(SPCFLAG_MODE_CHANGE);
1.1 root 1672: return 1;
1673: }
1.1.1.8 root 1674:
1.1 root 1675: return 0;
1676: }
1677:
1.1.1.3 root 1678:
1.1 root 1679: /* It's really sad to have two almost identical functions for this, but we
1680: do it all for performance... :( */
1681: static void m68k_run_1 (void)
1682: {
1683: #ifdef DEBUG_PREFETCH
1684: uae_u8 saved_bytes[20];
1685: uae_u16 *oldpcp;
1686: #endif
1.1.1.8 root 1687:
1688: for (;;) {
1.1 root 1689: int cycles;
1690: uae_u32 opcode = get_iword_prefetch (0);
1.1.1.8 root 1691:
1.1 root 1692: #ifdef DEBUG_PREFETCH
1693: if (get_ilong (0) != do_get_mem_long (®s.prefetch)) {
1694: fprintf (stderr, "Prefetch differs from memory.\n");
1695: debugging = 1;
1696: return;
1697: }
1698: oldpcp = regs.pc_p;
1699: memcpy (saved_bytes, regs.pc_p, 20);
1700: #endif
1701:
1702: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.15 root 1703: if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
1704: {
1705: int FrameCycles, HblCounterVideo, LineCycles;
1706:
1707: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
1708:
1709: LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
1.1.1.19! root 1710: Disasm(stderr, m68k_getpc (), NULL, 1);
1.1.1.15 root 1711: }
1.1 root 1712:
1713: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1714: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1715: #if COUNT_INSTRS == 2
1716: if (table68k[opcode].handler != -1)
1717: instrcount[table68k[opcode].handler]++;
1718: #elif COUNT_INSTRS == 1
1719: instrcount[opcode]++;
1720: #endif
1.1.1.2 root 1721:
1.1.1.12 root 1722: /* In case of a Bus Error, we need the PC of the instruction that caused */
1723: /* the error to build the exception stack frame */
1724: BusErrorPC = m68k_getpc();
1725:
1.1.1.18 root 1726: if (bDspEnabled)
1727: Cycles_SetCounter(CYCLES_COUNTER_CPU, 0); /* to measure the total number of cycles spent in the cpu */
1728:
1.1.1.6 root 1729: cycles = (*cpufunctbl[opcode])(opcode);
1730:
1.1 root 1731: #ifdef DEBUG_PREFETCH
1732: if (memcmp (saved_bytes, oldpcp, 20) != 0) {
1.1.1.12 root 1733: fprintf (stderr, "Self-modifying code detected %x.\n" , m68k_getpc() );
1.1 root 1734: set_special (SPCFLAG_BRK);
1735: debugging = 1;
1736: }
1737: #endif
1.1.1.2 root 1738:
1.1.1.12 root 1739: M68000_AddCyclesWithPairing(cycles);
1.1.1.13 root 1740: if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1741: /* Add some extra cycles to simulate a wait state */
1742: unset_special(SPCFLAG_EXTRA_CYCLES);
1743: M68000_AddCycles(nWaitStateCycles);
1744: nWaitStateCycles = 0;
1745: }
1746:
1.1.1.14 root 1747: /* We can have several interrupts at the same time before the next CPU instruction */
1748: /* We must check for pending interrupt and call do_specialties_interrupt() only */
1749: /* if the cpu is not in the STOP state. Else, the int could be acknowledged now */
1750: /* and prevent exiting the STOP state when calling do_specialties() after. */
1751: /* For performance, we first test PendingInterruptCount, then regs.spcflags */
1.1.1.19! root 1752: if ( PendingInterruptCount <= 0 )
! 1753: {
! 1754: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) && ( ( regs.spcflags & SPCFLAG_STOP ) == 0 ) )
! 1755: CALL_VAR ( PendingInterruptFunction ); /* call the interrupt's handler */
! 1756: if ( MFP_UpdateNeeded == true )
! 1757: MFP_UpdateIRQ ( 0 ); /* update MFP's state if some internal timers related to MFP expired */
! 1758: }
1.1.1.14 root 1759:
1760: if (regs.spcflags) {
1761: if (do_specialties ())
1762: return;
1763: }
1764:
1.1.1.15 root 1765: /* Run DSP 56k code if necessary */
1766: if (bDspEnabled) {
1.1.1.18 root 1767: DSP_Run( Cycles_GetCounter(CYCLES_COUNTER_CPU) * 2);
1.1.1.15 root 1768: }
1.1 root 1769: }
1770: }
1771:
1772:
1773: /* Same thing, but don't use prefetch to get opcode. */
1774: static void m68k_run_2 (void)
1775: {
1.1.1.8 root 1776: for (;;) {
1.1 root 1777: int cycles;
1778: uae_u32 opcode = get_iword (0);
1779:
1780: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.15 root 1781: if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
1782: {
1783: int FrameCycles, HblCounterVideo, LineCycles;
1784:
1785: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
1786:
1787: LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
1.1.1.19! root 1788: Disasm(stderr, m68k_getpc (), NULL, 1);
1.1.1.15 root 1789: }
1.1.1.12 root 1790:
1.1 root 1791: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1792: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1793: #if COUNT_INSTRS == 2
1794: if (table68k[opcode].handler != -1)
1795: instrcount[table68k[opcode].handler]++;
1796: #elif COUNT_INSTRS == 1
1797: instrcount[opcode]++;
1798: #endif
1.1.1.2 root 1799:
1.1.1.17 root 1800: /* In case of a Bus Error, we need the PC of the instruction that caused */
1801: /* the error to build the exception stack frame */
1802: BusErrorPC = m68k_getpc();
1803:
1.1.1.6 root 1804: cycles = (*cpufunctbl[opcode])(opcode);
1805:
1.1.1.16 root 1806: if (bDspEnabled)
1807: Cycles_SetCounter(CYCLES_COUNTER_CPU, 0); /* to measure the total number of cycles spent in the cpu */
1808:
1.1.1.8 root 1809: M68000_AddCycles(cycles);
1.1.1.13 root 1810: if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1811: /* Add some extra cycles to simulate a wait state */
1812: unset_special(SPCFLAG_EXTRA_CYCLES);
1813: M68000_AddCycles(nWaitStateCycles);
1814: nWaitStateCycles = 0;
1815: }
1816:
1.1.1.19! root 1817: if ( PendingInterruptCount <= 0 )
! 1818: {
! 1819: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
! 1820: CALL_VAR(PendingInterruptFunction);
! 1821: if ( MFP_UpdateNeeded == true )
! 1822: MFP_UpdateIRQ ( 0 );
! 1823: }
1.1.1.8 root 1824:
1.1 root 1825: if (regs.spcflags) {
1826: if (do_specialties ())
1827: return;
1828: }
1.1.1.15 root 1829:
1830: /* Run DSP 56k code if necessary */
1831: if (bDspEnabled) {
1.1.1.16 root 1832: DSP_Run( Cycles_GetCounter(CYCLES_COUNTER_CPU) );
1.1.1.15 root 1833: }
1.1 root 1834: }
1835: }
1836:
1837:
1838: void m68k_go (int may_quit)
1839: {
1.1.1.8 root 1840: static int in_m68k_go = 0;
1841:
1.1 root 1842: if (in_m68k_go || !may_quit) {
1843: write_log ("Bug! m68k_go is not reentrant.\n");
1844: abort ();
1845: }
1846:
1847: in_m68k_go++;
1.1.1.8 root 1848: while (!(regs.spcflags & SPCFLAG_BRK)) {
1.1.1.12 root 1849: if(currprefs.cpu_compatible)
1.1.1.2 root 1850: m68k_run_1();
1851: else
1852: m68k_run_2();
1.1 root 1853: }
1.1.1.8 root 1854: unset_special(SPCFLAG_BRK);
1.1 root 1855: in_m68k_go--;
1856: }
1857:
1.1.1.8 root 1858:
1859: /*
1.1 root 1860: static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1861: {
1862: uae_u32 opcode, val;
1863: struct instr *dp;
1864:
1865: opcode = get_iword_1(0);
1866: last_op_for_exception_3 = opcode;
1867: m68kpc_offset = 2;
1868:
1.1.1.6 root 1869: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1870: opcode = 0x4AFC;
1871: }
1872: dp = table68k + opcode;
1873:
1874: if (dp->suse) {
1875: if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) {
1.1.1.16 root 1876: Exception (3, 0,M68000_EXC_SRC_CPU);
1.1 root 1877: return;
1878: }
1879: }
1880: if (dp->duse) {
1881: if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) {
1.1.1.16 root 1882: Exception (3, 0,M68000_EXC_SRC_CPU);
1.1 root 1883: return;
1884: }
1885: }
1886: }
1.1.1.8 root 1887: */
1888:
1.1 root 1889:
1890: void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1891: {
1.1.1.11 root 1892: static const char * const ccnames[] =
1.1.1.8 root 1893: { "T ","F ","HI","LS","CC","CS","NE","EQ",
1894: "VC","VS","PL","MI","GE","LT","GT","LE" };
1895:
1.1 root 1896: uaecptr newpc = 0;
1897: m68kpc_offset = addr - m68k_getpc ();
1898: while (cnt-- > 0) {
1899: char instrname[20],*ccpt;
1900: int opwords;
1901: uae_u32 opcode;
1.1.1.11 root 1902: const struct mnemolookup *lookup;
1.1 root 1903: struct instr *dp;
1904: fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset);
1905: for (opwords = 0; opwords < 5; opwords++){
1906: fprintf (f, "%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1907: }
1908: opcode = get_iword_1 (m68kpc_offset);
1909: m68kpc_offset += 2;
1.1.1.6 root 1910: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1911: opcode = 0x4AFC;
1912: }
1913: dp = table68k + opcode;
1914: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1915: ;
1916:
1917: strcpy (instrname, lookup->name);
1918: ccpt = strstr (instrname, "cc");
1919: if (ccpt != 0) {
1920: strncpy (ccpt, ccnames[dp->cc], 2);
1921: }
1922: fprintf (f, "%s", instrname);
1923: switch (dp->size){
1924: case sz_byte: fprintf (f, ".B "); break;
1925: case sz_word: fprintf (f, ".W "); break;
1926: case sz_long: fprintf (f, ".L "); break;
1927: default: fprintf (f, " "); break;
1928: }
1929:
1930: if (dp->suse) {
1931: newpc = m68k_getpc () + m68kpc_offset;
1932: newpc += ShowEA (f, dp->sreg, dp->smode, dp->size, 0);
1933: }
1934: if (dp->suse && dp->duse)
1935: fprintf (f, ",");
1936: if (dp->duse) {
1937: newpc = m68k_getpc () + m68kpc_offset;
1938: newpc += ShowEA (f, dp->dreg, dp->dmode, dp->size, 0);
1939: }
1940: if (ccpt != 0) {
1941: if (cctrue(dp->cc))
1.1.1.5 root 1942: fprintf (f, " == %08lx (TRUE)", (long)newpc);
1.1 root 1943: else
1.1.1.5 root 1944: fprintf (f, " == %08lx (FALSE)", (long)newpc);
1.1 root 1945: } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1.1.1.5 root 1946: fprintf (f, " == %08lx", (long)newpc);
1.1 root 1947: fprintf (f, "\n");
1948: }
1949: if (nextpc)
1950: *nextpc = m68k_getpc () + m68kpc_offset;
1951: }
1952:
1953: void m68k_dumpstate (FILE *f, uaecptr *nextpc)
1954: {
1955: int i;
1956: for (i = 0; i < 8; i++){
1.1.1.5 root 1957: fprintf (f, "D%d: %08lx ", i, (long)m68k_dreg(regs, i));
1.1 root 1958: if ((i & 3) == 3) fprintf (f, "\n");
1959: }
1960: for (i = 0; i < 8; i++){
1.1.1.5 root 1961: fprintf (f, "A%d: %08lx ", i, (long)m68k_areg(regs, i));
1.1 root 1962: if ((i & 3) == 3) fprintf (f, "\n");
1963: }
1964: if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1965: if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1966: if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1967: fprintf (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1.1.1.5 root 1968: (long)regs.usp,(long)regs.isp,(long)regs.msp,(long)regs.vbr);
1.1 root 1969: fprintf (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1970: regs.t1, regs.t0, regs.s, regs.m,
1971: GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1972: for (i = 0; i < 8; i++){
1973: fprintf (f, "FP%d: %g ", i, regs.fp[i]);
1974: if ((i & 3) == 3) fprintf (f, "\n");
1975: }
1976: fprintf (f, "N=%d Z=%d I=%d NAN=%d\n",
1977: (regs.fpsr & 0x8000000) != 0,
1978: (regs.fpsr & 0x4000000) != 0,
1979: (regs.fpsr & 0x2000000) != 0,
1980: (regs.fpsr & 0x1000000) != 0);
1.1.1.12 root 1981: if (currprefs.cpu_compatible)
1.1 root 1982: fprintf (f, "prefetch %08lx\n", (unsigned long)do_get_mem_long(®s.prefetch));
1983:
1984: m68k_disasm (f, m68k_getpc (), nextpc, 1);
1985: if (nextpc)
1.1.1.5 root 1986: fprintf (f, "next PC: %08lx\n", (long)*nextpc);
1.1 root 1987: }
1.1.1.12 root 1988:
1989:
1990: /*
1991:
1992: The routines below take dividend and divisor as parameters.
1993: They return 0 if division by zero, or exact number of cycles otherwise.
1994:
1995: The number of cycles returned assumes a register operand.
1996: Effective address time must be added if memory operand.
1997:
1998: For 68000 only (not 68010, 68012, 68020, etc).
1999: Probably valid for 68008 after adding the extra prefetch cycle.
2000:
2001:
2002: Best and worst cases are for register operand:
2003: (Note the difference with the documented range.)
2004:
2005:
2006: DIVU:
2007:
2008: Overflow (always): 10 cycles.
2009: Worst case: 136 cycles.
2010: Best case: 76 cycles.
2011:
2012:
2013: DIVS:
2014:
2015: Absolute overflow: 16-18 cycles.
2016: Signed overflow is not detected prematurely.
2017:
2018: Worst case: 156 cycles.
2019: Best case without signed overflow: 122 cycles.
2020: Best case with signed overflow: 120 cycles
2021:
2022:
2023: */
2024:
2025:
2026: //
2027: // DIVU
2028: // Unsigned division
2029: //
2030:
2031: STATIC_INLINE int getDivu68kCycles_2 (uae_u32 dividend, uae_u16 divisor)
2032: {
2033: int mcycles;
2034: uae_u32 hdivisor;
2035: int i;
2036:
2037: if (divisor == 0)
2038: return 0;
2039:
2040: // Overflow
2041: if ((dividend >> 16) >= divisor)
2042: return (mcycles = 5) * 2;
2043:
2044: mcycles = 38;
2045: hdivisor = divisor << 16;
2046:
2047: for (i = 0; i < 15; i++) {
2048: uae_u32 temp;
2049: temp = dividend;
2050:
2051: dividend <<= 1;
2052:
2053: // If carry from shift
2054: if ((uae_s32)temp < 0)
2055: dividend -= hdivisor;
2056: else {
2057: mcycles += 2;
2058: if (dividend >= hdivisor) {
2059: dividend -= hdivisor;
2060: mcycles--;
2061: }
2062: }
2063: }
2064: return mcycles * 2;
2065: }
2066: int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor)
2067: {
2068: int v = getDivu68kCycles_2 (dividend, divisor) - 4;
2069: // write_log ("U%d ", v);
2070: return v;
2071: }
2072:
2073: //
2074: // DIVS
2075: // Signed division
2076: //
2077:
2078: STATIC_INLINE int getDivs68kCycles_2 (uae_s32 dividend, uae_s16 divisor)
2079: {
2080: int mcycles;
2081: uae_u32 aquot;
2082: int i;
2083:
2084: if (divisor == 0)
2085: return 0;
2086:
2087: mcycles = 6;
2088:
2089: if (dividend < 0)
2090: mcycles++;
2091:
2092: // Check for absolute overflow
2093: if (((uae_u32)abs (dividend) >> 16) >= (uae_u16)abs (divisor))
2094: return (mcycles + 2) * 2;
2095:
2096: // Absolute quotient
2097: aquot = (uae_u32) abs (dividend) / (uae_u16)abs (divisor);
2098:
2099: mcycles += 55;
2100:
2101: if (divisor >= 0) {
2102: if (dividend >= 0)
2103: mcycles--;
2104: else
2105: mcycles++;
2106: }
2107:
2108: // Count 15 msbits in absolute of quotient
2109:
2110: for (i = 0; i < 15; i++) {
2111: if ((uae_s16)aquot >= 0)
2112: mcycles++;
2113: aquot <<= 1;
2114: }
2115:
2116: return mcycles * 2;
2117: }
2118: int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor)
2119: {
2120: int v = getDivs68kCycles_2 (dividend, divisor) - 4;
2121: // write_log ("S%d ", v);
2122: return v;
2123: }
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