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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation
5: *
6: * (c) 1995 Bernd Schmidt
1.1.1.2 root 7: *
8: * Adaptation to Hatari by Thomas Huth
9: *
1.1.1.19 root 10: * This file is distributed under the GNU General Public License, version 2
11: * or at your option any later version. Read the file gpl.txt for details.
1.1 root 12: */
1.1.1.12 root 13:
14:
15: /* 2007/11/12 [NP] Add HATARI_TRACE_CPU_DISASM. */
16: /* 2007/11/15 [NP] In MakeFromSR, writes to m and t0 should be ignored and set to 0 if cpu < 68020 */
17: /* 2007/11/26 [NP] We set BusErrorPC in m68k_run_1 instead of M68000_BusError, else the BusErrorPC */
18: /* will not point to the opcode that generated the bus error. */
19: /* Huge debug/work on Exceptions 2/3 stack frames, result is more accurate and */
20: /* allow to pass the very tricky Transbeauce 2 Demo's protection. */
21: /* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */
22: /* Cwik, [email protected]). */
23: /* 2007/12/06 [NP] The PC stored in the stack frame for the bus error is complex to emulate, */
24: /* because it doesn't necessarily point to the next instruction after the one that */
25: /* triggered the bus error. In the case of the Transbeauce 2 Demo, after */
26: /* 'move.l $0.w,$24.w', PC is incremented of 4 bytes, not 6, and stored in the */
27: /* stack. Special case to decrement PC of 2 bytes if opcode is '21f8'. */
28: /* This should be fixed with a real model. */
29: /* 2007/12/07 [NP] If Trace is enabled and a group 2 exception occurs (such as CHK), the trace */
30: /* handler should be called after the group 2's handler. If a bus error, address */
31: /* error or illegal occurs while Trace is enabled, the trace handler should not be */
32: /* called after this instruction (Transbeauce 2 Demo, Phaleon Demo). */
33: /* This means that if a CHK is executed while trace bit was set, we must set PC */
34: /* to CHK handler, turn trace off in the internal SR, but we must still call the */
35: /* trace handler one last time with the PC set to the CHK's handler (even if */
36: /* trace mode is internally turned off while processing an exception). Once trace */
37: /* handler is finished (RTE), we return to the CHK's handler. */
38: /* This is true for DIV BY 0, CHK, TRAPV and TRAP. */
39: /* Backport exception_trace() from WinUAE to handle this behaviour (used in */
40: /* Transbeauce 2 demo). */
41: /* 2007/12/09 [NP] 'dc.w $a' should not be used to call 'OpCode_SysInit' but should give an illegal*/
42: /* instruction (Transbeauce 2 demo). */
43: /* Instead of always replacing the illegal instructions $8, $a and $c by the */
44: /* 3 functions required for HD emulation, we now do it in cart.c only if the */
45: /* built-in cartridge image is loaded. */
46: /* YEAH! Hatari is now the first emulator to pass the Transbeauce 2 protection :) */
47: /* 2007/12/18 [NP] More precise timings for HBL, VBL and MFP interrupts. On ST, these interrupts */
48: /* are taking 56 cycles instead of the 44 cycles in the 68000's documentation. */
1.1.1.19 root 49: /* 2007/12/24 [NP] If an interrupt (HBL, VBL) is pending after instruction 'n' was processed, the */
1.1.1.12 root 50: /* exception should be called before instr. 'n+1' is processed, not after (else the*/
51: /* interrupt's handler is delayed by one 68000's instruction, which could break */
52: /* some demos with too strict timings) (ACF's Demo Main Menu). */
53: /* We call the interrupt if ( SPCFLAG_INT | SPCFLAG_DOINT ) is set, not only if */
54: /* SPCFLAG_DOINT is set (as it was already the case when handling 'STOP'). */
55: /* 2007/12/25 [NP] FIXME When handling exceptions' cycles, using nr >= 64 to determine if this is */
56: /* an MFP exception could be wrong if the MFP VR was set to another value than the */
57: /* default $40 (this could be a problem with programs requiring a precise cycles */
58: /* calculation while changing VR, but no such programs were encountered so far). */
1.1.1.13 root 59: /* -> FIXED, see 2008/10/05 */
60: /* 2008/04/17 [NP] In m68k_run_1/m68k_run_2, add the wait state cycles before testing if content */
61: /* of PendingInterruptCount is <= 0 (else the int could happen a few cycles earlier*/
62: /* than expected in some rare cases (reading $fffa21 in BIG Demo Screen 1)). */
63: /* 2008/09/14 [NP] Add the value of the new PC in the exception's log. */
64: /* 2008/09/14 [NP] Correct cycles for TRAP are 34 not 38 (4 more cycles were counted because cpuemu*/
65: /* returns 4 and Exception() adds 34) (Phaleon / Illusion Demo by Next). */
66: /* FIXME : Others exception cycles may be wrong too. */
67: /* 2008/10/05 [NP] Add a parameter 'ExceptionSource' to Exception(). This allows to know the source*/
68: /* of the exception (video, mfp, cpu) and properly handle MFP interrupts. Since */
69: /* it's possible to change the vector base in $fffa17, MFP int vectors can overlap */
70: /* the 'normal' 68000 ones and the exception number is not enough to decide. */
71: /* We need ExceptionSource to remove the ambiguity. */
72: /* Fix High Fidelity Dreams by Aura which sets MFP vector base to $c0 instead of */
73: /* $100. In that case, timer B int becomes exception nr 56 and conflicts with the */
74: /* 'MMU config error' exception, which takes 4 cycles instead of 56 cycles for MFP.*/
75: /* 2008/11/18 [NP] In 'do_specialties()', when the cpu is in the STOP state, we must test all */
76: /* possible int handlers while PendingInterruptCount <= 0 without increasing the */
77: /* cpu cycle counter. In the case where both an MFP int and an HBL occur at the */
1.1.1.14 root 78: /* same time for example, the HBL was delayed by 4 cycles if no MFP exception */
1.1.1.13 root 79: /* was triggered, which was wrong (this happened mainly with the TOS timer D that */
80: /* expires very often). Such precision is required for very recent hardscroll */
81: /* techniques that use 'stop' to stay in sync with the video shifter. */
1.1.1.14 root 82: /* 2008/11/23 [NP] In 'do_specialties()', when in STOP state, we must first test for a pending */
1.1.1.19 root 83: /* interrupt that would exit the STOP state immediately, without doing a 'while' */
1.1.1.14 root 84: /* loop until 'SPCFLAG_INT' or 'SPCFLAG_DOINT' are set. */
85: /* 2008/11/29 [NP] Call 'InterruptAddJitter()' when a video interrupt happens to precisely emulate */
86: /* the jitter happening on the Atari (see video.c for the jitter patterns). */
87: /* FIXME : Pattern is not always correct when handling pending interrupt in STOP */
88: /* state, but this should be harmless as no program has been found using this. */
89: /* 2008/12/05 [NP] On Atari it takes 56 cycles to process an interrupt. During that time, a higher */
90: /* level interrupt could happen and we must execute it before the previous int */
91: /* (see m68k_run_1()). */
92: /* This is the case for the VBL which can interrupt the last HBL of a screen */
93: /* (end of line 312) at various point (from 0 to 8 cycles). */
94: /* This fixes the fullscreen tunnel in Suretrip 49% by Checkpoint, which uses a */
95: /* really buggy vbl/hbl combination, even on a real ST. Also fixes sample sound */
96: /* in Swedish New Year's TCB screen. */
97: /* 2008/12/11 [NP] Extract interrupt handling from do_specialties() in do_specialties_interrupt() */
98: /* and factorize some code. In m68k_run_1 when testing for multiple interrupts at */
99: /* the same time, call do_specialties_interrupt() to check only the special flags */
100: /* related to interrupts (MFP and video) (else, this caused problem when the TRACE */
101: /* flag was set). */
102: /* 2008/12/14 [NP] In m68k_run_1(), we should check for simultaneous ints only if the cpu is not */
103: /* in the STOP state after the last instruction was executed. Else, the call to */
104: /* do_specialties_interrupt() could acknowledge the interrupt and we would never */
105: /* exit the STOP state in do_specialties() just after (the problem can happen if */
106: /* the TOS timer D expires just at the same time as the STOP instruction). */
107: /* Fix regression since 2008/12/11 in the hidden screen from ULM in Oh Crickey... */
108: /* 2008/12/20 [NP] In m68k_run_1(), when checking interrupts and STOP mode, we should test */
109: /* PendingInterruptCount before regs.spcflags to have a faster evaluation of the */
110: /* 'while' condition (PendingInterruptCount <= 0 is true less often than STOP==0) */
1.1.1.17 root 111: /* 2011/04/29 [NP] In Exception(), check the new PC is not on odd address ; raise an address error */
112: /* exception if it's the case. */
1.1.1.20! root 113: /* 2012/09/01 [NP] Add a special case to correct the stacked PC when a bus error happens during */
! 114: /* a movem (fix the game Blood Money). */
! 115: /* 2013/03/16 [NP] In refill_prefetch(), reload only one new word in regs.prefetch if low word is */
! 116: /* still valid : low word goes to high word and we reload only low word */
! 117: /* (fix EOR/ADD self modified code in the protection for the game Damocles). */
1.1.1.19 root 118: /* 2013/04/11 [NP] In Exception(), call MFP_ProcessIACK after 12 cycles to update the MFP's vector */
119: /* number used for the exception (see mfp.c). */
120: /* 2013/05/03 [NP] In Exception(), handle IACK for HBL and VBL interrupts too, allowing pending bit*/
121: /* to be set twice during an active video interrupt (correct fix for Super Monaco */
122: /* GP, Super Hang On, Monster Business, European Demo's Intro, BBC Menu 52). */
1.1.1.20! root 123: /* 2014/02/22 [NP] In Exception(), call valid_address() before reading the opcode at BusErrorPC, */
! 124: /* else this will cause an unwanted "double bus error" ("Union Demo" loader). */
! 125: /* 2014/02/22 [NP] In refill_prefetch(), use get_word() instead of do_get_mem_word() to generate */
! 126: /* a bus error when trying to read from an invalid region. */
! 127: /* 2014/03/18 [NP] In Exception(), add a specific case to restore the dest part of a "move" after */
! 128: /* it was overwritten during a bus error (fix the game Dragon Flight). */
! 129: /* 2014/04/06 [NP] In Exception(), add a special case for last_addr_for_exception_3 stored in the */
! 130: /* stack after a bus error (fix the game Batman The Movie). */
1.1.1.12 root 131:
1.1.1.15 root 132: const char NewCpu_fileid[] = "Hatari newcpu.c : " __DATE__ " " __TIME__;
1.1 root 133:
134: #include "sysdeps.h"
135: #include "hatari-glue.h"
136: #include "maccess.h"
137: #include "memory.h"
138: #include "newcpu.h"
1.1.1.16 root 139: #include "main.h"
140: #include "m68000.h"
141: #include "cycInt.h"
142: #include "mfp.h"
143: #include "tos.h"
144: #include "vdi.h"
145: #include "cart.h"
146: #include "dialog.h"
147: #include "bios.h"
148: #include "xbios.h"
1.1.1.17 root 149: #include "screen.h"
1.1.1.16 root 150: #include "video.h"
151: #include "options.h"
152: #include "dsp.h"
153: #include "log.h"
154: #include "debugui.h"
155: #include "debugcpu.h"
1.1.1.17 root 156: #include "68kDisass.h"
1.1 root 157:
1.1.1.20! root 158: #ifdef HAVE_CAPSIMAGE
! 159: #if CAPSIMAGE_VERSION == 5
! 160: #include <caps5/CapsLibAll.h>
! 161: #endif
! 162: #endif
! 163:
1.1.1.12 root 164: //#define DEBUG_PREFETCH
1.1 root 165:
166: struct flag_struct regflags;
167:
168: /* Opcode of faulting instruction */
169: uae_u16 last_op_for_exception_3;
170: /* PC at fault time */
171: uaecptr last_addr_for_exception_3;
172: /* Address that generated the exception */
173: uaecptr last_fault_for_exception_3;
174:
1.1.1.11 root 175: const int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
176: const int imm8_table[] = { 8,1,2,3,4,5,6,7 };
1.1 root 177:
178: int movem_index1[256];
179: int movem_index2[256];
180: int movem_next[256];
181:
182: int fpp_movem_index1[256];
183: int fpp_movem_index2[256];
184: int fpp_movem_next[256];
185:
186: cpuop_func *cpufunctbl[65536];
187:
1.1.1.12 root 188: int OpcodeFamily;
1.1.1.16 root 189: int BusCyclePenalty = 0;
1.1.1.6 root 190:
1.1 root 191: #define COUNT_INSTRS 0
192:
193: #if COUNT_INSTRS
194: static unsigned long int instrcount[65536];
195: static uae_u16 opcodenums[65536];
196:
197: static int compfn (const void *el1, const void *el2)
198: {
199: return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
200: }
201:
202: static char *icountfilename (void)
203: {
204: char *name = getenv ("INSNCOUNT");
205: if (name)
206: return name;
207: return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
208: }
209:
210: void dump_counts (void)
211: {
212: FILE *f = fopen (icountfilename (), "w");
213: unsigned long int total;
214: int i;
215:
216: write_log ("Writing instruction count file...\n");
217: for (i = 0; i < 65536; i++) {
218: opcodenums[i] = i;
219: total += instrcount[i];
220: }
221: qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
222:
223: fprintf (f, "Total: %lu\n", total);
224: for (i=0; i < 65536; i++) {
225: unsigned long int cnt = instrcount[opcodenums[i]];
226: struct instr *dp;
227: struct mnemolookup *lookup;
228: if (!cnt)
229: break;
230: dp = table68k + opcodenums[i];
231: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
232: ;
233: fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
234: }
235: fclose (f);
236: }
237: #else
238: void dump_counts (void)
239: {
240: }
241: #endif
242:
243:
244: static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM;
245:
246: static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
247: {
1.1.1.6 root 248: op_illg (opcode);
1.1 root 249: return 4;
250: }
251:
1.1.1.4 root 252:
253: void build_cpufunctbl(void)
1.1 root 254: {
255: int i;
256: unsigned long opcode;
1.1.1.12 root 257: const struct cputbl *tbl = (currprefs.cpu_level == 4 ? op_smalltbl_0_ff
258: : currprefs.cpu_level == 3 ? op_smalltbl_1_ff
259: : currprefs.cpu_level == 2 ? op_smalltbl_2_ff
260: : currprefs.cpu_level == 1 ? op_smalltbl_3_ff
261: : ! currprefs.cpu_compatible ? op_smalltbl_4_ff
1.1.1.11 root 262: : op_smalltbl_5_ff);
1.1 root 263:
1.1.1.10 root 264: Log_Printf(LOG_DEBUG, "Building CPU function table (%d %d %d).\n",
1.1.1.12 root 265: currprefs.cpu_level, currprefs.cpu_compatible, currprefs.address_space_24);
1.1 root 266:
267: for (opcode = 0; opcode < 65536; opcode++)
1.1.1.6 root 268: cpufunctbl[opcode] = op_illg_1;
1.1 root 269: for (i = 0; tbl[i].handler != NULL; i++) {
270: if (! tbl[i].specific)
1.1.1.6 root 271: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 272: }
273: for (opcode = 0; opcode < 65536; opcode++) {
274: cpuop_func *f;
275:
1.1.1.12 root 276: if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > currprefs.cpu_level)
1.1 root 277: continue;
278:
279: if (table68k[opcode].handler != -1) {
1.1.1.6 root 280: f = cpufunctbl[table68k[opcode].handler];
1.1 root 281: if (f == op_illg_1)
282: abort();
1.1.1.6 root 283: cpufunctbl[opcode] = f;
1.1 root 284: }
285: }
286: for (i = 0; tbl[i].handler != NULL; i++) {
287: if (tbl[i].specific)
1.1.1.6 root 288: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 289: }
290: }
291:
292:
293:
294: void init_m68k (void)
295: {
296: int i;
297:
298: for (i = 0 ; i < 256 ; i++) {
299: int j;
300: for (j = 0 ; j < 8 ; j++) {
301: if (i & (1 << j)) break;
302: }
303: movem_index1[i] = j;
304: movem_index2[i] = 7-j;
305: movem_next[i] = i & (~(1 << j));
306: }
307: for (i = 0 ; i < 256 ; i++) {
308: int j;
309: for (j = 7 ; j >= 0 ; j--) {
310: if (i & (1 << j)) break;
311: }
312: fpp_movem_index1[i] = 7-j;
313: fpp_movem_index2[i] = j;
314: fpp_movem_next[i] = i & (~(1 << j));
315: }
316: #if COUNT_INSTRS
317: {
318: FILE *f = fopen (icountfilename (), "r");
319: memset (instrcount, 0, sizeof instrcount);
320: if (f) {
321: uae_u32 opcode, count, total;
322: char name[20];
323: write_log ("Reading instruction count file...\n");
324: fscanf (f, "Total: %lu\n", &total);
325: while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
326: instrcount[opcode] = count;
327: }
328: fclose(f);
329: }
330: }
331: #endif
332: write_log ("Building CPU table for configuration: 68");
1.1.1.12 root 333: if (currprefs.address_space_24 && currprefs.cpu_level > 1)
1.1 root 334: write_log ("EC");
1.1.1.12 root 335: switch (currprefs.cpu_level) {
1.1 root 336: case 1:
337: write_log ("010");
338: break;
339: case 2:
340: write_log ("020");
341: break;
342: case 3:
343: write_log ("020/881");
344: break;
345: case 4:
346: /* Who is going to miss the MMU anyway...? :-) */
347: write_log ("040");
348: break;
349: default:
350: write_log ("000");
351: break;
352: }
1.1.1.12 root 353: if (currprefs.cpu_compatible)
1.1 root 354: write_log (" (compatible mode)");
355: write_log ("\n");
1.1.1.7 root 356:
1.1 root 357: read_table68k ();
358: do_merges ();
359:
1.1.1.10 root 360: Log_Printf(LOG_DEBUG, "%d CPU functions\n", nr_cpuop_funcs);
1.1 root 361:
362: build_cpufunctbl ();
363: }
364:
1.1.1.4 root 365:
1.1.1.8 root 366: /* not used ATM:
1.1 root 367: static struct regstruct regs_backup[16];
368: static int backup_pointer = 0;
1.1.1.10 root 369: struct regstruct lastint_regs;
370: int lastint_no;
1.1.1.8 root 371: */
1.1.1.10 root 372: struct regstruct regs;
1.1 root 373: static long int m68kpc_offset;
1.1.1.10 root 374:
1.1 root 375:
376: #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
377: #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
378: #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
379:
380: uae_s32 ShowEA (FILE *f, int reg, amodes mode, wordsizes size, char *buf)
381: {
382: uae_u16 dp;
383: uae_s8 disp8;
384: uae_s16 disp16;
385: int r;
386: uae_u32 dispreg;
387: uaecptr addr;
388: uae_s32 offset = 0;
389: char buffer[80];
390:
391: switch (mode){
392: case Dreg:
393: sprintf (buffer,"D%d", reg);
394: break;
395: case Areg:
396: sprintf (buffer,"A%d", reg);
397: break;
398: case Aind:
399: sprintf (buffer,"(A%d)", reg);
400: break;
401: case Aipi:
402: sprintf (buffer,"(A%d)+", reg);
403: break;
404: case Apdi:
405: sprintf (buffer,"-(A%d)", reg);
406: break;
407: case Ad16:
408: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
409: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
410: sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
411: (unsigned long)addr);
412: break;
413: case Ad8r:
414: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
415: disp8 = dp & 0xFF;
416: r = (dp & 0x7000) >> 12;
417: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
418: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
419: dispreg <<= (dp >> 9) & 3;
420:
421: if (dp & 0x100) {
422: uae_s32 outer = 0, disp = 0;
423: uae_s32 base = m68k_areg(regs,reg);
424: char name[10];
425: sprintf (name,"A%d, ",reg);
426: if (dp & 0x80) { base = 0; name[0] = 0; }
427: if (dp & 0x40) dispreg = 0;
428: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
429: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
430: base += disp;
431:
432: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
433: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
434:
435: if (!(dp & 4)) base += dispreg;
436: if (dp & 3) base = get_long (base);
437: if (dp & 4) base += dispreg;
438:
439: addr = base + outer;
440: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
441: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
442: 1 << ((dp >> 9) & 3),
1.1.1.5 root 443: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 444: } else {
445: addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
446: sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
447: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
448: 1 << ((dp >> 9) & 3), disp8,
449: (unsigned long)addr);
450: }
451: break;
452: case PC16:
453: addr = m68k_getpc () + m68kpc_offset;
454: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
455: addr += (uae_s16)disp16;
456: sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
457: break;
458: case PC8r:
459: addr = m68k_getpc () + m68kpc_offset;
460: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
461: disp8 = dp & 0xFF;
462: r = (dp & 0x7000) >> 12;
463: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
464: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
465: dispreg <<= (dp >> 9) & 3;
466:
467: if (dp & 0x100) {
468: uae_s32 outer = 0,disp = 0;
469: uae_s32 base = addr;
470: char name[10];
471: sprintf (name,"PC, ");
472: if (dp & 0x80) { base = 0; name[0] = 0; }
473: if (dp & 0x40) dispreg = 0;
474: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
475: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
476: base += disp;
477:
478: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
479: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
480:
481: if (!(dp & 4)) base += dispreg;
482: if (dp & 3) base = get_long (base);
483: if (dp & 4) base += dispreg;
484:
485: addr = base + outer;
486: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
487: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
488: 1 << ((dp >> 9) & 3),
1.1.1.5 root 489: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 490: } else {
491: addr += (uae_s32)((uae_s8)disp8) + dispreg;
492: sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
493: (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
494: disp8, (unsigned long)addr);
495: }
496: break;
497: case absw:
498: sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
499: m68kpc_offset += 2;
500: break;
501: case absl:
502: sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
503: m68kpc_offset += 4;
504: break;
505: case imm:
506: switch (size){
507: case sz_byte:
508: sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
509: m68kpc_offset += 2;
510: break;
511: case sz_word:
512: sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
513: m68kpc_offset += 2;
514: break;
515: case sz_long:
516: sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
517: m68kpc_offset += 4;
518: break;
519: default:
520: break;
521: }
522: break;
523: case imm0:
524: offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
525: m68kpc_offset += 2;
526: sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
527: break;
528: case imm1:
529: offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
530: m68kpc_offset += 2;
531: sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
532: break;
533: case imm2:
534: offset = (uae_s32)get_ilong_1 (m68kpc_offset);
535: m68kpc_offset += 4;
536: sprintf (buffer,"#$%08lx", (unsigned long)offset);
537: break;
538: case immi:
539: offset = (uae_s32)(uae_s8)(reg & 0xff);
540: sprintf (buffer,"#$%08lx", (unsigned long)offset);
541: break;
542: default:
543: break;
544: }
545: if (buf == 0)
546: fprintf (f, "%s", buffer);
547: else
548: strcat (buf, buffer);
549: return offset;
550: }
551:
1.1.1.8 root 552:
1.1 root 553: /* The plan is that this will take over the job of exception 3 handling -
554: * the CPU emulation functions will just do a longjmp to m68k_go whenever
555: * they hit an odd address. */
1.1.1.8 root 556: #if 0
1.1 root 557: static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
558: {
559: uae_u16 dp;
560: uae_s8 disp8;
561: uae_s16 disp16;
562: int r;
563: uae_u32 dispreg;
564: uaecptr addr;
1.1.1.5 root 565: /*uae_s32 offset = 0;*/
1.1 root 566:
567: switch (mode){
568: case Dreg:
569: *val = m68k_dreg (regs, reg);
570: return 1;
571: case Areg:
572: *val = m68k_areg (regs, reg);
573: return 1;
574:
575: case Aind:
576: case Aipi:
577: addr = m68k_areg (regs, reg);
578: break;
579: case Apdi:
580: addr = m68k_areg (regs, reg);
581: break;
582: case Ad16:
583: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
584: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
585: break;
586: case Ad8r:
587: addr = m68k_areg (regs, reg);
588: d8r_common:
589: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
590: disp8 = dp & 0xFF;
591: r = (dp & 0x7000) >> 12;
592: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
593: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
594: dispreg <<= (dp >> 9) & 3;
595:
596: if (dp & 0x100) {
597: uae_s32 outer = 0, disp = 0;
598: uae_s32 base = addr;
599: if (dp & 0x80) base = 0;
600: if (dp & 0x40) dispreg = 0;
601: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
602: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
603: base += disp;
604:
605: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
606: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
607:
608: if (!(dp & 4)) base += dispreg;
609: if (dp & 3) base = get_long (base);
610: if (dp & 4) base += dispreg;
611:
612: addr = base + outer;
613: } else {
614: addr += (uae_s32)((uae_s8)disp8) + dispreg;
615: }
616: break;
617: case PC16:
618: addr = m68k_getpc () + m68kpc_offset;
619: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
620: addr += (uae_s16)disp16;
621: break;
622: case PC8r:
623: addr = m68k_getpc () + m68kpc_offset;
624: goto d8r_common;
625: case absw:
626: addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
627: m68kpc_offset += 2;
628: break;
629: case absl:
630: addr = get_ilong_1 (m68kpc_offset);
631: m68kpc_offset += 4;
632: break;
633: case imm:
634: switch (size){
635: case sz_byte:
636: *val = get_iword_1 (m68kpc_offset) & 0xff;
637: m68kpc_offset += 2;
638: break;
639: case sz_word:
640: *val = get_iword_1 (m68kpc_offset) & 0xffff;
641: m68kpc_offset += 2;
642: break;
643: case sz_long:
644: *val = get_ilong_1 (m68kpc_offset);
645: m68kpc_offset += 4;
646: break;
647: default:
648: break;
649: }
650: return 1;
651: case imm0:
652: *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
653: m68kpc_offset += 2;
654: return 1;
655: case imm1:
656: *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
657: m68kpc_offset += 2;
658: return 1;
659: case imm2:
660: *val = get_ilong_1 (m68kpc_offset);
661: m68kpc_offset += 4;
662: return 1;
663: case immi:
664: *val = (uae_s32)(uae_s8)(reg & 0xff);
665: return 1;
666: default:
667: addr = 0;
668: break;
669: }
670: if ((addr & 1) == 0)
671: return 1;
672:
673: last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
674: last_fault_for_exception_3 = addr;
675: return 0;
676: }
1.1.1.8 root 677: #endif
678:
1.1 root 679:
680: uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
681: {
682: int reg = (dp >> 12) & 15;
683: uae_s32 regd = regs.regs[reg];
684: if ((dp & 0x800) == 0)
685: regd = (uae_s32)(uae_s16)regd;
686: regd <<= (dp >> 9) & 3;
687: if (dp & 0x100) {
688: uae_s32 outer = 0;
689: if (dp & 0x80) base = 0;
690: if (dp & 0x40) regd = 0;
691:
692: if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
693: if ((dp & 0x30) == 0x30) base += next_ilong();
694:
695: if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
696: if ((dp & 0x3) == 0x3) outer = next_ilong();
697:
698: if ((dp & 0x4) == 0) base += regd;
699: if (dp & 0x3) base = get_long (base);
700: if (dp & 0x4) base += regd;
701:
702: return base + outer;
703: } else {
704: return base + (uae_s32)((uae_s8)dp) + regd;
705: }
706: }
707:
708: uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
709: {
710: int reg = (dp >> 12) & 15;
711: uae_s32 regd = regs.regs[reg];
712: #if 1
713: if ((dp & 0x800) == 0)
714: regd = (uae_s32)(uae_s16)regd;
715: return base + (uae_s8)dp + regd;
716: #else
717: /* Branch-free code... benchmark this again now that
718: * things are no longer inline. */
719: uae_s32 regd16;
720: uae_u32 mask;
721: mask = ((dp & 0x800) >> 11) - 1;
722: regd16 = (uae_s32)(uae_s16)regd;
723: regd16 &= mask;
724: mask = ~mask;
725: base += (uae_s8)dp;
726: regd &= mask;
727: regd |= regd16;
728: return base + regd;
729: #endif
730: }
731:
1.1.1.8 root 732:
733: /* Create the Status Register from the flags */
1.1 root 734: void MakeSR (void)
735: {
736: #if 0
737: assert((regs.t1 & 1) == regs.t1);
738: assert((regs.t0 & 1) == regs.t0);
739: assert((regs.s & 1) == regs.s);
740: assert((regs.m & 1) == regs.m);
741: assert((XFLG & 1) == XFLG);
742: assert((NFLG & 1) == NFLG);
743: assert((ZFLG & 1) == ZFLG);
744: assert((VFLG & 1) == VFLG);
745: assert((CFLG & 1) == CFLG);
746: #endif
747: regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
748: | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
749: | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
750: | GET_CFLG);
751: }
752:
1.1.1.8 root 753:
754: /* Set up the flags from Status Register */
1.1 root 755: void MakeFromSR (void)
756: {
757: int oldm = regs.m;
758: int olds = regs.s;
759:
760: regs.t1 = (regs.sr >> 15) & 1;
761: regs.t0 = (regs.sr >> 14) & 1;
762: regs.s = (regs.sr >> 13) & 1;
763: regs.m = (regs.sr >> 12) & 1;
764: regs.intmask = (regs.sr >> 8) & 7;
765: SET_XFLG ((regs.sr >> 4) & 1);
766: SET_NFLG ((regs.sr >> 3) & 1);
767: SET_ZFLG ((regs.sr >> 2) & 1);
768: SET_VFLG ((regs.sr >> 1) & 1);
769: SET_CFLG (regs.sr & 1);
1.1.1.12 root 770: if (currprefs.cpu_level >= 2) {
1.1 root 771: if (olds != regs.s) {
772: if (olds) {
773: if (oldm)
774: regs.msp = m68k_areg(regs, 7);
775: else
776: regs.isp = m68k_areg(regs, 7);
777: m68k_areg(regs, 7) = regs.usp;
778: } else {
779: regs.usp = m68k_areg(regs, 7);
780: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
781: }
782: } else if (olds && oldm != regs.m) {
783: if (oldm) {
784: regs.msp = m68k_areg(regs, 7);
785: m68k_areg(regs, 7) = regs.isp;
786: } else {
787: regs.isp = m68k_areg(regs, 7);
788: m68k_areg(regs, 7) = regs.msp;
789: }
790: }
791: } else {
1.1.1.12 root 792: /* [NP] If cpu < 68020, m and t0 are ignored and should be set to 0 */
793: regs.t0 = 0;
794: regs.m = 0;
795:
1.1 root 796: if (olds != regs.s) {
797: if (olds) {
798: regs.isp = m68k_areg(regs, 7);
799: m68k_areg(regs, 7) = regs.usp;
800: } else {
801: regs.usp = m68k_areg(regs, 7);
802: m68k_areg(regs, 7) = regs.isp;
803: }
804: }
805: }
806:
1.1.1.8 root 807: /* Pending interrupts can occur again after a write to the SR: */
808: set_special (SPCFLAG_DOINT);
1.1 root 809: if (regs.t1 || regs.t0)
810: set_special (SPCFLAG_TRACE);
811: else
1.1.1.6 root 812: /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
813: SR-modifying instructions (including STOP). */
814: unset_special (SPCFLAG_TRACE);
1.1 root 815: }
816:
1.1.1.5 root 817:
1.1.1.12 root 818: static void exception_trace (int nr)
819: {
820: unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
821: if (regs.t1 && !regs.t0) {
822: /* trace stays pending if exception is div by zero, chk,
823: * trapv or trap #x
824: */
825: if (nr == 5 || nr == 6 || nr == 7 || (nr >= 32 && nr <= 47))
826: set_special (SPCFLAG_DOTRACE);
827: }
828: regs.t1 = regs.t0 = regs.m = 0;
829: }
830:
831:
1.1.1.14 root 832: /*
833: * Compute the number of jitter cycles to add when a video interrupt occurs
834: * (this is specific to the Atari ST)
835: */
836: static void InterruptAddJitter (int Level , int Pending)
837: {
838: int cycles = 0;
839:
840: if ( Level == 2 ) /* HBL */
841: {
842: if ( Pending )
843: cycles = HblJitterArrayPending[ HblJitterIndex ];
844: else
845: cycles = HblJitterArray[ HblJitterIndex ];
846: }
847:
848: else if ( Level == 4 ) /* VBL */
849: {
850: if ( Pending )
851: cycles = VblJitterArrayPending[ VblJitterIndex ];
852: else
853: cycles = VblJitterArray[ VblJitterIndex ];
854: }
855:
856: //fprintf ( stderr , "jitter %d\n" , cycles );
857: //cycles=0;
858: if ( cycles > 0 ) /* no need to call M68000_AddCycles if cycles == 0 */
859: M68000_AddCycles ( cycles );
860: }
861:
862:
1.1.1.13 root 863: /* Handle exceptions. We need a special case to handle MFP exceptions */
864: /* on Atari ST, because it's possible to change the MFP's vector base */
865: /* and get a conflict with 'normal' cpu exceptions. */
866: void Exception(int nr, uaecptr oldpc, int ExceptionSource)
1.1 root 867: {
1.1.1.17 root 868: uae_u32 currpc = m68k_getpc () , newpc;
1.1 root 869:
1.1.1.2 root 870: /*if( nr>=2 && nr<10 ) fprintf(stderr,"Exception (-> %i bombs)!\n",nr);*/
1.1 root 871:
1.1.1.19 root 872: /* Pending bits / vector number can change before the end of the IACK sequence. */
873: /* We need to handle MFP and HBL/VBL cases for this. */
874: if ( ExceptionSource == M68000_EXC_SRC_INT_MFP )
875: {
876: M68000_AddCycles ( CPU_IACK_CYCLES_MFP );
877: CPU_IACK = true;
878: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
879: CALL_VAR(PendingInterruptFunction);
880: nr = MFP_ProcessIACK ( nr );
881: CPU_IACK = false;
882: }
1.1.1.20! root 883: else if ( ( ExceptionSource == M68000_EXC_SRC_AUTOVEC ) && ( ( nr == 26 ) || ( nr == 28 ) ) )
1.1.1.19 root 884: {
885: M68000_AddCycles ( CPU_IACK_CYCLES_VIDEO );
886: CPU_IACK = true;
887: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
888: CALL_VAR(PendingInterruptFunction);
1.1.1.20! root 889: if ( MFP_UpdateNeeded == true )
! 890: MFP_UpdateIRQ ( 0 ); /* update MFP's state if some internal timers related to MFP expired */
1.1.1.19 root 891: pendingInterrupts &= ~( 1 << ( nr - 24 ) ); /* clear HBL or VBL pending bit */
892: CPU_IACK = false;
893: }
894:
895:
1.1.1.16 root 896: if (ExceptionSource == M68000_EXC_SRC_CPU)
1.1.1.5 root 897: {
1.1.1.20! root 898: if (nr == 0x22)
1.1.1.13 root 899: {
1.1.1.17 root 900: /* Intercept VDI & AES exceptions (Trap #2) */
1.1.1.20! root 901: if(bVdiAesIntercept && VDI_AES_Entry())
1.1.1.13 root 902: {
1.1.1.17 root 903: /* Set 'PC' to address of 'VDI_OPCODE' illegal instruction.
904: * This will call OpCode_VDI() after completion of Trap call!
905: * This is used to modify specific VDI return vectors contents.
906: */
1.1.1.13 root 907: VDI_OldPC = currpc;
908: currpc = CART_VDI_OPCODE_ADDR;
909: }
910: }
1.1.1.20! root 911: else if (nr == 0x2d)
1.1.1.13 root 912: {
1.1.1.20! root 913: /* Intercept BIOS (Trap #13) calls */
! 914: if (Bios()) return;
! 915: }
! 916: else if (nr == 0x2e)
! 917: {
! 918: /* Intercept XBIOS (Trap #14) calls */
! 919: if (XBios()) return;
1.1.1.13 root 920: }
1.1.1.5 root 921: }
1.1.1.8 root 922:
1.1 root 923: MakeSR();
924:
1.1.1.8 root 925: /* Change to supervisor mode if necessary */
1.1 root 926: if (!regs.s) {
927: regs.usp = m68k_areg(regs, 7);
1.1.1.12 root 928: if (currprefs.cpu_level >= 2)
1.1 root 929: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
930: else
931: m68k_areg(regs, 7) = regs.isp;
932: regs.s = 1;
933: }
1.1.1.8 root 934:
935: /* Build additional exception stack frame for 68010 and higher */
1.1.1.13 root 936: /* (special case for MFP) */
1.1.1.12 root 937: if (currprefs.cpu_level > 0) {
1.1.1.16 root 938: if (ExceptionSource == M68000_EXC_SRC_INT_MFP
939: || ExceptionSource == M68000_EXC_SRC_INT_DSP) {
1.1.1.13 root 940: m68k_areg(regs, 7) -= 2;
941: put_word (m68k_areg(regs, 7), nr * 4); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
942: }
943: else if (nr == 2 || nr == 3) {
1.1 root 944: int i;
945: /* @@@ this is probably wrong (?) */
946: for (i = 0 ; i < 12 ; i++) {
947: m68k_areg(regs, 7) -= 2;
948: put_word (m68k_areg(regs, 7), 0);
949: }
950: m68k_areg(regs, 7) -= 2;
951: put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
952: } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
953: m68k_areg(regs, 7) -= 4;
954: put_long (m68k_areg(regs, 7), oldpc);
955: m68k_areg(regs, 7) -= 2;
956: put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
957: } else if (regs.m && nr >= 24 && nr < 32) {
958: m68k_areg(regs, 7) -= 2;
959: put_word (m68k_areg(regs, 7), nr * 4);
960: m68k_areg(regs, 7) -= 4;
961: put_long (m68k_areg(regs, 7), currpc);
962: m68k_areg(regs, 7) -= 2;
963: put_word (m68k_areg(regs, 7), regs.sr);
964: regs.sr |= (1 << 13);
965: regs.msp = m68k_areg(regs, 7);
966: m68k_areg(regs, 7) = regs.isp;
967: m68k_areg(regs, 7) -= 2;
968: put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
969: } else {
970: m68k_areg(regs, 7) -= 2;
971: put_word (m68k_areg(regs, 7), nr * 4);
972: }
973: }
1.1.1.3 root 974:
975: /* Push PC on stack: */
1.1 root 976: m68k_areg(regs, 7) -= 4;
977: put_long (m68k_areg(regs, 7), currpc);
1.1.1.3 root 978: /* Push SR on stack: */
1.1 root 979: m68k_areg(regs, 7) -= 2;
980: put_word (m68k_areg(regs, 7), regs.sr);
1.1.1.3 root 981:
1.1.1.15 root 982: LOG_TRACE(TRACE_CPU_EXCEPTION, "cpu exception %d currpc %x buspc %x newpc %x fault_e3 %x op_e3 %hx addr_e3 %x\n",
983: nr, currpc, BusErrorPC, get_long (regs.vbr + 4*nr), last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3);
1.1.1.12 root 984:
1.1.1.3 root 985: /* 68000 bus/address errors: */
1.1.1.16 root 986: if (currprefs.cpu_level==0 && (nr==2 || nr==3) && ExceptionSource == M68000_EXC_SRC_CPU) {
1.1.1.12 root 987: uae_u16 specialstatus = 1;
1.1.1.20! root 988: uae_u16 BusError_opcode;
1.1.1.12 root 989:
1.1.1.8 root 990: /* Special status word emulation isn't perfect yet... :-( */
991: if (regs.sr & 0x2000)
992: specialstatus |= 0x4;
1.1.1.3 root 993: m68k_areg(regs, 7) -= 8;
994: if (nr == 3) { /* Address error */
1.1.1.12 root 995: specialstatus |= ( last_op_for_exception_3 & (~0x1f) ); /* [NP] unused bits of specialstatus are those of the last opcode ! */
1.1.1.8 root 996: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.3 root 997: put_long (m68k_areg(regs, 7)+2, last_fault_for_exception_3);
998: put_word (m68k_areg(regs, 7)+6, last_op_for_exception_3);
999: put_long (m68k_areg(regs, 7)+10, last_addr_for_exception_3);
1.1.1.20! root 1000: if (ExceptionDebugMask & EXCEPT_ADDRESS) {
1.1.1.8 root 1001: fprintf(stderr,"Address Error at address $%x, PC=$%x\n",last_fault_for_exception_3,currpc);
1.1.1.18 root 1002: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.8 root 1003: }
1.1.1.3 root 1004: }
1.1.1.8 root 1005: else { /* Bus error */
1.1.1.20! root 1006: /* Get the opcode that caused the bus error, to adapt the stack frame in some cases */
! 1007: /* (we must call get_word() only on valid region, else this will cause a double bus error) */
! 1008: if ( valid_address ( BusErrorPC , 2 ) )
! 1009: BusError_opcode = get_word(BusErrorPC);
! 1010: else
! 1011: BusError_opcode = 0;
! 1012:
! 1013: specialstatus |= ( BusError_opcode & (~0x1f) ); /* [NP] unused bits of special status are those of the last opcode ! */
1.1.1.8 root 1014: if (bBusErrorReadWrite)
1015: specialstatus |= 0x10;
1016: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.10 root 1017: put_long (m68k_areg(regs, 7)+2, BusErrorAddress);
1.1.1.20! root 1018: put_word (m68k_areg(regs, 7)+6, BusError_opcode); /* Opcode */
1.1.1.12 root 1019:
1020: /* [NP] PC stored in the stack frame is not necessarily pointing to the next instruction ! */
1021: /* FIXME : we should have a proper model for this, in the meantime we handle specific cases */
1.1.1.20! root 1022: if ( BusError_opcode == 0x21f8 ) /* move.l $0.w,$24.w (Transbeauce 2 loader) */
! 1023: put_long (m68k_areg(regs, 7)+10, currpc-2); /* correct PC is 2 bytes less than usual value */
! 1024:
! 1025: else if ( ( BusErrorPC == 0xccc ) && ( BusError_opcode == 0x48d6 ) ) /* 48d6 3f00 movem.l a0-a5,(a6) (Blood Money) */
! 1026: put_long (m68k_areg(regs, 7)+10, currpc+2); /* correct PC is 2 bytes more than usual value */
! 1027:
! 1028: else if ( ( BusErrorPC == 0x1fece ) && ( BusError_opcode == 0x33d4 ) ) /* 1fece : 33d4 0001 fdca move.w (a4),$1fdca (Batman The Movie) */
! 1029: put_long (m68k_areg(regs, 7)+10, currpc-4); /* correct PC is 4 bytes less than usual value */
! 1030:
! 1031: /* [NP] In case of a move with a bus error on the read part, uae cpu is writing to the dest part */
! 1032: /* then process the bus error ; on a real CPU, the bus error occurs after the read and before the */
! 1033: /* write, so the dest part doesn't change. For now, we restore the dest part on some specific cases */
! 1034: /* FIXME : the bus error should be processed just after the read, not at the end of the instruction */
! 1035: else if ( ( BusErrorPC == 0x62a ) && ( BusError_opcode == 0x3079 ) ) /* 3079 4ef9 0000 move.l $4ef90000,a0 (Dragon Flight) */
! 1036: m68k_areg(regs, 0) = 8; /* A0 should not be changed to "0" but keep its value "8" */
! 1037:
! 1038: else if ( get_long(BusErrorPC) == 0x13f88e21 ) /* 13f8 8e21 move.b $ffff8e21.w,$xxxxx (Tymewarp) */
! 1039: put_byte ( get_long(BusErrorPC+4) , 0x00 ); /* dest content should not be changed to "ff" but keep its value "00" */
! 1040:
! 1041: fprintf(stderr,"Bus Error at address $%x, PC=$%lx %x %x\n", BusErrorAddress, (long)currpc, BusErrorPC , BusError_opcode);
! 1042:
1.1.1.8 root 1043: /* Check for double bus errors: */
1044: if (regs.spcflags & SPCFLAG_BUSERROR) {
1045: fprintf(stderr, "Detected double bus error at address $%x, PC=$%lx => CPU halted!\n",
1.1.1.10 root 1046: BusErrorAddress, (long)currpc);
1.1.1.8 root 1047: unset_special(SPCFLAG_BUSERROR);
1.1.1.20! root 1048: if (ExceptionDebugMask & EXCEPT_BUS)
1.1.1.18 root 1049: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.15 root 1050: else
1.1.1.17 root 1051: DlgAlert_Notice("Detected double bus error => CPU halted!\nEmulation needs to be reset.\n");
1.1.1.8 root 1052: regs.intmask = 7;
1.1.1.15 root 1053: m68k_setstopped(true);
1.1.1.8 root 1054: return;
1055: }
1.1.1.20! root 1056: if ((ExceptionDebugMask & EXCEPT_BUS) && BusErrorAddress!=0xff8a00) {
1.1.1.10 root 1057: fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n", BusErrorAddress, (long)currpc);
1.1.1.18 root 1058: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.8 root 1059: }
1060: }
1.1.1.3 root 1061: }
1062:
1.1.1.8 root 1063: /* Set PC and flags */
1.1.1.20! root 1064: if ((ExceptionDebugMask & EXCEPT_NOHANDLER) && (regs.vbr + 4*nr) == 0) {
! 1065: fprintf(stderr,"Uninitialized exception handler #%i!\n", nr);
1.1.1.18 root 1066: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.8 root 1067: }
1.1.1.17 root 1068: newpc = get_long (regs.vbr + 4*nr);
1069: if ( newpc & 1) /* check new pc is even */
1070: {
1071: if ( nr==2 || nr==3 ) /* address error during bus/address error -> stop emulation */
1072: {
1.1.1.20! root 1073: fprintf(stderr,"Address Error during exception 2/3, aborting new PC=$%x\n",newpc);
! 1074: if (ExceptionDebugMask & (EXCEPT_BUS|EXCEPT_ADDRESS))
! 1075: DebugUI(REASON_CPU_EXCEPTION);
! 1076: else
! 1077: DlgAlert_Notice("Address Error during exception 2/3 => CPU halted!\nEmulation needs to be reset.\n");
1.1.1.17 root 1078: }
1079: else
1080: {
1081: fprintf(stderr,"Address Error during exception, new PC=$%x\n",newpc);
1082: Exception ( 3 , m68k_getpc() , M68000_EXC_SRC_CPU );
1083: }
1084: return;
1085: }
1.1.1.20! root 1086: /* handle debugger invocation for rest of exceptions */
! 1087: if (ExceptionDebugMask && nr > 3 && nr < 9)
! 1088: DebugUI_Exceptions(nr, currpc);
1.1.1.17 root 1089:
1.1 root 1090: m68k_setpc (get_long (regs.vbr + 4*nr));
1091: fill_prefetch_0 ();
1.1.1.12 root 1092: /* Handle trace flags depending on current state */
1093: exception_trace (nr);
1.1.1.6 root 1094:
1.1.1.13 root 1095: /* Handle exception cycles (special case for MFP) */
1.1.1.16 root 1096: if (ExceptionSource == M68000_EXC_SRC_INT_MFP)
1.1.1.13 root 1097: {
1.1.1.19 root 1098: M68000_AddCycles(44+12-CPU_IACK_CYCLES_MFP); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
1.1.1.13 root 1099: }
1100: else if (nr >= 24 && nr <= 31)
1.1.1.7 root 1101: {
1.1.1.19 root 1102: if ( nr == 26 ) /* HBL */
1103: M68000_AddCycles(44+12-CPU_IACK_CYCLES_VIDEO); /* Video Interrupt */
1104: else if ( nr == 28 ) /* VBL */
1105: M68000_AddCycles(44+12-CPU_IACK_CYCLES_VIDEO); /* Video Interrupt */
1.1.1.12 root 1106: else
1.1.1.19 root 1107: M68000_AddCycles(44+4); /* Other Interrupts */
1.1.1.7 root 1108: }
1109: else if(nr >= 32 && nr <= 47)
1110: {
1.1.1.13 root 1111: M68000_AddCycles(34-4); /* Trap (total is 34, but cpuemu.c already adds 4) */
1.1.1.7 root 1112: }
1113: else switch(nr)
1114: {
1.1.1.12 root 1115: case 2: M68000_AddCycles(50); break; /* Bus error */
1116: case 3: M68000_AddCycles(50); break; /* Address error */
1117: case 4: M68000_AddCycles(34); break; /* Illegal instruction */
1118: case 5: M68000_AddCycles(38); break; /* Div by zero */
1119: case 6: M68000_AddCycles(40); break; /* CHK */
1120: case 7: M68000_AddCycles(34); break; /* TRAPV */
1121: case 8: M68000_AddCycles(34); break; /* Privilege violation */
1122: case 9: M68000_AddCycles(34); break; /* Trace */
1123: case 10: M68000_AddCycles(34); break; /* Line-A - probably wrong */
1124: case 11: M68000_AddCycles(34); break; /* Line-F - probably wrong */
1.1.1.7 root 1125: default:
1.1.1.8 root 1126: /* FIXME: Add right cycles value for MFP interrupts and copro exceptions ... */
1.1.1.7 root 1127: if(nr < 64)
1.1.1.12 root 1128: M68000_AddCycles(4); /* Coprocessor and unassigned exceptions (???) */
1.1.1.7 root 1129: else
1.1.1.16 root 1130: M68000_AddCycles(44+12); /* Must be a MFP or DSP interrupt */
1.1.1.7 root 1131: break;
1.1.1.6 root 1132: }
1.1.1.14 root 1133:
1.1 root 1134: }
1135:
1.1.1.7 root 1136:
1.1.1.14 root 1137: static void Interrupt(int nr , int Pending)
1.1 root 1138: {
1139: assert(nr < 8 && nr >= 0);
1.1.1.10 root 1140: /*lastint_regs = regs;*/
1141: /*lastint_no = nr;*/
1.1.1.13 root 1142:
1.1.1.16 root 1143: /* On Hatari, only video ints are using SPCFLAG_INT (see m68000.c) */
1144: Exception(nr+24, 0, M68000_EXC_SRC_AUTOVEC);
1.1 root 1145:
1146: regs.intmask = nr;
1147: set_special (SPCFLAG_INT);
1.1.1.14 root 1148:
1149: /* Handle Atari ST's specific jitter for hbl/vbl */
1150: InterruptAddJitter ( nr , Pending );
1.1 root 1151: }
1152:
1.1.1.7 root 1153:
1.1.1.12 root 1154: uae_u32 caar, cacr;
1.1.1.8 root 1155: static uae_u32 itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp;
1.1 root 1156:
1.1.1.7 root 1157:
1.1.1.12 root 1158: static int movec_illg (int regno)
1159: {
1160: int regno2 = regno & 0x7ff;
1161: if (currprefs.cpu_level == 1) { /* 68010 */
1162: if (regno2 < 2)
1163: return 0;
1164: return 1;
1165: }
1166: if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) { /* 68020 */
1167: if (regno == 3) return 1; /* 68040 only */
1168: /* 4 is >=68040, but 0x804 is in 68020 */
1169: if (regno2 < 4 || regno == 0x804)
1170: return 0;
1171: return 1;
1172: }
1173: if (currprefs.cpu_level >= 4) { /* 68040 */
1174: if (regno == 0x802) return 1; /* 68020 only */
1175: if (regno2 < 8) return 0;
1176: if (currprefs.cpu_level == 6 && regno2 == 8) /* 68060 only */
1177: return 0;
1178: return 1;
1179: }
1180: return 1;
1181: }
1182:
1.1 root 1183: int m68k_move2c (int regno, uae_u32 *regp)
1184: {
1.1.1.12 root 1185: if (movec_illg (regno)) {
1.1 root 1186: op_illg (0x4E7B);
1187: return 0;
1188: } else {
1189: switch (regno) {
1190: case 0: regs.sfc = *regp & 7; break;
1191: case 1: regs.dfc = *regp & 7; break;
1.1.1.16 root 1192: case 2:
1193: {
1194: uae_u32 cacr_mask = 0;
1195: if (currprefs.cpu_level == 2) // 68020
1196: cacr_mask = 0x0000000f;
1197: else if (currprefs.cpu_level == 3) // Fake 68030
1198: cacr_mask = 0x00003f1f;
1199: else if (currprefs.cpu_level == 4) // 68040
1200: cacr_mask = 0x80008000;
1201: cacr = *regp & cacr_mask;
1202: }
1.1 root 1203: case 3: tc = *regp & 0xc000; break;
1204: /* Mask out fields that should be zero. */
1205: case 4: itt0 = *regp & 0xffffe364; break;
1206: case 5: itt1 = *regp & 0xffffe364; break;
1207: case 6: dtt0 = *regp & 0xffffe364; break;
1208: case 7: dtt1 = *regp & 0xffffe364; break;
1.1.1.7 root 1209:
1.1 root 1210: case 0x800: regs.usp = *regp; break;
1211: case 0x801: regs.vbr = *regp; break;
1.1.1.20! root 1212: case 0x802: caar = *regp; break;
1.1 root 1213: case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
1214: case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
1.1.1.6 root 1215: case 0x805: mmusr = *regp; break;
1216: case 0x806: urp = *regp; break;
1217: case 0x807: srp = *regp; break;
1.1 root 1218: default:
1219: op_illg (0x4E7B);
1220: return 0;
1221: }
1222: }
1223: return 1;
1224: }
1225:
1226: int m68k_movec2 (int regno, uae_u32 *regp)
1227: {
1.1.1.12 root 1228: if (movec_illg (regno)) {
1.1 root 1229: op_illg (0x4E7A);
1230: return 0;
1231: } else {
1232: switch (regno) {
1233: case 0: *regp = regs.sfc; break;
1234: case 1: *regp = regs.dfc; break;
1.1.1.12 root 1235: case 2: *regp = cacr; break;
1.1 root 1236: case 3: *regp = tc; break;
1237: case 4: *regp = itt0; break;
1238: case 5: *regp = itt1; break;
1239: case 6: *regp = dtt0; break;
1240: case 7: *regp = dtt1; break;
1241: case 0x800: *regp = regs.usp; break;
1242: case 0x801: *regp = regs.vbr; break;
1.1.1.12 root 1243: case 0x802: *regp = caar; break;
1.1 root 1244: case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
1245: case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
1246: case 0x805: *regp = mmusr; break;
1.1.1.6 root 1247: case 0x806: *regp = urp; break;
1248: case 0x807: *regp = srp; break;
1.1 root 1249: default:
1250: op_illg (0x4E7A);
1251: return 0;
1252: }
1253: }
1254: return 1;
1255: }
1256:
1257: STATIC_INLINE int
1.1.1.10 root 1258: div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 ndiv, uae_u32 *quot, uae_u32 *rem)
1.1 root 1259: {
1260: uae_u32 q = 0, cbit = 0;
1261: int i;
1262:
1.1.1.10 root 1263: if (ndiv <= src_hi) {
1.1 root 1264: return 1;
1265: }
1266: for (i = 0 ; i < 32 ; i++) {
1267: cbit = src_hi & 0x80000000ul;
1268: src_hi <<= 1;
1269: if (src_lo & 0x80000000ul) src_hi++;
1270: src_lo <<= 1;
1271: q = q << 1;
1.1.1.10 root 1272: if (cbit || ndiv <= src_hi) {
1.1 root 1273: q |= 1;
1.1.1.10 root 1274: src_hi -= ndiv;
1.1 root 1275: }
1276: }
1277: *quot = q;
1278: *rem = src_hi;
1279: return 0;
1280: }
1281:
1282: void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
1283: {
1284: #if defined(uae_s64)
1285: if (src == 0) {
1.1.1.16 root 1286: Exception (5, oldpc,M68000_EXC_SRC_CPU);
1.1 root 1287: return;
1288: }
1289: if (extra & 0x800) {
1290: /* signed variant */
1291: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1292: uae_s64 quot, rem;
1293:
1294: if (extra & 0x400) {
1295: a &= 0xffffffffu;
1296: a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
1297: }
1298: rem = a % (uae_s64)(uae_s32)src;
1299: quot = a / (uae_s64)(uae_s32)src;
1300: if ((quot & UVAL64(0xffffffff80000000)) != 0
1301: && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1302: {
1303: SET_VFLG (1);
1304: SET_NFLG (1);
1305: SET_CFLG (0);
1306: } else {
1307: if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
1308: SET_VFLG (0);
1309: SET_CFLG (0);
1310: SET_ZFLG (((uae_s32)quot) == 0);
1311: SET_NFLG (((uae_s32)quot) < 0);
1312: m68k_dreg(regs, extra & 7) = rem;
1313: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1314: }
1315: } else {
1316: /* unsigned */
1317: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1318: uae_u64 quot, rem;
1319:
1320: if (extra & 0x400) {
1321: a &= 0xffffffffu;
1322: a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
1323: }
1324: rem = a % (uae_u64)src;
1325: quot = a / (uae_u64)src;
1326: if (quot > 0xffffffffu) {
1327: SET_VFLG (1);
1328: SET_NFLG (1);
1329: SET_CFLG (0);
1330: } else {
1331: SET_VFLG (0);
1332: SET_CFLG (0);
1333: SET_ZFLG (((uae_s32)quot) == 0);
1334: SET_NFLG (((uae_s32)quot) < 0);
1335: m68k_dreg(regs, extra & 7) = rem;
1336: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1337: }
1338: }
1339: #else
1340: if (src == 0) {
1.1.1.16 root 1341: Exception (5, oldpc,M68000_EXC_SRC_CPU);
1.1 root 1342: return;
1343: }
1344: if (extra & 0x800) {
1345: /* signed variant */
1346: uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1347: uae_s32 hi = lo < 0 ? -1 : 0;
1348: uae_s32 save_high;
1349: uae_u32 quot, rem;
1350: uae_u32 sign;
1351:
1352: if (extra & 0x400) {
1353: hi = (uae_s32)m68k_dreg(regs, extra & 7);
1354: }
1355: save_high = hi;
1356: sign = (hi ^ src);
1357: if (hi < 0) {
1358: hi = ~hi;
1359: lo = -lo;
1360: if (lo == 0) hi++;
1361: }
1362: if ((uae_s32)src < 0) src = -src;
1363: if (div_unsigned(hi, lo, src, ", &rem) ||
1364: (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
1365: SET_VFLG (1);
1366: SET_NFLG (1);
1367: SET_CFLG (0);
1368: } else {
1369: if (sign & 0x80000000) quot = -quot;
1370: if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
1371: SET_VFLG (0);
1372: SET_CFLG (0);
1373: SET_ZFLG (((uae_s32)quot) == 0);
1374: SET_NFLG (((uae_s32)quot) < 0);
1375: m68k_dreg(regs, extra & 7) = rem;
1376: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1377: }
1378: } else {
1379: /* unsigned */
1380: uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1381: uae_u32 hi = 0;
1382: uae_u32 quot, rem;
1383:
1384: if (extra & 0x400) {
1385: hi = (uae_u32)m68k_dreg(regs, extra & 7);
1386: }
1387: if (div_unsigned(hi, lo, src, ", &rem)) {
1388: SET_VFLG (1);
1389: SET_NFLG (1);
1390: SET_CFLG (0);
1391: } else {
1392: SET_VFLG (0);
1393: SET_CFLG (0);
1394: SET_ZFLG (((uae_s32)quot) == 0);
1395: SET_NFLG (((uae_s32)quot) < 0);
1396: m68k_dreg(regs, extra & 7) = rem;
1397: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1398: }
1399: }
1400: #endif
1401: }
1402:
1403: STATIC_INLINE void
1404: mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1405: {
1406: uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1407: uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1408: uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1409: uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1410: uae_u32 lo;
1411:
1412: lo = r0 + ((r1 << 16) & 0xffff0000ul);
1413: if (lo < r0) r3++;
1414: r0 = lo;
1415: lo = r0 + ((r2 << 16) & 0xffff0000ul);
1416: if (lo < r0) r3++;
1417: r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1418: *dst_lo = lo;
1419: *dst_hi = r3;
1420: }
1421:
1422: void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1423: {
1424: #if defined(uae_s64)
1425: if (extra & 0x800) {
1426: /* signed variant */
1427: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1428:
1429: a *= (uae_s64)(uae_s32)src;
1430: SET_VFLG (0);
1431: SET_CFLG (0);
1432: SET_ZFLG (a == 0);
1433: SET_NFLG (a < 0);
1434: if (extra & 0x400)
1435: m68k_dreg(regs, extra & 7) = a >> 32;
1436: else if ((a & UVAL64(0xffffffff80000000)) != 0
1437: && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1438: {
1439: SET_VFLG (1);
1440: }
1441: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1442: } else {
1443: /* unsigned */
1444: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1445:
1446: a *= (uae_u64)src;
1447: SET_VFLG (0);
1448: SET_CFLG (0);
1449: SET_ZFLG (a == 0);
1450: SET_NFLG (((uae_s64)a) < 0);
1451: if (extra & 0x400)
1452: m68k_dreg(regs, extra & 7) = a >> 32;
1453: else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1454: SET_VFLG (1);
1455: }
1456: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1457: }
1458: #else
1459: if (extra & 0x800) {
1460: /* signed variant */
1461: uae_s32 src1,src2;
1462: uae_u32 dst_lo,dst_hi;
1463: uae_u32 sign;
1464:
1465: src1 = (uae_s32)src;
1466: src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1467: sign = (src1 ^ src2);
1468: if (src1 < 0) src1 = -src1;
1469: if (src2 < 0) src2 = -src2;
1470: mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1471: if (sign & 0x80000000) {
1472: dst_hi = ~dst_hi;
1473: dst_lo = -dst_lo;
1474: if (dst_lo == 0) dst_hi++;
1475: }
1476: SET_VFLG (0);
1477: SET_CFLG (0);
1478: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1479: SET_NFLG (((uae_s32)dst_hi) < 0);
1480: if (extra & 0x400)
1481: m68k_dreg(regs, extra & 7) = dst_hi;
1482: else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1483: && ((dst_hi & 0xffffffff) != 0xffffffff
1484: || (dst_lo & 0x80000000) != 0x80000000))
1485: {
1486: SET_VFLG (1);
1487: }
1488: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1489: } else {
1490: /* unsigned */
1491: uae_u32 dst_lo,dst_hi;
1492:
1493: mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1494:
1495: SET_VFLG (0);
1496: SET_CFLG (0);
1497: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1498: SET_NFLG (((uae_s32)dst_hi) < 0);
1499: if (extra & 0x400)
1500: m68k_dreg(regs, extra & 7) = dst_hi;
1501: else if (dst_hi != 0) {
1502: SET_VFLG (1);
1503: }
1504: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1505: }
1506: #endif
1507: }
1.1.1.6 root 1508:
1.1 root 1509:
1510: void m68k_reset (void)
1511: {
1512: regs.s = 1;
1513: regs.m = 0;
1514: regs.stopped = 0;
1515: regs.t1 = 0;
1516: regs.t0 = 0;
1517: SET_ZFLG (0);
1518: SET_XFLG (0);
1519: SET_CFLG (0);
1520: SET_VFLG (0);
1521: SET_NFLG (0);
1.1.1.16 root 1522: regs.spcflags &= ( SPCFLAG_MODE_CHANGE | SPCFLAG_DEBUGGER ); /* Clear specialflags except mode-change and debugger */
1.1 root 1523: regs.intmask = 7;
1524: regs.vbr = regs.sfc = regs.dfc = 0;
1525: regs.fpcr = regs.fpsr = regs.fpiar = 0;
1.1.1.7 root 1526:
1527: m68k_areg(regs, 7) = get_long(0);
1528: m68k_setpc(get_long(4));
1529: refill_prefetch (m68k_getpc(), 0);
1.1 root 1530: }
1531:
1.1.1.8 root 1532:
1.1 root 1533: unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1534: {
1.1.1.8 root 1535: #if 0
1.1 root 1536: uaecptr pc = m68k_getpc ();
1.1.1.8 root 1537: #endif
1.1.1.6 root 1538: if ((opcode & 0xF000) == 0xF000) {
1.1.1.16 root 1539: Exception(0xB,0,M68000_EXC_SRC_CPU);
1.1 root 1540: return 4;
1.1.1.6 root 1541: }
1542: if ((opcode & 0xF000) == 0xA000) {
1.1.1.16 root 1543: Exception(0xA,0,M68000_EXC_SRC_CPU);
1.1 root 1544: return 4;
1.1.1.6 root 1545: }
1.1.1.3 root 1546: #if 0
1.1.1.6 root 1547: write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc);
1.1 root 1548: #endif
1.1.1.16 root 1549: Exception (4,0,M68000_EXC_SRC_CPU);
1.1 root 1550: return 4;
1551: }
1552:
1.1.1.8 root 1553:
1.1 root 1554: void mmu_op(uae_u32 opcode, uae_u16 extra)
1555: {
1556: if ((opcode & 0xFE0) == 0x0500) {
1557: /* PFLUSH */
1558: mmusr = 0;
1559: write_log ("PFLUSH\n");
1560: } else if ((opcode & 0x0FD8) == 0x548) {
1561: /* PTEST */
1562: write_log ("PTEST\n");
1563: } else
1564: op_illg (opcode);
1565: }
1566:
1567:
1568: static uaecptr last_trace_ad = 0;
1569:
1570: static void do_trace (void)
1571: {
1.1.1.12 root 1572: if (regs.t0 && currprefs.cpu_level >= 2) {
1.1 root 1573: uae_u16 opcode;
1574: /* should also include TRAP, CHK, SR modification FPcc */
1575: /* probably never used so why bother */
1576: /* We can afford this to be inefficient... */
1577: m68k_setpc (m68k_getpc ());
1578: fill_prefetch_0 ();
1579: opcode = get_word (regs.pc);
1.1.1.19 root 1580: if (opcode == 0x4e73 /* RTE */
1.1 root 1581: || opcode == 0x4e74 /* RTD */
1582: || opcode == 0x4e75 /* RTS */
1583: || opcode == 0x4e77 /* RTR */
1584: || opcode == 0x4e76 /* TRAPV */
1585: || (opcode & 0xffc0) == 0x4e80 /* JSR */
1586: || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1587: || (opcode & 0xff00) == 0x6100 /* BSR */
1588: || ((opcode & 0xf000) == 0x6000 /* Bcc */
1589: && cctrue((opcode >> 8) & 0xf))
1590: || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1591: && !cctrue((opcode >> 8) & 0xf)
1592: && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1593: {
1594: last_trace_ad = m68k_getpc ();
1595: unset_special (SPCFLAG_TRACE);
1596: set_special (SPCFLAG_DOTRACE);
1597: }
1598: } else if (regs.t1) {
1599: last_trace_ad = m68k_getpc ();
1600: unset_special (SPCFLAG_TRACE);
1601: set_special (SPCFLAG_DOTRACE);
1602: }
1603: }
1604:
1605:
1.1.1.8 root 1606: /*
1607: * Handle special flags
1608: */
1.1.1.14 root 1609:
1610: static bool do_specialties_interrupt (int Pending)
1611: {
1.1.1.19 root 1612: #if ENABLE_DSP_EMU
1613: /* Check for DSP int first (if enabled) (level 6) */
1614: if (regs.spcflags & SPCFLAG_DSP) {
1615: if (DSP_ProcessIRQ() == true)
1616: return true;
1617: }
1618: #endif
1619:
1620: /* Check for MFP ints (level 6) */
1.1.1.14 root 1621: if (regs.spcflags & SPCFLAG_MFP) {
1.1.1.19 root 1622: if (MFP_ProcessIRQ() == true)
1.1.1.15 root 1623: return true; /* MFP exception was generated, no higher interrupt can happen */
1.1.1.14 root 1624: }
1625:
1626: /* No MFP int, check for VBL/HBL ints (levels 4/2) */
1627: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1628: int intr = intlev ();
1629: /* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */
1630: // unset_special (SPCFLAG_DOINT);
1631: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1632: if (intr != -1 && intr > regs.intmask) {
1633: Interrupt (intr , Pending); /* process the interrupt and add pending jitter if necessary */
1.1.1.15 root 1634: return true;
1.1.1.14 root 1635: }
1636: }
1637:
1.1.1.15 root 1638: return false; /* no interrupt was found */
1.1.1.14 root 1639: }
1640:
1641:
1.1 root 1642: static int do_specialties (void)
1643: {
1.1.1.7 root 1644: if(regs.spcflags & SPCFLAG_BUSERROR) {
1645: /* We can not execute bus errors directly in the memory handler
1646: * functions since the PC should point to the address of the next
1647: * instruction, so we're executing the bus errors here: */
1.1.1.8 root 1648: unset_special(SPCFLAG_BUSERROR);
1.1.1.16 root 1649: Exception(2,0,M68000_EXC_SRC_CPU);
1.1.1.7 root 1650: }
1651:
1.1.1.8 root 1652: if(regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1653: /* Add some extra cycles to simulate a wait state */
1654: unset_special(SPCFLAG_EXTRA_CYCLES);
1.1.1.11 root 1655: M68000_AddCycles(nWaitStateCycles);
1.1.1.12 root 1656: nWaitStateCycles = 0;
1.1.1.8 root 1657: }
1658:
1.1 root 1659: if (regs.spcflags & SPCFLAG_DOTRACE) {
1.1.1.16 root 1660: Exception (9,last_trace_ad,M68000_EXC_SRC_CPU);
1.1 root 1661: }
1.1.1.8 root 1662:
1.1.1.14 root 1663:
1664: /* Handle the STOP instruction */
1665: if ( regs.spcflags & SPCFLAG_STOP ) {
1.1.1.19 root 1666: //fprintf ( stderr , "test stop %d\n" , nCyclesMainCounter );
1.1.1.14 root 1667: /* We first test if there's a pending interrupt that would */
1.1.1.19 root 1668: /* allow to immediately leave the STOP state */
1.1.1.15 root 1669: if ( do_specialties_interrupt(true) ) { /* test if there's an interrupt and add pending jitter */
1.1.1.14 root 1670: regs.stopped = 0;
1671: unset_special (SPCFLAG_STOP);
1.1.1.19 root 1672: //fprintf ( stderr , "exit stop %d\n" , nCyclesMainCounter );
1.1.1.14 root 1673: }
1674:
1675: /* No pending int, we have to wait for the next matching int */
1676: while (regs.spcflags & SPCFLAG_STOP) {
1677:
1678: /* Take care of quit event if needed */
1679: if (regs.spcflags & SPCFLAG_BRK)
1680: return 1;
1681:
1682: M68000_AddCycles(4);
1683:
1684: /* It is possible one or more ints happen at the same time */
1.1.1.19 root 1685: /* We must process them during the same cpu cycle then choose the highest priority one */
1686: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
1.1.1.14 root 1687: CALL_VAR(PendingInterruptFunction);
1.1.1.19 root 1688: if ( MFP_UpdateNeeded == true )
1689: MFP_UpdateIRQ ( 0 );
1690:
1691: /* Check is there's an interrupt to process (could be a delayed MFP interrupt) */
1692: if ( do_specialties_interrupt(false) ) { /* test if there's an interrupt and add non pending jitter */
1693: regs.stopped = 0;
1694: unset_special (SPCFLAG_STOP);
1.1.1.6 root 1695: }
1.1 root 1696: }
1697: }
1.1.1.8 root 1698:
1.1.1.14 root 1699:
1.1 root 1700: if (regs.spcflags & SPCFLAG_TRACE)
1701: do_trace ();
1702:
1.1.1.12 root 1703: // if (regs.spcflags & SPCFLAG_DOINT) {
1704: /* [NP] pending int should be processed now, not after the current instr */
1.1.1.14 root 1705: /* so we check for (SPCFLAG_INT | SPCFLAG_DOINT), not just for SPCFLAG_DOINT */
1.1.1.15 root 1706:
1707: if ( do_specialties_interrupt(false) ) { /* test if there's an interrupt and add non pending jitter */
1.1.1.14 root 1708: regs.stopped = 0; /* [NP] useless ? */
1709: }
1710: if (regs.spcflags & SPCFLAG_INT) {
1711: unset_special (SPCFLAG_INT);
1712: set_special (SPCFLAG_DOINT);
1713: }
1.1.1.8 root 1714:
1.1.1.15 root 1715: if (regs.spcflags & SPCFLAG_DEBUGGER)
1.1.1.16 root 1716: DebugCpu_Check();
1.1.1.15 root 1717:
1.1 root 1718: if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1.1.1.8 root 1719: unset_special(SPCFLAG_MODE_CHANGE);
1.1 root 1720: return 1;
1721: }
1.1.1.8 root 1722:
1.1 root 1723: return 0;
1724: }
1725:
1.1.1.3 root 1726:
1.1 root 1727: /* It's really sad to have two almost identical functions for this, but we
1728: do it all for performance... :( */
1729: static void m68k_run_1 (void)
1730: {
1731: #ifdef DEBUG_PREFETCH
1732: uae_u8 saved_bytes[20];
1.1.1.20! root 1733: uae_u8 *oldpcp;
1.1 root 1734: #endif
1.1.1.8 root 1735:
1736: for (;;) {
1.1 root 1737: int cycles;
1.1.1.20! root 1738: //fprintf (stderr, "ir in %x %x\n",do_get_mem_long(®s.prefetch) , regs.prefetch_pc);
1.1 root 1739: uae_u32 opcode = get_iword_prefetch (0);
1.1.1.8 root 1740:
1.1 root 1741: #ifdef DEBUG_PREFETCH
1.1.1.20! root 1742: // if (get_ilong (0) != do_get_mem_long (®s.prefetch)) {
! 1743: // fprintf (stderr, "Prefetch differs from memory.\n");
! 1744: // debugging = 1;
! 1745: // return;
! 1746: // }
1.1 root 1747: oldpcp = regs.pc_p;
1748: memcpy (saved_bytes, regs.pc_p, 20);
1749: #endif
1750:
1751: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.15 root 1752: if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
1753: {
1754: int FrameCycles, HblCounterVideo, LineCycles;
1755:
1756: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
1757:
1758: LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
1.1.1.19 root 1759: Disasm(stderr, m68k_getpc (), NULL, 1);
1.1.1.15 root 1760: }
1.1 root 1761:
1762: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1763: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1764: #if COUNT_INSTRS == 2
1765: if (table68k[opcode].handler != -1)
1766: instrcount[table68k[opcode].handler]++;
1767: #elif COUNT_INSTRS == 1
1768: instrcount[opcode]++;
1769: #endif
1.1.1.2 root 1770:
1.1.1.12 root 1771: /* In case of a Bus Error, we need the PC of the instruction that caused */
1772: /* the error to build the exception stack frame */
1773: BusErrorPC = m68k_getpc();
1774:
1.1.1.18 root 1775: if (bDspEnabled)
1776: Cycles_SetCounter(CYCLES_COUNTER_CPU, 0); /* to measure the total number of cycles spent in the cpu */
1777:
1.1.1.20! root 1778: /* Uncomment following lines to call capslib's debugger after each instruction */
! 1779: //if ( CAPSGetDebugRequest() )
! 1780: // DebugUI(REASON_CPU_BREAKPOINT);
! 1781:
1.1.1.6 root 1782: cycles = (*cpufunctbl[opcode])(opcode);
1.1.1.20! root 1783: //fprintf (stderr, "ir out %x %x\n",do_get_mem_long(®s.prefetch) , regs.prefetch_pc);
1.1.1.6 root 1784:
1.1 root 1785: #ifdef DEBUG_PREFETCH
1786: if (memcmp (saved_bytes, oldpcp, 20) != 0) {
1.1.1.12 root 1787: fprintf (stderr, "Self-modifying code detected %x.\n" , m68k_getpc() );
1.1.1.20! root 1788: // set_special (SPCFLAG_BRK);
! 1789: // debugging = 1;
1.1 root 1790: }
1791: #endif
1.1.1.2 root 1792:
1.1.1.12 root 1793: M68000_AddCyclesWithPairing(cycles);
1.1.1.13 root 1794: if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1795: /* Add some extra cycles to simulate a wait state */
1796: unset_special(SPCFLAG_EXTRA_CYCLES);
1797: M68000_AddCycles(nWaitStateCycles);
1798: nWaitStateCycles = 0;
1799: }
1800:
1.1.1.14 root 1801: /* We can have several interrupts at the same time before the next CPU instruction */
1802: /* We must check for pending interrupt and call do_specialties_interrupt() only */
1803: /* if the cpu is not in the STOP state. Else, the int could be acknowledged now */
1804: /* and prevent exiting the STOP state when calling do_specialties() after. */
1805: /* For performance, we first test PendingInterruptCount, then regs.spcflags */
1.1.1.19 root 1806: if ( PendingInterruptCount <= 0 )
1807: {
1808: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) && ( ( regs.spcflags & SPCFLAG_STOP ) == 0 ) )
1809: CALL_VAR ( PendingInterruptFunction ); /* call the interrupt's handler */
1810: if ( MFP_UpdateNeeded == true )
1811: MFP_UpdateIRQ ( 0 ); /* update MFP's state if some internal timers related to MFP expired */
1812: }
1.1.1.14 root 1813:
1814: if (regs.spcflags) {
1815: if (do_specialties ())
1816: return;
1817: }
1818:
1.1.1.15 root 1819: /* Run DSP 56k code if necessary */
1820: if (bDspEnabled) {
1.1.1.18 root 1821: DSP_Run( Cycles_GetCounter(CYCLES_COUNTER_CPU) * 2);
1.1.1.15 root 1822: }
1.1 root 1823: }
1824: }
1825:
1826:
1827: /* Same thing, but don't use prefetch to get opcode. */
1828: static void m68k_run_2 (void)
1829: {
1.1.1.8 root 1830: for (;;) {
1.1 root 1831: int cycles;
1832: uae_u32 opcode = get_iword (0);
1833:
1834: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.15 root 1835: if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
1836: {
1837: int FrameCycles, HblCounterVideo, LineCycles;
1838:
1839: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
1840:
1841: LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
1.1.1.19 root 1842: Disasm(stderr, m68k_getpc (), NULL, 1);
1.1.1.15 root 1843: }
1.1.1.12 root 1844:
1.1 root 1845: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1846: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1847: #if COUNT_INSTRS == 2
1848: if (table68k[opcode].handler != -1)
1849: instrcount[table68k[opcode].handler]++;
1850: #elif COUNT_INSTRS == 1
1851: instrcount[opcode]++;
1852: #endif
1.1.1.2 root 1853:
1.1.1.17 root 1854: /* In case of a Bus Error, we need the PC of the instruction that caused */
1855: /* the error to build the exception stack frame */
1856: BusErrorPC = m68k_getpc();
1857:
1.1.1.6 root 1858: cycles = (*cpufunctbl[opcode])(opcode);
1859:
1.1.1.16 root 1860: if (bDspEnabled)
1861: Cycles_SetCounter(CYCLES_COUNTER_CPU, 0); /* to measure the total number of cycles spent in the cpu */
1862:
1.1.1.8 root 1863: M68000_AddCycles(cycles);
1.1.1.13 root 1864: if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1865: /* Add some extra cycles to simulate a wait state */
1866: unset_special(SPCFLAG_EXTRA_CYCLES);
1867: M68000_AddCycles(nWaitStateCycles);
1868: nWaitStateCycles = 0;
1869: }
1870:
1.1.1.19 root 1871: if ( PendingInterruptCount <= 0 )
1872: {
1873: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
1874: CALL_VAR(PendingInterruptFunction);
1875: if ( MFP_UpdateNeeded == true )
1876: MFP_UpdateIRQ ( 0 );
1877: }
1.1.1.8 root 1878:
1.1 root 1879: if (regs.spcflags) {
1880: if (do_specialties ())
1881: return;
1882: }
1.1.1.15 root 1883:
1884: /* Run DSP 56k code if necessary */
1885: if (bDspEnabled) {
1.1.1.16 root 1886: DSP_Run( Cycles_GetCounter(CYCLES_COUNTER_CPU) );
1.1.1.15 root 1887: }
1.1 root 1888: }
1889: }
1890:
1891:
1892: void m68k_go (int may_quit)
1893: {
1.1.1.8 root 1894: static int in_m68k_go = 0;
1895:
1.1 root 1896: if (in_m68k_go || !may_quit) {
1897: write_log ("Bug! m68k_go is not reentrant.\n");
1898: abort ();
1899: }
1900:
1901: in_m68k_go++;
1.1.1.8 root 1902: while (!(regs.spcflags & SPCFLAG_BRK)) {
1.1.1.12 root 1903: if(currprefs.cpu_compatible)
1.1.1.2 root 1904: m68k_run_1();
1905: else
1906: m68k_run_2();
1.1 root 1907: }
1.1.1.8 root 1908: unset_special(SPCFLAG_BRK);
1.1 root 1909: in_m68k_go--;
1910: }
1911:
1.1.1.8 root 1912:
1913: /*
1.1 root 1914: static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1915: {
1916: uae_u32 opcode, val;
1917: struct instr *dp;
1918:
1919: opcode = get_iword_1(0);
1920: last_op_for_exception_3 = opcode;
1921: m68kpc_offset = 2;
1922:
1.1.1.6 root 1923: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1924: opcode = 0x4AFC;
1925: }
1926: dp = table68k + opcode;
1927:
1928: if (dp->suse) {
1929: if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) {
1.1.1.16 root 1930: Exception (3, 0,M68000_EXC_SRC_CPU);
1.1 root 1931: return;
1932: }
1933: }
1934: if (dp->duse) {
1935: if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) {
1.1.1.16 root 1936: Exception (3, 0,M68000_EXC_SRC_CPU);
1.1 root 1937: return;
1938: }
1939: }
1940: }
1.1.1.8 root 1941: */
1942:
1.1 root 1943:
1944: void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1945: {
1.1.1.11 root 1946: static const char * const ccnames[] =
1.1.1.8 root 1947: { "T ","F ","HI","LS","CC","CS","NE","EQ",
1948: "VC","VS","PL","MI","GE","LT","GT","LE" };
1949:
1.1 root 1950: uaecptr newpc = 0;
1951: m68kpc_offset = addr - m68k_getpc ();
1952: while (cnt-- > 0) {
1953: char instrname[20],*ccpt;
1954: int opwords;
1955: uae_u32 opcode;
1.1.1.11 root 1956: const struct mnemolookup *lookup;
1.1 root 1957: struct instr *dp;
1958: fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset);
1959: for (opwords = 0; opwords < 5; opwords++){
1960: fprintf (f, "%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1961: }
1962: opcode = get_iword_1 (m68kpc_offset);
1963: m68kpc_offset += 2;
1.1.1.6 root 1964: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1965: opcode = 0x4AFC;
1966: }
1967: dp = table68k + opcode;
1968: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1969: ;
1970:
1971: strcpy (instrname, lookup->name);
1972: ccpt = strstr (instrname, "cc");
1973: if (ccpt != 0) {
1974: strncpy (ccpt, ccnames[dp->cc], 2);
1975: }
1976: fprintf (f, "%s", instrname);
1977: switch (dp->size){
1978: case sz_byte: fprintf (f, ".B "); break;
1979: case sz_word: fprintf (f, ".W "); break;
1980: case sz_long: fprintf (f, ".L "); break;
1981: default: fprintf (f, " "); break;
1982: }
1983:
1984: if (dp->suse) {
1985: newpc = m68k_getpc () + m68kpc_offset;
1986: newpc += ShowEA (f, dp->sreg, dp->smode, dp->size, 0);
1987: }
1988: if (dp->suse && dp->duse)
1989: fprintf (f, ",");
1990: if (dp->duse) {
1991: newpc = m68k_getpc () + m68kpc_offset;
1992: newpc += ShowEA (f, dp->dreg, dp->dmode, dp->size, 0);
1993: }
1994: if (ccpt != 0) {
1995: if (cctrue(dp->cc))
1.1.1.5 root 1996: fprintf (f, " == %08lx (TRUE)", (long)newpc);
1.1 root 1997: else
1.1.1.5 root 1998: fprintf (f, " == %08lx (FALSE)", (long)newpc);
1.1 root 1999: } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1.1.1.5 root 2000: fprintf (f, " == %08lx", (long)newpc);
1.1 root 2001: fprintf (f, "\n");
2002: }
2003: if (nextpc)
2004: *nextpc = m68k_getpc () + m68kpc_offset;
2005: }
2006:
2007: void m68k_dumpstate (FILE *f, uaecptr *nextpc)
2008: {
2009: int i;
2010: for (i = 0; i < 8; i++){
1.1.1.5 root 2011: fprintf (f, "D%d: %08lx ", i, (long)m68k_dreg(regs, i));
1.1 root 2012: if ((i & 3) == 3) fprintf (f, "\n");
2013: }
2014: for (i = 0; i < 8; i++){
1.1.1.5 root 2015: fprintf (f, "A%d: %08lx ", i, (long)m68k_areg(regs, i));
1.1 root 2016: if ((i & 3) == 3) fprintf (f, "\n");
2017: }
2018: if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
2019: if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
2020: if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
2021: fprintf (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1.1.1.5 root 2022: (long)regs.usp,(long)regs.isp,(long)regs.msp,(long)regs.vbr);
1.1 root 2023: fprintf (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
2024: regs.t1, regs.t0, regs.s, regs.m,
2025: GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
2026: for (i = 0; i < 8; i++){
2027: fprintf (f, "FP%d: %g ", i, regs.fp[i]);
2028: if ((i & 3) == 3) fprintf (f, "\n");
2029: }
2030: fprintf (f, "N=%d Z=%d I=%d NAN=%d\n",
2031: (regs.fpsr & 0x8000000) != 0,
2032: (regs.fpsr & 0x4000000) != 0,
2033: (regs.fpsr & 0x2000000) != 0,
2034: (regs.fpsr & 0x1000000) != 0);
1.1.1.12 root 2035: if (currprefs.cpu_compatible)
1.1 root 2036: fprintf (f, "prefetch %08lx\n", (unsigned long)do_get_mem_long(®s.prefetch));
2037:
2038: m68k_disasm (f, m68k_getpc (), nextpc, 1);
2039: if (nextpc)
1.1.1.5 root 2040: fprintf (f, "next PC: %08lx\n", (long)*nextpc);
1.1 root 2041: }
1.1.1.12 root 2042:
2043:
2044: /*
2045:
2046: The routines below take dividend and divisor as parameters.
2047: They return 0 if division by zero, or exact number of cycles otherwise.
2048:
2049: The number of cycles returned assumes a register operand.
2050: Effective address time must be added if memory operand.
2051:
2052: For 68000 only (not 68010, 68012, 68020, etc).
2053: Probably valid for 68008 after adding the extra prefetch cycle.
2054:
2055:
2056: Best and worst cases are for register operand:
2057: (Note the difference with the documented range.)
2058:
2059:
2060: DIVU:
2061:
2062: Overflow (always): 10 cycles.
2063: Worst case: 136 cycles.
2064: Best case: 76 cycles.
2065:
2066:
2067: DIVS:
2068:
2069: Absolute overflow: 16-18 cycles.
2070: Signed overflow is not detected prematurely.
2071:
2072: Worst case: 156 cycles.
2073: Best case without signed overflow: 122 cycles.
2074: Best case with signed overflow: 120 cycles
2075:
2076:
2077: */
2078:
2079:
2080: //
2081: // DIVU
2082: // Unsigned division
2083: //
2084:
2085: STATIC_INLINE int getDivu68kCycles_2 (uae_u32 dividend, uae_u16 divisor)
2086: {
2087: int mcycles;
2088: uae_u32 hdivisor;
2089: int i;
2090:
2091: if (divisor == 0)
2092: return 0;
2093:
2094: // Overflow
2095: if ((dividend >> 16) >= divisor)
2096: return (mcycles = 5) * 2;
2097:
2098: mcycles = 38;
2099: hdivisor = divisor << 16;
2100:
2101: for (i = 0; i < 15; i++) {
2102: uae_u32 temp;
2103: temp = dividend;
2104:
2105: dividend <<= 1;
2106:
2107: // If carry from shift
2108: if ((uae_s32)temp < 0)
2109: dividend -= hdivisor;
2110: else {
2111: mcycles += 2;
2112: if (dividend >= hdivisor) {
2113: dividend -= hdivisor;
2114: mcycles--;
2115: }
2116: }
2117: }
2118: return mcycles * 2;
2119: }
2120: int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor)
2121: {
2122: int v = getDivu68kCycles_2 (dividend, divisor) - 4;
2123: // write_log ("U%d ", v);
2124: return v;
2125: }
2126:
2127: //
2128: // DIVS
2129: // Signed division
2130: //
2131:
2132: STATIC_INLINE int getDivs68kCycles_2 (uae_s32 dividend, uae_s16 divisor)
2133: {
2134: int mcycles;
2135: uae_u32 aquot;
2136: int i;
2137:
2138: if (divisor == 0)
2139: return 0;
2140:
2141: mcycles = 6;
2142:
2143: if (dividend < 0)
2144: mcycles++;
2145:
2146: // Check for absolute overflow
2147: if (((uae_u32)abs (dividend) >> 16) >= (uae_u16)abs (divisor))
2148: return (mcycles + 2) * 2;
2149:
2150: // Absolute quotient
2151: aquot = (uae_u32) abs (dividend) / (uae_u16)abs (divisor);
2152:
2153: mcycles += 55;
2154:
2155: if (divisor >= 0) {
2156: if (dividend >= 0)
2157: mcycles--;
2158: else
2159: mcycles++;
2160: }
2161:
2162: // Count 15 msbits in absolute of quotient
2163:
2164: for (i = 0; i < 15; i++) {
2165: if ((uae_s16)aquot >= 0)
2166: mcycles++;
2167: aquot <<= 1;
2168: }
2169:
2170: return mcycles * 2;
2171: }
2172: int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor)
2173: {
2174: int v = getDivs68kCycles_2 (dividend, divisor) - 4;
2175: // write_log ("S%d ", v);
2176: return v;
2177: }
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