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1.1 root 1: /*
1.1.1.2 root 2: * UAE - The Un*x Amiga Emulator - CPU core
1.1 root 3: *
4: * MC68000 emulation
5: *
6: * (c) 1995 Bernd Schmidt
1.1.1.2 root 7: *
8: * Adaptation to Hatari by Thomas Huth
9: *
1.1.1.19 root 10: * This file is distributed under the GNU General Public License, version 2
11: * or at your option any later version. Read the file gpl.txt for details.
1.1 root 12: */
1.1.1.12 root 13:
14:
15: /* 2007/11/12 [NP] Add HATARI_TRACE_CPU_DISASM. */
16: /* 2007/11/15 [NP] In MakeFromSR, writes to m and t0 should be ignored and set to 0 if cpu < 68020 */
17: /* 2007/11/26 [NP] We set BusErrorPC in m68k_run_1 instead of M68000_BusError, else the BusErrorPC */
18: /* will not point to the opcode that generated the bus error. */
19: /* Huge debug/work on Exceptions 2/3 stack frames, result is more accurate and */
20: /* allow to pass the very tricky Transbeauce 2 Demo's protection. */
21: /* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */
22: /* Cwik, [email protected]). */
23: /* 2007/12/06 [NP] The PC stored in the stack frame for the bus error is complex to emulate, */
24: /* because it doesn't necessarily point to the next instruction after the one that */
25: /* triggered the bus error. In the case of the Transbeauce 2 Demo, after */
26: /* 'move.l $0.w,$24.w', PC is incremented of 4 bytes, not 6, and stored in the */
27: /* stack. Special case to decrement PC of 2 bytes if opcode is '21f8'. */
28: /* This should be fixed with a real model. */
29: /* 2007/12/07 [NP] If Trace is enabled and a group 2 exception occurs (such as CHK), the trace */
30: /* handler should be called after the group 2's handler. If a bus error, address */
31: /* error or illegal occurs while Trace is enabled, the trace handler should not be */
32: /* called after this instruction (Transbeauce 2 Demo, Phaleon Demo). */
33: /* This means that if a CHK is executed while trace bit was set, we must set PC */
34: /* to CHK handler, turn trace off in the internal SR, but we must still call the */
35: /* trace handler one last time with the PC set to the CHK's handler (even if */
36: /* trace mode is internally turned off while processing an exception). Once trace */
37: /* handler is finished (RTE), we return to the CHK's handler. */
38: /* This is true for DIV BY 0, CHK, TRAPV and TRAP. */
39: /* Backport exception_trace() from WinUAE to handle this behaviour (used in */
40: /* Transbeauce 2 demo). */
41: /* 2007/12/09 [NP] 'dc.w $a' should not be used to call 'OpCode_SysInit' but should give an illegal*/
42: /* instruction (Transbeauce 2 demo). */
43: /* Instead of always replacing the illegal instructions $8, $a and $c by the */
44: /* 3 functions required for HD emulation, we now do it in cart.c only if the */
45: /* built-in cartridge image is loaded. */
46: /* YEAH! Hatari is now the first emulator to pass the Transbeauce 2 protection :) */
47: /* 2007/12/18 [NP] More precise timings for HBL, VBL and MFP interrupts. On ST, these interrupts */
48: /* are taking 56 cycles instead of the 44 cycles in the 68000's documentation. */
1.1.1.19 root 49: /* 2007/12/24 [NP] If an interrupt (HBL, VBL) is pending after instruction 'n' was processed, the */
1.1.1.12 root 50: /* exception should be called before instr. 'n+1' is processed, not after (else the*/
51: /* interrupt's handler is delayed by one 68000's instruction, which could break */
52: /* some demos with too strict timings) (ACF's Demo Main Menu). */
53: /* We call the interrupt if ( SPCFLAG_INT | SPCFLAG_DOINT ) is set, not only if */
54: /* SPCFLAG_DOINT is set (as it was already the case when handling 'STOP'). */
55: /* 2007/12/25 [NP] FIXME When handling exceptions' cycles, using nr >= 64 to determine if this is */
56: /* an MFP exception could be wrong if the MFP VR was set to another value than the */
57: /* default $40 (this could be a problem with programs requiring a precise cycles */
58: /* calculation while changing VR, but no such programs were encountered so far). */
1.1.1.13 root 59: /* -> FIXED, see 2008/10/05 */
60: /* 2008/04/17 [NP] In m68k_run_1/m68k_run_2, add the wait state cycles before testing if content */
61: /* of PendingInterruptCount is <= 0 (else the int could happen a few cycles earlier*/
62: /* than expected in some rare cases (reading $fffa21 in BIG Demo Screen 1)). */
63: /* 2008/09/14 [NP] Add the value of the new PC in the exception's log. */
64: /* 2008/09/14 [NP] Correct cycles for TRAP are 34 not 38 (4 more cycles were counted because cpuemu*/
65: /* returns 4 and Exception() adds 34) (Phaleon / Illusion Demo by Next). */
66: /* FIXME : Others exception cycles may be wrong too. */
67: /* 2008/10/05 [NP] Add a parameter 'ExceptionSource' to Exception(). This allows to know the source*/
68: /* of the exception (video, mfp, cpu) and properly handle MFP interrupts. Since */
69: /* it's possible to change the vector base in $fffa17, MFP int vectors can overlap */
70: /* the 'normal' 68000 ones and the exception number is not enough to decide. */
71: /* We need ExceptionSource to remove the ambiguity. */
72: /* Fix High Fidelity Dreams by Aura which sets MFP vector base to $c0 instead of */
73: /* $100. In that case, timer B int becomes exception nr 56 and conflicts with the */
74: /* 'MMU config error' exception, which takes 4 cycles instead of 56 cycles for MFP.*/
75: /* 2008/11/18 [NP] In 'do_specialties()', when the cpu is in the STOP state, we must test all */
76: /* possible int handlers while PendingInterruptCount <= 0 without increasing the */
77: /* cpu cycle counter. In the case where both an MFP int and an HBL occur at the */
1.1.1.14 root 78: /* same time for example, the HBL was delayed by 4 cycles if no MFP exception */
1.1.1.13 root 79: /* was triggered, which was wrong (this happened mainly with the TOS timer D that */
80: /* expires very often). Such precision is required for very recent hardscroll */
81: /* techniques that use 'stop' to stay in sync with the video shifter. */
1.1.1.14 root 82: /* 2008/11/23 [NP] In 'do_specialties()', when in STOP state, we must first test for a pending */
1.1.1.19 root 83: /* interrupt that would exit the STOP state immediately, without doing a 'while' */
1.1.1.14 root 84: /* loop until 'SPCFLAG_INT' or 'SPCFLAG_DOINT' are set. */
85: /* 2008/11/29 [NP] Call 'InterruptAddJitter()' when a video interrupt happens to precisely emulate */
86: /* the jitter happening on the Atari (see video.c for the jitter patterns). */
87: /* FIXME : Pattern is not always correct when handling pending interrupt in STOP */
88: /* state, but this should be harmless as no program has been found using this. */
89: /* 2008/12/05 [NP] On Atari it takes 56 cycles to process an interrupt. During that time, a higher */
90: /* level interrupt could happen and we must execute it before the previous int */
91: /* (see m68k_run_1()). */
92: /* This is the case for the VBL which can interrupt the last HBL of a screen */
93: /* (end of line 312) at various point (from 0 to 8 cycles). */
94: /* This fixes the fullscreen tunnel in Suretrip 49% by Checkpoint, which uses a */
95: /* really buggy vbl/hbl combination, even on a real ST. Also fixes sample sound */
96: /* in Swedish New Year's TCB screen. */
97: /* 2008/12/11 [NP] Extract interrupt handling from do_specialties() in do_specialties_interrupt() */
98: /* and factorize some code. In m68k_run_1 when testing for multiple interrupts at */
99: /* the same time, call do_specialties_interrupt() to check only the special flags */
100: /* related to interrupts (MFP and video) (else, this caused problem when the TRACE */
101: /* flag was set). */
102: /* 2008/12/14 [NP] In m68k_run_1(), we should check for simultaneous ints only if the cpu is not */
103: /* in the STOP state after the last instruction was executed. Else, the call to */
104: /* do_specialties_interrupt() could acknowledge the interrupt and we would never */
105: /* exit the STOP state in do_specialties() just after (the problem can happen if */
106: /* the TOS timer D expires just at the same time as the STOP instruction). */
107: /* Fix regression since 2008/12/11 in the hidden screen from ULM in Oh Crickey... */
108: /* 2008/12/20 [NP] In m68k_run_1(), when checking interrupts and STOP mode, we should test */
109: /* PendingInterruptCount before regs.spcflags to have a faster evaluation of the */
110: /* 'while' condition (PendingInterruptCount <= 0 is true less often than STOP==0) */
1.1.1.17 root 111: /* 2011/04/29 [NP] In Exception(), check the new PC is not on odd address ; raise an address error */
112: /* exception if it's the case. */
1.1.1.20 root 113: /* 2012/09/01 [NP] Add a special case to correct the stacked PC when a bus error happens during */
114: /* a movem (fix the game Blood Money). */
115: /* 2013/03/16 [NP] In refill_prefetch(), reload only one new word in regs.prefetch if low word is */
116: /* still valid : low word goes to high word and we reload only low word */
117: /* (fix EOR/ADD self modified code in the protection for the game Damocles). */
1.1.1.19 root 118: /* 2013/04/11 [NP] In Exception(), call MFP_ProcessIACK after 12 cycles to update the MFP's vector */
119: /* number used for the exception (see mfp.c). */
120: /* 2013/05/03 [NP] In Exception(), handle IACK for HBL and VBL interrupts too, allowing pending bit*/
121: /* to be set twice during an active video interrupt (correct fix for Super Monaco */
122: /* GP, Super Hang On, Monster Business, European Demo's Intro, BBC Menu 52). */
1.1.1.20 root 123: /* 2014/02/22 [NP] In Exception(), call valid_address() before reading the opcode at BusErrorPC, */
124: /* else this will cause an unwanted "double bus error" ("Union Demo" loader). */
125: /* 2014/02/22 [NP] In refill_prefetch(), use get_word() instead of do_get_mem_word() to generate */
126: /* a bus error when trying to read from an invalid region. */
127: /* 2014/03/18 [NP] In Exception(), add a specific case to restore the dest part of a "move" after */
128: /* it was overwritten during a bus error (fix the game Dragon Flight). */
129: /* 2014/04/06 [NP] In Exception(), add a special case for last_addr_for_exception_3 stored in the */
130: /* stack after a bus error (fix the game Batman The Movie). */
1.1.1.21! root 131: /* 2014/09/07 [NP] In m68k_run_1(), if get_iword_prefetch() triggers a bus error, we must call the */
! 132: /* bus error immediately and fetch the correct opcode for the bus error handler */
! 133: /* (fix Blood Money on Superior 65, PC=4e664e66 after RTS). */
! 134: /* 2014/09/07 [NP] For address error, store if the access was in cpu space or data space and fix */
! 135: /* the exception stack frame accordingly (fix Blood Money on Superior 65, */
! 136: /* PC=4e664e66 after RTS) */
! 137: /* 2015/02/11 [NP] Replace BusErrorPC by regs.instruction_pc, to get similar code to WinUAE's cpu */
! 138:
1.1.1.12 root 139:
1.1.1.15 root 140: const char NewCpu_fileid[] = "Hatari newcpu.c : " __DATE__ " " __TIME__;
1.1 root 141:
142: #include "sysdeps.h"
143: #include "hatari-glue.h"
144: #include "maccess.h"
145: #include "memory.h"
146: #include "newcpu.h"
1.1.1.16 root 147: #include "main.h"
148: #include "m68000.h"
1.1.1.21! root 149: #include "reset.h"
1.1.1.16 root 150: #include "cycInt.h"
151: #include "mfp.h"
152: #include "tos.h"
153: #include "vdi.h"
154: #include "cart.h"
155: #include "dialog.h"
156: #include "bios.h"
157: #include "xbios.h"
1.1.1.17 root 158: #include "screen.h"
1.1.1.16 root 159: #include "video.h"
160: #include "options.h"
161: #include "dsp.h"
162: #include "log.h"
163: #include "debugui.h"
164: #include "debugcpu.h"
1.1.1.17 root 165: #include "68kDisass.h"
1.1 root 166:
1.1.1.20 root 167: #ifdef HAVE_CAPSIMAGE
168: #if CAPSIMAGE_VERSION == 5
169: #include <caps5/CapsLibAll.h>
170: #endif
171: #endif
172:
1.1.1.12 root 173: //#define DEBUG_PREFETCH
1.1 root 174:
175: struct flag_struct regflags;
176:
177: /* Opcode of faulting instruction */
178: uae_u16 last_op_for_exception_3;
179: /* PC at fault time */
180: uaecptr last_addr_for_exception_3;
181: /* Address that generated the exception */
182: uaecptr last_fault_for_exception_3;
1.1.1.21! root 183: /* read (0) or write (1) access */
! 184: int last_writeaccess_for_exception_3;
! 185: /* instruction (1) or data (0) access */
! 186: int last_instructionaccess_for_exception_3;
1.1 root 187:
1.1.1.11 root 188: const int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
189: const int imm8_table[] = { 8,1,2,3,4,5,6,7 };
1.1 root 190:
191: int movem_index1[256];
192: int movem_index2[256];
193: int movem_next[256];
194:
195: int fpp_movem_index1[256];
196: int fpp_movem_index2[256];
197: int fpp_movem_next[256];
198:
199: cpuop_func *cpufunctbl[65536];
200:
1.1.1.12 root 201: int OpcodeFamily;
1.1.1.16 root 202: int BusCyclePenalty = 0;
1.1.1.6 root 203:
1.1 root 204: #define COUNT_INSTRS 0
205:
206: #if COUNT_INSTRS
207: static unsigned long int instrcount[65536];
208: static uae_u16 opcodenums[65536];
209:
210: static int compfn (const void *el1, const void *el2)
211: {
212: return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
213: }
214:
215: static char *icountfilename (void)
216: {
217: char *name = getenv ("INSNCOUNT");
218: if (name)
219: return name;
220: return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
221: }
222:
223: void dump_counts (void)
224: {
225: FILE *f = fopen (icountfilename (), "w");
226: unsigned long int total;
227: int i;
228:
229: write_log ("Writing instruction count file...\n");
230: for (i = 0; i < 65536; i++) {
231: opcodenums[i] = i;
232: total += instrcount[i];
233: }
234: qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
235:
236: fprintf (f, "Total: %lu\n", total);
237: for (i=0; i < 65536; i++) {
238: unsigned long int cnt = instrcount[opcodenums[i]];
239: struct instr *dp;
240: struct mnemolookup *lookup;
241: if (!cnt)
242: break;
243: dp = table68k + opcodenums[i];
244: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
245: ;
246: fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
247: }
248: fclose (f);
249: }
250: #else
251: void dump_counts (void)
252: {
253: }
254: #endif
255:
1.1.1.21! root 256: static void cpu_halt ( void )
! 257: {
! 258: Dialog_HaltDlg();
! 259: }
! 260:
1.1 root 261:
262: static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM;
263:
264: static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
265: {
1.1.1.6 root 266: op_illg (opcode);
1.1 root 267: return 4;
268: }
269:
1.1.1.4 root 270:
271: void build_cpufunctbl(void)
1.1 root 272: {
273: int i;
274: unsigned long opcode;
1.1.1.12 root 275: const struct cputbl *tbl = (currprefs.cpu_level == 4 ? op_smalltbl_0_ff
276: : currprefs.cpu_level == 3 ? op_smalltbl_1_ff
277: : currprefs.cpu_level == 2 ? op_smalltbl_2_ff
278: : currprefs.cpu_level == 1 ? op_smalltbl_3_ff
279: : ! currprefs.cpu_compatible ? op_smalltbl_4_ff
1.1.1.11 root 280: : op_smalltbl_5_ff);
1.1 root 281:
1.1.1.10 root 282: Log_Printf(LOG_DEBUG, "Building CPU function table (%d %d %d).\n",
1.1.1.12 root 283: currprefs.cpu_level, currprefs.cpu_compatible, currprefs.address_space_24);
1.1 root 284:
285: for (opcode = 0; opcode < 65536; opcode++)
1.1.1.6 root 286: cpufunctbl[opcode] = op_illg_1;
1.1 root 287: for (i = 0; tbl[i].handler != NULL; i++) {
288: if (! tbl[i].specific)
1.1.1.6 root 289: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 290: }
291: for (opcode = 0; opcode < 65536; opcode++) {
292: cpuop_func *f;
293:
1.1.1.12 root 294: if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > currprefs.cpu_level)
1.1 root 295: continue;
296:
297: if (table68k[opcode].handler != -1) {
1.1.1.6 root 298: f = cpufunctbl[table68k[opcode].handler];
1.1 root 299: if (f == op_illg_1)
300: abort();
1.1.1.6 root 301: cpufunctbl[opcode] = f;
1.1 root 302: }
303: }
304: for (i = 0; tbl[i].handler != NULL; i++) {
305: if (tbl[i].specific)
1.1.1.6 root 306: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1 root 307: }
308: }
309:
310:
311:
312: void init_m68k (void)
313: {
314: int i;
315:
316: for (i = 0 ; i < 256 ; i++) {
317: int j;
318: for (j = 0 ; j < 8 ; j++) {
319: if (i & (1 << j)) break;
320: }
321: movem_index1[i] = j;
322: movem_index2[i] = 7-j;
323: movem_next[i] = i & (~(1 << j));
324: }
325: for (i = 0 ; i < 256 ; i++) {
326: int j;
327: for (j = 7 ; j >= 0 ; j--) {
328: if (i & (1 << j)) break;
329: }
330: fpp_movem_index1[i] = 7-j;
331: fpp_movem_index2[i] = j;
332: fpp_movem_next[i] = i & (~(1 << j));
333: }
334: #if COUNT_INSTRS
335: {
336: FILE *f = fopen (icountfilename (), "r");
337: memset (instrcount, 0, sizeof instrcount);
338: if (f) {
339: uae_u32 opcode, count, total;
340: char name[20];
341: write_log ("Reading instruction count file...\n");
342: fscanf (f, "Total: %lu\n", &total);
343: while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
344: instrcount[opcode] = count;
345: }
346: fclose(f);
347: }
348: }
349: #endif
350: write_log ("Building CPU table for configuration: 68");
1.1.1.12 root 351: if (currprefs.address_space_24 && currprefs.cpu_level > 1)
1.1 root 352: write_log ("EC");
1.1.1.12 root 353: switch (currprefs.cpu_level) {
1.1 root 354: case 1:
355: write_log ("010");
356: break;
357: case 2:
358: write_log ("020");
359: break;
360: case 3:
361: write_log ("020/881");
362: break;
363: case 4:
364: /* Who is going to miss the MMU anyway...? :-) */
365: write_log ("040");
366: break;
367: default:
368: write_log ("000");
369: break;
370: }
1.1.1.12 root 371: if (currprefs.cpu_compatible)
1.1 root 372: write_log (" (compatible mode)");
373: write_log ("\n");
1.1.1.7 root 374:
1.1 root 375: read_table68k ();
376: do_merges ();
377:
1.1.1.10 root 378: Log_Printf(LOG_DEBUG, "%d CPU functions\n", nr_cpuop_funcs);
1.1 root 379:
380: build_cpufunctbl ();
381: }
382:
1.1.1.4 root 383:
1.1.1.8 root 384: /* not used ATM:
1.1 root 385: static struct regstruct regs_backup[16];
386: static int backup_pointer = 0;
1.1.1.10 root 387: struct regstruct lastint_regs;
388: int lastint_no;
1.1.1.8 root 389: */
1.1.1.10 root 390: struct regstruct regs;
1.1 root 391: static long int m68kpc_offset;
1.1.1.10 root 392:
1.1 root 393:
394: #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
395: #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
396: #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
397:
398: uae_s32 ShowEA (FILE *f, int reg, amodes mode, wordsizes size, char *buf)
399: {
400: uae_u16 dp;
401: uae_s8 disp8;
402: uae_s16 disp16;
403: int r;
404: uae_u32 dispreg;
405: uaecptr addr;
406: uae_s32 offset = 0;
407: char buffer[80];
408:
409: switch (mode){
410: case Dreg:
411: sprintf (buffer,"D%d", reg);
412: break;
413: case Areg:
414: sprintf (buffer,"A%d", reg);
415: break;
416: case Aind:
417: sprintf (buffer,"(A%d)", reg);
418: break;
419: case Aipi:
420: sprintf (buffer,"(A%d)+", reg);
421: break;
422: case Apdi:
423: sprintf (buffer,"-(A%d)", reg);
424: break;
425: case Ad16:
426: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
427: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
428: sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
429: (unsigned long)addr);
430: break;
431: case Ad8r:
432: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
433: disp8 = dp & 0xFF;
434: r = (dp & 0x7000) >> 12;
435: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
436: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
437: dispreg <<= (dp >> 9) & 3;
438:
439: if (dp & 0x100) {
440: uae_s32 outer = 0, disp = 0;
441: uae_s32 base = m68k_areg(regs,reg);
442: char name[10];
443: sprintf (name,"A%d, ",reg);
444: if (dp & 0x80) { base = 0; name[0] = 0; }
445: if (dp & 0x40) dispreg = 0;
446: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
447: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
448: base += disp;
449:
450: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
451: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
452:
453: if (!(dp & 4)) base += dispreg;
454: if (dp & 3) base = get_long (base);
455: if (dp & 4) base += dispreg;
456:
457: addr = base + outer;
458: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
459: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
460: 1 << ((dp >> 9) & 3),
1.1.1.5 root 461: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 462: } else {
463: addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
464: sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
465: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
466: 1 << ((dp >> 9) & 3), disp8,
467: (unsigned long)addr);
468: }
469: break;
470: case PC16:
471: addr = m68k_getpc () + m68kpc_offset;
472: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
473: addr += (uae_s16)disp16;
474: sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
475: break;
476: case PC8r:
477: addr = m68k_getpc () + m68kpc_offset;
478: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
479: disp8 = dp & 0xFF;
480: r = (dp & 0x7000) >> 12;
481: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
482: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
483: dispreg <<= (dp >> 9) & 3;
484:
485: if (dp & 0x100) {
486: uae_s32 outer = 0,disp = 0;
487: uae_s32 base = addr;
488: char name[10];
489: sprintf (name,"PC, ");
490: if (dp & 0x80) { base = 0; name[0] = 0; }
491: if (dp & 0x40) dispreg = 0;
492: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
493: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
494: base += disp;
495:
496: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
497: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
498:
499: if (!(dp & 4)) base += dispreg;
500: if (dp & 3) base = get_long (base);
501: if (dp & 4) base += dispreg;
502:
503: addr = base + outer;
504: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
505: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
506: 1 << ((dp >> 9) & 3),
1.1.1.5 root 507: (long)disp, (long)outer, (unsigned long)addr);
1.1 root 508: } else {
509: addr += (uae_s32)((uae_s8)disp8) + dispreg;
510: sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
511: (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
512: disp8, (unsigned long)addr);
513: }
514: break;
515: case absw:
516: sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
517: m68kpc_offset += 2;
518: break;
519: case absl:
520: sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
521: m68kpc_offset += 4;
522: break;
523: case imm:
524: switch (size){
525: case sz_byte:
526: sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
527: m68kpc_offset += 2;
528: break;
529: case sz_word:
530: sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
531: m68kpc_offset += 2;
532: break;
533: case sz_long:
534: sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
535: m68kpc_offset += 4;
536: break;
537: default:
538: break;
539: }
540: break;
541: case imm0:
542: offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
543: m68kpc_offset += 2;
544: sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
545: break;
546: case imm1:
547: offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
548: m68kpc_offset += 2;
549: sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
550: break;
551: case imm2:
552: offset = (uae_s32)get_ilong_1 (m68kpc_offset);
553: m68kpc_offset += 4;
554: sprintf (buffer,"#$%08lx", (unsigned long)offset);
555: break;
556: case immi:
557: offset = (uae_s32)(uae_s8)(reg & 0xff);
558: sprintf (buffer,"#$%08lx", (unsigned long)offset);
559: break;
560: default:
561: break;
562: }
563: if (buf == 0)
564: fprintf (f, "%s", buffer);
565: else
566: strcat (buf, buffer);
567: return offset;
568: }
569:
1.1.1.8 root 570:
1.1 root 571: /* The plan is that this will take over the job of exception 3 handling -
572: * the CPU emulation functions will just do a longjmp to m68k_go whenever
573: * they hit an odd address. */
1.1.1.8 root 574: #if 0
1.1 root 575: static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
576: {
577: uae_u16 dp;
578: uae_s8 disp8;
579: uae_s16 disp16;
580: int r;
581: uae_u32 dispreg;
582: uaecptr addr;
1.1.1.5 root 583: /*uae_s32 offset = 0;*/
1.1 root 584:
585: switch (mode){
586: case Dreg:
587: *val = m68k_dreg (regs, reg);
588: return 1;
589: case Areg:
590: *val = m68k_areg (regs, reg);
591: return 1;
592:
593: case Aind:
594: case Aipi:
595: addr = m68k_areg (regs, reg);
596: break;
597: case Apdi:
598: addr = m68k_areg (regs, reg);
599: break;
600: case Ad16:
601: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
602: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
603: break;
604: case Ad8r:
605: addr = m68k_areg (regs, reg);
606: d8r_common:
607: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
608: disp8 = dp & 0xFF;
609: r = (dp & 0x7000) >> 12;
610: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
611: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
612: dispreg <<= (dp >> 9) & 3;
613:
614: if (dp & 0x100) {
615: uae_s32 outer = 0, disp = 0;
616: uae_s32 base = addr;
617: if (dp & 0x80) base = 0;
618: if (dp & 0x40) dispreg = 0;
619: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
620: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
621: base += disp;
622:
623: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
624: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
625:
626: if (!(dp & 4)) base += dispreg;
627: if (dp & 3) base = get_long (base);
628: if (dp & 4) base += dispreg;
629:
630: addr = base + outer;
631: } else {
632: addr += (uae_s32)((uae_s8)disp8) + dispreg;
633: }
634: break;
635: case PC16:
636: addr = m68k_getpc () + m68kpc_offset;
637: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
638: addr += (uae_s16)disp16;
639: break;
640: case PC8r:
641: addr = m68k_getpc () + m68kpc_offset;
642: goto d8r_common;
643: case absw:
644: addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
645: m68kpc_offset += 2;
646: break;
647: case absl:
648: addr = get_ilong_1 (m68kpc_offset);
649: m68kpc_offset += 4;
650: break;
651: case imm:
652: switch (size){
653: case sz_byte:
654: *val = get_iword_1 (m68kpc_offset) & 0xff;
655: m68kpc_offset += 2;
656: break;
657: case sz_word:
658: *val = get_iword_1 (m68kpc_offset) & 0xffff;
659: m68kpc_offset += 2;
660: break;
661: case sz_long:
662: *val = get_ilong_1 (m68kpc_offset);
663: m68kpc_offset += 4;
664: break;
665: default:
666: break;
667: }
668: return 1;
669: case imm0:
670: *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
671: m68kpc_offset += 2;
672: return 1;
673: case imm1:
674: *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
675: m68kpc_offset += 2;
676: return 1;
677: case imm2:
678: *val = get_ilong_1 (m68kpc_offset);
679: m68kpc_offset += 4;
680: return 1;
681: case immi:
682: *val = (uae_s32)(uae_s8)(reg & 0xff);
683: return 1;
684: default:
685: addr = 0;
686: break;
687: }
688: if ((addr & 1) == 0)
689: return 1;
690:
691: last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
692: last_fault_for_exception_3 = addr;
693: return 0;
694: }
1.1.1.8 root 695: #endif
696:
1.1 root 697:
698: uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
699: {
700: int reg = (dp >> 12) & 15;
701: uae_s32 regd = regs.regs[reg];
702: if ((dp & 0x800) == 0)
703: regd = (uae_s32)(uae_s16)regd;
704: regd <<= (dp >> 9) & 3;
705: if (dp & 0x100) {
706: uae_s32 outer = 0;
707: if (dp & 0x80) base = 0;
708: if (dp & 0x40) regd = 0;
709:
710: if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
711: if ((dp & 0x30) == 0x30) base += next_ilong();
712:
713: if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
714: if ((dp & 0x3) == 0x3) outer = next_ilong();
715:
716: if ((dp & 0x4) == 0) base += regd;
717: if (dp & 0x3) base = get_long (base);
718: if (dp & 0x4) base += regd;
719:
720: return base + outer;
721: } else {
722: return base + (uae_s32)((uae_s8)dp) + regd;
723: }
724: }
725:
726: uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
727: {
728: int reg = (dp >> 12) & 15;
729: uae_s32 regd = regs.regs[reg];
730: #if 1
731: if ((dp & 0x800) == 0)
732: regd = (uae_s32)(uae_s16)regd;
733: return base + (uae_s8)dp + regd;
734: #else
735: /* Branch-free code... benchmark this again now that
736: * things are no longer inline. */
737: uae_s32 regd16;
738: uae_u32 mask;
739: mask = ((dp & 0x800) >> 11) - 1;
740: regd16 = (uae_s32)(uae_s16)regd;
741: regd16 &= mask;
742: mask = ~mask;
743: base += (uae_s8)dp;
744: regd &= mask;
745: regd |= regd16;
746: return base + regd;
747: #endif
748: }
749:
1.1.1.8 root 750:
751: /* Create the Status Register from the flags */
1.1 root 752: void MakeSR (void)
753: {
754: #if 0
755: assert((regs.t1 & 1) == regs.t1);
756: assert((regs.t0 & 1) == regs.t0);
757: assert((regs.s & 1) == regs.s);
758: assert((regs.m & 1) == regs.m);
759: assert((XFLG & 1) == XFLG);
760: assert((NFLG & 1) == NFLG);
761: assert((ZFLG & 1) == ZFLG);
762: assert((VFLG & 1) == VFLG);
763: assert((CFLG & 1) == CFLG);
764: #endif
765: regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
766: | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
767: | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
768: | GET_CFLG);
769: }
770:
1.1.1.8 root 771:
772: /* Set up the flags from Status Register */
1.1 root 773: void MakeFromSR (void)
774: {
775: int oldm = regs.m;
776: int olds = regs.s;
777:
778: regs.t1 = (regs.sr >> 15) & 1;
779: regs.t0 = (regs.sr >> 14) & 1;
780: regs.s = (regs.sr >> 13) & 1;
781: regs.m = (regs.sr >> 12) & 1;
782: regs.intmask = (regs.sr >> 8) & 7;
783: SET_XFLG ((regs.sr >> 4) & 1);
784: SET_NFLG ((regs.sr >> 3) & 1);
785: SET_ZFLG ((regs.sr >> 2) & 1);
786: SET_VFLG ((regs.sr >> 1) & 1);
787: SET_CFLG (regs.sr & 1);
1.1.1.12 root 788: if (currprefs.cpu_level >= 2) {
1.1 root 789: if (olds != regs.s) {
790: if (olds) {
791: if (oldm)
792: regs.msp = m68k_areg(regs, 7);
793: else
794: regs.isp = m68k_areg(regs, 7);
795: m68k_areg(regs, 7) = regs.usp;
796: } else {
797: regs.usp = m68k_areg(regs, 7);
798: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
799: }
800: } else if (olds && oldm != regs.m) {
801: if (oldm) {
802: regs.msp = m68k_areg(regs, 7);
803: m68k_areg(regs, 7) = regs.isp;
804: } else {
805: regs.isp = m68k_areg(regs, 7);
806: m68k_areg(regs, 7) = regs.msp;
807: }
808: }
809: } else {
1.1.1.12 root 810: /* [NP] If cpu < 68020, m and t0 are ignored and should be set to 0 */
811: regs.t0 = 0;
812: regs.m = 0;
813:
1.1 root 814: if (olds != regs.s) {
815: if (olds) {
816: regs.isp = m68k_areg(regs, 7);
817: m68k_areg(regs, 7) = regs.usp;
818: } else {
819: regs.usp = m68k_areg(regs, 7);
820: m68k_areg(regs, 7) = regs.isp;
821: }
822: }
823: }
824:
1.1.1.8 root 825: /* Pending interrupts can occur again after a write to the SR: */
826: set_special (SPCFLAG_DOINT);
1.1 root 827: if (regs.t1 || regs.t0)
828: set_special (SPCFLAG_TRACE);
829: else
1.1.1.6 root 830: /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
831: SR-modifying instructions (including STOP). */
832: unset_special (SPCFLAG_TRACE);
1.1 root 833: }
834:
1.1.1.5 root 835:
1.1.1.12 root 836: static void exception_trace (int nr)
837: {
838: unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
839: if (regs.t1 && !regs.t0) {
840: /* trace stays pending if exception is div by zero, chk,
841: * trapv or trap #x
842: */
843: if (nr == 5 || nr == 6 || nr == 7 || (nr >= 32 && nr <= 47))
844: set_special (SPCFLAG_DOTRACE);
845: }
846: regs.t1 = regs.t0 = regs.m = 0;
847: }
848:
849:
1.1.1.14 root 850: /*
851: * Compute the number of jitter cycles to add when a video interrupt occurs
852: * (this is specific to the Atari ST)
853: */
854: static void InterruptAddJitter (int Level , int Pending)
855: {
856: int cycles = 0;
857:
858: if ( Level == 2 ) /* HBL */
859: {
860: if ( Pending )
861: cycles = HblJitterArrayPending[ HblJitterIndex ];
862: else
863: cycles = HblJitterArray[ HblJitterIndex ];
864: }
865:
866: else if ( Level == 4 ) /* VBL */
867: {
868: if ( Pending )
869: cycles = VblJitterArrayPending[ VblJitterIndex ];
870: else
871: cycles = VblJitterArray[ VblJitterIndex ];
872: }
873:
874: //fprintf ( stderr , "jitter %d\n" , cycles );
875: //cycles=0;
876: if ( cycles > 0 ) /* no need to call M68000_AddCycles if cycles == 0 */
877: M68000_AddCycles ( cycles );
878: }
879:
880:
1.1.1.13 root 881: /* Handle exceptions. We need a special case to handle MFP exceptions */
882: /* on Atari ST, because it's possible to change the MFP's vector base */
883: /* and get a conflict with 'normal' cpu exceptions. */
884: void Exception(int nr, uaecptr oldpc, int ExceptionSource)
1.1 root 885: {
1.1.1.17 root 886: uae_u32 currpc = m68k_getpc () , newpc;
1.1 root 887:
1.1.1.2 root 888: /*if( nr>=2 && nr<10 ) fprintf(stderr,"Exception (-> %i bombs)!\n",nr);*/
1.1 root 889:
1.1.1.19 root 890: /* Pending bits / vector number can change before the end of the IACK sequence. */
891: /* We need to handle MFP and HBL/VBL cases for this. */
892: if ( ExceptionSource == M68000_EXC_SRC_INT_MFP )
893: {
1.1.1.21! root 894: M68000_AddCycles ( CPU_IACK_CYCLES_START+CPU_IACK_CYCLES_MFP );
1.1.1.19 root 895: CPU_IACK = true;
896: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
897: CALL_VAR(PendingInterruptFunction);
898: nr = MFP_ProcessIACK ( nr );
899: CPU_IACK = false;
900: }
1.1.1.20 root 901: else if ( ( ExceptionSource == M68000_EXC_SRC_AUTOVEC ) && ( ( nr == 26 ) || ( nr == 28 ) ) )
1.1.1.19 root 902: {
1.1.1.21! root 903: M68000_AddCycles ( CPU_IACK_CYCLES_START+CPU_IACK_CYCLES_VIDEO );
1.1.1.19 root 904: CPU_IACK = true;
905: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
906: CALL_VAR(PendingInterruptFunction);
1.1.1.20 root 907: if ( MFP_UpdateNeeded == true )
908: MFP_UpdateIRQ ( 0 ); /* update MFP's state if some internal timers related to MFP expired */
1.1.1.19 root 909: pendingInterrupts &= ~( 1 << ( nr - 24 ) ); /* clear HBL or VBL pending bit */
910: CPU_IACK = false;
911: }
912:
913:
1.1.1.16 root 914: if (ExceptionSource == M68000_EXC_SRC_CPU)
1.1.1.5 root 915: {
1.1.1.20 root 916: if (nr == 0x22)
1.1.1.13 root 917: {
1.1.1.17 root 918: /* Intercept VDI & AES exceptions (Trap #2) */
1.1.1.20 root 919: if(bVdiAesIntercept && VDI_AES_Entry())
1.1.1.13 root 920: {
1.1.1.17 root 921: /* Set 'PC' to address of 'VDI_OPCODE' illegal instruction.
922: * This will call OpCode_VDI() after completion of Trap call!
923: * This is used to modify specific VDI return vectors contents.
924: */
1.1.1.13 root 925: VDI_OldPC = currpc;
926: currpc = CART_VDI_OPCODE_ADDR;
927: }
928: }
1.1.1.20 root 929: else if (nr == 0x2d)
1.1.1.13 root 930: {
1.1.1.20 root 931: /* Intercept BIOS (Trap #13) calls */
932: if (Bios()) return;
933: }
934: else if (nr == 0x2e)
935: {
936: /* Intercept XBIOS (Trap #14) calls */
937: if (XBios()) return;
1.1.1.13 root 938: }
1.1.1.5 root 939: }
1.1.1.8 root 940:
1.1 root 941: MakeSR();
942:
1.1.1.8 root 943: /* Change to supervisor mode if necessary */
1.1 root 944: if (!regs.s) {
945: regs.usp = m68k_areg(regs, 7);
1.1.1.12 root 946: if (currprefs.cpu_level >= 2)
1.1 root 947: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
948: else
949: m68k_areg(regs, 7) = regs.isp;
950: regs.s = 1;
951: }
1.1.1.8 root 952:
953: /* Build additional exception stack frame for 68010 and higher */
1.1.1.13 root 954: /* (special case for MFP) */
1.1.1.12 root 955: if (currprefs.cpu_level > 0) {
1.1.1.16 root 956: if (ExceptionSource == M68000_EXC_SRC_INT_MFP
957: || ExceptionSource == M68000_EXC_SRC_INT_DSP) {
1.1.1.13 root 958: m68k_areg(regs, 7) -= 2;
959: put_word (m68k_areg(regs, 7), nr * 4); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
960: }
961: else if (nr == 2 || nr == 3) {
1.1 root 962: int i;
963: /* @@@ this is probably wrong (?) */
964: for (i = 0 ; i < 12 ; i++) {
965: m68k_areg(regs, 7) -= 2;
966: put_word (m68k_areg(regs, 7), 0);
967: }
968: m68k_areg(regs, 7) -= 2;
969: put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
970: } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
971: m68k_areg(regs, 7) -= 4;
972: put_long (m68k_areg(regs, 7), oldpc);
973: m68k_areg(regs, 7) -= 2;
974: put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
975: } else if (regs.m && nr >= 24 && nr < 32) {
976: m68k_areg(regs, 7) -= 2;
977: put_word (m68k_areg(regs, 7), nr * 4);
978: m68k_areg(regs, 7) -= 4;
979: put_long (m68k_areg(regs, 7), currpc);
980: m68k_areg(regs, 7) -= 2;
981: put_word (m68k_areg(regs, 7), regs.sr);
982: regs.sr |= (1 << 13);
983: regs.msp = m68k_areg(regs, 7);
984: m68k_areg(regs, 7) = regs.isp;
985: m68k_areg(regs, 7) -= 2;
986: put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
987: } else {
988: m68k_areg(regs, 7) -= 2;
989: put_word (m68k_areg(regs, 7), nr * 4);
990: }
991: }
1.1.1.3 root 992:
993: /* Push PC on stack: */
1.1 root 994: m68k_areg(regs, 7) -= 4;
995: put_long (m68k_areg(regs, 7), currpc);
1.1.1.3 root 996: /* Push SR on stack: */
1.1 root 997: m68k_areg(regs, 7) -= 2;
998: put_word (m68k_areg(regs, 7), regs.sr);
1.1.1.3 root 999:
1.1.1.15 root 1000: LOG_TRACE(TRACE_CPU_EXCEPTION, "cpu exception %d currpc %x buspc %x newpc %x fault_e3 %x op_e3 %hx addr_e3 %x\n",
1.1.1.21! root 1001: nr, currpc, regs.instruction_pc, get_long (regs.vbr + 4*nr), last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3);
1.1.1.12 root 1002:
1.1.1.3 root 1003: /* 68000 bus/address errors: */
1.1.1.16 root 1004: if (currprefs.cpu_level==0 && (nr==2 || nr==3) && ExceptionSource == M68000_EXC_SRC_CPU) {
1.1.1.21! root 1005: uae_u16 specialstatus = last_instructionaccess_for_exception_3 ? 2 : 1;
1.1.1.20 root 1006: uae_u16 BusError_opcode;
1.1.1.12 root 1007:
1.1.1.8 root 1008: /* Special status word emulation isn't perfect yet... :-( */
1009: if (regs.sr & 0x2000)
1010: specialstatus |= 0x4;
1.1.1.3 root 1011: m68k_areg(regs, 7) -= 8;
1012: if (nr == 3) { /* Address error */
1.1.1.12 root 1013: specialstatus |= ( last_op_for_exception_3 & (~0x1f) ); /* [NP] unused bits of specialstatus are those of the last opcode ! */
1.1.1.21! root 1014: if (last_writeaccess_for_exception_3==0)
! 1015: specialstatus |= 0x10; /* bit 4 : 0=write 1=read */
1.1.1.8 root 1016: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.3 root 1017: put_long (m68k_areg(regs, 7)+2, last_fault_for_exception_3);
1018: put_word (m68k_areg(regs, 7)+6, last_op_for_exception_3);
1019: put_long (m68k_areg(regs, 7)+10, last_addr_for_exception_3);
1.1.1.21! root 1020:
! 1021: /* [NP] PC stored in the stack frame is not necessarily pointing to the next instruction ! */
! 1022: /* FIXME : we should have a proper model for this, in the meantime we handle specific cases */
! 1023: if ( last_op_for_exception_3 == 0x2285 ) /* move.l d5,(a1) (War Heli) */
! 1024: put_long (m68k_areg(regs, 7)+10, currpc+4); /* correct PC is 2 bytes more than usual value */
! 1025:
! 1026: fprintf(stderr,"Address Error at address $%x, PC=$%x addr_e3=%x op_e3=%x\n",last_fault_for_exception_3, currpc, last_addr_for_exception_3, last_op_for_exception_3);
1.1.1.20 root 1027: if (ExceptionDebugMask & EXCEPT_ADDRESS) {
1.1.1.18 root 1028: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.8 root 1029: }
1.1.1.3 root 1030: }
1.1.1.8 root 1031: else { /* Bus error */
1.1.1.20 root 1032: /* Get the opcode that caused the bus error, to adapt the stack frame in some cases */
1.1.1.21! root 1033: BusError_opcode = regs.opcode;
1.1.1.20 root 1034:
1035: specialstatus |= ( BusError_opcode & (~0x1f) ); /* [NP] unused bits of special status are those of the last opcode ! */
1.1.1.8 root 1036: if (bBusErrorReadWrite)
1.1.1.21! root 1037: specialstatus |= 0x10; /* bit 4 : 0=write 1=read */
1.1.1.8 root 1038: put_word (m68k_areg(regs, 7), specialstatus);
1.1.1.10 root 1039: put_long (m68k_areg(regs, 7)+2, BusErrorAddress);
1.1.1.20 root 1040: put_word (m68k_areg(regs, 7)+6, BusError_opcode); /* Opcode */
1.1.1.12 root 1041:
1042: /* [NP] PC stored in the stack frame is not necessarily pointing to the next instruction ! */
1043: /* FIXME : we should have a proper model for this, in the meantime we handle specific cases */
1.1.1.21! root 1044: if ( BusError_opcode == 0x21f8 ) /* move.l $0.w,$24.w (Transbeauce 2 loader) */
! 1045: put_long (m68k_areg(regs, 7)+10, currpc-2); /* correct PC is 2 bytes less than usual value */
1.1.1.20 root 1046:
1.1.1.21! root 1047: else if ( ( regs.instruction_pc == 0xccc ) && ( BusError_opcode == 0x48d6 ) ) /* 48d6 3f00 movem.l a0-a5,(a6) (Blood Money) */
! 1048: put_long (m68k_areg(regs, 7)+10, currpc+2); /* correct PC is 2 bytes more than usual value */
1.1.1.20 root 1049:
1.1.1.21! root 1050: else if ( ( regs.instruction_pc == 0x1fece ) && ( BusError_opcode == 0x33d4 ) ) /* 1fece : 33d4 0001 fdca move.w (a4),$1fdca (Batman The Movie) */
! 1051: put_long (m68k_areg(regs, 7)+10, currpc-4); /* correct PC is 4 bytes less than usual value */
1.1.1.20 root 1052:
1053: /* [NP] In case of a move with a bus error on the read part, uae cpu is writing to the dest part */
1054: /* then process the bus error ; on a real CPU, the bus error occurs after the read and before the */
1055: /* write, so the dest part doesn't change. For now, we restore the dest part on some specific cases */
1056: /* FIXME : the bus error should be processed just after the read, not at the end of the instruction */
1.1.1.21! root 1057: else if ( ( regs.instruction_pc == 0x62a ) && ( BusError_opcode == 0x3079 ) ) /* 3079 4ef9 0000 move.l $4ef90000,a0 (Dragon Flight) */
! 1058: m68k_areg(regs, 0) = 8; /* A0 should not be changed to "0" but keep its value "8" */
1.1.1.20 root 1059:
1.1.1.21! root 1060: else if ( get_long(regs.instruction_pc) == 0x13f88e21 ) /* 13f8 8e21 move.b $ffff8e21.w,$xxxxx (Tymewarp) */
! 1061: put_byte ( get_long(regs.instruction_pc+4) , 0x00 ); /* dest content should not be changed to "ff" but keep its value "00" */
1.1.1.20 root 1062:
1.1.1.21! root 1063: fprintf(stderr,"Bus Error at address $%x, PC=$%x addr_e3=%x op_e3=%x\n", BusErrorAddress, currpc, get_long(m68k_areg(regs, 7)+10) , BusError_opcode);
1.1.1.20 root 1064:
1.1.1.8 root 1065: /* Check for double bus errors: */
1066: if (regs.spcflags & SPCFLAG_BUSERROR) {
1.1.1.21! root 1067: fprintf(stderr, "Detected double bus error at address $%x, PC=$%lx => CPU halted!\n", BusErrorAddress, (long)currpc);
! 1068: cpu_halt();
1.1.1.8 root 1069: return;
1070: }
1.1.1.20 root 1071: if ((ExceptionDebugMask & EXCEPT_BUS) && BusErrorAddress!=0xff8a00) {
1.1.1.10 root 1072: fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n", BusErrorAddress, (long)currpc);
1.1.1.18 root 1073: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.8 root 1074: }
1075: }
1.1.1.3 root 1076: }
1077:
1.1.1.8 root 1078: /* Set PC and flags */
1.1.1.20 root 1079: if ((ExceptionDebugMask & EXCEPT_NOHANDLER) && (regs.vbr + 4*nr) == 0) {
1080: fprintf(stderr,"Uninitialized exception handler #%i!\n", nr);
1.1.1.18 root 1081: DebugUI(REASON_CPU_EXCEPTION);
1.1.1.8 root 1082: }
1.1.1.17 root 1083: newpc = get_long (regs.vbr + 4*nr);
1084: if ( newpc & 1) /* check new pc is even */
1085: {
1086: if ( nr==2 || nr==3 ) /* address error during bus/address error -> stop emulation */
1087: {
1.1.1.21! root 1088: fprintf(stderr,"Address Error during exception 2/3, new PC=$%x => CPU halted\n",newpc);
! 1089: cpu_halt();
1.1.1.17 root 1090: }
1091: else
1092: {
1093: fprintf(stderr,"Address Error during exception, new PC=$%x\n",newpc);
1094: Exception ( 3 , m68k_getpc() , M68000_EXC_SRC_CPU );
1095: }
1096: return;
1097: }
1.1.1.20 root 1098: /* handle debugger invocation for rest of exceptions */
1099: if (ExceptionDebugMask && nr > 3 && nr < 9)
1100: DebugUI_Exceptions(nr, currpc);
1.1.1.17 root 1101:
1.1 root 1102: m68k_setpc (get_long (regs.vbr + 4*nr));
1103: fill_prefetch_0 ();
1.1.1.12 root 1104: /* Handle trace flags depending on current state */
1105: exception_trace (nr);
1.1.1.6 root 1106:
1.1.1.13 root 1107: /* Handle exception cycles (special case for MFP) */
1.1.1.16 root 1108: if (ExceptionSource == M68000_EXC_SRC_INT_MFP)
1.1.1.13 root 1109: {
1.1.1.21! root 1110: M68000_AddCycles(44+12-CPU_IACK_CYCLES_START-CPU_IACK_CYCLES_MFP); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
1.1.1.13 root 1111: }
1112: else if (nr >= 24 && nr <= 31)
1.1.1.7 root 1113: {
1.1.1.21! root 1114: if ( nr == 26 ) /* HBL */
! 1115: M68000_AddCycles(44+12-CPU_IACK_CYCLES_START-CPU_IACK_CYCLES_VIDEO); /* Video Interrupt */
! 1116: else if ( nr == 28 ) /* VBL */
! 1117: M68000_AddCycles(44+12-CPU_IACK_CYCLES_START-CPU_IACK_CYCLES_VIDEO); /* Video Interrupt */
1.1.1.12 root 1118: else
1.1.1.21! root 1119: M68000_AddCycles(44+4); /* Other Interrupts */
1.1.1.7 root 1120: }
1121: else if(nr >= 32 && nr <= 47)
1122: {
1.1.1.13 root 1123: M68000_AddCycles(34-4); /* Trap (total is 34, but cpuemu.c already adds 4) */
1.1.1.7 root 1124: }
1125: else switch(nr)
1126: {
1.1.1.12 root 1127: case 2: M68000_AddCycles(50); break; /* Bus error */
1128: case 3: M68000_AddCycles(50); break; /* Address error */
1129: case 4: M68000_AddCycles(34); break; /* Illegal instruction */
1130: case 5: M68000_AddCycles(38); break; /* Div by zero */
1131: case 6: M68000_AddCycles(40); break; /* CHK */
1132: case 7: M68000_AddCycles(34); break; /* TRAPV */
1133: case 8: M68000_AddCycles(34); break; /* Privilege violation */
1134: case 9: M68000_AddCycles(34); break; /* Trace */
1135: case 10: M68000_AddCycles(34); break; /* Line-A - probably wrong */
1136: case 11: M68000_AddCycles(34); break; /* Line-F - probably wrong */
1.1.1.7 root 1137: default:
1.1.1.8 root 1138: /* FIXME: Add right cycles value for MFP interrupts and copro exceptions ... */
1.1.1.7 root 1139: if(nr < 64)
1.1.1.12 root 1140: M68000_AddCycles(4); /* Coprocessor and unassigned exceptions (???) */
1.1.1.7 root 1141: else
1.1.1.16 root 1142: M68000_AddCycles(44+12); /* Must be a MFP or DSP interrupt */
1.1.1.7 root 1143: break;
1.1.1.6 root 1144: }
1.1.1.14 root 1145:
1.1 root 1146: }
1147:
1.1.1.7 root 1148:
1.1.1.14 root 1149: static void Interrupt(int nr , int Pending)
1.1 root 1150: {
1151: assert(nr < 8 && nr >= 0);
1.1.1.10 root 1152: /*lastint_regs = regs;*/
1153: /*lastint_no = nr;*/
1.1.1.13 root 1154:
1.1.1.16 root 1155: /* On Hatari, only video ints are using SPCFLAG_INT (see m68000.c) */
1156: Exception(nr+24, 0, M68000_EXC_SRC_AUTOVEC);
1.1 root 1157:
1158: regs.intmask = nr;
1159: set_special (SPCFLAG_INT);
1.1.1.14 root 1160:
1161: /* Handle Atari ST's specific jitter for hbl/vbl */
1162: InterruptAddJitter ( nr , Pending );
1.1 root 1163: }
1164:
1.1.1.7 root 1165:
1.1.1.12 root 1166: uae_u32 caar, cacr;
1.1.1.8 root 1167: static uae_u32 itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp;
1.1 root 1168:
1.1.1.7 root 1169:
1.1.1.12 root 1170: static int movec_illg (int regno)
1171: {
1172: int regno2 = regno & 0x7ff;
1173: if (currprefs.cpu_level == 1) { /* 68010 */
1174: if (regno2 < 2)
1175: return 0;
1176: return 1;
1177: }
1178: if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) { /* 68020 */
1179: if (regno == 3) return 1; /* 68040 only */
1180: /* 4 is >=68040, but 0x804 is in 68020 */
1181: if (regno2 < 4 || regno == 0x804)
1182: return 0;
1183: return 1;
1184: }
1185: if (currprefs.cpu_level >= 4) { /* 68040 */
1186: if (regno == 0x802) return 1; /* 68020 only */
1187: if (regno2 < 8) return 0;
1188: if (currprefs.cpu_level == 6 && regno2 == 8) /* 68060 only */
1189: return 0;
1190: return 1;
1191: }
1192: return 1;
1193: }
1194:
1.1 root 1195: int m68k_move2c (int regno, uae_u32 *regp)
1196: {
1.1.1.12 root 1197: if (movec_illg (regno)) {
1.1 root 1198: op_illg (0x4E7B);
1199: return 0;
1200: } else {
1201: switch (regno) {
1202: case 0: regs.sfc = *regp & 7; break;
1203: case 1: regs.dfc = *regp & 7; break;
1.1.1.16 root 1204: case 2:
1205: {
1206: uae_u32 cacr_mask = 0;
1207: if (currprefs.cpu_level == 2) // 68020
1208: cacr_mask = 0x0000000f;
1209: else if (currprefs.cpu_level == 3) // Fake 68030
1210: cacr_mask = 0x00003f1f;
1211: else if (currprefs.cpu_level == 4) // 68040
1212: cacr_mask = 0x80008000;
1213: cacr = *regp & cacr_mask;
1214: }
1.1 root 1215: case 3: tc = *regp & 0xc000; break;
1216: /* Mask out fields that should be zero. */
1217: case 4: itt0 = *regp & 0xffffe364; break;
1218: case 5: itt1 = *regp & 0xffffe364; break;
1219: case 6: dtt0 = *regp & 0xffffe364; break;
1220: case 7: dtt1 = *regp & 0xffffe364; break;
1.1.1.7 root 1221:
1.1 root 1222: case 0x800: regs.usp = *regp; break;
1223: case 0x801: regs.vbr = *regp; break;
1.1.1.20 root 1224: case 0x802: caar = *regp; break;
1.1 root 1225: case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
1226: case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
1.1.1.6 root 1227: case 0x805: mmusr = *regp; break;
1228: case 0x806: urp = *regp; break;
1229: case 0x807: srp = *regp; break;
1.1 root 1230: default:
1231: op_illg (0x4E7B);
1232: return 0;
1233: }
1234: }
1235: return 1;
1236: }
1237:
1238: int m68k_movec2 (int regno, uae_u32 *regp)
1239: {
1.1.1.12 root 1240: if (movec_illg (regno)) {
1.1 root 1241: op_illg (0x4E7A);
1242: return 0;
1243: } else {
1244: switch (regno) {
1245: case 0: *regp = regs.sfc; break;
1246: case 1: *regp = regs.dfc; break;
1.1.1.12 root 1247: case 2: *regp = cacr; break;
1.1 root 1248: case 3: *regp = tc; break;
1249: case 4: *regp = itt0; break;
1250: case 5: *regp = itt1; break;
1251: case 6: *regp = dtt0; break;
1252: case 7: *regp = dtt1; break;
1253: case 0x800: *regp = regs.usp; break;
1254: case 0x801: *regp = regs.vbr; break;
1.1.1.12 root 1255: case 0x802: *regp = caar; break;
1.1 root 1256: case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
1257: case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
1258: case 0x805: *regp = mmusr; break;
1.1.1.6 root 1259: case 0x806: *regp = urp; break;
1260: case 0x807: *regp = srp; break;
1.1 root 1261: default:
1262: op_illg (0x4E7A);
1263: return 0;
1264: }
1265: }
1266: return 1;
1267: }
1268:
1269: STATIC_INLINE int
1.1.1.10 root 1270: div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 ndiv, uae_u32 *quot, uae_u32 *rem)
1.1 root 1271: {
1272: uae_u32 q = 0, cbit = 0;
1273: int i;
1274:
1.1.1.10 root 1275: if (ndiv <= src_hi) {
1.1 root 1276: return 1;
1277: }
1278: for (i = 0 ; i < 32 ; i++) {
1279: cbit = src_hi & 0x80000000ul;
1280: src_hi <<= 1;
1281: if (src_lo & 0x80000000ul) src_hi++;
1282: src_lo <<= 1;
1283: q = q << 1;
1.1.1.10 root 1284: if (cbit || ndiv <= src_hi) {
1.1 root 1285: q |= 1;
1.1.1.10 root 1286: src_hi -= ndiv;
1.1 root 1287: }
1288: }
1289: *quot = q;
1290: *rem = src_hi;
1291: return 0;
1292: }
1293:
1294: void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
1295: {
1296: #if defined(uae_s64)
1297: if (src == 0) {
1.1.1.16 root 1298: Exception (5, oldpc,M68000_EXC_SRC_CPU);
1.1 root 1299: return;
1300: }
1301: if (extra & 0x800) {
1302: /* signed variant */
1303: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1304: uae_s64 quot, rem;
1305:
1306: if (extra & 0x400) {
1307: a &= 0xffffffffu;
1308: a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
1309: }
1310: rem = a % (uae_s64)(uae_s32)src;
1311: quot = a / (uae_s64)(uae_s32)src;
1312: if ((quot & UVAL64(0xffffffff80000000)) != 0
1313: && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1314: {
1315: SET_VFLG (1);
1316: SET_NFLG (1);
1317: SET_CFLG (0);
1318: } else {
1319: if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
1320: SET_VFLG (0);
1321: SET_CFLG (0);
1322: SET_ZFLG (((uae_s32)quot) == 0);
1323: SET_NFLG (((uae_s32)quot) < 0);
1324: m68k_dreg(regs, extra & 7) = rem;
1325: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1326: }
1327: } else {
1328: /* unsigned */
1329: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1330: uae_u64 quot, rem;
1331:
1332: if (extra & 0x400) {
1333: a &= 0xffffffffu;
1334: a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
1335: }
1336: rem = a % (uae_u64)src;
1337: quot = a / (uae_u64)src;
1338: if (quot > 0xffffffffu) {
1339: SET_VFLG (1);
1340: SET_NFLG (1);
1341: SET_CFLG (0);
1342: } else {
1343: SET_VFLG (0);
1344: SET_CFLG (0);
1345: SET_ZFLG (((uae_s32)quot) == 0);
1346: SET_NFLG (((uae_s32)quot) < 0);
1347: m68k_dreg(regs, extra & 7) = rem;
1348: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1349: }
1350: }
1351: #else
1352: if (src == 0) {
1.1.1.16 root 1353: Exception (5, oldpc,M68000_EXC_SRC_CPU);
1.1 root 1354: return;
1355: }
1356: if (extra & 0x800) {
1357: /* signed variant */
1358: uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1359: uae_s32 hi = lo < 0 ? -1 : 0;
1360: uae_s32 save_high;
1361: uae_u32 quot, rem;
1362: uae_u32 sign;
1363:
1364: if (extra & 0x400) {
1365: hi = (uae_s32)m68k_dreg(regs, extra & 7);
1366: }
1367: save_high = hi;
1368: sign = (hi ^ src);
1369: if (hi < 0) {
1370: hi = ~hi;
1371: lo = -lo;
1372: if (lo == 0) hi++;
1373: }
1374: if ((uae_s32)src < 0) src = -src;
1375: if (div_unsigned(hi, lo, src, ", &rem) ||
1376: (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
1377: SET_VFLG (1);
1378: SET_NFLG (1);
1379: SET_CFLG (0);
1380: } else {
1381: if (sign & 0x80000000) quot = -quot;
1382: if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
1383: SET_VFLG (0);
1384: SET_CFLG (0);
1385: SET_ZFLG (((uae_s32)quot) == 0);
1386: SET_NFLG (((uae_s32)quot) < 0);
1387: m68k_dreg(regs, extra & 7) = rem;
1388: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1389: }
1390: } else {
1391: /* unsigned */
1392: uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1393: uae_u32 hi = 0;
1394: uae_u32 quot, rem;
1395:
1396: if (extra & 0x400) {
1397: hi = (uae_u32)m68k_dreg(regs, extra & 7);
1398: }
1399: if (div_unsigned(hi, lo, src, ", &rem)) {
1400: SET_VFLG (1);
1401: SET_NFLG (1);
1402: SET_CFLG (0);
1403: } else {
1404: SET_VFLG (0);
1405: SET_CFLG (0);
1406: SET_ZFLG (((uae_s32)quot) == 0);
1407: SET_NFLG (((uae_s32)quot) < 0);
1408: m68k_dreg(regs, extra & 7) = rem;
1409: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1410: }
1411: }
1412: #endif
1413: }
1414:
1415: STATIC_INLINE void
1416: mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1417: {
1418: uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1419: uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1420: uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1421: uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1422: uae_u32 lo;
1423:
1424: lo = r0 + ((r1 << 16) & 0xffff0000ul);
1425: if (lo < r0) r3++;
1426: r0 = lo;
1427: lo = r0 + ((r2 << 16) & 0xffff0000ul);
1428: if (lo < r0) r3++;
1429: r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1430: *dst_lo = lo;
1431: *dst_hi = r3;
1432: }
1433:
1434: void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1435: {
1436: #if defined(uae_s64)
1437: if (extra & 0x800) {
1438: /* signed variant */
1439: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1440:
1441: a *= (uae_s64)(uae_s32)src;
1442: SET_VFLG (0);
1443: SET_CFLG (0);
1444: SET_ZFLG (a == 0);
1445: SET_NFLG (a < 0);
1446: if (extra & 0x400)
1447: m68k_dreg(regs, extra & 7) = a >> 32;
1448: else if ((a & UVAL64(0xffffffff80000000)) != 0
1449: && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1450: {
1451: SET_VFLG (1);
1452: }
1453: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1454: } else {
1455: /* unsigned */
1456: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1457:
1458: a *= (uae_u64)src;
1459: SET_VFLG (0);
1460: SET_CFLG (0);
1461: SET_ZFLG (a == 0);
1462: SET_NFLG (((uae_s64)a) < 0);
1463: if (extra & 0x400)
1464: m68k_dreg(regs, extra & 7) = a >> 32;
1465: else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1466: SET_VFLG (1);
1467: }
1468: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1469: }
1470: #else
1471: if (extra & 0x800) {
1472: /* signed variant */
1473: uae_s32 src1,src2;
1474: uae_u32 dst_lo,dst_hi;
1475: uae_u32 sign;
1476:
1477: src1 = (uae_s32)src;
1478: src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1479: sign = (src1 ^ src2);
1480: if (src1 < 0) src1 = -src1;
1481: if (src2 < 0) src2 = -src2;
1482: mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1483: if (sign & 0x80000000) {
1484: dst_hi = ~dst_hi;
1485: dst_lo = -dst_lo;
1486: if (dst_lo == 0) dst_hi++;
1487: }
1488: SET_VFLG (0);
1489: SET_CFLG (0);
1490: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1491: SET_NFLG (((uae_s32)dst_hi) < 0);
1492: if (extra & 0x400)
1493: m68k_dreg(regs, extra & 7) = dst_hi;
1494: else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1495: && ((dst_hi & 0xffffffff) != 0xffffffff
1496: || (dst_lo & 0x80000000) != 0x80000000))
1497: {
1498: SET_VFLG (1);
1499: }
1500: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1501: } else {
1502: /* unsigned */
1503: uae_u32 dst_lo,dst_hi;
1504:
1505: mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1506:
1507: SET_VFLG (0);
1508: SET_CFLG (0);
1509: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1510: SET_NFLG (((uae_s32)dst_hi) < 0);
1511: if (extra & 0x400)
1512: m68k_dreg(regs, extra & 7) = dst_hi;
1513: else if (dst_hi != 0) {
1514: SET_VFLG (1);
1515: }
1516: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1517: }
1518: #endif
1519: }
1.1.1.6 root 1520:
1.1 root 1521:
1522: void m68k_reset (void)
1523: {
1524: regs.s = 1;
1525: regs.m = 0;
1526: regs.stopped = 0;
1527: regs.t1 = 0;
1528: regs.t0 = 0;
1529: SET_ZFLG (0);
1530: SET_XFLG (0);
1531: SET_CFLG (0);
1532: SET_VFLG (0);
1533: SET_NFLG (0);
1.1.1.16 root 1534: regs.spcflags &= ( SPCFLAG_MODE_CHANGE | SPCFLAG_DEBUGGER ); /* Clear specialflags except mode-change and debugger */
1.1 root 1535: regs.intmask = 7;
1536: regs.vbr = regs.sfc = regs.dfc = 0;
1537: regs.fpcr = regs.fpsr = regs.fpiar = 0;
1.1.1.7 root 1538:
1539: m68k_areg(regs, 7) = get_long(0);
1540: m68k_setpc(get_long(4));
1541: refill_prefetch (m68k_getpc(), 0);
1.1 root 1542: }
1543:
1.1.1.8 root 1544:
1.1 root 1545: unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1546: {
1.1.1.8 root 1547: #if 0
1.1 root 1548: uaecptr pc = m68k_getpc ();
1.1.1.8 root 1549: #endif
1.1.1.6 root 1550: if ((opcode & 0xF000) == 0xF000) {
1.1.1.16 root 1551: Exception(0xB,0,M68000_EXC_SRC_CPU);
1.1 root 1552: return 4;
1.1.1.6 root 1553: }
1554: if ((opcode & 0xF000) == 0xA000) {
1.1.1.16 root 1555: Exception(0xA,0,M68000_EXC_SRC_CPU);
1.1 root 1556: return 4;
1.1.1.6 root 1557: }
1.1.1.3 root 1558: #if 0
1.1.1.6 root 1559: write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc);
1.1 root 1560: #endif
1.1.1.16 root 1561: Exception (4,0,M68000_EXC_SRC_CPU);
1.1 root 1562: return 4;
1563: }
1564:
1.1.1.8 root 1565:
1.1 root 1566: void mmu_op(uae_u32 opcode, uae_u16 extra)
1567: {
1568: if ((opcode & 0xFE0) == 0x0500) {
1569: /* PFLUSH */
1570: mmusr = 0;
1571: write_log ("PFLUSH\n");
1572: } else if ((opcode & 0x0FD8) == 0x548) {
1573: /* PTEST */
1574: write_log ("PTEST\n");
1575: } else
1576: op_illg (opcode);
1577: }
1578:
1579:
1580: static uaecptr last_trace_ad = 0;
1581:
1582: static void do_trace (void)
1583: {
1.1.1.12 root 1584: if (regs.t0 && currprefs.cpu_level >= 2) {
1.1 root 1585: uae_u16 opcode;
1586: /* should also include TRAP, CHK, SR modification FPcc */
1587: /* probably never used so why bother */
1588: /* We can afford this to be inefficient... */
1589: m68k_setpc (m68k_getpc ());
1590: fill_prefetch_0 ();
1591: opcode = get_word (regs.pc);
1.1.1.19 root 1592: if (opcode == 0x4e73 /* RTE */
1.1 root 1593: || opcode == 0x4e74 /* RTD */
1594: || opcode == 0x4e75 /* RTS */
1595: || opcode == 0x4e77 /* RTR */
1596: || opcode == 0x4e76 /* TRAPV */
1597: || (opcode & 0xffc0) == 0x4e80 /* JSR */
1598: || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1599: || (opcode & 0xff00) == 0x6100 /* BSR */
1600: || ((opcode & 0xf000) == 0x6000 /* Bcc */
1601: && cctrue((opcode >> 8) & 0xf))
1602: || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1603: && !cctrue((opcode >> 8) & 0xf)
1604: && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1605: {
1606: last_trace_ad = m68k_getpc ();
1607: unset_special (SPCFLAG_TRACE);
1608: set_special (SPCFLAG_DOTRACE);
1609: }
1610: } else if (regs.t1) {
1611: last_trace_ad = m68k_getpc ();
1612: unset_special (SPCFLAG_TRACE);
1613: set_special (SPCFLAG_DOTRACE);
1614: }
1615: }
1616:
1617:
1.1.1.8 root 1618: /*
1619: * Handle special flags
1620: */
1.1.1.14 root 1621:
1622: static bool do_specialties_interrupt (int Pending)
1623: {
1.1.1.19 root 1624: #if ENABLE_DSP_EMU
1625: /* Check for DSP int first (if enabled) (level 6) */
1626: if (regs.spcflags & SPCFLAG_DSP) {
1627: if (DSP_ProcessIRQ() == true)
1628: return true;
1629: }
1630: #endif
1631:
1632: /* Check for MFP ints (level 6) */
1.1.1.14 root 1633: if (regs.spcflags & SPCFLAG_MFP) {
1.1.1.19 root 1634: if (MFP_ProcessIRQ() == true)
1.1.1.15 root 1635: return true; /* MFP exception was generated, no higher interrupt can happen */
1.1.1.14 root 1636: }
1637:
1638: /* No MFP int, check for VBL/HBL ints (levels 4/2) */
1639: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1640: int intr = intlev ();
1641: /* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */
1642: // unset_special (SPCFLAG_DOINT);
1643: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1644: if (intr != -1 && intr > regs.intmask) {
1645: Interrupt (intr , Pending); /* process the interrupt and add pending jitter if necessary */
1.1.1.15 root 1646: return true;
1.1.1.14 root 1647: }
1648: }
1649:
1.1.1.15 root 1650: return false; /* no interrupt was found */
1.1.1.14 root 1651: }
1652:
1653:
1.1 root 1654: static int do_specialties (void)
1655: {
1.1.1.7 root 1656: if(regs.spcflags & SPCFLAG_BUSERROR) {
1657: /* We can not execute bus errors directly in the memory handler
1658: * functions since the PC should point to the address of the next
1659: * instruction, so we're executing the bus errors here: */
1.1.1.8 root 1660: unset_special(SPCFLAG_BUSERROR);
1.1.1.16 root 1661: Exception(2,0,M68000_EXC_SRC_CPU);
1.1.1.7 root 1662: }
1663:
1.1.1.8 root 1664: if(regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1665: /* Add some extra cycles to simulate a wait state */
1666: unset_special(SPCFLAG_EXTRA_CYCLES);
1.1.1.11 root 1667: M68000_AddCycles(nWaitStateCycles);
1.1.1.12 root 1668: nWaitStateCycles = 0;
1.1.1.8 root 1669: }
1670:
1.1 root 1671: if (regs.spcflags & SPCFLAG_DOTRACE) {
1.1.1.16 root 1672: Exception (9,last_trace_ad,M68000_EXC_SRC_CPU);
1.1 root 1673: }
1.1.1.8 root 1674:
1.1.1.14 root 1675:
1676: /* Handle the STOP instruction */
1677: if ( regs.spcflags & SPCFLAG_STOP ) {
1.1.1.19 root 1678: //fprintf ( stderr , "test stop %d\n" , nCyclesMainCounter );
1.1.1.14 root 1679: /* We first test if there's a pending interrupt that would */
1.1.1.19 root 1680: /* allow to immediately leave the STOP state */
1.1.1.15 root 1681: if ( do_specialties_interrupt(true) ) { /* test if there's an interrupt and add pending jitter */
1.1.1.14 root 1682: regs.stopped = 0;
1683: unset_special (SPCFLAG_STOP);
1.1.1.19 root 1684: //fprintf ( stderr , "exit stop %d\n" , nCyclesMainCounter );
1.1.1.14 root 1685: }
1686:
1687: /* No pending int, we have to wait for the next matching int */
1688: while (regs.spcflags & SPCFLAG_STOP) {
1689:
1690: /* Take care of quit event if needed */
1691: if (regs.spcflags & SPCFLAG_BRK)
1692: return 1;
1693:
1694: M68000_AddCycles(4);
1695:
1696: /* It is possible one or more ints happen at the same time */
1.1.1.19 root 1697: /* We must process them during the same cpu cycle then choose the highest priority one */
1698: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
1.1.1.14 root 1699: CALL_VAR(PendingInterruptFunction);
1.1.1.19 root 1700: if ( MFP_UpdateNeeded == true )
1701: MFP_UpdateIRQ ( 0 );
1702:
1703: /* Check is there's an interrupt to process (could be a delayed MFP interrupt) */
1704: if ( do_specialties_interrupt(false) ) { /* test if there's an interrupt and add non pending jitter */
1705: regs.stopped = 0;
1706: unset_special (SPCFLAG_STOP);
1.1.1.6 root 1707: }
1.1 root 1708: }
1709: }
1.1.1.8 root 1710:
1.1.1.14 root 1711:
1.1 root 1712: if (regs.spcflags & SPCFLAG_TRACE)
1713: do_trace ();
1714:
1.1.1.12 root 1715: // if (regs.spcflags & SPCFLAG_DOINT) {
1716: /* [NP] pending int should be processed now, not after the current instr */
1.1.1.14 root 1717: /* so we check for (SPCFLAG_INT | SPCFLAG_DOINT), not just for SPCFLAG_DOINT */
1.1.1.15 root 1718:
1719: if ( do_specialties_interrupt(false) ) { /* test if there's an interrupt and add non pending jitter */
1.1.1.14 root 1720: regs.stopped = 0; /* [NP] useless ? */
1721: }
1722: if (regs.spcflags & SPCFLAG_INT) {
1723: unset_special (SPCFLAG_INT);
1724: set_special (SPCFLAG_DOINT);
1725: }
1.1.1.8 root 1726:
1.1.1.15 root 1727: if (regs.spcflags & SPCFLAG_DEBUGGER)
1.1.1.16 root 1728: DebugCpu_Check();
1.1.1.15 root 1729:
1.1 root 1730: if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1.1.1.8 root 1731: unset_special(SPCFLAG_MODE_CHANGE);
1.1 root 1732: return 1;
1733: }
1.1.1.8 root 1734:
1.1 root 1735: return 0;
1736: }
1737:
1.1.1.3 root 1738:
1.1 root 1739: /* It's really sad to have two almost identical functions for this, but we
1740: do it all for performance... :( */
1741: static void m68k_run_1 (void)
1742: {
1743: #ifdef DEBUG_PREFETCH
1744: uae_u8 saved_bytes[20];
1.1.1.20 root 1745: uae_u8 *oldpcp;
1.1 root 1746: #endif
1.1.1.8 root 1747:
1748: for (;;) {
1.1 root 1749: int cycles;
1.1.1.20 root 1750: //fprintf (stderr, "ir in %x %x\n",do_get_mem_long(®s.prefetch) , regs.prefetch_pc);
1.1.1.21! root 1751: regs.opcode = get_iword_prefetch (0);
! 1752:
! 1753: if (regs.spcflags & SPCFLAG_BUSERROR)
! 1754: {
! 1755: unset_special(SPCFLAG_BUSERROR);
! 1756: Exception(2,0,M68000_EXC_SRC_CPU);
! 1757:
! 1758: /* Get opcode for bus error handler and check other special bits */
! 1759: regs.opcode = get_iword_prefetch (0);
! 1760: if (regs.spcflags) {
! 1761: if (do_specialties ())
! 1762: return;
! 1763: }
! 1764: }
1.1.1.8 root 1765:
1.1 root 1766: #ifdef DEBUG_PREFETCH
1.1.1.20 root 1767: // if (get_ilong (0) != do_get_mem_long (®s.prefetch)) {
1768: // fprintf (stderr, "Prefetch differs from memory.\n");
1769: // debugging = 1;
1770: // return;
1771: // }
1.1 root 1772: oldpcp = regs.pc_p;
1773: memcpy (saved_bytes, regs.pc_p, 20);
1774: #endif
1775:
1776: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.15 root 1777: if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
1778: {
1779: int FrameCycles, HblCounterVideo, LineCycles;
1780:
1781: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
1782:
1783: LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
1.1.1.19 root 1784: Disasm(stderr, m68k_getpc (), NULL, 1);
1.1.1.15 root 1785: }
1.1 root 1786:
1787: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1788: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1789: #if COUNT_INSTRS == 2
1.1.1.21! root 1790: if (table68k[regs.opcode].handler != -1)
! 1791: instrcount[table68k[regs.opcode].handler]++;
1.1 root 1792: #elif COUNT_INSTRS == 1
1.1.1.21! root 1793: instrcount[regs.opcode]++;
1.1 root 1794: #endif
1.1.1.2 root 1795:
1.1.1.12 root 1796: /* In case of a Bus Error, we need the PC of the instruction that caused */
1797: /* the error to build the exception stack frame */
1.1.1.21! root 1798: regs.instruction_pc = m68k_getpc();
1.1.1.12 root 1799:
1.1.1.18 root 1800: if (bDspEnabled)
1801: Cycles_SetCounter(CYCLES_COUNTER_CPU, 0); /* to measure the total number of cycles spent in the cpu */
1802:
1.1.1.20 root 1803: /* Uncomment following lines to call capslib's debugger after each instruction */
1804: //if ( CAPSGetDebugRequest() )
1805: // DebugUI(REASON_CPU_BREAKPOINT);
1806:
1.1.1.21! root 1807: cycles = (*cpufunctbl[regs.opcode])(regs.opcode);
1.1.1.20 root 1808: //fprintf (stderr, "ir out %x %x\n",do_get_mem_long(®s.prefetch) , regs.prefetch_pc);
1.1.1.6 root 1809:
1.1 root 1810: #ifdef DEBUG_PREFETCH
1811: if (memcmp (saved_bytes, oldpcp, 20) != 0) {
1.1.1.12 root 1812: fprintf (stderr, "Self-modifying code detected %x.\n" , m68k_getpc() );
1.1.1.20 root 1813: // set_special (SPCFLAG_BRK);
1814: // debugging = 1;
1.1 root 1815: }
1816: #endif
1.1.1.2 root 1817:
1.1.1.12 root 1818: M68000_AddCyclesWithPairing(cycles);
1.1.1.13 root 1819: if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1820: /* Add some extra cycles to simulate a wait state */
1821: unset_special(SPCFLAG_EXTRA_CYCLES);
1822: M68000_AddCycles(nWaitStateCycles);
1823: nWaitStateCycles = 0;
1824: }
1825:
1.1.1.14 root 1826: /* We can have several interrupts at the same time before the next CPU instruction */
1827: /* We must check for pending interrupt and call do_specialties_interrupt() only */
1828: /* if the cpu is not in the STOP state. Else, the int could be acknowledged now */
1829: /* and prevent exiting the STOP state when calling do_specialties() after. */
1830: /* For performance, we first test PendingInterruptCount, then regs.spcflags */
1.1.1.19 root 1831: if ( PendingInterruptCount <= 0 )
1832: {
1833: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) && ( ( regs.spcflags & SPCFLAG_STOP ) == 0 ) )
1834: CALL_VAR ( PendingInterruptFunction ); /* call the interrupt's handler */
1835: if ( MFP_UpdateNeeded == true )
1836: MFP_UpdateIRQ ( 0 ); /* update MFP's state if some internal timers related to MFP expired */
1837: }
1.1.1.14 root 1838:
1839: if (regs.spcflags) {
1840: if (do_specialties ())
1841: return;
1842: }
1843:
1.1.1.15 root 1844: /* Run DSP 56k code if necessary */
1845: if (bDspEnabled) {
1.1.1.18 root 1846: DSP_Run( Cycles_GetCounter(CYCLES_COUNTER_CPU) * 2);
1.1.1.15 root 1847: }
1.1 root 1848: }
1849: }
1850:
1851:
1852: /* Same thing, but don't use prefetch to get opcode. */
1853: static void m68k_run_2 (void)
1854: {
1.1.1.8 root 1855: for (;;) {
1.1 root 1856: int cycles;
1.1.1.21! root 1857:
! 1858: regs.opcode = get_iword (0);
1.1 root 1859:
1860: /*m68k_dumpstate(stderr, NULL);*/
1.1.1.15 root 1861: if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
1862: {
1863: int FrameCycles, HblCounterVideo, LineCycles;
1864:
1865: Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
1866:
1867: LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
1.1.1.19 root 1868: Disasm(stderr, m68k_getpc (), NULL, 1);
1.1.1.15 root 1869: }
1.1.1.12 root 1870:
1.1 root 1871: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1872: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1873: #if COUNT_INSTRS == 2
1.1.1.21! root 1874: if (table68k[regs.opcode].handler != -1)
! 1875: instrcount[table68k[regs.opcode].handler]++;
1.1 root 1876: #elif COUNT_INSTRS == 1
1.1.1.21! root 1877: instrcount[regs.opcode]++;
1.1 root 1878: #endif
1.1.1.2 root 1879:
1.1.1.17 root 1880: /* In case of a Bus Error, we need the PC of the instruction that caused */
1881: /* the error to build the exception stack frame */
1.1.1.21! root 1882: regs.instruction_pc = m68k_getpc();
1.1.1.17 root 1883:
1.1.1.21! root 1884: cycles = (*cpufunctbl[regs.opcode])(regs.opcode);
1.1.1.6 root 1885:
1.1.1.16 root 1886: if (bDspEnabled)
1887: Cycles_SetCounter(CYCLES_COUNTER_CPU, 0); /* to measure the total number of cycles spent in the cpu */
1888:
1.1.1.8 root 1889: M68000_AddCycles(cycles);
1.1.1.13 root 1890: if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
1891: /* Add some extra cycles to simulate a wait state */
1892: unset_special(SPCFLAG_EXTRA_CYCLES);
1893: M68000_AddCycles(nWaitStateCycles);
1894: nWaitStateCycles = 0;
1895: }
1896:
1.1.1.19 root 1897: if ( PendingInterruptCount <= 0 )
1898: {
1899: while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
1900: CALL_VAR(PendingInterruptFunction);
1901: if ( MFP_UpdateNeeded == true )
1902: MFP_UpdateIRQ ( 0 );
1903: }
1.1.1.8 root 1904:
1.1 root 1905: if (regs.spcflags) {
1906: if (do_specialties ())
1907: return;
1908: }
1.1.1.15 root 1909:
1910: /* Run DSP 56k code if necessary */
1911: if (bDspEnabled) {
1.1.1.16 root 1912: DSP_Run( Cycles_GetCounter(CYCLES_COUNTER_CPU) );
1.1.1.15 root 1913: }
1.1 root 1914: }
1915: }
1916:
1917:
1918: void m68k_go (int may_quit)
1919: {
1.1.1.8 root 1920: static int in_m68k_go = 0;
1921:
1.1 root 1922: if (in_m68k_go || !may_quit) {
1923: write_log ("Bug! m68k_go is not reentrant.\n");
1924: abort ();
1925: }
1926:
1927: in_m68k_go++;
1.1.1.8 root 1928: while (!(regs.spcflags & SPCFLAG_BRK)) {
1.1.1.12 root 1929: if(currprefs.cpu_compatible)
1.1.1.2 root 1930: m68k_run_1();
1931: else
1932: m68k_run_2();
1.1 root 1933: }
1.1.1.8 root 1934: unset_special(SPCFLAG_BRK);
1.1 root 1935: in_m68k_go--;
1936: }
1937:
1.1.1.8 root 1938:
1939: /*
1.1 root 1940: static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1941: {
1942: uae_u32 opcode, val;
1943: struct instr *dp;
1944:
1945: opcode = get_iword_1(0);
1946: last_op_for_exception_3 = opcode;
1947: m68kpc_offset = 2;
1948:
1.1.1.6 root 1949: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1950: opcode = 0x4AFC;
1951: }
1952: dp = table68k + opcode;
1953:
1954: if (dp->suse) {
1955: if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) {
1.1.1.16 root 1956: Exception (3, 0,M68000_EXC_SRC_CPU);
1.1 root 1957: return;
1958: }
1959: }
1960: if (dp->duse) {
1961: if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) {
1.1.1.16 root 1962: Exception (3, 0,M68000_EXC_SRC_CPU);
1.1 root 1963: return;
1964: }
1965: }
1966: }
1.1.1.8 root 1967: */
1968:
1.1 root 1969:
1970: void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1971: {
1.1.1.11 root 1972: static const char * const ccnames[] =
1.1.1.8 root 1973: { "T ","F ","HI","LS","CC","CS","NE","EQ",
1974: "VC","VS","PL","MI","GE","LT","GT","LE" };
1975:
1.1 root 1976: uaecptr newpc = 0;
1977: m68kpc_offset = addr - m68k_getpc ();
1978: while (cnt-- > 0) {
1979: char instrname[20],*ccpt;
1980: int opwords;
1981: uae_u32 opcode;
1.1.1.11 root 1982: const struct mnemolookup *lookup;
1.1 root 1983: struct instr *dp;
1984: fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset);
1985: for (opwords = 0; opwords < 5; opwords++){
1.1.1.21! root 1986: if ( valid_address ( m68k_getpc () + m68kpc_offset + opwords*2 , 2 ) )
! 1987: fprintf (f, "%04x ", get_iword_1 (m68kpc_offset + opwords*2));
! 1988: else
! 1989: fprintf (f, "**** " );
1.1 root 1990: }
1.1.1.21! root 1991: if ( ! valid_address ( m68k_getpc () + m68kpc_offset , 2 ) ) {
! 1992: fprintf (f , "BUS ERROR\n" ); /* If region is not valid (bus error region) */
! 1993: m68kpc_offset += 2;
! 1994: continue;
! 1995: }
! 1996:
1.1 root 1997: opcode = get_iword_1 (m68kpc_offset);
1998: m68kpc_offset += 2;
1.1.1.6 root 1999: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 2000: opcode = 0x4AFC;
2001: }
2002: dp = table68k + opcode;
2003: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
2004: ;
2005:
2006: strcpy (instrname, lookup->name);
2007: ccpt = strstr (instrname, "cc");
2008: if (ccpt != 0) {
2009: strncpy (ccpt, ccnames[dp->cc], 2);
2010: }
2011: fprintf (f, "%s", instrname);
2012: switch (dp->size){
2013: case sz_byte: fprintf (f, ".B "); break;
2014: case sz_word: fprintf (f, ".W "); break;
2015: case sz_long: fprintf (f, ".L "); break;
2016: default: fprintf (f, " "); break;
2017: }
2018:
2019: if (dp->suse) {
2020: newpc = m68k_getpc () + m68kpc_offset;
2021: newpc += ShowEA (f, dp->sreg, dp->smode, dp->size, 0);
2022: }
2023: if (dp->suse && dp->duse)
2024: fprintf (f, ",");
2025: if (dp->duse) {
2026: newpc = m68k_getpc () + m68kpc_offset;
2027: newpc += ShowEA (f, dp->dreg, dp->dmode, dp->size, 0);
2028: }
2029: if (ccpt != 0) {
2030: if (cctrue(dp->cc))
1.1.1.5 root 2031: fprintf (f, " == %08lx (TRUE)", (long)newpc);
1.1 root 2032: else
1.1.1.5 root 2033: fprintf (f, " == %08lx (FALSE)", (long)newpc);
1.1 root 2034: } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1.1.1.5 root 2035: fprintf (f, " == %08lx", (long)newpc);
1.1 root 2036: fprintf (f, "\n");
2037: }
2038: if (nextpc)
2039: *nextpc = m68k_getpc () + m68kpc_offset;
2040: }
2041:
2042: void m68k_dumpstate (FILE *f, uaecptr *nextpc)
2043: {
2044: int i;
2045: for (i = 0; i < 8; i++){
1.1.1.5 root 2046: fprintf (f, "D%d: %08lx ", i, (long)m68k_dreg(regs, i));
1.1 root 2047: if ((i & 3) == 3) fprintf (f, "\n");
2048: }
2049: for (i = 0; i < 8; i++){
1.1.1.5 root 2050: fprintf (f, "A%d: %08lx ", i, (long)m68k_areg(regs, i));
1.1 root 2051: if ((i & 3) == 3) fprintf (f, "\n");
2052: }
2053: if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
2054: if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
2055: if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
2056: fprintf (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1.1.1.5 root 2057: (long)regs.usp,(long)regs.isp,(long)regs.msp,(long)regs.vbr);
1.1 root 2058: fprintf (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
2059: regs.t1, regs.t0, regs.s, regs.m,
2060: GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
2061: for (i = 0; i < 8; i++){
2062: fprintf (f, "FP%d: %g ", i, regs.fp[i]);
2063: if ((i & 3) == 3) fprintf (f, "\n");
2064: }
2065: fprintf (f, "N=%d Z=%d I=%d NAN=%d\n",
2066: (regs.fpsr & 0x8000000) != 0,
2067: (regs.fpsr & 0x4000000) != 0,
2068: (regs.fpsr & 0x2000000) != 0,
2069: (regs.fpsr & 0x1000000) != 0);
1.1.1.12 root 2070: if (currprefs.cpu_compatible)
1.1 root 2071: fprintf (f, "prefetch %08lx\n", (unsigned long)do_get_mem_long(®s.prefetch));
2072:
2073: m68k_disasm (f, m68k_getpc (), nextpc, 1);
2074: if (nextpc)
1.1.1.5 root 2075: fprintf (f, "next PC: %08lx\n", (long)*nextpc);
1.1 root 2076: }
1.1.1.12 root 2077:
2078:
2079: /*
2080:
2081: The routines below take dividend and divisor as parameters.
2082: They return 0 if division by zero, or exact number of cycles otherwise.
2083:
2084: The number of cycles returned assumes a register operand.
2085: Effective address time must be added if memory operand.
2086:
2087: For 68000 only (not 68010, 68012, 68020, etc).
2088: Probably valid for 68008 after adding the extra prefetch cycle.
2089:
2090:
2091: Best and worst cases are for register operand:
2092: (Note the difference with the documented range.)
2093:
2094:
2095: DIVU:
2096:
2097: Overflow (always): 10 cycles.
2098: Worst case: 136 cycles.
2099: Best case: 76 cycles.
2100:
2101:
2102: DIVS:
2103:
2104: Absolute overflow: 16-18 cycles.
2105: Signed overflow is not detected prematurely.
2106:
2107: Worst case: 156 cycles.
2108: Best case without signed overflow: 122 cycles.
2109: Best case with signed overflow: 120 cycles
2110:
2111:
2112: */
2113:
2114:
2115: //
2116: // DIVU
2117: // Unsigned division
2118: //
2119:
2120: STATIC_INLINE int getDivu68kCycles_2 (uae_u32 dividend, uae_u16 divisor)
2121: {
2122: int mcycles;
2123: uae_u32 hdivisor;
2124: int i;
2125:
2126: if (divisor == 0)
2127: return 0;
2128:
2129: // Overflow
2130: if ((dividend >> 16) >= divisor)
2131: return (mcycles = 5) * 2;
2132:
2133: mcycles = 38;
2134: hdivisor = divisor << 16;
2135:
2136: for (i = 0; i < 15; i++) {
2137: uae_u32 temp;
2138: temp = dividend;
2139:
2140: dividend <<= 1;
2141:
2142: // If carry from shift
2143: if ((uae_s32)temp < 0)
2144: dividend -= hdivisor;
2145: else {
2146: mcycles += 2;
2147: if (dividend >= hdivisor) {
2148: dividend -= hdivisor;
2149: mcycles--;
2150: }
2151: }
2152: }
2153: return mcycles * 2;
2154: }
2155: int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor)
2156: {
2157: int v = getDivu68kCycles_2 (dividend, divisor) - 4;
2158: // write_log ("U%d ", v);
2159: return v;
2160: }
2161:
2162: //
2163: // DIVS
2164: // Signed division
2165: //
2166:
2167: STATIC_INLINE int getDivs68kCycles_2 (uae_s32 dividend, uae_s16 divisor)
2168: {
2169: int mcycles;
2170: uae_u32 aquot;
2171: int i;
2172:
2173: if (divisor == 0)
2174: return 0;
2175:
2176: mcycles = 6;
2177:
2178: if (dividend < 0)
2179: mcycles++;
2180:
2181: // Check for absolute overflow
2182: if (((uae_u32)abs (dividend) >> 16) >= (uae_u16)abs (divisor))
2183: return (mcycles + 2) * 2;
2184:
2185: // Absolute quotient
2186: aquot = (uae_u32) abs (dividend) / (uae_u16)abs (divisor);
2187:
2188: mcycles += 55;
2189:
2190: if (divisor >= 0) {
2191: if (dividend >= 0)
2192: mcycles--;
2193: else
2194: mcycles++;
2195: }
2196:
2197: // Count 15 msbits in absolute of quotient
2198:
2199: for (i = 0; i < 15; i++) {
2200: if ((uae_s16)aquot >= 0)
2201: mcycles++;
2202: aquot <<= 1;
2203: }
2204:
2205: return mcycles * 2;
2206: }
2207: int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor)
2208: {
2209: int v = getDivs68kCycles_2 (dividend, divisor) - 4;
2210: // write_log ("S%d ", v);
2211: return v;
2212: }
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